mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #11015 from SiliconLabs/fix/fpga_tests/adc
Fix wrongly declared ADC pinout for EFM32GG11 STK3701Apull/11053/head
commit
6ef5e228b5
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@ -29,41 +29,78 @@
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#if DEVICE_ANALOGIN
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#if DEVICE_ANALOGIN
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MBED_WEAK const PinMap PinMap_ADC[] = {
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MBED_WEAK const PinMap PinMap_ADC[] = {
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#if ADC0_BASE
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#if ADC0_BASE
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{PA0, ADC_0, adcPosSelAPORT3XCH8},
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{PA0, ADC_0, adcPosSelAPORT1XCH0},
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{PA1, ADC_0, adcPosSelAPORT4XCH9},
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{PA1, ADC_0, adcPosSelAPORT2XCH1},
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{PA2, ADC_0, adcPosSelAPORT3XCH10},
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{PA2, ADC_0, adcPosSelAPORT1XCH2},
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{PA3, ADC_0, adcPosSelAPORT4XCH11},
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{PA3, ADC_0, adcPosSelAPORT2XCH3},
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{PA4, ADC_0, adcPosSelAPORT3XCH12},
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{PA4, ADC_0, adcPosSelAPORT1XCH4},
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{PA5, ADC_0, adcPosSelAPORT4XCH13},
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{PA5, ADC_0, adcPosSelAPORT2XCH5},
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{PA6, ADC_0, adcPosSelAPORT1XCH6},
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{PA7, ADC_0, adcPosSelAPORT2XCH7},
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{PA8, ADC_0, adcPosSelAPORT1XCH8},
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{PA9, ADC_0, adcPosSelAPORT2XCH9},
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{PA10, ADC_0, adcPosSelAPORT1XCH10},
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{PA11, ADC_0, adcPosSelAPORT2XCH11},
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{PA12, ADC_0, adcPosSelAPORT1XCH12},
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{PA13, ADC_0, adcPosSelAPORT2XCH13},
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{PA14, ADC_0, adcPosSelAPORT1XCH14},
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{PA15, ADC_0, adcPosSelAPORT2XCH15},
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{PB11, ADC_0, adcPosSelAPORT4XCH27},
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{PB0, ADC_0, adcPosSelAPORT1XCH16},
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{PB12, ADC_0, adcPosSelAPORT3XCH28},
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{PB1, ADC_0, adcPosSelAPORT2XCH17},
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{PB14, ADC_0, adcPosSelAPORT3XCH30},
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{PB2, ADC_0, adcPosSelAPORT1XCH18},
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{PB15, ADC_0, adcPosSelAPORT4XCH31},
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{PB3, ADC_0, adcPosSelAPORT2XCH19},
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{PB4, ADC_0, adcPosSelAPORT1XCH20},
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{PB5, ADC_0, adcPosSelAPORT2XCH21},
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{PB6, ADC_0, adcPosSelAPORT1XCH22},
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{PC6, ADC_0, adcPosSelAPORT1XCH6},
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{PB9, ADC_0, adcPosSelAPORT2XCH25},
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{PC7, ADC_0, adcPosSelAPORT2XCH7},
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{PB10, ADC_0, adcPosSelAPORT1XCH26},
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{PC8, ADC_0, adcPosSelAPORT1XCH8},
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{PB11, ADC_0, adcPosSelAPORT2XCH27},
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{PC9, ADC_0, adcPosSelAPORT2XCH9},
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{PB12, ADC_0, adcPosSelAPORT1XCH28},
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{PC10, ADC_0, adcPosSelAPORT1XCH10},
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{PB14, ADC_0, adcPosSelAPORT1XCH30},
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{PC11, ADC_0, adcPosSelAPORT2XCH11},
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{PB15, ADC_0, adcPosSelAPORT2XCH31},
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{PD9, ADC_0, adcPosSelAPORT4XCH1},
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{PD0, ADC_0, adcPosSelAPORT0XCH0},
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{PD10, ADC_0, adcPosSelAPORT3XCH2},
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{PD1, ADC_0, adcPosSelAPORT0XCH1},
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{PD11, ADC_0, adcPosSelAPORT3YCH3},
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{PD2, ADC_0, adcPosSelAPORT0XCH2},
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{PD12, ADC_0, adcPosSelAPORT3XCH4},
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{PD3, ADC_0, adcPosSelAPORT0XCH3},
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{PD13, ADC_0, adcPosSelAPORT3YCH5},
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{PD4, ADC_0, adcPosSelAPORT0XCH4},
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{PD14, ADC_0, adcPosSelAPORT3XCH6},
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{PD5, ADC_0, adcPosSelAPORT0XCH5},
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{PD15, ADC_0, adcPosSelAPORT4XCH7},
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{PD6, ADC_0, adcPosSelAPORT0XCH6},
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{PD7, ADC_0, adcPosSelAPORT0XCH7},
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{PF0, ADC_0, adcPosSelAPORT1XCH16},
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{PE0, ADC_0, adcPosSelAPORT3XCH0},
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{PF1, ADC_0, adcPosSelAPORT2XCH17},
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{PE1, ADC_0, adcPosSelAPORT4XCH1},
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{PF2, ADC_0, adcPosSelAPORT1XCH18},
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{PE4, ADC_0, adcPosSelAPORT3XCH4},
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{PF3, ADC_0, adcPosSelAPORT2XCH19},
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{PE5, ADC_0, adcPosSelAPORT4XCH5},
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{PF4, ADC_0, adcPosSelAPORT1XCH20},
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{PE6, ADC_0, adcPosSelAPORT3XCH6},
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{PF5, ADC_0, adcPosSelAPORT2XCH21},
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{PE7, ADC_0, adcPosSelAPORT4XCH7},
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{PF6, ADC_0, adcPosSelAPORT1XCH22},
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{PE8, ADC_0, adcPosSelAPORT3XCH8},
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{PF7, ADC_0, adcPosSelAPORT2XCH23},
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{PE9, ADC_0, adcPosSelAPORT4XCH9},
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{PE10, ADC_0, adcPosSelAPORT3XCH10},
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{PE11, ADC_0, adcPosSelAPORT4XCH11},
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{PE12, ADC_0, adcPosSelAPORT3XCH12},
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{PE13, ADC_0, adcPosSelAPORT4XCH13},
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{PE14, ADC_0, adcPosSelAPORT3XCH14},
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{PE15, ADC_0, adcPosSelAPORT4XCH15},
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{PF0, ADC_0, adcPosSelAPORT3XCH16},
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{PF1, ADC_0, adcPosSelAPORT4XCH17},
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{PF2, ADC_0, adcPosSelAPORT3XCH18},
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{PF3, ADC_0, adcPosSelAPORT4XCH19},
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{PF4, ADC_0, adcPosSelAPORT3XCH20},
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{PF5, ADC_0, adcPosSelAPORT4XCH21},
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{PF6, ADC_0, adcPosSelAPORT3XCH22},
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{PF7, ADC_0, adcPosSelAPORT4XCH23},
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{PF8, ADC_0, adcPosSelAPORT3XCH24},
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{PF9, ADC_0, adcPosSelAPORT4XCH25},
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{PF10, ADC_0, adcPosSelAPORT3XCH26},
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{PF11, ADC_0, adcPosSelAPORT4XCH27},
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{PF12, ADC_0, adcPosSelAPORT3XCH28},
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{PF13, ADC_0, adcPosSelAPORT4XCH31},
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{PF14, ADC_0, adcPosSelAPORT3XCH30},
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{PF15, ADC_0, adcPosSelAPORT4XCH31},
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#endif
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#endif
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{NC , NC , NC}
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{NC , NC , NC}
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};
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};
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