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Merge pull request #11015 from SiliconLabs/fix/fpga_tests/adc 

Fix wrongly declared ADC pinout for EFM32GG11 STK3701A
pull/11053/head
Arto Kinnunen 2019-07-15 15:38:47 +03:00 committed by GitHub
parent aca726d59f 35851005ef
commit 6ef5e228b5
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1 changed files with 68 additions and 31 deletions
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99
targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/PeripheralPins.c
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@ -29,41 +29,78 @@
#if DEVICE_ANALOGIN
MBED_WEAK const PinMap PinMap_ADC[] = {
#if ADC0_BASE
{PA0, ADC_0, adcPosSelAPORT3XCH8},
{PA1, ADC_0, adcPosSelAPORT4XCH9},
{PA2, ADC_0, adcPosSelAPORT3XCH10},
{PA3, ADC_0, adcPosSelAPORT4XCH11},
{PA4, ADC_0, adcPosSelAPORT3XCH12},
{PA5, ADC_0, adcPosSelAPORT4XCH13},
{PA0, ADC_0, adcPosSelAPORT1XCH0},
{PA1, ADC_0, adcPosSelAPORT2XCH1},
{PA2, ADC_0, adcPosSelAPORT1XCH2},
{PA3, ADC_0, adcPosSelAPORT2XCH3},
{PA4, ADC_0, adcPosSelAPORT1XCH4},
{PA5, ADC_0, adcPosSelAPORT2XCH5},
{PA6, ADC_0, adcPosSelAPORT1XCH6},
{PA7, ADC_0, adcPosSelAPORT2XCH7},
{PA8, ADC_0, adcPosSelAPORT1XCH8},
{PA9, ADC_0, adcPosSelAPORT2XCH9},
{PA10, ADC_0, adcPosSelAPORT1XCH10},
{PA11, ADC_0, adcPosSelAPORT2XCH11},
{PA12, ADC_0, adcPosSelAPORT1XCH12},
{PA13, ADC_0, adcPosSelAPORT2XCH13},
{PA14, ADC_0, adcPosSelAPORT1XCH14},
{PA15, ADC_0, adcPosSelAPORT2XCH15},
{PB11, ADC_0, adcPosSelAPORT4XCH27},
{PB12, ADC_0, adcPosSelAPORT3XCH28},
{PB14, ADC_0, adcPosSelAPORT3XCH30},
{PB15, ADC_0, adcPosSelAPORT4XCH31},
{PB0, ADC_0, adcPosSelAPORT1XCH16},
{PB1, ADC_0, adcPosSelAPORT2XCH17},
{PB2, ADC_0, adcPosSelAPORT1XCH18},
{PB3, ADC_0, adcPosSelAPORT2XCH19},
{PB4, ADC_0, adcPosSelAPORT1XCH20},
{PB5, ADC_0, adcPosSelAPORT2XCH21},
{PB6, ADC_0, adcPosSelAPORT1XCH22},
{PC6, ADC_0, adcPosSelAPORT1XCH6},
{PC7, ADC_0, adcPosSelAPORT2XCH7},
{PC8, ADC_0, adcPosSelAPORT1XCH8},
{PC9, ADC_0, adcPosSelAPORT2XCH9},
{PC10, ADC_0, adcPosSelAPORT1XCH10},
{PC11, ADC_0, adcPosSelAPORT2XCH11},
{PB9, ADC_0, adcPosSelAPORT2XCH25},
{PB10, ADC_0, adcPosSelAPORT1XCH26},
{PB11, ADC_0, adcPosSelAPORT2XCH27},
{PB12, ADC_0, adcPosSelAPORT1XCH28},
{PB14, ADC_0, adcPosSelAPORT1XCH30},
{PB15, ADC_0, adcPosSelAPORT2XCH31},
{PD9, ADC_0, adcPosSelAPORT4XCH1},
{PD10, ADC_0, adcPosSelAPORT3XCH2},
{PD11, ADC_0, adcPosSelAPORT3YCH3},
{PD12, ADC_0, adcPosSelAPORT3XCH4},
{PD13, ADC_0, adcPosSelAPORT3YCH5},
{PD14, ADC_0, adcPosSelAPORT3XCH6},
{PD15, ADC_0, adcPosSelAPORT4XCH7},
{PD0, ADC_0, adcPosSelAPORT0XCH0},
{PD1, ADC_0, adcPosSelAPORT0XCH1},
{PD2, ADC_0, adcPosSelAPORT0XCH2},
{PD3, ADC_0, adcPosSelAPORT0XCH3},
{PD4, ADC_0, adcPosSelAPORT0XCH4},
{PD5, ADC_0, adcPosSelAPORT0XCH5},
{PD6, ADC_0, adcPosSelAPORT0XCH6},
{PD7, ADC_0, adcPosSelAPORT0XCH7},
{PF0, ADC_0, adcPosSelAPORT1XCH16},
{PF1, ADC_0, adcPosSelAPORT2XCH17},
{PF2, ADC_0, adcPosSelAPORT1XCH18},
{PF3, ADC_0, adcPosSelAPORT2XCH19},
{PF4, ADC_0, adcPosSelAPORT1XCH20},
{PF5, ADC_0, adcPosSelAPORT2XCH21},
{PF6, ADC_0, adcPosSelAPORT1XCH22},
{PF7, ADC_0, adcPosSelAPORT2XCH23},
{PE0, ADC_0, adcPosSelAPORT3XCH0},
{PE1, ADC_0, adcPosSelAPORT4XCH1},
{PE4, ADC_0, adcPosSelAPORT3XCH4},
{PE5, ADC_0, adcPosSelAPORT4XCH5},
{PE6, ADC_0, adcPosSelAPORT3XCH6},
{PE7, ADC_0, adcPosSelAPORT4XCH7},
{PE8, ADC_0, adcPosSelAPORT3XCH8},
{PE9, ADC_0, adcPosSelAPORT4XCH9},
{PE10, ADC_0, adcPosSelAPORT3XCH10},
{PE11, ADC_0, adcPosSelAPORT4XCH11},
{PE12, ADC_0, adcPosSelAPORT3XCH12},
{PE13, ADC_0, adcPosSelAPORT4XCH13},
{PE14, ADC_0, adcPosSelAPORT3XCH14},
{PE15, ADC_0, adcPosSelAPORT4XCH15},
{PF0, ADC_0, adcPosSelAPORT3XCH16},
{PF1, ADC_0, adcPosSelAPORT4XCH17},
{PF2, ADC_0, adcPosSelAPORT3XCH18},
{PF3, ADC_0, adcPosSelAPORT4XCH19},
{PF4, ADC_0, adcPosSelAPORT3XCH20},
{PF5, ADC_0, adcPosSelAPORT4XCH21},
{PF6, ADC_0, adcPosSelAPORT3XCH22},
{PF7, ADC_0, adcPosSelAPORT4XCH23},
{PF8, ADC_0, adcPosSelAPORT3XCH24},
{PF9, ADC_0, adcPosSelAPORT4XCH25},
{PF10, ADC_0, adcPosSelAPORT3XCH26},
{PF11, ADC_0, adcPosSelAPORT4XCH27},
{PF12, ADC_0, adcPosSelAPORT3XCH28},
{PF13, ADC_0, adcPosSelAPORT4XCH31},
{PF14, ADC_0, adcPosSelAPORT3XCH30},
{PF15, ADC_0, adcPosSelAPORT4XCH31},
#endif
{NC , NC , NC}
};