diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/stm32l053xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/stm32l053xx.h index 88d4d061a8..30fd888e28 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/stm32l053xx.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/stm32l053xx.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l053xx.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for stm32l053xx devices. @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -634,66 +634,70 @@ typedef struct #define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */ #define DATA_EEPROM_END ((uint32_t)0x080807FFU) /*!< DATA EEPROM end address in the alias region */ #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */ +#define SRAM_SIZE_MAX ((uint32_t)0x00002000U) /*!< maximum SRAM size (up to 8KBytes) */ + #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */ /*!< Peripheral memory map */ #define APBPERIPH_BASE PERIPH_BASE -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) -#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) +#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000U) -#define TIM2_BASE (APBPERIPH_BASE + 0x00000000) -#define TIM6_BASE (APBPERIPH_BASE + 0x00001000) -#define LCD_BASE (APBPERIPH_BASE + 0x00002400) -#define RTC_BASE (APBPERIPH_BASE + 0x00002800) -#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00) -#define IWDG_BASE (APBPERIPH_BASE + 0x00003000) -#define SPI2_BASE (APBPERIPH_BASE + 0x00003800) -#define USART2_BASE (APBPERIPH_BASE + 0x00004400) -#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800) -#define I2C1_BASE (APBPERIPH_BASE + 0x00005400) -#define I2C2_BASE (APBPERIPH_BASE + 0x00005800) -#define CRS_BASE (APBPERIPH_BASE + 0x00006C00) -#define PWR_BASE (APBPERIPH_BASE + 0x00007000) -#define DAC_BASE (APBPERIPH_BASE + 0x00007400) -#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00) +#define TIM2_BASE (APBPERIPH_BASE + 0x00000000U) +#define TIM6_BASE (APBPERIPH_BASE + 0x00001000U) +#define LCD_BASE (APBPERIPH_BASE + 0x00002400U) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800U) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00U) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000U) +#define SPI2_BASE (APBPERIPH_BASE + 0x00003800U) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400U) +#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800U) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400U) +#define I2C2_BASE (APBPERIPH_BASE + 0x00005800U) +#define CRS_BASE (APBPERIPH_BASE + 0x00006C00U) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000U) +#define DAC_BASE (APBPERIPH_BASE + 0x00007400U) +#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00U) -#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000) -#define COMP1_BASE (APBPERIPH_BASE + 0x00010018) -#define COMP2_BASE (APBPERIPH_BASE + 0x0001001C) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000U) +#define COMP1_BASE (APBPERIPH_BASE + 0x00010018U) +#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CU) #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE) -#define EXTI_BASE (APBPERIPH_BASE + 0x00010400) -#define TIM21_BASE (APBPERIPH_BASE + 0x00010800) -#define TIM22_BASE (APBPERIPH_BASE + 0x00011400) -#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00) -#define ADC1_BASE (APBPERIPH_BASE + 0x00012400) -#define ADC_BASE (APBPERIPH_BASE + 0x00012708) -#define SPI1_BASE (APBPERIPH_BASE + 0x00013000) -#define USART1_BASE (APBPERIPH_BASE + 0x00013800) -#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800) +#define EXTI_BASE (APBPERIPH_BASE + 0x00010400U) +#define TIM21_BASE (APBPERIPH_BASE + 0x00010800U) +#define TIM22_BASE (APBPERIPH_BASE + 0x00011400U) +#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00U) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400U) +#define ADC_BASE (APBPERIPH_BASE + 0x00012708U) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000U) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800U) +#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800U) -#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080) -#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8) +#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8U) -#define RCC_BASE (AHBPERIPH_BASE + 0x00001000) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */ +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */ #define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */ -#define CRC_BASE (AHBPERIPH_BASE + 0x00003000) -#define TSC_BASE (AHBPERIPH_BASE + 0x00004000) -#define RNG_BASE (AHBPERIPH_BASE + 0x00005000) +#define FLASHSIZE_BASE ((uint32_t)0x1FF8007CU) /*!< FLASH Size register base address */ +#define UID_BASE ((uint32_t)0x1FF80050U) /*!< Unique device ID register base address */ +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) +#define TSC_BASE (AHBPERIPH_BASE + 0x00004000U) +#define RNG_BASE (AHBPERIPH_BASE + 0x00005000U) -#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000) -#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400) -#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800) -#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00) -#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00) +#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000U) +#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400U) +#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800U) +#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00U) +#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00U) /** * @} @@ -782,91 +786,173 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for ADC_ISR register ******************/ -#define ADC_ISR_EOCAL ((uint32_t)0x00000800U) /*!< End of calibration flag */ -#define ADC_ISR_AWD ((uint32_t)0x00000080U) /*!< Analog watchdog flag */ -#define ADC_ISR_OVR ((uint32_t)0x00000010U) /*!< Overrun flag */ -#define ADC_ISR_EOSEQ ((uint32_t)0x00000008U) /*!< End of Sequence flag */ -#define ADC_ISR_EOC ((uint32_t)0x00000004U) /*!< End of Conversion */ -#define ADC_ISR_EOSMP ((uint32_t)0x00000002U) /*!< End of sampling flag */ -#define ADC_ISR_ADRDY ((uint32_t)0x00000001U) /*!< ADC Ready */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1U << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */ +#define ADC_ISR_AWD_Pos (7U) +#define ADC_ISR_AWD_Msk (0x1U << ADC_ISR_AWD_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */ +#define ADC_ISR_EOSEQ_Pos (3U) +#define ADC_ISR_EOSEQ_Msk (0x1U << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */ /* Old EOSEQ bit definition, maintained for legacy purpose */ #define ADC_ISR_EOS ADC_ISR_EOSEQ /******************** Bits definition for ADC_IER register ******************/ -#define ADC_IER_EOCALIE ((uint32_t)0x00000800U) /*!< Enf Of Calibration interrupt enable */ -#define ADC_IER_AWDIE ((uint32_t)0x00000080U) /*!< Analog Watchdog interrupt enable */ -#define ADC_IER_OVRIE ((uint32_t)0x00000010U) /*!< Overrun interrupt enable */ -#define ADC_IER_EOSEQIE ((uint32_t)0x00000008U) /*!< End of Sequence of conversion interrupt enable */ -#define ADC_IER_EOCIE ((uint32_t)0x00000004U) /*!< End of Conversion interrupt enable */ -#define ADC_IER_EOSMPIE ((uint32_t)0x00000002U) /*!< End of sampling interrupt enable */ -#define ADC_IER_ADRDYIE ((uint32_t)0x00000001U) /*!< ADC Ready interrupt enable */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1U << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */ +#define ADC_IER_AWDIE_Pos (7U) +#define ADC_IER_AWDIE_Msk (0x1U << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */ +#define ADC_IER_EOSEQIE_Pos (3U) +#define ADC_IER_EOSEQIE_Msk (0x1U << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */ /* Old EOSEQIE bit definition, maintained for legacy purpose */ #define ADC_IER_EOSIE ADC_IER_EOSEQIE /******************** Bits definition for ADC_CR register *******************/ -#define ADC_CR_ADCAL ((uint32_t)0x80000000U) /*!< ADC calibration */ -#define ADC_CR_ADVREGEN ((uint32_t)0x10000000U) /*!< ADC Voltage Regulator Enable */ -#define ADC_CR_ADSTP ((uint32_t)0x00000010U) /*!< ADC stop of conversion command */ -#define ADC_CR_ADSTART ((uint32_t)0x00000004U) /*!< ADC start of conversion */ -#define ADC_CR_ADDIS ((uint32_t)0x00000002U) /*!< ADC disable command */ -#define ADC_CR_ADEN ((uint32_t)0x00000001U) /*!< ADC enable control */ /*#### TBV */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */ /******************* Bits definition for ADC_CFGR1 register *****************/ -#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000U) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000U) /*!< Bit 0 */ -#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000U) /*!< Bit 1 */ -#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000U) /*!< Bit 2 */ -#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000U) /*!< Bit 3 */ -#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000U) /*!< Bit 4 */ -#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000U) /*!< Analog watchdog enable on regular channels */ -#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000U) /*!< Enable the watchdog on a single channel or on all channels */ -#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000U) /*!< Discontinuous mode on regular channels */ -#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000U) /*!< ADC auto power off */ -#define ADC_CFGR1_WAIT ((uint32_t)0x00004000U) /*!< ADC wait conversion mode */ -#define ADC_CFGR1_CONT ((uint32_t)0x00002000U) /*!< Continuous Conversion */ -#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000U) /*!< Overrun mode */ -#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00U) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ -#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ -#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ -#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0U) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ -#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ -#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100U) /*!< Bit 2 */ -#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020U) /*!< Data Alignment */ -#define ADC_CFGR1_RES ((uint32_t)0x00000018U) /*!< RES[1:0] bits (Resolution) */ -#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ -#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004U) /*!< Sequence scan direction */ -#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002U) /*!< Direct memory access configuration */ -#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001U) /*!< Direct memory access enable */ +#define ADC_CFGR1_AWDCH_Pos (26U) +#define ADC_CFGR1_AWDCH_Msk (0x1FU << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CFGR1_AWDCH_0 (0x01U << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWDCH_1 (0x02U << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWDCH_2 (0x04U << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWDCH_3 (0x08U << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWDCH_4 (0x10U << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ +#define ADC_CFGR1_AWDEN_Pos (23U) +#define ADC_CFGR1_AWDEN_Msk (0x1U << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */ +#define ADC_CFGR1_AWDSGL_Pos (22U) +#define ADC_CFGR1_AWDSGL_Msk (0x1U << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */ +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */ +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ +#define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */ +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */ /* Old WAIT bit definition, maintained for legacy purpose */ #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT /******************* Bits definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_TOVS ((uint32_t)0x80000200U) /*!< Triggered Oversampling */ -#define ADC_CFGR2_OVSS ((uint32_t)0x000001E0U) /*!< OVSS [3:0] bits (Oversampling shift) */ -#define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ -#define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ -#define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ -#define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ -#define ADC_CFGR2_OVSR ((uint32_t)0x0000001CU) /*!< OVSR [2:0] bits (Oversampling ratio) */ -#define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004U) /*!< Bit 0 */ -#define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008U) /*!< Bit 1 */ -#define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010U) /*!< Bit 2 */ -#define ADC_CFGR2_OVSE ((uint32_t)0x00000001U) /*!< Oversampler Enable */ -#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000U) /*!< CKMODE [1:0] bits (ADC clock mode) */ -#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000U) /*!< Bit 0 */ -#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000U) /*!< Bit 1 */ +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x400001U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */ +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */ +#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */ +#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1U << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */ +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */ +#define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ /****************** Bit definition for ADC_SMPR register ********************/ -#define ADC_SMPR_SMP ((uint32_t)0x00000007U) /*!< SMPR[2:0] bits (Sampling time selection) */ -#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ -#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ -#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SMPR_SMP_Pos (0U) +#define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */ +#define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ /* Legacy defines */ #define ADC_SMPR_SMPR ADC_SMPR_SMP @@ -875,47 +961,105 @@ typedef struct #define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2 /******************* Bit definition for ADC_TR register ********************/ -#define ADC_TR_HT ((uint32_t)0x0FFF0000U) /*!< Analog watchdog high threshold */ -#define ADC_TR_LT ((uint32_t)0x00000FFFU) /*!< Analog watchdog low threshold */ +#define ADC_TR_HT_Pos (16U) +#define ADC_TR_HT_Msk (0xFFFU << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */ +#define ADC_TR_LT_Pos (0U) +#define ADC_TR_LT_Msk (0xFFFU << ADC_TR_LT_Pos) /*!< 0x00000FFF */ +#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */ /****************** Bit definition for ADC_CHSELR register ******************/ -#define ADC_CHSELR_CHSEL ((uint32_t)0x0007FFFFU) /*!< ADC group regular sequencer channels */ -#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000U) /*!< Channel 18 selection */ -#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000U) /*!< Channel 17 selection */ -#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000U) /*!< Channel 16 selection */ -#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000U) /*!< Channel 15 selection */ -#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000U) /*!< Channel 14 selection */ -#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000U) /*!< Channel 13 selection */ -#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000U) /*!< Channel 12 selection */ -#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800U) /*!< Channel 11 selection */ -#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400U) /*!< Channel 10 selection */ -#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200U) /*!< Channel 9 selection */ -#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100U) /*!< Channel 8 selection */ -#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080U) /*!< Channel 7 selection */ -#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040U) /*!< Channel 6 selection */ -#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020U) /*!< Channel 5 selection */ -#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010U) /*!< Channel 4 selection */ -#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008U) /*!< Channel 3 selection */ -#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004U) /*!< Channel 2 selection */ -#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002U) /*!< Channel 1 selection */ -#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001U) /*!< Channel 0 selection */ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1U << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< Channel 16 selection */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFFU) /*!< Regular data */ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */ /******************** Bit definition for ADC_CALFACT register ********************/ -#define ADC_CALFACT_CALFACT ((uint32_t)0x0000007FU) /*!< Calibration factor */ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FU << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */ /******************* Bit definition for ADC_CCR register ********************/ -#define ADC_CCR_LFMEN ((uint32_t)0x02000000U) /*!< Low Frequency Mode enable */ -#define ADC_CCR_VLCDEN ((uint32_t)0x01000000U) /*!< Voltage LCD enable */ -#define ADC_CCR_TSEN ((uint32_t)0x00800000U) /*!< Temperature sensore enable */ -#define ADC_CCR_VREFEN ((uint32_t)0x00400000U) /*!< Vrefint enable */ -#define ADC_CCR_PRESC ((uint32_t)0x003C0000U) /*!< PRESC [3:0] bits (ADC prescaler) */ -#define ADC_CCR_PRESC_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ -#define ADC_CCR_PRESC_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ -#define ADC_CCR_PRESC_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ -#define ADC_CCR_PRESC_3 ((uint32_t)0x00200000U) /*!< Bit 3 */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1U << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */ +#define ADC_CCR_VLCDEN_Pos (24U) +#define ADC_CCR_VLCDEN_Msk (0x1U << ADC_CCR_VLCDEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VLCDEN ADC_CCR_VLCDEN_Msk /*!< Voltage LCD enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */ +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */ +#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ /******************************************************************************/ /* */ @@ -924,37 +1068,77 @@ typedef struct /******************************************************************************/ /************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/ /* COMP1 bits definition */ -#define COMP_CSR_COMP1EN ((uint32_t)0x00000001U) /*!< COMP1 enable */ -#define COMP_CSR_COMP1INNSEL ((uint32_t)0x00000030U) /*!< COMP1 inverting input select */ -#define COMP_CSR_COMP1INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP1 inverting input select bit 0 */ -#define COMP_CSR_COMP1INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP1 inverting input select bit 1 */ -#define COMP_CSR_COMP1WM ((uint32_t)0x00000100U) /*!< Comparators window mode enable */ -#define COMP_CSR_COMP1LPTIM1IN1 ((uint32_t)0x00001000U) /*!< COMP1 LPTIM1 IN1 connection */ -#define COMP_CSR_COMP1POLARITY ((uint32_t)0x00008000U) /*!< COMP1 output polarity */ -#define COMP_CSR_COMP1VALUE ((uint32_t)0x40000000U) /*!< COMP1 output level */ -#define COMP_CSR_COMP1LOCK ((uint32_t)0x80000000U) /*!< COMP1 lock */ +#define COMP_CSR_COMP1EN_Pos (0U) +#define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */ +#define COMP_CSR_COMP1INNSEL_Pos (4U) +#define COMP_CSR_COMP1INNSEL_Msk (0x3U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */ +#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */ +#define COMP_CSR_COMP1INNSEL_0 (0x1U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_COMP1INNSEL_1 (0x2U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_COMP1WM_Pos (8U) +#define COMP_CSR_COMP1WM_Msk (0x1U << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */ +#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */ +#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U) +#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */ +#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */ +#define COMP_CSR_COMP1POLARITY_Pos (15U) +#define COMP_CSR_COMP1POLARITY_Msk (0x1U << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */ +#define COMP_CSR_COMP1VALUE_Pos (30U) +#define COMP_CSR_COMP1VALUE_Msk (0x1U << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */ +#define COMP_CSR_COMP1LOCK_Pos (31U) +#define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */ /* COMP2 bits definition */ -#define COMP_CSR_COMP2EN ((uint32_t)0x00000001U) /*!< COMP2 enable */ -#define COMP_CSR_COMP2SPEED ((uint32_t)0x00000008U) /*!< COMP2 power mode */ -#define COMP_CSR_COMP2INNSEL ((uint32_t)0x00000070U) /*!< COMP2 inverting input select */ -#define COMP_CSR_COMP2INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP2 inverting input select bit 0 */ -#define COMP_CSR_COMP2INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP2 inverting input select bit 1 */ -#define COMP_CSR_COMP2INNSEL_2 ((uint32_t)0x00000040U) /*!< COMP2 inverting input select bit 2 */ -#define COMP_CSR_COMP2INPSEL ((uint32_t)0x00000700U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2INPSEL_0 ((uint32_t)0x00000100U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2INPSEL_1 ((uint32_t)0x00000200U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2INPSEL_2 ((uint32_t)0x00000400U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2LPTIM1IN2 ((uint32_t)0x00001000U) /*!< COMP2 LPTIM1 IN2 connection */ -#define COMP_CSR_COMP2LPTIM1IN1 ((uint32_t)0x00002000U) /*!< COMP2 LPTIM1 IN1 connection */ -#define COMP_CSR_COMP2POLARITY ((uint32_t)0x00008000U) /*!< COMP2 output polarity */ -#define COMP_CSR_COMP2VALUE ((uint32_t)0x40000000U) /*!< COMP2 output level */ -#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000U) /*!< COMP2 lock */ +#define COMP_CSR_COMP2EN_Pos (0U) +#define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */ +#define COMP_CSR_COMP2SPEED_Pos (3U) +#define COMP_CSR_COMP2SPEED_Msk (0x1U << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */ +#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */ +#define COMP_CSR_COMP2INNSEL_Pos (4U) +#define COMP_CSR_COMP2INNSEL_Msk (0x7U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */ +#define COMP_CSR_COMP2INNSEL_0 (0x1U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_COMP2INNSEL_1 (0x2U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_COMP2INNSEL_2 (0x4U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_COMP2INPSEL_Pos (8U) +#define COMP_CSR_COMP2INPSEL_Msk (0x7U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */ +#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */ +#define COMP_CSR_COMP2INPSEL_0 (0x1U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_COMP2INPSEL_1 (0x2U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */ +#define COMP_CSR_COMP2INPSEL_2 (0x4U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */ +#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U) +#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */ +#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */ +#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U) +#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */ +#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */ +#define COMP_CSR_COMP2POLARITY_Pos (15U) +#define COMP_CSR_COMP2POLARITY_Msk (0x1U << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */ +#define COMP_CSR_COMP2VALUE_Pos (30U) +#define COMP_CSR_COMP2VALUE_Msk (0x1U << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */ +#define COMP_CSR_COMP2LOCK_Pos (31U) +#define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */ /********************** Bit definition for COMP_CSR register common ****************/ -#define COMP_CSR_COMPxEN ((uint32_t)0x00000001U) /*!< COMPx enable */ -#define COMP_CSR_COMPxPOLARITY ((uint32_t)0x00008000U) /*!< COMPx output polarity */ -#define COMP_CSR_COMPxOUTVALUE ((uint32_t)0x40000000U) /*!< COMPx output level */ -#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000U) /*!< COMPx lock */ +#define COMP_CSR_COMPxEN_Pos (0U) +#define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */ +#define COMP_CSR_COMPxPOLARITY_Pos (15U) +#define COMP_CSR_COMPxPOLARITY_Msk (0x1U << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */ +#define COMP_CSR_COMPxOUTVALUE_Pos (30U) +#define COMP_CSR_COMPxOUTVALUE_Msk (0x1U << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */ +#define COMP_CSR_COMPxLOCK_Pos (31U) +#define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */ /* Reference defines */ #define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ @@ -965,26 +1149,40 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ +#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET the CRC computation unit bit */ -#define CRC_CR_POLYSIZE ((uint32_t)0x00000018U) /*!< Polynomial size bits */ -#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008U) /*!< Polynomial size bit 0 */ -#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010U) /*!< Polynomial size bit 1 */ -#define CRC_CR_REV_IN ((uint32_t)0x00000060U) /*!< REV_IN Reverse Input Data bits */ -#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ -#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ -#define CRC_CR_REV_OUT ((uint32_t)0x00000080U) /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ /******************* Bit definition for CRC_INIT register *******************/ -#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFFU) /*!< Initial CRC value bits */ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ -#define CRC_POL_POL ((uint32_t)0xFFFFFFFFU) /*!< Coefficients of the polynomial */ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ /******************************************************************************/ /* */ @@ -993,46 +1191,98 @@ typedef struct /******************************************************************************/ /******************* Bit definition for CRS_CR register *********************/ -#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001U) /* SYNC event OK interrupt enable */ -#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002U) /* SYNC warning interrupt enable */ -#define CRS_CR_ERRIE ((uint32_t)0x00000004U) /* SYNC error interrupt enable */ -#define CRS_CR_ESYNCIE ((uint32_t)0x00000008U) /* Expected SYNC(ESYNCF) interrupt Enable*/ -#define CRS_CR_CEN ((uint32_t)0x00000020U) /* Frequency error counter enable */ -#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040U) /* Automatic trimming enable */ -#define CRS_CR_SWSYNC ((uint32_t)0x00000080U) /* A Software SYNC event is generated */ -#define CRS_CR_TRIM ((uint32_t)0x00003F00U) /* HSI48 oscillator smooth trimming */ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ -#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFFU) /* Counter reload value */ -#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000U) /* Frequency error limit */ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */ -#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000U) /* SYNC divider */ -#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000U) /* Bit 0 */ -#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000U) /* Bit 1 */ -#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000U) /* Bit 2 */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ -#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000U) /* SYNC signal source selection */ -#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000U) /* Bit 0 */ -#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000U) /* Bit 1 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ -#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000U) /* SYNC polarity selection */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */ /******************* Bit definition for CRS_ISR register *********************/ -#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001U) /* SYNC event OK flag */ -#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002U) /* SYNC warning */ -#define CRS_ISR_ERRF ((uint32_t)0x00000004U) /* SYNC error flag */ -#define CRS_ISR_ESYNCF ((uint32_t)0x00000008U) /* Expected SYNC flag */ -#define CRS_ISR_SYNCERR ((uint32_t)0x00000100U) /* SYNC error */ -#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200U) /* SYNC missed */ -#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400U) /* Trimming overflow or underflow */ -#define CRS_ISR_FEDIR ((uint32_t)0x00008000U) /* Frequency error direction */ -#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000U) /* Frequency error capture */ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */ /******************* Bit definition for CRS_ICR register *********************/ -#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001U) /* SYNC event OK clear flag */ -#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002U) /* SYNC warning clear flag */ -#define CRS_ICR_ERRC ((uint32_t)0x00000004U) /* Error clear flag */ -#define CRS_ICR_ESYNCC ((uint32_t)0x00000008U) /* Expected SYNC clear flag */ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */ /******************************************************************************/ /* */ @@ -1046,45 +1296,71 @@ typedef struct /* Note: No specific macro feature on this device */ /******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((uint32_t)0x00000001U) /*!< DAC channel1 enable */ -#define DAC_CR_BOFF1 ((uint32_t)0x00000002U) /*!< DAC channel1 output buffer disable */ -#define DAC_CR_TEN1 ((uint32_t)0x00000004U) /*!< DAC channel1 Trigger enable */ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ +#define DAC_CR_BOFF1_Pos (1U) +#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ +#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */ +#define DAC_CR_TEN1_Pos (2U) +#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ +#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */ -#define DAC_CR_TSEL1 ((uint32_t)0x00000038U) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ -#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ +#define DAC_CR_TSEL1_Pos (3U) +#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ +#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ +#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ +#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ -#define DAC_CR_WAVE1 ((uint32_t)0x000000C0U) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ -#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ +#define DAC_CR_WAVE1_Pos (6U) +#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ +#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ +#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ -#define DAC_CR_MAMP1 ((uint32_t)0x00000F00U) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ -#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */ -#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */ -#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */ -#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800U) /*!< Bit 3 */ +#define DAC_CR_MAMP1_Pos (8U) +#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ +#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ +#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ +#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ +#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ -#define DAC_CR_DMAEN1 ((uint32_t)0x00001000U) /*!< DAC channel1 DMA enable */ -#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA Underrun interrupt enable */ +#define DAC_CR_DMAEN1_Pos (12U) +#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ +#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ +#define DAC_CR_DMAUDRIE1_Pos (13U) +#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ +#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun interrupt enable */ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001U) /*!< DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */ /***************** Bit definition for DAC_DHR12R1 register ******************/ -#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFFU) /*!< DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12R1_DACC1DHR_Pos (0U) +#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ /***************** Bit definition for DAC_DHR12L1 register ******************/ -#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0U) /*!< DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12L1_DACC1DHR_Pos (4U) +#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ /****************** Bit definition for DAC_DHR8R1 register ******************/ -#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FFU) /*!< DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8R1_DACC1DHR_Pos (0U) +#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ /******************* Bit definition for DAC_DOR1 register *******************/ -#define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFFU) /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFFU) /*!< DAC channel1 data output */ /******************** Bit definition for DAC_SR register ********************/ -#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_DMAUDR1_Pos (13U) +#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ +#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ /******************************************************************************/ /* */ @@ -1093,44 +1369,76 @@ typedef struct /******************************************************************************/ /**************** Bit definition for DBGMCU_IDCODE register *****************/ -#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU) /*!< Device Identifier */ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ -#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U) /*!< REV_ID[15:0] bits (Revision Identifier) */ -#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ -#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ -#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000U) /*!< Bit 2 */ -#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000U) /*!< Bit 3 */ -#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000U) /*!< Bit 4 */ -#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000U) /*!< Bit 5 */ -#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000U) /*!< Bit 6 */ -#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000U) /*!< Bit 7 */ -#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000U) /*!< Bit 8 */ -#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000U) /*!< Bit 9 */ -#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000U) /*!< Bit 10 */ -#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000U) /*!< Bit 11 */ -#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000U) /*!< Bit 12 */ -#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000U) /*!< Bit 13 */ -#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000U) /*!< Bit 14 */ -#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000U) /*!< Bit 15 */ +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ +#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ +#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ +#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ +#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ +#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ +#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ +#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ +#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ +#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ +#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ +#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ +#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ +#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ +#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ +#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ +#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ /****************** Bit definition for DBGMCU_CR register *******************/ -#define DBGMCU_CR_DBG ((uint32_t)0x00000007U) /*!< Debug mode mask */ -#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001U) /*!< Debug Sleep Mode */ -#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U) /*!< Debug Stop Mode */ -#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U) /*!< Debug Standby mode */ +#define DBGMCU_CR_DBG_Pos (0U) +#define DBGMCU_CR_DBG_Msk (0x7U << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */ +#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */ +#define DBGMCU_CR_DBG_SLEEP_Pos (0U) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ /****************** Bit definition for DBGMCU_APB1_FZ register **************/ -#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001U) /*!< TIM2 counter stopped when core is halted */ -#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010U) /*!< TIM6 counter stopped when core is halted */ -#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400U) /*!< RTC Calendar frozen when core is halted */ -#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800U) /*!< Debug Window Watchdog stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000U) /*!< Debug Independent Watchdog stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_I2C1_STOP ((uint32_t)0x00200000U) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_I2C2_STOP ((uint32_t)0x00400000U) /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP ((uint32_t)0x80000000U) /*!< LPTIM1 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) +#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) +#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */ +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U) +#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U) +#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */ +#define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U) +#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */ +#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */ /****************** Bit definition for DBGMCU_APB2_FZ register **************/ -#define DBGMCU_APB2_FZ_DBG_TIM22_STOP ((uint32_t)0x00000020U) /*!< TIM22 counter stopped when core is halted */ -#define DBGMCU_APB2_FZ_DBG_TIM21_STOP ((uint32_t)0x00000004U) /*!< TIM21 counter stopped when core is halted */ +#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U) +#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */ +#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U) +#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */ /******************************************************************************/ /* */ @@ -1139,108 +1447,263 @@ typedef struct /******************************************************************************/ /******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error flag */ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ /******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt clear */ -#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error clear */ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ /******************* Bit definition for DMA_CCR register ********************/ -#define DMA_CCR_EN ((uint32_t)0x00000001U) /*!< Channel enable */ -#define DMA_CCR_TCIE ((uint32_t)0x00000002U) /*!< Transfer complete interrupt enable */ -#define DMA_CCR_HTIE ((uint32_t)0x00000004U) /*!< Half Transfer interrupt enable */ -#define DMA_CCR_TEIE ((uint32_t)0x00000008U) /*!< Transfer error interrupt enable */ -#define DMA_CCR_DIR ((uint32_t)0x00000010U) /*!< Data transfer direction */ -#define DMA_CCR_CIRC ((uint32_t)0x00000020U) /*!< Circular mode */ -#define DMA_CCR_PINC ((uint32_t)0x00000040U) /*!< Peripheral increment mode */ -#define DMA_CCR_MINC ((uint32_t)0x00000080U) /*!< Memory increment mode */ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ -#define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */ -#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */ +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ -#define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ -#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ -#define DMA_CCR_PL ((uint32_t)0x00003000U) /*!< PL[1:0] bits(Channel Priority level)*/ -#define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ -#define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ -#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /*!< Memory to memory mode */ +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ /****************** Bit definition for DMA_CNDTR register *******************/ -#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ /****************** Bit definition for DMA_CPAR register ********************/ -#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ /****************** Bit definition for DMA_CMAR register ********************/ -#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ /******************* Bit definition for DMA_CSELR register *******************/ -#define DMA_CSELR_C1S ((uint32_t)0x0000000FU) /*!< Channel 1 Selection */ -#define DMA_CSELR_C2S ((uint32_t)0x000000F0U) /*!< Channel 2 Selection */ -#define DMA_CSELR_C3S ((uint32_t)0x00000F00U) /*!< Channel 3 Selection */ -#define DMA_CSELR_C4S ((uint32_t)0x0000F000U) /*!< Channel 4 Selection */ -#define DMA_CSELR_C5S ((uint32_t)0x000F0000U) /*!< Channel 5 Selection */ -#define DMA_CSELR_C6S ((uint32_t)0x00F00000U) /*!< Channel 6 Selection */ -#define DMA_CSELR_C7S ((uint32_t)0x0F000000U) /*!< Channel 7 Selection */ - +#define DMA_CSELR_C1S_Pos (0U) +#define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */ +#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */ +#define DMA_CSELR_C2S_Pos (4U) +#define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */ +#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */ +#define DMA_CSELR_C3S_Pos (8U) +#define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */ +#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */ +#define DMA_CSELR_C4S_Pos (12U) +#define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */ +#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */ +#define DMA_CSELR_C5S_Pos (16U) +#define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */ +#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */ +#define DMA_CSELR_C6S_Pos (20U) +#define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */ +#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */ +#define DMA_CSELR_C7S_Pos (24U) +#define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */ +#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */ /******************************************************************************/ /* */ @@ -1249,88 +1712,248 @@ typedef struct /******************************************************************************/ /******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_IM0 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_IM1 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_IM2 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_IM3 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_IM4 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_IM5 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_IM6 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_IM7 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_IM8 ((uint32_t)0x00000100U) /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_IM9 ((uint32_t)0x00000200U) /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_IM10 ((uint32_t)0x00000400U) /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_IM11 ((uint32_t)0x00000800U) /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_IM12 ((uint32_t)0x00001000U) /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_IM13 ((uint32_t)0x00002000U) /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_IM14 ((uint32_t)0x00004000U) /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_IM15 ((uint32_t)0x00008000U) /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_IM16 ((uint32_t)0x00010000U) /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_IM17 ((uint32_t)0x00020000U) /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_IM18 ((uint32_t)0x00040000U) /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_IM19 ((uint32_t)0x00080000U) /*!< Interrupt Mask on line 19 */ -#define EXTI_IMR_IM20 ((uint32_t)0x00100000U) /*!< Interrupt Mask on line 20 */ -#define EXTI_IMR_IM21 ((uint32_t)0x00200000U) /*!< Interrupt Mask on line 21 */ -#define EXTI_IMR_IM22 ((uint32_t)0x00400000U) /*!< Interrupt Mask on line 22 */ -#define EXTI_IMR_IM23 ((uint32_t)0x00800000U) /*!< Interrupt Mask on line 23 */ -#define EXTI_IMR_IM25 ((uint32_t)0x02000000U) /*!< Interrupt Mask on line 25 */ -#define EXTI_IMR_IM26 ((uint32_t)0x04000000U) /*!< Interrupt Mask on line 26 */ -#define EXTI_IMR_IM28 ((uint32_t)0x10000000U) /*!< Interrupt Mask on line 28 */ -#define EXTI_IMR_IM29 ((uint32_t)0x20000000U) /*!< Interrupt Mask on line 29 */ +#define EXTI_IMR_IM0_Pos (0U) +#define EXTI_IMR_IM0_Msk (0x1U << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_IM1_Pos (1U) +#define EXTI_IMR_IM1_Msk (0x1U << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_IM2_Pos (2U) +#define EXTI_IMR_IM2_Msk (0x1U << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_IM3_Pos (3U) +#define EXTI_IMR_IM3_Msk (0x1U << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_IM4_Pos (4U) +#define EXTI_IMR_IM4_Msk (0x1U << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_IM5_Pos (5U) +#define EXTI_IMR_IM5_Msk (0x1U << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_IM6_Pos (6U) +#define EXTI_IMR_IM6_Msk (0x1U << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_IM7_Pos (7U) +#define EXTI_IMR_IM7_Msk (0x1U << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_IM8_Pos (8U) +#define EXTI_IMR_IM8_Msk (0x1U << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_IM9_Pos (9U) +#define EXTI_IMR_IM9_Msk (0x1U << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_IM10_Pos (10U) +#define EXTI_IMR_IM10_Msk (0x1U << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_IM11_Pos (11U) +#define EXTI_IMR_IM11_Msk (0x1U << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_IM12_Pos (12U) +#define EXTI_IMR_IM12_Msk (0x1U << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_IM13_Pos (13U) +#define EXTI_IMR_IM13_Msk (0x1U << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_IM14_Pos (14U) +#define EXTI_IMR_IM14_Msk (0x1U << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_IM15_Pos (15U) +#define EXTI_IMR_IM15_Msk (0x1U << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_IM16_Pos (16U) +#define EXTI_IMR_IM16_Msk (0x1U << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_IM17_Pos (17U) +#define EXTI_IMR_IM17_Msk (0x1U << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_IM18_Pos (18U) +#define EXTI_IMR_IM18_Msk (0x1U << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_IM19_Pos (19U) +#define EXTI_IMR_IM19_Msk (0x1U << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR_IM20_Pos (20U) +#define EXTI_IMR_IM20_Msk (0x1U << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */ +#define EXTI_IMR_IM21_Pos (21U) +#define EXTI_IMR_IM21_Msk (0x1U << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */ +#define EXTI_IMR_IM22_Pos (22U) +#define EXTI_IMR_IM22_Msk (0x1U << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */ +#define EXTI_IMR_IM23_Pos (23U) +#define EXTI_IMR_IM23_Msk (0x1U << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR_IM25_Pos (25U) +#define EXTI_IMR_IM25_Msk (0x1U << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR_IM26_Pos (26U) +#define EXTI_IMR_IM26_Msk (0x1U << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */ +#define EXTI_IMR_IM28_Pos (28U) +#define EXTI_IMR_IM28_Msk (0x1U << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */ +#define EXTI_IMR_IM29_Pos (29U) +#define EXTI_IMR_IM29_Msk (0x1U << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */ + +#define EXTI_IMR_IM_Pos (0U) +#define EXTI_IMR_IM_Msk (0x36FFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */ +#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ /****************** Bit definition for EXTI_EMR register ********************/ -#define EXTI_EMR_EM0 ((uint32_t)0x00000001U) /*!< Event Mask on line 0 */ -#define EXTI_EMR_EM1 ((uint32_t)0x00000002U) /*!< Event Mask on line 1 */ -#define EXTI_EMR_EM2 ((uint32_t)0x00000004U) /*!< Event Mask on line 2 */ -#define EXTI_EMR_EM3 ((uint32_t)0x00000008U) /*!< Event Mask on line 3 */ -#define EXTI_EMR_EM4 ((uint32_t)0x00000010U) /*!< Event Mask on line 4 */ -#define EXTI_EMR_EM5 ((uint32_t)0x00000020U) /*!< Event Mask on line 5 */ -#define EXTI_EMR_EM6 ((uint32_t)0x00000040U) /*!< Event Mask on line 6 */ -#define EXTI_EMR_EM7 ((uint32_t)0x00000080U) /*!< Event Mask on line 7 */ -#define EXTI_EMR_EM8 ((uint32_t)0x00000100U) /*!< Event Mask on line 8 */ -#define EXTI_EMR_EM9 ((uint32_t)0x00000200U) /*!< Event Mask on line 9 */ -#define EXTI_EMR_EM10 ((uint32_t)0x00000400U) /*!< Event Mask on line 10 */ -#define EXTI_EMR_EM11 ((uint32_t)0x00000800U) /*!< Event Mask on line 11 */ -#define EXTI_EMR_EM12 ((uint32_t)0x00001000U) /*!< Event Mask on line 12 */ -#define EXTI_EMR_EM13 ((uint32_t)0x00002000U) /*!< Event Mask on line 13 */ -#define EXTI_EMR_EM14 ((uint32_t)0x00004000U) /*!< Event Mask on line 14 */ -#define EXTI_EMR_EM15 ((uint32_t)0x00008000U) /*!< Event Mask on line 15 */ -#define EXTI_EMR_EM16 ((uint32_t)0x00010000U) /*!< Event Mask on line 16 */ -#define EXTI_EMR_EM17 ((uint32_t)0x00020000U) /*!< Event Mask on line 17 */ -#define EXTI_EMR_EM18 ((uint32_t)0x00040000U) /*!< Event Mask on line 18 */ -#define EXTI_EMR_EM19 ((uint32_t)0x00080000U) /*!< Event Mask on line 19 */ -#define EXTI_EMR_EM20 ((uint32_t)0x00100000U) /*!< Event Mask on line 20 */ -#define EXTI_EMR_EM21 ((uint32_t)0x00200000U) /*!< Event Mask on line 21 */ -#define EXTI_EMR_EM22 ((uint32_t)0x00400000U) /*!< Event Mask on line 22 */ -#define EXTI_EMR_EM23 ((uint32_t)0x00800000U) /*!< Event Mask on line 23 */ -#define EXTI_EMR_EM25 ((uint32_t)0x02000000U) /*!< Event Mask on line 25 */ -#define EXTI_EMR_EM26 ((uint32_t)0x04000000U) /*!< Event Mask on line 26 */ -#define EXTI_EMR_EM28 ((uint32_t)0x10000000U) /*!< Event Mask on line 28 */ -#define EXTI_EMR_EM29 ((uint32_t)0x20000000U) /*!< Event Mask on line 29 */ +#define EXTI_EMR_EM0_Pos (0U) +#define EXTI_EMR_EM0_Msk (0x1U << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR_EM1_Pos (1U) +#define EXTI_EMR_EM1_Msk (0x1U << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR_EM2_Pos (2U) +#define EXTI_EMR_EM2_Msk (0x1U << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR_EM3_Pos (3U) +#define EXTI_EMR_EM3_Msk (0x1U << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR_EM4_Pos (4U) +#define EXTI_EMR_EM4_Msk (0x1U << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR_EM5_Pos (5U) +#define EXTI_EMR_EM5_Msk (0x1U << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR_EM6_Pos (6U) +#define EXTI_EMR_EM6_Msk (0x1U << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR_EM7_Pos (7U) +#define EXTI_EMR_EM7_Msk (0x1U << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR_EM8_Pos (8U) +#define EXTI_EMR_EM8_Msk (0x1U << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR_EM9_Pos (9U) +#define EXTI_EMR_EM9_Msk (0x1U << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR_EM10_Pos (10U) +#define EXTI_EMR_EM10_Msk (0x1U << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR_EM11_Pos (11U) +#define EXTI_EMR_EM11_Msk (0x1U << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR_EM12_Pos (12U) +#define EXTI_EMR_EM12_Msk (0x1U << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR_EM13_Pos (13U) +#define EXTI_EMR_EM13_Msk (0x1U << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR_EM14_Pos (14U) +#define EXTI_EMR_EM14_Msk (0x1U << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR_EM15_Pos (15U) +#define EXTI_EMR_EM15_Msk (0x1U << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR_EM16_Pos (16U) +#define EXTI_EMR_EM16_Msk (0x1U << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR_EM17_Pos (17U) +#define EXTI_EMR_EM17_Msk (0x1U << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR_EM18_Pos (18U) +#define EXTI_EMR_EM18_Msk (0x1U << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */ +#define EXTI_EMR_EM19_Pos (19U) +#define EXTI_EMR_EM19_Msk (0x1U << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR_EM20_Pos (20U) +#define EXTI_EMR_EM20_Msk (0x1U << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */ +#define EXTI_EMR_EM21_Pos (21U) +#define EXTI_EMR_EM21_Msk (0x1U << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */ +#define EXTI_EMR_EM22_Pos (22U) +#define EXTI_EMR_EM22_Msk (0x1U << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */ +#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */ +#define EXTI_EMR_EM23_Pos (23U) +#define EXTI_EMR_EM23_Msk (0x1U << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR_EM25_Pos (25U) +#define EXTI_EMR_EM25_Msk (0x1U << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR_EM26_Pos (26U) +#define EXTI_EMR_EM26_Msk (0x1U << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */ +#define EXTI_EMR_EM28_Pos (28U) +#define EXTI_EMR_EM28_Msk (0x1U << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */ +#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */ +#define EXTI_EMR_EM29_Pos (29U) +#define EXTI_EMR_EM29_Msk (0x1U << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */ +#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */ /******************* Bit definition for EXTI_RTSR register ******************/ -#define EXTI_RTSR_RT0 ((uint32_t)0x00000001U) /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_RT1 ((uint32_t)0x00000002U) /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_RT2 ((uint32_t)0x00000004U) /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_RT3 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_RT4 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_RT5 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_RT6 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_RT7 ((uint32_t)0x00000080U) /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_RT8 ((uint32_t)0x00000100U) /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_RT9 ((uint32_t)0x00000200U) /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_RT10 ((uint32_t)0x00000400U) /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_RT11 ((uint32_t)0x00000800U) /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_RT12 ((uint32_t)0x00001000U) /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_RT13 ((uint32_t)0x00002000U) /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_RT14 ((uint32_t)0x00004000U) /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_RT15 ((uint32_t)0x00008000U) /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_RT16 ((uint32_t)0x00010000U) /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_RT17 ((uint32_t)0x00020000U) /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_RT19 ((uint32_t)0x00080000U) /*!< Rising trigger event configuration bit of line 19 */ -#define EXTI_RTSR_RT20 ((uint32_t)0x00100000U) /*!< Rising trigger event configuration bit of line 20 */ -#define EXTI_RTSR_RT21 ((uint32_t)0x00200000U) /*!< Rising trigger event configuration bit of line 21 */ -#define EXTI_RTSR_RT22 ((uint32_t)0x00400000U) /*!< Rising trigger event configuration bit of line 22 */ +#define EXTI_RTSR_RT0_Pos (0U) +#define EXTI_RTSR_RT0_Msk (0x1U << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_RT1_Pos (1U) +#define EXTI_RTSR_RT1_Msk (0x1U << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_RT2_Pos (2U) +#define EXTI_RTSR_RT2_Msk (0x1U << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_RT3_Pos (3U) +#define EXTI_RTSR_RT3_Msk (0x1U << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_RT4_Pos (4U) +#define EXTI_RTSR_RT4_Msk (0x1U << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_RT5_Pos (5U) +#define EXTI_RTSR_RT5_Msk (0x1U << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_RT6_Pos (6U) +#define EXTI_RTSR_RT6_Msk (0x1U << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_RT7_Pos (7U) +#define EXTI_RTSR_RT7_Msk (0x1U << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_RT8_Pos (8U) +#define EXTI_RTSR_RT8_Msk (0x1U << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_RT9_Pos (9U) +#define EXTI_RTSR_RT9_Msk (0x1U << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_RT10_Pos (10U) +#define EXTI_RTSR_RT10_Msk (0x1U << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_RT11_Pos (11U) +#define EXTI_RTSR_RT11_Msk (0x1U << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_RT12_Pos (12U) +#define EXTI_RTSR_RT12_Msk (0x1U << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_RT13_Pos (13U) +#define EXTI_RTSR_RT13_Msk (0x1U << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_RT14_Pos (14U) +#define EXTI_RTSR_RT14_Msk (0x1U << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_RT15_Pos (15U) +#define EXTI_RTSR_RT15_Msk (0x1U << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_RT16_Pos (16U) +#define EXTI_RTSR_RT16_Msk (0x1U << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_RT17_Pos (17U) +#define EXTI_RTSR_RT17_Msk (0x1U << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_RT19_Pos (19U) +#define EXTI_RTSR_RT19_Msk (0x1U << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */ +#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_RTSR_RT20_Pos (20U) +#define EXTI_RTSR_RT20_Msk (0x1U << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */ +#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ +#define EXTI_RTSR_RT21_Pos (21U) +#define EXTI_RTSR_RT21_Msk (0x1U << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */ +#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ +#define EXTI_RTSR_RT22_Pos (22U) +#define EXTI_RTSR_RT22_Msk (0x1U << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */ +#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */ /* Legacy defines */ #define EXTI_RTSR_TR0 EXTI_RTSR_RT0 @@ -1357,28 +1980,72 @@ typedef struct #define EXTI_RTSR_TR22 EXTI_RTSR_RT22 /******************* Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_FT0 ((uint32_t)0x00000001U) /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_FT1 ((uint32_t)0x00000002U) /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_FT2 ((uint32_t)0x00000004U) /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_FT3 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_FT4 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_FT5 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_FT6 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_FT7 ((uint32_t)0x00000080U) /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_FT8 ((uint32_t)0x00000100U) /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_FT9 ((uint32_t)0x00000200U) /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_FT10 ((uint32_t)0x00000400U) /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_FT11 ((uint32_t)0x00000800U) /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_FT12 ((uint32_t)0x00001000U) /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_FT13 ((uint32_t)0x00002000U) /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_FT14 ((uint32_t)0x00004000U) /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_FT15 ((uint32_t)0x00008000U) /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_FT16 ((uint32_t)0x00010000U) /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_FT17 ((uint32_t)0x00020000U) /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_FT19 ((uint32_t)0x00080000U) /*!< Falling trigger event configuration bit of line 19 */ -#define EXTI_FTSR_FT20 ((uint32_t)0x00100000U) /*!< Falling trigger event configuration bit of line 20 */ -#define EXTI_FTSR_FT21 ((uint32_t)0x00200000U) /*!< Falling trigger event configuration bit of line 21 */ -#define EXTI_FTSR_FT22 ((uint32_t)0x00400000U) /*!< Falling trigger event configuration bit of line 22 */ +#define EXTI_FTSR_FT0_Pos (0U) +#define EXTI_FTSR_FT0_Msk (0x1U << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_FT1_Pos (1U) +#define EXTI_FTSR_FT1_Msk (0x1U << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_FT2_Pos (2U) +#define EXTI_FTSR_FT2_Msk (0x1U << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_FT3_Pos (3U) +#define EXTI_FTSR_FT3_Msk (0x1U << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_FT4_Pos (4U) +#define EXTI_FTSR_FT4_Msk (0x1U << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_FT5_Pos (5U) +#define EXTI_FTSR_FT5_Msk (0x1U << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_FT6_Pos (6U) +#define EXTI_FTSR_FT6_Msk (0x1U << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_FT7_Pos (7U) +#define EXTI_FTSR_FT7_Msk (0x1U << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_FT8_Pos (8U) +#define EXTI_FTSR_FT8_Msk (0x1U << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_FT9_Pos (9U) +#define EXTI_FTSR_FT9_Msk (0x1U << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_FT10_Pos (10U) +#define EXTI_FTSR_FT10_Msk (0x1U << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_FT11_Pos (11U) +#define EXTI_FTSR_FT11_Msk (0x1U << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_FT12_Pos (12U) +#define EXTI_FTSR_FT12_Msk (0x1U << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_FT13_Pos (13U) +#define EXTI_FTSR_FT13_Msk (0x1U << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_FT14_Pos (14U) +#define EXTI_FTSR_FT14_Msk (0x1U << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_FT15_Pos (15U) +#define EXTI_FTSR_FT15_Msk (0x1U << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_FT16_Pos (16U) +#define EXTI_FTSR_FT16_Msk (0x1U << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_FT17_Pos (17U) +#define EXTI_FTSR_FT17_Msk (0x1U << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_FT19_Pos (19U) +#define EXTI_FTSR_FT19_Msk (0x1U << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */ +#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_FTSR_FT20_Pos (20U) +#define EXTI_FTSR_FT20_Msk (0x1U << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */ +#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */ +#define EXTI_FTSR_FT21_Pos (21U) +#define EXTI_FTSR_FT21_Msk (0x1U << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */ +#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ +#define EXTI_FTSR_FT22_Pos (22U) +#define EXTI_FTSR_FT22_Msk (0x1U << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */ +#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */ /* Legacy defines */ #define EXTI_FTSR_TR0 EXTI_FTSR_FT0 @@ -1405,28 +2072,72 @@ typedef struct #define EXTI_FTSR_TR22 EXTI_FTSR_FT22 /******************* Bit definition for EXTI_SWIER register *******************/ -#define EXTI_SWIER_SWI0 ((uint32_t)0x00000001U) /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWI1 ((uint32_t)0x00000002U) /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWI2 ((uint32_t)0x00000004U) /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWI3 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWI4 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWI5 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWI6 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWI7 ((uint32_t)0x00000080U) /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWI8 ((uint32_t)0x00000100U) /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWI9 ((uint32_t)0x00000200U) /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWI10 ((uint32_t)0x00000400U) /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWI11 ((uint32_t)0x00000800U) /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWI12 ((uint32_t)0x00001000U) /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWI13 ((uint32_t)0x00002000U) /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWI14 ((uint32_t)0x00004000U) /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWI15 ((uint32_t)0x00008000U) /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWI16 ((uint32_t)0x00010000U) /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWI17 ((uint32_t)0x00020000U) /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWI19 ((uint32_t)0x00080000U) /*!< Software Interrupt on line 19 */ -#define EXTI_SWIER_SWI20 ((uint32_t)0x00100000U) /*!< Software Interrupt on line 20 */ -#define EXTI_SWIER_SWI21 ((uint32_t)0x00200000U) /*!< Software Interrupt on line 21 */ -#define EXTI_SWIER_SWI22 ((uint32_t)0x00400000U) /*!< Software Interrupt on line 22 */ +#define EXTI_SWIER_SWI0_Pos (0U) +#define EXTI_SWIER_SWI0_Msk (0x1U << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWI1_Pos (1U) +#define EXTI_SWIER_SWI1_Msk (0x1U << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWI2_Pos (2U) +#define EXTI_SWIER_SWI2_Msk (0x1U << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWI3_Pos (3U) +#define EXTI_SWIER_SWI3_Msk (0x1U << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWI4_Pos (4U) +#define EXTI_SWIER_SWI4_Msk (0x1U << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWI5_Pos (5U) +#define EXTI_SWIER_SWI5_Msk (0x1U << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWI6_Pos (6U) +#define EXTI_SWIER_SWI6_Msk (0x1U << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWI7_Pos (7U) +#define EXTI_SWIER_SWI7_Msk (0x1U << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWI8_Pos (8U) +#define EXTI_SWIER_SWI8_Msk (0x1U << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWI9_Pos (9U) +#define EXTI_SWIER_SWI9_Msk (0x1U << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWI10_Pos (10U) +#define EXTI_SWIER_SWI10_Msk (0x1U << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWI11_Pos (11U) +#define EXTI_SWIER_SWI11_Msk (0x1U << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWI12_Pos (12U) +#define EXTI_SWIER_SWI12_Msk (0x1U << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWI13_Pos (13U) +#define EXTI_SWIER_SWI13_Msk (0x1U << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWI14_Pos (14U) +#define EXTI_SWIER_SWI14_Msk (0x1U << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWI15_Pos (15U) +#define EXTI_SWIER_SWI15_Msk (0x1U << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWI16_Pos (16U) +#define EXTI_SWIER_SWI16_Msk (0x1U << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWI17_Pos (17U) +#define EXTI_SWIER_SWI17_Msk (0x1U << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWI19_Pos (19U) +#define EXTI_SWIER_SWI19_Msk (0x1U << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */ +#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */ +#define EXTI_SWIER_SWI20_Pos (20U) +#define EXTI_SWIER_SWI20_Msk (0x1U << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */ +#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */ +#define EXTI_SWIER_SWI21_Pos (21U) +#define EXTI_SWIER_SWI21_Msk (0x1U << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */ +#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */ +#define EXTI_SWIER_SWI22_Pos (22U) +#define EXTI_SWIER_SWI22_Msk (0x1U << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */ +#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */ /* Legacy defines */ #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0 @@ -1453,28 +2164,72 @@ typedef struct #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22 /****************** Bit definition for EXTI_PR register *********************/ -#define EXTI_PR_PIF0 ((uint32_t)0x00000001U) /*!< Pending bit 0 */ -#define EXTI_PR_PIF1 ((uint32_t)0x00000002U) /*!< Pending bit 1 */ -#define EXTI_PR_PIF2 ((uint32_t)0x00000004U) /*!< Pending bit 2 */ -#define EXTI_PR_PIF3 ((uint32_t)0x00000008U) /*!< Pending bit 3 */ -#define EXTI_PR_PIF4 ((uint32_t)0x00000010U) /*!< Pending bit 4 */ -#define EXTI_PR_PIF5 ((uint32_t)0x00000020U) /*!< Pending bit 5 */ -#define EXTI_PR_PIF6 ((uint32_t)0x00000040U) /*!< Pending bit 6 */ -#define EXTI_PR_PIF7 ((uint32_t)0x00000080U) /*!< Pending bit 7 */ -#define EXTI_PR_PIF8 ((uint32_t)0x00000100U) /*!< Pending bit 8 */ -#define EXTI_PR_PIF9 ((uint32_t)0x00000200U) /*!< Pending bit 9 */ -#define EXTI_PR_PIF10 ((uint32_t)0x00000400U) /*!< Pending bit 10 */ -#define EXTI_PR_PIF11 ((uint32_t)0x00000800U) /*!< Pending bit 11 */ -#define EXTI_PR_PIF12 ((uint32_t)0x00001000U) /*!< Pending bit 12 */ -#define EXTI_PR_PIF13 ((uint32_t)0x00002000U) /*!< Pending bit 13 */ -#define EXTI_PR_PIF14 ((uint32_t)0x00004000U) /*!< Pending bit 14 */ -#define EXTI_PR_PIF15 ((uint32_t)0x00008000U) /*!< Pending bit 15 */ -#define EXTI_PR_PIF16 ((uint32_t)0x00010000U) /*!< Pending bit 16 */ -#define EXTI_PR_PIF17 ((uint32_t)0x00020000U) /*!< Pending bit 17 */ -#define EXTI_PR_PIF19 ((uint32_t)0x00080000U) /*!< Pending bit 19 */ -#define EXTI_PR_PIF20 ((uint32_t)0x00100000U) /*!< Pending bit 20 */ -#define EXTI_PR_PIF21 ((uint32_t)0x00200000U) /*!< Pending bit 21 */ -#define EXTI_PR_PIF22 ((uint32_t)0x00400000U) /*!< Pending bit 22 */ +#define EXTI_PR_PIF0_Pos (0U) +#define EXTI_PR_PIF0_Msk (0x1U << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */ +#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */ +#define EXTI_PR_PIF1_Pos (1U) +#define EXTI_PR_PIF1_Msk (0x1U << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */ +#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */ +#define EXTI_PR_PIF2_Pos (2U) +#define EXTI_PR_PIF2_Msk (0x1U << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */ +#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */ +#define EXTI_PR_PIF3_Pos (3U) +#define EXTI_PR_PIF3_Msk (0x1U << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */ +#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */ +#define EXTI_PR_PIF4_Pos (4U) +#define EXTI_PR_PIF4_Msk (0x1U << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */ +#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */ +#define EXTI_PR_PIF5_Pos (5U) +#define EXTI_PR_PIF5_Msk (0x1U << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */ +#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */ +#define EXTI_PR_PIF6_Pos (6U) +#define EXTI_PR_PIF6_Msk (0x1U << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */ +#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */ +#define EXTI_PR_PIF7_Pos (7U) +#define EXTI_PR_PIF7_Msk (0x1U << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */ +#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */ +#define EXTI_PR_PIF8_Pos (8U) +#define EXTI_PR_PIF8_Msk (0x1U << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */ +#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */ +#define EXTI_PR_PIF9_Pos (9U) +#define EXTI_PR_PIF9_Msk (0x1U << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */ +#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */ +#define EXTI_PR_PIF10_Pos (10U) +#define EXTI_PR_PIF10_Msk (0x1U << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */ +#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */ +#define EXTI_PR_PIF11_Pos (11U) +#define EXTI_PR_PIF11_Msk (0x1U << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */ +#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */ +#define EXTI_PR_PIF12_Pos (12U) +#define EXTI_PR_PIF12_Msk (0x1U << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */ +#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */ +#define EXTI_PR_PIF13_Pos (13U) +#define EXTI_PR_PIF13_Msk (0x1U << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */ +#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */ +#define EXTI_PR_PIF14_Pos (14U) +#define EXTI_PR_PIF14_Msk (0x1U << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */ +#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */ +#define EXTI_PR_PIF15_Pos (15U) +#define EXTI_PR_PIF15_Msk (0x1U << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */ +#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */ +#define EXTI_PR_PIF16_Pos (16U) +#define EXTI_PR_PIF16_Msk (0x1U << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */ +#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */ +#define EXTI_PR_PIF17_Pos (17U) +#define EXTI_PR_PIF17_Msk (0x1U << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */ +#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */ +#define EXTI_PR_PIF19_Pos (19U) +#define EXTI_PR_PIF19_Msk (0x1U << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */ +#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */ +#define EXTI_PR_PIF20_Pos (20U) +#define EXTI_PR_PIF20_Msk (0x1U << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */ +#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */ +#define EXTI_PR_PIF21_Pos (21U) +#define EXTI_PR_PIF21_Msk (0x1U << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */ +#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */ +#define EXTI_PR_PIF22_Pos (22U) +#define EXTI_PR_PIF22_Msk (0x1U << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */ +#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */ /* Legacy defines */ #define EXTI_PR_PR0 EXTI_PR_PIF0 @@ -1507,52 +2262,118 @@ typedef struct /******************************************************************************/ /******************* Bit definition for FLASH_ACR register ******************/ -#define FLASH_ACR_LATENCY ((uint32_t)0x00000001U) /*!< LATENCY bit (Latency) */ -#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002U) /*!< Prefetch Buffer Enable */ -#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008U) /*!< Flash mode during sleep mode */ -#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010U) /*!< Flash mode during RUN mode */ -#define FLASH_ACR_DISAB_BUF ((uint32_t)0x00000020U) /*!< Disable Buffer */ -#define FLASH_ACR_PRE_READ ((uint32_t)0x00000040U) /*!< Pre-read data address */ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */ +#define FLASH_ACR_PRFTEN_Pos (1U) +#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */ +#define FLASH_ACR_SLEEP_PD_Pos (3U) +#define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */ +#define FLASH_ACR_RUN_PD_Pos (4U) +#define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */ +#define FLASH_ACR_DISAB_BUF_Pos (5U) +#define FLASH_ACR_DISAB_BUF_Msk (0x1U << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */ +#define FLASH_ACR_PRE_READ_Pos (6U) +#define FLASH_ACR_PRE_READ_Msk (0x1U << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */ +#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */ /******************* Bit definition for FLASH_PECR register ******************/ -#define FLASH_PECR_PELOCK ((uint32_t)0x00000001U) /*!< FLASH_PECR and Flash data Lock */ -#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002U) /*!< Program matrix Lock */ -#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004U) /*!< Option byte matrix Lock */ -#define FLASH_PECR_PROG ((uint32_t)0x00000008U) /*!< Program matrix selection */ -#define FLASH_PECR_DATA ((uint32_t)0x00000010U) /*!< Data matrix selection */ -#define FLASH_PECR_FIX ((uint32_t)0x00000100U) /*!< Fixed Time Data write for Word/Half Word/Byte programming */ -#define FLASH_PECR_ERASE ((uint32_t)0x00000200U) /*!< Page erasing mode */ -#define FLASH_PECR_FPRG ((uint32_t)0x00000400U) /*!< Fast Page/Half Page programming mode */ -#define FLASH_PECR_EOPIE ((uint32_t)0x00010000U) /*!< End of programming interrupt */ -#define FLASH_PECR_ERRIE ((uint32_t)0x00020000U) /*!< Error interrupt */ -#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000U) /*!< Launch the option byte loading */ -#define FLASH_PECR_HALF_ARRAY ((uint32_t)0x00080000U) /*!< Half array mode */ +#define FLASH_PECR_PELOCK_Pos (0U) +#define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */ +#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */ +#define FLASH_PECR_PRGLOCK_Pos (1U) +#define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */ +#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */ +#define FLASH_PECR_OPTLOCK_Pos (2U) +#define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */ +#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */ +#define FLASH_PECR_PROG_Pos (3U) +#define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */ +#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */ +#define FLASH_PECR_DATA_Pos (4U) +#define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */ +#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */ +#define FLASH_PECR_FIX_Pos (8U) +#define FLASH_PECR_FIX_Msk (0x1U << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */ +#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */ +#define FLASH_PECR_ERASE_Pos (9U) +#define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */ +#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */ +#define FLASH_PECR_FPRG_Pos (10U) +#define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */ +#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */ +#define FLASH_PECR_EOPIE_Pos (16U) +#define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */ +#define FLASH_PECR_ERRIE_Pos (17U) +#define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */ +#define FLASH_PECR_OBL_LAUNCH_Pos (18U) +#define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */ +#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */ +#define FLASH_PECR_HALF_ARRAY_Pos (19U) +#define FLASH_PECR_HALF_ARRAY_Msk (0x1U << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */ +#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */ /****************** Bit definition for FLASH_PDKEYR register ******************/ -#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */ +#define FLASH_PDKEYR_PDKEYR_Pos (0U) +#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */ /****************** Bit definition for FLASH_PEKEYR register ******************/ -#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */ +#define FLASH_PEKEYR_PEKEYR_Pos (0U) +#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */ /****************** Bit definition for FLASH_PRGKEYR register ******************/ -#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFFU) /*!< Program matrix Key */ +#define FLASH_PRGKEYR_PRGKEYR_Pos (0U) +#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */ /****************** Bit definition for FLASH_OPTKEYR register ******************/ -#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFFU) /*!< Option bytes matrix Key */ +#define FLASH_OPTKEYR_OPTKEYR_Pos (0U) +#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */ /****************** Bit definition for FLASH_SR register *******************/ -#define FLASH_SR_BSY ((uint32_t)0x00000001U) /*!< Busy */ -#define FLASH_SR_EOP ((uint32_t)0x00000002U) /*!< End Of Programming*/ -#define FLASH_SR_HVOFF ((uint32_t)0x00000004U) /*!< End of high voltage */ -#define FLASH_SR_READY ((uint32_t)0x00000008U) /*!< Flash ready after low power mode */ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ +#define FLASH_SR_EOP_Pos (1U) +#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000002 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/ +#define FLASH_SR_HVOFF_Pos (2U) +#define FLASH_SR_HVOFF_Msk (0x1U << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */ +#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */ +#define FLASH_SR_READY_Pos (3U) +#define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /*!< 0x00000008 */ +#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */ -#define FLASH_SR_WRPERR ((uint32_t)0x00000100U) /*!< Write protection error */ -#define FLASH_SR_PGAERR ((uint32_t)0x00000200U) /*!< Programming Alignment Error */ -#define FLASH_SR_SIZERR ((uint32_t)0x00000400U) /*!< Size error */ -#define FLASH_SR_OPTVERR ((uint32_t)0x00000800U) /*!< Option Valid error */ -#define FLASH_SR_RDERR ((uint32_t)0x00002000U) /*!< Read protected error */ -#define FLASH_SR_NOTZEROERR ((uint32_t)0x00010000U) /*!< Not Zero error */ -#define FLASH_SR_FWWERR ((uint32_t)0x00020000U) /*!< Write/Errase operation aborted */ +#define FLASH_SR_WRPERR_Pos (8U) +#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */ +#define FLASH_SR_PGAERR_Pos (9U) +#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */ +#define FLASH_SR_SIZERR_Pos (10U) +#define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ +#define FLASH_SR_OPTVERR_Pos (11U) +#define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */ +#define FLASH_SR_RDERR_Pos (13U) +#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */ +#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */ +#define FLASH_SR_NOTZEROERR_Pos (16U) +#define FLASH_SR_NOTZEROERR_Msk (0x1U << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */ +#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */ +#define FLASH_SR_FWWERR_Pos (17U) +#define FLASH_SR_FWWERR_Msk (0x1U << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */ /* Legacy defines */ #define FLASH_SR_FWWER FLASH_SR_FWWERR @@ -1560,17 +2381,35 @@ typedef struct #define FLASH_SR_ENDHV FLASH_SR_HVOFF /****************** Bit definition for FLASH_OPTR register *******************/ -#define FLASH_OPTR_RDPROT ((uint32_t)0x000000FFU) /*!< Read Protection */ -#define FLASH_OPTR_WPRMOD ((uint32_t)0x00000100U) /*!< Selection of protection mode of WPR bits */ -#define FLASH_OPTR_BOR_LEV ((uint32_t)0x000F0000U) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ -#define FLASH_OPTR_IWDG_SW ((uint32_t)0x00100000U) /*!< IWDG_SW */ -#define FLASH_OPTR_nRST_STOP ((uint32_t)0x00200000U) /*!< nRST_STOP */ -#define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00400000U) /*!< nRST_STDBY */ -#define FLASH_OPTR_USER ((uint32_t)0x00700000U) /*!< User Option Bytes */ -#define FLASH_OPTR_BOOT1 ((uint32_t)0x80000000U) /*!< BOOT1 */ +#define FLASH_OPTR_RDPROT_Pos (0U) +#define FLASH_OPTR_RDPROT_Msk (0xFFU << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */ +#define FLASH_OPTR_WPRMOD_Pos (8U) +#define FLASH_OPTR_WPRMOD_Msk (0x1U << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */ +#define FLASH_OPTR_BOR_LEV_Pos (16U) +#define FLASH_OPTR_BOR_LEV_Msk (0xFU << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ +#define FLASH_OPTR_IWDG_SW_Pos (20U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */ +#define FLASH_OPTR_nRST_STOP_Pos (21U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (22U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_USER_Pos (20U) +#define FLASH_OPTR_USER_Msk (0x7U << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */ +#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */ +#define FLASH_OPTR_BOOT1_Pos (31U) +#define FLASH_OPTR_BOOT1_Msk (0x1U << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */ /****************** Bit definition for FLASH_WRPR register ******************/ -#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFFU) /*!< Write Protection bits */ +#define FLASH_WRPR_WRP_Pos (0U) +#define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */ /******************************************************************************/ /* */ @@ -1578,299 +2417,525 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0 ((uint32_t)0x00000003U) -#define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001U) -#define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002U) -#define GPIO_MODER_MODE1 ((uint32_t)0x0000000CU) -#define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004U) -#define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008U) -#define GPIO_MODER_MODE2 ((uint32_t)0x00000030U) -#define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010U) -#define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020U) -#define GPIO_MODER_MODE3 ((uint32_t)0x000000C0U) -#define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040U) -#define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080U) -#define GPIO_MODER_MODE4 ((uint32_t)0x00000300U) -#define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100U) -#define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200U) -#define GPIO_MODER_MODE5 ((uint32_t)0x00000C00U) -#define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400U) -#define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800U) -#define GPIO_MODER_MODE6 ((uint32_t)0x00003000U) -#define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000U) -#define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000U) -#define GPIO_MODER_MODE7 ((uint32_t)0x0000C000U) -#define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000U) -#define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000U) -#define GPIO_MODER_MODE8 ((uint32_t)0x00030000U) -#define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000U) -#define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000U) -#define GPIO_MODER_MODE9 ((uint32_t)0x000C0000U) -#define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000U) -#define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000U) -#define GPIO_MODER_MODE10 ((uint32_t)0x00300000U) -#define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000U) -#define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000U) -#define GPIO_MODER_MODE11 ((uint32_t)0x00C00000U) -#define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000U) -#define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000U) -#define GPIO_MODER_MODE12 ((uint32_t)0x03000000U) -#define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000U) -#define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000U) -#define GPIO_MODER_MODE13 ((uint32_t)0x0C000000U) -#define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000U) -#define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000U) -#define GPIO_MODER_MODE14 ((uint32_t)0x30000000U) -#define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000U) -#define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000U) -#define GPIO_MODER_MODE15 ((uint32_t)0xC0000000U) -#define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000U) -#define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000U) +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_OTYPER register *****************/ -#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001U) -#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002U) -#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004U) -#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008U) -#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010U) -#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020U) -#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040U) -#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080U) -#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100U) -#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200U) -#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400U) -#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800U) -#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000U) -#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000U) -#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000U) -#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000U) +#define GPIO_OTYPER_OT_0 (0x00000001U) +#define GPIO_OTYPER_OT_1 (0x00000002U) +#define GPIO_OTYPER_OT_2 (0x00000004U) +#define GPIO_OTYPER_OT_3 (0x00000008U) +#define GPIO_OTYPER_OT_4 (0x00000010U) +#define GPIO_OTYPER_OT_5 (0x00000020U) +#define GPIO_OTYPER_OT_6 (0x00000040U) +#define GPIO_OTYPER_OT_7 (0x00000080U) +#define GPIO_OTYPER_OT_8 (0x00000100U) +#define GPIO_OTYPER_OT_9 (0x00000200U) +#define GPIO_OTYPER_OT_10 (0x00000400U) +#define GPIO_OTYPER_OT_11 (0x00000800U) +#define GPIO_OTYPER_OT_12 (0x00001000U) +#define GPIO_OTYPER_OT_13 (0x00002000U) +#define GPIO_OTYPER_OT_14 (0x00004000U) +#define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0 ((uint32_t)0x00000003U) -#define GPIO_OSPEEDER_OSPEED0_0 ((uint32_t)0x00000001U) -#define GPIO_OSPEEDER_OSPEED0_1 ((uint32_t)0x00000002U) -#define GPIO_OSPEEDER_OSPEED1 ((uint32_t)0x0000000CU) -#define GPIO_OSPEEDER_OSPEED1_0 ((uint32_t)0x00000004U) -#define GPIO_OSPEEDER_OSPEED1_1 ((uint32_t)0x00000008U) -#define GPIO_OSPEEDER_OSPEED2 ((uint32_t)0x00000030U) -#define GPIO_OSPEEDER_OSPEED2_0 ((uint32_t)0x00000010U) -#define GPIO_OSPEEDER_OSPEED2_1 ((uint32_t)0x00000020U) -#define GPIO_OSPEEDER_OSPEED3 ((uint32_t)0x000000C0U) -#define GPIO_OSPEEDER_OSPEED3_0 ((uint32_t)0x00000040U) -#define GPIO_OSPEEDER_OSPEED3_1 ((uint32_t)0x00000080U) -#define GPIO_OSPEEDER_OSPEED4 ((uint32_t)0x00000300U) -#define GPIO_OSPEEDER_OSPEED4_0 ((uint32_t)0x00000100U) -#define GPIO_OSPEEDER_OSPEED4_1 ((uint32_t)0x00000200U) -#define GPIO_OSPEEDER_OSPEED5 ((uint32_t)0x00000C00U) -#define GPIO_OSPEEDER_OSPEED5_0 ((uint32_t)0x00000400U) -#define GPIO_OSPEEDER_OSPEED5_1 ((uint32_t)0x00000800U) -#define GPIO_OSPEEDER_OSPEED6 ((uint32_t)0x00003000U) -#define GPIO_OSPEEDER_OSPEED6_0 ((uint32_t)0x00001000U) -#define GPIO_OSPEEDER_OSPEED6_1 ((uint32_t)0x00002000U) -#define GPIO_OSPEEDER_OSPEED7 ((uint32_t)0x0000C000U) -#define GPIO_OSPEEDER_OSPEED7_0 ((uint32_t)0x00004000U) -#define GPIO_OSPEEDER_OSPEED7_1 ((uint32_t)0x00008000U) -#define GPIO_OSPEEDER_OSPEED8 ((uint32_t)0x00030000U) -#define GPIO_OSPEEDER_OSPEED8_0 ((uint32_t)0x00010000U) -#define GPIO_OSPEEDER_OSPEED8_1 ((uint32_t)0x00020000U) -#define GPIO_OSPEEDER_OSPEED9 ((uint32_t)0x000C0000U) -#define GPIO_OSPEEDER_OSPEED9_0 ((uint32_t)0x00040000U) -#define GPIO_OSPEEDER_OSPEED9_1 ((uint32_t)0x00080000U) -#define GPIO_OSPEEDER_OSPEED10 ((uint32_t)0x00300000U) -#define GPIO_OSPEEDER_OSPEED10_0 ((uint32_t)0x00100000U) -#define GPIO_OSPEEDER_OSPEED10_1 ((uint32_t)0x00200000U) -#define GPIO_OSPEEDER_OSPEED11 ((uint32_t)0x00C00000U) -#define GPIO_OSPEEDER_OSPEED11_0 ((uint32_t)0x00400000U) -#define GPIO_OSPEEDER_OSPEED11_1 ((uint32_t)0x00800000U) -#define GPIO_OSPEEDER_OSPEED12 ((uint32_t)0x03000000U) -#define GPIO_OSPEEDER_OSPEED12_0 ((uint32_t)0x01000000U) -#define GPIO_OSPEEDER_OSPEED12_1 ((uint32_t)0x02000000U) -#define GPIO_OSPEEDER_OSPEED13 ((uint32_t)0x0C000000U) -#define GPIO_OSPEEDER_OSPEED13_0 ((uint32_t)0x04000000U) -#define GPIO_OSPEEDER_OSPEED13_1 ((uint32_t)0x08000000U) -#define GPIO_OSPEEDER_OSPEED14 ((uint32_t)0x30000000U) -#define GPIO_OSPEEDER_OSPEED14_0 ((uint32_t)0x10000000U) -#define GPIO_OSPEEDER_OSPEED14_1 ((uint32_t)0x20000000U) -#define GPIO_OSPEEDER_OSPEED15 ((uint32_t)0xC0000000U) -#define GPIO_OSPEEDER_OSPEED15_0 ((uint32_t)0x40000000U) -#define GPIO_OSPEEDER_OSPEED15_1 ((uint32_t)0x80000000U) +#define GPIO_OSPEEDER_OSPEED0_Pos (0U) +#define GPIO_OSPEEDER_OSPEED0_Msk (0x3U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0_0 (0x1U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDER_OSPEED0_1 (0x2U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDER_OSPEED1_Pos (2U) +#define GPIO_OSPEEDER_OSPEED1_Msk (0x3U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1_0 (0x1U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDER_OSPEED1_1 (0x2U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDER_OSPEED2_Pos (4U) +#define GPIO_OSPEEDER_OSPEED2_Msk (0x3U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2_0 (0x1U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDER_OSPEED2_1 (0x2U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDER_OSPEED3_Pos (6U) +#define GPIO_OSPEEDER_OSPEED3_Msk (0x3U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3_0 (0x1U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDER_OSPEED3_1 (0x2U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDER_OSPEED4_Pos (8U) +#define GPIO_OSPEEDER_OSPEED4_Msk (0x3U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4_0 (0x1U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDER_OSPEED4_1 (0x2U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDER_OSPEED5_Pos (10U) +#define GPIO_OSPEEDER_OSPEED5_Msk (0x3U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5_0 (0x1U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDER_OSPEED5_1 (0x2U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDER_OSPEED6_Pos (12U) +#define GPIO_OSPEEDER_OSPEED6_Msk (0x3U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6_0 (0x1U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDER_OSPEED6_1 (0x2U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDER_OSPEED7_Pos (14U) +#define GPIO_OSPEEDER_OSPEED7_Msk (0x3U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7_0 (0x1U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDER_OSPEED7_1 (0x2U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDER_OSPEED8_Pos (16U) +#define GPIO_OSPEEDER_OSPEED8_Msk (0x3U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8_0 (0x1U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDER_OSPEED8_1 (0x2U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDER_OSPEED9_Pos (18U) +#define GPIO_OSPEEDER_OSPEED9_Msk (0x3U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9_0 (0x1U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDER_OSPEED9_1 (0x2U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDER_OSPEED10_Pos (20U) +#define GPIO_OSPEEDER_OSPEED10_Msk (0x3U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10_0 (0x1U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDER_OSPEED10_1 (0x2U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDER_OSPEED11_Pos (22U) +#define GPIO_OSPEEDER_OSPEED11_Msk (0x3U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11_0 (0x1U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDER_OSPEED11_1 (0x2U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDER_OSPEED12_Pos (24U) +#define GPIO_OSPEEDER_OSPEED12_Msk (0x3U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12_0 (0x1U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDER_OSPEED12_1 (0x2U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDER_OSPEED13_Pos (26U) +#define GPIO_OSPEEDER_OSPEED13_Msk (0x3U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13_0 (0x1U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDER_OSPEED13_1 (0x2U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDER_OSPEED14_Pos (28U) +#define GPIO_OSPEEDER_OSPEED14_Msk (0x3U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14_0 (0x1U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDER_OSPEED14_1 (0x2U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDER_OSPEED15_Pos (30U) +#define GPIO_OSPEEDER_OSPEED15_Msk (0x3U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15_0 (0x1U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDER_OSPEED15_1 (0x2U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ /******************* Bit definition for GPIO_PUPDR register ******************/ -#define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003U) -#define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001U) -#define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002U) -#define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000CU) -#define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004U) -#define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008U) -#define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030U) -#define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010U) -#define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020U) -#define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0U) -#define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040U) -#define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080U) -#define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300U) -#define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100U) -#define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200U) -#define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00U) -#define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400U) -#define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800U) -#define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000U) -#define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000U) -#define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000U) -#define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000U) -#define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000U) -#define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000U) -#define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000U) -#define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000U) -#define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000U) -#define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000U) -#define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000U) -#define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000U) -#define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000U) -#define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000U) -#define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000U) -#define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000U) -#define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000U) -#define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000U) -#define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000U) -#define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000U) -#define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000U) -#define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000U) -#define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000U) -#define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000U) -#define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000U) -#define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000U) -#define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000U) -#define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000U) -#define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000U) -#define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000U) +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ /******************* Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0 ((uint32_t)0x00000001U) -#define GPIO_IDR_ID1 ((uint32_t)0x00000002U) -#define GPIO_IDR_ID2 ((uint32_t)0x00000004U) -#define GPIO_IDR_ID3 ((uint32_t)0x00000008U) -#define GPIO_IDR_ID4 ((uint32_t)0x00000010U) -#define GPIO_IDR_ID5 ((uint32_t)0x00000020U) -#define GPIO_IDR_ID6 ((uint32_t)0x00000040U) -#define GPIO_IDR_ID7 ((uint32_t)0x00000080U) -#define GPIO_IDR_ID8 ((uint32_t)0x00000100U) -#define GPIO_IDR_ID9 ((uint32_t)0x00000200U) -#define GPIO_IDR_ID10 ((uint32_t)0x00000400U) -#define GPIO_IDR_ID11 ((uint32_t)0x00000800U) -#define GPIO_IDR_ID12 ((uint32_t)0x00001000U) -#define GPIO_IDR_ID13 ((uint32_t)0x00002000U) -#define GPIO_IDR_ID14 ((uint32_t)0x00004000U) -#define GPIO_IDR_ID15 ((uint32_t)0x00008000U) +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk /****************** Bit definition for GPIO_ODR register ********************/ -#define GPIO_ODR_OD0 ((uint32_t)0x00000001U) -#define GPIO_ODR_OD1 ((uint32_t)0x00000002U) -#define GPIO_ODR_OD2 ((uint32_t)0x00000004U) -#define GPIO_ODR_OD3 ((uint32_t)0x00000008U) -#define GPIO_ODR_OD4 ((uint32_t)0x00000010U) -#define GPIO_ODR_OD5 ((uint32_t)0x00000020U) -#define GPIO_ODR_OD6 ((uint32_t)0x00000040U) -#define GPIO_ODR_OD7 ((uint32_t)0x00000080U) -#define GPIO_ODR_OD8 ((uint32_t)0x00000100U) -#define GPIO_ODR_OD9 ((uint32_t)0x00000200U) -#define GPIO_ODR_OD10 ((uint32_t)0x00000400U) -#define GPIO_ODR_OD11 ((uint32_t)0x00000800U) -#define GPIO_ODR_OD12 ((uint32_t)0x00001000U) -#define GPIO_ODR_OD13 ((uint32_t)0x00002000U) -#define GPIO_ODR_OD14 ((uint32_t)0x00004000U) -#define GPIO_ODR_OD15 ((uint32_t)0x00008000U) +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk /****************** Bit definition for GPIO_BSRR register ********************/ -#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001U) -#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002U) -#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004U) -#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008U) -#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010U) -#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020U) -#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040U) -#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080U) -#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100U) -#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200U) -#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400U) -#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800U) -#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000U) -#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000U) -#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000U) -#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000U) -#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000U) -#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000U) -#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000U) -#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000U) -#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000U) -#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000U) -#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000U) -#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000U) -#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000U) -#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000U) -#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000U) -#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000U) -#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000U) -#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000U) -#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000U) -#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000U) +#define GPIO_BSRR_BS_0 (0x00000001U) +#define GPIO_BSRR_BS_1 (0x00000002U) +#define GPIO_BSRR_BS_2 (0x00000004U) +#define GPIO_BSRR_BS_3 (0x00000008U) +#define GPIO_BSRR_BS_4 (0x00000010U) +#define GPIO_BSRR_BS_5 (0x00000020U) +#define GPIO_BSRR_BS_6 (0x00000040U) +#define GPIO_BSRR_BS_7 (0x00000080U) +#define GPIO_BSRR_BS_8 (0x00000100U) +#define GPIO_BSRR_BS_9 (0x00000200U) +#define GPIO_BSRR_BS_10 (0x00000400U) +#define GPIO_BSRR_BS_11 (0x00000800U) +#define GPIO_BSRR_BS_12 (0x00001000U) +#define GPIO_BSRR_BS_13 (0x00002000U) +#define GPIO_BSRR_BS_14 (0x00004000U) +#define GPIO_BSRR_BS_15 (0x00008000U) +#define GPIO_BSRR_BR_0 (0x00010000U) +#define GPIO_BSRR_BR_1 (0x00020000U) +#define GPIO_BSRR_BR_2 (0x00040000U) +#define GPIO_BSRR_BR_3 (0x00080000U) +#define GPIO_BSRR_BR_4 (0x00100000U) +#define GPIO_BSRR_BR_5 (0x00200000U) +#define GPIO_BSRR_BR_6 (0x00400000U) +#define GPIO_BSRR_BR_7 (0x00800000U) +#define GPIO_BSRR_BR_8 (0x01000000U) +#define GPIO_BSRR_BR_9 (0x02000000U) +#define GPIO_BSRR_BR_10 (0x04000000U) +#define GPIO_BSRR_BR_11 (0x08000000U) +#define GPIO_BSRR_BR_12 (0x10000000U) +#define GPIO_BSRR_BR_13 (0x20000000U) +#define GPIO_BSRR_BR_14 (0x40000000U) +#define GPIO_BSRR_BR_15 (0x80000000U) /****************** Bit definition for GPIO_LCKR register ********************/ -#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U) -#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U) -#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U) -#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U) -#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U) -#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U) -#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U) -#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U) -#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U) -#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U) -#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U) -#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U) -#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U) -#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U) -#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U) -#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U) -#define GPIO_LCKR_LCKK ((uint32_t)0x00010000U) +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000FU) -#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0U) -#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00U) -#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000U) -#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000U) -#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000U) -#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000U) -#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000U) +#define GPIO_AFRL_AFRL0_Pos (0U) +#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk +#define GPIO_AFRL_AFRL1_Pos (4U) +#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk +#define GPIO_AFRL_AFRL2_Pos (8U) +#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk +#define GPIO_AFRL_AFRL3_Pos (12U) +#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk +#define GPIO_AFRL_AFRL4_Pos (16U) +#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk +#define GPIO_AFRL_AFRL5_Pos (20U) +#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk +#define GPIO_AFRL_AFRL6_Pos (24U) +#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk +#define GPIO_AFRL_AFRL7_Pos (28U) +#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000FU) -#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0U) -#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00U) -#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000U) -#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000U) -#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000U) -#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000U) -#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000U) +#define GPIO_AFRH_AFRH0_Pos (0U) +#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk +#define GPIO_AFRH_AFRH1_Pos (4U) +#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk +#define GPIO_AFRH_AFRH2_Pos (8U) +#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk +#define GPIO_AFRH_AFRH3_Pos (12U) +#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk +#define GPIO_AFRH_AFRH4_Pos (16U) +#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk +#define GPIO_AFRH_AFRH5_Pos (20U) +#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk +#define GPIO_AFRH_AFRH6_Pos (24U) +#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk +#define GPIO_AFRH_AFRH7_Pos (28U) +#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk /****************** Bit definition for GPIO_BRR register *********************/ -#define GPIO_BRR_BR_0 ((uint32_t)0x00000001U) -#define GPIO_BRR_BR_1 ((uint32_t)0x00000002U) -#define GPIO_BRR_BR_2 ((uint32_t)0x00000004U) -#define GPIO_BRR_BR_3 ((uint32_t)0x00000008U) -#define GPIO_BRR_BR_4 ((uint32_t)0x00000010U) -#define GPIO_BRR_BR_5 ((uint32_t)0x00000020U) -#define GPIO_BRR_BR_6 ((uint32_t)0x00000040U) -#define GPIO_BRR_BR_7 ((uint32_t)0x00000080U) -#define GPIO_BRR_BR_8 ((uint32_t)0x00000100U) -#define GPIO_BRR_BR_9 ((uint32_t)0x00000200U) -#define GPIO_BRR_BR_10 ((uint32_t)0x00000400U) -#define GPIO_BRR_BR_11 ((uint32_t)0x00000800U) -#define GPIO_BRR_BR_12 ((uint32_t)0x00001000U) -#define GPIO_BRR_BR_13 ((uint32_t)0x00002000U) -#define GPIO_BRR_BR_14 ((uint32_t)0x00004000U) -#define GPIO_BRR_BR_15 ((uint32_t)0x00008000U) +#define GPIO_BRR_BR_0 (0x00000001U) +#define GPIO_BRR_BR_1 (0x00000002U) +#define GPIO_BRR_BR_2 (0x00000004U) +#define GPIO_BRR_BR_3 (0x00000008U) +#define GPIO_BRR_BR_4 (0x00000010U) +#define GPIO_BRR_BR_5 (0x00000020U) +#define GPIO_BRR_BR_6 (0x00000040U) +#define GPIO_BRR_BR_7 (0x00000080U) +#define GPIO_BRR_BR_8 (0x00000100U) +#define GPIO_BRR_BR_9 (0x00000200U) +#define GPIO_BRR_BR_10 (0x00000400U) +#define GPIO_BRR_BR_11 (0x00000800U) +#define GPIO_BRR_BR_12 (0x00001000U) +#define GPIO_BRR_BR_13 (0x00002000U) +#define GPIO_BRR_BR_14 (0x00004000U) +#define GPIO_BRR_BR_15 (0x00008000U) /******************************************************************************/ /* */ @@ -1879,110 +2944,276 @@ typedef struct /******************************************************************************/ /******************* Bit definition for I2C_CR1 register *******************/ -#define I2C_CR1_PE ((uint32_t)0x00000001U) /*!< Peripheral enable */ -#define I2C_CR1_TXIE ((uint32_t)0x00000002U) /*!< TX interrupt enable */ -#define I2C_CR1_RXIE ((uint32_t)0x00000004U) /*!< RX interrupt enable */ -#define I2C_CR1_ADDRIE ((uint32_t)0x00000008U) /*!< Address match interrupt enable */ -#define I2C_CR1_NACKIE ((uint32_t)0x00000010U) /*!< NACK received interrupt enable */ -#define I2C_CR1_STOPIE ((uint32_t)0x00000020U) /*!< STOP detection interrupt enable */ -#define I2C_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transfer complete interrupt enable */ -#define I2C_CR1_ERRIE ((uint32_t)0x00000080U) /*!< Errors interrupt enable */ -#define I2C_CR1_DNF ((uint32_t)0x00000F00U) /*!< Digital noise filter */ -#define I2C_CR1_ANFOFF ((uint32_t)0x00001000U) /*!< Analog noise filter OFF */ -#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000U) /*!< DMA transmission requests enable */ -#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000U) /*!< DMA reception requests enable */ -#define I2C_CR1_SBC ((uint32_t)0x00010000U) /*!< Slave byte control */ -#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000U) /*!< Clock stretching disable */ -#define I2C_CR1_WUPEN ((uint32_t)0x00040000U) /*!< Wakeup from STOP enable */ -#define I2C_CR1_GCEN ((uint32_t)0x00080000U) /*!< General call enable */ -#define I2C_CR1_SMBHEN ((uint32_t)0x00100000U) /*!< SMBus host address enable */ -#define I2C_CR1_SMBDEN ((uint32_t)0x00200000U) /*!< SMBus device default address enable */ -#define I2C_CR1_ALERTEN ((uint32_t)0x00400000U) /*!< SMBus alert enable */ -#define I2C_CR1_PECEN ((uint32_t)0x00800000U) /*!< PEC enable */ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ /****************** Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_SADD ((uint32_t)0x000003FFU) /*!< Slave address (master mode) */ -#define I2C_CR2_RD_WRN ((uint32_t)0x00000400U) /*!< Transfer direction (master mode) */ -#define I2C_CR2_ADD10 ((uint32_t)0x00000800U) /*!< 10-bit addressing mode (master mode) */ -#define I2C_CR2_HEAD10R ((uint32_t)0x00001000U) /*!< 10-bit address header only read direction (master mode) */ -#define I2C_CR2_START ((uint32_t)0x00002000U) /*!< START generation */ -#define I2C_CR2_STOP ((uint32_t)0x00004000U) /*!< STOP generation (master mode) */ -#define I2C_CR2_NACK ((uint32_t)0x00008000U) /*!< NACK generation (slave mode) */ -#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000U) /*!< Number of bytes */ -#define I2C_CR2_RELOAD ((uint32_t)0x01000000U) /*!< NBYTES reload mode */ -#define I2C_CR2_AUTOEND ((uint32_t)0x02000000U) /*!< Automatic end mode (master mode) */ -#define I2C_CR2_PECBYTE ((uint32_t)0x04000000U) /*!< Packet error checking byte */ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ /******************* Bit definition for I2C_OAR1 register ******************/ -#define I2C_OAR1_OA1 ((uint32_t)0x000003FFU) /*!< Interface own address 1 */ -#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400U) /*!< Own address 1 10-bit mode */ -#define I2C_OAR1_OA1EN ((uint32_t)0x00008000U) /*!< Own address 1 enable */ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ /******************* Bit definition for I2C_OAR2 register ******************/ -#define I2C_OAR2_OA2 ((uint32_t)0x000000FEU) /*!< Interface own address 2 */ -#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700U) /*!< Own address 2 masks */ -#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000U) /*!< No mask */ -#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100U) /*!< OA2[1] is masked, Only OA2[7:2] are compared */ -#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200U) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ -#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300U) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ -#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400U) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ -#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500U) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ -#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600U) /*!< OA2[6:1] is masked, Only OA2[7] are compared */ -#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700U) /*!< OA2[7:1] is masked, No comparison is done */ -#define I2C_OAR2_OA2EN ((uint32_t)0x00008000U) /*!< Own address 2 enable */ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ /******************* Bit definition for I2C_TIMINGR register *******************/ -#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FFU) /*!< SCL low period (master mode) */ -#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00U) /*!< SCL high period (master mode) */ -#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000U) /*!< Data hold time */ -#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000U) /*!< Data setup time */ -#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000U) /*!< Timings prescaler */ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ /******************* Bit definition for I2C_TIMEOUTR register *******************/ -#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFFU) /*!< Bus timeout A */ -#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000U) /*!< Idle clock timeout detection */ -#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000U) /*!< Clock timeout enable */ -#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000U) /*!< Bus timeout B*/ -#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000U) /*!< Extended clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ /****************** Bit definition for I2C_ISR register *********************/ -#define I2C_ISR_TXE ((uint32_t)0x00000001U) /*!< Transmit data register empty */ -#define I2C_ISR_TXIS ((uint32_t)0x00000002U) /*!< Transmit interrupt status */ -#define I2C_ISR_RXNE ((uint32_t)0x00000004U) /*!< Receive data register not empty */ -#define I2C_ISR_ADDR ((uint32_t)0x00000008U) /*!< Address matched (slave mode)*/ -#define I2C_ISR_NACKF ((uint32_t)0x00000010U) /*!< NACK received flag */ -#define I2C_ISR_STOPF ((uint32_t)0x00000020U) /*!< STOP detection flag */ -#define I2C_ISR_TC ((uint32_t)0x00000040U) /*!< Transfer complete (master mode) */ -#define I2C_ISR_TCR ((uint32_t)0x00000080U) /*!< Transfer complete reload */ -#define I2C_ISR_BERR ((uint32_t)0x00000100U) /*!< Bus error */ -#define I2C_ISR_ARLO ((uint32_t)0x00000200U) /*!< Arbitration lost */ -#define I2C_ISR_OVR ((uint32_t)0x00000400U) /*!< Overrun/Underrun */ -#define I2C_ISR_PECERR ((uint32_t)0x00000800U) /*!< PEC error in reception */ -#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000U) /*!< Timeout or Tlow detection flag */ -#define I2C_ISR_ALERT ((uint32_t)0x00002000U) /*!< SMBus alert */ -#define I2C_ISR_BUSY ((uint32_t)0x00008000U) /*!< Bus busy */ -#define I2C_ISR_DIR ((uint32_t)0x00010000U) /*!< Transfer direction (slave mode) */ -#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000U) /*!< Address match code (slave mode) */ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ /****************** Bit definition for I2C_ICR register *********************/ -#define I2C_ICR_ADDRCF ((uint32_t)0x00000008U) /*!< Address matched clear flag */ -#define I2C_ICR_NACKCF ((uint32_t)0x00000010U) /*!< NACK clear flag */ -#define I2C_ICR_STOPCF ((uint32_t)0x00000020U) /*!< STOP detection clear flag */ -#define I2C_ICR_BERRCF ((uint32_t)0x00000100U) /*!< Bus error clear flag */ -#define I2C_ICR_ARLOCF ((uint32_t)0x00000200U) /*!< Arbitration lost clear flag */ -#define I2C_ICR_OVRCF ((uint32_t)0x00000400U) /*!< Overrun/Underrun clear flag */ -#define I2C_ICR_PECCF ((uint32_t)0x00000800U) /*!< PAC error clear flag */ -#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000U) /*!< Timeout clear flag */ -#define I2C_ICR_ALERTCF ((uint32_t)0x00002000U) /*!< Alert clear flag */ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ /****************** Bit definition for I2C_PECR register *********************/ -#define I2C_PECR_PEC ((uint32_t)0x000000FFU) /*!< PEC register */ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ /****************** Bit definition for I2C_RXDR register *********************/ -#define I2C_RXDR_RXDATA ((uint32_t)0x000000FFU) /*!< 8-bit receive data */ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ /****************** Bit definition for I2C_TXDR register *********************/ -#define I2C_TXDR_TXDATA ((uint32_t)0x000000FFU) /*!< 8-bit transmit data */ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ /******************************************************************************/ /* */ @@ -1990,24 +3221,38 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_KR_KEY ((uint32_t)0x0000FFFFU) /*!< Key value (write only, read 0000h) */ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ /******************* Bit definition for IWDG_PR register ********************/ -#define IWDG_PR_PR ((uint32_t)0x00000007U) /*!< PR[2:0] (Prescaler divider) */ -#define IWDG_PR_PR_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ -#define IWDG_PR_PR_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ -#define IWDG_PR_PR_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define IWDG_PR_PR_Pos (0U) +#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ +#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */ +#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */ +#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */ /******************* Bit definition for IWDG_RLR register *******************/ -#define IWDG_RLR_RL ((uint32_t)0x00000FFFU) /*!< Watchdog counter reload value */ +#define IWDG_RLR_RL_Pos (0U) +#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ +#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ /******************* Bit definition for IWDG_SR register ********************/ -#define IWDG_SR_PVU ((uint32_t)0x00000001U) /*!< Watchdog prescaler value update */ -#define IWDG_SR_RVU ((uint32_t)0x00000002U) /*!< Watchdog counter reload value update */ -#define IWDG_SR_WVU ((uint32_t)0x00000004U) /*!< Watchdog counter window value update */ +#define IWDG_SR_PVU_Pos (0U) +#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ +#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ +#define IWDG_SR_RVU_Pos (1U) +#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ +#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ +#define IWDG_SR_WVU_Pos (2U) +#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ +#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ /******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_WINR_WIN ((uint32_t)0x00000FFFU) /*!< Watchdog counter window value */ +#define IWDG_WINR_WIN_Pos (0U) +#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ +#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ /******************************************************************************/ /* */ @@ -2016,66 +3261,118 @@ typedef struct /******************************************************************************/ /******************* Bit definition for LCD_CR register *********************/ -#define LCD_CR_LCDEN ((uint32_t)0x00000001U) /*!< LCD Enable Bit */ -#define LCD_CR_VSEL ((uint32_t)0x00000002U) /*!< Voltage source selector Bit */ +#define LCD_CR_LCDEN_Pos (0U) +#define LCD_CR_LCDEN_Msk (0x1U << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */ +#define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */ +#define LCD_CR_VSEL_Pos (1U) +#define LCD_CR_VSEL_Msk (0x1U << LCD_CR_VSEL_Pos) /*!< 0x00000002 */ +#define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */ -#define LCD_CR_DUTY ((uint32_t)0x0000001CU) /*!< DUTY[2:0] bits (Duty selector) */ -#define LCD_CR_DUTY_0 ((uint32_t)0x00000004U) /*!< Duty selector Bit 0 */ -#define LCD_CR_DUTY_1 ((uint32_t)0x00000008U) /*!< Duty selector Bit 1 */ -#define LCD_CR_DUTY_2 ((uint32_t)0x00000010U) /*!< Duty selector Bit 2 */ +#define LCD_CR_DUTY_Pos (2U) +#define LCD_CR_DUTY_Msk (0x7U << LCD_CR_DUTY_Pos) /*!< 0x0000001C */ +#define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */ +#define LCD_CR_DUTY_0 (0x1U << LCD_CR_DUTY_Pos) /*!< 0x00000004 */ +#define LCD_CR_DUTY_1 (0x2U << LCD_CR_DUTY_Pos) /*!< 0x00000008 */ +#define LCD_CR_DUTY_2 (0x4U << LCD_CR_DUTY_Pos) /*!< 0x00000010 */ -#define LCD_CR_BIAS ((uint32_t)0x00000060U) /*!< BIAS[1:0] bits (Bias selector) */ -#define LCD_CR_BIAS_0 ((uint32_t)0x00000020U) /*!< Bias selector Bit 0 */ -#define LCD_CR_BIAS_1 ((uint32_t)0x00000040U) /*!< Bias selector Bit 1 */ +#define LCD_CR_BIAS_Pos (5U) +#define LCD_CR_BIAS_Msk (0x3U << LCD_CR_BIAS_Pos) /*!< 0x00000060 */ +#define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */ +#define LCD_CR_BIAS_0 (0x1U << LCD_CR_BIAS_Pos) /*!< 0x00000020 */ +#define LCD_CR_BIAS_1 (0x2U << LCD_CR_BIAS_Pos) /*!< 0x00000040 */ -#define LCD_CR_MUX_SEG ((uint32_t)0x00000080U) /*!< Mux Segment Enable Bit */ +#define LCD_CR_MUX_SEG_Pos (7U) +#define LCD_CR_MUX_SEG_Msk (0x1U << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */ +#define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */ + +#define LCD_CR_BUFEN_Pos (8U) +#define LCD_CR_BUFEN_Msk (0x1U << LCD_CR_BUFEN_Pos) /*!< 0x00000100 */ +#define LCD_CR_BUFEN LCD_CR_BUFEN_Msk /*!< Voltage output buffer enable Bit */ /******************* Bit definition for LCD_FCR register ********************/ -#define LCD_FCR_HD ((uint32_t)0x00000001U) /*!< High Drive Enable Bit */ -#define LCD_FCR_SOFIE ((uint32_t)0x00000002U) /*!< Start of Frame Interrupt Enable Bit */ -#define LCD_FCR_UDDIE ((uint32_t)0x00000008U) /*!< Update Display Done Interrupt Enable Bit */ +#define LCD_FCR_HD_Pos (0U) +#define LCD_FCR_HD_Msk (0x1U << LCD_FCR_HD_Pos) /*!< 0x00000001 */ +#define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */ +#define LCD_FCR_SOFIE_Pos (1U) +#define LCD_FCR_SOFIE_Msk (0x1U << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */ +#define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */ +#define LCD_FCR_UDDIE_Pos (3U) +#define LCD_FCR_UDDIE_Msk (0x1U << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */ +#define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */ -#define LCD_FCR_PON ((uint32_t)0x00000070U) /*!< PON[2:0] bits (Puls ON Duration) */ -#define LCD_FCR_PON_0 ((uint32_t)0x00000010U) /*!< Bit 0 */ -#define LCD_FCR_PON_1 ((uint32_t)0x00000020U) /*!< Bit 1 */ -#define LCD_FCR_PON_2 ((uint32_t)0x00000040U) /*!< Bit 2 */ +#define LCD_FCR_PON_Pos (4U) +#define LCD_FCR_PON_Msk (0x7U << LCD_FCR_PON_Pos) /*!< 0x00000070 */ +#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */ +#define LCD_FCR_PON_0 (0x1U << LCD_FCR_PON_Pos) /*!< 0x00000010 */ +#define LCD_FCR_PON_1 (0x2U << LCD_FCR_PON_Pos) /*!< 0x00000020 */ +#define LCD_FCR_PON_2 (0x4U << LCD_FCR_PON_Pos) /*!< 0x00000040 */ -#define LCD_FCR_DEAD ((uint32_t)0x00000380U) /*!< DEAD[2:0] bits (DEAD Time) */ -#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080U) /*!< Bit 0 */ -#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100U) /*!< Bit 1 */ -#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200U) /*!< Bit 2 */ +#define LCD_FCR_DEAD_Pos (7U) +#define LCD_FCR_DEAD_Msk (0x7U << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */ +#define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */ +#define LCD_FCR_DEAD_0 (0x1U << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */ +#define LCD_FCR_DEAD_1 (0x2U << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */ +#define LCD_FCR_DEAD_2 (0x4U << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */ -#define LCD_FCR_CC ((uint32_t)0x00001C00U) /*!< CC[2:0] bits (Contrast Control) */ -#define LCD_FCR_CC_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ -#define LCD_FCR_CC_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ -#define LCD_FCR_CC_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define LCD_FCR_CC_Pos (10U) +#define LCD_FCR_CC_Msk (0x7U << LCD_FCR_CC_Pos) /*!< 0x00001C00 */ +#define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */ +#define LCD_FCR_CC_0 (0x1U << LCD_FCR_CC_Pos) /*!< 0x00000400 */ +#define LCD_FCR_CC_1 (0x2U << LCD_FCR_CC_Pos) /*!< 0x00000800 */ +#define LCD_FCR_CC_2 (0x4U << LCD_FCR_CC_Pos) /*!< 0x00001000 */ -#define LCD_FCR_BLINKF ((uint32_t)0x0000E000U) /*!< BLINKF[2:0] bits (Blink Frequency) */ -#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000U) /*!< Bit 0 */ -#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000U) /*!< Bit 1 */ -#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000U) /*!< Bit 2 */ +#define LCD_FCR_BLINKF_Pos (13U) +#define LCD_FCR_BLINKF_Msk (0x7U << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */ +#define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */ +#define LCD_FCR_BLINKF_0 (0x1U << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */ +#define LCD_FCR_BLINKF_1 (0x2U << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */ +#define LCD_FCR_BLINKF_2 (0x4U << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */ -#define LCD_FCR_BLINK ((uint32_t)0x00030000U) /*!< BLINK[1:0] bits (Blink Enable) */ -#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ -#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ +#define LCD_FCR_BLINK_Pos (16U) +#define LCD_FCR_BLINK_Msk (0x3U << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */ +#define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */ +#define LCD_FCR_BLINK_0 (0x1U << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */ +#define LCD_FCR_BLINK_1 (0x2U << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */ -#define LCD_FCR_DIV ((uint32_t)0x003C0000U) /*!< DIV[3:0] bits (Divider) */ -#define LCD_FCR_PS ((uint32_t)0x03C00000U) /*!< PS[3:0] bits (Prescaler) */ +#define LCD_FCR_DIV_Pos (18U) +#define LCD_FCR_DIV_Msk (0xFU << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */ +#define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */ +#define LCD_FCR_PS_Pos (22U) +#define LCD_FCR_PS_Msk (0xFU << LCD_FCR_PS_Pos) /*!< 0x03C00000 */ +#define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */ /******************* Bit definition for LCD_SR register *********************/ -#define LCD_SR_ENS ((uint32_t)0x00000001U) /*!< LCD Enabled Bit */ -#define LCD_SR_SOF ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Bit */ -#define LCD_SR_UDR ((uint32_t)0x00000004U) /*!< Update Display Request Bit */ -#define LCD_SR_UDD ((uint32_t)0x00000008U) /*!< Update Display Done Flag Bit */ -#define LCD_SR_RDY ((uint32_t)0x00000010U) /*!< Ready Flag Bit */ -#define LCD_SR_FCRSR ((uint32_t)0x00000020U) /*!< LCD FCR Register Synchronization Flag Bit */ +#define LCD_SR_ENS_Pos (0U) +#define LCD_SR_ENS_Msk (0x1U << LCD_SR_ENS_Pos) /*!< 0x00000001 */ +#define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */ +#define LCD_SR_SOF_Pos (1U) +#define LCD_SR_SOF_Msk (0x1U << LCD_SR_SOF_Pos) /*!< 0x00000002 */ +#define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */ +#define LCD_SR_UDR_Pos (2U) +#define LCD_SR_UDR_Msk (0x1U << LCD_SR_UDR_Pos) /*!< 0x00000004 */ +#define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */ +#define LCD_SR_UDD_Pos (3U) +#define LCD_SR_UDD_Msk (0x1U << LCD_SR_UDD_Pos) /*!< 0x00000008 */ +#define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */ +#define LCD_SR_RDY_Pos (4U) +#define LCD_SR_RDY_Msk (0x1U << LCD_SR_RDY_Pos) /*!< 0x00000010 */ +#define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */ +#define LCD_SR_FCRSR_Pos (5U) +#define LCD_SR_FCRSR_Msk (0x1U << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */ +#define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */ /******************* Bit definition for LCD_CLR register ********************/ -#define LCD_CLR_SOFC ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Clear Bit */ -#define LCD_CLR_UDDC ((uint32_t)0x00000008U) /*!< Update Display Done Flag Clear Bit */ +#define LCD_CLR_SOFC_Pos (1U) +#define LCD_CLR_SOFC_Msk (0x1U << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */ +#define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */ +#define LCD_CLR_UDDC_Pos (3U) +#define LCD_CLR_UDDC_Msk (0x1U << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */ +#define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */ /******************* Bit definition for LCD_RAM register ********************/ -#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFFU) /*!< Segment Data Bits */ +#define LCD_RAM_SEGMENT_DATA_Pos (0U) +#define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */ +#define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */ /******************************************************************************/ /* */ @@ -2083,81 +3380,161 @@ typedef struct /* */ /******************************************************************************/ /****************** Bit definition for LPTIM_ISR register *******************/ -#define LPTIM_ISR_CMPM ((uint32_t)0x00000001U) /*!< Compare match */ -#define LPTIM_ISR_ARRM ((uint32_t)0x00000002U) /*!< Autoreload match */ -#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004U) /*!< External trigger edge event */ -#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008U) /*!< Compare register update OK */ -#define LPTIM_ISR_ARROK ((uint32_t)0x00000010U) /*!< Autoreload register update OK */ -#define LPTIM_ISR_UP ((uint32_t)0x00000020U) /*!< Counter direction change down to up */ -#define LPTIM_ISR_DOWN ((uint32_t)0x00000040U) /*!< Counter direction change up to down */ +#define LPTIM_ISR_CMPM_Pos (0U) +#define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */ +#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */ +#define LPTIM_ISR_ARRM_Pos (1U) +#define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */ +#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */ +#define LPTIM_ISR_EXTTRIG_Pos (2U) +#define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */ +#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */ +#define LPTIM_ISR_CMPOK_Pos (3U) +#define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */ +#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */ +#define LPTIM_ISR_ARROK_Pos (4U) +#define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */ +#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */ +#define LPTIM_ISR_UP_Pos (5U) +#define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */ +#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */ +#define LPTIM_ISR_DOWN_Pos (6U) +#define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */ +#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */ /****************** Bit definition for LPTIM_ICR register *******************/ -#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001U) /*!< Compare match Clear Flag */ -#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002U) /*!< Autoreload match Clear Flag */ -#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004U) /*!< External trigger edge event Clear Flag */ -#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008U) /*!< Compare register update OK Clear Flag */ -#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010U) /*!< Autoreload register update OK Clear Flag */ -#define LPTIM_ICR_UPCF ((uint32_t)0x00000020U) /*!< Counter direction change down to up Clear Flag */ -#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040U) /*!< Counter direction change up to down Clear Flag */ +#define LPTIM_ICR_CMPMCF_Pos (0U) +#define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */ +#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */ +#define LPTIM_ICR_ARRMCF_Pos (1U) +#define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */ +#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */ +#define LPTIM_ICR_EXTTRIGCF_Pos (2U) +#define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */ +#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */ +#define LPTIM_ICR_CMPOKCF_Pos (3U) +#define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */ +#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */ +#define LPTIM_ICR_ARROKCF_Pos (4U) +#define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */ +#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */ +#define LPTIM_ICR_UPCF_Pos (5U) +#define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */ +#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */ +#define LPTIM_ICR_DOWNCF_Pos (6U) +#define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */ +#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */ /****************** Bit definition for LPTIM_IER register ********************/ -#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001U) /*!< Compare match Interrupt Enable */ -#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002U) /*!< Autoreload match Interrupt Enable */ -#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004U) /*!< External trigger edge event Interrupt Enable */ -#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008U) /*!< Compare register update OK Interrupt Enable */ -#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010U) /*!< Autoreload register update OK Interrupt Enable */ -#define LPTIM_IER_UPIE ((uint32_t)0x00000020U) /*!< Counter direction change down to up Interrupt Enable */ -#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040U) /*!< Counter direction change up to down Interrupt Enable */ +#define LPTIM_IER_CMPMIE_Pos (0U) +#define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */ +#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */ +#define LPTIM_IER_ARRMIE_Pos (1U) +#define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */ +#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */ +#define LPTIM_IER_EXTTRIGIE_Pos (2U) +#define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */ +#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */ +#define LPTIM_IER_CMPOKIE_Pos (3U) +#define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */ +#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */ +#define LPTIM_IER_ARROKIE_Pos (4U) +#define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */ +#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */ +#define LPTIM_IER_UPIE_Pos (5U) +#define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */ +#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */ +#define LPTIM_IER_DOWNIE_Pos (6U) +#define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */ +#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */ /****************** Bit definition for LPTIM_CFGR register *******************/ -#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001U) /*!< Clock selector */ +#define LPTIM_CFGR_CKSEL_Pos (0U) +#define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */ +#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */ -#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006U) /*!< CKPOL[1:0] bits (Clock polarity) */ -#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002U) /*!< Bit 0 */ -#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004U) /*!< Bit 1 */ +#define LPTIM_CFGR_CKPOL_Pos (1U) +#define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */ +#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */ +#define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */ +#define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */ -#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018U) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ -#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ +#define LPTIM_CFGR_CKFLT_Pos (3U) +#define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */ +#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ +#define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */ +#define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */ -#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0U) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ -#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ -#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ +#define LPTIM_CFGR_TRGFLT_Pos (6U) +#define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */ +#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ +#define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */ +#define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */ -#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00U) /*!< PRESC[2:0] bits (Clock prescaler) */ -#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200U) /*!< Bit 0 */ -#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400U) /*!< Bit 1 */ -#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800U) /*!< Bit 2 */ +#define LPTIM_CFGR_PRESC_Pos (9U) +#define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */ +#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */ +#define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */ +#define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */ +#define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */ -#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000U) /*!< TRIGSEL[2:0]] bits (Trigger selector) */ -#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000U) /*!< Bit 0 */ -#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000U) /*!< Bit 1 */ -#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000U) /*!< Bit 2 */ +#define LPTIM_CFGR_TRIGSEL_Pos (13U) +#define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */ +#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */ +#define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */ +#define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */ +#define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */ -#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000U) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ -#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000U) /*!< Bit 0 */ -#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000U) /*!< Bit 1 */ +#define LPTIM_CFGR_TRIGEN_Pos (17U) +#define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */ +#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ +#define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */ +#define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */ -#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000U) /*!< Timout enable */ -#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000U) /*!< Waveform shape */ -#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000U) /*!< Waveform shape polarity */ -#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000U) /*!< Reg update mode */ -#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000U) /*!< Counter mode enable */ -#define LPTIM_CFGR_ENC ((uint32_t)0x01000000U) /*!< Encoder mode enable */ +#define LPTIM_CFGR_TIMOUT_Pos (19U) +#define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */ +#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */ +#define LPTIM_CFGR_WAVE_Pos (20U) +#define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */ +#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */ +#define LPTIM_CFGR_WAVPOL_Pos (21U) +#define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */ +#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */ +#define LPTIM_CFGR_PRELOAD_Pos (22U) +#define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */ +#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */ +#define LPTIM_CFGR_COUNTMODE_Pos (23U) +#define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */ +#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */ +#define LPTIM_CFGR_ENC_Pos (24U) +#define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */ +#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */ /****************** Bit definition for LPTIM_CR register ********************/ -#define LPTIM_CR_ENABLE ((uint32_t)0x00000001U) /*!< LPTIMer enable */ -#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002U) /*!< Timer start in single mode */ -#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004U) /*!< Timer start in continuous mode */ +#define LPTIM_CR_ENABLE_Pos (0U) +#define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */ +#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */ +#define LPTIM_CR_SNGSTRT_Pos (1U) +#define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */ +#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */ +#define LPTIM_CR_CNTSTRT_Pos (2U) +#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */ +#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */ /****************** Bit definition for LPTIM_CMP register *******************/ -#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFFU) /*!< Compare register */ +#define LPTIM_CMP_CMP_Pos (0U) +#define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */ +#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */ /****************** Bit definition for LPTIM_ARR register *******************/ -#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!< Auto reload register */ +#define LPTIM_ARR_ARR_Pos (0U) +#define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */ +#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */ /****************** Bit definition for LPTIM_CNT register *******************/ -#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!< Counter register */ +#define LPTIM_CNT_CNT_Pos (0U) +#define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */ +#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */ /******************************************************************************/ /* */ @@ -2166,17 +3543,35 @@ typedef struct /******************************************************************************/ /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */ -#define FW_CSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Code Segment Start Address */ -#define FW_CSL_LENG ((uint32_t)0x003FFF00U) /*!< Code Segment Length */ -#define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Non Volatile Dat Segment Start Address */ -#define FW_NVDSL_LENG ((uint32_t)0x003FFF00U) /*!< Non Volatile Data Segment Length */ -#define FW_VDSSA_ADD ((uint32_t)0x0000FFC0U) /*!< Volatile Data Segment Start Address */ -#define FW_VDSL_LENG ((uint32_t)0x0000FFC0U) /*!< Volatile Data Segment Length */ +#define FW_CSSA_ADD_Pos (8U) +#define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */ +#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */ +#define FW_CSL_LENG_Pos (8U) +#define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */ +#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */ +#define FW_NVDSSA_ADD_Pos (8U) +#define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */ +#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */ +#define FW_NVDSL_LENG_Pos (8U) +#define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */ +#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */ +#define FW_VDSSA_ADD_Pos (6U) +#define FW_VDSSA_ADD_Msk (0x3FFU << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */ +#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */ +#define FW_VDSL_LENG_Pos (6U) +#define FW_VDSL_LENG_Msk (0x3FFU << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */ +#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */ /**************************Bit definition for CR register *********************/ -#define FW_CR_FPA ((uint32_t)0x00000001U) /*!< Firewall Pre Arm*/ -#define FW_CR_VDS ((uint32_t)0x00000002U) /*!< Volatile Data Sharing*/ -#define FW_CR_VDE ((uint32_t)0x00000004U) /*!< Volatile Data Execution*/ +#define FW_CR_FPA_Pos (0U) +#define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */ +#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/ +#define FW_CR_VDS_Pos (1U) +#define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */ +#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/ +#define FW_CR_VDE_Pos (2U) +#define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */ +#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/ /******************************************************************************/ /* */ @@ -2184,48 +3579,90 @@ typedef struct /* */ /******************************************************************************/ -/******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPSDSR ((uint32_t)0x00000001U) /*!< Low-power deepsleep/sleep/low power run */ -#define PWR_CR_PDDS ((uint32_t)0x00000002U) /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF ((uint32_t)0x00000004U) /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF ((uint32_t)0x00000008U) /*!< Clear Standby Flag */ -#define PWR_CR_PVDE ((uint32_t)0x00000010U) /*!< Power Voltage Detector Enable */ +#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */ -#define PWR_CR_PLS ((uint32_t)0x000000E0U) /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ -#define PWR_CR_PLS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ -#define PWR_CR_PLS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPSDSR_Pos (0U) +#define PWR_CR_LPSDSR_Msk (0x1U << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */ +#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */ +#define PWR_CR_PDDS_Pos (1U) +#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ +#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF_Pos (2U) +#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ +#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF_Pos (3U) +#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ +#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ +#define PWR_CR_PVDE_Pos (4U) +#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS_Pos (5U) +#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ +#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ +#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ +#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ /*!< PVD level configuration */ -#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000U) /*!< PVD level 0 */ -#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020U) /*!< PVD level 1 */ -#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040U) /*!< PVD level 2 */ -#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060U) /*!< PVD level 3 */ -#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080U) /*!< PVD level 4 */ -#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0U) /*!< PVD level 5 */ -#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0U) /*!< PVD level 6 */ -#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0U) /*!< PVD level 7 */ +#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ +#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */ +#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */ +#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */ +#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */ +#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */ +#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */ +#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */ -#define PWR_CR_DBP ((uint32_t)0x00000100U) /*!< Disable Backup Domain write protection */ -#define PWR_CR_ULP ((uint32_t)0x00000200U) /*!< Ultra Low Power mode */ -#define PWR_CR_FWU ((uint32_t)0x00000400U) /*!< Fast wakeup */ +#define PWR_CR_DBP_Pos (8U) +#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ +#define PWR_CR_ULP_Pos (9U) +#define PWR_CR_ULP_Msk (0x1U << PWR_CR_ULP_Pos) /*!< 0x00000200 */ +#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */ +#define PWR_CR_FWU_Pos (10U) +#define PWR_CR_FWU_Msk (0x1U << PWR_CR_FWU_Pos) /*!< 0x00000400 */ +#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */ -#define PWR_CR_VOS ((uint32_t)0x00001800U) /*!< VOS[1:0] bits (Voltage scaling range selection) */ -#define PWR_CR_VOS_0 ((uint32_t)0x00000800U) /*!< Bit 0 */ -#define PWR_CR_VOS_1 ((uint32_t)0x00001000U) /*!< Bit 1 */ -#define PWR_CR_DSEEKOFF ((uint32_t)0x00002000U) /*!< Deep Sleep mode with EEPROM kept Off */ -#define PWR_CR_LPRUN ((uint32_t)0x00004000U) /*!< Low power run mode */ +#define PWR_CR_VOS_Pos (11U) +#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x00001800 */ +#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */ +#define PWR_CR_VOS_0 (0x1U << PWR_CR_VOS_Pos) /*!< 0x00000800 */ +#define PWR_CR_VOS_1 (0x2U << PWR_CR_VOS_Pos) /*!< 0x00001000 */ +#define PWR_CR_DSEEKOFF_Pos (13U) +#define PWR_CR_DSEEKOFF_Msk (0x1U << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */ +#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */ +#define PWR_CR_LPRUN_Pos (14U) +#define PWR_CR_LPRUN_Msk (0x1U << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */ +#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */ /******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint32_t)0x00000001U) /*!< Wakeup Flag */ -#define PWR_CSR_SBF ((uint32_t)0x00000002U) /*!< Standby Flag */ -#define PWR_CSR_PVDO ((uint32_t)0x00000004U) /*!< PVD Output */ -#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008U) /*!< Internal voltage reference (VREFINT) ready flag */ -#define PWR_CSR_VOSF ((uint32_t)0x00000010U) /*!< Voltage Scaling select flag */ -#define PWR_CSR_REGLPF ((uint32_t)0x00000020U) /*!< Regulator LP flag */ +#define PWR_CSR_WUF_Pos (0U) +#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ +#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ +#define PWR_CSR_SBF_Pos (1U) +#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ +#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ +#define PWR_CSR_PVDO_Pos (2U) +#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ +#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ +#define PWR_CSR_VREFINTRDYF_Pos (3U) +#define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */ +#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */ +#define PWR_CSR_VOSF_Pos (4U) +#define PWR_CSR_VOSF_Msk (0x1U << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */ +#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */ +#define PWR_CSR_REGLPF_Pos (5U) +#define PWR_CSR_REGLPF_Msk (0x1U << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */ +#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */ -#define PWR_CSR_EWUP1 ((uint32_t)0x00000100U) /*!< Enable WKUP pin 1 */ -#define PWR_CSR_EWUP2 ((uint32_t)0x00000200U) /*!< Enable WKUP pin 2 */ +#define PWR_CSR_EWUP1_Pos (8U) +#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ +#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ +#define PWR_CSR_EWUP2_Pos (9U) +#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ +#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ /******************************************************************************/ /* */ @@ -2233,173 +3670,274 @@ typedef struct /* */ /******************************************************************************/ +#define RCC_HSI48_SUPPORT /*!< HSI48 feature support */ +#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */ + /******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION ((uint32_t)0x00000001U) /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIKERON ((uint32_t)0x00000002U) /*!< Internal High Speed clock enable for some IPs Kernel */ -#define RCC_CR_HSIRDY ((uint32_t)0x00000004U) /*!< Internal High Speed clock ready flag */ -#define RCC_CR_HSIDIVEN ((uint32_t)0x00000008U) /*!< Internal High Speed clock divider enable */ -#define RCC_CR_HSIDIVF ((uint32_t)0x00000010U) /*!< Internal High Speed clock divider flag */ -#define RCC_CR_MSION ((uint32_t)0x00000100U) /*!< Internal Multi Speed clock enable */ -#define RCC_CR_MSIRDY ((uint32_t)0x00000200U) /*!< Internal Multi Speed clock ready flag */ -#define RCC_CR_HSEON ((uint32_t)0x00010000U) /*!< External High Speed clock enable */ -#define RCC_CR_HSERDY ((uint32_t)0x00020000U) /*!< External High Speed clock ready flag */ -#define RCC_CR_HSEBYP ((uint32_t)0x00040000U) /*!< External High Speed clock Bypass */ -#define RCC_CR_CSSHSEON ((uint32_t)0x00080000U) /*!< HSE Clock Security System enable */ -#define RCC_CR_RTCPRE ((uint32_t)0x00300000U) /*!< RTC/LCD prescaler [1:0] bits */ -#define RCC_CR_RTCPRE_0 ((uint32_t)0x00100000U) /*!< RTC/LCD prescaler Bit 0 */ -#define RCC_CR_RTCPRE_1 ((uint32_t)0x00200000U) /*!< RTC/LCD prescaler Bit 1 */ -#define RCC_CR_PLLON ((uint32_t)0x01000000U) /*!< PLL enable */ -#define RCC_CR_PLLRDY ((uint32_t)0x02000000U) /*!< PLL clock ready flag */ +#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIKERON_Pos (1U) +#define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */ +#define RCC_CR_HSIRDY_Pos (2U) +#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSIDIVEN_Pos (3U) +#define RCC_CR_HSIDIVEN_Msk (0x1U << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */ +#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */ +#define RCC_CR_HSIDIVF_Pos (4U) +#define RCC_CR_HSIDIVF_Msk (0x1U << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */ +#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */ +#define RCC_CR_MSION_Pos (8U) +#define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000100 */ +#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */ +#define RCC_CR_MSIRDY_Pos (9U) +#define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */ +#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSHSEON_Pos (19U) +#define RCC_CR_CSSHSEON_Msk (0x1U << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */ +#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */ +#define RCC_CR_RTCPRE_Pos (20U) +#define RCC_CR_RTCPRE_Msk (0x3U << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */ +#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC/LCD prescaler [1:0] bits */ +#define RCC_CR_RTCPRE_0 (0x1U << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */ +#define RCC_CR_RTCPRE_1 (0x2U << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */ +#define RCC_CR_PLLON_Pos (24U) +#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ +#define RCC_CR_PLLRDY_Pos (25U) +#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ /* Reference defines */ #define RCC_CR_CSSON RCC_CR_CSSHSEON /******************** Bit definition for RCC_ICSCR register *****************/ -#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FFU) /*!< Internal High Speed clock Calibration */ -#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00U) /*!< Internal High Speed clock trimming */ +#define RCC_ICSCR_HSICAL_Pos (0U) +#define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */ +#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ +#define RCC_ICSCR_HSITRIM_Pos (8U) +#define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ -#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000U) /*!< Internal Multi Speed clock Range */ -#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000U) /*!< Internal Multi Speed clock Range 65.536 KHz */ -#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000U) /*!< Internal Multi Speed clock Range 131.072 KHz */ -#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000U) /*!< Internal Multi Speed clock Range 262.144 KHz */ -#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000U) /*!< Internal Multi Speed clock Range 524.288 KHz */ -#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000U) /*!< Internal Multi Speed clock Range 1.048 MHz */ -#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000U) /*!< Internal Multi Speed clock Range 2.097 MHz */ -#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000U) /*!< Internal Multi Speed clock Range 4.194 MHz */ -#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000U) /*!< Internal Multi Speed clock Calibration */ -#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000U) /*!< Internal Multi Speed clock trimming */ +#define RCC_ICSCR_MSIRANGE_Pos (13U) +#define RCC_ICSCR_MSIRANGE_Msk (0x7U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */ +#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */ +#define RCC_ICSCR_MSIRANGE_0 (0x0U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */ +#define RCC_ICSCR_MSIRANGE_1 (0x1U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */ +#define RCC_ICSCR_MSIRANGE_2 (0x2U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */ +#define RCC_ICSCR_MSIRANGE_3 (0x3U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */ +#define RCC_ICSCR_MSIRANGE_4 (0x4U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */ +#define RCC_ICSCR_MSIRANGE_5 (0x5U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */ +#define RCC_ICSCR_MSIRANGE_6 (0x6U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */ +#define RCC_ICSCR_MSICAL_Pos (16U) +#define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */ +#define RCC_ICSCR_MSITRIM_Pos (24U) +#define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */ +#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */ /******************** Bit definition for RCC_CRRCR register *****************/ -#define RCC_CRRCR_HSI48ON ((uint32_t)0x00000001U) /*!< HSI 48MHz clock enable */ -#define RCC_CRRCR_HSI48RDY ((uint32_t)0x00000002U) /*!< HSI 48MHz clock ready flag */ -#define RCC_CRRCR_HSI48CAL ((uint32_t)0x0000FF00U) /*!< HSI 48MHz clock Calibration */ +#define RCC_CRRCR_HSI48ON_Pos (0U) +#define RCC_CRRCR_HSI48ON_Msk (0x1U << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */ +#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk /*!< HSI 48MHz clock enable */ +#define RCC_CRRCR_HSI48RDY_Pos (1U) +#define RCC_CRRCR_HSI48RDY_Msk (0x1U << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */ +#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk /*!< HSI 48MHz clock ready flag */ +#define RCC_CRRCR_HSI48CAL_Pos (8U) +#define RCC_CRRCR_HSI48CAL_Msk (0xFFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF00 */ +#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI 48MHz clock Calibration */ /******************* Bit definition for RCC_CFGR register *******************/ /*!< SW configuration */ -#define RCC_CFGR_SW ((uint32_t)0x00000003U) /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ -#define RCC_CFGR_SW_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ -#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000U) /*!< MSI selected as system clock */ -#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001U) /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002U) /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003U) /*!< PLL selected as system clock */ +#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */ +#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */ /*!< SWS configuration */ -#define RCC_CFGR_SWS ((uint32_t)0x0000000CU) /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004U) /*!< Bit 0 */ -#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008U) /*!< Bit 1 */ +#define RCC_CFGR_SWS_Pos (2U) +#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ +#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ -#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004U) /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008U) /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000CU) /*!< PLL used as system clock */ +#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */ /*!< HPRE configuration */ -#define RCC_CFGR_HPRE ((uint32_t)0x000000F0U) /*!< HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010U) /*!< Bit 0 */ -#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020U) /*!< Bit 1 */ -#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040U) /*!< Bit 2 */ -#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080U) /*!< Bit 3 */ +#define RCC_CFGR_HPRE_Pos (4U) +#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ +#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ +#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ -#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000U) /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080U) /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090U) /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0U) /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0U) /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0U) /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0U) /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0U) /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0U) /*!< SYSCLK divided by 512 */ +#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ /*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700U) /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */ -#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */ -#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */ +#define RCC_CFGR_PPRE1_Pos (8U) +#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ +#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ +#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ +#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ -#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400U) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500U) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600U) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700U) /*!< HCLK divided by 16 */ +#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */ /*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800U) /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800U) /*!< Bit 0 */ -#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000U) /*!< Bit 1 */ -#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000U) /*!< Bit 2 */ +#define RCC_CFGR_PPRE2_Pos (11U) +#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ +#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ +#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ +#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ -#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000U) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800U) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000U) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800U) /*!< HCLK divided by 16 */ +#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */ -#define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000U) /*!< Wake Up from Stop Clock selection */ +#define RCC_CFGR_STOPWUCK_Pos (15U) +#define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */ +#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */ /*!< PLL entry clock source*/ -#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000U) /*!< PLL entry clock source */ +#define RCC_CFGR_PLLSRC_Pos (16U) +#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ +#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ -#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000U) /*!< HSI as PLL entry clock source */ -#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000U) /*!< HSE as PLL entry clock source */ +#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */ +#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */ /*!< PLLMUL configuration */ -#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000U) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ -#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ -#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ -#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000U) /*!< Bit 3 */ +#define RCC_CFGR_PLLMUL_Pos (18U) +#define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ -#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000U) /*!< PLL input clock * 3 */ -#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000U) /*!< PLL input clock * 4 */ -#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000U) /*!< PLL input clock * 6 */ -#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000U) /*!< PLL input clock * 8 */ -#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000U) /*!< PLL input clock * 12 */ -#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000U) /*!< PLL input clock * 16 */ -#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000U) /*!< PLL input clock * 24 */ -#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000U) /*!< PLL input clock * 32 */ -#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000U) /*!< PLL input clock * 48 */ +#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */ +#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */ +#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */ +#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */ +#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */ +#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */ +#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */ +#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */ +#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */ /*!< PLLDIV configuration */ -#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000U) /*!< PLLDIV[1:0] bits (PLL Output Division) */ -#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000U) /*!< Bit0 */ -#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000U) /*!< Bit1 */ +#define RCC_CFGR_PLLDIV_Pos (22U) +#define RCC_CFGR_PLLDIV_Msk (0x3U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */ +#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */ +#define RCC_CFGR_PLLDIV_0 (0x1U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_PLLDIV_1 (0x2U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */ -#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000U) /*!< PLL clock output = CKVCO / 2 */ -#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000U) /*!< PLL clock output = CKVCO / 3 */ -#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000U) /*!< PLL clock output = CKVCO / 4 */ +#define RCC_CFGR_PLLDIV2_Pos (22U) +#define RCC_CFGR_PLLDIV2_Msk (0x1U << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */ +#define RCC_CFGR_PLLDIV3_Pos (23U) +#define RCC_CFGR_PLLDIV3_Msk (0x1U << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */ +#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */ +#define RCC_CFGR_PLLDIV4_Pos (22U) +#define RCC_CFGR_PLLDIV4_Msk (0x3U << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */ +#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */ /*!< MCO configuration */ -#define RCC_CFGR_MCOSEL ((uint32_t)0x0F000000U) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ -#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ -#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ -#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000U) /*!< Bit 2 */ -#define RCC_CFGR_MCOSEL_3 ((uint32_t)0x08000000U) /*!< Bit 3 */ +#define RCC_CFGR_MCOSEL_Pos (24U) +#define RCC_CFGR_MCOSEL_Msk (0xFU << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */ +#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */ +#define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ +#define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */ -#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */ -#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000U) /*!< System clock selected as MCO source */ -#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000U) /*!< Internal 16 MHz RC oscillator clock selected */ -#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000U) /*!< Internal Medium Speed RC oscillator clock selected */ -#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000U) /*!< External 1-25 MHz oscillator clock selected */ -#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000U) /*!< PLL clock divided */ -#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000U) /*!< LSI selected */ -#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000U) /*!< LSE selected */ -#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000U) /*!< HSI48 clock selected as MCO source */ +#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */ +#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U) +#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */ +#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */ +#define RCC_CFGR_MCOSEL_HSI_Pos (25U) +#define RCC_CFGR_MCOSEL_HSI_Msk (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */ +#define RCC_CFGR_MCOSEL_MSI_Pos (24U) +#define RCC_CFGR_MCOSEL_MSI_Msk (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */ +#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */ +#define RCC_CFGR_MCOSEL_HSE_Pos (26U) +#define RCC_CFGR_MCOSEL_HSE_Msk (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */ +#define RCC_CFGR_MCOSEL_PLL_Pos (24U) +#define RCC_CFGR_MCOSEL_PLL_Msk (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */ +#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */ +#define RCC_CFGR_MCOSEL_LSI_Pos (25U) +#define RCC_CFGR_MCOSEL_LSI_Msk (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */ +#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */ +#define RCC_CFGR_MCOSEL_LSE_Pos (24U) +#define RCC_CFGR_MCOSEL_LSE_Msk (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */ +#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */ +#define RCC_CFGR_MCOSEL_HSI48_Pos (27U) +#define RCC_CFGR_MCOSEL_HSI48_Msk (0x1U << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */ +#define RCC_CFGR_MCOSEL_HSI48 RCC_CFGR_MCOSEL_HSI48_Msk /*!< HSI48 clock selected as MCO source */ -#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000U) /*!< MCO prescaler */ -#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */ -#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */ -#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000U) /*!< MCO is divided by 8 */ +#define RCC_CFGR_MCOPRE_Pos (28U) +#define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ +#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */ +#define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ +#define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ -#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000U) /*!< MCO is divided by 1 */ -#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */ -#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */ -#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000U) /*!< MCO is divided by 8 */ -#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000U) /*!< MCO is divided by 16 */ +#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ +#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ +#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ +#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ +#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ /* Legacy defines */ +#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK +#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK +#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI +#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI +#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE +#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL +#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI +#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE +#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48 + #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */ #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */ #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */ @@ -2408,53 +3946,115 @@ typedef struct #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */ /*!<****************** Bit definition for RCC_CIER register ********************/ -#define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Enable */ -#define RCC_CIER_LSERDYIE ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Enable */ -#define RCC_CIER_HSIRDYIE ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Enable */ -#define RCC_CIER_HSERDYIE ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Enable */ -#define RCC_CIER_PLLRDYIE ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Enable */ -#define RCC_CIER_MSIRDYIE ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Enable */ -#define RCC_CIER_HSI48RDYIE ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt Enable */ -#define RCC_CIER_CSSLSE ((uint32_t)0x00000080U) /*!< LSE CSS Interrupt Enable */ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ +#define RCC_CIER_HSIRDYIE_Pos (2U) +#define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ +#define RCC_CIER_HSERDYIE_Pos (3U) +#define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ +#define RCC_CIER_PLLRDYIE_Pos (4U) +#define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ +#define RCC_CIER_MSIRDYIE_Pos (5U) +#define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */ +#define RCC_CIER_HSI48RDYIE_Pos (6U) +#define RCC_CIER_HSI48RDYIE_Msk (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk /*!< HSI48 Ready Interrupt Enable */ +#define RCC_CIER_CSSLSE_Pos (7U) +#define RCC_CIER_CSSLSE_Msk (0x1U << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */ /* Reference defines */ #define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE /*!<****************** Bit definition for RCC_CIFR register ********************/ -#define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt flag */ -#define RCC_CIFR_LSERDYF ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt flag */ -#define RCC_CIFR_HSIRDYF ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt flag */ -#define RCC_CIFR_HSERDYF ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt flag */ -#define RCC_CIFR_PLLRDYF ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt flag */ -#define RCC_CIFR_MSIRDYF ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt flag */ -#define RCC_CIFR_HSI48RDYF ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt flag */ -#define RCC_CIFR_CSSLSEF ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt flag */ -#define RCC_CIFR_CSSHSEF ((uint32_t)0x00000100U) /*!< HSE Clock Security System Interrupt flag */ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ +#define RCC_CIFR_HSIRDYF_Pos (2U) +#define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ +#define RCC_CIFR_HSERDYF_Pos (3U) +#define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ +#define RCC_CIFR_PLLRDYF_Pos (4U) +#define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ +#define RCC_CIFR_MSIRDYF_Pos (5U) +#define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */ +#define RCC_CIFR_HSI48RDYF_Pos (6U) +#define RCC_CIFR_HSI48RDYF_Msk (0x1U << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk /*!< HSI48 Ready Interrupt flag */ +#define RCC_CIFR_CSSLSEF_Pos (7U) +#define RCC_CIFR_CSSLSEF_Msk (0x1U << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */ +#define RCC_CIFR_CSSHSEF_Pos (8U) +#define RCC_CIFR_CSSHSEF_Msk (0x1U << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */ /* Reference defines */ #define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF #define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF /*!<****************** Bit definition for RCC_CICR register ********************/ -#define RCC_CICR_LSIRDYC ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Clear */ -#define RCC_CICR_LSERDYC ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Clear */ -#define RCC_CICR_HSIRDYC ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Clear */ -#define RCC_CICR_HSERDYC ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Clear */ -#define RCC_CICR_PLLRDYC ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Clear */ -#define RCC_CICR_MSIRDYC ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Clear */ -#define RCC_CICR_HSI48RDYC ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt Clear */ -#define RCC_CICR_CSSLSEC ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt Clear */ -#define RCC_CICR_CSSHSEC ((uint32_t)0x00000100U) /*!< HSE Clock Security System Interrupt Clear */ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ +#define RCC_CICR_HSIRDYC_Pos (2U) +#define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ +#define RCC_CICR_HSERDYC_Pos (3U) +#define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ +#define RCC_CICR_PLLRDYC_Pos (4U) +#define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ +#define RCC_CICR_MSIRDYC_Pos (5U) +#define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */ +#define RCC_CICR_HSI48RDYC_Pos (6U) +#define RCC_CICR_HSI48RDYC_Msk (0x1U << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk /*!< HSI48 Ready Interrupt Clear */ +#define RCC_CICR_CSSLSEC_Pos (7U) +#define RCC_CICR_CSSLSEC_Msk (0x1U << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */ +#define RCC_CICR_CSSHSEC_Pos (8U) +#define RCC_CICR_CSSHSEC_Msk (0x1U << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */ /* Reference defines */ #define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC #define RCC_CICR_CSSC RCC_CICR_CSSHSEC /***************** Bit definition for RCC_IOPRSTR register ******************/ -#define RCC_IOPRSTR_IOPARST ((uint32_t)0x00000001U) /*!< GPIO port A reset */ -#define RCC_IOPRSTR_IOPBRST ((uint32_t)0x00000002U) /*!< GPIO port B reset */ -#define RCC_IOPRSTR_IOPCRST ((uint32_t)0x00000004U) /*!< GPIO port C reset */ -#define RCC_IOPRSTR_IOPDRST ((uint32_t)0x00000008U) /*!< GPIO port D reset */ -#define RCC_IOPRSTR_IOPHRST ((uint32_t)0x00000080U) /*!< GPIO port H reset */ +#define RCC_IOPRSTR_IOPARST_Pos (0U) +#define RCC_IOPRSTR_IOPARST_Msk (0x1U << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */ +#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */ +#define RCC_IOPRSTR_IOPBRST_Pos (1U) +#define RCC_IOPRSTR_IOPBRST_Msk (0x1U << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */ +#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */ +#define RCC_IOPRSTR_IOPCRST_Pos (2U) +#define RCC_IOPRSTR_IOPCRST_Msk (0x1U << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */ +#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */ +#define RCC_IOPRSTR_IOPDRST_Pos (3U) +#define RCC_IOPRSTR_IOPDRST_Msk (0x1U << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */ +#define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */ +#define RCC_IOPRSTR_IOPHRST_Pos (7U) +#define RCC_IOPRSTR_IOPHRST_Msk (0x1U << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */ +#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */ /* Reference defines */ #define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */ @@ -2465,50 +4065,112 @@ typedef struct /****************** Bit definition for RCC_AHBRST register ******************/ -#define RCC_AHBRSTR_DMARST ((uint32_t)0x00000001U) /*!< DMA1 reset */ -#define RCC_AHBRSTR_MIFRST ((uint32_t)0x00000100U) /*!< Memory interface reset reset */ -#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000U) /*!< CRC reset */ -#define RCC_AHBRSTR_TSCRST ((uint32_t)0x00010000U) /*!< TSC reset */ -#define RCC_AHBRSTR_RNGRST ((uint32_t)0x00100000U) /*!< RNG reset */ +#define RCC_AHBRSTR_DMARST_Pos (0U) +#define RCC_AHBRSTR_DMARST_Msk (0x1U << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */ +#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */ +#define RCC_AHBRSTR_MIFRST_Pos (8U) +#define RCC_AHBRSTR_MIFRST_Msk (0x1U << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */ +#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset reset */ +#define RCC_AHBRSTR_CRCRST_Pos (12U) +#define RCC_AHBRSTR_CRCRST_Msk (0x1U << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */ +#define RCC_AHBRSTR_TSCRST_Pos (16U) +#define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */ +#define RCC_AHBRSTR_RNGRST_Pos (20U) +#define RCC_AHBRSTR_RNGRST_Msk (0x1U << RCC_AHBRSTR_RNGRST_Pos) /*!< 0x00100000 */ +#define RCC_AHBRSTR_RNGRST RCC_AHBRSTR_RNGRST_Msk /*!< RNG reset */ /* Reference defines */ #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */ /***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001U) /*!< SYSCFG clock reset */ -#define RCC_APB2RSTR_TIM21RST ((uint32_t)0x00000004U) /*!< TIM21 clock reset */ -#define RCC_APB2RSTR_TIM22RST ((uint32_t)0x00000020U) /*!< TIM22 clock reset */ -#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200U) /*!< ADC1 clock reset */ -#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000U) /*!< SPI1 clock reset */ -#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000U) /*!< USART1 clock reset */ -#define RCC_APB2RSTR_DBGRST ((uint32_t)0x00400000U) /*!< DBGMCU clock reset */ +#define RCC_APB2RSTR_SYSCFGRST_Pos (0U) +#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ +#define RCC_APB2RSTR_TIM21RST_Pos (2U) +#define RCC_APB2RSTR_TIM21RST_Msk (0x1U << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 clock reset */ +#define RCC_APB2RSTR_TIM22RST_Pos (5U) +#define RCC_APB2RSTR_TIM22RST_Msk (0x1U << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 clock reset */ +#define RCC_APB2RSTR_ADCRST_Pos (9U) +#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 clock reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ +#define RCC_APB2RSTR_DBGRST_Pos (22U) +#define RCC_APB2RSTR_DBGRST_Msk (0x1U << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU clock reset */ /* Reference defines */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 clock reset */ #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU clock reset */ /***************** Bit definition for RCC_APB1RSTR register *****************/ -#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001U) /*!< Timer 2 clock reset */ -#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010U) /*!< Timer 6 clock reset */ -#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200U) /*!< LCD clock reset */ -#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800U) /*!< Window Watchdog clock reset */ -#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000U) /*!< SPI2 clock reset */ -#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000U) /*!< USART 2 clock reset */ -#define RCC_APB1RSTR_LPUART1RST ((uint32_t)0x00040000U) /*!< LPUART1 clock reset */ -#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000U) /*!< I2C 1 clock reset */ -#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000U) /*!< I2C 2 clock reset */ -#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000U) /*!< USB clock reset */ -#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000U) /*!< CRS clock reset */ -#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000U) /*!< PWR clock reset */ -#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000U) /*!< DAC clock reset */ -#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x80000000U) /*!< LPTIM1 clock reset */ +#define RCC_APB1RSTR_TIM2RST_Pos (0U) +#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ +#define RCC_APB1RSTR_TIM6RST_Pos (4U) +#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */ +#define RCC_APB1RSTR_LCDRST_Pos (9U) +#define RCC_APB1RSTR_LCDRST_Msk (0x1U << RCC_APB1RSTR_LCDRST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTR_LCDRST RCC_APB1RSTR_LCDRST_Msk /*!< LCD clock reset */ +#define RCC_APB1RSTR_WWDGRST_Pos (11U) +#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ +#define RCC_APB1RSTR_SPI2RST_Pos (14U) +#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ +#define RCC_APB1RSTR_USART2RST_Pos (17U) +#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ +#define RCC_APB1RSTR_LPUART1RST_Pos (18U) +#define RCC_APB1RSTR_LPUART1RST_Msk (0x1U << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 clock reset */ +#define RCC_APB1RSTR_I2C1RST_Pos (21U) +#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ +#define RCC_APB1RSTR_I2C2RST_Pos (22U) +#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ +#define RCC_APB1RSTR_USBRST_Pos (23U) +#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB clock reset */ +#define RCC_APB1RSTR_CRSRST_Pos (27U) +#define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS clock reset */ +#define RCC_APB1RSTR_PWRRST_Pos (28U) +#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ +#define RCC_APB1RSTR_DACRST_Pos (29U) +#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC clock reset */ +#define RCC_APB1RSTR_LPTIM1RST_Pos (31U) +#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 clock reset */ /***************** Bit definition for RCC_IOPENR register ******************/ -#define RCC_IOPENR_IOPAEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enable */ -#define RCC_IOPENR_IOPBEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enable */ -#define RCC_IOPENR_IOPCEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enable */ -#define RCC_IOPENR_IOPDEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enable */ -#define RCC_IOPENR_IOPHEN ((uint32_t)0x00000080U) /*!< GPIO port H clock enable */ +#define RCC_IOPENR_IOPAEN_Pos (0U) +#define RCC_IOPENR_IOPAEN_Msk (0x1U << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */ +#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */ +#define RCC_IOPENR_IOPBEN_Pos (1U) +#define RCC_IOPENR_IOPBEN_Msk (0x1U << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */ +#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */ +#define RCC_IOPENR_IOPCEN_Pos (2U) +#define RCC_IOPENR_IOPCEN_Msk (0x1U << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */ +#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */ +#define RCC_IOPENR_IOPDEN_Pos (3U) +#define RCC_IOPENR_IOPDEN_Msk (0x1U << RCC_IOPENR_IOPDEN_Pos) /*!< 0x00000008 */ +#define RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk /*!< GPIO port D clock enable */ +#define RCC_IOPENR_IOPHEN_Pos (7U) +#define RCC_IOPENR_IOPHEN_Msk (0x1U << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */ +#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */ /* Reference defines */ #define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */ @@ -2518,24 +4180,50 @@ typedef struct #define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */ /***************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001U) /*!< DMA1 clock enable */ -#define RCC_AHBENR_MIFEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable bit */ -#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000U) /*!< CRC clock enable */ -#define RCC_AHBENR_TSCEN ((uint32_t)0x00010000U) /*!< TSC clock enable */ -#define RCC_AHBENR_RNGEN ((uint32_t)0x00100000U) /*!< RNG clock enable */ +#define RCC_AHBENR_DMAEN_Pos (0U) +#define RCC_AHBENR_DMAEN_Msk (0x1U << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */ +#define RCC_AHBENR_MIFEN_Pos (8U) +#define RCC_AHBENR_MIFEN_Msk (0x1U << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */ +#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */ +#define RCC_AHBENR_CRCEN_Pos (12U) +#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ +#define RCC_AHBENR_TSCEN_Pos (16U) +#define RCC_AHBENR_TSCEN_Msk (0x1U << RCC_AHBENR_TSCEN_Pos) /*!< 0x00010000 */ +#define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TSC clock enable */ +#define RCC_AHBENR_RNGEN_Pos (20U) +#define RCC_AHBENR_RNGEN_Msk (0x1U << RCC_AHBENR_RNGEN_Pos) /*!< 0x00100000 */ +#define RCC_AHBENR_RNGEN RCC_AHBENR_RNGEN_Msk /*!< RNG clock enable */ /* Reference defines */ #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ /***************** Bit definition for RCC_APB2ENR register ******************/ -#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enable */ -#define RCC_APB2ENR_TIM21EN ((uint32_t)0x00000004U) /*!< TIM21 clock enable */ -#define RCC_APB2ENR_TIM22EN ((uint32_t)0x00000020U) /*!< TIM22 clock enable */ -#define RCC_APB2ENR_FWEN ((uint32_t)0x00000080U) /*!< MiFare Firewall clock enable */ -#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200U) /*!< ADC1 clock enable */ -#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000U) /*!< SPI1 clock enable */ -#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000U) /*!< USART1 clock enable */ -#define RCC_APB2ENR_DBGEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enable */ +#define RCC_APB2ENR_SYSCFGEN_Pos (0U) +#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */ +#define RCC_APB2ENR_TIM21EN_Pos (2U) +#define RCC_APB2ENR_TIM21EN_Msk (0x1U << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */ +#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */ +#define RCC_APB2ENR_TIM22EN_Pos (5U) +#define RCC_APB2ENR_TIM22EN_Msk (0x1U << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */ +#define RCC_APB2ENR_FWEN_Pos (7U) +#define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */ +#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */ +#define RCC_APB2ENR_ADCEN_Pos (9U) +#define RCC_APB2ENR_ADCEN_Msk (0x1U << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */ +#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ +#define RCC_APB2ENR_DBGEN_Pos (22U) +#define RCC_APB2ENR_DBGEN_Msk (0x1U << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */ /* Reference defines */ @@ -2544,27 +4232,65 @@ typedef struct #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */ /***************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001U) /*!< Timer 2 clock enable */ -#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010U) /*!< Timer 6 clock enable */ -#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200U) /*!< LCD clock enable */ -#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enable */ -#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000U) /*!< SPI2 clock enable */ -#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000U) /*!< USART2 clock enable */ -#define RCC_APB1ENR_LPUART1EN ((uint32_t)0x00040000U) /*!< LPUART1 clock enable */ -#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000U) /*!< I2C1 clock enable */ -#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000U) /*!< I2C2 clock enable */ -#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000U) /*!< USB clock enable */ -#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000U) /*!< CRS clock enable */ -#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000U) /*!< PWR clock enable */ -#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000U) /*!< DAC clock enable */ -#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enable */ +#define RCC_APB1ENR_TIM2EN_Pos (0U) +#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */ +#define RCC_APB1ENR_TIM6EN_Pos (4U) +#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ +#define RCC_APB1ENR_LCDEN_Pos (9U) +#define RCC_APB1ENR_LCDEN_Msk (0x1U << RCC_APB1ENR_LCDEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1ENR_LCDEN RCC_APB1ENR_LCDEN_Msk /*!< LCD clock enable */ +#define RCC_APB1ENR_WWDGEN_Pos (11U) +#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_SPI2EN_Pos (14U) +#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */ +#define RCC_APB1ENR_USART2EN_Pos (17U) +#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */ +#define RCC_APB1ENR_LPUART1EN_Pos (18U) +#define RCC_APB1ENR_LPUART1EN_Msk (0x1U << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */ +#define RCC_APB1ENR_I2C1EN_Pos (21U) +#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */ +#define RCC_APB1ENR_I2C2EN_Pos (22U) +#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */ +#define RCC_APB1ENR_USBEN_Pos (23U) +#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */ +#define RCC_APB1ENR_CRSEN_Pos (27U) +#define RCC_APB1ENR_CRSEN_Msk (0x1U << RCC_APB1ENR_CRSEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enable */ +#define RCC_APB1ENR_PWREN_Pos (28U) +#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ +#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */ +#define RCC_APB1ENR_DACEN_Pos (29U) +#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ +#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC clock enable */ +#define RCC_APB1ENR_LPTIM1EN_Pos (31U) +#define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */ /****************** Bit definition for RCC_IOPSMENR register ****************/ -#define RCC_IOPSMENR_IOPASMEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enabled in sleep mode */ -#define RCC_IOPSMENR_IOPBSMEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enabled in sleep mode */ -#define RCC_IOPSMENR_IOPCSMEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enabled in sleep mode */ -#define RCC_IOPSMENR_IOPDSMEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enabled in sleep mode */ -#define RCC_IOPSMENR_IOPHSMEN ((uint32_t)0x00000080U) /*!< GPIO port H clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPASMEN_Pos (0U) +#define RCC_IOPSMENR_IOPASMEN_Msk (0x1U << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */ +#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPBSMEN_Pos (1U) +#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1U << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */ +#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPCSMEN_Pos (2U) +#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1U << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */ +#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPDSMEN_Pos (3U) +#define RCC_IOPSMENR_IOPDSMEN_Msk (0x1U << RCC_IOPSMENR_IOPDSMEN_Pos) /*!< 0x00000008 */ +#define RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk /*!< GPIO port D clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPHSMEN_Pos (7U) +#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1U << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */ +#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */ /* Reference defines */ #define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */ @@ -2574,115 +4300,227 @@ typedef struct #define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */ /***************** Bit definition for RCC_AHBSMENR register ******************/ -#define RCC_AHBSMENR_DMASMEN ((uint32_t)0x00000001U) /*!< DMA1 clock enabled in sleep mode */ -#define RCC_AHBSMENR_MIFSMEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable during sleep mode */ -#define RCC_AHBSMENR_SRAMSMEN ((uint32_t)0x00000200U) /*!< SRAM clock enabled in sleep mode */ -#define RCC_AHBSMENR_CRCSMEN ((uint32_t)0x00001000U) /*!< CRC clock enabled in sleep mode */ -#define RCC_AHBSMENR_TSCSMEN ((uint32_t)0x00010000U) /*!< TSC clock enabled in sleep mode */ -#define RCC_AHBSMENR_RNGSMEN ((uint32_t)0x00100000U) /*!< RNG clock enabled in sleep mode */ +#define RCC_AHBSMENR_DMASMEN_Pos (0U) +#define RCC_AHBSMENR_DMASMEN_Msk (0x1U << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */ +#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */ +#define RCC_AHBSMENR_MIFSMEN_Pos (8U) +#define RCC_AHBSMENR_MIFSMEN_Msk (0x1U << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */ +#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */ +#define RCC_AHBSMENR_SRAMSMEN_Pos (9U) +#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1U << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */ +#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */ +#define RCC_AHBSMENR_CRCSMEN_Pos (12U) +#define RCC_AHBSMENR_CRCSMEN_Msk (0x1U << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */ +#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */ +#define RCC_AHBSMENR_TSCSMEN_Pos (16U) +#define RCC_AHBSMENR_TSCSMEN_Msk (0x1U << RCC_AHBSMENR_TSCSMEN_Pos) /*!< 0x00010000 */ +#define RCC_AHBSMENR_TSCSMEN RCC_AHBSMENR_TSCSMEN_Msk /*!< TSC clock enabled in sleep mode */ +#define RCC_AHBSMENR_RNGSMEN_Pos (20U) +#define RCC_AHBSMENR_RNGSMEN_Msk (0x1U << RCC_AHBSMENR_RNGSMEN_Pos) /*!< 0x00100000 */ +#define RCC_AHBSMENR_RNGSMEN RCC_AHBSMENR_RNGSMEN_Msk /*!< RNG clock enabled in sleep mode */ /* Reference defines */ #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */ /***************** Bit definition for RCC_APB2SMENR register ******************/ -#define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enabled in sleep mode */ -#define RCC_APB2SMENR_TIM21SMEN ((uint32_t)0x00000004U) /*!< TIM21 clock enabled in sleep mode */ -#define RCC_APB2SMENR_TIM22SMEN ((uint32_t)0x00000020U) /*!< TIM22 clock enabled in sleep mode */ -#define RCC_APB2SMENR_ADCSMEN ((uint32_t)0x00000200U) /*!< ADC1 clock enabled in sleep mode */ -#define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000U) /*!< SPI1 clock enabled in sleep mode */ -#define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000U) /*!< USART1 clock enabled in sleep mode */ -#define RCC_APB2SMENR_DBGSMEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enabled in sleep mode */ +#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U) +#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */ +#define RCC_APB2SMENR_TIM21SMEN_Pos (2U) +#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1U << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */ +#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */ +#define RCC_APB2SMENR_TIM22SMEN_Pos (5U) +#define RCC_APB2SMENR_TIM22SMEN_Msk (0x1U << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */ +#define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */ +#define RCC_APB2SMENR_ADCSMEN_Pos (9U) +#define RCC_APB2SMENR_ADCSMEN_Msk (0x1U << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */ +#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */ +#define RCC_APB2SMENR_SPI1SMEN_Pos (12U) +#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */ +#define RCC_APB2SMENR_USART1SMEN_Pos (14U) +#define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk /*!< USART1 clock enabled in sleep mode */ +#define RCC_APB2SMENR_DBGSMEN_Pos (22U) +#define RCC_APB2SMENR_DBGSMEN_Msk (0x1U << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */ /* Reference defines */ #define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */ #define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */ /***************** Bit definition for RCC_APB1SMENR register ******************/ -#define RCC_APB1SMENR_TIM2SMEN ((uint32_t)0x00000001U) /*!< Timer 2 clock enabled in sleep mode */ -#define RCC_APB1SMENR_TIM6SMEN ((uint32_t)0x00000010U) /*!< Timer 6 clock enabled in sleep mode */ -#define RCC_APB1SMENR_LCDSMEN ((uint32_t)0x00000200U) /*!< LCD clock enabled in sleep mode */ -#define RCC_APB1SMENR_WWDGSMEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enabled in sleep mode */ -#define RCC_APB1SMENR_SPI2SMEN ((uint32_t)0x00004000U) /*!< SPI2 clock enabled in sleep mode */ -#define RCC_APB1SMENR_USART2SMEN ((uint32_t)0x00020000U) /*!< USART2 clock enabled in sleep mode */ -#define RCC_APB1SMENR_LPUART1SMEN ((uint32_t)0x00040000U) /*!< LPUART1 clock enabled in sleep mode */ -#define RCC_APB1SMENR_I2C1SMEN ((uint32_t)0x00200000U) /*!< I2C1 clock enabled in sleep mode */ -#define RCC_APB1SMENR_I2C2SMEN ((uint32_t)0x00400000U) /*!< I2C2 clock enabled in sleep mode */ -#define RCC_APB1SMENR_USBSMEN ((uint32_t)0x00800000U) /*!< USB clock enabled in sleep mode */ -#define RCC_APB1SMENR_CRSSMEN ((uint32_t)0x08000000U) /*!< CRS clock enabled in sleep mode */ -#define RCC_APB1SMENR_PWRSMEN ((uint32_t)0x10000000U) /*!< PWR clock enabled in sleep mode */ -#define RCC_APB1SMENR_DACSMEN ((uint32_t)0x20000000U) /*!< DAC clock enabled in sleep mode */ -#define RCC_APB1SMENR_LPTIM1SMEN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enabled in sleep mode */ +#define RCC_APB1SMENR_TIM2SMEN_Pos (0U) +#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */ +#define RCC_APB1SMENR_TIM6SMEN_Pos (4U) +#define RCC_APB1SMENR_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR_TIM6SMEN_Pos) /*!< 0x00000010 */ +#define RCC_APB1SMENR_TIM6SMEN RCC_APB1SMENR_TIM6SMEN_Msk /*!< Timer 6 clock enabled in sleep mode */ +#define RCC_APB1SMENR_LCDSMEN_Pos (9U) +#define RCC_APB1SMENR_LCDSMEN_Msk (0x1U << RCC_APB1SMENR_LCDSMEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1SMENR_LCDSMEN RCC_APB1SMENR_LCDSMEN_Msk /*!< LCD clock enabled in sleep mode */ +#define RCC_APB1SMENR_WWDGSMEN_Pos (11U) +#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */ +#define RCC_APB1SMENR_SPI2SMEN_Pos (14U) +#define RCC_APB1SMENR_SPI2SMEN_Msk (0x1U << RCC_APB1SMENR_SPI2SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1SMENR_SPI2SMEN RCC_APB1SMENR_SPI2SMEN_Msk /*!< SPI2 clock enabled in sleep mode */ +#define RCC_APB1SMENR_USART2SMEN_Pos (17U) +#define RCC_APB1SMENR_USART2SMEN_Msk (0x1U << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */ +#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U) +#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */ +#define RCC_APB1SMENR_I2C1SMEN_Pos (21U) +#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */ +#define RCC_APB1SMENR_I2C2SMEN_Pos (22U) +#define RCC_APB1SMENR_I2C2SMEN_Msk (0x1U << RCC_APB1SMENR_I2C2SMEN_Pos) /*!< 0x00400000 */ +#define RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_Msk /*!< I2C2 clock enabled in sleep mode */ +#define RCC_APB1SMENR_USBSMEN_Pos (23U) +#define RCC_APB1SMENR_USBSMEN_Msk (0x1U << RCC_APB1SMENR_USBSMEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1SMENR_USBSMEN RCC_APB1SMENR_USBSMEN_Msk /*!< USB clock enabled in sleep mode */ +#define RCC_APB1SMENR_CRSSMEN_Pos (27U) +#define RCC_APB1SMENR_CRSSMEN_Msk (0x1U << RCC_APB1SMENR_CRSSMEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1SMENR_CRSSMEN RCC_APB1SMENR_CRSSMEN_Msk /*!< CRS clock enabled in sleep mode */ +#define RCC_APB1SMENR_PWRSMEN_Pos (28U) +#define RCC_APB1SMENR_PWRSMEN_Msk (0x1U << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */ +#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */ +#define RCC_APB1SMENR_DACSMEN_Pos (29U) +#define RCC_APB1SMENR_DACSMEN_Msk (0x1U << RCC_APB1SMENR_DACSMEN_Pos) /*!< 0x20000000 */ +#define RCC_APB1SMENR_DACSMEN RCC_APB1SMENR_DACSMEN_Msk /*!< DAC clock enabled in sleep mode */ +#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U) +#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */ +#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */ /******************* Bit definition for RCC_CCIPR register *******************/ /*!< USART1 Clock source selection */ -#define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003U) /*!< USART1SEL[1:0] bits */ -#define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ -#define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define RCC_CCIPR_USART1SEL_Pos (0U) +#define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk /*!< USART1SEL[1:0] bits */ +#define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */ /*!< USART2 Clock source selection */ -#define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000CU) /*!< USART2SEL[1:0] bits */ -#define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004U) /*!< Bit 0 */ -#define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008U) /*!< Bit 1 */ +#define RCC_CCIPR_USART2SEL_Pos (2U) +#define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */ +#define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */ /*!< LPUART1 Clock source selection */ -#define RCC_CCIPR_LPUART1SEL ((uint32_t)0x0000C00) /*!< LPUART1SEL[1:0] bits */ -#define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x0000400) /*!< Bit 0 */ -#define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x0000800) /*!< Bit 1 */ +#define RCC_CCIPR_LPUART1SEL_Pos (10U) +#define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */ +#define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */ +#define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */ /*!< I2C1 Clock source selection */ -#define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000U) /*!< I2C1SEL [1:0] bits */ -#define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ -#define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define RCC_CCIPR_I2C1SEL_Pos (12U) +#define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */ +#define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */ /*!< LPTIM1 Clock source selection */ -#define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000U) /*!< LPTIM1SEL [1:0] bits */ -#define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ -#define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ +#define RCC_CCIPR_LPTIM1SEL_Pos (18U) +#define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */ +#define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */ /*!< HSI48 Clock source selection */ -#define RCC_CCIPR_HSI48SEL ((uint32_t)0x04000000U) /*!< HSI48 RC clock source selection bit for USB and RNG*/ +#define RCC_CCIPR_HSI48SEL_Pos (26U) +#define RCC_CCIPR_HSI48SEL_Msk (0x1U << RCC_CCIPR_HSI48SEL_Pos) /*!< 0x04000000 */ +#define RCC_CCIPR_HSI48SEL RCC_CCIPR_HSI48SEL_Msk /*!< HSI48 RC clock source selection bit for USB and RNG*/ /* Legacy defines */ #define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL /******************* Bit definition for RCC_CSR register *******************/ -#define RCC_CSR_LSION ((uint32_t)0x00000001U) /*!< Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY ((uint32_t)0x00000002U) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_LSEON ((uint32_t)0x00000100U) /*!< External Low Speed oscillator enable */ -#define RCC_CSR_LSERDY ((uint32_t)0x00000200U) /*!< External Low Speed oscillator Ready */ -#define RCC_CSR_LSEBYP ((uint32_t)0x00000400U) /*!< External Low Speed oscillator Bypass */ +#define RCC_CSR_LSEON_Pos (8U) +#define RCC_CSR_LSEON_Msk (0x1U << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */ +#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */ +#define RCC_CSR_LSERDY_Pos (9U) +#define RCC_CSR_LSERDY_Msk (0x1U << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */ +#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ +#define RCC_CSR_LSEBYP_Pos (10U) +#define RCC_CSR_LSEBYP_Msk (0x1U << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ -#define RCC_CSR_LSEDRV ((uint32_t)0x00001800U) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ -#define RCC_CSR_LSEDRV_0 ((uint32_t)0x00000800U) /*!< Bit 0 */ -#define RCC_CSR_LSEDRV_1 ((uint32_t)0x00001000U) /*!< Bit 1 */ +#define RCC_CSR_LSEDRV_Pos (11U) +#define RCC_CSR_LSEDRV_Msk (0x3U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */ +#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ +#define RCC_CSR_LSEDRV_0 (0x1U << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */ +#define RCC_CSR_LSEDRV_1 (0x2U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */ -#define RCC_CSR_LSECSSON ((uint32_t)0x00002000U) /*!< External Low Speed oscillator CSS Enable */ -#define RCC_CSR_LSECSSD ((uint32_t)0x00004000U) /*!< External Low Speed oscillator CSS Detected */ +#define RCC_CSR_LSECSSON_Pos (13U) +#define RCC_CSR_LSECSSON_Msk (0x1U << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */ +#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */ +#define RCC_CSR_LSECSSD_Pos (14U) +#define RCC_CSR_LSECSSD_Msk (0x1U << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ +#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ /*!< RTC congiguration */ -#define RCC_CSR_RTCSEL ((uint32_t)0x00030000U) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ -#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ +#define RCC_CSR_RTCSEL_Pos (16U) +#define RCC_CSR_RTCSEL_Msk (0x3U << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ +#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_CSR_RTCSEL_0 (0x1U << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */ +#define RCC_CSR_RTCSEL_1 (0x2U << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */ -#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */ -#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000U) /*!< LSE oscillator clock used as RTC clock */ -#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000U) /*!< LSI oscillator clock used as RTC clock */ -#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000U) /*!< HSE oscillator clock used as RTC clock */ +#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ +#define RCC_CSR_RTCSEL_LSE_Pos (16U) +#define RCC_CSR_RTCSEL_LSE_Msk (0x1U << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */ +#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */ +#define RCC_CSR_RTCSEL_LSI_Pos (17U) +#define RCC_CSR_RTCSEL_LSI_Msk (0x1U << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */ +#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */ +#define RCC_CSR_RTCSEL_HSE_Pos (16U) +#define RCC_CSR_RTCSEL_HSE_Msk (0x3U << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */ +#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */ -#define RCC_CSR_RTCEN ((uint32_t)0x00040000U) /*!< RTC clock enable */ -#define RCC_CSR_RTCRST ((uint32_t)0x00080000U) /*!< RTC software reset */ +#define RCC_CSR_RTCEN_Pos (18U) +#define RCC_CSR_RTCEN_Msk (0x1U << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */ +#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */ +#define RCC_CSR_RTCRST_Pos (19U) +#define RCC_CSR_RTCRST_Msk (0x1U << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */ +#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */ -#define RCC_CSR_RMVF ((uint32_t)0x00800000U) /*!< Remove reset flag */ -#define RCC_CSR_FWRSTF ((uint32_t)0x01000000U) /*!< Mifare Firewall reset flag */ -#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000U) /*!< OBL reset flag */ -#define RCC_CSR_PINRSTF ((uint32_t)0x04000000U) /*!< PIN reset flag */ -#define RCC_CSR_PORRSTF ((uint32_t)0x08000000U) /*!< POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000U) /*!< Software Reset flag */ -#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000U) /*!< Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000U) /*!< Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000U) /*!< Low-Power reset flag */ +#define RCC_CSR_RMVF_Pos (23U) +#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_CSR_FWRSTF_Pos (24U) +#define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */ +#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */ +#define RCC_CSR_OBLRSTF_Pos (25U) +#define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ +#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */ +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF_Pos (27U) +#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ /* Reference defines */ #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */ @@ -2694,292 +4532,518 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ -#define RNG_CR_RNGEN ((uint32_t)0x00000004U) -#define RNG_CR_IE ((uint32_t)0x00000008U) +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /******************** Bits definition for RNG_SR register *******************/ -#define RNG_SR_DRDY ((uint32_t)0x00000001U) -#define RNG_SR_CECS ((uint32_t)0x00000002U) -#define RNG_SR_SECS ((uint32_t)0x00000004U) -#define RNG_SR_CEIS ((uint32_t)0x00000020U) -#define RNG_SR_SEIS ((uint32_t)0x00000040U) +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk /******************************************************************************/ /* */ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +/* +* @brief Specific device feature definitions +*/ +#define RTC_TAMPER1_SUPPORT +#define RTC_TAMPER2_SUPPORT +#define RTC_WAKEUP_SUPPORT +#define RTC_BACKUP_SUPPORT + /******************** Bits definition for RTC_TR register *******************/ -#define RTC_TR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_TR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_TR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_TR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_TR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_TR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_TR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_TR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_TR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_TR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_TR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_TR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_TR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_TR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_TR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_TR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_TR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_TR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_TR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_TR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_TR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk /*!< */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk /*!< */ +#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk /*!< */ +#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */ +#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */ +#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk /*!< */ +#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk /*!< */ +#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_DR register *******************/ -#define RTC_DR_YT ((uint32_t)0x00F00000U) /*!< */ -#define RTC_DR_YT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_DR_YT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_DR_YT_2 ((uint32_t)0x00400000U) /*!< */ -#define RTC_DR_YT_3 ((uint32_t)0x00800000U) /*!< */ -#define RTC_DR_YU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_DR_YU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_DR_YU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_DR_YU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_DR_YU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_DR_WDU ((uint32_t)0x0000E000U) /*!< */ -#define RTC_DR_WDU_0 ((uint32_t)0x00002000U) /*!< */ -#define RTC_DR_WDU_1 ((uint32_t)0x00004000U) /*!< */ -#define RTC_DR_WDU_2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_DR_MT ((uint32_t)0x00001000U) /*!< */ -#define RTC_DR_MU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_DR_MU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_DR_MU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_DR_MU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_DR_MU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_DR_DT ((uint32_t)0x00000030U) /*!< */ -#define RTC_DR_DT_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_DR_DT_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_DR_DU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_DR_DU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_DR_DU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_DR_DU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_DR_DU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk /*!< */ +#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk /*!< */ +#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */ +#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk /*!< */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk /*!< */ +#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk /*!< */ +#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk /*!< */ +#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_CR register *******************/ -#define RTC_CR_COE ((uint32_t)0x00800000U) /*!< */ -#define RTC_CR_OSEL ((uint32_t)0x00600000U) /*!< */ -#define RTC_CR_OSEL_0 ((uint32_t)0x00200000U) /*!< */ -#define RTC_CR_OSEL_1 ((uint32_t)0x00400000U) /*!< */ -#define RTC_CR_POL ((uint32_t)0x00100000U) /*!< */ -#define RTC_CR_COSEL ((uint32_t)0x00080000U) /*!< */ -#define RTC_CR_BCK ((uint32_t)0x00040000U) /*!< */ -#define RTC_CR_SUB1H ((uint32_t)0x00020000U) /*!< */ -#define RTC_CR_ADD1H ((uint32_t)0x00010000U) /*!< */ -#define RTC_CR_TSIE ((uint32_t)0x00008000U) /*!< */ -#define RTC_CR_WUTIE ((uint32_t)0x00004000U) /*!< */ -#define RTC_CR_ALRBIE ((uint32_t)0x00002000U) /*!< */ -#define RTC_CR_ALRAIE ((uint32_t)0x00001000U) /*!< */ -#define RTC_CR_TSE ((uint32_t)0x00000800U) /*!< */ -#define RTC_CR_WUTE ((uint32_t)0x00000400U) /*!< */ -#define RTC_CR_ALRBE ((uint32_t)0x00000200U) /*!< */ -#define RTC_CR_ALRAE ((uint32_t)0x00000100U) /*!< */ -#define RTC_CR_FMT ((uint32_t)0x00000040U) /*!< */ -#define RTC_CR_BYPSHAD ((uint32_t)0x00000020U) /*!< */ -#define RTC_CR_REFCKON ((uint32_t)0x00000010U) /*!< */ -#define RTC_CR_TSEDGE ((uint32_t)0x00000008U) /*!< */ -#define RTC_CR_WUCKSEL ((uint32_t)0x00000007U) /*!< */ -#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004U) /*!< */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk /*!< */ +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */ +#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< */ +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */ +#define RTC_CR_BCK_Pos (18U) +#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ +#define RTC_CR_BCK RTC_CR_BCK_Msk /*!< */ +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */ +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */ +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */ +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */ +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */ +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */ +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */ +#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_ISR register ******************/ -#define RTC_ISR_RECALPF ((uint32_t)0x00010000U) /*!< */ -#define RTC_ISR_TAMP2F ((uint32_t)0x00004000U) /*!< */ -#define RTC_ISR_TAMP1F ((uint32_t)0x00002000U) /*!< */ -#define RTC_ISR_TSOVF ((uint32_t)0x00001000U) /*!< */ -#define RTC_ISR_TSF ((uint32_t)0x00000800U) /*!< */ -#define RTC_ISR_WUTF ((uint32_t)0x00000400U) /*!< */ -#define RTC_ISR_ALRBF ((uint32_t)0x00000200U) /*!< */ -#define RTC_ISR_ALRAF ((uint32_t)0x00000100U) /*!< */ -#define RTC_ISR_INIT ((uint32_t)0x00000080U) /*!< */ -#define RTC_ISR_INITF ((uint32_t)0x00000040U) /*!< */ -#define RTC_ISR_RSF ((uint32_t)0x00000020U) /*!< */ -#define RTC_ISR_INITS ((uint32_t)0x00000010U) /*!< */ -#define RTC_ISR_SHPF ((uint32_t)0x00000008U) /*!< */ -#define RTC_ISR_WUTWF ((uint32_t)0x00000004U) /*!< */ -#define RTC_ISR_ALRBWF ((uint32_t)0x00000002U) /*!< */ -#define RTC_ISR_ALRAWF ((uint32_t)0x00000001U) /*!< */ +#define RTC_ISR_RECALPF_Pos (16U) +#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */ +#define RTC_ISR_TAMP2F_Pos (14U) +#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ +#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */ +#define RTC_ISR_TAMP1F_Pos (13U) +#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ +#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */ +#define RTC_ISR_TSOVF_Pos (12U) +#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ +#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */ +#define RTC_ISR_TSF_Pos (11U) +#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ +#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */ +#define RTC_ISR_WUTF_Pos (10U) +#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ +#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */ +#define RTC_ISR_ALRBF_Pos (9U) +#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ +#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */ +#define RTC_ISR_ALRAF_Pos (8U) +#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ +#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */ +#define RTC_ISR_INIT_Pos (7U) +#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */ +#define RTC_ISR_INITF_Pos (6U) +#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */ +#define RTC_ISR_RSF_Pos (5U) +#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */ +#define RTC_ISR_INITS_Pos (4U) +#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */ +#define RTC_ISR_SHPF_Pos (3U) +#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */ +#define RTC_ISR_WUTWF_Pos (2U) +#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */ +#define RTC_ISR_ALRBWF_Pos (1U) +#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */ +#define RTC_ISR_ALRAWF_Pos (0U) +#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */ /******************** Bits definition for RTC_PRER register *****************/ -#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000U) /*!< */ -#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFFU) /*!< */ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */ /******************** Bits definition for RTC_WUTR register *****************/ -#define RTC_WUTR_WUT ((uint32_t)0x0000FFFFU) +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000U) /*!< */ -#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000U) /*!< */ -#define RTC_ALRMAR_DT ((uint32_t)0x30000000U) /*!< */ -#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000U) /*!< */ -#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000U) /*!< */ -#define RTC_ALRMAR_DU ((uint32_t)0x0F000000U) /*!< */ -#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000U) /*!< */ -#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000U) /*!< */ -#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000U) /*!< */ -#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000U) /*!< */ -#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000U) /*!< */ -#define RTC_ALRMAR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_ALRMAR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_ALRMAR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_ALRMAR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080U) /*!< */ -#define RTC_ALRMAR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_ALRMAR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */ +#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */ +#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */ +#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */ +#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */ +#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */ +#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */ +#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */ +#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000U) /*!< */ -#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000U) /*!< */ -#define RTC_ALRMBR_DT ((uint32_t)0x30000000U) /*!< */ -#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000U) /*!< */ -#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000U) /*!< */ -#define RTC_ALRMBR_DU ((uint32_t)0x0F000000U) /*!< */ -#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000U) /*!< */ -#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000U) /*!< */ -#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000U) /*!< */ -#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000U) /*!< */ -#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000U) /*!< */ -#define RTC_ALRMBR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_ALRMBR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_ALRMBR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_ALRMBR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080U) /*!< */ -#define RTC_ALRMBR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_ALRMBR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */ +#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */ +#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */ +#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */ +#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */ +#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */ +#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */ +#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */ +#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_WPR register ******************/ -#define RTC_WPR_KEY ((uint32_t)0x000000FFU) /*!< */ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */ /******************** Bits definition for RTC_SSR register ******************/ -#define RTC_SSR_SS ((uint32_t)0x0000FFFFU) /*!< */ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */ /******************** Bits definition for RTC_SHIFTR register ***************/ -#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFFU) /*!< */ -#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000U) /*!< */ +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */ +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */ /******************** Bits definition for RTC_TSTR register *****************/ -#define RTC_TSTR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_TSTR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_TSTR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_TSTR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_TSTR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_TSTR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_TSTR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_TSTR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_TSTR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_TSTR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TSTR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TSTR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_TSTR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_TSTR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_TSTR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_TSTR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_TSTR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_TSTR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_TSTR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_TSTR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */ +#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */ +#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */ +#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */ +#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */ +#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */ +#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_TSDR register *****************/ -#define RTC_TSDR_WDU ((uint32_t)0x0000E000U) /*!< */ -#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_TSDR_MT ((uint32_t)0x00001000U) /*!< */ -#define RTC_TSDR_MU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_TSDR_MU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TSDR_MU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TSDR_MU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TSDR_MU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TSDR_DT ((uint32_t)0x00000030U) /*!< */ -#define RTC_TSDR_DT_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_TSDR_DT_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_TSDR_DU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_TSDR_DU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_TSDR_DU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_TSDR_DU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_TSDR_DU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */ +#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */ +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */ +#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */ +#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */ +#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_TSSSR register ****************/ -#define RTC_TSSSR_SS ((uint32_t)0x0000FFFFU) +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /******************** Bits definition for RTC_CALR register *****************/ -#define RTC_CALR_CALP ((uint32_t)0x00008000U) /*!< */ -#define RTC_CALR_CALW8 ((uint32_t)0x00004000U) /*!< */ -#define RTC_CALR_CALW16 ((uint32_t)0x00002000U) /*!< */ -#define RTC_CALR_CALM ((uint32_t)0x000001FFU) /*!< */ -#define RTC_CALR_CALM_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_CALR_CALM_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_CALR_CALM_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_CALR_CALM_3 ((uint32_t)0x00000008U) /*!< */ -#define RTC_CALR_CALM_4 ((uint32_t)0x00000010U) /*!< */ -#define RTC_CALR_CALM_5 ((uint32_t)0x00000020U) /*!< */ -#define RTC_CALR_CALM_6 ((uint32_t)0x00000040U) /*!< */ -#define RTC_CALR_CALM_7 ((uint32_t)0x00000080U) /*!< */ -#define RTC_CALR_CALM_8 ((uint32_t)0x00000100U) /*!< */ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */ +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */ +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */ +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */ +#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ /* Legacy defines */ #define RTC_CAL_CALP RTC_CALR_CALP @@ -2997,146 +5061,296 @@ typedef struct #define RTC_CAL_CALM_8 RTC_CALR_CALM_8 /******************** Bits definition for RTC_TAMPCR register ****************/ -#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000U) /*!< */ -#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000U) /*!< */ -#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000U) /*!< */ -#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000U) /*!< */ -#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000U) /*!< */ -#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000U) /*!< */ -#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000U) /*!< */ -#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000U) /*!< */ -#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800U) /*!< */ -#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080U) /*!< */ -#define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010U) /*!< */ -#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008U) /*!< */ -#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004U) /*!< */ -#define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002U) /*!< */ -#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001U) /*!< */ +#define RTC_TAMPCR_TAMP2MF_Pos (21U) +#define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */ +#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */ +#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U) +#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */ +#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */ +#define RTC_TAMPCR_TAMP2IE_Pos (19U) +#define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */ +#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */ +#define RTC_TAMPCR_TAMP1MF_Pos (18U) +#define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */ +#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */ +#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U) +#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */ +#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */ +#define RTC_TAMPCR_TAMP1IE_Pos (16U) +#define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ +#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */ +#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) +#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */ +#define RTC_TAMPCR_TAMPPRCH_Pos (13U) +#define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */ +#define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAMPCR_TAMPFLT_Pos (11U) +#define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */ +#define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAMPCR_TAMPFREQ_Pos (8U) +#define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */ +#define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAMPCR_TAMPTS_Pos (7U) +#define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */ +#define RTC_TAMPCR_TAMP2TRG_Pos (4U) +#define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ +#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */ +#define RTC_TAMPCR_TAMP2E_Pos (3U) +#define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ +#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */ +#define RTC_TAMPCR_TAMPIE_Pos (2U) +#define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */ +#define RTC_TAMPCR_TAMP1TRG_Pos (1U) +#define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ +#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */ +#define RTC_TAMPCR_TAMP1E_Pos (0U) +#define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ +#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */ /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000U) -#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000U) -#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000U) -#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000U) -#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000U) -#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFFU) +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000U) -#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000U) -#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000U) -#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000U) -#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000U) -#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFFU) +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT_RMP ((uint32_t)0x00000002U) /*!< */ -#define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001U) /*!< */ +#define RTC_OR_OUT_RMP_Pos (1U) +#define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */ +#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */ +#define RTC_OR_ALARMOUTTYPE_Pos (0U) +#define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */ +#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */ /* Legacy defines */ #define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP /******************** Bits definition for RTC_BKP0R register ****************/ -#define RTC_BKP0R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP0R_Pos (0U) +#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP0R RTC_BKP0R_Msk /*!< */ /******************** Bits definition for RTC_BKP1R register ****************/ -#define RTC_BKP1R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP1R_Pos (0U) +#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP1R RTC_BKP1R_Msk /*!< */ /******************** Bits definition for RTC_BKP2R register ****************/ -#define RTC_BKP2R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP2R_Pos (0U) +#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP2R RTC_BKP2R_Msk /*!< */ /******************** Bits definition for RTC_BKP3R register ****************/ -#define RTC_BKP3R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP3R_Pos (0U) +#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP3R RTC_BKP3R_Msk /*!< */ /******************** Bits definition for RTC_BKP4R register ****************/ -#define RTC_BKP4R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP4R_Pos (0U) +#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP4R RTC_BKP4R_Msk /*!< */ /******************** Number of backup registers ******************************/ -#define RTC_BKP_NUMBER ((uint32_t)0x00000005U) /*!< */ +#define RTC_BKP_NUMBER (0x00000005U) /*!< */ /******************************************************************************/ /* */ /* Serial Peripheral Interface (SPI) */ /* */ /******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32L0 family) + */ +#define SPI_I2S_SUPPORT /*!< I2S support */ + /******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA ((uint32_t)0x00000001U) /*!< Clock Phase */ -#define SPI_CR1_CPOL ((uint32_t)0x00000002U) /*!< Clock Polarity */ -#define SPI_CR1_MSTR ((uint32_t)0x00000004U) /*!< Master Selection */ -#define SPI_CR1_BR ((uint32_t)0x00000038U) /*!< BR[2:0] bits (Baud Rate Control) */ -#define SPI_CR1_BR_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define SPI_CR1_BR_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ -#define SPI_CR1_BR_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ -#define SPI_CR1_SPE ((uint32_t)0x00000040U) /*!< SPI Enable */ -#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080U) /*!< Frame Format */ -#define SPI_CR1_SSI ((uint32_t)0x00000100U) /*!< Internal slave select */ -#define SPI_CR1_SSM ((uint32_t)0x00000200U) /*!< Software slave management */ -#define SPI_CR1_RXONLY ((uint32_t)0x00000400U) /*!< Receive only */ -#define SPI_CR1_DFF ((uint32_t)0x00000800U) /*!< Data Frame Format */ -#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000U) /*!< Transmit CRC next */ -#define SPI_CR1_CRCEN ((uint32_t)0x00002000U) /*!< Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE ((uint32_t)0x00004000U) /*!< Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000U) /*!< Bidirectional data mode enable */ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ +#define SPI_CR1_CPOL_Pos (1U) +#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ +#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ +#define SPI_CR1_MSTR_Pos (2U) +#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ +#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ +#define SPI_CR1_BR_Pos (3U) +#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */ +#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ +#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ +#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ +#define SPI_CR1_SPE_Pos (6U) +#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ +#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ +#define SPI_CR1_LSBFIRST_Pos (7U) +#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ +#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ +#define SPI_CR1_SSI_Pos (8U) +#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ +#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ +#define SPI_CR1_SSM_Pos (9U) +#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ +#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ +#define SPI_CR1_RXONLY_Pos (10U) +#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ +#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ +#define SPI_CR1_DFF_Pos (11U) +#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ +#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ +#define SPI_CR1_CRCNEXT_Pos (12U) +#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ +#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ +#define SPI_CR1_CRCEN_Pos (13U) +#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ +#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE_Pos (14U) +#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ +#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE_Pos (15U) +#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ +#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ /******************* Bit definition for SPI_CR2 register ********************/ -#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001U) /*!< Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002U) /*!< Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE ((uint32_t)0x00000004U) /*!< SS Output Enable */ -#define SPI_CR2_FRF ((uint32_t)0x00000010U) /*!< Frame Format Enable */ -#define SPI_CR2_ERRIE ((uint32_t)0x00000020U) /*!< Error Interrupt Enable */ -#define SPI_CR2_RXNEIE ((uint32_t)0x00000040U) /*!< RX buffer Not Empty Interrupt Enable */ -#define SPI_CR2_TXEIE ((uint32_t)0x00000080U) /*!< Tx buffer Empty Interrupt Enable */ +#define SPI_CR2_RXDMAEN_Pos (0U) +#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ +#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN_Pos (1U) +#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ +#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE_Pos (2U) +#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ +#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ +#define SPI_CR2_FRF_Pos (4U) +#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ +#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ +#define SPI_CR2_ERRIE_Pos (5U) +#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ +#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ +#define SPI_CR2_RXNEIE_Pos (6U) +#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ +#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE_Pos (7U) +#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ +#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ /******************** Bit definition for SPI_SR register ********************/ -#define SPI_SR_RXNE ((uint32_t)0x00000001U) /*!< Receive buffer Not Empty */ -#define SPI_SR_TXE ((uint32_t)0x00000002U) /*!< Transmit buffer Empty */ -#define SPI_SR_CHSIDE ((uint32_t)0x00000004U) /*!< Channel side */ -#define SPI_SR_UDR ((uint32_t)0x00000008U) /*!< Underrun flag */ -#define SPI_SR_CRCERR ((uint32_t)0x00000010U) /*!< CRC Error flag */ -#define SPI_SR_MODF ((uint32_t)0x00000020U) /*!< Mode fault */ -#define SPI_SR_OVR ((uint32_t)0x00000040U) /*!< Overrun flag */ -#define SPI_SR_BSY ((uint32_t)0x00000080U) /*!< Busy flag */ -#define SPI_SR_FRE ((uint32_t)0x00000100U) /*!< TI frame format error */ +#define SPI_SR_RXNE_Pos (0U) +#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ +#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ +#define SPI_SR_TXE_Pos (1U) +#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ +#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ +#define SPI_SR_CHSIDE_Pos (2U) +#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ +#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ +#define SPI_SR_UDR_Pos (3U) +#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */ +#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ +#define SPI_SR_CRCERR_Pos (4U) +#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ +#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ +#define SPI_SR_MODF_Pos (5U) +#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */ +#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ +#define SPI_SR_OVR_Pos (6U) +#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */ +#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ +#define SPI_SR_BSY_Pos (7U) +#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */ +#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ +#define SPI_SR_FRE_Pos (8U) +#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */ +#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ /******************** Bit definition for SPI_DR register ********************/ -#define SPI_DR_DR ((uint32_t)0x0000FFFFU) /*!< Data Register */ +#define SPI_DR_DR_Pos (0U) +#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ +#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ /******************* Bit definition for SPI_CRCPR register ******************/ -#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFFU) /*!< CRC polynomial register */ +#define SPI_CRCPR_CRCPOLY_Pos (0U) +#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ +#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ /****************** Bit definition for SPI_RXCRCR register ******************/ -#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFFU) /*!< Rx CRC Register */ +#define SPI_RXCRCR_RXCRC_Pos (0U) +#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ /****************** Bit definition for SPI_TXCRCR register ******************/ -#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFFU) /*!< Tx CRC Register */ +#define SPI_TXCRCR_TXCRC_Pos (0U) +#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ /****************** Bit definition for SPI_I2SCFGR register *****************/ -#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001U) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -83,15 +83,15 @@ #include "hal_tick.h" #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/ + #define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* MSI_VALUE */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ @@ -115,8 +115,8 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. + This value must be a multiple of 0x100. */ /******************************************************************************/ /** * @} @@ -146,8 +146,9 @@ variable is updated automatically. */ uint32_t SystemCoreClock = 32000000; -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U}; /** * @} @@ -179,25 +180,25 @@ uint8_t SetSysClock_PLL_HSI(void); void SystemInit (void) { /*!< Set MSION bit */ - RCC->CR |= (uint32_t)0x00000100; + RCC->CR |= (uint32_t)0x00000100U; /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ - RCC->CFGR &= (uint32_t) 0x88FF400C; + RCC->CFGR &= (uint32_t) 0x88FF400CU; /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFF6; + RCC->CR &= (uint32_t)0xFEF6FFF6U; /*!< Reset HSI48ON bit */ - RCC->CRRCR &= (uint32_t)0xFFFFFFFE; + RCC->CRRCR &= (uint32_t)0xFFFFFFFEU; /*!< Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; + RCC->CR &= (uint32_t)0xFFFBFFFFU; /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ - RCC->CFGR &= (uint32_t)0xFF02FFFF; + RCC->CFGR &= (uint32_t)0xFF02FFFFU; /*!< Disable all interrupts */ - RCC->CIER = 0x00000000; + RCC->CIER = 0x00000000U; /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM @@ -259,33 +260,33 @@ void SystemInit (void) */ void SystemCoreClockUpdate (void) { - uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; + uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; switch (tmp) { - case 0x00: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); + case 0x00U: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; + SystemCoreClock = (32768U * (1U << (msirange + 1U))); break; - case 0x04: /* HSI used as system clock */ + case 0x04U: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; break; - case 0x08: /* HSE used as system clock */ + case 0x08U: /* HSE used as system clock */ SystemCoreClock = HSE_VALUE; break; - case 0x0C: /* PLL used as system clock */ + case 0x0CU: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; - pllmul = PLLMulTable[(pllmul >> 18)]; - plldiv = (plldiv >> 22) + 1; + pllmul = PLLMulTable[(pllmul >> 18U)]; + plldiv = (plldiv >> 22U) + 1U; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - if (pllsource == 0x00) + if (pllsource == 0x00U) { /* HSI oscillator clock selected as PLL clock entry */ SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); @@ -297,13 +298,13 @@ void SystemCoreClockUpdate (void) } break; default: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; + SystemCoreClock = (32768U * (1U << (msirange + 1U))); break; } /* Compute HCLK clock frequency --------------------------------------------*/ /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/system_stm32l0xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/system_stm32l0xx.h index 4a82de7134..7015debf51 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/system_stm32l0xx.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/system_stm32l0xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32l0xx.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -74,6 +74,11 @@ variable is updated automatically. */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/* +*/ +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/stm32l011xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/stm32l011xx.h index e4fea50e9b..0728b40f5b 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/stm32l011xx.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/stm32l011xx.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l011xx.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for stm32l011xx devices. @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -494,55 +494,59 @@ typedef struct * @{ */ #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */ -#define FLASH_END ((uint32_t)0x08003FFFUU) /*!< FLASH end address in the alias region */ +#define FLASH_END ((uint32_t)0x08003FFFU) /*!< FLASH end address in the alias region */ #define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */ #define DATA_EEPROM_END ((uint32_t)0x080801FFU) /*!< DATA EEPROM end address in the alias region */ #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */ +#define SRAM_SIZE_MAX ((uint32_t)0x00000800U) /*!< maximum SRAM size (up to 2KBytes) */ + #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */ /*!< Peripheral memory map */ #define APBPERIPH_BASE PERIPH_BASE -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) -#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) +#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000U) -#define TIM2_BASE (APBPERIPH_BASE + 0x00000000) -#define RTC_BASE (APBPERIPH_BASE + 0x00002800) -#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00) -#define IWDG_BASE (APBPERIPH_BASE + 0x00003000) -#define USART2_BASE (APBPERIPH_BASE + 0x00004400) -#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800) -#define I2C1_BASE (APBPERIPH_BASE + 0x00005400) -#define PWR_BASE (APBPERIPH_BASE + 0x00007000) -#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00) +#define TIM2_BASE (APBPERIPH_BASE + 0x00000000U) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800U) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00U) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000U) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400U) +#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800U) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400U) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000U) +#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00U) -#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000) -#define COMP1_BASE (APBPERIPH_BASE + 0x00010018) -#define COMP2_BASE (APBPERIPH_BASE + 0x0001001C) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000U) +#define COMP1_BASE (APBPERIPH_BASE + 0x00010018U) +#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CU) #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE) -#define EXTI_BASE (APBPERIPH_BASE + 0x00010400) -#define TIM21_BASE (APBPERIPH_BASE + 0x00010800) -#define ADC1_BASE (APBPERIPH_BASE + 0x00012400) -#define ADC_BASE (APBPERIPH_BASE + 0x00012708) -#define SPI1_BASE (APBPERIPH_BASE + 0x00013000) -#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800) +#define EXTI_BASE (APBPERIPH_BASE + 0x00010400U) +#define TIM21_BASE (APBPERIPH_BASE + 0x00010800U) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400U) +#define ADC_BASE (APBPERIPH_BASE + 0x00012708U) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000U) +#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800U) -#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058) -#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8) +#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8U) -#define RCC_BASE (AHBPERIPH_BASE + 0x00001000) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */ +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */ #define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */ -#define CRC_BASE (AHBPERIPH_BASE + 0x00003000) +#define FLASHSIZE_BASE ((uint32_t)0x1FF8007CU) /*!< FLASH Size register base address */ +#define UID_BASE ((uint32_t)0x1FF80050U) /*!< Unique device ID register base address */ +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) -#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000) -#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400) -#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800) +#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000U) +#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400U) +#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800U) /** * @} @@ -613,91 +617,173 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for ADC_ISR register ******************/ -#define ADC_ISR_EOCAL ((uint32_t)0x00000800U) /*!< End of calibration flag */ -#define ADC_ISR_AWD ((uint32_t)0x00000080U) /*!< Analog watchdog flag */ -#define ADC_ISR_OVR ((uint32_t)0x00000010U) /*!< Overrun flag */ -#define ADC_ISR_EOSEQ ((uint32_t)0x00000008U) /*!< End of Sequence flag */ -#define ADC_ISR_EOC ((uint32_t)0x00000004U) /*!< End of Conversion */ -#define ADC_ISR_EOSMP ((uint32_t)0x00000002U) /*!< End of sampling flag */ -#define ADC_ISR_ADRDY ((uint32_t)0x00000001U) /*!< ADC Ready */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1U << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */ +#define ADC_ISR_AWD_Pos (7U) +#define ADC_ISR_AWD_Msk (0x1U << ADC_ISR_AWD_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */ +#define ADC_ISR_EOSEQ_Pos (3U) +#define ADC_ISR_EOSEQ_Msk (0x1U << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */ /* Old EOSEQ bit definition, maintained for legacy purpose */ #define ADC_ISR_EOS ADC_ISR_EOSEQ /******************** Bits definition for ADC_IER register ******************/ -#define ADC_IER_EOCALIE ((uint32_t)0x00000800U) /*!< Enf Of Calibration interrupt enable */ -#define ADC_IER_AWDIE ((uint32_t)0x00000080U) /*!< Analog Watchdog interrupt enable */ -#define ADC_IER_OVRIE ((uint32_t)0x00000010U) /*!< Overrun interrupt enable */ -#define ADC_IER_EOSEQIE ((uint32_t)0x00000008U) /*!< End of Sequence of conversion interrupt enable */ -#define ADC_IER_EOCIE ((uint32_t)0x00000004U) /*!< End of Conversion interrupt enable */ -#define ADC_IER_EOSMPIE ((uint32_t)0x00000002U) /*!< End of sampling interrupt enable */ -#define ADC_IER_ADRDYIE ((uint32_t)0x00000001U) /*!< ADC Ready interrupt enable */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1U << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */ +#define ADC_IER_AWDIE_Pos (7U) +#define ADC_IER_AWDIE_Msk (0x1U << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */ +#define ADC_IER_EOSEQIE_Pos (3U) +#define ADC_IER_EOSEQIE_Msk (0x1U << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */ /* Old EOSEQIE bit definition, maintained for legacy purpose */ #define ADC_IER_EOSIE ADC_IER_EOSEQIE /******************** Bits definition for ADC_CR register *******************/ -#define ADC_CR_ADCAL ((uint32_t)0x80000000U) /*!< ADC calibration */ -#define ADC_CR_ADVREGEN ((uint32_t)0x10000000U) /*!< ADC Voltage Regulator Enable */ -#define ADC_CR_ADSTP ((uint32_t)0x00000010U) /*!< ADC stop of conversion command */ -#define ADC_CR_ADSTART ((uint32_t)0x00000004U) /*!< ADC start of conversion */ -#define ADC_CR_ADDIS ((uint32_t)0x00000002U) /*!< ADC disable command */ -#define ADC_CR_ADEN ((uint32_t)0x00000001U) /*!< ADC enable control */ /*#### TBV */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */ /******************* Bits definition for ADC_CFGR1 register *****************/ -#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000U) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000U) /*!< Bit 0 */ -#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000U) /*!< Bit 1 */ -#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000U) /*!< Bit 2 */ -#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000U) /*!< Bit 3 */ -#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000U) /*!< Bit 4 */ -#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000U) /*!< Analog watchdog enable on regular channels */ -#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000U) /*!< Enable the watchdog on a single channel or on all channels */ -#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000U) /*!< Discontinuous mode on regular channels */ -#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000U) /*!< ADC auto power off */ -#define ADC_CFGR1_WAIT ((uint32_t)0x00004000U) /*!< ADC wait conversion mode */ -#define ADC_CFGR1_CONT ((uint32_t)0x00002000U) /*!< Continuous Conversion */ -#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000U) /*!< Overrun mode */ -#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00U) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ -#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ -#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ -#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0U) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ -#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ -#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100U) /*!< Bit 2 */ -#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020U) /*!< Data Alignment */ -#define ADC_CFGR1_RES ((uint32_t)0x00000018U) /*!< RES[1:0] bits (Resolution) */ -#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ -#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004U) /*!< Sequence scan direction */ -#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002U) /*!< Direct memory access configuration */ -#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001U) /*!< Direct memory access enable */ +#define ADC_CFGR1_AWDCH_Pos (26U) +#define ADC_CFGR1_AWDCH_Msk (0x1FU << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CFGR1_AWDCH_0 (0x01U << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWDCH_1 (0x02U << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWDCH_2 (0x04U << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWDCH_3 (0x08U << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWDCH_4 (0x10U << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ +#define ADC_CFGR1_AWDEN_Pos (23U) +#define ADC_CFGR1_AWDEN_Msk (0x1U << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */ +#define ADC_CFGR1_AWDSGL_Pos (22U) +#define ADC_CFGR1_AWDSGL_Msk (0x1U << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */ +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */ +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ +#define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */ +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */ /* Old WAIT bit definition, maintained for legacy purpose */ #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT /******************* Bits definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_TOVS ((uint32_t)0x80000200U) /*!< Triggered Oversampling */ -#define ADC_CFGR2_OVSS ((uint32_t)0x000001E0U) /*!< OVSS [3:0] bits (Oversampling shift) */ -#define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ -#define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ -#define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ -#define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ -#define ADC_CFGR2_OVSR ((uint32_t)0x0000001CU) /*!< OVSR [2:0] bits (Oversampling ratio) */ -#define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004U) /*!< Bit 0 */ -#define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008U) /*!< Bit 1 */ -#define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010U) /*!< Bit 2 */ -#define ADC_CFGR2_OVSE ((uint32_t)0x00000001U) /*!< Oversampler Enable */ -#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000U) /*!< CKMODE [1:0] bits (ADC clock mode) */ -#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000U) /*!< Bit 0 */ -#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000U) /*!< Bit 1 */ +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x400001U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */ +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */ +#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */ +#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1U << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */ +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */ +#define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ /****************** Bit definition for ADC_SMPR register ********************/ -#define ADC_SMPR_SMP ((uint32_t)0x00000007U) /*!< SMPR[2:0] bits (Sampling time selection) */ -#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ -#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ -#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SMPR_SMP_Pos (0U) +#define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */ +#define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ /* Legacy defines */ #define ADC_SMPR_SMPR ADC_SMPR_SMP @@ -706,45 +792,99 @@ typedef struct #define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2 /******************* Bit definition for ADC_TR register ********************/ -#define ADC_TR_HT ((uint32_t)0x0FFF0000U) /*!< Analog watchdog high threshold */ -#define ADC_TR_LT ((uint32_t)0x00000FFFU) /*!< Analog watchdog low threshold */ +#define ADC_TR_HT_Pos (16U) +#define ADC_TR_HT_Msk (0xFFFU << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */ +#define ADC_TR_LT_Pos (0U) +#define ADC_TR_LT_Msk (0xFFFU << ADC_TR_LT_Pos) /*!< 0x00000FFF */ +#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */ /****************** Bit definition for ADC_CHSELR register ******************/ -#define ADC_CHSELR_CHSEL ((uint32_t)0x0007FFFFU) /*!< ADC group regular sequencer channels */ -#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000U) /*!< Channel 18 selection */ -#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000U) /*!< Channel 17 selection */ -#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000U) /*!< Channel 15 selection */ -#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000U) /*!< Channel 14 selection */ -#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000U) /*!< Channel 13 selection */ -#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000U) /*!< Channel 12 selection */ -#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800U) /*!< Channel 11 selection */ -#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400U) /*!< Channel 10 selection */ -#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200U) /*!< Channel 9 selection */ -#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100U) /*!< Channel 8 selection */ -#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080U) /*!< Channel 7 selection */ -#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040U) /*!< Channel 6 selection */ -#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020U) /*!< Channel 5 selection */ -#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010U) /*!< Channel 4 selection */ -#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008U) /*!< Channel 3 selection */ -#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004U) /*!< Channel 2 selection */ -#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002U) /*!< Channel 1 selection */ -#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001U) /*!< Channel 0 selection */ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFFU) /*!< Regular data */ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */ /******************** Bit definition for ADC_CALFACT register ********************/ -#define ADC_CALFACT_CALFACT ((uint32_t)0x0000007FU) /*!< Calibration factor */ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FU << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */ /******************* Bit definition for ADC_CCR register ********************/ -#define ADC_CCR_LFMEN ((uint32_t)0x02000000U) /*!< Low Frequency Mode enable */ -#define ADC_CCR_TSEN ((uint32_t)0x00800000U) /*!< Temperature sensore enable */ -#define ADC_CCR_VREFEN ((uint32_t)0x00400000U) /*!< Vrefint enable */ -#define ADC_CCR_PRESC ((uint32_t)0x003C0000U) /*!< PRESC [3:0] bits (ADC prescaler) */ -#define ADC_CCR_PRESC_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ -#define ADC_CCR_PRESC_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ -#define ADC_CCR_PRESC_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ -#define ADC_CCR_PRESC_3 ((uint32_t)0x00200000U) /*!< Bit 3 */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1U << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */ +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */ +#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ /******************************************************************************/ /* */ @@ -753,37 +893,77 @@ typedef struct /******************************************************************************/ /************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/ /* COMP1 bits definition */ -#define COMP_CSR_COMP1EN ((uint32_t)0x00000001U) /*!< COMP1 enable */ -#define COMP_CSR_COMP1INNSEL ((uint32_t)0x00000030U) /*!< COMP1 inverting input select */ -#define COMP_CSR_COMP1INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP1 inverting input select bit 0 */ -#define COMP_CSR_COMP1INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP1 inverting input select bit 1 */ -#define COMP_CSR_COMP1WM ((uint32_t)0x00000100U) /*!< Comparators window mode enable */ -#define COMP_CSR_COMP1LPTIM1IN1 ((uint32_t)0x00001000U) /*!< COMP1 LPTIM1 IN1 connection */ -#define COMP_CSR_COMP1POLARITY ((uint32_t)0x00008000U) /*!< COMP1 output polarity */ -#define COMP_CSR_COMP1VALUE ((uint32_t)0x40000000U) /*!< COMP1 output level */ -#define COMP_CSR_COMP1LOCK ((uint32_t)0x80000000U) /*!< COMP1 lock */ +#define COMP_CSR_COMP1EN_Pos (0U) +#define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */ +#define COMP_CSR_COMP1INNSEL_Pos (4U) +#define COMP_CSR_COMP1INNSEL_Msk (0x3U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */ +#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */ +#define COMP_CSR_COMP1INNSEL_0 (0x1U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_COMP1INNSEL_1 (0x2U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_COMP1WM_Pos (8U) +#define COMP_CSR_COMP1WM_Msk (0x1U << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */ +#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */ +#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U) +#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */ +#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */ +#define COMP_CSR_COMP1POLARITY_Pos (15U) +#define COMP_CSR_COMP1POLARITY_Msk (0x1U << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */ +#define COMP_CSR_COMP1VALUE_Pos (30U) +#define COMP_CSR_COMP1VALUE_Msk (0x1U << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */ +#define COMP_CSR_COMP1LOCK_Pos (31U) +#define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */ /* COMP2 bits definition */ -#define COMP_CSR_COMP2EN ((uint32_t)0x00000001U) /*!< COMP2 enable */ -#define COMP_CSR_COMP2SPEED ((uint32_t)0x00000008U) /*!< COMP2 power mode */ -#define COMP_CSR_COMP2INNSEL ((uint32_t)0x00000070U) /*!< COMP2 inverting input select */ -#define COMP_CSR_COMP2INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP2 inverting input select bit 0 */ -#define COMP_CSR_COMP2INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP2 inverting input select bit 1 */ -#define COMP_CSR_COMP2INNSEL_2 ((uint32_t)0x00000040U) /*!< COMP2 inverting input select bit 2 */ -#define COMP_CSR_COMP2INPSEL ((uint32_t)0x00000700U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2INPSEL_0 ((uint32_t)0x00000100U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2INPSEL_1 ((uint32_t)0x00000200U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2INPSEL_2 ((uint32_t)0x00000400U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2LPTIM1IN2 ((uint32_t)0x00001000U) /*!< COMP2 LPTIM1 IN2 connection */ -#define COMP_CSR_COMP2LPTIM1IN1 ((uint32_t)0x00002000U) /*!< COMP2 LPTIM1 IN1 connection */ -#define COMP_CSR_COMP2POLARITY ((uint32_t)0x00008000U) /*!< COMP2 output polarity */ -#define COMP_CSR_COMP2VALUE ((uint32_t)0x40000000U) /*!< COMP2 output level */ -#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000U) /*!< COMP2 lock */ +#define COMP_CSR_COMP2EN_Pos (0U) +#define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */ +#define COMP_CSR_COMP2SPEED_Pos (3U) +#define COMP_CSR_COMP2SPEED_Msk (0x1U << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */ +#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */ +#define COMP_CSR_COMP2INNSEL_Pos (4U) +#define COMP_CSR_COMP2INNSEL_Msk (0x7U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */ +#define COMP_CSR_COMP2INNSEL_0 (0x1U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_COMP2INNSEL_1 (0x2U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_COMP2INNSEL_2 (0x4U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_COMP2INPSEL_Pos (8U) +#define COMP_CSR_COMP2INPSEL_Msk (0x7U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */ +#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */ +#define COMP_CSR_COMP2INPSEL_0 (0x1U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_COMP2INPSEL_1 (0x2U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */ +#define COMP_CSR_COMP2INPSEL_2 (0x4U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */ +#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U) +#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */ +#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */ +#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U) +#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */ +#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */ +#define COMP_CSR_COMP2POLARITY_Pos (15U) +#define COMP_CSR_COMP2POLARITY_Msk (0x1U << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */ +#define COMP_CSR_COMP2VALUE_Pos (30U) +#define COMP_CSR_COMP2VALUE_Msk (0x1U << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */ +#define COMP_CSR_COMP2LOCK_Pos (31U) +#define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */ /********************** Bit definition for COMP_CSR register common ****************/ -#define COMP_CSR_COMPxEN ((uint32_t)0x00000001U) /*!< COMPx enable */ -#define COMP_CSR_COMPxPOLARITY ((uint32_t)0x00008000U) /*!< COMPx output polarity */ -#define COMP_CSR_COMPxOUTVALUE ((uint32_t)0x40000000U) /*!< COMPx output level */ -#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000U) /*!< COMPx lock */ +#define COMP_CSR_COMPxEN_Pos (0U) +#define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */ +#define COMP_CSR_COMPxPOLARITY_Pos (15U) +#define COMP_CSR_COMPxPOLARITY_Msk (0x1U << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */ +#define COMP_CSR_COMPxOUTVALUE_Pos (30U) +#define COMP_CSR_COMPxOUTVALUE_Msk (0x1U << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */ +#define COMP_CSR_COMPxLOCK_Pos (31U) +#define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */ /* Reference defines */ #define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ @@ -794,26 +974,40 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ +#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET the CRC computation unit bit */ -#define CRC_CR_POLYSIZE ((uint32_t)0x00000018U) /*!< Polynomial size bits */ -#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008U) /*!< Polynomial size bit 0 */ -#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010U) /*!< Polynomial size bit 1 */ -#define CRC_CR_REV_IN ((uint32_t)0x00000060U) /*!< REV_IN Reverse Input Data bits */ -#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ -#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ -#define CRC_CR_REV_OUT ((uint32_t)0x00000080U) /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ /******************* Bit definition for CRC_INIT register *******************/ -#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFFU) /*!< Initial CRC value bits */ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ -#define CRC_POL_POL ((uint32_t)0xFFFFFFFFU) /*!< Coefficients of the polynomial */ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ /******************************************************************************/ /* */ @@ -822,41 +1016,67 @@ typedef struct /******************************************************************************/ /**************** Bit definition for DBGMCU_IDCODE register *****************/ -#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU) /*!< Device Identifier */ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ -#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U) /*!< REV_ID[15:0] bits (Revision Identifier) */ -#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ -#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ -#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000U) /*!< Bit 2 */ -#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000U) /*!< Bit 3 */ -#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000U) /*!< Bit 4 */ -#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000U) /*!< Bit 5 */ -#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000U) /*!< Bit 6 */ -#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000U) /*!< Bit 7 */ -#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000U) /*!< Bit 8 */ -#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000U) /*!< Bit 9 */ -#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000U) /*!< Bit 10 */ -#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000U) /*!< Bit 11 */ -#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000U) /*!< Bit 12 */ -#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000U) /*!< Bit 13 */ -#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000U) /*!< Bit 14 */ -#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000U) /*!< Bit 15 */ +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ +#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ +#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ +#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ +#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ +#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ +#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ +#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ +#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ +#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ +#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ +#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ +#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ +#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ +#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ +#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ +#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ /****************** Bit definition for DBGMCU_CR register *******************/ -#define DBGMCU_CR_DBG ((uint32_t)0x00000007U) /*!< Debug mode mask */ -#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001U) /*!< Debug Sleep Mode */ -#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U) /*!< Debug Stop Mode */ -#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U) /*!< Debug Standby mode */ +#define DBGMCU_CR_DBG_Pos (0U) +#define DBGMCU_CR_DBG_Msk (0x7U << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */ +#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */ +#define DBGMCU_CR_DBG_SLEEP_Pos (0U) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ /****************** Bit definition for DBGMCU_APB1_FZ register **************/ -#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001U) /*!< TIM2 counter stopped when core is halted */ -#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400U) /*!< RTC Calendar frozen when core is halted */ -#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800U) /*!< Debug Window Watchdog stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000U) /*!< Debug Independent Watchdog stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_I2C1_STOP ((uint32_t)0x00200000U) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP ((uint32_t)0x80000000U) /*!< LPTIM1 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) +#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */ +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U) +#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U) +#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */ +#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */ /****************** Bit definition for DBGMCU_APB2_FZ register **************/ -#define DBGMCU_APB2_FZ_DBG_TIM21_STOP ((uint32_t)0x00000004U) /*!< TIM21 counter stopped when core is halted */ +#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U) +#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */ /******************************************************************************/ /* */ @@ -865,108 +1085,209 @@ typedef struct /******************************************************************************/ /******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error flag */ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ /******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt clear */ -#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error clear */ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ /******************* Bit definition for DMA_CCR register ********************/ -#define DMA_CCR_EN ((uint32_t)0x00000001U) /*!< Channel enable */ -#define DMA_CCR_TCIE ((uint32_t)0x00000002U) /*!< Transfer complete interrupt enable */ -#define DMA_CCR_HTIE ((uint32_t)0x00000004U) /*!< Half Transfer interrupt enable */ -#define DMA_CCR_TEIE ((uint32_t)0x00000008U) /*!< Transfer error interrupt enable */ -#define DMA_CCR_DIR ((uint32_t)0x00000010U) /*!< Data transfer direction */ -#define DMA_CCR_CIRC ((uint32_t)0x00000020U) /*!< Circular mode */ -#define DMA_CCR_PINC ((uint32_t)0x00000040U) /*!< Peripheral increment mode */ -#define DMA_CCR_MINC ((uint32_t)0x00000080U) /*!< Memory increment mode */ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ -#define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */ -#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */ +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ -#define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ -#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ -#define DMA_CCR_PL ((uint32_t)0x00003000U) /*!< PL[1:0] bits(Channel Priority level)*/ -#define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ -#define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ -#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /*!< Memory to memory mode */ +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ /****************** Bit definition for DMA_CNDTR register *******************/ -#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ /****************** Bit definition for DMA_CPAR register ********************/ -#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ /****************** Bit definition for DMA_CMAR register ********************/ -#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ /******************* Bit definition for DMA_CSELR register *******************/ -#define DMA_CSELR_C1S ((uint32_t)0x0000000FU) /*!< Channel 1 Selection */ -#define DMA_CSELR_C2S ((uint32_t)0x000000F0U) /*!< Channel 2 Selection */ -#define DMA_CSELR_C3S ((uint32_t)0x00000F00U) /*!< Channel 3 Selection */ -#define DMA_CSELR_C4S ((uint32_t)0x0000F000U) /*!< Channel 4 Selection */ -#define DMA_CSELR_C5S ((uint32_t)0x000F0000U) /*!< Channel 5 Selection */ -#define DMA_CSELR_C6S ((uint32_t)0x00F00000U) /*!< Channel 6 Selection */ -#define DMA_CSELR_C7S ((uint32_t)0x0F000000U) /*!< Channel 7 Selection */ - +#define DMA_CSELR_C1S_Pos (0U) +#define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */ +#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */ +#define DMA_CSELR_C2S_Pos (4U) +#define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */ +#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */ +#define DMA_CSELR_C3S_Pos (8U) +#define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */ +#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */ +#define DMA_CSELR_C4S_Pos (12U) +#define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */ +#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */ +#define DMA_CSELR_C5S_Pos (16U) +#define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */ +#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */ /******************************************************************************/ /* */ @@ -975,88 +1296,248 @@ typedef struct /******************************************************************************/ /******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_IM0 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_IM1 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_IM2 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_IM3 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_IM4 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_IM5 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_IM6 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_IM7 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_IM8 ((uint32_t)0x00000100U) /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_IM9 ((uint32_t)0x00000200U) /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_IM10 ((uint32_t)0x00000400U) /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_IM11 ((uint32_t)0x00000800U) /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_IM12 ((uint32_t)0x00001000U) /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_IM13 ((uint32_t)0x00002000U) /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_IM14 ((uint32_t)0x00004000U) /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_IM15 ((uint32_t)0x00008000U) /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_IM16 ((uint32_t)0x00010000U) /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_IM17 ((uint32_t)0x00020000U) /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_IM18 ((uint32_t)0x00040000U) /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_IM19 ((uint32_t)0x00080000U) /*!< Interrupt Mask on line 19 */ -#define EXTI_IMR_IM20 ((uint32_t)0x00100000U) /*!< Interrupt Mask on line 20 */ -#define EXTI_IMR_IM21 ((uint32_t)0x00200000U) /*!< Interrupt Mask on line 21 */ -#define EXTI_IMR_IM22 ((uint32_t)0x00400000U) /*!< Interrupt Mask on line 22 */ -#define EXTI_IMR_IM23 ((uint32_t)0x00800000U) /*!< Interrupt Mask on line 23 */ -#define EXTI_IMR_IM25 ((uint32_t)0x02000000U) /*!< Interrupt Mask on line 25 */ -#define EXTI_IMR_IM26 ((uint32_t)0x04000000U) /*!< Interrupt Mask on line 26 */ -#define EXTI_IMR_IM28 ((uint32_t)0x10000000U) /*!< Interrupt Mask on line 28 */ -#define EXTI_IMR_IM29 ((uint32_t)0x20000000U) /*!< Interrupt Mask on line 29 */ +#define EXTI_IMR_IM0_Pos (0U) +#define EXTI_IMR_IM0_Msk (0x1U << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_IM1_Pos (1U) +#define EXTI_IMR_IM1_Msk (0x1U << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_IM2_Pos (2U) +#define EXTI_IMR_IM2_Msk (0x1U << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_IM3_Pos (3U) +#define EXTI_IMR_IM3_Msk (0x1U << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_IM4_Pos (4U) +#define EXTI_IMR_IM4_Msk (0x1U << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_IM5_Pos (5U) +#define EXTI_IMR_IM5_Msk (0x1U << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_IM6_Pos (6U) +#define EXTI_IMR_IM6_Msk (0x1U << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_IM7_Pos (7U) +#define EXTI_IMR_IM7_Msk (0x1U << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_IM8_Pos (8U) +#define EXTI_IMR_IM8_Msk (0x1U << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_IM9_Pos (9U) +#define EXTI_IMR_IM9_Msk (0x1U << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_IM10_Pos (10U) +#define EXTI_IMR_IM10_Msk (0x1U << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_IM11_Pos (11U) +#define EXTI_IMR_IM11_Msk (0x1U << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_IM12_Pos (12U) +#define EXTI_IMR_IM12_Msk (0x1U << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_IM13_Pos (13U) +#define EXTI_IMR_IM13_Msk (0x1U << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_IM14_Pos (14U) +#define EXTI_IMR_IM14_Msk (0x1U << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_IM15_Pos (15U) +#define EXTI_IMR_IM15_Msk (0x1U << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_IM16_Pos (16U) +#define EXTI_IMR_IM16_Msk (0x1U << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_IM17_Pos (17U) +#define EXTI_IMR_IM17_Msk (0x1U << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_IM18_Pos (18U) +#define EXTI_IMR_IM18_Msk (0x1U << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_IM19_Pos (19U) +#define EXTI_IMR_IM19_Msk (0x1U << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR_IM20_Pos (20U) +#define EXTI_IMR_IM20_Msk (0x1U << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */ +#define EXTI_IMR_IM21_Pos (21U) +#define EXTI_IMR_IM21_Msk (0x1U << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */ +#define EXTI_IMR_IM22_Pos (22U) +#define EXTI_IMR_IM22_Msk (0x1U << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */ +#define EXTI_IMR_IM23_Pos (23U) +#define EXTI_IMR_IM23_Msk (0x1U << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR_IM25_Pos (25U) +#define EXTI_IMR_IM25_Msk (0x1U << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR_IM26_Pos (26U) +#define EXTI_IMR_IM26_Msk (0x1U << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */ +#define EXTI_IMR_IM28_Pos (28U) +#define EXTI_IMR_IM28_Msk (0x1U << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */ +#define EXTI_IMR_IM29_Pos (29U) +#define EXTI_IMR_IM29_Msk (0x1U << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */ + +#define EXTI_IMR_IM_Pos (0U) +#define EXTI_IMR_IM_Msk (0x36FFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */ +#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ /****************** Bit definition for EXTI_EMR register ********************/ -#define EXTI_EMR_EM0 ((uint32_t)0x00000001U) /*!< Event Mask on line 0 */ -#define EXTI_EMR_EM1 ((uint32_t)0x00000002U) /*!< Event Mask on line 1 */ -#define EXTI_EMR_EM2 ((uint32_t)0x00000004U) /*!< Event Mask on line 2 */ -#define EXTI_EMR_EM3 ((uint32_t)0x00000008U) /*!< Event Mask on line 3 */ -#define EXTI_EMR_EM4 ((uint32_t)0x00000010U) /*!< Event Mask on line 4 */ -#define EXTI_EMR_EM5 ((uint32_t)0x00000020U) /*!< Event Mask on line 5 */ -#define EXTI_EMR_EM6 ((uint32_t)0x00000040U) /*!< Event Mask on line 6 */ -#define EXTI_EMR_EM7 ((uint32_t)0x00000080U) /*!< Event Mask on line 7 */ -#define EXTI_EMR_EM8 ((uint32_t)0x00000100U) /*!< Event Mask on line 8 */ -#define EXTI_EMR_EM9 ((uint32_t)0x00000200U) /*!< Event Mask on line 9 */ -#define EXTI_EMR_EM10 ((uint32_t)0x00000400U) /*!< Event Mask on line 10 */ -#define EXTI_EMR_EM11 ((uint32_t)0x00000800U) /*!< Event Mask on line 11 */ -#define EXTI_EMR_EM12 ((uint32_t)0x00001000U) /*!< Event Mask on line 12 */ -#define EXTI_EMR_EM13 ((uint32_t)0x00002000U) /*!< Event Mask on line 13 */ -#define EXTI_EMR_EM14 ((uint32_t)0x00004000U) /*!< Event Mask on line 14 */ -#define EXTI_EMR_EM15 ((uint32_t)0x00008000U) /*!< Event Mask on line 15 */ -#define EXTI_EMR_EM16 ((uint32_t)0x00010000U) /*!< Event Mask on line 16 */ -#define EXTI_EMR_EM17 ((uint32_t)0x00020000U) /*!< Event Mask on line 17 */ -#define EXTI_EMR_EM18 ((uint32_t)0x00040000U) /*!< Event Mask on line 18 */ -#define EXTI_EMR_EM19 ((uint32_t)0x00080000U) /*!< Event Mask on line 19 */ -#define EXTI_EMR_EM20 ((uint32_t)0x00100000U) /*!< Event Mask on line 20 */ -#define EXTI_EMR_EM21 ((uint32_t)0x00200000U) /*!< Event Mask on line 21 */ -#define EXTI_EMR_EM22 ((uint32_t)0x00400000U) /*!< Event Mask on line 22 */ -#define EXTI_EMR_EM23 ((uint32_t)0x00800000U) /*!< Event Mask on line 23 */ -#define EXTI_EMR_EM25 ((uint32_t)0x02000000U) /*!< Event Mask on line 25 */ -#define EXTI_EMR_EM26 ((uint32_t)0x04000000U) /*!< Event Mask on line 26 */ -#define EXTI_EMR_EM28 ((uint32_t)0x10000000U) /*!< Event Mask on line 28 */ -#define EXTI_EMR_EM29 ((uint32_t)0x20000000U) /*!< Event Mask on line 29 */ +#define EXTI_EMR_EM0_Pos (0U) +#define EXTI_EMR_EM0_Msk (0x1U << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR_EM1_Pos (1U) +#define EXTI_EMR_EM1_Msk (0x1U << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR_EM2_Pos (2U) +#define EXTI_EMR_EM2_Msk (0x1U << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR_EM3_Pos (3U) +#define EXTI_EMR_EM3_Msk (0x1U << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR_EM4_Pos (4U) +#define EXTI_EMR_EM4_Msk (0x1U << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR_EM5_Pos (5U) +#define EXTI_EMR_EM5_Msk (0x1U << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR_EM6_Pos (6U) +#define EXTI_EMR_EM6_Msk (0x1U << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR_EM7_Pos (7U) +#define EXTI_EMR_EM7_Msk (0x1U << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR_EM8_Pos (8U) +#define EXTI_EMR_EM8_Msk (0x1U << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR_EM9_Pos (9U) +#define EXTI_EMR_EM9_Msk (0x1U << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR_EM10_Pos (10U) +#define EXTI_EMR_EM10_Msk (0x1U << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR_EM11_Pos (11U) +#define EXTI_EMR_EM11_Msk (0x1U << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR_EM12_Pos (12U) +#define EXTI_EMR_EM12_Msk (0x1U << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR_EM13_Pos (13U) +#define EXTI_EMR_EM13_Msk (0x1U << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR_EM14_Pos (14U) +#define EXTI_EMR_EM14_Msk (0x1U << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR_EM15_Pos (15U) +#define EXTI_EMR_EM15_Msk (0x1U << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR_EM16_Pos (16U) +#define EXTI_EMR_EM16_Msk (0x1U << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR_EM17_Pos (17U) +#define EXTI_EMR_EM17_Msk (0x1U << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR_EM18_Pos (18U) +#define EXTI_EMR_EM18_Msk (0x1U << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */ +#define EXTI_EMR_EM19_Pos (19U) +#define EXTI_EMR_EM19_Msk (0x1U << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR_EM20_Pos (20U) +#define EXTI_EMR_EM20_Msk (0x1U << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */ +#define EXTI_EMR_EM21_Pos (21U) +#define EXTI_EMR_EM21_Msk (0x1U << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */ +#define EXTI_EMR_EM22_Pos (22U) +#define EXTI_EMR_EM22_Msk (0x1U << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */ +#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */ +#define EXTI_EMR_EM23_Pos (23U) +#define EXTI_EMR_EM23_Msk (0x1U << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR_EM25_Pos (25U) +#define EXTI_EMR_EM25_Msk (0x1U << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR_EM26_Pos (26U) +#define EXTI_EMR_EM26_Msk (0x1U << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */ +#define EXTI_EMR_EM28_Pos (28U) +#define EXTI_EMR_EM28_Msk (0x1U << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */ +#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */ +#define EXTI_EMR_EM29_Pos (29U) +#define EXTI_EMR_EM29_Msk (0x1U << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */ +#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */ /******************* Bit definition for EXTI_RTSR register ******************/ -#define EXTI_RTSR_RT0 ((uint32_t)0x00000001U) /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_RT1 ((uint32_t)0x00000002U) /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_RT2 ((uint32_t)0x00000004U) /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_RT3 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_RT4 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_RT5 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_RT6 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_RT7 ((uint32_t)0x00000080U) /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_RT8 ((uint32_t)0x00000100U) /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_RT9 ((uint32_t)0x00000200U) /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_RT10 ((uint32_t)0x00000400U) /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_RT11 ((uint32_t)0x00000800U) /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_RT12 ((uint32_t)0x00001000U) /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_RT13 ((uint32_t)0x00002000U) /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_RT14 ((uint32_t)0x00004000U) /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_RT15 ((uint32_t)0x00008000U) /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_RT16 ((uint32_t)0x00010000U) /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_RT17 ((uint32_t)0x00020000U) /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_RT19 ((uint32_t)0x00080000U) /*!< Rising trigger event configuration bit of line 19 */ -#define EXTI_RTSR_RT20 ((uint32_t)0x00100000U) /*!< Rising trigger event configuration bit of line 20 */ -#define EXTI_RTSR_RT21 ((uint32_t)0x00200000U) /*!< Rising trigger event configuration bit of line 21 */ -#define EXTI_RTSR_RT22 ((uint32_t)0x00400000U) /*!< Rising trigger event configuration bit of line 22 */ +#define EXTI_RTSR_RT0_Pos (0U) +#define EXTI_RTSR_RT0_Msk (0x1U << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_RT1_Pos (1U) +#define EXTI_RTSR_RT1_Msk (0x1U << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_RT2_Pos (2U) +#define EXTI_RTSR_RT2_Msk (0x1U << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_RT3_Pos (3U) +#define EXTI_RTSR_RT3_Msk (0x1U << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_RT4_Pos (4U) +#define EXTI_RTSR_RT4_Msk (0x1U << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_RT5_Pos (5U) +#define EXTI_RTSR_RT5_Msk (0x1U << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_RT6_Pos (6U) +#define EXTI_RTSR_RT6_Msk (0x1U << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_RT7_Pos (7U) +#define EXTI_RTSR_RT7_Msk (0x1U << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_RT8_Pos (8U) +#define EXTI_RTSR_RT8_Msk (0x1U << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_RT9_Pos (9U) +#define EXTI_RTSR_RT9_Msk (0x1U << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_RT10_Pos (10U) +#define EXTI_RTSR_RT10_Msk (0x1U << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_RT11_Pos (11U) +#define EXTI_RTSR_RT11_Msk (0x1U << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_RT12_Pos (12U) +#define EXTI_RTSR_RT12_Msk (0x1U << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_RT13_Pos (13U) +#define EXTI_RTSR_RT13_Msk (0x1U << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_RT14_Pos (14U) +#define EXTI_RTSR_RT14_Msk (0x1U << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_RT15_Pos (15U) +#define EXTI_RTSR_RT15_Msk (0x1U << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_RT16_Pos (16U) +#define EXTI_RTSR_RT16_Msk (0x1U << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_RT17_Pos (17U) +#define EXTI_RTSR_RT17_Msk (0x1U << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_RT19_Pos (19U) +#define EXTI_RTSR_RT19_Msk (0x1U << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */ +#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_RTSR_RT20_Pos (20U) +#define EXTI_RTSR_RT20_Msk (0x1U << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */ +#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ +#define EXTI_RTSR_RT21_Pos (21U) +#define EXTI_RTSR_RT21_Msk (0x1U << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */ +#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ +#define EXTI_RTSR_RT22_Pos (22U) +#define EXTI_RTSR_RT22_Msk (0x1U << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */ +#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */ /* Legacy defines */ #define EXTI_RTSR_TR0 EXTI_RTSR_RT0 @@ -1083,28 +1564,72 @@ typedef struct #define EXTI_RTSR_TR22 EXTI_RTSR_RT22 /******************* Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_FT0 ((uint32_t)0x00000001U) /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_FT1 ((uint32_t)0x00000002U) /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_FT2 ((uint32_t)0x00000004U) /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_FT3 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_FT4 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_FT5 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_FT6 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_FT7 ((uint32_t)0x00000080U) /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_FT8 ((uint32_t)0x00000100U) /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_FT9 ((uint32_t)0x00000200U) /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_FT10 ((uint32_t)0x00000400U) /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_FT11 ((uint32_t)0x00000800U) /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_FT12 ((uint32_t)0x00001000U) /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_FT13 ((uint32_t)0x00002000U) /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_FT14 ((uint32_t)0x00004000U) /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_FT15 ((uint32_t)0x00008000U) /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_FT16 ((uint32_t)0x00010000U) /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_FT17 ((uint32_t)0x00020000U) /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_FT19 ((uint32_t)0x00080000U) /*!< Falling trigger event configuration bit of line 19 */ -#define EXTI_FTSR_FT20 ((uint32_t)0x00100000U) /*!< Falling trigger event configuration bit of line 20 */ -#define EXTI_FTSR_FT21 ((uint32_t)0x00200000U) /*!< Falling trigger event configuration bit of line 21 */ -#define EXTI_FTSR_FT22 ((uint32_t)0x00400000U) /*!< Falling trigger event configuration bit of line 22 */ +#define EXTI_FTSR_FT0_Pos (0U) +#define EXTI_FTSR_FT0_Msk (0x1U << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_FT1_Pos (1U) +#define EXTI_FTSR_FT1_Msk (0x1U << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_FT2_Pos (2U) +#define EXTI_FTSR_FT2_Msk (0x1U << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_FT3_Pos (3U) +#define EXTI_FTSR_FT3_Msk (0x1U << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_FT4_Pos (4U) +#define EXTI_FTSR_FT4_Msk (0x1U << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_FT5_Pos (5U) +#define EXTI_FTSR_FT5_Msk (0x1U << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_FT6_Pos (6U) +#define EXTI_FTSR_FT6_Msk (0x1U << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_FT7_Pos (7U) +#define EXTI_FTSR_FT7_Msk (0x1U << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_FT8_Pos (8U) +#define EXTI_FTSR_FT8_Msk (0x1U << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_FT9_Pos (9U) +#define EXTI_FTSR_FT9_Msk (0x1U << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_FT10_Pos (10U) +#define EXTI_FTSR_FT10_Msk (0x1U << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_FT11_Pos (11U) +#define EXTI_FTSR_FT11_Msk (0x1U << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_FT12_Pos (12U) +#define EXTI_FTSR_FT12_Msk (0x1U << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_FT13_Pos (13U) +#define EXTI_FTSR_FT13_Msk (0x1U << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_FT14_Pos (14U) +#define EXTI_FTSR_FT14_Msk (0x1U << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_FT15_Pos (15U) +#define EXTI_FTSR_FT15_Msk (0x1U << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_FT16_Pos (16U) +#define EXTI_FTSR_FT16_Msk (0x1U << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_FT17_Pos (17U) +#define EXTI_FTSR_FT17_Msk (0x1U << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_FT19_Pos (19U) +#define EXTI_FTSR_FT19_Msk (0x1U << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */ +#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_FTSR_FT20_Pos (20U) +#define EXTI_FTSR_FT20_Msk (0x1U << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */ +#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */ +#define EXTI_FTSR_FT21_Pos (21U) +#define EXTI_FTSR_FT21_Msk (0x1U << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */ +#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ +#define EXTI_FTSR_FT22_Pos (22U) +#define EXTI_FTSR_FT22_Msk (0x1U << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */ +#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */ /* Legacy defines */ #define EXTI_FTSR_TR0 EXTI_FTSR_FT0 @@ -1131,28 +1656,72 @@ typedef struct #define EXTI_FTSR_TR22 EXTI_FTSR_FT22 /******************* Bit definition for EXTI_SWIER register *******************/ -#define EXTI_SWIER_SWI0 ((uint32_t)0x00000001U) /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWI1 ((uint32_t)0x00000002U) /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWI2 ((uint32_t)0x00000004U) /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWI3 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWI4 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWI5 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWI6 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWI7 ((uint32_t)0x00000080U) /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWI8 ((uint32_t)0x00000100U) /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWI9 ((uint32_t)0x00000200U) /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWI10 ((uint32_t)0x00000400U) /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWI11 ((uint32_t)0x00000800U) /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWI12 ((uint32_t)0x00001000U) /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWI13 ((uint32_t)0x00002000U) /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWI14 ((uint32_t)0x00004000U) /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWI15 ((uint32_t)0x00008000U) /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWI16 ((uint32_t)0x00010000U) /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWI17 ((uint32_t)0x00020000U) /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWI19 ((uint32_t)0x00080000U) /*!< Software Interrupt on line 19 */ -#define EXTI_SWIER_SWI20 ((uint32_t)0x00100000U) /*!< Software Interrupt on line 20 */ -#define EXTI_SWIER_SWI21 ((uint32_t)0x00200000U) /*!< Software Interrupt on line 21 */ -#define EXTI_SWIER_SWI22 ((uint32_t)0x00400000U) /*!< Software Interrupt on line 22 */ +#define EXTI_SWIER_SWI0_Pos (0U) +#define EXTI_SWIER_SWI0_Msk (0x1U << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWI1_Pos (1U) +#define EXTI_SWIER_SWI1_Msk (0x1U << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWI2_Pos (2U) +#define EXTI_SWIER_SWI2_Msk (0x1U << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWI3_Pos (3U) +#define EXTI_SWIER_SWI3_Msk (0x1U << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWI4_Pos (4U) +#define EXTI_SWIER_SWI4_Msk (0x1U << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWI5_Pos (5U) +#define EXTI_SWIER_SWI5_Msk (0x1U << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWI6_Pos (6U) +#define EXTI_SWIER_SWI6_Msk (0x1U << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWI7_Pos (7U) +#define EXTI_SWIER_SWI7_Msk (0x1U << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWI8_Pos (8U) +#define EXTI_SWIER_SWI8_Msk (0x1U << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWI9_Pos (9U) +#define EXTI_SWIER_SWI9_Msk (0x1U << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWI10_Pos (10U) +#define EXTI_SWIER_SWI10_Msk (0x1U << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWI11_Pos (11U) +#define EXTI_SWIER_SWI11_Msk (0x1U << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWI12_Pos (12U) +#define EXTI_SWIER_SWI12_Msk (0x1U << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWI13_Pos (13U) +#define EXTI_SWIER_SWI13_Msk (0x1U << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWI14_Pos (14U) +#define EXTI_SWIER_SWI14_Msk (0x1U << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWI15_Pos (15U) +#define EXTI_SWIER_SWI15_Msk (0x1U << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWI16_Pos (16U) +#define EXTI_SWIER_SWI16_Msk (0x1U << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWI17_Pos (17U) +#define EXTI_SWIER_SWI17_Msk (0x1U << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWI19_Pos (19U) +#define EXTI_SWIER_SWI19_Msk (0x1U << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */ +#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */ +#define EXTI_SWIER_SWI20_Pos (20U) +#define EXTI_SWIER_SWI20_Msk (0x1U << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */ +#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */ +#define EXTI_SWIER_SWI21_Pos (21U) +#define EXTI_SWIER_SWI21_Msk (0x1U << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */ +#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */ +#define EXTI_SWIER_SWI22_Pos (22U) +#define EXTI_SWIER_SWI22_Msk (0x1U << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */ +#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */ /* Legacy defines */ #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0 @@ -1179,28 +1748,72 @@ typedef struct #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22 /****************** Bit definition for EXTI_PR register *********************/ -#define EXTI_PR_PIF0 ((uint32_t)0x00000001U) /*!< Pending bit 0 */ -#define EXTI_PR_PIF1 ((uint32_t)0x00000002U) /*!< Pending bit 1 */ -#define EXTI_PR_PIF2 ((uint32_t)0x00000004U) /*!< Pending bit 2 */ -#define EXTI_PR_PIF3 ((uint32_t)0x00000008U) /*!< Pending bit 3 */ -#define EXTI_PR_PIF4 ((uint32_t)0x00000010U) /*!< Pending bit 4 */ -#define EXTI_PR_PIF5 ((uint32_t)0x00000020U) /*!< Pending bit 5 */ -#define EXTI_PR_PIF6 ((uint32_t)0x00000040U) /*!< Pending bit 6 */ -#define EXTI_PR_PIF7 ((uint32_t)0x00000080U) /*!< Pending bit 7 */ -#define EXTI_PR_PIF8 ((uint32_t)0x00000100U) /*!< Pending bit 8 */ -#define EXTI_PR_PIF9 ((uint32_t)0x00000200U) /*!< Pending bit 9 */ -#define EXTI_PR_PIF10 ((uint32_t)0x00000400U) /*!< Pending bit 10 */ -#define EXTI_PR_PIF11 ((uint32_t)0x00000800U) /*!< Pending bit 11 */ -#define EXTI_PR_PIF12 ((uint32_t)0x00001000U) /*!< Pending bit 12 */ -#define EXTI_PR_PIF13 ((uint32_t)0x00002000U) /*!< Pending bit 13 */ -#define EXTI_PR_PIF14 ((uint32_t)0x00004000U) /*!< Pending bit 14 */ -#define EXTI_PR_PIF15 ((uint32_t)0x00008000U) /*!< Pending bit 15 */ -#define EXTI_PR_PIF16 ((uint32_t)0x00010000U) /*!< Pending bit 16 */ -#define EXTI_PR_PIF17 ((uint32_t)0x00020000U) /*!< Pending bit 17 */ -#define EXTI_PR_PIF19 ((uint32_t)0x00080000U) /*!< Pending bit 19 */ -#define EXTI_PR_PIF20 ((uint32_t)0x00100000U) /*!< Pending bit 20 */ -#define EXTI_PR_PIF21 ((uint32_t)0x00200000U) /*!< Pending bit 21 */ -#define EXTI_PR_PIF22 ((uint32_t)0x00400000U) /*!< Pending bit 22 */ +#define EXTI_PR_PIF0_Pos (0U) +#define EXTI_PR_PIF0_Msk (0x1U << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */ +#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */ +#define EXTI_PR_PIF1_Pos (1U) +#define EXTI_PR_PIF1_Msk (0x1U << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */ +#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */ +#define EXTI_PR_PIF2_Pos (2U) +#define EXTI_PR_PIF2_Msk (0x1U << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */ +#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */ +#define EXTI_PR_PIF3_Pos (3U) +#define EXTI_PR_PIF3_Msk (0x1U << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */ +#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */ +#define EXTI_PR_PIF4_Pos (4U) +#define EXTI_PR_PIF4_Msk (0x1U << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */ +#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */ +#define EXTI_PR_PIF5_Pos (5U) +#define EXTI_PR_PIF5_Msk (0x1U << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */ +#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */ +#define EXTI_PR_PIF6_Pos (6U) +#define EXTI_PR_PIF6_Msk (0x1U << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */ +#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */ +#define EXTI_PR_PIF7_Pos (7U) +#define EXTI_PR_PIF7_Msk (0x1U << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */ +#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */ +#define EXTI_PR_PIF8_Pos (8U) +#define EXTI_PR_PIF8_Msk (0x1U << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */ +#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */ +#define EXTI_PR_PIF9_Pos (9U) +#define EXTI_PR_PIF9_Msk (0x1U << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */ +#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */ +#define EXTI_PR_PIF10_Pos (10U) +#define EXTI_PR_PIF10_Msk (0x1U << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */ +#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */ +#define EXTI_PR_PIF11_Pos (11U) +#define EXTI_PR_PIF11_Msk (0x1U << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */ +#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */ +#define EXTI_PR_PIF12_Pos (12U) +#define EXTI_PR_PIF12_Msk (0x1U << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */ +#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */ +#define EXTI_PR_PIF13_Pos (13U) +#define EXTI_PR_PIF13_Msk (0x1U << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */ +#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */ +#define EXTI_PR_PIF14_Pos (14U) +#define EXTI_PR_PIF14_Msk (0x1U << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */ +#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */ +#define EXTI_PR_PIF15_Pos (15U) +#define EXTI_PR_PIF15_Msk (0x1U << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */ +#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */ +#define EXTI_PR_PIF16_Pos (16U) +#define EXTI_PR_PIF16_Msk (0x1U << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */ +#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */ +#define EXTI_PR_PIF17_Pos (17U) +#define EXTI_PR_PIF17_Msk (0x1U << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */ +#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */ +#define EXTI_PR_PIF19_Pos (19U) +#define EXTI_PR_PIF19_Msk (0x1U << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */ +#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */ +#define EXTI_PR_PIF20_Pos (20U) +#define EXTI_PR_PIF20_Msk (0x1U << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */ +#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */ +#define EXTI_PR_PIF21_Pos (21U) +#define EXTI_PR_PIF21_Msk (0x1U << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */ +#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */ +#define EXTI_PR_PIF22_Pos (22U) +#define EXTI_PR_PIF22_Msk (0x1U << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */ +#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */ /* Legacy defines */ #define EXTI_PR_PR0 EXTI_PR_PIF0 @@ -1233,52 +1846,118 @@ typedef struct /******************************************************************************/ /******************* Bit definition for FLASH_ACR register ******************/ -#define FLASH_ACR_LATENCY ((uint32_t)0x00000001U) /*!< LATENCY bit (Latency) */ -#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002U) /*!< Prefetch Buffer Enable */ -#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008U) /*!< Flash mode during sleep mode */ -#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010U) /*!< Flash mode during RUN mode */ -#define FLASH_ACR_DISAB_BUF ((uint32_t)0x00000020U) /*!< Disable Buffer */ -#define FLASH_ACR_PRE_READ ((uint32_t)0x00000040U) /*!< Pre-read data address */ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */ +#define FLASH_ACR_PRFTEN_Pos (1U) +#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */ +#define FLASH_ACR_SLEEP_PD_Pos (3U) +#define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */ +#define FLASH_ACR_RUN_PD_Pos (4U) +#define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */ +#define FLASH_ACR_DISAB_BUF_Pos (5U) +#define FLASH_ACR_DISAB_BUF_Msk (0x1U << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */ +#define FLASH_ACR_PRE_READ_Pos (6U) +#define FLASH_ACR_PRE_READ_Msk (0x1U << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */ +#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */ /******************* Bit definition for FLASH_PECR register ******************/ -#define FLASH_PECR_PELOCK ((uint32_t)0x00000001U) /*!< FLASH_PECR and Flash data Lock */ -#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002U) /*!< Program matrix Lock */ -#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004U) /*!< Option byte matrix Lock */ -#define FLASH_PECR_PROG ((uint32_t)0x00000008U) /*!< Program matrix selection */ -#define FLASH_PECR_DATA ((uint32_t)0x00000010U) /*!< Data matrix selection */ -#define FLASH_PECR_FIX ((uint32_t)0x00000100U) /*!< Fixed Time Data write for Word/Half Word/Byte programming */ -#define FLASH_PECR_ERASE ((uint32_t)0x00000200U) /*!< Page erasing mode */ -#define FLASH_PECR_FPRG ((uint32_t)0x00000400U) /*!< Fast Page/Half Page programming mode */ -#define FLASH_PECR_EOPIE ((uint32_t)0x00010000U) /*!< End of programming interrupt */ -#define FLASH_PECR_ERRIE ((uint32_t)0x00020000U) /*!< Error interrupt */ -#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000U) /*!< Launch the option byte loading */ -#define FLASH_PECR_HALF_ARRAY ((uint32_t)0x00080000U) /*!< Half array mode */ +#define FLASH_PECR_PELOCK_Pos (0U) +#define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */ +#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */ +#define FLASH_PECR_PRGLOCK_Pos (1U) +#define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */ +#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */ +#define FLASH_PECR_OPTLOCK_Pos (2U) +#define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */ +#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */ +#define FLASH_PECR_PROG_Pos (3U) +#define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */ +#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */ +#define FLASH_PECR_DATA_Pos (4U) +#define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */ +#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */ +#define FLASH_PECR_FIX_Pos (8U) +#define FLASH_PECR_FIX_Msk (0x1U << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */ +#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */ +#define FLASH_PECR_ERASE_Pos (9U) +#define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */ +#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */ +#define FLASH_PECR_FPRG_Pos (10U) +#define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */ +#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */ +#define FLASH_PECR_EOPIE_Pos (16U) +#define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */ +#define FLASH_PECR_ERRIE_Pos (17U) +#define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */ +#define FLASH_PECR_OBL_LAUNCH_Pos (18U) +#define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */ +#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */ +#define FLASH_PECR_HALF_ARRAY_Pos (19U) +#define FLASH_PECR_HALF_ARRAY_Msk (0x1U << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */ +#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */ /****************** Bit definition for FLASH_PDKEYR register ******************/ -#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */ +#define FLASH_PDKEYR_PDKEYR_Pos (0U) +#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */ /****************** Bit definition for FLASH_PEKEYR register ******************/ -#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */ +#define FLASH_PEKEYR_PEKEYR_Pos (0U) +#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */ /****************** Bit definition for FLASH_PRGKEYR register ******************/ -#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFFU) /*!< Program matrix Key */ +#define FLASH_PRGKEYR_PRGKEYR_Pos (0U) +#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */ /****************** Bit definition for FLASH_OPTKEYR register ******************/ -#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFFU) /*!< Option bytes matrix Key */ +#define FLASH_OPTKEYR_OPTKEYR_Pos (0U) +#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */ /****************** Bit definition for FLASH_SR register *******************/ -#define FLASH_SR_BSY ((uint32_t)0x00000001U) /*!< Busy */ -#define FLASH_SR_EOP ((uint32_t)0x00000002U) /*!< End Of Programming*/ -#define FLASH_SR_HVOFF ((uint32_t)0x00000004U) /*!< End of high voltage */ -#define FLASH_SR_READY ((uint32_t)0x00000008U) /*!< Flash ready after low power mode */ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ +#define FLASH_SR_EOP_Pos (1U) +#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000002 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/ +#define FLASH_SR_HVOFF_Pos (2U) +#define FLASH_SR_HVOFF_Msk (0x1U << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */ +#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */ +#define FLASH_SR_READY_Pos (3U) +#define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /*!< 0x00000008 */ +#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */ -#define FLASH_SR_WRPERR ((uint32_t)0x00000100U) /*!< Write protection error */ -#define FLASH_SR_PGAERR ((uint32_t)0x00000200U) /*!< Programming Alignment Error */ -#define FLASH_SR_SIZERR ((uint32_t)0x00000400U) /*!< Size error */ -#define FLASH_SR_OPTVERR ((uint32_t)0x00000800U) /*!< Option Valid error */ -#define FLASH_SR_RDERR ((uint32_t)0x00002000U) /*!< Read protected error */ -#define FLASH_SR_NOTZEROERR ((uint32_t)0x00010000U) /*!< Not Zero error */ -#define FLASH_SR_FWWERR ((uint32_t)0x00020000U) /*!< Write/Errase operation aborted */ +#define FLASH_SR_WRPERR_Pos (8U) +#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */ +#define FLASH_SR_PGAERR_Pos (9U) +#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */ +#define FLASH_SR_SIZERR_Pos (10U) +#define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ +#define FLASH_SR_OPTVERR_Pos (11U) +#define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */ +#define FLASH_SR_RDERR_Pos (13U) +#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */ +#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */ +#define FLASH_SR_NOTZEROERR_Pos (16U) +#define FLASH_SR_NOTZEROERR_Msk (0x1U << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */ +#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */ +#define FLASH_SR_FWWERR_Pos (17U) +#define FLASH_SR_FWWERR_Msk (0x1U << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */ /* Legacy defines */ #define FLASH_SR_FWWER FLASH_SR_FWWERR @@ -1286,17 +1965,35 @@ typedef struct #define FLASH_SR_ENDHV FLASH_SR_HVOFF /****************** Bit definition for FLASH_OPTR register *******************/ -#define FLASH_OPTR_RDPROT ((uint32_t)0x000000FFU) /*!< Read Protection */ -#define FLASH_OPTR_WPRMOD ((uint32_t)0x00000100U) /*!< Selection of protection mode of WPR bits */ -#define FLASH_OPTR_BOR_LEV ((uint32_t)0x000F0000U) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ -#define FLASH_OPTR_IWDG_SW ((uint32_t)0x00100000U) /*!< IWDG_SW */ -#define FLASH_OPTR_nRST_STOP ((uint32_t)0x00200000U) /*!< nRST_STOP */ -#define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00400000U) /*!< nRST_STDBY */ -#define FLASH_OPTR_USER ((uint32_t)0x00700000U) /*!< User Option Bytes */ -#define FLASH_OPTR_BOOT1 ((uint32_t)0x80000000U) /*!< BOOT1 */ +#define FLASH_OPTR_RDPROT_Pos (0U) +#define FLASH_OPTR_RDPROT_Msk (0xFFU << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */ +#define FLASH_OPTR_WPRMOD_Pos (8U) +#define FLASH_OPTR_WPRMOD_Msk (0x1U << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */ +#define FLASH_OPTR_BOR_LEV_Pos (16U) +#define FLASH_OPTR_BOR_LEV_Msk (0xFU << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ +#define FLASH_OPTR_IWDG_SW_Pos (20U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */ +#define FLASH_OPTR_nRST_STOP_Pos (21U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (22U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_USER_Pos (20U) +#define FLASH_OPTR_USER_Msk (0x7U << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */ +#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */ +#define FLASH_OPTR_BOOT1_Pos (31U) +#define FLASH_OPTR_BOOT1_Msk (0x1U << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */ /****************** Bit definition for FLASH_WRPR register ******************/ -#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFFU) /*!< Write Protection bits */ +#define FLASH_WRPR_WRP_Pos (0U) +#define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */ /******************************************************************************/ /* */ @@ -1304,299 +2001,525 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0 ((uint32_t)0x00000003U) -#define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001U) -#define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002U) -#define GPIO_MODER_MODE1 ((uint32_t)0x0000000CU) -#define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004U) -#define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008U) -#define GPIO_MODER_MODE2 ((uint32_t)0x00000030U) -#define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010U) -#define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020U) -#define GPIO_MODER_MODE3 ((uint32_t)0x000000C0U) -#define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040U) -#define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080U) -#define GPIO_MODER_MODE4 ((uint32_t)0x00000300U) -#define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100U) -#define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200U) -#define GPIO_MODER_MODE5 ((uint32_t)0x00000C00U) -#define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400U) -#define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800U) -#define GPIO_MODER_MODE6 ((uint32_t)0x00003000U) -#define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000U) -#define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000U) -#define GPIO_MODER_MODE7 ((uint32_t)0x0000C000U) -#define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000U) -#define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000U) -#define GPIO_MODER_MODE8 ((uint32_t)0x00030000U) -#define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000U) -#define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000U) -#define GPIO_MODER_MODE9 ((uint32_t)0x000C0000U) -#define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000U) -#define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000U) -#define GPIO_MODER_MODE10 ((uint32_t)0x00300000U) -#define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000U) -#define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000U) -#define GPIO_MODER_MODE11 ((uint32_t)0x00C00000U) -#define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000U) -#define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000U) -#define GPIO_MODER_MODE12 ((uint32_t)0x03000000U) -#define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000U) -#define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000U) -#define GPIO_MODER_MODE13 ((uint32_t)0x0C000000U) -#define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000U) -#define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000U) -#define GPIO_MODER_MODE14 ((uint32_t)0x30000000U) -#define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000U) -#define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000U) -#define GPIO_MODER_MODE15 ((uint32_t)0xC0000000U) -#define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000U) -#define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000U) +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_OTYPER register *****************/ -#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001U) -#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002U) -#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004U) -#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008U) -#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010U) -#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020U) -#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040U) -#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080U) -#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100U) -#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200U) -#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400U) -#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800U) -#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000U) -#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000U) -#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000U) -#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000U) +#define GPIO_OTYPER_OT_0 (0x00000001U) +#define GPIO_OTYPER_OT_1 (0x00000002U) +#define GPIO_OTYPER_OT_2 (0x00000004U) +#define GPIO_OTYPER_OT_3 (0x00000008U) +#define GPIO_OTYPER_OT_4 (0x00000010U) +#define GPIO_OTYPER_OT_5 (0x00000020U) +#define GPIO_OTYPER_OT_6 (0x00000040U) +#define GPIO_OTYPER_OT_7 (0x00000080U) +#define GPIO_OTYPER_OT_8 (0x00000100U) +#define GPIO_OTYPER_OT_9 (0x00000200U) +#define GPIO_OTYPER_OT_10 (0x00000400U) +#define GPIO_OTYPER_OT_11 (0x00000800U) +#define GPIO_OTYPER_OT_12 (0x00001000U) +#define GPIO_OTYPER_OT_13 (0x00002000U) +#define GPIO_OTYPER_OT_14 (0x00004000U) +#define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0 ((uint32_t)0x00000003U) -#define GPIO_OSPEEDER_OSPEED0_0 ((uint32_t)0x00000001U) -#define GPIO_OSPEEDER_OSPEED0_1 ((uint32_t)0x00000002U) -#define GPIO_OSPEEDER_OSPEED1 ((uint32_t)0x0000000CU) -#define GPIO_OSPEEDER_OSPEED1_0 ((uint32_t)0x00000004U) -#define GPIO_OSPEEDER_OSPEED1_1 ((uint32_t)0x00000008U) -#define GPIO_OSPEEDER_OSPEED2 ((uint32_t)0x00000030U) -#define GPIO_OSPEEDER_OSPEED2_0 ((uint32_t)0x00000010U) -#define GPIO_OSPEEDER_OSPEED2_1 ((uint32_t)0x00000020U) -#define GPIO_OSPEEDER_OSPEED3 ((uint32_t)0x000000C0U) -#define GPIO_OSPEEDER_OSPEED3_0 ((uint32_t)0x00000040U) -#define GPIO_OSPEEDER_OSPEED3_1 ((uint32_t)0x00000080U) -#define GPIO_OSPEEDER_OSPEED4 ((uint32_t)0x00000300U) -#define GPIO_OSPEEDER_OSPEED4_0 ((uint32_t)0x00000100U) -#define GPIO_OSPEEDER_OSPEED4_1 ((uint32_t)0x00000200U) -#define GPIO_OSPEEDER_OSPEED5 ((uint32_t)0x00000C00U) -#define GPIO_OSPEEDER_OSPEED5_0 ((uint32_t)0x00000400U) -#define GPIO_OSPEEDER_OSPEED5_1 ((uint32_t)0x00000800U) -#define GPIO_OSPEEDER_OSPEED6 ((uint32_t)0x00003000U) -#define GPIO_OSPEEDER_OSPEED6_0 ((uint32_t)0x00001000U) -#define GPIO_OSPEEDER_OSPEED6_1 ((uint32_t)0x00002000U) -#define GPIO_OSPEEDER_OSPEED7 ((uint32_t)0x0000C000U) -#define GPIO_OSPEEDER_OSPEED7_0 ((uint32_t)0x00004000U) -#define GPIO_OSPEEDER_OSPEED7_1 ((uint32_t)0x00008000U) -#define GPIO_OSPEEDER_OSPEED8 ((uint32_t)0x00030000U) -#define GPIO_OSPEEDER_OSPEED8_0 ((uint32_t)0x00010000U) -#define GPIO_OSPEEDER_OSPEED8_1 ((uint32_t)0x00020000U) -#define GPIO_OSPEEDER_OSPEED9 ((uint32_t)0x000C0000U) -#define GPIO_OSPEEDER_OSPEED9_0 ((uint32_t)0x00040000U) -#define GPIO_OSPEEDER_OSPEED9_1 ((uint32_t)0x00080000U) -#define GPIO_OSPEEDER_OSPEED10 ((uint32_t)0x00300000U) -#define GPIO_OSPEEDER_OSPEED10_0 ((uint32_t)0x00100000U) -#define GPIO_OSPEEDER_OSPEED10_1 ((uint32_t)0x00200000U) -#define GPIO_OSPEEDER_OSPEED11 ((uint32_t)0x00C00000U) -#define GPIO_OSPEEDER_OSPEED11_0 ((uint32_t)0x00400000U) -#define GPIO_OSPEEDER_OSPEED11_1 ((uint32_t)0x00800000U) -#define GPIO_OSPEEDER_OSPEED12 ((uint32_t)0x03000000U) -#define GPIO_OSPEEDER_OSPEED12_0 ((uint32_t)0x01000000U) -#define GPIO_OSPEEDER_OSPEED12_1 ((uint32_t)0x02000000U) -#define GPIO_OSPEEDER_OSPEED13 ((uint32_t)0x0C000000U) -#define GPIO_OSPEEDER_OSPEED13_0 ((uint32_t)0x04000000U) -#define GPIO_OSPEEDER_OSPEED13_1 ((uint32_t)0x08000000U) -#define GPIO_OSPEEDER_OSPEED14 ((uint32_t)0x30000000U) -#define GPIO_OSPEEDER_OSPEED14_0 ((uint32_t)0x10000000U) -#define GPIO_OSPEEDER_OSPEED14_1 ((uint32_t)0x20000000U) -#define GPIO_OSPEEDER_OSPEED15 ((uint32_t)0xC0000000U) -#define GPIO_OSPEEDER_OSPEED15_0 ((uint32_t)0x40000000U) -#define GPIO_OSPEEDER_OSPEED15_1 ((uint32_t)0x80000000U) +#define GPIO_OSPEEDER_OSPEED0_Pos (0U) +#define GPIO_OSPEEDER_OSPEED0_Msk (0x3U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0_0 (0x1U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDER_OSPEED0_1 (0x2U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDER_OSPEED1_Pos (2U) +#define GPIO_OSPEEDER_OSPEED1_Msk (0x3U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1_0 (0x1U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDER_OSPEED1_1 (0x2U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDER_OSPEED2_Pos (4U) +#define GPIO_OSPEEDER_OSPEED2_Msk (0x3U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2_0 (0x1U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDER_OSPEED2_1 (0x2U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDER_OSPEED3_Pos (6U) +#define GPIO_OSPEEDER_OSPEED3_Msk (0x3U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3_0 (0x1U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDER_OSPEED3_1 (0x2U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDER_OSPEED4_Pos (8U) +#define GPIO_OSPEEDER_OSPEED4_Msk (0x3U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4_0 (0x1U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDER_OSPEED4_1 (0x2U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDER_OSPEED5_Pos (10U) +#define GPIO_OSPEEDER_OSPEED5_Msk (0x3U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5_0 (0x1U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDER_OSPEED5_1 (0x2U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDER_OSPEED6_Pos (12U) +#define GPIO_OSPEEDER_OSPEED6_Msk (0x3U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6_0 (0x1U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDER_OSPEED6_1 (0x2U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDER_OSPEED7_Pos (14U) +#define GPIO_OSPEEDER_OSPEED7_Msk (0x3U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7_0 (0x1U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDER_OSPEED7_1 (0x2U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDER_OSPEED8_Pos (16U) +#define GPIO_OSPEEDER_OSPEED8_Msk (0x3U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8_0 (0x1U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDER_OSPEED8_1 (0x2U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDER_OSPEED9_Pos (18U) +#define GPIO_OSPEEDER_OSPEED9_Msk (0x3U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9_0 (0x1U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDER_OSPEED9_1 (0x2U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDER_OSPEED10_Pos (20U) +#define GPIO_OSPEEDER_OSPEED10_Msk (0x3U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10_0 (0x1U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDER_OSPEED10_1 (0x2U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDER_OSPEED11_Pos (22U) +#define GPIO_OSPEEDER_OSPEED11_Msk (0x3U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11_0 (0x1U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDER_OSPEED11_1 (0x2U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDER_OSPEED12_Pos (24U) +#define GPIO_OSPEEDER_OSPEED12_Msk (0x3U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12_0 (0x1U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDER_OSPEED12_1 (0x2U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDER_OSPEED13_Pos (26U) +#define GPIO_OSPEEDER_OSPEED13_Msk (0x3U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13_0 (0x1U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDER_OSPEED13_1 (0x2U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDER_OSPEED14_Pos (28U) +#define GPIO_OSPEEDER_OSPEED14_Msk (0x3U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14_0 (0x1U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDER_OSPEED14_1 (0x2U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDER_OSPEED15_Pos (30U) +#define GPIO_OSPEEDER_OSPEED15_Msk (0x3U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15_0 (0x1U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDER_OSPEED15_1 (0x2U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ /******************* Bit definition for GPIO_PUPDR register ******************/ -#define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003U) -#define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001U) -#define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002U) -#define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000CU) -#define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004U) -#define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008U) -#define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030U) -#define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010U) -#define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020U) -#define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0U) -#define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040U) -#define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080U) -#define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300U) -#define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100U) -#define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200U) -#define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00U) -#define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400U) -#define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800U) -#define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000U) -#define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000U) -#define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000U) -#define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000U) -#define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000U) -#define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000U) -#define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000U) -#define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000U) -#define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000U) -#define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000U) -#define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000U) -#define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000U) -#define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000U) -#define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000U) -#define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000U) -#define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000U) -#define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000U) -#define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000U) -#define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000U) -#define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000U) -#define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000U) -#define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000U) -#define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000U) -#define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000U) -#define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000U) -#define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000U) -#define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000U) -#define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000U) -#define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000U) -#define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000U) +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ /******************* Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0 ((uint32_t)0x00000001U) -#define GPIO_IDR_ID1 ((uint32_t)0x00000002U) -#define GPIO_IDR_ID2 ((uint32_t)0x00000004U) -#define GPIO_IDR_ID3 ((uint32_t)0x00000008U) -#define GPIO_IDR_ID4 ((uint32_t)0x00000010U) -#define GPIO_IDR_ID5 ((uint32_t)0x00000020U) -#define GPIO_IDR_ID6 ((uint32_t)0x00000040U) -#define GPIO_IDR_ID7 ((uint32_t)0x00000080U) -#define GPIO_IDR_ID8 ((uint32_t)0x00000100U) -#define GPIO_IDR_ID9 ((uint32_t)0x00000200U) -#define GPIO_IDR_ID10 ((uint32_t)0x00000400U) -#define GPIO_IDR_ID11 ((uint32_t)0x00000800U) -#define GPIO_IDR_ID12 ((uint32_t)0x00001000U) -#define GPIO_IDR_ID13 ((uint32_t)0x00002000U) -#define GPIO_IDR_ID14 ((uint32_t)0x00004000U) -#define GPIO_IDR_ID15 ((uint32_t)0x00008000U) +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk /****************** Bit definition for GPIO_ODR register ********************/ -#define GPIO_ODR_OD0 ((uint32_t)0x00000001U) -#define GPIO_ODR_OD1 ((uint32_t)0x00000002U) -#define GPIO_ODR_OD2 ((uint32_t)0x00000004U) -#define GPIO_ODR_OD3 ((uint32_t)0x00000008U) -#define GPIO_ODR_OD4 ((uint32_t)0x00000010U) -#define GPIO_ODR_OD5 ((uint32_t)0x00000020U) -#define GPIO_ODR_OD6 ((uint32_t)0x00000040U) -#define GPIO_ODR_OD7 ((uint32_t)0x00000080U) -#define GPIO_ODR_OD8 ((uint32_t)0x00000100U) -#define GPIO_ODR_OD9 ((uint32_t)0x00000200U) -#define GPIO_ODR_OD10 ((uint32_t)0x00000400U) -#define GPIO_ODR_OD11 ((uint32_t)0x00000800U) -#define GPIO_ODR_OD12 ((uint32_t)0x00001000U) -#define GPIO_ODR_OD13 ((uint32_t)0x00002000U) -#define GPIO_ODR_OD14 ((uint32_t)0x00004000U) -#define GPIO_ODR_OD15 ((uint32_t)0x00008000U) +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk /****************** Bit definition for GPIO_BSRR register ********************/ -#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001U) -#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002U) -#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004U) -#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008U) -#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010U) -#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020U) -#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040U) -#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080U) -#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100U) -#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200U) -#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400U) -#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800U) -#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000U) -#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000U) -#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000U) -#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000U) -#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000U) -#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000U) -#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000U) -#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000U) -#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000U) -#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000U) -#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000U) -#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000U) -#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000U) -#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000U) -#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000U) -#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000U) -#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000U) -#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000U) -#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000U) -#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000U) +#define GPIO_BSRR_BS_0 (0x00000001U) +#define GPIO_BSRR_BS_1 (0x00000002U) +#define GPIO_BSRR_BS_2 (0x00000004U) +#define GPIO_BSRR_BS_3 (0x00000008U) +#define GPIO_BSRR_BS_4 (0x00000010U) +#define GPIO_BSRR_BS_5 (0x00000020U) +#define GPIO_BSRR_BS_6 (0x00000040U) +#define GPIO_BSRR_BS_7 (0x00000080U) +#define GPIO_BSRR_BS_8 (0x00000100U) +#define GPIO_BSRR_BS_9 (0x00000200U) +#define GPIO_BSRR_BS_10 (0x00000400U) +#define GPIO_BSRR_BS_11 (0x00000800U) +#define GPIO_BSRR_BS_12 (0x00001000U) +#define GPIO_BSRR_BS_13 (0x00002000U) +#define GPIO_BSRR_BS_14 (0x00004000U) +#define GPIO_BSRR_BS_15 (0x00008000U) +#define GPIO_BSRR_BR_0 (0x00010000U) +#define GPIO_BSRR_BR_1 (0x00020000U) +#define GPIO_BSRR_BR_2 (0x00040000U) +#define GPIO_BSRR_BR_3 (0x00080000U) +#define GPIO_BSRR_BR_4 (0x00100000U) +#define GPIO_BSRR_BR_5 (0x00200000U) +#define GPIO_BSRR_BR_6 (0x00400000U) +#define GPIO_BSRR_BR_7 (0x00800000U) +#define GPIO_BSRR_BR_8 (0x01000000U) +#define GPIO_BSRR_BR_9 (0x02000000U) +#define GPIO_BSRR_BR_10 (0x04000000U) +#define GPIO_BSRR_BR_11 (0x08000000U) +#define GPIO_BSRR_BR_12 (0x10000000U) +#define GPIO_BSRR_BR_13 (0x20000000U) +#define GPIO_BSRR_BR_14 (0x40000000U) +#define GPIO_BSRR_BR_15 (0x80000000U) /****************** Bit definition for GPIO_LCKR register ********************/ -#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U) -#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U) -#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U) -#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U) -#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U) -#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U) -#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U) -#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U) -#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U) -#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U) -#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U) -#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U) -#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U) -#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U) -#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U) -#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U) -#define GPIO_LCKR_LCKK ((uint32_t)0x00010000U) +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000FU) -#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0U) -#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00U) -#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000U) -#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000U) -#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000U) -#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000U) -#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000U) +#define GPIO_AFRL_AFRL0_Pos (0U) +#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk +#define GPIO_AFRL_AFRL1_Pos (4U) +#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk +#define GPIO_AFRL_AFRL2_Pos (8U) +#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk +#define GPIO_AFRL_AFRL3_Pos (12U) +#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk +#define GPIO_AFRL_AFRL4_Pos (16U) +#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk +#define GPIO_AFRL_AFRL5_Pos (20U) +#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk +#define GPIO_AFRL_AFRL6_Pos (24U) +#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk +#define GPIO_AFRL_AFRL7_Pos (28U) +#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000FU) -#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0U) -#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00U) -#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000U) -#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000U) -#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000U) -#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000U) -#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000U) +#define GPIO_AFRH_AFRH0_Pos (0U) +#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk +#define GPIO_AFRH_AFRH1_Pos (4U) +#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk +#define GPIO_AFRH_AFRH2_Pos (8U) +#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk +#define GPIO_AFRH_AFRH3_Pos (12U) +#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk +#define GPIO_AFRH_AFRH4_Pos (16U) +#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk +#define GPIO_AFRH_AFRH5_Pos (20U) +#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk +#define GPIO_AFRH_AFRH6_Pos (24U) +#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk +#define GPIO_AFRH_AFRH7_Pos (28U) +#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk /****************** Bit definition for GPIO_BRR register *********************/ -#define GPIO_BRR_BR_0 ((uint32_t)0x00000001U) -#define GPIO_BRR_BR_1 ((uint32_t)0x00000002U) -#define GPIO_BRR_BR_2 ((uint32_t)0x00000004U) -#define GPIO_BRR_BR_3 ((uint32_t)0x00000008U) -#define GPIO_BRR_BR_4 ((uint32_t)0x00000010U) -#define GPIO_BRR_BR_5 ((uint32_t)0x00000020U) -#define GPIO_BRR_BR_6 ((uint32_t)0x00000040U) -#define GPIO_BRR_BR_7 ((uint32_t)0x00000080U) -#define GPIO_BRR_BR_8 ((uint32_t)0x00000100U) -#define GPIO_BRR_BR_9 ((uint32_t)0x00000200U) -#define GPIO_BRR_BR_10 ((uint32_t)0x00000400U) -#define GPIO_BRR_BR_11 ((uint32_t)0x00000800U) -#define GPIO_BRR_BR_12 ((uint32_t)0x00001000U) -#define GPIO_BRR_BR_13 ((uint32_t)0x00002000U) -#define GPIO_BRR_BR_14 ((uint32_t)0x00004000U) -#define GPIO_BRR_BR_15 ((uint32_t)0x00008000U) +#define GPIO_BRR_BR_0 (0x00000001U) +#define GPIO_BRR_BR_1 (0x00000002U) +#define GPIO_BRR_BR_2 (0x00000004U) +#define GPIO_BRR_BR_3 (0x00000008U) +#define GPIO_BRR_BR_4 (0x00000010U) +#define GPIO_BRR_BR_5 (0x00000020U) +#define GPIO_BRR_BR_6 (0x00000040U) +#define GPIO_BRR_BR_7 (0x00000080U) +#define GPIO_BRR_BR_8 (0x00000100U) +#define GPIO_BRR_BR_9 (0x00000200U) +#define GPIO_BRR_BR_10 (0x00000400U) +#define GPIO_BRR_BR_11 (0x00000800U) +#define GPIO_BRR_BR_12 (0x00001000U) +#define GPIO_BRR_BR_13 (0x00002000U) +#define GPIO_BRR_BR_14 (0x00004000U) +#define GPIO_BRR_BR_15 (0x00008000U) /******************************************************************************/ /* */ @@ -1605,110 +2528,276 @@ typedef struct /******************************************************************************/ /******************* Bit definition for I2C_CR1 register *******************/ -#define I2C_CR1_PE ((uint32_t)0x00000001U) /*!< Peripheral enable */ -#define I2C_CR1_TXIE ((uint32_t)0x00000002U) /*!< TX interrupt enable */ -#define I2C_CR1_RXIE ((uint32_t)0x00000004U) /*!< RX interrupt enable */ -#define I2C_CR1_ADDRIE ((uint32_t)0x00000008U) /*!< Address match interrupt enable */ -#define I2C_CR1_NACKIE ((uint32_t)0x00000010U) /*!< NACK received interrupt enable */ -#define I2C_CR1_STOPIE ((uint32_t)0x00000020U) /*!< STOP detection interrupt enable */ -#define I2C_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transfer complete interrupt enable */ -#define I2C_CR1_ERRIE ((uint32_t)0x00000080U) /*!< Errors interrupt enable */ -#define I2C_CR1_DNF ((uint32_t)0x00000F00U) /*!< Digital noise filter */ -#define I2C_CR1_ANFOFF ((uint32_t)0x00001000U) /*!< Analog noise filter OFF */ -#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000U) /*!< DMA transmission requests enable */ -#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000U) /*!< DMA reception requests enable */ -#define I2C_CR1_SBC ((uint32_t)0x00010000U) /*!< Slave byte control */ -#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000U) /*!< Clock stretching disable */ -#define I2C_CR1_WUPEN ((uint32_t)0x00040000U) /*!< Wakeup from STOP enable */ -#define I2C_CR1_GCEN ((uint32_t)0x00080000U) /*!< General call enable */ -#define I2C_CR1_SMBHEN ((uint32_t)0x00100000U) /*!< SMBus host address enable */ -#define I2C_CR1_SMBDEN ((uint32_t)0x00200000U) /*!< SMBus device default address enable */ -#define I2C_CR1_ALERTEN ((uint32_t)0x00400000U) /*!< SMBus alert enable */ -#define I2C_CR1_PECEN ((uint32_t)0x00800000U) /*!< PEC enable */ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ /****************** Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_SADD ((uint32_t)0x000003FFU) /*!< Slave address (master mode) */ -#define I2C_CR2_RD_WRN ((uint32_t)0x00000400U) /*!< Transfer direction (master mode) */ -#define I2C_CR2_ADD10 ((uint32_t)0x00000800U) /*!< 10-bit addressing mode (master mode) */ -#define I2C_CR2_HEAD10R ((uint32_t)0x00001000U) /*!< 10-bit address header only read direction (master mode) */ -#define I2C_CR2_START ((uint32_t)0x00002000U) /*!< START generation */ -#define I2C_CR2_STOP ((uint32_t)0x00004000U) /*!< STOP generation (master mode) */ -#define I2C_CR2_NACK ((uint32_t)0x00008000U) /*!< NACK generation (slave mode) */ -#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000U) /*!< Number of bytes */ -#define I2C_CR2_RELOAD ((uint32_t)0x01000000U) /*!< NBYTES reload mode */ -#define I2C_CR2_AUTOEND ((uint32_t)0x02000000U) /*!< Automatic end mode (master mode) */ -#define I2C_CR2_PECBYTE ((uint32_t)0x04000000U) /*!< Packet error checking byte */ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ /******************* Bit definition for I2C_OAR1 register ******************/ -#define I2C_OAR1_OA1 ((uint32_t)0x000003FFU) /*!< Interface own address 1 */ -#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400U) /*!< Own address 1 10-bit mode */ -#define I2C_OAR1_OA1EN ((uint32_t)0x00008000U) /*!< Own address 1 enable */ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ /******************* Bit definition for I2C_OAR2 register ******************/ -#define I2C_OAR2_OA2 ((uint32_t)0x000000FEU) /*!< Interface own address 2 */ -#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700U) /*!< Own address 2 masks */ -#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000U) /*!< No mask */ -#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100U) /*!< OA2[1] is masked, Only OA2[7:2] are compared */ -#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200U) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ -#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300U) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ -#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400U) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ -#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500U) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ -#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600U) /*!< OA2[6:1] is masked, Only OA2[7] are compared */ -#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700U) /*!< OA2[7:1] is masked, No comparison is done */ -#define I2C_OAR2_OA2EN ((uint32_t)0x00008000U) /*!< Own address 2 enable */ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ /******************* Bit definition for I2C_TIMINGR register *******************/ -#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FFU) /*!< SCL low period (master mode) */ -#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00U) /*!< SCL high period (master mode) */ -#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000U) /*!< Data hold time */ -#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000U) /*!< Data setup time */ -#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000U) /*!< Timings prescaler */ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ /******************* Bit definition for I2C_TIMEOUTR register *******************/ -#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFFU) /*!< Bus timeout A */ -#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000U) /*!< Idle clock timeout detection */ -#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000U) /*!< Clock timeout enable */ -#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000U) /*!< Bus timeout B*/ -#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000U) /*!< Extended clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ /****************** Bit definition for I2C_ISR register *********************/ -#define I2C_ISR_TXE ((uint32_t)0x00000001U) /*!< Transmit data register empty */ -#define I2C_ISR_TXIS ((uint32_t)0x00000002U) /*!< Transmit interrupt status */ -#define I2C_ISR_RXNE ((uint32_t)0x00000004U) /*!< Receive data register not empty */ -#define I2C_ISR_ADDR ((uint32_t)0x00000008U) /*!< Address matched (slave mode)*/ -#define I2C_ISR_NACKF ((uint32_t)0x00000010U) /*!< NACK received flag */ -#define I2C_ISR_STOPF ((uint32_t)0x00000020U) /*!< STOP detection flag */ -#define I2C_ISR_TC ((uint32_t)0x00000040U) /*!< Transfer complete (master mode) */ -#define I2C_ISR_TCR ((uint32_t)0x00000080U) /*!< Transfer complete reload */ -#define I2C_ISR_BERR ((uint32_t)0x00000100U) /*!< Bus error */ -#define I2C_ISR_ARLO ((uint32_t)0x00000200U) /*!< Arbitration lost */ -#define I2C_ISR_OVR ((uint32_t)0x00000400U) /*!< Overrun/Underrun */ -#define I2C_ISR_PECERR ((uint32_t)0x00000800U) /*!< PEC error in reception */ -#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000U) /*!< Timeout or Tlow detection flag */ -#define I2C_ISR_ALERT ((uint32_t)0x00002000U) /*!< SMBus alert */ -#define I2C_ISR_BUSY ((uint32_t)0x00008000U) /*!< Bus busy */ -#define I2C_ISR_DIR ((uint32_t)0x00010000U) /*!< Transfer direction (slave mode) */ -#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000U) /*!< Address match code (slave mode) */ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ /****************** Bit definition for I2C_ICR register *********************/ -#define I2C_ICR_ADDRCF ((uint32_t)0x00000008U) /*!< Address matched clear flag */ -#define I2C_ICR_NACKCF ((uint32_t)0x00000010U) /*!< NACK clear flag */ -#define I2C_ICR_STOPCF ((uint32_t)0x00000020U) /*!< STOP detection clear flag */ -#define I2C_ICR_BERRCF ((uint32_t)0x00000100U) /*!< Bus error clear flag */ -#define I2C_ICR_ARLOCF ((uint32_t)0x00000200U) /*!< Arbitration lost clear flag */ -#define I2C_ICR_OVRCF ((uint32_t)0x00000400U) /*!< Overrun/Underrun clear flag */ -#define I2C_ICR_PECCF ((uint32_t)0x00000800U) /*!< PAC error clear flag */ -#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000U) /*!< Timeout clear flag */ -#define I2C_ICR_ALERTCF ((uint32_t)0x00002000U) /*!< Alert clear flag */ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ /****************** Bit definition for I2C_PECR register *********************/ -#define I2C_PECR_PEC ((uint32_t)0x000000FFU) /*!< PEC register */ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ /****************** Bit definition for I2C_RXDR register *********************/ -#define I2C_RXDR_RXDATA ((uint32_t)0x000000FFU) /*!< 8-bit receive data */ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ /****************** Bit definition for I2C_TXDR register *********************/ -#define I2C_TXDR_TXDATA ((uint32_t)0x000000FFU) /*!< 8-bit transmit data */ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ /******************************************************************************/ /* */ @@ -1716,24 +2805,38 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_KR_KEY ((uint32_t)0x0000FFFFU) /*!< Key value (write only, read 0000h) */ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ /******************* Bit definition for IWDG_PR register ********************/ -#define IWDG_PR_PR ((uint32_t)0x00000007U) /*!< PR[2:0] (Prescaler divider) */ -#define IWDG_PR_PR_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ -#define IWDG_PR_PR_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ -#define IWDG_PR_PR_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define IWDG_PR_PR_Pos (0U) +#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ +#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */ +#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */ +#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */ /******************* Bit definition for IWDG_RLR register *******************/ -#define IWDG_RLR_RL ((uint32_t)0x00000FFFU) /*!< Watchdog counter reload value */ +#define IWDG_RLR_RL_Pos (0U) +#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ +#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ /******************* Bit definition for IWDG_SR register ********************/ -#define IWDG_SR_PVU ((uint32_t)0x00000001U) /*!< Watchdog prescaler value update */ -#define IWDG_SR_RVU ((uint32_t)0x00000002U) /*!< Watchdog counter reload value update */ -#define IWDG_SR_WVU ((uint32_t)0x00000004U) /*!< Watchdog counter window value update */ +#define IWDG_SR_PVU_Pos (0U) +#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ +#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ +#define IWDG_SR_RVU_Pos (1U) +#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ +#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ +#define IWDG_SR_WVU_Pos (2U) +#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ +#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ /******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_WINR_WIN ((uint32_t)0x00000FFFU) /*!< Watchdog counter window value */ +#define IWDG_WINR_WIN_Pos (0U) +#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ +#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ /******************************************************************************/ /* */ @@ -1741,81 +2844,161 @@ typedef struct /* */ /******************************************************************************/ /****************** Bit definition for LPTIM_ISR register *******************/ -#define LPTIM_ISR_CMPM ((uint32_t)0x00000001U) /*!< Compare match */ -#define LPTIM_ISR_ARRM ((uint32_t)0x00000002U) /*!< Autoreload match */ -#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004U) /*!< External trigger edge event */ -#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008U) /*!< Compare register update OK */ -#define LPTIM_ISR_ARROK ((uint32_t)0x00000010U) /*!< Autoreload register update OK */ -#define LPTIM_ISR_UP ((uint32_t)0x00000020U) /*!< Counter direction change down to up */ -#define LPTIM_ISR_DOWN ((uint32_t)0x00000040U) /*!< Counter direction change up to down */ +#define LPTIM_ISR_CMPM_Pos (0U) +#define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */ +#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */ +#define LPTIM_ISR_ARRM_Pos (1U) +#define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */ +#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */ +#define LPTIM_ISR_EXTTRIG_Pos (2U) +#define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */ +#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */ +#define LPTIM_ISR_CMPOK_Pos (3U) +#define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */ +#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */ +#define LPTIM_ISR_ARROK_Pos (4U) +#define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */ +#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */ +#define LPTIM_ISR_UP_Pos (5U) +#define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */ +#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */ +#define LPTIM_ISR_DOWN_Pos (6U) +#define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */ +#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */ /****************** Bit definition for LPTIM_ICR register *******************/ -#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001U) /*!< Compare match Clear Flag */ -#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002U) /*!< Autoreload match Clear Flag */ -#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004U) /*!< External trigger edge event Clear Flag */ -#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008U) /*!< Compare register update OK Clear Flag */ -#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010U) /*!< Autoreload register update OK Clear Flag */ -#define LPTIM_ICR_UPCF ((uint32_t)0x00000020U) /*!< Counter direction change down to up Clear Flag */ -#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040U) /*!< Counter direction change up to down Clear Flag */ +#define LPTIM_ICR_CMPMCF_Pos (0U) +#define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */ +#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */ +#define LPTIM_ICR_ARRMCF_Pos (1U) +#define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */ +#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */ +#define LPTIM_ICR_EXTTRIGCF_Pos (2U) +#define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */ +#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */ +#define LPTIM_ICR_CMPOKCF_Pos (3U) +#define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */ +#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */ +#define LPTIM_ICR_ARROKCF_Pos (4U) +#define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */ +#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */ +#define LPTIM_ICR_UPCF_Pos (5U) +#define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */ +#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */ +#define LPTIM_ICR_DOWNCF_Pos (6U) +#define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */ +#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */ /****************** Bit definition for LPTIM_IER register ********************/ -#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001U) /*!< Compare match Interrupt Enable */ -#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002U) /*!< Autoreload match Interrupt Enable */ -#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004U) /*!< External trigger edge event Interrupt Enable */ -#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008U) /*!< Compare register update OK Interrupt Enable */ -#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010U) /*!< Autoreload register update OK Interrupt Enable */ -#define LPTIM_IER_UPIE ((uint32_t)0x00000020U) /*!< Counter direction change down to up Interrupt Enable */ -#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040U) /*!< Counter direction change up to down Interrupt Enable */ +#define LPTIM_IER_CMPMIE_Pos (0U) +#define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */ +#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */ +#define LPTIM_IER_ARRMIE_Pos (1U) +#define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */ +#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */ +#define LPTIM_IER_EXTTRIGIE_Pos (2U) +#define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */ +#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */ +#define LPTIM_IER_CMPOKIE_Pos (3U) +#define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */ +#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */ +#define LPTIM_IER_ARROKIE_Pos (4U) +#define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */ +#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */ +#define LPTIM_IER_UPIE_Pos (5U) +#define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */ +#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */ +#define LPTIM_IER_DOWNIE_Pos (6U) +#define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */ +#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */ /****************** Bit definition for LPTIM_CFGR register *******************/ -#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001U) /*!< Clock selector */ +#define LPTIM_CFGR_CKSEL_Pos (0U) +#define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */ +#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */ -#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006U) /*!< CKPOL[1:0] bits (Clock polarity) */ -#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002U) /*!< Bit 0 */ -#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004U) /*!< Bit 1 */ +#define LPTIM_CFGR_CKPOL_Pos (1U) +#define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */ +#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */ +#define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */ +#define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */ -#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018U) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ -#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ +#define LPTIM_CFGR_CKFLT_Pos (3U) +#define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */ +#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ +#define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */ +#define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */ -#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0U) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ -#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ -#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ +#define LPTIM_CFGR_TRGFLT_Pos (6U) +#define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */ +#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ +#define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */ +#define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */ -#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00U) /*!< PRESC[2:0] bits (Clock prescaler) */ -#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200U) /*!< Bit 0 */ -#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400U) /*!< Bit 1 */ -#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800U) /*!< Bit 2 */ +#define LPTIM_CFGR_PRESC_Pos (9U) +#define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */ +#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */ +#define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */ +#define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */ +#define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */ -#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000U) /*!< TRIGSEL[2:0]] bits (Trigger selector) */ -#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000U) /*!< Bit 0 */ -#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000U) /*!< Bit 1 */ -#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000U) /*!< Bit 2 */ +#define LPTIM_CFGR_TRIGSEL_Pos (13U) +#define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */ +#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */ +#define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */ +#define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */ +#define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */ -#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000U) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ -#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000U) /*!< Bit 0 */ -#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000U) /*!< Bit 1 */ +#define LPTIM_CFGR_TRIGEN_Pos (17U) +#define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */ +#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ +#define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */ +#define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */ -#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000U) /*!< Timout enable */ -#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000U) /*!< Waveform shape */ -#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000U) /*!< Waveform shape polarity */ -#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000U) /*!< Reg update mode */ -#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000U) /*!< Counter mode enable */ -#define LPTIM_CFGR_ENC ((uint32_t)0x01000000U) /*!< Encoder mode enable */ +#define LPTIM_CFGR_TIMOUT_Pos (19U) +#define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */ +#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */ +#define LPTIM_CFGR_WAVE_Pos (20U) +#define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */ +#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */ +#define LPTIM_CFGR_WAVPOL_Pos (21U) +#define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */ +#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */ +#define LPTIM_CFGR_PRELOAD_Pos (22U) +#define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */ +#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */ +#define LPTIM_CFGR_COUNTMODE_Pos (23U) +#define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */ +#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */ +#define LPTIM_CFGR_ENC_Pos (24U) +#define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */ +#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */ /****************** Bit definition for LPTIM_CR register ********************/ -#define LPTIM_CR_ENABLE ((uint32_t)0x00000001U) /*!< LPTIMer enable */ -#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002U) /*!< Timer start in single mode */ -#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004U) /*!< Timer start in continuous mode */ +#define LPTIM_CR_ENABLE_Pos (0U) +#define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */ +#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */ +#define LPTIM_CR_SNGSTRT_Pos (1U) +#define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */ +#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */ +#define LPTIM_CR_CNTSTRT_Pos (2U) +#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */ +#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */ /****************** Bit definition for LPTIM_CMP register *******************/ -#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFFU) /*!< Compare register */ +#define LPTIM_CMP_CMP_Pos (0U) +#define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */ +#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */ /****************** Bit definition for LPTIM_ARR register *******************/ -#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!< Auto reload register */ +#define LPTIM_ARR_ARR_Pos (0U) +#define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */ +#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */ /****************** Bit definition for LPTIM_CNT register *******************/ -#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!< Counter register */ +#define LPTIM_CNT_CNT_Pos (0U) +#define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */ +#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */ /******************************************************************************/ /* */ @@ -1823,50 +3006,96 @@ typedef struct /* */ /******************************************************************************/ -/******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPSDSR ((uint32_t)0x00000001U) /*!< Low-power deepsleep/sleep/low power run */ -#define PWR_CR_PDDS ((uint32_t)0x00000002U) /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF ((uint32_t)0x00000004U) /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF ((uint32_t)0x00000008U) /*!< Clear Standby Flag */ -#define PWR_CR_PVDE ((uint32_t)0x00000010U) /*!< Power Voltage Detector Enable */ +#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */ -#define PWR_CR_PLS ((uint32_t)0x000000E0U) /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ -#define PWR_CR_PLS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ -#define PWR_CR_PLS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPSDSR_Pos (0U) +#define PWR_CR_LPSDSR_Msk (0x1U << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */ +#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */ +#define PWR_CR_PDDS_Pos (1U) +#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ +#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF_Pos (2U) +#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ +#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF_Pos (3U) +#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ +#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ +#define PWR_CR_PVDE_Pos (4U) +#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS_Pos (5U) +#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ +#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ +#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ +#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ /*!< PVD level configuration */ -#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000U) /*!< PVD level 0 */ -#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020U) /*!< PVD level 1 */ -#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040U) /*!< PVD level 2 */ -#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060U) /*!< PVD level 3 */ -#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080U) /*!< PVD level 4 */ -#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0U) /*!< PVD level 5 */ -#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0U) /*!< PVD level 6 */ -#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0U) /*!< PVD level 7 */ +#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ +#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */ +#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */ +#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */ +#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */ +#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */ +#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */ +#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */ -#define PWR_CR_DBP ((uint32_t)0x00000100U) /*!< Disable Backup Domain write protection */ -#define PWR_CR_ULP ((uint32_t)0x00000200U) /*!< Ultra Low Power mode */ -#define PWR_CR_FWU ((uint32_t)0x00000400U) /*!< Fast wakeup */ +#define PWR_CR_DBP_Pos (8U) +#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ +#define PWR_CR_ULP_Pos (9U) +#define PWR_CR_ULP_Msk (0x1U << PWR_CR_ULP_Pos) /*!< 0x00000200 */ +#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */ +#define PWR_CR_FWU_Pos (10U) +#define PWR_CR_FWU_Msk (0x1U << PWR_CR_FWU_Pos) /*!< 0x00000400 */ +#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */ -#define PWR_CR_VOS ((uint32_t)0x00001800U) /*!< VOS[1:0] bits (Voltage scaling range selection) */ -#define PWR_CR_VOS_0 ((uint32_t)0x00000800U) /*!< Bit 0 */ -#define PWR_CR_VOS_1 ((uint32_t)0x00001000U) /*!< Bit 1 */ -#define PWR_CR_DSEEKOFF ((uint32_t)0x00002000U) /*!< Deep Sleep mode with EEPROM kept Off */ -#define PWR_CR_LPRUN ((uint32_t)0x00004000U) /*!< Low power run mode */ -#define PWR_CR_LPDS ((uint32_t)0x00010000U) /*!< regulator in low power deepsleep mode */ +#define PWR_CR_VOS_Pos (11U) +#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x00001800 */ +#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */ +#define PWR_CR_VOS_0 (0x1U << PWR_CR_VOS_Pos) /*!< 0x00000800 */ +#define PWR_CR_VOS_1 (0x2U << PWR_CR_VOS_Pos) /*!< 0x00001000 */ +#define PWR_CR_DSEEKOFF_Pos (13U) +#define PWR_CR_DSEEKOFF_Msk (0x1U << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */ +#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */ +#define PWR_CR_LPRUN_Pos (14U) +#define PWR_CR_LPRUN_Msk (0x1U << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */ +#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */ +#define PWR_CR_LPDS_Pos (16U) +#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00010000 */ +#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< regulator in low power deepsleep mode */ /******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint32_t)0x00000001U) /*!< Wakeup Flag */ -#define PWR_CSR_SBF ((uint32_t)0x00000002U) /*!< Standby Flag */ -#define PWR_CSR_PVDO ((uint32_t)0x00000004U) /*!< PVD Output */ -#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008U) /*!< Internal voltage reference (VREFINT) ready flag */ -#define PWR_CSR_VOSF ((uint32_t)0x00000010U) /*!< Voltage Scaling select flag */ -#define PWR_CSR_REGLPF ((uint32_t)0x00000020U) /*!< Regulator LP flag */ +#define PWR_CSR_WUF_Pos (0U) +#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ +#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ +#define PWR_CSR_SBF_Pos (1U) +#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ +#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ +#define PWR_CSR_PVDO_Pos (2U) +#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ +#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ +#define PWR_CSR_VREFINTRDYF_Pos (3U) +#define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */ +#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */ +#define PWR_CSR_VOSF_Pos (4U) +#define PWR_CSR_VOSF_Msk (0x1U << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */ +#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */ +#define PWR_CSR_REGLPF_Pos (5U) +#define PWR_CSR_REGLPF_Msk (0x1U << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */ +#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */ -#define PWR_CSR_EWUP1 ((uint32_t)0x00000100U) /*!< Enable WKUP pin 1 */ -#define PWR_CSR_EWUP2 ((uint32_t)0x00000200U) /*!< Enable WKUP pin 2 */ -#define PWR_CSR_EWUP3 ((uint32_t)0x00000400U) /*!< Enable WKUP pin 3 */ +#define PWR_CSR_EWUP1_Pos (8U) +#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ +#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ +#define PWR_CSR_EWUP2_Pos (9U) +#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ +#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ +#define PWR_CSR_EWUP3_Pos (10U) +#define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */ +#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */ /******************************************************************************/ /* */ @@ -1874,167 +3103,260 @@ typedef struct /* */ /******************************************************************************/ + /******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION ((uint32_t)0x00000001U) /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIKERON ((uint32_t)0x00000002U) /*!< Internal High Speed clock enable for some IPs Kernel */ -#define RCC_CR_HSIRDY ((uint32_t)0x00000004U) /*!< Internal High Speed clock ready flag */ -#define RCC_CR_HSIDIVEN ((uint32_t)0x00000008U) /*!< Internal High Speed clock divider enable */ -#define RCC_CR_HSIDIVF ((uint32_t)0x00000010U) /*!< Internal High Speed clock divider flag */ -#define RCC_CR_HSIOUTEN ((uint32_t)0x00000020U) /*!< Internal High Speed clock out enable */ -#define RCC_CR_MSION ((uint32_t)0x00000100U) /*!< Internal Multi Speed clock enable */ -#define RCC_CR_MSIRDY ((uint32_t)0x00000200U) /*!< Internal Multi Speed clock ready flag */ -#define RCC_CR_HSEON ((uint32_t)0x00010000U) /*!< External High Speed clock enable */ -#define RCC_CR_HSERDY ((uint32_t)0x00020000U) /*!< External High Speed clock ready flag */ -#define RCC_CR_HSEBYP ((uint32_t)0x00040000U) /*!< External High Speed clock Bypass */ -#define RCC_CR_RTCPRE ((uint32_t)0x00300000U) /*!< RTC prescaler [1:0] bits */ -#define RCC_CR_RTCPRE_0 ((uint32_t)0x00100000U) /*!< RTC prescaler Bit 0 */ -#define RCC_CR_RTCPRE_1 ((uint32_t)0x00200000U) /*!< RTC prescaler Bit 1 */ -#define RCC_CR_PLLON ((uint32_t)0x01000000U) /*!< PLL enable */ -#define RCC_CR_PLLRDY ((uint32_t)0x02000000U) /*!< PLL clock ready flag */ +#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIKERON_Pos (1U) +#define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */ +#define RCC_CR_HSIRDY_Pos (2U) +#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSIDIVEN_Pos (3U) +#define RCC_CR_HSIDIVEN_Msk (0x1U << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */ +#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */ +#define RCC_CR_HSIDIVF_Pos (4U) +#define RCC_CR_HSIDIVF_Msk (0x1U << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */ +#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */ +#define RCC_CR_HSIOUTEN_Pos (5U) +#define RCC_CR_HSIOUTEN_Msk (0x1U << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */ +#define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */ +#define RCC_CR_MSION_Pos (8U) +#define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000100 */ +#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */ +#define RCC_CR_MSIRDY_Pos (9U) +#define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */ +#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ +#define RCC_CR_RTCPRE_Pos (20U) +#define RCC_CR_RTCPRE_Msk (0x3U << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */ +#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */ +#define RCC_CR_RTCPRE_0 (0x1U << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */ +#define RCC_CR_RTCPRE_1 (0x2U << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */ +#define RCC_CR_PLLON_Pos (24U) +#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ +#define RCC_CR_PLLRDY_Pos (25U) +#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ /* Reference defines */ /******************** Bit definition for RCC_ICSCR register *****************/ -#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FFU) /*!< Internal High Speed clock Calibration */ -#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00U) /*!< Internal High Speed clock trimming */ +#define RCC_ICSCR_HSICAL_Pos (0U) +#define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */ +#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ +#define RCC_ICSCR_HSITRIM_Pos (8U) +#define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ -#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000U) /*!< Internal Multi Speed clock Range */ -#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000U) /*!< Internal Multi Speed clock Range 65.536 KHz */ -#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000U) /*!< Internal Multi Speed clock Range 131.072 KHz */ -#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000U) /*!< Internal Multi Speed clock Range 262.144 KHz */ -#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000U) /*!< Internal Multi Speed clock Range 524.288 KHz */ -#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000U) /*!< Internal Multi Speed clock Range 1.048 MHz */ -#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000U) /*!< Internal Multi Speed clock Range 2.097 MHz */ -#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000U) /*!< Internal Multi Speed clock Range 4.194 MHz */ -#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000U) /*!< Internal Multi Speed clock Calibration */ -#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000U) /*!< Internal Multi Speed clock trimming */ +#define RCC_ICSCR_MSIRANGE_Pos (13U) +#define RCC_ICSCR_MSIRANGE_Msk (0x7U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */ +#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */ +#define RCC_ICSCR_MSIRANGE_0 (0x0U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */ +#define RCC_ICSCR_MSIRANGE_1 (0x1U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */ +#define RCC_ICSCR_MSIRANGE_2 (0x2U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */ +#define RCC_ICSCR_MSIRANGE_3 (0x3U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */ +#define RCC_ICSCR_MSIRANGE_4 (0x4U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */ +#define RCC_ICSCR_MSIRANGE_5 (0x5U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */ +#define RCC_ICSCR_MSIRANGE_6 (0x6U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */ +#define RCC_ICSCR_MSICAL_Pos (16U) +#define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */ +#define RCC_ICSCR_MSITRIM_Pos (24U) +#define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */ +#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */ /******************* Bit definition for RCC_CFGR register *******************/ /*!< SW configuration */ -#define RCC_CFGR_SW ((uint32_t)0x00000003U) /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ -#define RCC_CFGR_SW_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ -#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000U) /*!< MSI selected as system clock */ -#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001U) /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002U) /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003U) /*!< PLL selected as system clock */ +#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */ +#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */ /*!< SWS configuration */ -#define RCC_CFGR_SWS ((uint32_t)0x0000000CU) /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004U) /*!< Bit 0 */ -#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008U) /*!< Bit 1 */ +#define RCC_CFGR_SWS_Pos (2U) +#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ +#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ -#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004U) /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008U) /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000CU) /*!< PLL used as system clock */ +#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */ /*!< HPRE configuration */ -#define RCC_CFGR_HPRE ((uint32_t)0x000000F0U) /*!< HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010U) /*!< Bit 0 */ -#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020U) /*!< Bit 1 */ -#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040U) /*!< Bit 2 */ -#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080U) /*!< Bit 3 */ +#define RCC_CFGR_HPRE_Pos (4U) +#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ +#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ +#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ -#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000U) /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080U) /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090U) /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0U) /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0U) /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0U) /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0U) /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0U) /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0U) /*!< SYSCLK divided by 512 */ +#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ /*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700U) /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */ -#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */ -#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */ +#define RCC_CFGR_PPRE1_Pos (8U) +#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ +#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ +#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ +#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ -#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400U) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500U) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600U) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700U) /*!< HCLK divided by 16 */ +#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */ /*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800U) /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800U) /*!< Bit 0 */ -#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000U) /*!< Bit 1 */ -#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000U) /*!< Bit 2 */ +#define RCC_CFGR_PPRE2_Pos (11U) +#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ +#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ +#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ +#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ -#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000U) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800U) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000U) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800U) /*!< HCLK divided by 16 */ +#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */ -#define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000U) /*!< Wake Up from Stop Clock selection */ +#define RCC_CFGR_STOPWUCK_Pos (15U) +#define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */ +#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */ /*!< PLL entry clock source*/ -#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000U) /*!< PLL entry clock source */ +#define RCC_CFGR_PLLSRC_Pos (16U) +#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ +#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ -#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000U) /*!< HSI as PLL entry clock source */ -#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000U) /*!< HSE as PLL entry clock source */ +#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */ +#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */ /*!< PLLMUL configuration */ -#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000U) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ -#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ -#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ -#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000U) /*!< Bit 3 */ +#define RCC_CFGR_PLLMUL_Pos (18U) +#define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ -#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000U) /*!< PLL input clock * 3 */ -#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000U) /*!< PLL input clock * 4 */ -#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000U) /*!< PLL input clock * 6 */ -#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000U) /*!< PLL input clock * 8 */ -#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000U) /*!< PLL input clock * 12 */ -#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000U) /*!< PLL input clock * 16 */ -#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000U) /*!< PLL input clock * 24 */ -#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000U) /*!< PLL input clock * 32 */ -#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000U) /*!< PLL input clock * 48 */ +#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */ +#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */ +#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */ +#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */ +#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */ +#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */ +#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */ +#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */ +#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */ /*!< PLLDIV configuration */ -#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000U) /*!< PLLDIV[1:0] bits (PLL Output Division) */ -#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000U) /*!< Bit0 */ -#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000U) /*!< Bit1 */ +#define RCC_CFGR_PLLDIV_Pos (22U) +#define RCC_CFGR_PLLDIV_Msk (0x3U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */ +#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */ +#define RCC_CFGR_PLLDIV_0 (0x1U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_PLLDIV_1 (0x2U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */ -#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000U) /*!< PLL clock output = CKVCO / 2 */ -#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000U) /*!< PLL clock output = CKVCO / 3 */ -#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000U) /*!< PLL clock output = CKVCO / 4 */ +#define RCC_CFGR_PLLDIV2_Pos (22U) +#define RCC_CFGR_PLLDIV2_Msk (0x1U << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */ +#define RCC_CFGR_PLLDIV3_Pos (23U) +#define RCC_CFGR_PLLDIV3_Msk (0x1U << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */ +#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */ +#define RCC_CFGR_PLLDIV4_Pos (22U) +#define RCC_CFGR_PLLDIV4_Msk (0x3U << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */ +#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */ /*!< MCO configuration */ -#define RCC_CFGR_MCOSEL ((uint32_t)0x0F000000U) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ -#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ -#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ -#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000U) /*!< Bit 2 */ -#define RCC_CFGR_MCOSEL_3 ((uint32_t)0x08000000U) /*!< Bit 3 */ +#define RCC_CFGR_MCOSEL_Pos (24U) +#define RCC_CFGR_MCOSEL_Msk (0xFU << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */ +#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */ +#define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ +#define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */ -#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */ -#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000U) /*!< System clock selected as MCO source */ -#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000U) /*!< Internal 16 MHz RC oscillator clock selected */ -#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000U) /*!< Internal Medium Speed RC oscillator clock selected */ -#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000U) /*!< External 1-25 MHz oscillator clock selected */ -#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000U) /*!< PLL clock divided */ -#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000U) /*!< LSI selected */ -#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000U) /*!< LSE selected */ +#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */ +#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U) +#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */ +#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */ +#define RCC_CFGR_MCOSEL_HSI_Pos (25U) +#define RCC_CFGR_MCOSEL_HSI_Msk (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */ +#define RCC_CFGR_MCOSEL_MSI_Pos (24U) +#define RCC_CFGR_MCOSEL_MSI_Msk (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */ +#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */ +#define RCC_CFGR_MCOSEL_HSE_Pos (26U) +#define RCC_CFGR_MCOSEL_HSE_Msk (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */ +#define RCC_CFGR_MCOSEL_PLL_Pos (24U) +#define RCC_CFGR_MCOSEL_PLL_Msk (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */ +#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */ +#define RCC_CFGR_MCOSEL_LSI_Pos (25U) +#define RCC_CFGR_MCOSEL_LSI_Msk (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */ +#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */ +#define RCC_CFGR_MCOSEL_LSE_Pos (24U) +#define RCC_CFGR_MCOSEL_LSE_Msk (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */ +#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */ -#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000U) /*!< MCO prescaler */ -#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */ -#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */ -#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000U) /*!< MCO is divided by 8 */ +#define RCC_CFGR_MCOPRE_Pos (28U) +#define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ +#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */ +#define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ +#define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ -#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000U) /*!< MCO is divided by 1 */ -#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */ -#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */ -#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000U) /*!< MCO is divided by 8 */ -#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000U) /*!< MCO is divided by 16 */ +#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ +#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ +#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ +#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ +#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ /* Legacy defines */ +#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK +#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK +#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI +#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI +#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE +#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL +#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI +#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE +#ifdef RCC_CFGR_MCOSEL_HSI48 +#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48 +#endif + #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */ #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */ #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */ @@ -2043,44 +3365,92 @@ typedef struct #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */ /*!<****************** Bit definition for RCC_CIER register ********************/ -#define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Enable */ -#define RCC_CIER_LSERDYIE ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Enable */ -#define RCC_CIER_HSIRDYIE ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Enable */ -#define RCC_CIER_HSERDYIE ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Enable */ -#define RCC_CIER_PLLRDYIE ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Enable */ -#define RCC_CIER_MSIRDYIE ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Enable */ -#define RCC_CIER_CSSLSE ((uint32_t)0x00000080U) /*!< LSE CSS Interrupt Enable */ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ +#define RCC_CIER_HSIRDYIE_Pos (2U) +#define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ +#define RCC_CIER_HSERDYIE_Pos (3U) +#define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ +#define RCC_CIER_PLLRDYIE_Pos (4U) +#define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ +#define RCC_CIER_MSIRDYIE_Pos (5U) +#define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */ +#define RCC_CIER_CSSLSE_Pos (7U) +#define RCC_CIER_CSSLSE_Msk (0x1U << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */ /* Reference defines */ #define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE /*!<****************** Bit definition for RCC_CIFR register ********************/ -#define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt flag */ -#define RCC_CIFR_LSERDYF ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt flag */ -#define RCC_CIFR_HSIRDYF ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt flag */ -#define RCC_CIFR_HSERDYF ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt flag */ -#define RCC_CIFR_PLLRDYF ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt flag */ -#define RCC_CIFR_MSIRDYF ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt flag */ -#define RCC_CIFR_CSSLSEF ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt flag */ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ +#define RCC_CIFR_HSIRDYF_Pos (2U) +#define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ +#define RCC_CIFR_HSERDYF_Pos (3U) +#define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ +#define RCC_CIFR_PLLRDYF_Pos (4U) +#define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ +#define RCC_CIFR_MSIRDYF_Pos (5U) +#define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */ +#define RCC_CIFR_CSSLSEF_Pos (7U) +#define RCC_CIFR_CSSLSEF_Msk (0x1U << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */ /* Reference defines */ #define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF /*!<****************** Bit definition for RCC_CICR register ********************/ -#define RCC_CICR_LSIRDYC ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Clear */ -#define RCC_CICR_LSERDYC ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Clear */ -#define RCC_CICR_HSIRDYC ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Clear */ -#define RCC_CICR_HSERDYC ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Clear */ -#define RCC_CICR_PLLRDYC ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Clear */ -#define RCC_CICR_MSIRDYC ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Clear */ -#define RCC_CICR_CSSLSEC ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt Clear */ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ +#define RCC_CICR_HSIRDYC_Pos (2U) +#define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ +#define RCC_CICR_HSERDYC_Pos (3U) +#define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ +#define RCC_CICR_PLLRDYC_Pos (4U) +#define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ +#define RCC_CICR_MSIRDYC_Pos (5U) +#define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */ +#define RCC_CICR_CSSLSEC_Pos (7U) +#define RCC_CICR_CSSLSEC_Msk (0x1U << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */ /* Reference defines */ #define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC /***************** Bit definition for RCC_IOPRSTR register ******************/ -#define RCC_IOPRSTR_IOPARST ((uint32_t)0x00000001U) /*!< GPIO port A reset */ -#define RCC_IOPRSTR_IOPBRST ((uint32_t)0x00000002U) /*!< GPIO port B reset */ -#define RCC_IOPRSTR_IOPCRST ((uint32_t)0x00000004U) /*!< GPIO port C reset */ +#define RCC_IOPRSTR_IOPARST_Pos (0U) +#define RCC_IOPRSTR_IOPARST_Msk (0x1U << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */ +#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */ +#define RCC_IOPRSTR_IOPBRST_Pos (1U) +#define RCC_IOPRSTR_IOPBRST_Msk (0x1U << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */ +#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */ +#define RCC_IOPRSTR_IOPCRST_Pos (2U) +#define RCC_IOPRSTR_IOPCRST_Msk (0x1U << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */ +#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */ /* Reference defines */ #define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */ @@ -2089,37 +3459,73 @@ typedef struct /****************** Bit definition for RCC_AHBRST register ******************/ -#define RCC_AHBRSTR_DMARST ((uint32_t)0x00000001U) /*!< DMA1 reset */ -#define RCC_AHBRSTR_MIFRST ((uint32_t)0x00000100U) /*!< Memory interface reset reset */ -#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000U) /*!< CRC reset */ +#define RCC_AHBRSTR_DMARST_Pos (0U) +#define RCC_AHBRSTR_DMARST_Msk (0x1U << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */ +#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */ +#define RCC_AHBRSTR_MIFRST_Pos (8U) +#define RCC_AHBRSTR_MIFRST_Msk (0x1U << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */ +#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset reset */ +#define RCC_AHBRSTR_CRCRST_Pos (12U) +#define RCC_AHBRSTR_CRCRST_Msk (0x1U << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */ /* Reference defines */ #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */ /***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001U) /*!< SYSCFG clock reset */ -#define RCC_APB2RSTR_TIM21RST ((uint32_t)0x00000004U) /*!< TIM21 clock reset */ -#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200U) /*!< ADC1 clock reset */ -#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000U) /*!< SPI1 clock reset */ -#define RCC_APB2RSTR_DBGRST ((uint32_t)0x00400000U) /*!< DBGMCU clock reset */ +#define RCC_APB2RSTR_SYSCFGRST_Pos (0U) +#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ +#define RCC_APB2RSTR_TIM21RST_Pos (2U) +#define RCC_APB2RSTR_TIM21RST_Msk (0x1U << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 clock reset */ +#define RCC_APB2RSTR_ADCRST_Pos (9U) +#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 clock reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ +#define RCC_APB2RSTR_DBGRST_Pos (22U) +#define RCC_APB2RSTR_DBGRST_Msk (0x1U << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU clock reset */ /* Reference defines */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 clock reset */ #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU clock reset */ /***************** Bit definition for RCC_APB1RSTR register *****************/ -#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001U) /*!< Timer 2 clock reset */ -#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800U) /*!< Window Watchdog clock reset */ -#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000U) /*!< USART 2 clock reset */ -#define RCC_APB1RSTR_LPUART1RST ((uint32_t)0x00040000U) /*!< LPUART1 clock reset */ -#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000U) /*!< I2C 1 clock reset */ -#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000U) /*!< PWR clock reset */ -#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x80000000U) /*!< LPTIM1 clock reset */ +#define RCC_APB1RSTR_TIM2RST_Pos (0U) +#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ +#define RCC_APB1RSTR_WWDGRST_Pos (11U) +#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ +#define RCC_APB1RSTR_USART2RST_Pos (17U) +#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ +#define RCC_APB1RSTR_LPUART1RST_Pos (18U) +#define RCC_APB1RSTR_LPUART1RST_Msk (0x1U << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 clock reset */ +#define RCC_APB1RSTR_I2C1RST_Pos (21U) +#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ +#define RCC_APB1RSTR_PWRRST_Pos (28U) +#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ +#define RCC_APB1RSTR_LPTIM1RST_Pos (31U) +#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 clock reset */ /***************** Bit definition for RCC_IOPENR register ******************/ -#define RCC_IOPENR_IOPAEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enable */ -#define RCC_IOPENR_IOPBEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enable */ -#define RCC_IOPENR_IOPCEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enable */ +#define RCC_IOPENR_IOPAEN_Pos (0U) +#define RCC_IOPENR_IOPAEN_Msk (0x1U << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */ +#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */ +#define RCC_IOPENR_IOPBEN_Pos (1U) +#define RCC_IOPENR_IOPBEN_Msk (0x1U << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */ +#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */ +#define RCC_IOPENR_IOPCEN_Pos (2U) +#define RCC_IOPENR_IOPCEN_Msk (0x1U << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */ +#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */ /* Reference defines */ #define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */ @@ -2127,20 +3533,38 @@ typedef struct #define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */ /***************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001U) /*!< DMA1 clock enable */ -#define RCC_AHBENR_MIFEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable bit */ -#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000U) /*!< CRC clock enable */ +#define RCC_AHBENR_DMAEN_Pos (0U) +#define RCC_AHBENR_DMAEN_Msk (0x1U << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */ +#define RCC_AHBENR_MIFEN_Pos (8U) +#define RCC_AHBENR_MIFEN_Msk (0x1U << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */ +#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */ +#define RCC_AHBENR_CRCEN_Pos (12U) +#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ /* Reference defines */ #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ /***************** Bit definition for RCC_APB2ENR register ******************/ -#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enable */ -#define RCC_APB2ENR_TIM21EN ((uint32_t)0x00000004U) /*!< TIM21 clock enable */ -#define RCC_APB2ENR_FWEN ((uint32_t)0x00000080U) /*!< MiFare Firewall clock enable */ -#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200U) /*!< ADC1 clock enable */ -#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000U) /*!< SPI1 clock enable */ -#define RCC_APB2ENR_DBGEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enable */ +#define RCC_APB2ENR_SYSCFGEN_Pos (0U) +#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */ +#define RCC_APB2ENR_TIM21EN_Pos (2U) +#define RCC_APB2ENR_TIM21EN_Msk (0x1U << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */ +#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */ +#define RCC_APB2ENR_FWEN_Pos (7U) +#define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */ +#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */ +#define RCC_APB2ENR_ADCEN_Pos (9U) +#define RCC_APB2ENR_ADCEN_Msk (0x1U << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */ +#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ +#define RCC_APB2ENR_DBGEN_Pos (22U) +#define RCC_APB2ENR_DBGEN_Msk (0x1U << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */ /* Reference defines */ @@ -2149,18 +3573,38 @@ typedef struct #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */ /***************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001U) /*!< Timer 2 clock enable */ -#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enable */ -#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000U) /*!< USART2 clock enable */ -#define RCC_APB1ENR_LPUART1EN ((uint32_t)0x00040000U) /*!< LPUART1 clock enable */ -#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000U) /*!< I2C1 clock enable */ -#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000U) /*!< PWR clock enable */ -#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enable */ +#define RCC_APB1ENR_TIM2EN_Pos (0U) +#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */ +#define RCC_APB1ENR_WWDGEN_Pos (11U) +#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_USART2EN_Pos (17U) +#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */ +#define RCC_APB1ENR_LPUART1EN_Pos (18U) +#define RCC_APB1ENR_LPUART1EN_Msk (0x1U << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */ +#define RCC_APB1ENR_I2C1EN_Pos (21U) +#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */ +#define RCC_APB1ENR_PWREN_Pos (28U) +#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ +#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */ +#define RCC_APB1ENR_LPTIM1EN_Pos (31U) +#define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */ /****************** Bit definition for RCC_IOPSMENR register ****************/ -#define RCC_IOPSMENR_IOPASMEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enabled in sleep mode */ -#define RCC_IOPSMENR_IOPBSMEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enabled in sleep mode */ -#define RCC_IOPSMENR_IOPCSMEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPASMEN_Pos (0U) +#define RCC_IOPSMENR_IOPASMEN_Msk (0x1U << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */ +#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPBSMEN_Pos (1U) +#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1U << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */ +#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPCSMEN_Pos (2U) +#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1U << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */ +#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */ /* Reference defines */ #define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */ @@ -2168,91 +3612,175 @@ typedef struct #define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */ /***************** Bit definition for RCC_AHBSMENR register ******************/ -#define RCC_AHBSMENR_DMASMEN ((uint32_t)0x00000001U) /*!< DMA1 clock enabled in sleep mode */ -#define RCC_AHBSMENR_MIFSMEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable during sleep mode */ -#define RCC_AHBSMENR_SRAMSMEN ((uint32_t)0x00000200U) /*!< SRAM clock enabled in sleep mode */ -#define RCC_AHBSMENR_CRCSMEN ((uint32_t)0x00001000U) /*!< CRC clock enabled in sleep mode */ +#define RCC_AHBSMENR_DMASMEN_Pos (0U) +#define RCC_AHBSMENR_DMASMEN_Msk (0x1U << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */ +#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */ +#define RCC_AHBSMENR_MIFSMEN_Pos (8U) +#define RCC_AHBSMENR_MIFSMEN_Msk (0x1U << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */ +#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */ +#define RCC_AHBSMENR_SRAMSMEN_Pos (9U) +#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1U << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */ +#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */ +#define RCC_AHBSMENR_CRCSMEN_Pos (12U) +#define RCC_AHBSMENR_CRCSMEN_Msk (0x1U << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */ +#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */ /* Reference defines */ #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */ /***************** Bit definition for RCC_APB2SMENR register ******************/ -#define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enabled in sleep mode */ -#define RCC_APB2SMENR_TIM21SMEN ((uint32_t)0x00000004U) /*!< TIM21 clock enabled in sleep mode */ -#define RCC_APB2SMENR_ADCSMEN ((uint32_t)0x00000200U) /*!< ADC1 clock enabled in sleep mode */ -#define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000U) /*!< SPI1 clock enabled in sleep mode */ -#define RCC_APB2SMENR_DBGSMEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enabled in sleep mode */ +#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U) +#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */ +#define RCC_APB2SMENR_TIM21SMEN_Pos (2U) +#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1U << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */ +#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */ +#define RCC_APB2SMENR_ADCSMEN_Pos (9U) +#define RCC_APB2SMENR_ADCSMEN_Msk (0x1U << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */ +#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */ +#define RCC_APB2SMENR_SPI1SMEN_Pos (12U) +#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */ +#define RCC_APB2SMENR_DBGSMEN_Pos (22U) +#define RCC_APB2SMENR_DBGSMEN_Msk (0x1U << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */ /* Reference defines */ #define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */ #define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */ /***************** Bit definition for RCC_APB1SMENR register ******************/ -#define RCC_APB1SMENR_TIM2SMEN ((uint32_t)0x00000001U) /*!< Timer 2 clock enabled in sleep mode */ -#define RCC_APB1SMENR_WWDGSMEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enabled in sleep mode */ -#define RCC_APB1SMENR_USART2SMEN ((uint32_t)0x00020000U) /*!< USART2 clock enabled in sleep mode */ -#define RCC_APB1SMENR_LPUART1SMEN ((uint32_t)0x00040000U) /*!< LPUART1 clock enabled in sleep mode */ -#define RCC_APB1SMENR_I2C1SMEN ((uint32_t)0x00200000U) /*!< I2C1 clock enabled in sleep mode */ -#define RCC_APB1SMENR_PWRSMEN ((uint32_t)0x10000000U) /*!< PWR clock enabled in sleep mode */ -#define RCC_APB1SMENR_LPTIM1SMEN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enabled in sleep mode */ +#define RCC_APB1SMENR_TIM2SMEN_Pos (0U) +#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */ +#define RCC_APB1SMENR_WWDGSMEN_Pos (11U) +#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */ +#define RCC_APB1SMENR_USART2SMEN_Pos (17U) +#define RCC_APB1SMENR_USART2SMEN_Msk (0x1U << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */ +#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U) +#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */ +#define RCC_APB1SMENR_I2C1SMEN_Pos (21U) +#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */ +#define RCC_APB1SMENR_PWRSMEN_Pos (28U) +#define RCC_APB1SMENR_PWRSMEN_Msk (0x1U << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */ +#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */ +#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U) +#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */ +#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */ /*!< USART2 Clock source selection */ -#define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000CU) /*!< USART2SEL[1:0] bits */ -#define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004U) /*!< Bit 0 */ -#define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008U) /*!< Bit 1 */ +#define RCC_CCIPR_USART2SEL_Pos (2U) +#define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */ +#define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */ /*!< LPUART1 Clock source selection */ -#define RCC_CCIPR_LPUART1SEL ((uint32_t)0x0000C00) /*!< LPUART1SEL[1:0] bits */ -#define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x0000400) /*!< Bit 0 */ -#define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x0000800) /*!< Bit 1 */ +#define RCC_CCIPR_LPUART1SEL_Pos (10U) +#define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */ +#define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */ +#define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */ /*!< I2C1 Clock source selection */ -#define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000U) /*!< I2C1SEL [1:0] bits */ -#define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ -#define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define RCC_CCIPR_I2C1SEL_Pos (12U) +#define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */ +#define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */ /*!< LPTIM1 Clock source selection */ -#define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000U) /*!< LPTIM1SEL [1:0] bits */ -#define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ -#define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ +#define RCC_CCIPR_LPTIM1SEL_Pos (18U) +#define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */ +#define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */ /******************* Bit definition for RCC_CSR register *******************/ -#define RCC_CSR_LSION ((uint32_t)0x00000001U) /*!< Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY ((uint32_t)0x00000002U) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_LSEON ((uint32_t)0x00000100U) /*!< External Low Speed oscillator enable */ -#define RCC_CSR_LSERDY ((uint32_t)0x00000200U) /*!< External Low Speed oscillator Ready */ -#define RCC_CSR_LSEBYP ((uint32_t)0x00000400U) /*!< External Low Speed oscillator Bypass */ +#define RCC_CSR_LSEON_Pos (8U) +#define RCC_CSR_LSEON_Msk (0x1U << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */ +#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */ +#define RCC_CSR_LSERDY_Pos (9U) +#define RCC_CSR_LSERDY_Msk (0x1U << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */ +#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ +#define RCC_CSR_LSEBYP_Pos (10U) +#define RCC_CSR_LSEBYP_Msk (0x1U << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ -#define RCC_CSR_LSEDRV ((uint32_t)0x00001800U) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ -#define RCC_CSR_LSEDRV_0 ((uint32_t)0x00000800U) /*!< Bit 0 */ -#define RCC_CSR_LSEDRV_1 ((uint32_t)0x00001000U) /*!< Bit 1 */ +#define RCC_CSR_LSEDRV_Pos (11U) +#define RCC_CSR_LSEDRV_Msk (0x3U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */ +#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ +#define RCC_CSR_LSEDRV_0 (0x1U << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */ +#define RCC_CSR_LSEDRV_1 (0x2U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */ -#define RCC_CSR_LSECSSON ((uint32_t)0x00002000U) /*!< External Low Speed oscillator CSS Enable */ -#define RCC_CSR_LSECSSD ((uint32_t)0x00004000U) /*!< External Low Speed oscillator CSS Detected */ +#define RCC_CSR_LSECSSON_Pos (13U) +#define RCC_CSR_LSECSSON_Msk (0x1U << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */ +#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */ +#define RCC_CSR_LSECSSD_Pos (14U) +#define RCC_CSR_LSECSSD_Msk (0x1U << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ +#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ /*!< RTC congiguration */ -#define RCC_CSR_RTCSEL ((uint32_t)0x00030000U) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ -#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ +#define RCC_CSR_RTCSEL_Pos (16U) +#define RCC_CSR_RTCSEL_Msk (0x3U << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ +#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_CSR_RTCSEL_0 (0x1U << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */ +#define RCC_CSR_RTCSEL_1 (0x2U << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */ -#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */ -#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000U) /*!< LSE oscillator clock used as RTC clock */ -#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000U) /*!< LSI oscillator clock used as RTC clock */ -#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000U) /*!< HSE oscillator clock used as RTC clock */ +#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ +#define RCC_CSR_RTCSEL_LSE_Pos (16U) +#define RCC_CSR_RTCSEL_LSE_Msk (0x1U << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */ +#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */ +#define RCC_CSR_RTCSEL_LSI_Pos (17U) +#define RCC_CSR_RTCSEL_LSI_Msk (0x1U << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */ +#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */ +#define RCC_CSR_RTCSEL_HSE_Pos (16U) +#define RCC_CSR_RTCSEL_HSE_Msk (0x3U << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */ +#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */ -#define RCC_CSR_RTCEN ((uint32_t)0x00040000U) /*!< RTC clock enable */ -#define RCC_CSR_RTCRST ((uint32_t)0x00080000U) /*!< RTC software reset */ +#define RCC_CSR_RTCEN_Pos (18U) +#define RCC_CSR_RTCEN_Msk (0x1U << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */ +#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */ +#define RCC_CSR_RTCRST_Pos (19U) +#define RCC_CSR_RTCRST_Msk (0x1U << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */ +#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */ -#define RCC_CSR_RMVF ((uint32_t)0x00800000U) /*!< Remove reset flag */ -#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000U) /*!< OBL reset flag */ -#define RCC_CSR_PINRSTF ((uint32_t)0x04000000U) /*!< PIN reset flag */ -#define RCC_CSR_PORRSTF ((uint32_t)0x08000000U) /*!< POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000U) /*!< Software Reset flag */ -#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000U) /*!< Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000U) /*!< Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000U) /*!< Low-Power reset flag */ +#define RCC_CSR_RMVF_Pos (23U) +#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_CSR_OBLRSTF_Pos (25U) +#define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ +#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */ +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF_Pos (27U) +#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ /* Reference defines */ #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */ @@ -2263,277 +3791,489 @@ typedef struct /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +/* +* @brief Specific device feature definitions +*/ +#define RTC_TAMPER2_SUPPORT +#define RTC_TAMPER3_SUPPORT +#define RTC_WAKEUP_SUPPORT +#define RTC_BACKUP_SUPPORT + /******************** Bits definition for RTC_TR register *******************/ -#define RTC_TR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_TR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_TR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_TR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_TR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_TR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_TR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_TR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_TR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_TR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_TR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_TR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_TR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_TR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_TR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_TR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_TR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_TR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_TR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_TR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_TR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk /*!< */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk /*!< */ +#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk /*!< */ +#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */ +#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */ +#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk /*!< */ +#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk /*!< */ +#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_DR register *******************/ -#define RTC_DR_YT ((uint32_t)0x00F00000U) /*!< */ -#define RTC_DR_YT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_DR_YT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_DR_YT_2 ((uint32_t)0x00400000U) /*!< */ -#define RTC_DR_YT_3 ((uint32_t)0x00800000U) /*!< */ -#define RTC_DR_YU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_DR_YU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_DR_YU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_DR_YU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_DR_YU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_DR_WDU ((uint32_t)0x0000E000U) /*!< */ -#define RTC_DR_WDU_0 ((uint32_t)0x00002000U) /*!< */ -#define RTC_DR_WDU_1 ((uint32_t)0x00004000U) /*!< */ -#define RTC_DR_WDU_2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_DR_MT ((uint32_t)0x00001000U) /*!< */ -#define RTC_DR_MU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_DR_MU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_DR_MU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_DR_MU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_DR_MU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_DR_DT ((uint32_t)0x00000030U) /*!< */ -#define RTC_DR_DT_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_DR_DT_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_DR_DU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_DR_DU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_DR_DU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_DR_DU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_DR_DU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk /*!< */ +#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk /*!< */ +#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */ +#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk /*!< */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk /*!< */ +#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk /*!< */ +#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk /*!< */ +#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_CR register *******************/ -#define RTC_CR_COE ((uint32_t)0x00800000U) /*!< */ -#define RTC_CR_OSEL ((uint32_t)0x00600000U) /*!< */ -#define RTC_CR_OSEL_0 ((uint32_t)0x00200000U) /*!< */ -#define RTC_CR_OSEL_1 ((uint32_t)0x00400000U) /*!< */ -#define RTC_CR_POL ((uint32_t)0x00100000U) /*!< */ -#define RTC_CR_COSEL ((uint32_t)0x00080000U) /*!< */ -#define RTC_CR_BCK ((uint32_t)0x00040000U) /*!< */ -#define RTC_CR_SUB1H ((uint32_t)0x00020000U) /*!< */ -#define RTC_CR_ADD1H ((uint32_t)0x00010000U) /*!< */ -#define RTC_CR_TSIE ((uint32_t)0x00008000U) /*!< */ -#define RTC_CR_WUTIE ((uint32_t)0x00004000U) /*!< */ -#define RTC_CR_ALRBIE ((uint32_t)0x00002000U) /*!< */ -#define RTC_CR_ALRAIE ((uint32_t)0x00001000U) /*!< */ -#define RTC_CR_TSE ((uint32_t)0x00000800U) /*!< */ -#define RTC_CR_WUTE ((uint32_t)0x00000400U) /*!< */ -#define RTC_CR_ALRBE ((uint32_t)0x00000200U) /*!< */ -#define RTC_CR_ALRAE ((uint32_t)0x00000100U) /*!< */ -#define RTC_CR_FMT ((uint32_t)0x00000040U) /*!< */ -#define RTC_CR_BYPSHAD ((uint32_t)0x00000020U) /*!< */ -#define RTC_CR_REFCKON ((uint32_t)0x00000010U) /*!< */ -#define RTC_CR_TSEDGE ((uint32_t)0x00000008U) /*!< */ -#define RTC_CR_WUCKSEL ((uint32_t)0x00000007U) /*!< */ -#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004U) /*!< */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk /*!< */ +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */ +#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< */ +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */ +#define RTC_CR_BCK_Pos (18U) +#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ +#define RTC_CR_BCK RTC_CR_BCK_Msk /*!< */ +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */ +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */ +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */ +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */ +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */ +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */ +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */ +#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_ISR register ******************/ -#define RTC_ISR_RECALPF ((uint32_t)0x00010000U) /*!< */ -#define RTC_ISR_TAMP3F ((uint32_t)0x00008000U) /*!< */ -#define RTC_ISR_TAMP2F ((uint32_t)0x00004000U) /*!< */ -#define RTC_ISR_TSOVF ((uint32_t)0x00001000U) /*!< */ -#define RTC_ISR_TSF ((uint32_t)0x00000800U) /*!< */ -#define RTC_ISR_WUTF ((uint32_t)0x00000400U) /*!< */ -#define RTC_ISR_ALRBF ((uint32_t)0x00000200U) /*!< */ -#define RTC_ISR_ALRAF ((uint32_t)0x00000100U) /*!< */ -#define RTC_ISR_INIT ((uint32_t)0x00000080U) /*!< */ -#define RTC_ISR_INITF ((uint32_t)0x00000040U) /*!< */ -#define RTC_ISR_RSF ((uint32_t)0x00000020U) /*!< */ -#define RTC_ISR_INITS ((uint32_t)0x00000010U) /*!< */ -#define RTC_ISR_SHPF ((uint32_t)0x00000008U) /*!< */ -#define RTC_ISR_WUTWF ((uint32_t)0x00000004U) /*!< */ -#define RTC_ISR_ALRBWF ((uint32_t)0x00000002U) /*!< */ -#define RTC_ISR_ALRAWF ((uint32_t)0x00000001U) /*!< */ +#define RTC_ISR_RECALPF_Pos (16U) +#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */ +#define RTC_ISR_TAMP3F_Pos (15U) +#define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */ +#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */ +#define RTC_ISR_TAMP2F_Pos (14U) +#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ +#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */ +#define RTC_ISR_TSOVF_Pos (12U) +#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ +#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */ +#define RTC_ISR_TSF_Pos (11U) +#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ +#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */ +#define RTC_ISR_WUTF_Pos (10U) +#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ +#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */ +#define RTC_ISR_ALRBF_Pos (9U) +#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ +#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */ +#define RTC_ISR_ALRAF_Pos (8U) +#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ +#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */ +#define RTC_ISR_INIT_Pos (7U) +#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */ +#define RTC_ISR_INITF_Pos (6U) +#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */ +#define RTC_ISR_RSF_Pos (5U) +#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */ +#define RTC_ISR_INITS_Pos (4U) +#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */ +#define RTC_ISR_SHPF_Pos (3U) +#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */ +#define RTC_ISR_WUTWF_Pos (2U) +#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */ +#define RTC_ISR_ALRBWF_Pos (1U) +#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */ +#define RTC_ISR_ALRAWF_Pos (0U) +#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */ /******************** Bits definition for RTC_PRER register *****************/ -#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000U) /*!< */ -#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFFU) /*!< */ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */ /******************** Bits definition for RTC_WUTR register *****************/ -#define RTC_WUTR_WUT ((uint32_t)0x0000FFFFU) +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000U) /*!< */ -#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000U) /*!< */ -#define RTC_ALRMAR_DT ((uint32_t)0x30000000U) /*!< */ -#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000U) /*!< */ -#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000U) /*!< */ -#define RTC_ALRMAR_DU ((uint32_t)0x0F000000U) /*!< */ -#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000U) /*!< */ -#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000U) /*!< */ -#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000U) /*!< */ -#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000U) /*!< */ -#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000U) /*!< */ -#define RTC_ALRMAR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_ALRMAR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_ALRMAR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_ALRMAR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080U) /*!< */ -#define RTC_ALRMAR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_ALRMAR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */ +#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */ +#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */ +#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */ +#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */ +#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */ +#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */ +#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */ +#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000U) /*!< */ -#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000U) /*!< */ -#define RTC_ALRMBR_DT ((uint32_t)0x30000000U) /*!< */ -#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000U) /*!< */ -#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000U) /*!< */ -#define RTC_ALRMBR_DU ((uint32_t)0x0F000000U) /*!< */ -#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000U) /*!< */ -#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000U) /*!< */ -#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000U) /*!< */ -#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000U) /*!< */ -#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000U) /*!< */ -#define RTC_ALRMBR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_ALRMBR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_ALRMBR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_ALRMBR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080U) /*!< */ -#define RTC_ALRMBR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_ALRMBR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */ +#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */ +#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */ +#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */ +#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */ +#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */ +#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */ +#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */ +#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_WPR register ******************/ -#define RTC_WPR_KEY ((uint32_t)0x000000FFU) /*!< */ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */ /******************** Bits definition for RTC_SSR register ******************/ -#define RTC_SSR_SS ((uint32_t)0x0000FFFFU) /*!< */ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */ /******************** Bits definition for RTC_SHIFTR register ***************/ -#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFFU) /*!< */ -#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000U) /*!< */ +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */ +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */ /******************** Bits definition for RTC_TSTR register *****************/ -#define RTC_TSTR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_TSTR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_TSTR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_TSTR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_TSTR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_TSTR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_TSTR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_TSTR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_TSTR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_TSTR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TSTR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TSTR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_TSTR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_TSTR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_TSTR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_TSTR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_TSTR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_TSTR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_TSTR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_TSTR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */ +#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */ +#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */ +#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */ +#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */ +#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */ +#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_TSDR register *****************/ -#define RTC_TSDR_WDU ((uint32_t)0x0000E000U) /*!< */ -#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_TSDR_MT ((uint32_t)0x00001000U) /*!< */ -#define RTC_TSDR_MU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_TSDR_MU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TSDR_MU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TSDR_MU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TSDR_MU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TSDR_DT ((uint32_t)0x00000030U) /*!< */ -#define RTC_TSDR_DT_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_TSDR_DT_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_TSDR_DU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_TSDR_DU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_TSDR_DU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_TSDR_DU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_TSDR_DU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */ +#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */ +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */ +#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */ +#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */ +#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_TSSSR register ****************/ -#define RTC_TSSSR_SS ((uint32_t)0x0000FFFFU) +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /******************** Bits definition for RTC_CALR register *****************/ -#define RTC_CALR_CALP ((uint32_t)0x00008000U) /*!< */ -#define RTC_CALR_CALW8 ((uint32_t)0x00004000U) /*!< */ -#define RTC_CALR_CALW16 ((uint32_t)0x00002000U) /*!< */ -#define RTC_CALR_CALM ((uint32_t)0x000001FFU) /*!< */ -#define RTC_CALR_CALM_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_CALR_CALM_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_CALR_CALM_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_CALR_CALM_3 ((uint32_t)0x00000008U) /*!< */ -#define RTC_CALR_CALM_4 ((uint32_t)0x00000010U) /*!< */ -#define RTC_CALR_CALM_5 ((uint32_t)0x00000020U) /*!< */ -#define RTC_CALR_CALM_6 ((uint32_t)0x00000040U) /*!< */ -#define RTC_CALR_CALM_7 ((uint32_t)0x00000080U) /*!< */ -#define RTC_CALR_CALM_8 ((uint32_t)0x00000100U) /*!< */ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */ +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */ +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */ +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */ +#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ /* Legacy defines */ #define RTC_CAL_CALP RTC_CALR_CALP @@ -2551,126 +4291,254 @@ typedef struct #define RTC_CAL_CALM_8 RTC_CALR_CALM_8 /******************** Bits definition for RTC_TAMPCR register ****************/ -#define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000U) /*!< */ -#define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000U) /*!< */ -#define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000U) /*!< */ -#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000U) /*!< */ -#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000U) /*!< */ -#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000U) /*!< */ -#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000U) /*!< */ -#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000U) /*!< */ -#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800U) /*!< */ -#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080U) /*!< */ -#define RTC_TAMPCR_TAMP3TRG ((uint32_t)0x00000040U) /*!< */ -#define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020U) /*!< */ -#define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010U) /*!< */ -#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008U) /*!< */ -#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004U) /*!< */ +#define RTC_TAMPCR_TAMP3MF_Pos (24U) +#define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ +#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */ +#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U) +#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */ +#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */ +#define RTC_TAMPCR_TAMP3IE_Pos (22U) +#define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */ +#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */ +#define RTC_TAMPCR_TAMP2MF_Pos (21U) +#define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */ +#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */ +#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U) +#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */ +#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */ +#define RTC_TAMPCR_TAMP2IE_Pos (19U) +#define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */ +#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */ +#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) +#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */ +#define RTC_TAMPCR_TAMPPRCH_Pos (13U) +#define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */ +#define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAMPCR_TAMPFLT_Pos (11U) +#define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */ +#define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAMPCR_TAMPFREQ_Pos (8U) +#define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */ +#define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAMPCR_TAMPTS_Pos (7U) +#define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */ +#define RTC_TAMPCR_TAMP3TRG_Pos (6U) +#define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ +#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */ +#define RTC_TAMPCR_TAMP3E_Pos (5U) +#define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ +#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */ +#define RTC_TAMPCR_TAMP2TRG_Pos (4U) +#define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ +#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */ +#define RTC_TAMPCR_TAMP2E_Pos (3U) +#define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ +#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */ +#define RTC_TAMPCR_TAMPIE_Pos (2U) +#define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */ /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000U) -#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000U) -#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000U) -#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000U) -#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000U) -#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFFU) +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000U) -#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000U) -#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000U) -#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000U) -#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000U) -#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFFU) +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT_RMP ((uint32_t)0x00000002U) /*!< */ -#define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001U) /*!< */ +#define RTC_OR_OUT_RMP_Pos (1U) +#define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */ +#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */ +#define RTC_OR_ALARMOUTTYPE_Pos (0U) +#define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */ +#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */ /* Legacy defines */ #define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP /******************** Bits definition for RTC_BKP0R register ****************/ -#define RTC_BKP0R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP0R_Pos (0U) +#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP0R RTC_BKP0R_Msk /*!< */ /******************** Bits definition for RTC_BKP1R register ****************/ -#define RTC_BKP1R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP1R_Pos (0U) +#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP1R RTC_BKP1R_Msk /*!< */ /******************** Bits definition for RTC_BKP2R register ****************/ -#define RTC_BKP2R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP2R_Pos (0U) +#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP2R RTC_BKP2R_Msk /*!< */ /******************** Bits definition for RTC_BKP3R register ****************/ -#define RTC_BKP3R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP3R_Pos (0U) +#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP3R RTC_BKP3R_Msk /*!< */ /******************** Bits definition for RTC_BKP4R register ****************/ -#define RTC_BKP4R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP4R_Pos (0U) +#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP4R RTC_BKP4R_Msk /*!< */ /******************** Number of backup registers ******************************/ -#define RTC_BKP_NUMBER ((uint32_t)0x00000005U) /*!< */ +#define RTC_BKP_NUMBER (0x00000005U) /*!< */ /******************************************************************************/ /* */ /* Serial Peripheral Interface (SPI) */ /* */ /******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32L0 family) + */ +/* Note: No specific macro feature on this device */ + /******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA ((uint32_t)0x00000001U) /*!< Clock Phase */ -#define SPI_CR1_CPOL ((uint32_t)0x00000002U) /*!< Clock Polarity */ -#define SPI_CR1_MSTR ((uint32_t)0x00000004U) /*!< Master Selection */ -#define SPI_CR1_BR ((uint32_t)0x00000038U) /*!< BR[2:0] bits (Baud Rate Control) */ -#define SPI_CR1_BR_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define SPI_CR1_BR_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ -#define SPI_CR1_BR_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ -#define SPI_CR1_SPE ((uint32_t)0x00000040U) /*!< SPI Enable */ -#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080U) /*!< Frame Format */ -#define SPI_CR1_SSI ((uint32_t)0x00000100U) /*!< Internal slave select */ -#define SPI_CR1_SSM ((uint32_t)0x00000200U) /*!< Software slave management */ -#define SPI_CR1_RXONLY ((uint32_t)0x00000400U) /*!< Receive only */ -#define SPI_CR1_DFF ((uint32_t)0x00000800U) /*!< Data Frame Format */ -#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000U) /*!< Transmit CRC next */ -#define SPI_CR1_CRCEN ((uint32_t)0x00002000U) /*!< Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE ((uint32_t)0x00004000U) /*!< Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000U) /*!< Bidirectional data mode enable */ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ +#define SPI_CR1_CPOL_Pos (1U) +#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ +#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ +#define SPI_CR1_MSTR_Pos (2U) +#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ +#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ +#define SPI_CR1_BR_Pos (3U) +#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */ +#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ +#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ +#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ +#define SPI_CR1_SPE_Pos (6U) +#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ +#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ +#define SPI_CR1_LSBFIRST_Pos (7U) +#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ +#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ +#define SPI_CR1_SSI_Pos (8U) +#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ +#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ +#define SPI_CR1_SSM_Pos (9U) +#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ +#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ +#define SPI_CR1_RXONLY_Pos (10U) +#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ +#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ +#define SPI_CR1_DFF_Pos (11U) +#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ +#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ +#define SPI_CR1_CRCNEXT_Pos (12U) +#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ +#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ +#define SPI_CR1_CRCEN_Pos (13U) +#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ +#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE_Pos (14U) +#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ +#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE_Pos (15U) +#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ +#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ /******************* Bit definition for SPI_CR2 register ********************/ -#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001U) /*!< Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002U) /*!< Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE ((uint32_t)0x00000004U) /*!< SS Output Enable */ -#define SPI_CR2_FRF ((uint32_t)0x00000010U) /*!< Frame Format Enable */ -#define SPI_CR2_ERRIE ((uint32_t)0x00000020U) /*!< Error Interrupt Enable */ -#define SPI_CR2_RXNEIE ((uint32_t)0x00000040U) /*!< RX buffer Not Empty Interrupt Enable */ -#define SPI_CR2_TXEIE ((uint32_t)0x00000080U) /*!< Tx buffer Empty Interrupt Enable */ +#define SPI_CR2_RXDMAEN_Pos (0U) +#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ +#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN_Pos (1U) +#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ +#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE_Pos (2U) +#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ +#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ +#define SPI_CR2_FRF_Pos (4U) +#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ +#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ +#define SPI_CR2_ERRIE_Pos (5U) +#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ +#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ +#define SPI_CR2_RXNEIE_Pos (6U) +#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ +#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE_Pos (7U) +#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ +#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ /******************** Bit definition for SPI_SR register ********************/ -#define SPI_SR_RXNE ((uint32_t)0x00000001U) /*!< Receive buffer Not Empty */ -#define SPI_SR_TXE ((uint32_t)0x00000002U) /*!< Transmit buffer Empty */ -#define SPI_SR_CHSIDE ((uint32_t)0x00000004U) /*!< Channel side */ -#define SPI_SR_UDR ((uint32_t)0x00000008U) /*!< Underrun flag */ -#define SPI_SR_CRCERR ((uint32_t)0x00000010U) /*!< CRC Error flag */ -#define SPI_SR_MODF ((uint32_t)0x00000020U) /*!< Mode fault */ -#define SPI_SR_OVR ((uint32_t)0x00000040U) /*!< Overrun flag */ -#define SPI_SR_BSY ((uint32_t)0x00000080U) /*!< Busy flag */ -#define SPI_SR_FRE ((uint32_t)0x00000100U) /*!< TI frame format error */ +#define SPI_SR_RXNE_Pos (0U) +#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ +#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ +#define SPI_SR_TXE_Pos (1U) +#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ +#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ +#define SPI_SR_CHSIDE_Pos (2U) +#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ +#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ +#define SPI_SR_UDR_Pos (3U) +#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */ +#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ +#define SPI_SR_CRCERR_Pos (4U) +#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ +#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ +#define SPI_SR_MODF_Pos (5U) +#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */ +#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ +#define SPI_SR_OVR_Pos (6U) +#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */ +#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ +#define SPI_SR_BSY_Pos (7U) +#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */ +#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ +#define SPI_SR_FRE_Pos (8U) +#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */ +#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ /******************** Bit definition for SPI_DR register ********************/ -#define SPI_DR_DR ((uint32_t)0x0000FFFFU) /*!< Data Register */ +#define SPI_DR_DR_Pos (0U) +#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ +#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ /******************* Bit definition for SPI_CRCPR register ******************/ -#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFFU) /*!< CRC polynomial register */ +#define SPI_CRCPR_CRCPOLY_Pos (0U) +#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ +#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ /****************** Bit definition for SPI_RXCRCR register ******************/ -#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFFU) /*!< Rx CRC Register */ +#define SPI_RXCRCR_RXCRC_Pos (0U) +#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ /****************** Bit definition for SPI_TXCRCR register ******************/ -#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFFU) /*!< Tx CRC Register */ +#define SPI_TXCRCR_TXCRC_Pos (0U) +#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ /******************************************************************************/ /* */ @@ -2678,181 +4546,239 @@ typedef struct /* */ /******************************************************************************/ /***************** Bit definition for SYSCFG_CFGR1 register ****************/ -#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003U) /*!< SYSCFG_Memory Remap Config */ -#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001U) /*!< SYSCFG_Memory Remap Config Bit 0 */ -#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002U) /*!< SYSCFG_Memory Remap Config Bit 1 */ -#define SYSCFG_CFGR1_BOOT_MODE ((uint32_t)0x00000300U) /*!< SYSCFG_Boot mode Config */ -#define SYSCFG_CFGR1_BOOT_MODE_0 ((uint32_t)0x00000100U) /*!< SYSCFG_Boot mode Config Bit 0 */ -#define SYSCFG_CFGR1_BOOT_MODE_1 ((uint32_t)0x00000200U) /*!< SYSCFG_Boot mode Config Bit 1 */ +#define SYSCFG_CFGR1_MEM_MODE_Pos (0U) +#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */ +#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ +#define SYSCFG_CFGR1_MEM_MODE_0 (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */ +#define SYSCFG_CFGR1_MEM_MODE_1 (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */ +#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U) +#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */ +#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */ +#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */ +#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */ /***************** Bit definition for SYSCFG_CFGR2 register ****************/ -#define SYSCFG_CFGR2_FWDISEN ((uint32_t)0x00000001U) /*!< Firewall disable bit */ -#define SYSCFG_CFGR2_I2C_PB6_FMP ((uint32_t)0x00000100U) /*!< I2C PB6 Fast mode plus */ -#define SYSCFG_CFGR2_I2C_PB7_FMP ((uint32_t)0x00000200U) /*!< I2C PB7 Fast mode plus */ -#define SYSCFG_CFGR2_I2C_PB8_FMP ((uint32_t)0x00000400U) /*!< I2C PB8 Fast mode plus */ -#define SYSCFG_CFGR2_I2C_PB9_FMP ((uint32_t)0x00000800U) /*!< I2C PB9 Fast mode plus */ -#define SYSCFG_CFGR2_I2C1_FMP ((uint32_t)0x00001000U) /*!< I2C1 Fast mode plus */ +#define SYSCFG_CFGR2_FWDISEN_Pos (0U) +#define SYSCFG_CFGR2_FWDISEN_Msk (0x1U << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */ +#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */ +#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U) +#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */ +#define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */ +#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U) +#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */ +#define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */ +#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U) +#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */ +#define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */ +#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U) +#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */ +#define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */ +#define SYSCFG_CFGR2_I2C1_FMP_Pos (12U) +#define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */ +#define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */ /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ -#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000FU) /*!< EXTI 0 configuration */ -#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0U) /*!< EXTI 1 configuration */ -#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00U) /*!< EXTI 2 configuration */ -#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000U) /*!< EXTI 3 configuration */ +#define SYSCFG_EXTICR1_EXTI0_Pos (0U) +#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ +#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define SYSCFG_EXTICR1_EXTI1_Pos (4U) +#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ +#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define SYSCFG_EXTICR1_EXTI2_Pos (8U) +#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ +#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define SYSCFG_EXTICR1_EXTI3_Pos (12U) +#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ +#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000U) /*!< PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001U) /*!< PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002U) /*!< PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005U) /*!< PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000U) /*!< PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010U) /*!< PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020U) /*!< PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050U) /*!< PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000U) /*!< PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100U) /*!< PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200U) /*!< PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300U) /*!< PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000U) /*!< PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000U) /*!< PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000U) /*!< PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register *****************/ -#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000FU) /*!< EXTI 4 configuration */ -#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0U) /*!< EXTI 5 configuration */ -#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00U) /*!< EXTI 6 configuration */ -#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000U) /*!< EXTI 7 configuration */ +#define SYSCFG_EXTICR2_EXTI4_Pos (0U) +#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ +#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define SYSCFG_EXTICR2_EXTI5_Pos (4U) +#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ +#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define SYSCFG_EXTICR2_EXTI6_Pos (8U) +#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ +#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define SYSCFG_EXTICR2_EXTI7_Pos (12U) +#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ +#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000U) /*!< PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001U) /*!< PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002U) /*!< PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000U) /*!< PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010U) /*!< PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020U) /*!< PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000U) /*!< PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100U) /*!< PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200U) /*!< PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000U) /*!< PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000U) /*!< PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000U) /*!< PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register *****************/ -#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000FU) /*!< EXTI 8 configuration */ -#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0U) /*!< EXTI 9 configuration */ -#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00U) /*!< EXTI 10 configuration */ -#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000U) /*!< EXTI 11 configuration */ +#define SYSCFG_EXTICR3_EXTI8_Pos (0U) +#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ +#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define SYSCFG_EXTICR3_EXTI9_Pos (4U) +#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ +#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define SYSCFG_EXTICR3_EXTI10_Pos (8U) +#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ +#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define SYSCFG_EXTICR3_EXTI11_Pos (12U) +#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ +#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000U) /*!< PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001U) /*!< PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002U) /*!< PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000U) /*!< PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010U) /*!< PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020U) /*!< PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000U) /*!< PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100U) /*!< PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200U) /*!< PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000U) /*!< PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000U) /*!< PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000U) /*!< PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register *****************/ -#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000FU) /*!< EXTI 12 configuration */ -#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0U) /*!< EXTI 13 configuration */ -#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00U) /*!< EXTI 14 configuration */ -#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000U) /*!< EXTI 15 configuration */ +#define SYSCFG_EXTICR4_EXTI12_Pos (0U) +#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ +#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define SYSCFG_EXTICR4_EXTI13_Pos (4U) +#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ +#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define SYSCFG_EXTICR4_EXTI14_Pos (8U) +#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ +#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define SYSCFG_EXTICR4_EXTI15_Pos (12U) +#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ +#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000U) /*!< PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001U) /*!< PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002U) /*!< PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000U) /*!< PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010U) /*!< PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020U) /*!< PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000U) /*!< PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100U) /*!< PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200U) /*!< PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000U) /*!< PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000U) /*!< PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000U) /*!< PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ /***************** Bit definition for SYSCFG_CFGR3 register ****************/ -#define SYSCFG_CFGR3_EN_VREFINT ((uint32_t)0x00000001U) /*!< Vref Enable bit*/ -#define SYSCFG_CFGR3_VREF_OUT ((uint32_t)0x00000030U) /*!< Verf_ADC connection bit */ -#define SYSCFG_CFGR3_VREF_OUT_0 ((uint32_t)0x00000010U) /*!< Bit 0 */ -#define SYSCFG_CFGR3_VREF_OUT_1 ((uint32_t)0x00000020U) /*!< Bit 1 */ -#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC ((uint32_t)0x00000100U) /*!< VREFINT reference for ADC enable bit */ -#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC ((uint32_t)0x00000200U) /*!< Sensor reference for ADC enable bit */ -#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP ((uint32_t)0x00001000U) /*!< VREFINT reference for comparator 2 enable bit */ -#define SYSCFG_CFGR3_SENSOR_ADC_RDYF ((uint32_t)0x08000000U) /*!< Sensor for ADC ready flag */ -#define SYSCFG_CFGR3_VREFINT_ADC_RDYF ((uint32_t)0x10000000U) /*!< VREFINT for ADC ready flag */ -#define SYSCFG_CFGR3_VREFINT_COMP_RDYF ((uint32_t)0x20000000U) /*!< VREFINT for comparator ready flag */ -#define SYSCFG_CFGR3_VREFINT_RDYF ((uint32_t)0x40000000U) /*!< VREFINT ready flag */ -#define SYSCFG_CFGR3_REF_LOCK ((uint32_t)0x80000000U) /*!< CFGR3 lock bit */ +#define SYSCFG_CFGR3_VREF_OUT_Pos (4U) +#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */ +#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */ +#define SYSCFG_CFGR3_VREF_OUT_0 (0x1U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */ +#define SYSCFG_CFGR3_VREF_OUT_1 (0x2U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */ +#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U) +#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1U << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */ +#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */ +#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U) +#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1U << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */ +#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */ +#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U) +#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1U << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */ +#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */ +#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U) +#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1U << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */ +#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */ +#define SYSCFG_CFGR3_REF_LOCK_Pos (31U) +#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1U << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */ +#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */ /* Legacy defines */ -#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT #define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC #define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP -#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_ADC_RDYF +#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF +#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF +#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF +#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF /******************************************************************************/ /* */ @@ -2871,266 +4797,470 @@ typedef struct #endif /******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN ((uint32_t)0x00000001U) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -83,15 +83,15 @@ #include "hal_tick.h" #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/ + #define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* MSI_VALUE */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ @@ -115,8 +115,8 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. + This value must be a multiple of 0x100. */ /******************************************************************************/ /** * @} @@ -146,8 +146,9 @@ variable is updated automatically. */ uint32_t SystemCoreClock = 32000000; -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U}; /** * @} @@ -179,25 +180,25 @@ uint8_t SetSysClock_PLL_HSI(void); void SystemInit (void) { /*!< Set MSION bit */ - RCC->CR |= (uint32_t)0x00000100; + RCC->CR |= (uint32_t)0x00000100U; /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ - RCC->CFGR &= (uint32_t) 0x88FF400C; + RCC->CFGR &= (uint32_t) 0x88FF400CU; /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFF6; + RCC->CR &= (uint32_t)0xFEF6FFF6U; /*!< Reset HSI48ON bit */ - RCC->CRRCR &= (uint32_t)0xFFFFFFFE; + RCC->CRRCR &= (uint32_t)0xFFFFFFFEU; /*!< Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; + RCC->CR &= (uint32_t)0xFFFBFFFFU; /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ - RCC->CFGR &= (uint32_t)0xFF02FFFF; + RCC->CFGR &= (uint32_t)0xFF02FFFFU; /*!< Disable all interrupts */ - RCC->CIER = 0x00000000; + RCC->CIER = 0x00000000U; /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM @@ -259,33 +260,33 @@ void SystemInit (void) */ void SystemCoreClockUpdate (void) { - uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; + uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; switch (tmp) { - case 0x00: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); + case 0x00U: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; + SystemCoreClock = (32768U * (1U << (msirange + 1U))); break; - case 0x04: /* HSI used as system clock */ + case 0x04U: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; break; - case 0x08: /* HSE used as system clock */ + case 0x08U: /* HSE used as system clock */ SystemCoreClock = HSE_VALUE; break; - case 0x0C: /* PLL used as system clock */ + case 0x0CU: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; - pllmul = PLLMulTable[(pllmul >> 18)]; - plldiv = (plldiv >> 22) + 1; + pllmul = PLLMulTable[(pllmul >> 18U)]; + plldiv = (plldiv >> 22U) + 1U; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - if (pllsource == 0x00) + if (pllsource == 0x00U) { /* HSI oscillator clock selected as PLL clock entry */ SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); @@ -297,13 +298,13 @@ void SystemCoreClockUpdate (void) } break; default: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; + SystemCoreClock = (32768U * (1U << (msirange + 1U))); break; } /* Compute HCLK clock frequency --------------------------------------------*/ /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/system_stm32l0xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/system_stm32l0xx.h index 4a82de7134..7015debf51 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/system_stm32l0xx.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/system_stm32l0xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32l0xx.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -74,6 +74,11 @@ variable is updated automatically. */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/* +*/ +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/stm32l031xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/stm32l031xx.h index 355646c4ee..63445fb605 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/stm32l031xx.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/stm32l031xx.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l031xx.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for stm32l031xx devices. @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -499,55 +499,59 @@ typedef struct #define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */ #define DATA_EEPROM_END ((uint32_t)0x080803FFU) /*!< DATA EEPROM end address in the alias region */ #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */ +#define SRAM_SIZE_MAX ((uint32_t)0x00002000U) /*!< maximum SRAM size (up to 8KBytes) */ + #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */ /*!< Peripheral memory map */ #define APBPERIPH_BASE PERIPH_BASE -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) -#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) +#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000U) -#define TIM2_BASE (APBPERIPH_BASE + 0x00000000) -#define RTC_BASE (APBPERIPH_BASE + 0x00002800) -#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00) -#define IWDG_BASE (APBPERIPH_BASE + 0x00003000) -#define USART2_BASE (APBPERIPH_BASE + 0x00004400) -#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800) -#define I2C1_BASE (APBPERIPH_BASE + 0x00005400) -#define PWR_BASE (APBPERIPH_BASE + 0x00007000) -#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00) +#define TIM2_BASE (APBPERIPH_BASE + 0x00000000U) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800U) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00U) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000U) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400U) +#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800U) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400U) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000U) +#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00U) -#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000) -#define COMP1_BASE (APBPERIPH_BASE + 0x00010018) -#define COMP2_BASE (APBPERIPH_BASE + 0x0001001C) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000U) +#define COMP1_BASE (APBPERIPH_BASE + 0x00010018U) +#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CU) #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE) -#define EXTI_BASE (APBPERIPH_BASE + 0x00010400) -#define TIM21_BASE (APBPERIPH_BASE + 0x00010800) -#define TIM22_BASE (APBPERIPH_BASE + 0x00011400) -#define ADC1_BASE (APBPERIPH_BASE + 0x00012400) -#define ADC_BASE (APBPERIPH_BASE + 0x00012708) -#define SPI1_BASE (APBPERIPH_BASE + 0x00013000) -#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800) +#define EXTI_BASE (APBPERIPH_BASE + 0x00010400U) +#define TIM21_BASE (APBPERIPH_BASE + 0x00010800U) +#define TIM22_BASE (APBPERIPH_BASE + 0x00011400U) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400U) +#define ADC_BASE (APBPERIPH_BASE + 0x00012708U) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000U) +#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800U) -#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080) -#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8) +#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8U) -#define RCC_BASE (AHBPERIPH_BASE + 0x00001000) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */ +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */ #define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */ -#define CRC_BASE (AHBPERIPH_BASE + 0x00003000) +#define FLASHSIZE_BASE ((uint32_t)0x1FF8007CU) /*!< FLASH Size register base address */ +#define UID_BASE ((uint32_t)0x1FF80050U) /*!< Unique device ID register base address */ +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) -#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000) -#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400) -#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800) -#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00) +#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000U) +#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400U) +#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800U) +#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00U) /** * @} @@ -622,91 +626,173 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for ADC_ISR register ******************/ -#define ADC_ISR_EOCAL ((uint32_t)0x00000800U) /*!< End of calibration flag */ -#define ADC_ISR_AWD ((uint32_t)0x00000080U) /*!< Analog watchdog flag */ -#define ADC_ISR_OVR ((uint32_t)0x00000010U) /*!< Overrun flag */ -#define ADC_ISR_EOSEQ ((uint32_t)0x00000008U) /*!< End of Sequence flag */ -#define ADC_ISR_EOC ((uint32_t)0x00000004U) /*!< End of Conversion */ -#define ADC_ISR_EOSMP ((uint32_t)0x00000002U) /*!< End of sampling flag */ -#define ADC_ISR_ADRDY ((uint32_t)0x00000001U) /*!< ADC Ready */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1U << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */ +#define ADC_ISR_AWD_Pos (7U) +#define ADC_ISR_AWD_Msk (0x1U << ADC_ISR_AWD_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */ +#define ADC_ISR_EOSEQ_Pos (3U) +#define ADC_ISR_EOSEQ_Msk (0x1U << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */ /* Old EOSEQ bit definition, maintained for legacy purpose */ #define ADC_ISR_EOS ADC_ISR_EOSEQ /******************** Bits definition for ADC_IER register ******************/ -#define ADC_IER_EOCALIE ((uint32_t)0x00000800U) /*!< Enf Of Calibration interrupt enable */ -#define ADC_IER_AWDIE ((uint32_t)0x00000080U) /*!< Analog Watchdog interrupt enable */ -#define ADC_IER_OVRIE ((uint32_t)0x00000010U) /*!< Overrun interrupt enable */ -#define ADC_IER_EOSEQIE ((uint32_t)0x00000008U) /*!< End of Sequence of conversion interrupt enable */ -#define ADC_IER_EOCIE ((uint32_t)0x00000004U) /*!< End of Conversion interrupt enable */ -#define ADC_IER_EOSMPIE ((uint32_t)0x00000002U) /*!< End of sampling interrupt enable */ -#define ADC_IER_ADRDYIE ((uint32_t)0x00000001U) /*!< ADC Ready interrupt enable */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1U << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */ +#define ADC_IER_AWDIE_Pos (7U) +#define ADC_IER_AWDIE_Msk (0x1U << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */ +#define ADC_IER_EOSEQIE_Pos (3U) +#define ADC_IER_EOSEQIE_Msk (0x1U << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */ /* Old EOSEQIE bit definition, maintained for legacy purpose */ #define ADC_IER_EOSIE ADC_IER_EOSEQIE /******************** Bits definition for ADC_CR register *******************/ -#define ADC_CR_ADCAL ((uint32_t)0x80000000U) /*!< ADC calibration */ -#define ADC_CR_ADVREGEN ((uint32_t)0x10000000U) /*!< ADC Voltage Regulator Enable */ -#define ADC_CR_ADSTP ((uint32_t)0x00000010U) /*!< ADC stop of conversion command */ -#define ADC_CR_ADSTART ((uint32_t)0x00000004U) /*!< ADC start of conversion */ -#define ADC_CR_ADDIS ((uint32_t)0x00000002U) /*!< ADC disable command */ -#define ADC_CR_ADEN ((uint32_t)0x00000001U) /*!< ADC enable control */ /*#### TBV */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */ /******************* Bits definition for ADC_CFGR1 register *****************/ -#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000U) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000U) /*!< Bit 0 */ -#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000U) /*!< Bit 1 */ -#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000U) /*!< Bit 2 */ -#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000U) /*!< Bit 3 */ -#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000U) /*!< Bit 4 */ -#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000U) /*!< Analog watchdog enable on regular channels */ -#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000U) /*!< Enable the watchdog on a single channel or on all channels */ -#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000U) /*!< Discontinuous mode on regular channels */ -#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000U) /*!< ADC auto power off */ -#define ADC_CFGR1_WAIT ((uint32_t)0x00004000U) /*!< ADC wait conversion mode */ -#define ADC_CFGR1_CONT ((uint32_t)0x00002000U) /*!< Continuous Conversion */ -#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000U) /*!< Overrun mode */ -#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00U) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ -#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ -#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ -#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0U) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ -#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ -#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100U) /*!< Bit 2 */ -#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020U) /*!< Data Alignment */ -#define ADC_CFGR1_RES ((uint32_t)0x00000018U) /*!< RES[1:0] bits (Resolution) */ -#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ -#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004U) /*!< Sequence scan direction */ -#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002U) /*!< Direct memory access configuration */ -#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001U) /*!< Direct memory access enable */ +#define ADC_CFGR1_AWDCH_Pos (26U) +#define ADC_CFGR1_AWDCH_Msk (0x1FU << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CFGR1_AWDCH_0 (0x01U << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWDCH_1 (0x02U << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWDCH_2 (0x04U << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWDCH_3 (0x08U << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWDCH_4 (0x10U << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ +#define ADC_CFGR1_AWDEN_Pos (23U) +#define ADC_CFGR1_AWDEN_Msk (0x1U << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */ +#define ADC_CFGR1_AWDSGL_Pos (22U) +#define ADC_CFGR1_AWDSGL_Msk (0x1U << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */ +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */ +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ +#define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */ +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */ /* Old WAIT bit definition, maintained for legacy purpose */ #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT /******************* Bits definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_TOVS ((uint32_t)0x80000200U) /*!< Triggered Oversampling */ -#define ADC_CFGR2_OVSS ((uint32_t)0x000001E0U) /*!< OVSS [3:0] bits (Oversampling shift) */ -#define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ -#define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ -#define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ -#define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ -#define ADC_CFGR2_OVSR ((uint32_t)0x0000001CU) /*!< OVSR [2:0] bits (Oversampling ratio) */ -#define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004U) /*!< Bit 0 */ -#define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008U) /*!< Bit 1 */ -#define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010U) /*!< Bit 2 */ -#define ADC_CFGR2_OVSE ((uint32_t)0x00000001U) /*!< Oversampler Enable */ -#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000U) /*!< CKMODE [1:0] bits (ADC clock mode) */ -#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000U) /*!< Bit 0 */ -#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000U) /*!< Bit 1 */ +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x400001U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */ +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */ +#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */ +#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1U << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */ +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */ +#define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ /****************** Bit definition for ADC_SMPR register ********************/ -#define ADC_SMPR_SMP ((uint32_t)0x00000007U) /*!< SMPR[2:0] bits (Sampling time selection) */ -#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ -#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ -#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SMPR_SMP_Pos (0U) +#define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */ +#define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ /* Legacy defines */ #define ADC_SMPR_SMPR ADC_SMPR_SMP @@ -715,45 +801,99 @@ typedef struct #define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2 /******************* Bit definition for ADC_TR register ********************/ -#define ADC_TR_HT ((uint32_t)0x0FFF0000U) /*!< Analog watchdog high threshold */ -#define ADC_TR_LT ((uint32_t)0x00000FFFU) /*!< Analog watchdog low threshold */ +#define ADC_TR_HT_Pos (16U) +#define ADC_TR_HT_Msk (0xFFFU << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */ +#define ADC_TR_LT_Pos (0U) +#define ADC_TR_LT_Msk (0xFFFU << ADC_TR_LT_Pos) /*!< 0x00000FFF */ +#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */ /****************** Bit definition for ADC_CHSELR register ******************/ -#define ADC_CHSELR_CHSEL ((uint32_t)0x0007FFFFU) /*!< ADC group regular sequencer channels */ -#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000U) /*!< Channel 18 selection */ -#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000U) /*!< Channel 17 selection */ -#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000U) /*!< Channel 15 selection */ -#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000U) /*!< Channel 14 selection */ -#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000U) /*!< Channel 13 selection */ -#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000U) /*!< Channel 12 selection */ -#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800U) /*!< Channel 11 selection */ -#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400U) /*!< Channel 10 selection */ -#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200U) /*!< Channel 9 selection */ -#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100U) /*!< Channel 8 selection */ -#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080U) /*!< Channel 7 selection */ -#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040U) /*!< Channel 6 selection */ -#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020U) /*!< Channel 5 selection */ -#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010U) /*!< Channel 4 selection */ -#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008U) /*!< Channel 3 selection */ -#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004U) /*!< Channel 2 selection */ -#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002U) /*!< Channel 1 selection */ -#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001U) /*!< Channel 0 selection */ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFFU) /*!< Regular data */ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */ /******************** Bit definition for ADC_CALFACT register ********************/ -#define ADC_CALFACT_CALFACT ((uint32_t)0x0000007FU) /*!< Calibration factor */ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FU << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */ /******************* Bit definition for ADC_CCR register ********************/ -#define ADC_CCR_LFMEN ((uint32_t)0x02000000U) /*!< Low Frequency Mode enable */ -#define ADC_CCR_TSEN ((uint32_t)0x00800000U) /*!< Temperature sensore enable */ -#define ADC_CCR_VREFEN ((uint32_t)0x00400000U) /*!< Vrefint enable */ -#define ADC_CCR_PRESC ((uint32_t)0x003C0000U) /*!< PRESC [3:0] bits (ADC prescaler) */ -#define ADC_CCR_PRESC_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ -#define ADC_CCR_PRESC_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ -#define ADC_CCR_PRESC_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ -#define ADC_CCR_PRESC_3 ((uint32_t)0x00200000U) /*!< Bit 3 */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1U << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */ +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */ +#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ /******************************************************************************/ /* */ @@ -762,37 +902,77 @@ typedef struct /******************************************************************************/ /************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/ /* COMP1 bits definition */ -#define COMP_CSR_COMP1EN ((uint32_t)0x00000001U) /*!< COMP1 enable */ -#define COMP_CSR_COMP1INNSEL ((uint32_t)0x00000030U) /*!< COMP1 inverting input select */ -#define COMP_CSR_COMP1INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP1 inverting input select bit 0 */ -#define COMP_CSR_COMP1INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP1 inverting input select bit 1 */ -#define COMP_CSR_COMP1WM ((uint32_t)0x00000100U) /*!< Comparators window mode enable */ -#define COMP_CSR_COMP1LPTIM1IN1 ((uint32_t)0x00001000U) /*!< COMP1 LPTIM1 IN1 connection */ -#define COMP_CSR_COMP1POLARITY ((uint32_t)0x00008000U) /*!< COMP1 output polarity */ -#define COMP_CSR_COMP1VALUE ((uint32_t)0x40000000U) /*!< COMP1 output level */ -#define COMP_CSR_COMP1LOCK ((uint32_t)0x80000000U) /*!< COMP1 lock */ +#define COMP_CSR_COMP1EN_Pos (0U) +#define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */ +#define COMP_CSR_COMP1INNSEL_Pos (4U) +#define COMP_CSR_COMP1INNSEL_Msk (0x3U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */ +#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */ +#define COMP_CSR_COMP1INNSEL_0 (0x1U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_COMP1INNSEL_1 (0x2U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_COMP1WM_Pos (8U) +#define COMP_CSR_COMP1WM_Msk (0x1U << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */ +#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */ +#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U) +#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */ +#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */ +#define COMP_CSR_COMP1POLARITY_Pos (15U) +#define COMP_CSR_COMP1POLARITY_Msk (0x1U << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */ +#define COMP_CSR_COMP1VALUE_Pos (30U) +#define COMP_CSR_COMP1VALUE_Msk (0x1U << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */ +#define COMP_CSR_COMP1LOCK_Pos (31U) +#define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */ /* COMP2 bits definition */ -#define COMP_CSR_COMP2EN ((uint32_t)0x00000001U) /*!< COMP2 enable */ -#define COMP_CSR_COMP2SPEED ((uint32_t)0x00000008U) /*!< COMP2 power mode */ -#define COMP_CSR_COMP2INNSEL ((uint32_t)0x00000070U) /*!< COMP2 inverting input select */ -#define COMP_CSR_COMP2INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP2 inverting input select bit 0 */ -#define COMP_CSR_COMP2INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP2 inverting input select bit 1 */ -#define COMP_CSR_COMP2INNSEL_2 ((uint32_t)0x00000040U) /*!< COMP2 inverting input select bit 2 */ -#define COMP_CSR_COMP2INPSEL ((uint32_t)0x00000700U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2INPSEL_0 ((uint32_t)0x00000100U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2INPSEL_1 ((uint32_t)0x00000200U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2INPSEL_2 ((uint32_t)0x00000400U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2LPTIM1IN2 ((uint32_t)0x00001000U) /*!< COMP2 LPTIM1 IN2 connection */ -#define COMP_CSR_COMP2LPTIM1IN1 ((uint32_t)0x00002000U) /*!< COMP2 LPTIM1 IN1 connection */ -#define COMP_CSR_COMP2POLARITY ((uint32_t)0x00008000U) /*!< COMP2 output polarity */ -#define COMP_CSR_COMP2VALUE ((uint32_t)0x40000000U) /*!< COMP2 output level */ -#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000U) /*!< COMP2 lock */ +#define COMP_CSR_COMP2EN_Pos (0U) +#define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */ +#define COMP_CSR_COMP2SPEED_Pos (3U) +#define COMP_CSR_COMP2SPEED_Msk (0x1U << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */ +#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */ +#define COMP_CSR_COMP2INNSEL_Pos (4U) +#define COMP_CSR_COMP2INNSEL_Msk (0x7U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */ +#define COMP_CSR_COMP2INNSEL_0 (0x1U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_COMP2INNSEL_1 (0x2U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_COMP2INNSEL_2 (0x4U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_COMP2INPSEL_Pos (8U) +#define COMP_CSR_COMP2INPSEL_Msk (0x7U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */ +#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */ +#define COMP_CSR_COMP2INPSEL_0 (0x1U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_COMP2INPSEL_1 (0x2U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */ +#define COMP_CSR_COMP2INPSEL_2 (0x4U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */ +#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U) +#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */ +#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */ +#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U) +#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */ +#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */ +#define COMP_CSR_COMP2POLARITY_Pos (15U) +#define COMP_CSR_COMP2POLARITY_Msk (0x1U << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */ +#define COMP_CSR_COMP2VALUE_Pos (30U) +#define COMP_CSR_COMP2VALUE_Msk (0x1U << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */ +#define COMP_CSR_COMP2LOCK_Pos (31U) +#define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */ /********************** Bit definition for COMP_CSR register common ****************/ -#define COMP_CSR_COMPxEN ((uint32_t)0x00000001U) /*!< COMPx enable */ -#define COMP_CSR_COMPxPOLARITY ((uint32_t)0x00008000U) /*!< COMPx output polarity */ -#define COMP_CSR_COMPxOUTVALUE ((uint32_t)0x40000000U) /*!< COMPx output level */ -#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000U) /*!< COMPx lock */ +#define COMP_CSR_COMPxEN_Pos (0U) +#define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */ +#define COMP_CSR_COMPxPOLARITY_Pos (15U) +#define COMP_CSR_COMPxPOLARITY_Msk (0x1U << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */ +#define COMP_CSR_COMPxOUTVALUE_Pos (30U) +#define COMP_CSR_COMPxOUTVALUE_Msk (0x1U << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */ +#define COMP_CSR_COMPxLOCK_Pos (31U) +#define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */ /* Reference defines */ #define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ @@ -803,26 +983,40 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ +#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET the CRC computation unit bit */ -#define CRC_CR_POLYSIZE ((uint32_t)0x00000018U) /*!< Polynomial size bits */ -#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008U) /*!< Polynomial size bit 0 */ -#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010U) /*!< Polynomial size bit 1 */ -#define CRC_CR_REV_IN ((uint32_t)0x00000060U) /*!< REV_IN Reverse Input Data bits */ -#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ -#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ -#define CRC_CR_REV_OUT ((uint32_t)0x00000080U) /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ /******************* Bit definition for CRC_INIT register *******************/ -#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFFU) /*!< Initial CRC value bits */ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ -#define CRC_POL_POL ((uint32_t)0xFFFFFFFFU) /*!< Coefficients of the polynomial */ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ /******************************************************************************/ /* */ @@ -831,42 +1025,70 @@ typedef struct /******************************************************************************/ /**************** Bit definition for DBGMCU_IDCODE register *****************/ -#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU) /*!< Device Identifier */ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ -#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U) /*!< REV_ID[15:0] bits (Revision Identifier) */ -#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ -#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ -#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000U) /*!< Bit 2 */ -#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000U) /*!< Bit 3 */ -#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000U) /*!< Bit 4 */ -#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000U) /*!< Bit 5 */ -#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000U) /*!< Bit 6 */ -#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000U) /*!< Bit 7 */ -#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000U) /*!< Bit 8 */ -#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000U) /*!< Bit 9 */ -#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000U) /*!< Bit 10 */ -#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000U) /*!< Bit 11 */ -#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000U) /*!< Bit 12 */ -#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000U) /*!< Bit 13 */ -#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000U) /*!< Bit 14 */ -#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000U) /*!< Bit 15 */ +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ +#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ +#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ +#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ +#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ +#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ +#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ +#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ +#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ +#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ +#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ +#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ +#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ +#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ +#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ +#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ +#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ /****************** Bit definition for DBGMCU_CR register *******************/ -#define DBGMCU_CR_DBG ((uint32_t)0x00000007U) /*!< Debug mode mask */ -#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001U) /*!< Debug Sleep Mode */ -#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U) /*!< Debug Stop Mode */ -#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U) /*!< Debug Standby mode */ +#define DBGMCU_CR_DBG_Pos (0U) +#define DBGMCU_CR_DBG_Msk (0x7U << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */ +#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */ +#define DBGMCU_CR_DBG_SLEEP_Pos (0U) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ /****************** Bit definition for DBGMCU_APB1_FZ register **************/ -#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001U) /*!< TIM2 counter stopped when core is halted */ -#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400U) /*!< RTC Calendar frozen when core is halted */ -#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800U) /*!< Debug Window Watchdog stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000U) /*!< Debug Independent Watchdog stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_I2C1_STOP ((uint32_t)0x00200000U) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP ((uint32_t)0x80000000U) /*!< LPTIM1 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) +#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */ +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U) +#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U) +#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */ +#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */ /****************** Bit definition for DBGMCU_APB2_FZ register **************/ -#define DBGMCU_APB2_FZ_DBG_TIM22_STOP ((uint32_t)0x00000020U) /*!< TIM22 counter stopped when core is halted */ -#define DBGMCU_APB2_FZ_DBG_TIM21_STOP ((uint32_t)0x00000004U) /*!< TIM21 counter stopped when core is halted */ +#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U) +#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */ +#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U) +#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */ /******************************************************************************/ /* */ @@ -875,108 +1097,263 @@ typedef struct /******************************************************************************/ /******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error flag */ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ /******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt clear */ -#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error clear */ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ /******************* Bit definition for DMA_CCR register ********************/ -#define DMA_CCR_EN ((uint32_t)0x00000001U) /*!< Channel enable */ -#define DMA_CCR_TCIE ((uint32_t)0x00000002U) /*!< Transfer complete interrupt enable */ -#define DMA_CCR_HTIE ((uint32_t)0x00000004U) /*!< Half Transfer interrupt enable */ -#define DMA_CCR_TEIE ((uint32_t)0x00000008U) /*!< Transfer error interrupt enable */ -#define DMA_CCR_DIR ((uint32_t)0x00000010U) /*!< Data transfer direction */ -#define DMA_CCR_CIRC ((uint32_t)0x00000020U) /*!< Circular mode */ -#define DMA_CCR_PINC ((uint32_t)0x00000040U) /*!< Peripheral increment mode */ -#define DMA_CCR_MINC ((uint32_t)0x00000080U) /*!< Memory increment mode */ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ -#define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */ -#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */ +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ -#define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ -#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ -#define DMA_CCR_PL ((uint32_t)0x00003000U) /*!< PL[1:0] bits(Channel Priority level)*/ -#define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ -#define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ -#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /*!< Memory to memory mode */ +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ /****************** Bit definition for DMA_CNDTR register *******************/ -#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ /****************** Bit definition for DMA_CPAR register ********************/ -#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ /****************** Bit definition for DMA_CMAR register ********************/ -#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ /******************* Bit definition for DMA_CSELR register *******************/ -#define DMA_CSELR_C1S ((uint32_t)0x0000000FU) /*!< Channel 1 Selection */ -#define DMA_CSELR_C2S ((uint32_t)0x000000F0U) /*!< Channel 2 Selection */ -#define DMA_CSELR_C3S ((uint32_t)0x00000F00U) /*!< Channel 3 Selection */ -#define DMA_CSELR_C4S ((uint32_t)0x0000F000U) /*!< Channel 4 Selection */ -#define DMA_CSELR_C5S ((uint32_t)0x000F0000U) /*!< Channel 5 Selection */ -#define DMA_CSELR_C6S ((uint32_t)0x00F00000U) /*!< Channel 6 Selection */ -#define DMA_CSELR_C7S ((uint32_t)0x0F000000U) /*!< Channel 7 Selection */ - +#define DMA_CSELR_C1S_Pos (0U) +#define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */ +#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */ +#define DMA_CSELR_C2S_Pos (4U) +#define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */ +#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */ +#define DMA_CSELR_C3S_Pos (8U) +#define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */ +#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */ +#define DMA_CSELR_C4S_Pos (12U) +#define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */ +#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */ +#define DMA_CSELR_C5S_Pos (16U) +#define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */ +#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */ +#define DMA_CSELR_C6S_Pos (20U) +#define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */ +#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */ +#define DMA_CSELR_C7S_Pos (24U) +#define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */ +#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */ /******************************************************************************/ /* */ @@ -985,88 +1362,248 @@ typedef struct /******************************************************************************/ /******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_IM0 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_IM1 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_IM2 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_IM3 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_IM4 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_IM5 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_IM6 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_IM7 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_IM8 ((uint32_t)0x00000100U) /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_IM9 ((uint32_t)0x00000200U) /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_IM10 ((uint32_t)0x00000400U) /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_IM11 ((uint32_t)0x00000800U) /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_IM12 ((uint32_t)0x00001000U) /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_IM13 ((uint32_t)0x00002000U) /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_IM14 ((uint32_t)0x00004000U) /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_IM15 ((uint32_t)0x00008000U) /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_IM16 ((uint32_t)0x00010000U) /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_IM17 ((uint32_t)0x00020000U) /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_IM18 ((uint32_t)0x00040000U) /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_IM19 ((uint32_t)0x00080000U) /*!< Interrupt Mask on line 19 */ -#define EXTI_IMR_IM20 ((uint32_t)0x00100000U) /*!< Interrupt Mask on line 20 */ -#define EXTI_IMR_IM21 ((uint32_t)0x00200000U) /*!< Interrupt Mask on line 21 */ -#define EXTI_IMR_IM22 ((uint32_t)0x00400000U) /*!< Interrupt Mask on line 22 */ -#define EXTI_IMR_IM23 ((uint32_t)0x00800000U) /*!< Interrupt Mask on line 23 */ -#define EXTI_IMR_IM25 ((uint32_t)0x02000000U) /*!< Interrupt Mask on line 25 */ -#define EXTI_IMR_IM26 ((uint32_t)0x04000000U) /*!< Interrupt Mask on line 26 */ -#define EXTI_IMR_IM28 ((uint32_t)0x10000000U) /*!< Interrupt Mask on line 28 */ -#define EXTI_IMR_IM29 ((uint32_t)0x20000000U) /*!< Interrupt Mask on line 29 */ +#define EXTI_IMR_IM0_Pos (0U) +#define EXTI_IMR_IM0_Msk (0x1U << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_IM1_Pos (1U) +#define EXTI_IMR_IM1_Msk (0x1U << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_IM2_Pos (2U) +#define EXTI_IMR_IM2_Msk (0x1U << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_IM3_Pos (3U) +#define EXTI_IMR_IM3_Msk (0x1U << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_IM4_Pos (4U) +#define EXTI_IMR_IM4_Msk (0x1U << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_IM5_Pos (5U) +#define EXTI_IMR_IM5_Msk (0x1U << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_IM6_Pos (6U) +#define EXTI_IMR_IM6_Msk (0x1U << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_IM7_Pos (7U) +#define EXTI_IMR_IM7_Msk (0x1U << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_IM8_Pos (8U) +#define EXTI_IMR_IM8_Msk (0x1U << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_IM9_Pos (9U) +#define EXTI_IMR_IM9_Msk (0x1U << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_IM10_Pos (10U) +#define EXTI_IMR_IM10_Msk (0x1U << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_IM11_Pos (11U) +#define EXTI_IMR_IM11_Msk (0x1U << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_IM12_Pos (12U) +#define EXTI_IMR_IM12_Msk (0x1U << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_IM13_Pos (13U) +#define EXTI_IMR_IM13_Msk (0x1U << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_IM14_Pos (14U) +#define EXTI_IMR_IM14_Msk (0x1U << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_IM15_Pos (15U) +#define EXTI_IMR_IM15_Msk (0x1U << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_IM16_Pos (16U) +#define EXTI_IMR_IM16_Msk (0x1U << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_IM17_Pos (17U) +#define EXTI_IMR_IM17_Msk (0x1U << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_IM18_Pos (18U) +#define EXTI_IMR_IM18_Msk (0x1U << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_IM19_Pos (19U) +#define EXTI_IMR_IM19_Msk (0x1U << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR_IM20_Pos (20U) +#define EXTI_IMR_IM20_Msk (0x1U << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */ +#define EXTI_IMR_IM21_Pos (21U) +#define EXTI_IMR_IM21_Msk (0x1U << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */ +#define EXTI_IMR_IM22_Pos (22U) +#define EXTI_IMR_IM22_Msk (0x1U << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */ +#define EXTI_IMR_IM23_Pos (23U) +#define EXTI_IMR_IM23_Msk (0x1U << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR_IM25_Pos (25U) +#define EXTI_IMR_IM25_Msk (0x1U << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR_IM26_Pos (26U) +#define EXTI_IMR_IM26_Msk (0x1U << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */ +#define EXTI_IMR_IM28_Pos (28U) +#define EXTI_IMR_IM28_Msk (0x1U << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */ +#define EXTI_IMR_IM29_Pos (29U) +#define EXTI_IMR_IM29_Msk (0x1U << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */ + +#define EXTI_IMR_IM_Pos (0U) +#define EXTI_IMR_IM_Msk (0x36FFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */ +#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ /****************** Bit definition for EXTI_EMR register ********************/ -#define EXTI_EMR_EM0 ((uint32_t)0x00000001U) /*!< Event Mask on line 0 */ -#define EXTI_EMR_EM1 ((uint32_t)0x00000002U) /*!< Event Mask on line 1 */ -#define EXTI_EMR_EM2 ((uint32_t)0x00000004U) /*!< Event Mask on line 2 */ -#define EXTI_EMR_EM3 ((uint32_t)0x00000008U) /*!< Event Mask on line 3 */ -#define EXTI_EMR_EM4 ((uint32_t)0x00000010U) /*!< Event Mask on line 4 */ -#define EXTI_EMR_EM5 ((uint32_t)0x00000020U) /*!< Event Mask on line 5 */ -#define EXTI_EMR_EM6 ((uint32_t)0x00000040U) /*!< Event Mask on line 6 */ -#define EXTI_EMR_EM7 ((uint32_t)0x00000080U) /*!< Event Mask on line 7 */ -#define EXTI_EMR_EM8 ((uint32_t)0x00000100U) /*!< Event Mask on line 8 */ -#define EXTI_EMR_EM9 ((uint32_t)0x00000200U) /*!< Event Mask on line 9 */ -#define EXTI_EMR_EM10 ((uint32_t)0x00000400U) /*!< Event Mask on line 10 */ -#define EXTI_EMR_EM11 ((uint32_t)0x00000800U) /*!< Event Mask on line 11 */ -#define EXTI_EMR_EM12 ((uint32_t)0x00001000U) /*!< Event Mask on line 12 */ -#define EXTI_EMR_EM13 ((uint32_t)0x00002000U) /*!< Event Mask on line 13 */ -#define EXTI_EMR_EM14 ((uint32_t)0x00004000U) /*!< Event Mask on line 14 */ -#define EXTI_EMR_EM15 ((uint32_t)0x00008000U) /*!< Event Mask on line 15 */ -#define EXTI_EMR_EM16 ((uint32_t)0x00010000U) /*!< Event Mask on line 16 */ -#define EXTI_EMR_EM17 ((uint32_t)0x00020000U) /*!< Event Mask on line 17 */ -#define EXTI_EMR_EM18 ((uint32_t)0x00040000U) /*!< Event Mask on line 18 */ -#define EXTI_EMR_EM19 ((uint32_t)0x00080000U) /*!< Event Mask on line 19 */ -#define EXTI_EMR_EM20 ((uint32_t)0x00100000U) /*!< Event Mask on line 20 */ -#define EXTI_EMR_EM21 ((uint32_t)0x00200000U) /*!< Event Mask on line 21 */ -#define EXTI_EMR_EM22 ((uint32_t)0x00400000U) /*!< Event Mask on line 22 */ -#define EXTI_EMR_EM23 ((uint32_t)0x00800000U) /*!< Event Mask on line 23 */ -#define EXTI_EMR_EM25 ((uint32_t)0x02000000U) /*!< Event Mask on line 25 */ -#define EXTI_EMR_EM26 ((uint32_t)0x04000000U) /*!< Event Mask on line 26 */ -#define EXTI_EMR_EM28 ((uint32_t)0x10000000U) /*!< Event Mask on line 28 */ -#define EXTI_EMR_EM29 ((uint32_t)0x20000000U) /*!< Event Mask on line 29 */ +#define EXTI_EMR_EM0_Pos (0U) +#define EXTI_EMR_EM0_Msk (0x1U << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR_EM1_Pos (1U) +#define EXTI_EMR_EM1_Msk (0x1U << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR_EM2_Pos (2U) +#define EXTI_EMR_EM2_Msk (0x1U << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR_EM3_Pos (3U) +#define EXTI_EMR_EM3_Msk (0x1U << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR_EM4_Pos (4U) +#define EXTI_EMR_EM4_Msk (0x1U << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR_EM5_Pos (5U) +#define EXTI_EMR_EM5_Msk (0x1U << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR_EM6_Pos (6U) +#define EXTI_EMR_EM6_Msk (0x1U << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR_EM7_Pos (7U) +#define EXTI_EMR_EM7_Msk (0x1U << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR_EM8_Pos (8U) +#define EXTI_EMR_EM8_Msk (0x1U << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR_EM9_Pos (9U) +#define EXTI_EMR_EM9_Msk (0x1U << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR_EM10_Pos (10U) +#define EXTI_EMR_EM10_Msk (0x1U << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR_EM11_Pos (11U) +#define EXTI_EMR_EM11_Msk (0x1U << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR_EM12_Pos (12U) +#define EXTI_EMR_EM12_Msk (0x1U << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR_EM13_Pos (13U) +#define EXTI_EMR_EM13_Msk (0x1U << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR_EM14_Pos (14U) +#define EXTI_EMR_EM14_Msk (0x1U << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR_EM15_Pos (15U) +#define EXTI_EMR_EM15_Msk (0x1U << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR_EM16_Pos (16U) +#define EXTI_EMR_EM16_Msk (0x1U << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR_EM17_Pos (17U) +#define EXTI_EMR_EM17_Msk (0x1U << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR_EM18_Pos (18U) +#define EXTI_EMR_EM18_Msk (0x1U << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */ +#define EXTI_EMR_EM19_Pos (19U) +#define EXTI_EMR_EM19_Msk (0x1U << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR_EM20_Pos (20U) +#define EXTI_EMR_EM20_Msk (0x1U << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */ +#define EXTI_EMR_EM21_Pos (21U) +#define EXTI_EMR_EM21_Msk (0x1U << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */ +#define EXTI_EMR_EM22_Pos (22U) +#define EXTI_EMR_EM22_Msk (0x1U << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */ +#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */ +#define EXTI_EMR_EM23_Pos (23U) +#define EXTI_EMR_EM23_Msk (0x1U << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR_EM25_Pos (25U) +#define EXTI_EMR_EM25_Msk (0x1U << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR_EM26_Pos (26U) +#define EXTI_EMR_EM26_Msk (0x1U << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */ +#define EXTI_EMR_EM28_Pos (28U) +#define EXTI_EMR_EM28_Msk (0x1U << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */ +#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */ +#define EXTI_EMR_EM29_Pos (29U) +#define EXTI_EMR_EM29_Msk (0x1U << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */ +#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */ /******************* Bit definition for EXTI_RTSR register ******************/ -#define EXTI_RTSR_RT0 ((uint32_t)0x00000001U) /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_RT1 ((uint32_t)0x00000002U) /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_RT2 ((uint32_t)0x00000004U) /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_RT3 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_RT4 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_RT5 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_RT6 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_RT7 ((uint32_t)0x00000080U) /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_RT8 ((uint32_t)0x00000100U) /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_RT9 ((uint32_t)0x00000200U) /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_RT10 ((uint32_t)0x00000400U) /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_RT11 ((uint32_t)0x00000800U) /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_RT12 ((uint32_t)0x00001000U) /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_RT13 ((uint32_t)0x00002000U) /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_RT14 ((uint32_t)0x00004000U) /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_RT15 ((uint32_t)0x00008000U) /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_RT16 ((uint32_t)0x00010000U) /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_RT17 ((uint32_t)0x00020000U) /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_RT19 ((uint32_t)0x00080000U) /*!< Rising trigger event configuration bit of line 19 */ -#define EXTI_RTSR_RT20 ((uint32_t)0x00100000U) /*!< Rising trigger event configuration bit of line 20 */ -#define EXTI_RTSR_RT21 ((uint32_t)0x00200000U) /*!< Rising trigger event configuration bit of line 21 */ -#define EXTI_RTSR_RT22 ((uint32_t)0x00400000U) /*!< Rising trigger event configuration bit of line 22 */ +#define EXTI_RTSR_RT0_Pos (0U) +#define EXTI_RTSR_RT0_Msk (0x1U << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_RT1_Pos (1U) +#define EXTI_RTSR_RT1_Msk (0x1U << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_RT2_Pos (2U) +#define EXTI_RTSR_RT2_Msk (0x1U << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_RT3_Pos (3U) +#define EXTI_RTSR_RT3_Msk (0x1U << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_RT4_Pos (4U) +#define EXTI_RTSR_RT4_Msk (0x1U << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_RT5_Pos (5U) +#define EXTI_RTSR_RT5_Msk (0x1U << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_RT6_Pos (6U) +#define EXTI_RTSR_RT6_Msk (0x1U << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_RT7_Pos (7U) +#define EXTI_RTSR_RT7_Msk (0x1U << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_RT8_Pos (8U) +#define EXTI_RTSR_RT8_Msk (0x1U << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_RT9_Pos (9U) +#define EXTI_RTSR_RT9_Msk (0x1U << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_RT10_Pos (10U) +#define EXTI_RTSR_RT10_Msk (0x1U << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_RT11_Pos (11U) +#define EXTI_RTSR_RT11_Msk (0x1U << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_RT12_Pos (12U) +#define EXTI_RTSR_RT12_Msk (0x1U << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_RT13_Pos (13U) +#define EXTI_RTSR_RT13_Msk (0x1U << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_RT14_Pos (14U) +#define EXTI_RTSR_RT14_Msk (0x1U << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_RT15_Pos (15U) +#define EXTI_RTSR_RT15_Msk (0x1U << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_RT16_Pos (16U) +#define EXTI_RTSR_RT16_Msk (0x1U << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_RT17_Pos (17U) +#define EXTI_RTSR_RT17_Msk (0x1U << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_RT19_Pos (19U) +#define EXTI_RTSR_RT19_Msk (0x1U << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */ +#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_RTSR_RT20_Pos (20U) +#define EXTI_RTSR_RT20_Msk (0x1U << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */ +#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ +#define EXTI_RTSR_RT21_Pos (21U) +#define EXTI_RTSR_RT21_Msk (0x1U << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */ +#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ +#define EXTI_RTSR_RT22_Pos (22U) +#define EXTI_RTSR_RT22_Msk (0x1U << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */ +#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */ /* Legacy defines */ #define EXTI_RTSR_TR0 EXTI_RTSR_RT0 @@ -1093,28 +1630,72 @@ typedef struct #define EXTI_RTSR_TR22 EXTI_RTSR_RT22 /******************* Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_FT0 ((uint32_t)0x00000001U) /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_FT1 ((uint32_t)0x00000002U) /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_FT2 ((uint32_t)0x00000004U) /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_FT3 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_FT4 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_FT5 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_FT6 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_FT7 ((uint32_t)0x00000080U) /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_FT8 ((uint32_t)0x00000100U) /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_FT9 ((uint32_t)0x00000200U) /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_FT10 ((uint32_t)0x00000400U) /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_FT11 ((uint32_t)0x00000800U) /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_FT12 ((uint32_t)0x00001000U) /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_FT13 ((uint32_t)0x00002000U) /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_FT14 ((uint32_t)0x00004000U) /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_FT15 ((uint32_t)0x00008000U) /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_FT16 ((uint32_t)0x00010000U) /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_FT17 ((uint32_t)0x00020000U) /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_FT19 ((uint32_t)0x00080000U) /*!< Falling trigger event configuration bit of line 19 */ -#define EXTI_FTSR_FT20 ((uint32_t)0x00100000U) /*!< Falling trigger event configuration bit of line 20 */ -#define EXTI_FTSR_FT21 ((uint32_t)0x00200000U) /*!< Falling trigger event configuration bit of line 21 */ -#define EXTI_FTSR_FT22 ((uint32_t)0x00400000U) /*!< Falling trigger event configuration bit of line 22 */ +#define EXTI_FTSR_FT0_Pos (0U) +#define EXTI_FTSR_FT0_Msk (0x1U << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_FT1_Pos (1U) +#define EXTI_FTSR_FT1_Msk (0x1U << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_FT2_Pos (2U) +#define EXTI_FTSR_FT2_Msk (0x1U << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_FT3_Pos (3U) +#define EXTI_FTSR_FT3_Msk (0x1U << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_FT4_Pos (4U) +#define EXTI_FTSR_FT4_Msk (0x1U << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_FT5_Pos (5U) +#define EXTI_FTSR_FT5_Msk (0x1U << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_FT6_Pos (6U) +#define EXTI_FTSR_FT6_Msk (0x1U << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_FT7_Pos (7U) +#define EXTI_FTSR_FT7_Msk (0x1U << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_FT8_Pos (8U) +#define EXTI_FTSR_FT8_Msk (0x1U << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_FT9_Pos (9U) +#define EXTI_FTSR_FT9_Msk (0x1U << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_FT10_Pos (10U) +#define EXTI_FTSR_FT10_Msk (0x1U << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_FT11_Pos (11U) +#define EXTI_FTSR_FT11_Msk (0x1U << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_FT12_Pos (12U) +#define EXTI_FTSR_FT12_Msk (0x1U << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_FT13_Pos (13U) +#define EXTI_FTSR_FT13_Msk (0x1U << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_FT14_Pos (14U) +#define EXTI_FTSR_FT14_Msk (0x1U << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_FT15_Pos (15U) +#define EXTI_FTSR_FT15_Msk (0x1U << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_FT16_Pos (16U) +#define EXTI_FTSR_FT16_Msk (0x1U << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_FT17_Pos (17U) +#define EXTI_FTSR_FT17_Msk (0x1U << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_FT19_Pos (19U) +#define EXTI_FTSR_FT19_Msk (0x1U << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */ +#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_FTSR_FT20_Pos (20U) +#define EXTI_FTSR_FT20_Msk (0x1U << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */ +#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */ +#define EXTI_FTSR_FT21_Pos (21U) +#define EXTI_FTSR_FT21_Msk (0x1U << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */ +#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ +#define EXTI_FTSR_FT22_Pos (22U) +#define EXTI_FTSR_FT22_Msk (0x1U << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */ +#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */ /* Legacy defines */ #define EXTI_FTSR_TR0 EXTI_FTSR_FT0 @@ -1141,28 +1722,72 @@ typedef struct #define EXTI_FTSR_TR22 EXTI_FTSR_FT22 /******************* Bit definition for EXTI_SWIER register *******************/ -#define EXTI_SWIER_SWI0 ((uint32_t)0x00000001U) /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWI1 ((uint32_t)0x00000002U) /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWI2 ((uint32_t)0x00000004U) /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWI3 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWI4 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWI5 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWI6 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWI7 ((uint32_t)0x00000080U) /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWI8 ((uint32_t)0x00000100U) /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWI9 ((uint32_t)0x00000200U) /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWI10 ((uint32_t)0x00000400U) /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWI11 ((uint32_t)0x00000800U) /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWI12 ((uint32_t)0x00001000U) /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWI13 ((uint32_t)0x00002000U) /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWI14 ((uint32_t)0x00004000U) /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWI15 ((uint32_t)0x00008000U) /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWI16 ((uint32_t)0x00010000U) /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWI17 ((uint32_t)0x00020000U) /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWI19 ((uint32_t)0x00080000U) /*!< Software Interrupt on line 19 */ -#define EXTI_SWIER_SWI20 ((uint32_t)0x00100000U) /*!< Software Interrupt on line 20 */ -#define EXTI_SWIER_SWI21 ((uint32_t)0x00200000U) /*!< Software Interrupt on line 21 */ -#define EXTI_SWIER_SWI22 ((uint32_t)0x00400000U) /*!< Software Interrupt on line 22 */ +#define EXTI_SWIER_SWI0_Pos (0U) +#define EXTI_SWIER_SWI0_Msk (0x1U << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWI1_Pos (1U) +#define EXTI_SWIER_SWI1_Msk (0x1U << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWI2_Pos (2U) +#define EXTI_SWIER_SWI2_Msk (0x1U << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWI3_Pos (3U) +#define EXTI_SWIER_SWI3_Msk (0x1U << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWI4_Pos (4U) +#define EXTI_SWIER_SWI4_Msk (0x1U << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWI5_Pos (5U) +#define EXTI_SWIER_SWI5_Msk (0x1U << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWI6_Pos (6U) +#define EXTI_SWIER_SWI6_Msk (0x1U << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWI7_Pos (7U) +#define EXTI_SWIER_SWI7_Msk (0x1U << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWI8_Pos (8U) +#define EXTI_SWIER_SWI8_Msk (0x1U << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWI9_Pos (9U) +#define EXTI_SWIER_SWI9_Msk (0x1U << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWI10_Pos (10U) +#define EXTI_SWIER_SWI10_Msk (0x1U << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWI11_Pos (11U) +#define EXTI_SWIER_SWI11_Msk (0x1U << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWI12_Pos (12U) +#define EXTI_SWIER_SWI12_Msk (0x1U << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWI13_Pos (13U) +#define EXTI_SWIER_SWI13_Msk (0x1U << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWI14_Pos (14U) +#define EXTI_SWIER_SWI14_Msk (0x1U << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWI15_Pos (15U) +#define EXTI_SWIER_SWI15_Msk (0x1U << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWI16_Pos (16U) +#define EXTI_SWIER_SWI16_Msk (0x1U << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWI17_Pos (17U) +#define EXTI_SWIER_SWI17_Msk (0x1U << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWI19_Pos (19U) +#define EXTI_SWIER_SWI19_Msk (0x1U << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */ +#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */ +#define EXTI_SWIER_SWI20_Pos (20U) +#define EXTI_SWIER_SWI20_Msk (0x1U << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */ +#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */ +#define EXTI_SWIER_SWI21_Pos (21U) +#define EXTI_SWIER_SWI21_Msk (0x1U << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */ +#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */ +#define EXTI_SWIER_SWI22_Pos (22U) +#define EXTI_SWIER_SWI22_Msk (0x1U << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */ +#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */ /* Legacy defines */ #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0 @@ -1189,28 +1814,72 @@ typedef struct #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22 /****************** Bit definition for EXTI_PR register *********************/ -#define EXTI_PR_PIF0 ((uint32_t)0x00000001U) /*!< Pending bit 0 */ -#define EXTI_PR_PIF1 ((uint32_t)0x00000002U) /*!< Pending bit 1 */ -#define EXTI_PR_PIF2 ((uint32_t)0x00000004U) /*!< Pending bit 2 */ -#define EXTI_PR_PIF3 ((uint32_t)0x00000008U) /*!< Pending bit 3 */ -#define EXTI_PR_PIF4 ((uint32_t)0x00000010U) /*!< Pending bit 4 */ -#define EXTI_PR_PIF5 ((uint32_t)0x00000020U) /*!< Pending bit 5 */ -#define EXTI_PR_PIF6 ((uint32_t)0x00000040U) /*!< Pending bit 6 */ -#define EXTI_PR_PIF7 ((uint32_t)0x00000080U) /*!< Pending bit 7 */ -#define EXTI_PR_PIF8 ((uint32_t)0x00000100U) /*!< Pending bit 8 */ -#define EXTI_PR_PIF9 ((uint32_t)0x00000200U) /*!< Pending bit 9 */ -#define EXTI_PR_PIF10 ((uint32_t)0x00000400U) /*!< Pending bit 10 */ -#define EXTI_PR_PIF11 ((uint32_t)0x00000800U) /*!< Pending bit 11 */ -#define EXTI_PR_PIF12 ((uint32_t)0x00001000U) /*!< Pending bit 12 */ -#define EXTI_PR_PIF13 ((uint32_t)0x00002000U) /*!< Pending bit 13 */ -#define EXTI_PR_PIF14 ((uint32_t)0x00004000U) /*!< Pending bit 14 */ -#define EXTI_PR_PIF15 ((uint32_t)0x00008000U) /*!< Pending bit 15 */ -#define EXTI_PR_PIF16 ((uint32_t)0x00010000U) /*!< Pending bit 16 */ -#define EXTI_PR_PIF17 ((uint32_t)0x00020000U) /*!< Pending bit 17 */ -#define EXTI_PR_PIF19 ((uint32_t)0x00080000U) /*!< Pending bit 19 */ -#define EXTI_PR_PIF20 ((uint32_t)0x00100000U) /*!< Pending bit 20 */ -#define EXTI_PR_PIF21 ((uint32_t)0x00200000U) /*!< Pending bit 21 */ -#define EXTI_PR_PIF22 ((uint32_t)0x00400000U) /*!< Pending bit 22 */ +#define EXTI_PR_PIF0_Pos (0U) +#define EXTI_PR_PIF0_Msk (0x1U << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */ +#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */ +#define EXTI_PR_PIF1_Pos (1U) +#define EXTI_PR_PIF1_Msk (0x1U << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */ +#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */ +#define EXTI_PR_PIF2_Pos (2U) +#define EXTI_PR_PIF2_Msk (0x1U << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */ +#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */ +#define EXTI_PR_PIF3_Pos (3U) +#define EXTI_PR_PIF3_Msk (0x1U << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */ +#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */ +#define EXTI_PR_PIF4_Pos (4U) +#define EXTI_PR_PIF4_Msk (0x1U << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */ +#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */ +#define EXTI_PR_PIF5_Pos (5U) +#define EXTI_PR_PIF5_Msk (0x1U << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */ +#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */ +#define EXTI_PR_PIF6_Pos (6U) +#define EXTI_PR_PIF6_Msk (0x1U << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */ +#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */ +#define EXTI_PR_PIF7_Pos (7U) +#define EXTI_PR_PIF7_Msk (0x1U << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */ +#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */ +#define EXTI_PR_PIF8_Pos (8U) +#define EXTI_PR_PIF8_Msk (0x1U << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */ +#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */ +#define EXTI_PR_PIF9_Pos (9U) +#define EXTI_PR_PIF9_Msk (0x1U << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */ +#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */ +#define EXTI_PR_PIF10_Pos (10U) +#define EXTI_PR_PIF10_Msk (0x1U << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */ +#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */ +#define EXTI_PR_PIF11_Pos (11U) +#define EXTI_PR_PIF11_Msk (0x1U << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */ +#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */ +#define EXTI_PR_PIF12_Pos (12U) +#define EXTI_PR_PIF12_Msk (0x1U << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */ +#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */ +#define EXTI_PR_PIF13_Pos (13U) +#define EXTI_PR_PIF13_Msk (0x1U << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */ +#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */ +#define EXTI_PR_PIF14_Pos (14U) +#define EXTI_PR_PIF14_Msk (0x1U << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */ +#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */ +#define EXTI_PR_PIF15_Pos (15U) +#define EXTI_PR_PIF15_Msk (0x1U << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */ +#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */ +#define EXTI_PR_PIF16_Pos (16U) +#define EXTI_PR_PIF16_Msk (0x1U << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */ +#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */ +#define EXTI_PR_PIF17_Pos (17U) +#define EXTI_PR_PIF17_Msk (0x1U << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */ +#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */ +#define EXTI_PR_PIF19_Pos (19U) +#define EXTI_PR_PIF19_Msk (0x1U << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */ +#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */ +#define EXTI_PR_PIF20_Pos (20U) +#define EXTI_PR_PIF20_Msk (0x1U << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */ +#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */ +#define EXTI_PR_PIF21_Pos (21U) +#define EXTI_PR_PIF21_Msk (0x1U << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */ +#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */ +#define EXTI_PR_PIF22_Pos (22U) +#define EXTI_PR_PIF22_Msk (0x1U << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */ +#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */ /* Legacy defines */ #define EXTI_PR_PR0 EXTI_PR_PIF0 @@ -1243,52 +1912,118 @@ typedef struct /******************************************************************************/ /******************* Bit definition for FLASH_ACR register ******************/ -#define FLASH_ACR_LATENCY ((uint32_t)0x00000001U) /*!< LATENCY bit (Latency) */ -#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002U) /*!< Prefetch Buffer Enable */ -#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008U) /*!< Flash mode during sleep mode */ -#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010U) /*!< Flash mode during RUN mode */ -#define FLASH_ACR_DISAB_BUF ((uint32_t)0x00000020U) /*!< Disable Buffer */ -#define FLASH_ACR_PRE_READ ((uint32_t)0x00000040U) /*!< Pre-read data address */ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */ +#define FLASH_ACR_PRFTEN_Pos (1U) +#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */ +#define FLASH_ACR_SLEEP_PD_Pos (3U) +#define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */ +#define FLASH_ACR_RUN_PD_Pos (4U) +#define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */ +#define FLASH_ACR_DISAB_BUF_Pos (5U) +#define FLASH_ACR_DISAB_BUF_Msk (0x1U << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */ +#define FLASH_ACR_PRE_READ_Pos (6U) +#define FLASH_ACR_PRE_READ_Msk (0x1U << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */ +#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */ /******************* Bit definition for FLASH_PECR register ******************/ -#define FLASH_PECR_PELOCK ((uint32_t)0x00000001U) /*!< FLASH_PECR and Flash data Lock */ -#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002U) /*!< Program matrix Lock */ -#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004U) /*!< Option byte matrix Lock */ -#define FLASH_PECR_PROG ((uint32_t)0x00000008U) /*!< Program matrix selection */ -#define FLASH_PECR_DATA ((uint32_t)0x00000010U) /*!< Data matrix selection */ -#define FLASH_PECR_FIX ((uint32_t)0x00000100U) /*!< Fixed Time Data write for Word/Half Word/Byte programming */ -#define FLASH_PECR_ERASE ((uint32_t)0x00000200U) /*!< Page erasing mode */ -#define FLASH_PECR_FPRG ((uint32_t)0x00000400U) /*!< Fast Page/Half Page programming mode */ -#define FLASH_PECR_EOPIE ((uint32_t)0x00010000U) /*!< End of programming interrupt */ -#define FLASH_PECR_ERRIE ((uint32_t)0x00020000U) /*!< Error interrupt */ -#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000U) /*!< Launch the option byte loading */ -#define FLASH_PECR_HALF_ARRAY ((uint32_t)0x00080000U) /*!< Half array mode */ +#define FLASH_PECR_PELOCK_Pos (0U) +#define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */ +#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */ +#define FLASH_PECR_PRGLOCK_Pos (1U) +#define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */ +#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */ +#define FLASH_PECR_OPTLOCK_Pos (2U) +#define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */ +#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */ +#define FLASH_PECR_PROG_Pos (3U) +#define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */ +#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */ +#define FLASH_PECR_DATA_Pos (4U) +#define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */ +#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */ +#define FLASH_PECR_FIX_Pos (8U) +#define FLASH_PECR_FIX_Msk (0x1U << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */ +#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */ +#define FLASH_PECR_ERASE_Pos (9U) +#define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */ +#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */ +#define FLASH_PECR_FPRG_Pos (10U) +#define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */ +#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */ +#define FLASH_PECR_EOPIE_Pos (16U) +#define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */ +#define FLASH_PECR_ERRIE_Pos (17U) +#define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */ +#define FLASH_PECR_OBL_LAUNCH_Pos (18U) +#define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */ +#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */ +#define FLASH_PECR_HALF_ARRAY_Pos (19U) +#define FLASH_PECR_HALF_ARRAY_Msk (0x1U << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */ +#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */ /****************** Bit definition for FLASH_PDKEYR register ******************/ -#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */ +#define FLASH_PDKEYR_PDKEYR_Pos (0U) +#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */ /****************** Bit definition for FLASH_PEKEYR register ******************/ -#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */ +#define FLASH_PEKEYR_PEKEYR_Pos (0U) +#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */ /****************** Bit definition for FLASH_PRGKEYR register ******************/ -#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFFU) /*!< Program matrix Key */ +#define FLASH_PRGKEYR_PRGKEYR_Pos (0U) +#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */ /****************** Bit definition for FLASH_OPTKEYR register ******************/ -#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFFU) /*!< Option bytes matrix Key */ +#define FLASH_OPTKEYR_OPTKEYR_Pos (0U) +#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */ /****************** Bit definition for FLASH_SR register *******************/ -#define FLASH_SR_BSY ((uint32_t)0x00000001U) /*!< Busy */ -#define FLASH_SR_EOP ((uint32_t)0x00000002U) /*!< End Of Programming*/ -#define FLASH_SR_HVOFF ((uint32_t)0x00000004U) /*!< End of high voltage */ -#define FLASH_SR_READY ((uint32_t)0x00000008U) /*!< Flash ready after low power mode */ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ +#define FLASH_SR_EOP_Pos (1U) +#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000002 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/ +#define FLASH_SR_HVOFF_Pos (2U) +#define FLASH_SR_HVOFF_Msk (0x1U << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */ +#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */ +#define FLASH_SR_READY_Pos (3U) +#define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /*!< 0x00000008 */ +#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */ -#define FLASH_SR_WRPERR ((uint32_t)0x00000100U) /*!< Write protection error */ -#define FLASH_SR_PGAERR ((uint32_t)0x00000200U) /*!< Programming Alignment Error */ -#define FLASH_SR_SIZERR ((uint32_t)0x00000400U) /*!< Size error */ -#define FLASH_SR_OPTVERR ((uint32_t)0x00000800U) /*!< Option Valid error */ -#define FLASH_SR_RDERR ((uint32_t)0x00002000U) /*!< Read protected error */ -#define FLASH_SR_NOTZEROERR ((uint32_t)0x00010000U) /*!< Not Zero error */ -#define FLASH_SR_FWWERR ((uint32_t)0x00020000U) /*!< Write/Errase operation aborted */ +#define FLASH_SR_WRPERR_Pos (8U) +#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */ +#define FLASH_SR_PGAERR_Pos (9U) +#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */ +#define FLASH_SR_SIZERR_Pos (10U) +#define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ +#define FLASH_SR_OPTVERR_Pos (11U) +#define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */ +#define FLASH_SR_RDERR_Pos (13U) +#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */ +#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */ +#define FLASH_SR_NOTZEROERR_Pos (16U) +#define FLASH_SR_NOTZEROERR_Msk (0x1U << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */ +#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */ +#define FLASH_SR_FWWERR_Pos (17U) +#define FLASH_SR_FWWERR_Msk (0x1U << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */ /* Legacy defines */ #define FLASH_SR_FWWER FLASH_SR_FWWERR @@ -1296,17 +2031,35 @@ typedef struct #define FLASH_SR_ENDHV FLASH_SR_HVOFF /****************** Bit definition for FLASH_OPTR register *******************/ -#define FLASH_OPTR_RDPROT ((uint32_t)0x000000FFU) /*!< Read Protection */ -#define FLASH_OPTR_WPRMOD ((uint32_t)0x00000100U) /*!< Selection of protection mode of WPR bits */ -#define FLASH_OPTR_BOR_LEV ((uint32_t)0x000F0000U) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ -#define FLASH_OPTR_IWDG_SW ((uint32_t)0x00100000U) /*!< IWDG_SW */ -#define FLASH_OPTR_nRST_STOP ((uint32_t)0x00200000U) /*!< nRST_STOP */ -#define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00400000U) /*!< nRST_STDBY */ -#define FLASH_OPTR_USER ((uint32_t)0x00700000U) /*!< User Option Bytes */ -#define FLASH_OPTR_BOOT1 ((uint32_t)0x80000000U) /*!< BOOT1 */ +#define FLASH_OPTR_RDPROT_Pos (0U) +#define FLASH_OPTR_RDPROT_Msk (0xFFU << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */ +#define FLASH_OPTR_WPRMOD_Pos (8U) +#define FLASH_OPTR_WPRMOD_Msk (0x1U << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */ +#define FLASH_OPTR_BOR_LEV_Pos (16U) +#define FLASH_OPTR_BOR_LEV_Msk (0xFU << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ +#define FLASH_OPTR_IWDG_SW_Pos (20U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */ +#define FLASH_OPTR_nRST_STOP_Pos (21U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (22U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_USER_Pos (20U) +#define FLASH_OPTR_USER_Msk (0x7U << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */ +#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */ +#define FLASH_OPTR_BOOT1_Pos (31U) +#define FLASH_OPTR_BOOT1_Msk (0x1U << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */ /****************** Bit definition for FLASH_WRPR register ******************/ -#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFFU) /*!< Write Protection bits */ +#define FLASH_WRPR_WRP_Pos (0U) +#define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */ /******************************************************************************/ /* */ @@ -1314,299 +2067,525 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0 ((uint32_t)0x00000003U) -#define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001U) -#define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002U) -#define GPIO_MODER_MODE1 ((uint32_t)0x0000000CU) -#define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004U) -#define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008U) -#define GPIO_MODER_MODE2 ((uint32_t)0x00000030U) -#define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010U) -#define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020U) -#define GPIO_MODER_MODE3 ((uint32_t)0x000000C0U) -#define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040U) -#define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080U) -#define GPIO_MODER_MODE4 ((uint32_t)0x00000300U) -#define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100U) -#define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200U) -#define GPIO_MODER_MODE5 ((uint32_t)0x00000C00U) -#define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400U) -#define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800U) -#define GPIO_MODER_MODE6 ((uint32_t)0x00003000U) -#define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000U) -#define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000U) -#define GPIO_MODER_MODE7 ((uint32_t)0x0000C000U) -#define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000U) -#define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000U) -#define GPIO_MODER_MODE8 ((uint32_t)0x00030000U) -#define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000U) -#define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000U) -#define GPIO_MODER_MODE9 ((uint32_t)0x000C0000U) -#define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000U) -#define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000U) -#define GPIO_MODER_MODE10 ((uint32_t)0x00300000U) -#define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000U) -#define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000U) -#define GPIO_MODER_MODE11 ((uint32_t)0x00C00000U) -#define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000U) -#define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000U) -#define GPIO_MODER_MODE12 ((uint32_t)0x03000000U) -#define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000U) -#define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000U) -#define GPIO_MODER_MODE13 ((uint32_t)0x0C000000U) -#define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000U) -#define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000U) -#define GPIO_MODER_MODE14 ((uint32_t)0x30000000U) -#define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000U) -#define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000U) -#define GPIO_MODER_MODE15 ((uint32_t)0xC0000000U) -#define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000U) -#define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000U) +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_OTYPER register *****************/ -#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001U) -#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002U) -#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004U) -#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008U) -#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010U) -#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020U) -#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040U) -#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080U) -#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100U) -#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200U) -#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400U) -#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800U) -#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000U) -#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000U) -#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000U) -#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000U) +#define GPIO_OTYPER_OT_0 (0x00000001U) +#define GPIO_OTYPER_OT_1 (0x00000002U) +#define GPIO_OTYPER_OT_2 (0x00000004U) +#define GPIO_OTYPER_OT_3 (0x00000008U) +#define GPIO_OTYPER_OT_4 (0x00000010U) +#define GPIO_OTYPER_OT_5 (0x00000020U) +#define GPIO_OTYPER_OT_6 (0x00000040U) +#define GPIO_OTYPER_OT_7 (0x00000080U) +#define GPIO_OTYPER_OT_8 (0x00000100U) +#define GPIO_OTYPER_OT_9 (0x00000200U) +#define GPIO_OTYPER_OT_10 (0x00000400U) +#define GPIO_OTYPER_OT_11 (0x00000800U) +#define GPIO_OTYPER_OT_12 (0x00001000U) +#define GPIO_OTYPER_OT_13 (0x00002000U) +#define GPIO_OTYPER_OT_14 (0x00004000U) +#define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0 ((uint32_t)0x00000003U) -#define GPIO_OSPEEDER_OSPEED0_0 ((uint32_t)0x00000001U) -#define GPIO_OSPEEDER_OSPEED0_1 ((uint32_t)0x00000002U) -#define GPIO_OSPEEDER_OSPEED1 ((uint32_t)0x0000000CU) -#define GPIO_OSPEEDER_OSPEED1_0 ((uint32_t)0x00000004U) -#define GPIO_OSPEEDER_OSPEED1_1 ((uint32_t)0x00000008U) -#define GPIO_OSPEEDER_OSPEED2 ((uint32_t)0x00000030U) -#define GPIO_OSPEEDER_OSPEED2_0 ((uint32_t)0x00000010U) -#define GPIO_OSPEEDER_OSPEED2_1 ((uint32_t)0x00000020U) -#define GPIO_OSPEEDER_OSPEED3 ((uint32_t)0x000000C0U) -#define GPIO_OSPEEDER_OSPEED3_0 ((uint32_t)0x00000040U) -#define GPIO_OSPEEDER_OSPEED3_1 ((uint32_t)0x00000080U) -#define GPIO_OSPEEDER_OSPEED4 ((uint32_t)0x00000300U) -#define GPIO_OSPEEDER_OSPEED4_0 ((uint32_t)0x00000100U) -#define GPIO_OSPEEDER_OSPEED4_1 ((uint32_t)0x00000200U) -#define GPIO_OSPEEDER_OSPEED5 ((uint32_t)0x00000C00U) -#define GPIO_OSPEEDER_OSPEED5_0 ((uint32_t)0x00000400U) -#define GPIO_OSPEEDER_OSPEED5_1 ((uint32_t)0x00000800U) -#define GPIO_OSPEEDER_OSPEED6 ((uint32_t)0x00003000U) -#define GPIO_OSPEEDER_OSPEED6_0 ((uint32_t)0x00001000U) -#define GPIO_OSPEEDER_OSPEED6_1 ((uint32_t)0x00002000U) -#define GPIO_OSPEEDER_OSPEED7 ((uint32_t)0x0000C000U) -#define GPIO_OSPEEDER_OSPEED7_0 ((uint32_t)0x00004000U) -#define GPIO_OSPEEDER_OSPEED7_1 ((uint32_t)0x00008000U) -#define GPIO_OSPEEDER_OSPEED8 ((uint32_t)0x00030000U) -#define GPIO_OSPEEDER_OSPEED8_0 ((uint32_t)0x00010000U) -#define GPIO_OSPEEDER_OSPEED8_1 ((uint32_t)0x00020000U) -#define GPIO_OSPEEDER_OSPEED9 ((uint32_t)0x000C0000U) -#define GPIO_OSPEEDER_OSPEED9_0 ((uint32_t)0x00040000U) -#define GPIO_OSPEEDER_OSPEED9_1 ((uint32_t)0x00080000U) -#define GPIO_OSPEEDER_OSPEED10 ((uint32_t)0x00300000U) -#define GPIO_OSPEEDER_OSPEED10_0 ((uint32_t)0x00100000U) -#define GPIO_OSPEEDER_OSPEED10_1 ((uint32_t)0x00200000U) -#define GPIO_OSPEEDER_OSPEED11 ((uint32_t)0x00C00000U) -#define GPIO_OSPEEDER_OSPEED11_0 ((uint32_t)0x00400000U) -#define GPIO_OSPEEDER_OSPEED11_1 ((uint32_t)0x00800000U) -#define GPIO_OSPEEDER_OSPEED12 ((uint32_t)0x03000000U) -#define GPIO_OSPEEDER_OSPEED12_0 ((uint32_t)0x01000000U) -#define GPIO_OSPEEDER_OSPEED12_1 ((uint32_t)0x02000000U) -#define GPIO_OSPEEDER_OSPEED13 ((uint32_t)0x0C000000U) -#define GPIO_OSPEEDER_OSPEED13_0 ((uint32_t)0x04000000U) -#define GPIO_OSPEEDER_OSPEED13_1 ((uint32_t)0x08000000U) -#define GPIO_OSPEEDER_OSPEED14 ((uint32_t)0x30000000U) -#define GPIO_OSPEEDER_OSPEED14_0 ((uint32_t)0x10000000U) -#define GPIO_OSPEEDER_OSPEED14_1 ((uint32_t)0x20000000U) -#define GPIO_OSPEEDER_OSPEED15 ((uint32_t)0xC0000000U) -#define GPIO_OSPEEDER_OSPEED15_0 ((uint32_t)0x40000000U) -#define GPIO_OSPEEDER_OSPEED15_1 ((uint32_t)0x80000000U) +#define GPIO_OSPEEDER_OSPEED0_Pos (0U) +#define GPIO_OSPEEDER_OSPEED0_Msk (0x3U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0_0 (0x1U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDER_OSPEED0_1 (0x2U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDER_OSPEED1_Pos (2U) +#define GPIO_OSPEEDER_OSPEED1_Msk (0x3U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1_0 (0x1U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDER_OSPEED1_1 (0x2U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDER_OSPEED2_Pos (4U) +#define GPIO_OSPEEDER_OSPEED2_Msk (0x3U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2_0 (0x1U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDER_OSPEED2_1 (0x2U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDER_OSPEED3_Pos (6U) +#define GPIO_OSPEEDER_OSPEED3_Msk (0x3U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3_0 (0x1U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDER_OSPEED3_1 (0x2U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDER_OSPEED4_Pos (8U) +#define GPIO_OSPEEDER_OSPEED4_Msk (0x3U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4_0 (0x1U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDER_OSPEED4_1 (0x2U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDER_OSPEED5_Pos (10U) +#define GPIO_OSPEEDER_OSPEED5_Msk (0x3U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5_0 (0x1U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDER_OSPEED5_1 (0x2U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDER_OSPEED6_Pos (12U) +#define GPIO_OSPEEDER_OSPEED6_Msk (0x3U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6_0 (0x1U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDER_OSPEED6_1 (0x2U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDER_OSPEED7_Pos (14U) +#define GPIO_OSPEEDER_OSPEED7_Msk (0x3U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7_0 (0x1U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDER_OSPEED7_1 (0x2U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDER_OSPEED8_Pos (16U) +#define GPIO_OSPEEDER_OSPEED8_Msk (0x3U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8_0 (0x1U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDER_OSPEED8_1 (0x2U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDER_OSPEED9_Pos (18U) +#define GPIO_OSPEEDER_OSPEED9_Msk (0x3U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9_0 (0x1U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDER_OSPEED9_1 (0x2U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDER_OSPEED10_Pos (20U) +#define GPIO_OSPEEDER_OSPEED10_Msk (0x3U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10_0 (0x1U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDER_OSPEED10_1 (0x2U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDER_OSPEED11_Pos (22U) +#define GPIO_OSPEEDER_OSPEED11_Msk (0x3U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11_0 (0x1U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDER_OSPEED11_1 (0x2U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDER_OSPEED12_Pos (24U) +#define GPIO_OSPEEDER_OSPEED12_Msk (0x3U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12_0 (0x1U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDER_OSPEED12_1 (0x2U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDER_OSPEED13_Pos (26U) +#define GPIO_OSPEEDER_OSPEED13_Msk (0x3U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13_0 (0x1U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDER_OSPEED13_1 (0x2U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDER_OSPEED14_Pos (28U) +#define GPIO_OSPEEDER_OSPEED14_Msk (0x3U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14_0 (0x1U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDER_OSPEED14_1 (0x2U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDER_OSPEED15_Pos (30U) +#define GPIO_OSPEEDER_OSPEED15_Msk (0x3U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15_0 (0x1U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDER_OSPEED15_1 (0x2U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ /******************* Bit definition for GPIO_PUPDR register ******************/ -#define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003U) -#define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001U) -#define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002U) -#define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000CU) -#define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004U) -#define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008U) -#define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030U) -#define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010U) -#define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020U) -#define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0U) -#define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040U) -#define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080U) -#define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300U) -#define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100U) -#define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200U) -#define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00U) -#define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400U) -#define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800U) -#define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000U) -#define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000U) -#define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000U) -#define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000U) -#define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000U) -#define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000U) -#define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000U) -#define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000U) -#define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000U) -#define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000U) -#define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000U) -#define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000U) -#define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000U) -#define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000U) -#define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000U) -#define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000U) -#define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000U) -#define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000U) -#define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000U) -#define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000U) -#define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000U) -#define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000U) -#define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000U) -#define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000U) -#define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000U) -#define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000U) -#define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000U) -#define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000U) -#define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000U) -#define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000U) +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ /******************* Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0 ((uint32_t)0x00000001U) -#define GPIO_IDR_ID1 ((uint32_t)0x00000002U) -#define GPIO_IDR_ID2 ((uint32_t)0x00000004U) -#define GPIO_IDR_ID3 ((uint32_t)0x00000008U) -#define GPIO_IDR_ID4 ((uint32_t)0x00000010U) -#define GPIO_IDR_ID5 ((uint32_t)0x00000020U) -#define GPIO_IDR_ID6 ((uint32_t)0x00000040U) -#define GPIO_IDR_ID7 ((uint32_t)0x00000080U) -#define GPIO_IDR_ID8 ((uint32_t)0x00000100U) -#define GPIO_IDR_ID9 ((uint32_t)0x00000200U) -#define GPIO_IDR_ID10 ((uint32_t)0x00000400U) -#define GPIO_IDR_ID11 ((uint32_t)0x00000800U) -#define GPIO_IDR_ID12 ((uint32_t)0x00001000U) -#define GPIO_IDR_ID13 ((uint32_t)0x00002000U) -#define GPIO_IDR_ID14 ((uint32_t)0x00004000U) -#define GPIO_IDR_ID15 ((uint32_t)0x00008000U) +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk /****************** Bit definition for GPIO_ODR register ********************/ -#define GPIO_ODR_OD0 ((uint32_t)0x00000001U) -#define GPIO_ODR_OD1 ((uint32_t)0x00000002U) -#define GPIO_ODR_OD2 ((uint32_t)0x00000004U) -#define GPIO_ODR_OD3 ((uint32_t)0x00000008U) -#define GPIO_ODR_OD4 ((uint32_t)0x00000010U) -#define GPIO_ODR_OD5 ((uint32_t)0x00000020U) -#define GPIO_ODR_OD6 ((uint32_t)0x00000040U) -#define GPIO_ODR_OD7 ((uint32_t)0x00000080U) -#define GPIO_ODR_OD8 ((uint32_t)0x00000100U) -#define GPIO_ODR_OD9 ((uint32_t)0x00000200U) -#define GPIO_ODR_OD10 ((uint32_t)0x00000400U) -#define GPIO_ODR_OD11 ((uint32_t)0x00000800U) -#define GPIO_ODR_OD12 ((uint32_t)0x00001000U) -#define GPIO_ODR_OD13 ((uint32_t)0x00002000U) -#define GPIO_ODR_OD14 ((uint32_t)0x00004000U) -#define GPIO_ODR_OD15 ((uint32_t)0x00008000U) +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk /****************** Bit definition for GPIO_BSRR register ********************/ -#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001U) -#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002U) -#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004U) -#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008U) -#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010U) -#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020U) -#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040U) -#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080U) -#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100U) -#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200U) -#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400U) -#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800U) -#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000U) -#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000U) -#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000U) -#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000U) -#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000U) -#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000U) -#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000U) -#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000U) -#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000U) -#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000U) -#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000U) -#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000U) -#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000U) -#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000U) -#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000U) -#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000U) -#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000U) -#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000U) -#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000U) -#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000U) +#define GPIO_BSRR_BS_0 (0x00000001U) +#define GPIO_BSRR_BS_1 (0x00000002U) +#define GPIO_BSRR_BS_2 (0x00000004U) +#define GPIO_BSRR_BS_3 (0x00000008U) +#define GPIO_BSRR_BS_4 (0x00000010U) +#define GPIO_BSRR_BS_5 (0x00000020U) +#define GPIO_BSRR_BS_6 (0x00000040U) +#define GPIO_BSRR_BS_7 (0x00000080U) +#define GPIO_BSRR_BS_8 (0x00000100U) +#define GPIO_BSRR_BS_9 (0x00000200U) +#define GPIO_BSRR_BS_10 (0x00000400U) +#define GPIO_BSRR_BS_11 (0x00000800U) +#define GPIO_BSRR_BS_12 (0x00001000U) +#define GPIO_BSRR_BS_13 (0x00002000U) +#define GPIO_BSRR_BS_14 (0x00004000U) +#define GPIO_BSRR_BS_15 (0x00008000U) +#define GPIO_BSRR_BR_0 (0x00010000U) +#define GPIO_BSRR_BR_1 (0x00020000U) +#define GPIO_BSRR_BR_2 (0x00040000U) +#define GPIO_BSRR_BR_3 (0x00080000U) +#define GPIO_BSRR_BR_4 (0x00100000U) +#define GPIO_BSRR_BR_5 (0x00200000U) +#define GPIO_BSRR_BR_6 (0x00400000U) +#define GPIO_BSRR_BR_7 (0x00800000U) +#define GPIO_BSRR_BR_8 (0x01000000U) +#define GPIO_BSRR_BR_9 (0x02000000U) +#define GPIO_BSRR_BR_10 (0x04000000U) +#define GPIO_BSRR_BR_11 (0x08000000U) +#define GPIO_BSRR_BR_12 (0x10000000U) +#define GPIO_BSRR_BR_13 (0x20000000U) +#define GPIO_BSRR_BR_14 (0x40000000U) +#define GPIO_BSRR_BR_15 (0x80000000U) /****************** Bit definition for GPIO_LCKR register ********************/ -#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U) -#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U) -#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U) -#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U) -#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U) -#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U) -#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U) -#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U) -#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U) -#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U) -#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U) -#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U) -#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U) -#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U) -#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U) -#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U) -#define GPIO_LCKR_LCKK ((uint32_t)0x00010000U) +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000FU) -#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0U) -#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00U) -#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000U) -#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000U) -#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000U) -#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000U) -#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000U) +#define GPIO_AFRL_AFRL0_Pos (0U) +#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk +#define GPIO_AFRL_AFRL1_Pos (4U) +#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk +#define GPIO_AFRL_AFRL2_Pos (8U) +#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk +#define GPIO_AFRL_AFRL3_Pos (12U) +#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk +#define GPIO_AFRL_AFRL4_Pos (16U) +#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk +#define GPIO_AFRL_AFRL5_Pos (20U) +#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk +#define GPIO_AFRL_AFRL6_Pos (24U) +#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk +#define GPIO_AFRL_AFRL7_Pos (28U) +#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000FU) -#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0U) -#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00U) -#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000U) -#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000U) -#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000U) -#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000U) -#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000U) +#define GPIO_AFRH_AFRH0_Pos (0U) +#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk +#define GPIO_AFRH_AFRH1_Pos (4U) +#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk +#define GPIO_AFRH_AFRH2_Pos (8U) +#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk +#define GPIO_AFRH_AFRH3_Pos (12U) +#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk +#define GPIO_AFRH_AFRH4_Pos (16U) +#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk +#define GPIO_AFRH_AFRH5_Pos (20U) +#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk +#define GPIO_AFRH_AFRH6_Pos (24U) +#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk +#define GPIO_AFRH_AFRH7_Pos (28U) +#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk /****************** Bit definition for GPIO_BRR register *********************/ -#define GPIO_BRR_BR_0 ((uint32_t)0x00000001U) -#define GPIO_BRR_BR_1 ((uint32_t)0x00000002U) -#define GPIO_BRR_BR_2 ((uint32_t)0x00000004U) -#define GPIO_BRR_BR_3 ((uint32_t)0x00000008U) -#define GPIO_BRR_BR_4 ((uint32_t)0x00000010U) -#define GPIO_BRR_BR_5 ((uint32_t)0x00000020U) -#define GPIO_BRR_BR_6 ((uint32_t)0x00000040U) -#define GPIO_BRR_BR_7 ((uint32_t)0x00000080U) -#define GPIO_BRR_BR_8 ((uint32_t)0x00000100U) -#define GPIO_BRR_BR_9 ((uint32_t)0x00000200U) -#define GPIO_BRR_BR_10 ((uint32_t)0x00000400U) -#define GPIO_BRR_BR_11 ((uint32_t)0x00000800U) -#define GPIO_BRR_BR_12 ((uint32_t)0x00001000U) -#define GPIO_BRR_BR_13 ((uint32_t)0x00002000U) -#define GPIO_BRR_BR_14 ((uint32_t)0x00004000U) -#define GPIO_BRR_BR_15 ((uint32_t)0x00008000U) +#define GPIO_BRR_BR_0 (0x00000001U) +#define GPIO_BRR_BR_1 (0x00000002U) +#define GPIO_BRR_BR_2 (0x00000004U) +#define GPIO_BRR_BR_3 (0x00000008U) +#define GPIO_BRR_BR_4 (0x00000010U) +#define GPIO_BRR_BR_5 (0x00000020U) +#define GPIO_BRR_BR_6 (0x00000040U) +#define GPIO_BRR_BR_7 (0x00000080U) +#define GPIO_BRR_BR_8 (0x00000100U) +#define GPIO_BRR_BR_9 (0x00000200U) +#define GPIO_BRR_BR_10 (0x00000400U) +#define GPIO_BRR_BR_11 (0x00000800U) +#define GPIO_BRR_BR_12 (0x00001000U) +#define GPIO_BRR_BR_13 (0x00002000U) +#define GPIO_BRR_BR_14 (0x00004000U) +#define GPIO_BRR_BR_15 (0x00008000U) /******************************************************************************/ /* */ @@ -1615,110 +2594,276 @@ typedef struct /******************************************************************************/ /******************* Bit definition for I2C_CR1 register *******************/ -#define I2C_CR1_PE ((uint32_t)0x00000001U) /*!< Peripheral enable */ -#define I2C_CR1_TXIE ((uint32_t)0x00000002U) /*!< TX interrupt enable */ -#define I2C_CR1_RXIE ((uint32_t)0x00000004U) /*!< RX interrupt enable */ -#define I2C_CR1_ADDRIE ((uint32_t)0x00000008U) /*!< Address match interrupt enable */ -#define I2C_CR1_NACKIE ((uint32_t)0x00000010U) /*!< NACK received interrupt enable */ -#define I2C_CR1_STOPIE ((uint32_t)0x00000020U) /*!< STOP detection interrupt enable */ -#define I2C_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transfer complete interrupt enable */ -#define I2C_CR1_ERRIE ((uint32_t)0x00000080U) /*!< Errors interrupt enable */ -#define I2C_CR1_DNF ((uint32_t)0x00000F00U) /*!< Digital noise filter */ -#define I2C_CR1_ANFOFF ((uint32_t)0x00001000U) /*!< Analog noise filter OFF */ -#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000U) /*!< DMA transmission requests enable */ -#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000U) /*!< DMA reception requests enable */ -#define I2C_CR1_SBC ((uint32_t)0x00010000U) /*!< Slave byte control */ -#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000U) /*!< Clock stretching disable */ -#define I2C_CR1_WUPEN ((uint32_t)0x00040000U) /*!< Wakeup from STOP enable */ -#define I2C_CR1_GCEN ((uint32_t)0x00080000U) /*!< General call enable */ -#define I2C_CR1_SMBHEN ((uint32_t)0x00100000U) /*!< SMBus host address enable */ -#define I2C_CR1_SMBDEN ((uint32_t)0x00200000U) /*!< SMBus device default address enable */ -#define I2C_CR1_ALERTEN ((uint32_t)0x00400000U) /*!< SMBus alert enable */ -#define I2C_CR1_PECEN ((uint32_t)0x00800000U) /*!< PEC enable */ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ /****************** Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_SADD ((uint32_t)0x000003FFU) /*!< Slave address (master mode) */ -#define I2C_CR2_RD_WRN ((uint32_t)0x00000400U) /*!< Transfer direction (master mode) */ -#define I2C_CR2_ADD10 ((uint32_t)0x00000800U) /*!< 10-bit addressing mode (master mode) */ -#define I2C_CR2_HEAD10R ((uint32_t)0x00001000U) /*!< 10-bit address header only read direction (master mode) */ -#define I2C_CR2_START ((uint32_t)0x00002000U) /*!< START generation */ -#define I2C_CR2_STOP ((uint32_t)0x00004000U) /*!< STOP generation (master mode) */ -#define I2C_CR2_NACK ((uint32_t)0x00008000U) /*!< NACK generation (slave mode) */ -#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000U) /*!< Number of bytes */ -#define I2C_CR2_RELOAD ((uint32_t)0x01000000U) /*!< NBYTES reload mode */ -#define I2C_CR2_AUTOEND ((uint32_t)0x02000000U) /*!< Automatic end mode (master mode) */ -#define I2C_CR2_PECBYTE ((uint32_t)0x04000000U) /*!< Packet error checking byte */ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ /******************* Bit definition for I2C_OAR1 register ******************/ -#define I2C_OAR1_OA1 ((uint32_t)0x000003FFU) /*!< Interface own address 1 */ -#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400U) /*!< Own address 1 10-bit mode */ -#define I2C_OAR1_OA1EN ((uint32_t)0x00008000U) /*!< Own address 1 enable */ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ /******************* Bit definition for I2C_OAR2 register ******************/ -#define I2C_OAR2_OA2 ((uint32_t)0x000000FEU) /*!< Interface own address 2 */ -#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700U) /*!< Own address 2 masks */ -#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000U) /*!< No mask */ -#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100U) /*!< OA2[1] is masked, Only OA2[7:2] are compared */ -#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200U) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ -#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300U) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ -#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400U) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ -#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500U) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ -#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600U) /*!< OA2[6:1] is masked, Only OA2[7] are compared */ -#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700U) /*!< OA2[7:1] is masked, No comparison is done */ -#define I2C_OAR2_OA2EN ((uint32_t)0x00008000U) /*!< Own address 2 enable */ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ /******************* Bit definition for I2C_TIMINGR register *******************/ -#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FFU) /*!< SCL low period (master mode) */ -#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00U) /*!< SCL high period (master mode) */ -#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000U) /*!< Data hold time */ -#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000U) /*!< Data setup time */ -#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000U) /*!< Timings prescaler */ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ /******************* Bit definition for I2C_TIMEOUTR register *******************/ -#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFFU) /*!< Bus timeout A */ -#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000U) /*!< Idle clock timeout detection */ -#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000U) /*!< Clock timeout enable */ -#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000U) /*!< Bus timeout B*/ -#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000U) /*!< Extended clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ /****************** Bit definition for I2C_ISR register *********************/ -#define I2C_ISR_TXE ((uint32_t)0x00000001U) /*!< Transmit data register empty */ -#define I2C_ISR_TXIS ((uint32_t)0x00000002U) /*!< Transmit interrupt status */ -#define I2C_ISR_RXNE ((uint32_t)0x00000004U) /*!< Receive data register not empty */ -#define I2C_ISR_ADDR ((uint32_t)0x00000008U) /*!< Address matched (slave mode)*/ -#define I2C_ISR_NACKF ((uint32_t)0x00000010U) /*!< NACK received flag */ -#define I2C_ISR_STOPF ((uint32_t)0x00000020U) /*!< STOP detection flag */ -#define I2C_ISR_TC ((uint32_t)0x00000040U) /*!< Transfer complete (master mode) */ -#define I2C_ISR_TCR ((uint32_t)0x00000080U) /*!< Transfer complete reload */ -#define I2C_ISR_BERR ((uint32_t)0x00000100U) /*!< Bus error */ -#define I2C_ISR_ARLO ((uint32_t)0x00000200U) /*!< Arbitration lost */ -#define I2C_ISR_OVR ((uint32_t)0x00000400U) /*!< Overrun/Underrun */ -#define I2C_ISR_PECERR ((uint32_t)0x00000800U) /*!< PEC error in reception */ -#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000U) /*!< Timeout or Tlow detection flag */ -#define I2C_ISR_ALERT ((uint32_t)0x00002000U) /*!< SMBus alert */ -#define I2C_ISR_BUSY ((uint32_t)0x00008000U) /*!< Bus busy */ -#define I2C_ISR_DIR ((uint32_t)0x00010000U) /*!< Transfer direction (slave mode) */ -#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000U) /*!< Address match code (slave mode) */ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ /****************** Bit definition for I2C_ICR register *********************/ -#define I2C_ICR_ADDRCF ((uint32_t)0x00000008U) /*!< Address matched clear flag */ -#define I2C_ICR_NACKCF ((uint32_t)0x00000010U) /*!< NACK clear flag */ -#define I2C_ICR_STOPCF ((uint32_t)0x00000020U) /*!< STOP detection clear flag */ -#define I2C_ICR_BERRCF ((uint32_t)0x00000100U) /*!< Bus error clear flag */ -#define I2C_ICR_ARLOCF ((uint32_t)0x00000200U) /*!< Arbitration lost clear flag */ -#define I2C_ICR_OVRCF ((uint32_t)0x00000400U) /*!< Overrun/Underrun clear flag */ -#define I2C_ICR_PECCF ((uint32_t)0x00000800U) /*!< PAC error clear flag */ -#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000U) /*!< Timeout clear flag */ -#define I2C_ICR_ALERTCF ((uint32_t)0x00002000U) /*!< Alert clear flag */ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ /****************** Bit definition for I2C_PECR register *********************/ -#define I2C_PECR_PEC ((uint32_t)0x000000FFU) /*!< PEC register */ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ /****************** Bit definition for I2C_RXDR register *********************/ -#define I2C_RXDR_RXDATA ((uint32_t)0x000000FFU) /*!< 8-bit receive data */ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ /****************** Bit definition for I2C_TXDR register *********************/ -#define I2C_TXDR_TXDATA ((uint32_t)0x000000FFU) /*!< 8-bit transmit data */ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ /******************************************************************************/ /* */ @@ -1726,24 +2871,38 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_KR_KEY ((uint32_t)0x0000FFFFU) /*!< Key value (write only, read 0000h) */ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ /******************* Bit definition for IWDG_PR register ********************/ -#define IWDG_PR_PR ((uint32_t)0x00000007U) /*!< PR[2:0] (Prescaler divider) */ -#define IWDG_PR_PR_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ -#define IWDG_PR_PR_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ -#define IWDG_PR_PR_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define IWDG_PR_PR_Pos (0U) +#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ +#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */ +#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */ +#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */ /******************* Bit definition for IWDG_RLR register *******************/ -#define IWDG_RLR_RL ((uint32_t)0x00000FFFU) /*!< Watchdog counter reload value */ +#define IWDG_RLR_RL_Pos (0U) +#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ +#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ /******************* Bit definition for IWDG_SR register ********************/ -#define IWDG_SR_PVU ((uint32_t)0x00000001U) /*!< Watchdog prescaler value update */ -#define IWDG_SR_RVU ((uint32_t)0x00000002U) /*!< Watchdog counter reload value update */ -#define IWDG_SR_WVU ((uint32_t)0x00000004U) /*!< Watchdog counter window value update */ +#define IWDG_SR_PVU_Pos (0U) +#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ +#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ +#define IWDG_SR_RVU_Pos (1U) +#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ +#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ +#define IWDG_SR_WVU_Pos (2U) +#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ +#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ /******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_WINR_WIN ((uint32_t)0x00000FFFU) /*!< Watchdog counter window value */ +#define IWDG_WINR_WIN_Pos (0U) +#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ +#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ /******************************************************************************/ /* */ @@ -1751,81 +2910,161 @@ typedef struct /* */ /******************************************************************************/ /****************** Bit definition for LPTIM_ISR register *******************/ -#define LPTIM_ISR_CMPM ((uint32_t)0x00000001U) /*!< Compare match */ -#define LPTIM_ISR_ARRM ((uint32_t)0x00000002U) /*!< Autoreload match */ -#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004U) /*!< External trigger edge event */ -#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008U) /*!< Compare register update OK */ -#define LPTIM_ISR_ARROK ((uint32_t)0x00000010U) /*!< Autoreload register update OK */ -#define LPTIM_ISR_UP ((uint32_t)0x00000020U) /*!< Counter direction change down to up */ -#define LPTIM_ISR_DOWN ((uint32_t)0x00000040U) /*!< Counter direction change up to down */ +#define LPTIM_ISR_CMPM_Pos (0U) +#define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */ +#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */ +#define LPTIM_ISR_ARRM_Pos (1U) +#define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */ +#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */ +#define LPTIM_ISR_EXTTRIG_Pos (2U) +#define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */ +#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */ +#define LPTIM_ISR_CMPOK_Pos (3U) +#define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */ +#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */ +#define LPTIM_ISR_ARROK_Pos (4U) +#define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */ +#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */ +#define LPTIM_ISR_UP_Pos (5U) +#define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */ +#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */ +#define LPTIM_ISR_DOWN_Pos (6U) +#define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */ +#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */ /****************** Bit definition for LPTIM_ICR register *******************/ -#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001U) /*!< Compare match Clear Flag */ -#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002U) /*!< Autoreload match Clear Flag */ -#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004U) /*!< External trigger edge event Clear Flag */ -#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008U) /*!< Compare register update OK Clear Flag */ -#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010U) /*!< Autoreload register update OK Clear Flag */ -#define LPTIM_ICR_UPCF ((uint32_t)0x00000020U) /*!< Counter direction change down to up Clear Flag */ -#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040U) /*!< Counter direction change up to down Clear Flag */ +#define LPTIM_ICR_CMPMCF_Pos (0U) +#define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */ +#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */ +#define LPTIM_ICR_ARRMCF_Pos (1U) +#define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */ +#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */ +#define LPTIM_ICR_EXTTRIGCF_Pos (2U) +#define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */ +#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */ +#define LPTIM_ICR_CMPOKCF_Pos (3U) +#define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */ +#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */ +#define LPTIM_ICR_ARROKCF_Pos (4U) +#define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */ +#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */ +#define LPTIM_ICR_UPCF_Pos (5U) +#define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */ +#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */ +#define LPTIM_ICR_DOWNCF_Pos (6U) +#define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */ +#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */ /****************** Bit definition for LPTIM_IER register ********************/ -#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001U) /*!< Compare match Interrupt Enable */ -#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002U) /*!< Autoreload match Interrupt Enable */ -#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004U) /*!< External trigger edge event Interrupt Enable */ -#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008U) /*!< Compare register update OK Interrupt Enable */ -#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010U) /*!< Autoreload register update OK Interrupt Enable */ -#define LPTIM_IER_UPIE ((uint32_t)0x00000020U) /*!< Counter direction change down to up Interrupt Enable */ -#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040U) /*!< Counter direction change up to down Interrupt Enable */ +#define LPTIM_IER_CMPMIE_Pos (0U) +#define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */ +#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */ +#define LPTIM_IER_ARRMIE_Pos (1U) +#define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */ +#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */ +#define LPTIM_IER_EXTTRIGIE_Pos (2U) +#define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */ +#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */ +#define LPTIM_IER_CMPOKIE_Pos (3U) +#define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */ +#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */ +#define LPTIM_IER_ARROKIE_Pos (4U) +#define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */ +#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */ +#define LPTIM_IER_UPIE_Pos (5U) +#define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */ +#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */ +#define LPTIM_IER_DOWNIE_Pos (6U) +#define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */ +#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */ /****************** Bit definition for LPTIM_CFGR register *******************/ -#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001U) /*!< Clock selector */ +#define LPTIM_CFGR_CKSEL_Pos (0U) +#define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */ +#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */ -#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006U) /*!< CKPOL[1:0] bits (Clock polarity) */ -#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002U) /*!< Bit 0 */ -#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004U) /*!< Bit 1 */ +#define LPTIM_CFGR_CKPOL_Pos (1U) +#define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */ +#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */ +#define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */ +#define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */ -#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018U) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ -#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ +#define LPTIM_CFGR_CKFLT_Pos (3U) +#define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */ +#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ +#define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */ +#define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */ -#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0U) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ -#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ -#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ +#define LPTIM_CFGR_TRGFLT_Pos (6U) +#define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */ +#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ +#define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */ +#define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */ -#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00U) /*!< PRESC[2:0] bits (Clock prescaler) */ -#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200U) /*!< Bit 0 */ -#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400U) /*!< Bit 1 */ -#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800U) /*!< Bit 2 */ +#define LPTIM_CFGR_PRESC_Pos (9U) +#define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */ +#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */ +#define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */ +#define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */ +#define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */ -#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000U) /*!< TRIGSEL[2:0]] bits (Trigger selector) */ -#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000U) /*!< Bit 0 */ -#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000U) /*!< Bit 1 */ -#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000U) /*!< Bit 2 */ +#define LPTIM_CFGR_TRIGSEL_Pos (13U) +#define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */ +#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */ +#define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */ +#define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */ +#define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */ -#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000U) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ -#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000U) /*!< Bit 0 */ -#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000U) /*!< Bit 1 */ +#define LPTIM_CFGR_TRIGEN_Pos (17U) +#define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */ +#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ +#define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */ +#define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */ -#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000U) /*!< Timout enable */ -#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000U) /*!< Waveform shape */ -#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000U) /*!< Waveform shape polarity */ -#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000U) /*!< Reg update mode */ -#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000U) /*!< Counter mode enable */ -#define LPTIM_CFGR_ENC ((uint32_t)0x01000000U) /*!< Encoder mode enable */ +#define LPTIM_CFGR_TIMOUT_Pos (19U) +#define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */ +#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */ +#define LPTIM_CFGR_WAVE_Pos (20U) +#define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */ +#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */ +#define LPTIM_CFGR_WAVPOL_Pos (21U) +#define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */ +#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */ +#define LPTIM_CFGR_PRELOAD_Pos (22U) +#define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */ +#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */ +#define LPTIM_CFGR_COUNTMODE_Pos (23U) +#define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */ +#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */ +#define LPTIM_CFGR_ENC_Pos (24U) +#define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */ +#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */ /****************** Bit definition for LPTIM_CR register ********************/ -#define LPTIM_CR_ENABLE ((uint32_t)0x00000001U) /*!< LPTIMer enable */ -#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002U) /*!< Timer start in single mode */ -#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004U) /*!< Timer start in continuous mode */ +#define LPTIM_CR_ENABLE_Pos (0U) +#define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */ +#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */ +#define LPTIM_CR_SNGSTRT_Pos (1U) +#define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */ +#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */ +#define LPTIM_CR_CNTSTRT_Pos (2U) +#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */ +#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */ /****************** Bit definition for LPTIM_CMP register *******************/ -#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFFU) /*!< Compare register */ +#define LPTIM_CMP_CMP_Pos (0U) +#define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */ +#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */ /****************** Bit definition for LPTIM_ARR register *******************/ -#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!< Auto reload register */ +#define LPTIM_ARR_ARR_Pos (0U) +#define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */ +#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */ /****************** Bit definition for LPTIM_CNT register *******************/ -#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!< Counter register */ +#define LPTIM_CNT_CNT_Pos (0U) +#define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */ +#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */ /******************************************************************************/ /* */ @@ -1833,49 +3072,93 @@ typedef struct /* */ /******************************************************************************/ -/******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPSDSR ((uint32_t)0x00000001U) /*!< Low-power deepsleep/sleep/low power run */ -#define PWR_CR_PDDS ((uint32_t)0x00000002U) /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF ((uint32_t)0x00000004U) /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF ((uint32_t)0x00000008U) /*!< Clear Standby Flag */ -#define PWR_CR_PVDE ((uint32_t)0x00000010U) /*!< Power Voltage Detector Enable */ +#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */ -#define PWR_CR_PLS ((uint32_t)0x000000E0U) /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ -#define PWR_CR_PLS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ -#define PWR_CR_PLS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPSDSR_Pos (0U) +#define PWR_CR_LPSDSR_Msk (0x1U << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */ +#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */ +#define PWR_CR_PDDS_Pos (1U) +#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ +#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF_Pos (2U) +#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ +#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF_Pos (3U) +#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ +#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ +#define PWR_CR_PVDE_Pos (4U) +#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS_Pos (5U) +#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ +#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ +#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ +#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ /*!< PVD level configuration */ -#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000U) /*!< PVD level 0 */ -#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020U) /*!< PVD level 1 */ -#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040U) /*!< PVD level 2 */ -#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060U) /*!< PVD level 3 */ -#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080U) /*!< PVD level 4 */ -#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0U) /*!< PVD level 5 */ -#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0U) /*!< PVD level 6 */ -#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0U) /*!< PVD level 7 */ +#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ +#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */ +#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */ +#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */ +#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */ +#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */ +#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */ +#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */ -#define PWR_CR_DBP ((uint32_t)0x00000100U) /*!< Disable Backup Domain write protection */ -#define PWR_CR_ULP ((uint32_t)0x00000200U) /*!< Ultra Low Power mode */ -#define PWR_CR_FWU ((uint32_t)0x00000400U) /*!< Fast wakeup */ +#define PWR_CR_DBP_Pos (8U) +#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ +#define PWR_CR_ULP_Pos (9U) +#define PWR_CR_ULP_Msk (0x1U << PWR_CR_ULP_Pos) /*!< 0x00000200 */ +#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */ +#define PWR_CR_FWU_Pos (10U) +#define PWR_CR_FWU_Msk (0x1U << PWR_CR_FWU_Pos) /*!< 0x00000400 */ +#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */ -#define PWR_CR_VOS ((uint32_t)0x00001800U) /*!< VOS[1:0] bits (Voltage scaling range selection) */ -#define PWR_CR_VOS_0 ((uint32_t)0x00000800U) /*!< Bit 0 */ -#define PWR_CR_VOS_1 ((uint32_t)0x00001000U) /*!< Bit 1 */ -#define PWR_CR_DSEEKOFF ((uint32_t)0x00002000U) /*!< Deep Sleep mode with EEPROM kept Off */ -#define PWR_CR_LPRUN ((uint32_t)0x00004000U) /*!< Low power run mode */ +#define PWR_CR_VOS_Pos (11U) +#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x00001800 */ +#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */ +#define PWR_CR_VOS_0 (0x1U << PWR_CR_VOS_Pos) /*!< 0x00000800 */ +#define PWR_CR_VOS_1 (0x2U << PWR_CR_VOS_Pos) /*!< 0x00001000 */ +#define PWR_CR_DSEEKOFF_Pos (13U) +#define PWR_CR_DSEEKOFF_Msk (0x1U << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */ +#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */ +#define PWR_CR_LPRUN_Pos (14U) +#define PWR_CR_LPRUN_Msk (0x1U << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */ +#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */ /******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint32_t)0x00000001U) /*!< Wakeup Flag */ -#define PWR_CSR_SBF ((uint32_t)0x00000002U) /*!< Standby Flag */ -#define PWR_CSR_PVDO ((uint32_t)0x00000004U) /*!< PVD Output */ -#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008U) /*!< Internal voltage reference (VREFINT) ready flag */ -#define PWR_CSR_VOSF ((uint32_t)0x00000010U) /*!< Voltage Scaling select flag */ -#define PWR_CSR_REGLPF ((uint32_t)0x00000020U) /*!< Regulator LP flag */ +#define PWR_CSR_WUF_Pos (0U) +#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ +#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ +#define PWR_CSR_SBF_Pos (1U) +#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ +#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ +#define PWR_CSR_PVDO_Pos (2U) +#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ +#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ +#define PWR_CSR_VREFINTRDYF_Pos (3U) +#define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */ +#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */ +#define PWR_CSR_VOSF_Pos (4U) +#define PWR_CSR_VOSF_Msk (0x1U << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */ +#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */ +#define PWR_CSR_REGLPF_Pos (5U) +#define PWR_CSR_REGLPF_Msk (0x1U << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */ +#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */ -#define PWR_CSR_EWUP1 ((uint32_t)0x00000100U) /*!< Enable WKUP pin 1 */ -#define PWR_CSR_EWUP2 ((uint32_t)0x00000200U) /*!< Enable WKUP pin 2 */ -#define PWR_CSR_EWUP3 ((uint32_t)0x00000400U) /*!< Enable WKUP pin 3 */ +#define PWR_CSR_EWUP1_Pos (8U) +#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ +#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ +#define PWR_CSR_EWUP2_Pos (9U) +#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ +#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ +#define PWR_CSR_EWUP3_Pos (10U) +#define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */ +#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */ /******************************************************************************/ /* */ @@ -1883,169 +3166,265 @@ typedef struct /* */ /******************************************************************************/ +#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */ + /******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION ((uint32_t)0x00000001U) /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIKERON ((uint32_t)0x00000002U) /*!< Internal High Speed clock enable for some IPs Kernel */ -#define RCC_CR_HSIRDY ((uint32_t)0x00000004U) /*!< Internal High Speed clock ready flag */ -#define RCC_CR_HSIDIVEN ((uint32_t)0x00000008U) /*!< Internal High Speed clock divider enable */ -#define RCC_CR_HSIDIVF ((uint32_t)0x00000010U) /*!< Internal High Speed clock divider flag */ -#define RCC_CR_HSIOUTEN ((uint32_t)0x00000020U) /*!< Internal High Speed clock out enable */ -#define RCC_CR_MSION ((uint32_t)0x00000100U) /*!< Internal Multi Speed clock enable */ -#define RCC_CR_MSIRDY ((uint32_t)0x00000200U) /*!< Internal Multi Speed clock ready flag */ -#define RCC_CR_HSEON ((uint32_t)0x00010000U) /*!< External High Speed clock enable */ -#define RCC_CR_HSERDY ((uint32_t)0x00020000U) /*!< External High Speed clock ready flag */ -#define RCC_CR_HSEBYP ((uint32_t)0x00040000U) /*!< External High Speed clock Bypass */ -#define RCC_CR_CSSHSEON ((uint32_t)0x00080000U) /*!< HSE Clock Security System enable */ -#define RCC_CR_RTCPRE ((uint32_t)0x00300000U) /*!< RTC prescaler [1:0] bits */ -#define RCC_CR_RTCPRE_0 ((uint32_t)0x00100000U) /*!< RTC prescaler Bit 0 */ -#define RCC_CR_RTCPRE_1 ((uint32_t)0x00200000U) /*!< RTC prescaler Bit 1 */ -#define RCC_CR_PLLON ((uint32_t)0x01000000U) /*!< PLL enable */ -#define RCC_CR_PLLRDY ((uint32_t)0x02000000U) /*!< PLL clock ready flag */ +#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIKERON_Pos (1U) +#define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */ +#define RCC_CR_HSIRDY_Pos (2U) +#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSIDIVEN_Pos (3U) +#define RCC_CR_HSIDIVEN_Msk (0x1U << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */ +#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */ +#define RCC_CR_HSIDIVF_Pos (4U) +#define RCC_CR_HSIDIVF_Msk (0x1U << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */ +#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */ +#define RCC_CR_HSIOUTEN_Pos (5U) +#define RCC_CR_HSIOUTEN_Msk (0x1U << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */ +#define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */ +#define RCC_CR_MSION_Pos (8U) +#define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000100 */ +#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */ +#define RCC_CR_MSIRDY_Pos (9U) +#define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */ +#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSHSEON_Pos (19U) +#define RCC_CR_CSSHSEON_Msk (0x1U << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */ +#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */ +#define RCC_CR_RTCPRE_Pos (20U) +#define RCC_CR_RTCPRE_Msk (0x3U << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */ +#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */ +#define RCC_CR_RTCPRE_0 (0x1U << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */ +#define RCC_CR_RTCPRE_1 (0x2U << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */ +#define RCC_CR_PLLON_Pos (24U) +#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ +#define RCC_CR_PLLRDY_Pos (25U) +#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ /* Reference defines */ #define RCC_CR_CSSON RCC_CR_CSSHSEON /******************** Bit definition for RCC_ICSCR register *****************/ -#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FFU) /*!< Internal High Speed clock Calibration */ -#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00U) /*!< Internal High Speed clock trimming */ +#define RCC_ICSCR_HSICAL_Pos (0U) +#define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */ +#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ +#define RCC_ICSCR_HSITRIM_Pos (8U) +#define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ -#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000U) /*!< Internal Multi Speed clock Range */ -#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000U) /*!< Internal Multi Speed clock Range 65.536 KHz */ -#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000U) /*!< Internal Multi Speed clock Range 131.072 KHz */ -#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000U) /*!< Internal Multi Speed clock Range 262.144 KHz */ -#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000U) /*!< Internal Multi Speed clock Range 524.288 KHz */ -#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000U) /*!< Internal Multi Speed clock Range 1.048 MHz */ -#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000U) /*!< Internal Multi Speed clock Range 2.097 MHz */ -#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000U) /*!< Internal Multi Speed clock Range 4.194 MHz */ -#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000U) /*!< Internal Multi Speed clock Calibration */ -#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000U) /*!< Internal Multi Speed clock trimming */ +#define RCC_ICSCR_MSIRANGE_Pos (13U) +#define RCC_ICSCR_MSIRANGE_Msk (0x7U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */ +#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */ +#define RCC_ICSCR_MSIRANGE_0 (0x0U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */ +#define RCC_ICSCR_MSIRANGE_1 (0x1U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */ +#define RCC_ICSCR_MSIRANGE_2 (0x2U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */ +#define RCC_ICSCR_MSIRANGE_3 (0x3U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */ +#define RCC_ICSCR_MSIRANGE_4 (0x4U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */ +#define RCC_ICSCR_MSIRANGE_5 (0x5U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */ +#define RCC_ICSCR_MSIRANGE_6 (0x6U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */ +#define RCC_ICSCR_MSICAL_Pos (16U) +#define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */ +#define RCC_ICSCR_MSITRIM_Pos (24U) +#define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */ +#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */ /******************* Bit definition for RCC_CFGR register *******************/ /*!< SW configuration */ -#define RCC_CFGR_SW ((uint32_t)0x00000003U) /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ -#define RCC_CFGR_SW_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ -#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000U) /*!< MSI selected as system clock */ -#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001U) /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002U) /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003U) /*!< PLL selected as system clock */ +#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */ +#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */ /*!< SWS configuration */ -#define RCC_CFGR_SWS ((uint32_t)0x0000000CU) /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004U) /*!< Bit 0 */ -#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008U) /*!< Bit 1 */ +#define RCC_CFGR_SWS_Pos (2U) +#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ +#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ -#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004U) /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008U) /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000CU) /*!< PLL used as system clock */ +#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */ /*!< HPRE configuration */ -#define RCC_CFGR_HPRE ((uint32_t)0x000000F0U) /*!< HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010U) /*!< Bit 0 */ -#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020U) /*!< Bit 1 */ -#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040U) /*!< Bit 2 */ -#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080U) /*!< Bit 3 */ +#define RCC_CFGR_HPRE_Pos (4U) +#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ +#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ +#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ -#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000U) /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080U) /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090U) /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0U) /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0U) /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0U) /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0U) /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0U) /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0U) /*!< SYSCLK divided by 512 */ +#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ /*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700U) /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */ -#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */ -#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */ +#define RCC_CFGR_PPRE1_Pos (8U) +#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ +#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ +#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ +#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ -#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400U) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500U) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600U) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700U) /*!< HCLK divided by 16 */ +#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */ /*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800U) /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800U) /*!< Bit 0 */ -#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000U) /*!< Bit 1 */ -#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000U) /*!< Bit 2 */ +#define RCC_CFGR_PPRE2_Pos (11U) +#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ +#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ +#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ +#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ -#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000U) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800U) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000U) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800U) /*!< HCLK divided by 16 */ +#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */ -#define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000U) /*!< Wake Up from Stop Clock selection */ +#define RCC_CFGR_STOPWUCK_Pos (15U) +#define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */ +#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */ /*!< PLL entry clock source*/ -#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000U) /*!< PLL entry clock source */ +#define RCC_CFGR_PLLSRC_Pos (16U) +#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ +#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ -#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000U) /*!< HSI as PLL entry clock source */ -#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000U) /*!< HSE as PLL entry clock source */ +#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */ +#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */ /*!< PLLMUL configuration */ -#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000U) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ -#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ -#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ -#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000U) /*!< Bit 3 */ +#define RCC_CFGR_PLLMUL_Pos (18U) +#define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ -#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000U) /*!< PLL input clock * 3 */ -#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000U) /*!< PLL input clock * 4 */ -#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000U) /*!< PLL input clock * 6 */ -#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000U) /*!< PLL input clock * 8 */ -#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000U) /*!< PLL input clock * 12 */ -#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000U) /*!< PLL input clock * 16 */ -#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000U) /*!< PLL input clock * 24 */ -#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000U) /*!< PLL input clock * 32 */ -#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000U) /*!< PLL input clock * 48 */ +#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */ +#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */ +#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */ +#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */ +#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */ +#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */ +#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */ +#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */ +#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */ /*!< PLLDIV configuration */ -#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000U) /*!< PLLDIV[1:0] bits (PLL Output Division) */ -#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000U) /*!< Bit0 */ -#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000U) /*!< Bit1 */ +#define RCC_CFGR_PLLDIV_Pos (22U) +#define RCC_CFGR_PLLDIV_Msk (0x3U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */ +#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */ +#define RCC_CFGR_PLLDIV_0 (0x1U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_PLLDIV_1 (0x2U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */ -#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000U) /*!< PLL clock output = CKVCO / 2 */ -#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000U) /*!< PLL clock output = CKVCO / 3 */ -#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000U) /*!< PLL clock output = CKVCO / 4 */ +#define RCC_CFGR_PLLDIV2_Pos (22U) +#define RCC_CFGR_PLLDIV2_Msk (0x1U << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */ +#define RCC_CFGR_PLLDIV3_Pos (23U) +#define RCC_CFGR_PLLDIV3_Msk (0x1U << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */ +#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */ +#define RCC_CFGR_PLLDIV4_Pos (22U) +#define RCC_CFGR_PLLDIV4_Msk (0x3U << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */ +#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */ /*!< MCO configuration */ -#define RCC_CFGR_MCOSEL ((uint32_t)0x0F000000U) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ -#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ -#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ -#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000U) /*!< Bit 2 */ -#define RCC_CFGR_MCOSEL_3 ((uint32_t)0x08000000U) /*!< Bit 3 */ +#define RCC_CFGR_MCOSEL_Pos (24U) +#define RCC_CFGR_MCOSEL_Msk (0xFU << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */ +#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */ +#define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ +#define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */ -#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */ -#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000U) /*!< System clock selected as MCO source */ -#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000U) /*!< Internal 16 MHz RC oscillator clock selected */ -#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000U) /*!< Internal Medium Speed RC oscillator clock selected */ -#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000U) /*!< External 1-25 MHz oscillator clock selected */ -#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000U) /*!< PLL clock divided */ -#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000U) /*!< LSI selected */ -#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000U) /*!< LSE selected */ +#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */ +#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U) +#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */ +#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */ +#define RCC_CFGR_MCOSEL_HSI_Pos (25U) +#define RCC_CFGR_MCOSEL_HSI_Msk (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */ +#define RCC_CFGR_MCOSEL_MSI_Pos (24U) +#define RCC_CFGR_MCOSEL_MSI_Msk (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */ +#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */ +#define RCC_CFGR_MCOSEL_HSE_Pos (26U) +#define RCC_CFGR_MCOSEL_HSE_Msk (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */ +#define RCC_CFGR_MCOSEL_PLL_Pos (24U) +#define RCC_CFGR_MCOSEL_PLL_Msk (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */ +#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */ +#define RCC_CFGR_MCOSEL_LSI_Pos (25U) +#define RCC_CFGR_MCOSEL_LSI_Msk (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */ +#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */ +#define RCC_CFGR_MCOSEL_LSE_Pos (24U) +#define RCC_CFGR_MCOSEL_LSE_Msk (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */ +#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */ -#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000U) /*!< MCO prescaler */ -#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */ -#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */ -#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000U) /*!< MCO is divided by 8 */ +#define RCC_CFGR_MCOPRE_Pos (28U) +#define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ +#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */ +#define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ +#define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ -#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000U) /*!< MCO is divided by 1 */ -#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */ -#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */ -#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000U) /*!< MCO is divided by 8 */ -#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000U) /*!< MCO is divided by 16 */ +#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ +#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ +#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ +#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ +#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ /* Legacy defines */ +#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK +#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK +#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI +#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI +#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE +#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL +#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI +#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE +#ifdef RCC_CFGR_MCOSEL_HSI48 +#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48 +#endif + #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */ #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */ #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */ @@ -2054,49 +3433,103 @@ typedef struct #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */ /*!<****************** Bit definition for RCC_CIER register ********************/ -#define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Enable */ -#define RCC_CIER_LSERDYIE ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Enable */ -#define RCC_CIER_HSIRDYIE ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Enable */ -#define RCC_CIER_HSERDYIE ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Enable */ -#define RCC_CIER_PLLRDYIE ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Enable */ -#define RCC_CIER_MSIRDYIE ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Enable */ -#define RCC_CIER_CSSLSE ((uint32_t)0x00000080U) /*!< LSE CSS Interrupt Enable */ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ +#define RCC_CIER_HSIRDYIE_Pos (2U) +#define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ +#define RCC_CIER_HSERDYIE_Pos (3U) +#define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ +#define RCC_CIER_PLLRDYIE_Pos (4U) +#define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ +#define RCC_CIER_MSIRDYIE_Pos (5U) +#define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */ +#define RCC_CIER_CSSLSE_Pos (7U) +#define RCC_CIER_CSSLSE_Msk (0x1U << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */ /* Reference defines */ #define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE /*!<****************** Bit definition for RCC_CIFR register ********************/ -#define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt flag */ -#define RCC_CIFR_LSERDYF ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt flag */ -#define RCC_CIFR_HSIRDYF ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt flag */ -#define RCC_CIFR_HSERDYF ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt flag */ -#define RCC_CIFR_PLLRDYF ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt flag */ -#define RCC_CIFR_MSIRDYF ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt flag */ -#define RCC_CIFR_CSSLSEF ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt flag */ -#define RCC_CIFR_CSSHSEF ((uint32_t)0x00000100U) /*!< HSE Clock Security System Interrupt flag */ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ +#define RCC_CIFR_HSIRDYF_Pos (2U) +#define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ +#define RCC_CIFR_HSERDYF_Pos (3U) +#define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ +#define RCC_CIFR_PLLRDYF_Pos (4U) +#define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ +#define RCC_CIFR_MSIRDYF_Pos (5U) +#define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */ +#define RCC_CIFR_CSSLSEF_Pos (7U) +#define RCC_CIFR_CSSLSEF_Msk (0x1U << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */ +#define RCC_CIFR_CSSHSEF_Pos (8U) +#define RCC_CIFR_CSSHSEF_Msk (0x1U << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */ /* Reference defines */ #define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF #define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF /*!<****************** Bit definition for RCC_CICR register ********************/ -#define RCC_CICR_LSIRDYC ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Clear */ -#define RCC_CICR_LSERDYC ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Clear */ -#define RCC_CICR_HSIRDYC ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Clear */ -#define RCC_CICR_HSERDYC ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Clear */ -#define RCC_CICR_PLLRDYC ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Clear */ -#define RCC_CICR_MSIRDYC ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Clear */ -#define RCC_CICR_CSSLSEC ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt Clear */ -#define RCC_CICR_CSSHSEC ((uint32_t)0x00000100U) /*!< HSE Clock Security System Interrupt Clear */ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ +#define RCC_CICR_HSIRDYC_Pos (2U) +#define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ +#define RCC_CICR_HSERDYC_Pos (3U) +#define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ +#define RCC_CICR_PLLRDYC_Pos (4U) +#define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ +#define RCC_CICR_MSIRDYC_Pos (5U) +#define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */ +#define RCC_CICR_CSSLSEC_Pos (7U) +#define RCC_CICR_CSSLSEC_Msk (0x1U << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */ +#define RCC_CICR_CSSHSEC_Pos (8U) +#define RCC_CICR_CSSHSEC_Msk (0x1U << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */ /* Reference defines */ #define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC #define RCC_CICR_CSSC RCC_CICR_CSSHSEC /***************** Bit definition for RCC_IOPRSTR register ******************/ -#define RCC_IOPRSTR_IOPARST ((uint32_t)0x00000001U) /*!< GPIO port A reset */ -#define RCC_IOPRSTR_IOPBRST ((uint32_t)0x00000002U) /*!< GPIO port B reset */ -#define RCC_IOPRSTR_IOPCRST ((uint32_t)0x00000004U) /*!< GPIO port C reset */ -#define RCC_IOPRSTR_IOPHRST ((uint32_t)0x00000080U) /*!< GPIO port H reset */ +#define RCC_IOPRSTR_IOPARST_Pos (0U) +#define RCC_IOPRSTR_IOPARST_Msk (0x1U << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */ +#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */ +#define RCC_IOPRSTR_IOPBRST_Pos (1U) +#define RCC_IOPRSTR_IOPBRST_Msk (0x1U << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */ +#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */ +#define RCC_IOPRSTR_IOPCRST_Pos (2U) +#define RCC_IOPRSTR_IOPCRST_Msk (0x1U << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */ +#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */ +#define RCC_IOPRSTR_IOPHRST_Pos (7U) +#define RCC_IOPRSTR_IOPHRST_Msk (0x1U << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */ +#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */ /* Reference defines */ #define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */ @@ -2106,39 +3539,79 @@ typedef struct /****************** Bit definition for RCC_AHBRST register ******************/ -#define RCC_AHBRSTR_DMARST ((uint32_t)0x00000001U) /*!< DMA1 reset */ -#define RCC_AHBRSTR_MIFRST ((uint32_t)0x00000100U) /*!< Memory interface reset reset */ -#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000U) /*!< CRC reset */ +#define RCC_AHBRSTR_DMARST_Pos (0U) +#define RCC_AHBRSTR_DMARST_Msk (0x1U << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */ +#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */ +#define RCC_AHBRSTR_MIFRST_Pos (8U) +#define RCC_AHBRSTR_MIFRST_Msk (0x1U << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */ +#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset reset */ +#define RCC_AHBRSTR_CRCRST_Pos (12U) +#define RCC_AHBRSTR_CRCRST_Msk (0x1U << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */ /* Reference defines */ #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */ /***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001U) /*!< SYSCFG clock reset */ -#define RCC_APB2RSTR_TIM21RST ((uint32_t)0x00000004U) /*!< TIM21 clock reset */ -#define RCC_APB2RSTR_TIM22RST ((uint32_t)0x00000020U) /*!< TIM22 clock reset */ -#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200U) /*!< ADC1 clock reset */ -#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000U) /*!< SPI1 clock reset */ -#define RCC_APB2RSTR_DBGRST ((uint32_t)0x00400000U) /*!< DBGMCU clock reset */ +#define RCC_APB2RSTR_SYSCFGRST_Pos (0U) +#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ +#define RCC_APB2RSTR_TIM21RST_Pos (2U) +#define RCC_APB2RSTR_TIM21RST_Msk (0x1U << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 clock reset */ +#define RCC_APB2RSTR_TIM22RST_Pos (5U) +#define RCC_APB2RSTR_TIM22RST_Msk (0x1U << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 clock reset */ +#define RCC_APB2RSTR_ADCRST_Pos (9U) +#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 clock reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ +#define RCC_APB2RSTR_DBGRST_Pos (22U) +#define RCC_APB2RSTR_DBGRST_Msk (0x1U << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU clock reset */ /* Reference defines */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 clock reset */ #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU clock reset */ /***************** Bit definition for RCC_APB1RSTR register *****************/ -#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001U) /*!< Timer 2 clock reset */ -#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800U) /*!< Window Watchdog clock reset */ -#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000U) /*!< USART 2 clock reset */ -#define RCC_APB1RSTR_LPUART1RST ((uint32_t)0x00040000U) /*!< LPUART1 clock reset */ -#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000U) /*!< I2C 1 clock reset */ -#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000U) /*!< PWR clock reset */ -#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x80000000U) /*!< LPTIM1 clock reset */ +#define RCC_APB1RSTR_TIM2RST_Pos (0U) +#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ +#define RCC_APB1RSTR_WWDGRST_Pos (11U) +#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ +#define RCC_APB1RSTR_USART2RST_Pos (17U) +#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ +#define RCC_APB1RSTR_LPUART1RST_Pos (18U) +#define RCC_APB1RSTR_LPUART1RST_Msk (0x1U << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 clock reset */ +#define RCC_APB1RSTR_I2C1RST_Pos (21U) +#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ +#define RCC_APB1RSTR_PWRRST_Pos (28U) +#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ +#define RCC_APB1RSTR_LPTIM1RST_Pos (31U) +#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 clock reset */ /***************** Bit definition for RCC_IOPENR register ******************/ -#define RCC_IOPENR_IOPAEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enable */ -#define RCC_IOPENR_IOPBEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enable */ -#define RCC_IOPENR_IOPCEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enable */ -#define RCC_IOPENR_IOPHEN ((uint32_t)0x00000080U) /*!< GPIO port H clock enable */ +#define RCC_IOPENR_IOPAEN_Pos (0U) +#define RCC_IOPENR_IOPAEN_Msk (0x1U << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */ +#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */ +#define RCC_IOPENR_IOPBEN_Pos (1U) +#define RCC_IOPENR_IOPBEN_Msk (0x1U << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */ +#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */ +#define RCC_IOPENR_IOPCEN_Pos (2U) +#define RCC_IOPENR_IOPCEN_Msk (0x1U << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */ +#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */ +#define RCC_IOPENR_IOPHEN_Pos (7U) +#define RCC_IOPENR_IOPHEN_Msk (0x1U << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */ +#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */ /* Reference defines */ #define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */ @@ -2147,21 +3620,41 @@ typedef struct #define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */ /***************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001U) /*!< DMA1 clock enable */ -#define RCC_AHBENR_MIFEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable bit */ -#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000U) /*!< CRC clock enable */ +#define RCC_AHBENR_DMAEN_Pos (0U) +#define RCC_AHBENR_DMAEN_Msk (0x1U << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */ +#define RCC_AHBENR_MIFEN_Pos (8U) +#define RCC_AHBENR_MIFEN_Msk (0x1U << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */ +#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */ +#define RCC_AHBENR_CRCEN_Pos (12U) +#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ /* Reference defines */ #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ /***************** Bit definition for RCC_APB2ENR register ******************/ -#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enable */ -#define RCC_APB2ENR_TIM21EN ((uint32_t)0x00000004U) /*!< TIM21 clock enable */ -#define RCC_APB2ENR_TIM22EN ((uint32_t)0x00000020U) /*!< TIM22 clock enable */ -#define RCC_APB2ENR_FWEN ((uint32_t)0x00000080U) /*!< MiFare Firewall clock enable */ -#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200U) /*!< ADC1 clock enable */ -#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000U) /*!< SPI1 clock enable */ -#define RCC_APB2ENR_DBGEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enable */ +#define RCC_APB2ENR_SYSCFGEN_Pos (0U) +#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */ +#define RCC_APB2ENR_TIM21EN_Pos (2U) +#define RCC_APB2ENR_TIM21EN_Msk (0x1U << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */ +#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */ +#define RCC_APB2ENR_TIM22EN_Pos (5U) +#define RCC_APB2ENR_TIM22EN_Msk (0x1U << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */ +#define RCC_APB2ENR_FWEN_Pos (7U) +#define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */ +#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */ +#define RCC_APB2ENR_ADCEN_Pos (9U) +#define RCC_APB2ENR_ADCEN_Msk (0x1U << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */ +#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ +#define RCC_APB2ENR_DBGEN_Pos (22U) +#define RCC_APB2ENR_DBGEN_Msk (0x1U << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */ /* Reference defines */ @@ -2170,19 +3663,41 @@ typedef struct #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */ /***************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001U) /*!< Timer 2 clock enable */ -#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enable */ -#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000U) /*!< USART2 clock enable */ -#define RCC_APB1ENR_LPUART1EN ((uint32_t)0x00040000U) /*!< LPUART1 clock enable */ -#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000U) /*!< I2C1 clock enable */ -#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000U) /*!< PWR clock enable */ -#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enable */ +#define RCC_APB1ENR_TIM2EN_Pos (0U) +#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */ +#define RCC_APB1ENR_WWDGEN_Pos (11U) +#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_USART2EN_Pos (17U) +#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */ +#define RCC_APB1ENR_LPUART1EN_Pos (18U) +#define RCC_APB1ENR_LPUART1EN_Msk (0x1U << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */ +#define RCC_APB1ENR_I2C1EN_Pos (21U) +#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */ +#define RCC_APB1ENR_PWREN_Pos (28U) +#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ +#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */ +#define RCC_APB1ENR_LPTIM1EN_Pos (31U) +#define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */ /****************** Bit definition for RCC_IOPSMENR register ****************/ -#define RCC_IOPSMENR_IOPASMEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enabled in sleep mode */ -#define RCC_IOPSMENR_IOPBSMEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enabled in sleep mode */ -#define RCC_IOPSMENR_IOPCSMEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enabled in sleep mode */ -#define RCC_IOPSMENR_IOPHSMEN ((uint32_t)0x00000080U) /*!< GPIO port H clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPASMEN_Pos (0U) +#define RCC_IOPSMENR_IOPASMEN_Msk (0x1U << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */ +#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPBSMEN_Pos (1U) +#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1U << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */ +#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPCSMEN_Pos (2U) +#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1U << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */ +#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPHSMEN_Pos (7U) +#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1U << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */ +#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */ /* Reference defines */ #define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */ @@ -2191,93 +3706,181 @@ typedef struct #define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */ /***************** Bit definition for RCC_AHBSMENR register ******************/ -#define RCC_AHBSMENR_DMASMEN ((uint32_t)0x00000001U) /*!< DMA1 clock enabled in sleep mode */ -#define RCC_AHBSMENR_MIFSMEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable during sleep mode */ -#define RCC_AHBSMENR_SRAMSMEN ((uint32_t)0x00000200U) /*!< SRAM clock enabled in sleep mode */ -#define RCC_AHBSMENR_CRCSMEN ((uint32_t)0x00001000U) /*!< CRC clock enabled in sleep mode */ +#define RCC_AHBSMENR_DMASMEN_Pos (0U) +#define RCC_AHBSMENR_DMASMEN_Msk (0x1U << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */ +#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */ +#define RCC_AHBSMENR_MIFSMEN_Pos (8U) +#define RCC_AHBSMENR_MIFSMEN_Msk (0x1U << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */ +#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */ +#define RCC_AHBSMENR_SRAMSMEN_Pos (9U) +#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1U << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */ +#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */ +#define RCC_AHBSMENR_CRCSMEN_Pos (12U) +#define RCC_AHBSMENR_CRCSMEN_Msk (0x1U << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */ +#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */ /* Reference defines */ #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */ /***************** Bit definition for RCC_APB2SMENR register ******************/ -#define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enabled in sleep mode */ -#define RCC_APB2SMENR_TIM21SMEN ((uint32_t)0x00000004U) /*!< TIM21 clock enabled in sleep mode */ -#define RCC_APB2SMENR_TIM22SMEN ((uint32_t)0x00000020U) /*!< TIM22 clock enabled in sleep mode */ -#define RCC_APB2SMENR_ADCSMEN ((uint32_t)0x00000200U) /*!< ADC1 clock enabled in sleep mode */ -#define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000U) /*!< SPI1 clock enabled in sleep mode */ -#define RCC_APB2SMENR_DBGSMEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enabled in sleep mode */ +#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U) +#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */ +#define RCC_APB2SMENR_TIM21SMEN_Pos (2U) +#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1U << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */ +#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */ +#define RCC_APB2SMENR_TIM22SMEN_Pos (5U) +#define RCC_APB2SMENR_TIM22SMEN_Msk (0x1U << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */ +#define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */ +#define RCC_APB2SMENR_ADCSMEN_Pos (9U) +#define RCC_APB2SMENR_ADCSMEN_Msk (0x1U << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */ +#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */ +#define RCC_APB2SMENR_SPI1SMEN_Pos (12U) +#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */ +#define RCC_APB2SMENR_DBGSMEN_Pos (22U) +#define RCC_APB2SMENR_DBGSMEN_Msk (0x1U << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */ /* Reference defines */ #define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */ #define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */ /***************** Bit definition for RCC_APB1SMENR register ******************/ -#define RCC_APB1SMENR_TIM2SMEN ((uint32_t)0x00000001U) /*!< Timer 2 clock enabled in sleep mode */ -#define RCC_APB1SMENR_WWDGSMEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enabled in sleep mode */ -#define RCC_APB1SMENR_USART2SMEN ((uint32_t)0x00020000U) /*!< USART2 clock enabled in sleep mode */ -#define RCC_APB1SMENR_LPUART1SMEN ((uint32_t)0x00040000U) /*!< LPUART1 clock enabled in sleep mode */ -#define RCC_APB1SMENR_I2C1SMEN ((uint32_t)0x00200000U) /*!< I2C1 clock enabled in sleep mode */ -#define RCC_APB1SMENR_PWRSMEN ((uint32_t)0x10000000U) /*!< PWR clock enabled in sleep mode */ -#define RCC_APB1SMENR_LPTIM1SMEN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enabled in sleep mode */ +#define RCC_APB1SMENR_TIM2SMEN_Pos (0U) +#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */ +#define RCC_APB1SMENR_WWDGSMEN_Pos (11U) +#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */ +#define RCC_APB1SMENR_USART2SMEN_Pos (17U) +#define RCC_APB1SMENR_USART2SMEN_Msk (0x1U << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */ +#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U) +#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */ +#define RCC_APB1SMENR_I2C1SMEN_Pos (21U) +#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */ +#define RCC_APB1SMENR_PWRSMEN_Pos (28U) +#define RCC_APB1SMENR_PWRSMEN_Msk (0x1U << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */ +#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */ +#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U) +#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */ +#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */ /*!< USART2 Clock source selection */ -#define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000CU) /*!< USART2SEL[1:0] bits */ -#define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004U) /*!< Bit 0 */ -#define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008U) /*!< Bit 1 */ +#define RCC_CCIPR_USART2SEL_Pos (2U) +#define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */ +#define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */ /*!< LPUART1 Clock source selection */ -#define RCC_CCIPR_LPUART1SEL ((uint32_t)0x0000C00) /*!< LPUART1SEL[1:0] bits */ -#define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x0000400) /*!< Bit 0 */ -#define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x0000800) /*!< Bit 1 */ +#define RCC_CCIPR_LPUART1SEL_Pos (10U) +#define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */ +#define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */ +#define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */ /*!< I2C1 Clock source selection */ -#define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000U) /*!< I2C1SEL [1:0] bits */ -#define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ -#define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define RCC_CCIPR_I2C1SEL_Pos (12U) +#define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */ +#define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */ /*!< LPTIM1 Clock source selection */ -#define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000U) /*!< LPTIM1SEL [1:0] bits */ -#define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ -#define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ +#define RCC_CCIPR_LPTIM1SEL_Pos (18U) +#define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */ +#define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */ /******************* Bit definition for RCC_CSR register *******************/ -#define RCC_CSR_LSION ((uint32_t)0x00000001U) /*!< Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY ((uint32_t)0x00000002U) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_LSEON ((uint32_t)0x00000100U) /*!< External Low Speed oscillator enable */ -#define RCC_CSR_LSERDY ((uint32_t)0x00000200U) /*!< External Low Speed oscillator Ready */ -#define RCC_CSR_LSEBYP ((uint32_t)0x00000400U) /*!< External Low Speed oscillator Bypass */ +#define RCC_CSR_LSEON_Pos (8U) +#define RCC_CSR_LSEON_Msk (0x1U << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */ +#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */ +#define RCC_CSR_LSERDY_Pos (9U) +#define RCC_CSR_LSERDY_Msk (0x1U << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */ +#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ +#define RCC_CSR_LSEBYP_Pos (10U) +#define RCC_CSR_LSEBYP_Msk (0x1U << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ -#define RCC_CSR_LSEDRV ((uint32_t)0x00001800U) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ -#define RCC_CSR_LSEDRV_0 ((uint32_t)0x00000800U) /*!< Bit 0 */ -#define RCC_CSR_LSEDRV_1 ((uint32_t)0x00001000U) /*!< Bit 1 */ +#define RCC_CSR_LSEDRV_Pos (11U) +#define RCC_CSR_LSEDRV_Msk (0x3U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */ +#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ +#define RCC_CSR_LSEDRV_0 (0x1U << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */ +#define RCC_CSR_LSEDRV_1 (0x2U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */ -#define RCC_CSR_LSECSSON ((uint32_t)0x00002000U) /*!< External Low Speed oscillator CSS Enable */ -#define RCC_CSR_LSECSSD ((uint32_t)0x00004000U) /*!< External Low Speed oscillator CSS Detected */ +#define RCC_CSR_LSECSSON_Pos (13U) +#define RCC_CSR_LSECSSON_Msk (0x1U << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */ +#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */ +#define RCC_CSR_LSECSSD_Pos (14U) +#define RCC_CSR_LSECSSD_Msk (0x1U << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ +#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ /*!< RTC congiguration */ -#define RCC_CSR_RTCSEL ((uint32_t)0x00030000U) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ -#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ +#define RCC_CSR_RTCSEL_Pos (16U) +#define RCC_CSR_RTCSEL_Msk (0x3U << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ +#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_CSR_RTCSEL_0 (0x1U << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */ +#define RCC_CSR_RTCSEL_1 (0x2U << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */ -#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */ -#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000U) /*!< LSE oscillator clock used as RTC clock */ -#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000U) /*!< LSI oscillator clock used as RTC clock */ -#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000U) /*!< HSE oscillator clock used as RTC clock */ +#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ +#define RCC_CSR_RTCSEL_LSE_Pos (16U) +#define RCC_CSR_RTCSEL_LSE_Msk (0x1U << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */ +#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */ +#define RCC_CSR_RTCSEL_LSI_Pos (17U) +#define RCC_CSR_RTCSEL_LSI_Msk (0x1U << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */ +#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */ +#define RCC_CSR_RTCSEL_HSE_Pos (16U) +#define RCC_CSR_RTCSEL_HSE_Msk (0x3U << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */ +#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */ -#define RCC_CSR_RTCEN ((uint32_t)0x00040000U) /*!< RTC clock enable */ -#define RCC_CSR_RTCRST ((uint32_t)0x00080000U) /*!< RTC software reset */ +#define RCC_CSR_RTCEN_Pos (18U) +#define RCC_CSR_RTCEN_Msk (0x1U << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */ +#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */ +#define RCC_CSR_RTCRST_Pos (19U) +#define RCC_CSR_RTCRST_Msk (0x1U << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */ +#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */ -#define RCC_CSR_RMVF ((uint32_t)0x00800000U) /*!< Remove reset flag */ -#define RCC_CSR_FWRSTF ((uint32_t)0x01000000U) /*!< Mifare Firewall reset flag */ -#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000U) /*!< OBL reset flag */ -#define RCC_CSR_PINRSTF ((uint32_t)0x04000000U) /*!< PIN reset flag */ -#define RCC_CSR_PORRSTF ((uint32_t)0x08000000U) /*!< POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000U) /*!< Software Reset flag */ -#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000U) /*!< Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000U) /*!< Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000U) /*!< Low-Power reset flag */ +#define RCC_CSR_RMVF_Pos (23U) +#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_CSR_FWRSTF_Pos (24U) +#define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */ +#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */ +#define RCC_CSR_OBLRSTF_Pos (25U) +#define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ +#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */ +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF_Pos (27U) +#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ /* Reference defines */ #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */ @@ -2288,278 +3891,493 @@ typedef struct /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +/* +* @brief Specific device feature definitions +*/ +#define RTC_TAMPER1_SUPPORT +#define RTC_TAMPER2_SUPPORT +#define RTC_TAMPER3_SUPPORT +#define RTC_WAKEUP_SUPPORT +#define RTC_BACKUP_SUPPORT + /******************** Bits definition for RTC_TR register *******************/ -#define RTC_TR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_TR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_TR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_TR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_TR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_TR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_TR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_TR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_TR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_TR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_TR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_TR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_TR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_TR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_TR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_TR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_TR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_TR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_TR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_TR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_TR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk /*!< */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk /*!< */ +#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk /*!< */ +#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */ +#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */ +#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk /*!< */ +#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk /*!< */ +#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_DR register *******************/ -#define RTC_DR_YT ((uint32_t)0x00F00000U) /*!< */ -#define RTC_DR_YT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_DR_YT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_DR_YT_2 ((uint32_t)0x00400000U) /*!< */ -#define RTC_DR_YT_3 ((uint32_t)0x00800000U) /*!< */ -#define RTC_DR_YU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_DR_YU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_DR_YU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_DR_YU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_DR_YU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_DR_WDU ((uint32_t)0x0000E000U) /*!< */ -#define RTC_DR_WDU_0 ((uint32_t)0x00002000U) /*!< */ -#define RTC_DR_WDU_1 ((uint32_t)0x00004000U) /*!< */ -#define RTC_DR_WDU_2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_DR_MT ((uint32_t)0x00001000U) /*!< */ -#define RTC_DR_MU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_DR_MU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_DR_MU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_DR_MU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_DR_MU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_DR_DT ((uint32_t)0x00000030U) /*!< */ -#define RTC_DR_DT_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_DR_DT_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_DR_DU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_DR_DU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_DR_DU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_DR_DU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_DR_DU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk /*!< */ +#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk /*!< */ +#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */ +#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk /*!< */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk /*!< */ +#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk /*!< */ +#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk /*!< */ +#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_CR register *******************/ -#define RTC_CR_COE ((uint32_t)0x00800000U) /*!< */ -#define RTC_CR_OSEL ((uint32_t)0x00600000U) /*!< */ -#define RTC_CR_OSEL_0 ((uint32_t)0x00200000U) /*!< */ -#define RTC_CR_OSEL_1 ((uint32_t)0x00400000U) /*!< */ -#define RTC_CR_POL ((uint32_t)0x00100000U) /*!< */ -#define RTC_CR_COSEL ((uint32_t)0x00080000U) /*!< */ -#define RTC_CR_BCK ((uint32_t)0x00040000U) /*!< */ -#define RTC_CR_SUB1H ((uint32_t)0x00020000U) /*!< */ -#define RTC_CR_ADD1H ((uint32_t)0x00010000U) /*!< */ -#define RTC_CR_TSIE ((uint32_t)0x00008000U) /*!< */ -#define RTC_CR_WUTIE ((uint32_t)0x00004000U) /*!< */ -#define RTC_CR_ALRBIE ((uint32_t)0x00002000U) /*!< */ -#define RTC_CR_ALRAIE ((uint32_t)0x00001000U) /*!< */ -#define RTC_CR_TSE ((uint32_t)0x00000800U) /*!< */ -#define RTC_CR_WUTE ((uint32_t)0x00000400U) /*!< */ -#define RTC_CR_ALRBE ((uint32_t)0x00000200U) /*!< */ -#define RTC_CR_ALRAE ((uint32_t)0x00000100U) /*!< */ -#define RTC_CR_FMT ((uint32_t)0x00000040U) /*!< */ -#define RTC_CR_BYPSHAD ((uint32_t)0x00000020U) /*!< */ -#define RTC_CR_REFCKON ((uint32_t)0x00000010U) /*!< */ -#define RTC_CR_TSEDGE ((uint32_t)0x00000008U) /*!< */ -#define RTC_CR_WUCKSEL ((uint32_t)0x00000007U) /*!< */ -#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004U) /*!< */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk /*!< */ +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */ +#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< */ +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */ +#define RTC_CR_BCK_Pos (18U) +#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ +#define RTC_CR_BCK RTC_CR_BCK_Msk /*!< */ +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */ +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */ +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */ +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */ +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */ +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */ +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */ +#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_ISR register ******************/ -#define RTC_ISR_RECALPF ((uint32_t)0x00010000U) /*!< */ -#define RTC_ISR_TAMP3F ((uint32_t)0x00008000U) /*!< */ -#define RTC_ISR_TAMP2F ((uint32_t)0x00004000U) /*!< */ -#define RTC_ISR_TAMP1F ((uint32_t)0x00002000U) /*!< */ -#define RTC_ISR_TSOVF ((uint32_t)0x00001000U) /*!< */ -#define RTC_ISR_TSF ((uint32_t)0x00000800U) /*!< */ -#define RTC_ISR_WUTF ((uint32_t)0x00000400U) /*!< */ -#define RTC_ISR_ALRBF ((uint32_t)0x00000200U) /*!< */ -#define RTC_ISR_ALRAF ((uint32_t)0x00000100U) /*!< */ -#define RTC_ISR_INIT ((uint32_t)0x00000080U) /*!< */ -#define RTC_ISR_INITF ((uint32_t)0x00000040U) /*!< */ -#define RTC_ISR_RSF ((uint32_t)0x00000020U) /*!< */ -#define RTC_ISR_INITS ((uint32_t)0x00000010U) /*!< */ -#define RTC_ISR_SHPF ((uint32_t)0x00000008U) /*!< */ -#define RTC_ISR_WUTWF ((uint32_t)0x00000004U) /*!< */ -#define RTC_ISR_ALRBWF ((uint32_t)0x00000002U) /*!< */ -#define RTC_ISR_ALRAWF ((uint32_t)0x00000001U) /*!< */ +#define RTC_ISR_RECALPF_Pos (16U) +#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */ +#define RTC_ISR_TAMP3F_Pos (15U) +#define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */ +#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */ +#define RTC_ISR_TAMP2F_Pos (14U) +#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ +#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */ +#define RTC_ISR_TAMP1F_Pos (13U) +#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ +#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */ +#define RTC_ISR_TSOVF_Pos (12U) +#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ +#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */ +#define RTC_ISR_TSF_Pos (11U) +#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ +#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */ +#define RTC_ISR_WUTF_Pos (10U) +#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ +#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */ +#define RTC_ISR_ALRBF_Pos (9U) +#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ +#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */ +#define RTC_ISR_ALRAF_Pos (8U) +#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ +#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */ +#define RTC_ISR_INIT_Pos (7U) +#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */ +#define RTC_ISR_INITF_Pos (6U) +#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */ +#define RTC_ISR_RSF_Pos (5U) +#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */ +#define RTC_ISR_INITS_Pos (4U) +#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */ +#define RTC_ISR_SHPF_Pos (3U) +#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */ +#define RTC_ISR_WUTWF_Pos (2U) +#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */ +#define RTC_ISR_ALRBWF_Pos (1U) +#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */ +#define RTC_ISR_ALRAWF_Pos (0U) +#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */ /******************** Bits definition for RTC_PRER register *****************/ -#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000U) /*!< */ -#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFFU) /*!< */ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */ /******************** Bits definition for RTC_WUTR register *****************/ -#define RTC_WUTR_WUT ((uint32_t)0x0000FFFFU) +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000U) /*!< */ -#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000U) /*!< */ -#define RTC_ALRMAR_DT ((uint32_t)0x30000000U) /*!< */ -#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000U) /*!< */ -#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000U) /*!< */ -#define RTC_ALRMAR_DU ((uint32_t)0x0F000000U) /*!< */ -#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000U) /*!< */ -#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000U) /*!< */ -#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000U) /*!< */ -#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000U) /*!< */ -#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000U) /*!< */ -#define RTC_ALRMAR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_ALRMAR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_ALRMAR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_ALRMAR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080U) /*!< */ -#define RTC_ALRMAR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_ALRMAR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */ +#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */ +#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */ +#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */ +#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */ +#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */ +#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */ +#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */ +#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000U) /*!< */ -#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000U) /*!< */ -#define RTC_ALRMBR_DT ((uint32_t)0x30000000U) /*!< */ -#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000U) /*!< */ -#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000U) /*!< */ -#define RTC_ALRMBR_DU ((uint32_t)0x0F000000U) /*!< */ -#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000U) /*!< */ -#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000U) /*!< */ -#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000U) /*!< */ -#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000U) /*!< */ -#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000U) /*!< */ -#define RTC_ALRMBR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_ALRMBR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_ALRMBR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_ALRMBR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080U) /*!< */ -#define RTC_ALRMBR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_ALRMBR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */ +#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */ +#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */ +#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */ +#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */ +#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */ +#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */ +#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */ +#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_WPR register ******************/ -#define RTC_WPR_KEY ((uint32_t)0x000000FFU) /*!< */ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */ /******************** Bits definition for RTC_SSR register ******************/ -#define RTC_SSR_SS ((uint32_t)0x0000FFFFU) /*!< */ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */ /******************** Bits definition for RTC_SHIFTR register ***************/ -#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFFU) /*!< */ -#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000U) /*!< */ +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */ +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */ /******************** Bits definition for RTC_TSTR register *****************/ -#define RTC_TSTR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_TSTR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_TSTR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_TSTR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_TSTR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_TSTR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_TSTR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_TSTR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_TSTR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_TSTR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TSTR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TSTR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_TSTR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_TSTR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_TSTR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_TSTR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_TSTR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_TSTR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_TSTR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_TSTR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */ +#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */ +#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */ +#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */ +#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */ +#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */ +#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_TSDR register *****************/ -#define RTC_TSDR_WDU ((uint32_t)0x0000E000U) /*!< */ -#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_TSDR_MT ((uint32_t)0x00001000U) /*!< */ -#define RTC_TSDR_MU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_TSDR_MU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TSDR_MU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TSDR_MU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TSDR_MU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TSDR_DT ((uint32_t)0x00000030U) /*!< */ -#define RTC_TSDR_DT_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_TSDR_DT_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_TSDR_DU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_TSDR_DU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_TSDR_DU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_TSDR_DU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_TSDR_DU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */ +#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */ +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */ +#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */ +#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */ +#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_TSSSR register ****************/ -#define RTC_TSSSR_SS ((uint32_t)0x0000FFFFU) +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /******************** Bits definition for RTC_CALR register *****************/ -#define RTC_CALR_CALP ((uint32_t)0x00008000U) /*!< */ -#define RTC_CALR_CALW8 ((uint32_t)0x00004000U) /*!< */ -#define RTC_CALR_CALW16 ((uint32_t)0x00002000U) /*!< */ -#define RTC_CALR_CALM ((uint32_t)0x000001FFU) /*!< */ -#define RTC_CALR_CALM_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_CALR_CALM_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_CALR_CALM_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_CALR_CALM_3 ((uint32_t)0x00000008U) /*!< */ -#define RTC_CALR_CALM_4 ((uint32_t)0x00000010U) /*!< */ -#define RTC_CALR_CALM_5 ((uint32_t)0x00000020U) /*!< */ -#define RTC_CALR_CALM_6 ((uint32_t)0x00000040U) /*!< */ -#define RTC_CALR_CALM_7 ((uint32_t)0x00000080U) /*!< */ -#define RTC_CALR_CALM_8 ((uint32_t)0x00000100U) /*!< */ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */ +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */ +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */ +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */ +#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ /* Legacy defines */ #define RTC_CAL_CALP RTC_CALR_CALP @@ -2577,131 +4395,269 @@ typedef struct #define RTC_CAL_CALM_8 RTC_CALR_CALM_8 /******************** Bits definition for RTC_TAMPCR register ****************/ -#define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000U) /*!< */ -#define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000U) /*!< */ -#define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000U) /*!< */ -#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000U) /*!< */ -#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000U) /*!< */ -#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000U) /*!< */ -#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000U) /*!< */ -#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000U) /*!< */ -#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000U) /*!< */ -#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000U) /*!< */ -#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000U) /*!< */ -#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800U) /*!< */ -#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080U) /*!< */ -#define RTC_TAMPCR_TAMP3TRG ((uint32_t)0x00000040U) /*!< */ -#define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020U) /*!< */ -#define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010U) /*!< */ -#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008U) /*!< */ -#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004U) /*!< */ -#define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002U) /*!< */ -#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001U) /*!< */ +#define RTC_TAMPCR_TAMP3MF_Pos (24U) +#define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ +#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */ +#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U) +#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */ +#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */ +#define RTC_TAMPCR_TAMP3IE_Pos (22U) +#define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */ +#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */ +#define RTC_TAMPCR_TAMP2MF_Pos (21U) +#define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */ +#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */ +#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U) +#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */ +#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */ +#define RTC_TAMPCR_TAMP2IE_Pos (19U) +#define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */ +#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */ +#define RTC_TAMPCR_TAMP1MF_Pos (18U) +#define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */ +#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */ +#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U) +#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */ +#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */ +#define RTC_TAMPCR_TAMP1IE_Pos (16U) +#define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ +#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */ +#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) +#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */ +#define RTC_TAMPCR_TAMPPRCH_Pos (13U) +#define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */ +#define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAMPCR_TAMPFLT_Pos (11U) +#define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */ +#define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAMPCR_TAMPFREQ_Pos (8U) +#define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */ +#define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAMPCR_TAMPTS_Pos (7U) +#define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */ +#define RTC_TAMPCR_TAMP3TRG_Pos (6U) +#define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ +#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */ +#define RTC_TAMPCR_TAMP3E_Pos (5U) +#define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ +#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */ +#define RTC_TAMPCR_TAMP2TRG_Pos (4U) +#define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ +#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */ +#define RTC_TAMPCR_TAMP2E_Pos (3U) +#define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ +#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */ +#define RTC_TAMPCR_TAMPIE_Pos (2U) +#define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */ +#define RTC_TAMPCR_TAMP1TRG_Pos (1U) +#define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ +#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */ +#define RTC_TAMPCR_TAMP1E_Pos (0U) +#define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ +#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */ /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000U) -#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000U) -#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000U) -#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000U) -#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000U) -#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFFU) +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000U) -#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000U) -#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000U) -#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000U) -#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000U) -#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFFU) +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT_RMP ((uint32_t)0x00000002U) /*!< */ -#define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001U) /*!< */ +#define RTC_OR_OUT_RMP_Pos (1U) +#define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */ +#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */ +#define RTC_OR_ALARMOUTTYPE_Pos (0U) +#define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */ +#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */ /* Legacy defines */ #define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP /******************** Bits definition for RTC_BKP0R register ****************/ -#define RTC_BKP0R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP0R_Pos (0U) +#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP0R RTC_BKP0R_Msk /*!< */ /******************** Bits definition for RTC_BKP1R register ****************/ -#define RTC_BKP1R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP1R_Pos (0U) +#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP1R RTC_BKP1R_Msk /*!< */ /******************** Bits definition for RTC_BKP2R register ****************/ -#define RTC_BKP2R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP2R_Pos (0U) +#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP2R RTC_BKP2R_Msk /*!< */ /******************** Bits definition for RTC_BKP3R register ****************/ -#define RTC_BKP3R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP3R_Pos (0U) +#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP3R RTC_BKP3R_Msk /*!< */ /******************** Bits definition for RTC_BKP4R register ****************/ -#define RTC_BKP4R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP4R_Pos (0U) +#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP4R RTC_BKP4R_Msk /*!< */ /******************** Number of backup registers ******************************/ -#define RTC_BKP_NUMBER ((uint32_t)0x00000005U) /*!< */ +#define RTC_BKP_NUMBER (0x00000005U) /*!< */ /******************************************************************************/ /* */ /* Serial Peripheral Interface (SPI) */ /* */ /******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32L0 family) + */ +/* Note: No specific macro feature on this device */ + /******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA ((uint32_t)0x00000001U) /*!< Clock Phase */ -#define SPI_CR1_CPOL ((uint32_t)0x00000002U) /*!< Clock Polarity */ -#define SPI_CR1_MSTR ((uint32_t)0x00000004U) /*!< Master Selection */ -#define SPI_CR1_BR ((uint32_t)0x00000038U) /*!< BR[2:0] bits (Baud Rate Control) */ -#define SPI_CR1_BR_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define SPI_CR1_BR_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ -#define SPI_CR1_BR_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ -#define SPI_CR1_SPE ((uint32_t)0x00000040U) /*!< SPI Enable */ -#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080U) /*!< Frame Format */ -#define SPI_CR1_SSI ((uint32_t)0x00000100U) /*!< Internal slave select */ -#define SPI_CR1_SSM ((uint32_t)0x00000200U) /*!< Software slave management */ -#define SPI_CR1_RXONLY ((uint32_t)0x00000400U) /*!< Receive only */ -#define SPI_CR1_DFF ((uint32_t)0x00000800U) /*!< Data Frame Format */ -#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000U) /*!< Transmit CRC next */ -#define SPI_CR1_CRCEN ((uint32_t)0x00002000U) /*!< Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE ((uint32_t)0x00004000U) /*!< Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000U) /*!< Bidirectional data mode enable */ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ +#define SPI_CR1_CPOL_Pos (1U) +#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ +#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ +#define SPI_CR1_MSTR_Pos (2U) +#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ +#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ +#define SPI_CR1_BR_Pos (3U) +#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */ +#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ +#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ +#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ +#define SPI_CR1_SPE_Pos (6U) +#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ +#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ +#define SPI_CR1_LSBFIRST_Pos (7U) +#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ +#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ +#define SPI_CR1_SSI_Pos (8U) +#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ +#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ +#define SPI_CR1_SSM_Pos (9U) +#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ +#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ +#define SPI_CR1_RXONLY_Pos (10U) +#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ +#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ +#define SPI_CR1_DFF_Pos (11U) +#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ +#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ +#define SPI_CR1_CRCNEXT_Pos (12U) +#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ +#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ +#define SPI_CR1_CRCEN_Pos (13U) +#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ +#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE_Pos (14U) +#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ +#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE_Pos (15U) +#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ +#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ /******************* Bit definition for SPI_CR2 register ********************/ -#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001U) /*!< Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002U) /*!< Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE ((uint32_t)0x00000004U) /*!< SS Output Enable */ -#define SPI_CR2_FRF ((uint32_t)0x00000010U) /*!< Frame Format Enable */ -#define SPI_CR2_ERRIE ((uint32_t)0x00000020U) /*!< Error Interrupt Enable */ -#define SPI_CR2_RXNEIE ((uint32_t)0x00000040U) /*!< RX buffer Not Empty Interrupt Enable */ -#define SPI_CR2_TXEIE ((uint32_t)0x00000080U) /*!< Tx buffer Empty Interrupt Enable */ +#define SPI_CR2_RXDMAEN_Pos (0U) +#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ +#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN_Pos (1U) +#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ +#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE_Pos (2U) +#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ +#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ +#define SPI_CR2_FRF_Pos (4U) +#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ +#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ +#define SPI_CR2_ERRIE_Pos (5U) +#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ +#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ +#define SPI_CR2_RXNEIE_Pos (6U) +#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ +#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE_Pos (7U) +#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ +#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ /******************** Bit definition for SPI_SR register ********************/ -#define SPI_SR_RXNE ((uint32_t)0x00000001U) /*!< Receive buffer Not Empty */ -#define SPI_SR_TXE ((uint32_t)0x00000002U) /*!< Transmit buffer Empty */ -#define SPI_SR_CHSIDE ((uint32_t)0x00000004U) /*!< Channel side */ -#define SPI_SR_UDR ((uint32_t)0x00000008U) /*!< Underrun flag */ -#define SPI_SR_CRCERR ((uint32_t)0x00000010U) /*!< CRC Error flag */ -#define SPI_SR_MODF ((uint32_t)0x00000020U) /*!< Mode fault */ -#define SPI_SR_OVR ((uint32_t)0x00000040U) /*!< Overrun flag */ -#define SPI_SR_BSY ((uint32_t)0x00000080U) /*!< Busy flag */ -#define SPI_SR_FRE ((uint32_t)0x00000100U) /*!< TI frame format error */ +#define SPI_SR_RXNE_Pos (0U) +#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ +#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ +#define SPI_SR_TXE_Pos (1U) +#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ +#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ +#define SPI_SR_CHSIDE_Pos (2U) +#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ +#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ +#define SPI_SR_UDR_Pos (3U) +#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */ +#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ +#define SPI_SR_CRCERR_Pos (4U) +#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ +#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ +#define SPI_SR_MODF_Pos (5U) +#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */ +#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ +#define SPI_SR_OVR_Pos (6U) +#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */ +#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ +#define SPI_SR_BSY_Pos (7U) +#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */ +#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ +#define SPI_SR_FRE_Pos (8U) +#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */ +#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ /******************** Bit definition for SPI_DR register ********************/ -#define SPI_DR_DR ((uint32_t)0x0000FFFFU) /*!< Data Register */ +#define SPI_DR_DR_Pos (0U) +#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ +#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ /******************* Bit definition for SPI_CRCPR register ******************/ -#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFFU) /*!< CRC polynomial register */ +#define SPI_CRCPR_CRCPOLY_Pos (0U) +#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ +#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ /****************** Bit definition for SPI_RXCRCR register ******************/ -#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFFU) /*!< Rx CRC Register */ +#define SPI_RXCRCR_RXCRC_Pos (0U) +#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ /****************** Bit definition for SPI_TXCRCR register ******************/ -#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFFU) /*!< Tx CRC Register */ +#define SPI_TXCRCR_TXCRC_Pos (0U) +#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ /******************************************************************************/ /* */ @@ -2709,181 +4665,239 @@ typedef struct /* */ /******************************************************************************/ /***************** Bit definition for SYSCFG_CFGR1 register ****************/ -#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003U) /*!< SYSCFG_Memory Remap Config */ -#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001U) /*!< SYSCFG_Memory Remap Config Bit 0 */ -#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002U) /*!< SYSCFG_Memory Remap Config Bit 1 */ -#define SYSCFG_CFGR1_BOOT_MODE ((uint32_t)0x00000300U) /*!< SYSCFG_Boot mode Config */ -#define SYSCFG_CFGR1_BOOT_MODE_0 ((uint32_t)0x00000100U) /*!< SYSCFG_Boot mode Config Bit 0 */ -#define SYSCFG_CFGR1_BOOT_MODE_1 ((uint32_t)0x00000200U) /*!< SYSCFG_Boot mode Config Bit 1 */ +#define SYSCFG_CFGR1_MEM_MODE_Pos (0U) +#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */ +#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ +#define SYSCFG_CFGR1_MEM_MODE_0 (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */ +#define SYSCFG_CFGR1_MEM_MODE_1 (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */ +#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U) +#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */ +#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */ +#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */ +#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */ /***************** Bit definition for SYSCFG_CFGR2 register ****************/ -#define SYSCFG_CFGR2_FWDISEN ((uint32_t)0x00000001U) /*!< Firewall disable bit */ -#define SYSCFG_CFGR2_I2C_PB6_FMP ((uint32_t)0x00000100U) /*!< I2C PB6 Fast mode plus */ -#define SYSCFG_CFGR2_I2C_PB7_FMP ((uint32_t)0x00000200U) /*!< I2C PB7 Fast mode plus */ -#define SYSCFG_CFGR2_I2C_PB8_FMP ((uint32_t)0x00000400U) /*!< I2C PB8 Fast mode plus */ -#define SYSCFG_CFGR2_I2C_PB9_FMP ((uint32_t)0x00000800U) /*!< I2C PB9 Fast mode plus */ -#define SYSCFG_CFGR2_I2C1_FMP ((uint32_t)0x00001000U) /*!< I2C1 Fast mode plus */ +#define SYSCFG_CFGR2_FWDISEN_Pos (0U) +#define SYSCFG_CFGR2_FWDISEN_Msk (0x1U << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */ +#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */ +#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U) +#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */ +#define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */ +#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U) +#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */ +#define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */ +#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U) +#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */ +#define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */ +#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U) +#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */ +#define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */ +#define SYSCFG_CFGR2_I2C1_FMP_Pos (12U) +#define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */ +#define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */ /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ -#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000FU) /*!< EXTI 0 configuration */ -#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0U) /*!< EXTI 1 configuration */ -#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00U) /*!< EXTI 2 configuration */ -#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000U) /*!< EXTI 3 configuration */ +#define SYSCFG_EXTICR1_EXTI0_Pos (0U) +#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ +#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define SYSCFG_EXTICR1_EXTI1_Pos (4U) +#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ +#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define SYSCFG_EXTICR1_EXTI2_Pos (8U) +#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ +#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define SYSCFG_EXTICR1_EXTI3_Pos (12U) +#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ +#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000U) /*!< PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001U) /*!< PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002U) /*!< PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005U) /*!< PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000U) /*!< PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010U) /*!< PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020U) /*!< PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050U) /*!< PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000U) /*!< PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100U) /*!< PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200U) /*!< PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300U) /*!< PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000U) /*!< PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000U) /*!< PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000U) /*!< PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register *****************/ -#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000FU) /*!< EXTI 4 configuration */ -#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0U) /*!< EXTI 5 configuration */ -#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00U) /*!< EXTI 6 configuration */ -#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000U) /*!< EXTI 7 configuration */ +#define SYSCFG_EXTICR2_EXTI4_Pos (0U) +#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ +#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define SYSCFG_EXTICR2_EXTI5_Pos (4U) +#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ +#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define SYSCFG_EXTICR2_EXTI6_Pos (8U) +#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ +#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define SYSCFG_EXTICR2_EXTI7_Pos (12U) +#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ +#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000U) /*!< PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001U) /*!< PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002U) /*!< PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000U) /*!< PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010U) /*!< PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020U) /*!< PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000U) /*!< PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100U) /*!< PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200U) /*!< PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000U) /*!< PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000U) /*!< PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000U) /*!< PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register *****************/ -#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000FU) /*!< EXTI 8 configuration */ -#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0U) /*!< EXTI 9 configuration */ -#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00U) /*!< EXTI 10 configuration */ -#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000U) /*!< EXTI 11 configuration */ +#define SYSCFG_EXTICR3_EXTI8_Pos (0U) +#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ +#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define SYSCFG_EXTICR3_EXTI9_Pos (4U) +#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ +#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define SYSCFG_EXTICR3_EXTI10_Pos (8U) +#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ +#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define SYSCFG_EXTICR3_EXTI11_Pos (12U) +#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ +#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000U) /*!< PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001U) /*!< PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002U) /*!< PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000U) /*!< PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010U) /*!< PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020U) /*!< PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000U) /*!< PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100U) /*!< PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200U) /*!< PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000U) /*!< PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000U) /*!< PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000U) /*!< PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register *****************/ -#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000FU) /*!< EXTI 12 configuration */ -#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0U) /*!< EXTI 13 configuration */ -#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00U) /*!< EXTI 14 configuration */ -#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000U) /*!< EXTI 15 configuration */ +#define SYSCFG_EXTICR4_EXTI12_Pos (0U) +#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ +#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define SYSCFG_EXTICR4_EXTI13_Pos (4U) +#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ +#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define SYSCFG_EXTICR4_EXTI14_Pos (8U) +#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ +#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define SYSCFG_EXTICR4_EXTI15_Pos (12U) +#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ +#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000U) /*!< PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001U) /*!< PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002U) /*!< PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000U) /*!< PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010U) /*!< PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020U) /*!< PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000U) /*!< PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100U) /*!< PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200U) /*!< PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000U) /*!< PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000U) /*!< PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000U) /*!< PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ /***************** Bit definition for SYSCFG_CFGR3 register ****************/ -#define SYSCFG_CFGR3_EN_VREFINT ((uint32_t)0x00000001U) /*!< Vref Enable bit*/ -#define SYSCFG_CFGR3_VREF_OUT ((uint32_t)0x00000030U) /*!< Verf_ADC connection bit */ -#define SYSCFG_CFGR3_VREF_OUT_0 ((uint32_t)0x00000010U) /*!< Bit 0 */ -#define SYSCFG_CFGR3_VREF_OUT_1 ((uint32_t)0x00000020U) /*!< Bit 1 */ -#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC ((uint32_t)0x00000100U) /*!< VREFINT reference for ADC enable bit */ -#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC ((uint32_t)0x00000200U) /*!< Sensor reference for ADC enable bit */ -#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP ((uint32_t)0x00001000U) /*!< VREFINT reference for comparator 2 enable bit */ -#define SYSCFG_CFGR3_SENSOR_ADC_RDYF ((uint32_t)0x08000000U) /*!< Sensor for ADC ready flag */ -#define SYSCFG_CFGR3_VREFINT_ADC_RDYF ((uint32_t)0x10000000U) /*!< VREFINT for ADC ready flag */ -#define SYSCFG_CFGR3_VREFINT_COMP_RDYF ((uint32_t)0x20000000U) /*!< VREFINT for comparator ready flag */ -#define SYSCFG_CFGR3_VREFINT_RDYF ((uint32_t)0x40000000U) /*!< VREFINT ready flag */ -#define SYSCFG_CFGR3_REF_LOCK ((uint32_t)0x80000000U) /*!< CFGR3 lock bit */ +#define SYSCFG_CFGR3_VREF_OUT_Pos (4U) +#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */ +#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */ +#define SYSCFG_CFGR3_VREF_OUT_0 (0x1U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */ +#define SYSCFG_CFGR3_VREF_OUT_1 (0x2U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */ +#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U) +#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1U << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */ +#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */ +#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U) +#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1U << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */ +#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */ +#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U) +#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1U << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */ +#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */ +#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U) +#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1U << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */ +#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */ +#define SYSCFG_CFGR3_REF_LOCK_Pos (31U) +#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1U << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */ +#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */ /* Legacy defines */ -#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT #define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC #define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP -#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_ADC_RDYF +#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF +#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF +#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF +#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF /******************************************************************************/ /* */ @@ -2902,273 +4916,481 @@ typedef struct #endif /******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN ((uint32_t)0x00000001U) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -83,15 +83,15 @@ #include "hal_tick.h" #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/ + #define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* MSI_VALUE */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ @@ -115,8 +115,8 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. + This value must be a multiple of 0x100. */ /******************************************************************************/ /** * @} @@ -147,8 +147,9 @@ variable is updated automatically. */ uint32_t SystemCoreClock = 32000000; -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U}; /** * @} @@ -181,25 +182,25 @@ uint8_t SetSysClock_MSI(void); void SystemInit (void) { /*!< Set MSION bit */ - RCC->CR |= (uint32_t)0x00000100; + RCC->CR |= (uint32_t)0x00000100U; /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ - RCC->CFGR &= (uint32_t) 0x88FF400C; + RCC->CFGR &= (uint32_t) 0x88FF400CU; /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFF6; + RCC->CR &= (uint32_t)0xFEF6FFF6U; /*!< Reset HSI48ON bit */ - RCC->CRRCR &= (uint32_t)0xFFFFFFFE; + RCC->CRRCR &= (uint32_t)0xFFFFFFFEU; /*!< Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; + RCC->CR &= (uint32_t)0xFFFBFFFFU; /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ - RCC->CFGR &= (uint32_t)0xFF02FFFF; + RCC->CFGR &= (uint32_t)0xFF02FFFFU; /*!< Disable all interrupts */ - RCC->CIER = 0x00000000; + RCC->CIER = 0x00000000U; /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM @@ -261,33 +262,33 @@ void SystemInit (void) */ void SystemCoreClockUpdate (void) { - uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; + uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; switch (tmp) { - case 0x00: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); + case 0x00U: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; + SystemCoreClock = (32768U * (1U << (msirange + 1U))); break; - case 0x04: /* HSI used as system clock */ + case 0x04U: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; break; - case 0x08: /* HSE used as system clock */ + case 0x08U: /* HSE used as system clock */ SystemCoreClock = HSE_VALUE; break; - case 0x0C: /* PLL used as system clock */ + case 0x0CU: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; - pllmul = PLLMulTable[(pllmul >> 18)]; - plldiv = (plldiv >> 22) + 1; + pllmul = PLLMulTable[(pllmul >> 18U)]; + plldiv = (plldiv >> 22U) + 1U; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - if (pllsource == 0x00) + if (pllsource == 0x00U) { /* HSI oscillator clock selected as PLL clock entry */ SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); @@ -299,13 +300,13 @@ void SystemCoreClockUpdate (void) } break; default: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; + SystemCoreClock = (32768U * (1U << (msirange + 1U))); break; } /* Compute HCLK clock frequency --------------------------------------------*/ /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/system_stm32l0xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/system_stm32l0xx.h index 4a82de7134..7015debf51 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/system_stm32l0xx.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/system_stm32l0xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32l0xx.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -74,6 +74,11 @@ variable is updated automatically. */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/* +*/ +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/stm32l053xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/stm32l053xx.h index 88d4d061a8..30fd888e28 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/stm32l053xx.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/stm32l053xx.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l053xx.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for stm32l053xx devices. @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -634,66 +634,70 @@ typedef struct #define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */ #define DATA_EEPROM_END ((uint32_t)0x080807FFU) /*!< DATA EEPROM end address in the alias region */ #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */ +#define SRAM_SIZE_MAX ((uint32_t)0x00002000U) /*!< maximum SRAM size (up to 8KBytes) */ + #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */ /*!< Peripheral memory map */ #define APBPERIPH_BASE PERIPH_BASE -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) -#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) +#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000U) -#define TIM2_BASE (APBPERIPH_BASE + 0x00000000) -#define TIM6_BASE (APBPERIPH_BASE + 0x00001000) -#define LCD_BASE (APBPERIPH_BASE + 0x00002400) -#define RTC_BASE (APBPERIPH_BASE + 0x00002800) -#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00) -#define IWDG_BASE (APBPERIPH_BASE + 0x00003000) -#define SPI2_BASE (APBPERIPH_BASE + 0x00003800) -#define USART2_BASE (APBPERIPH_BASE + 0x00004400) -#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800) -#define I2C1_BASE (APBPERIPH_BASE + 0x00005400) -#define I2C2_BASE (APBPERIPH_BASE + 0x00005800) -#define CRS_BASE (APBPERIPH_BASE + 0x00006C00) -#define PWR_BASE (APBPERIPH_BASE + 0x00007000) -#define DAC_BASE (APBPERIPH_BASE + 0x00007400) -#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00) +#define TIM2_BASE (APBPERIPH_BASE + 0x00000000U) +#define TIM6_BASE (APBPERIPH_BASE + 0x00001000U) +#define LCD_BASE (APBPERIPH_BASE + 0x00002400U) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800U) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00U) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000U) +#define SPI2_BASE (APBPERIPH_BASE + 0x00003800U) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400U) +#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800U) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400U) +#define I2C2_BASE (APBPERIPH_BASE + 0x00005800U) +#define CRS_BASE (APBPERIPH_BASE + 0x00006C00U) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000U) +#define DAC_BASE (APBPERIPH_BASE + 0x00007400U) +#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00U) -#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000) -#define COMP1_BASE (APBPERIPH_BASE + 0x00010018) -#define COMP2_BASE (APBPERIPH_BASE + 0x0001001C) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000U) +#define COMP1_BASE (APBPERIPH_BASE + 0x00010018U) +#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CU) #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE) -#define EXTI_BASE (APBPERIPH_BASE + 0x00010400) -#define TIM21_BASE (APBPERIPH_BASE + 0x00010800) -#define TIM22_BASE (APBPERIPH_BASE + 0x00011400) -#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00) -#define ADC1_BASE (APBPERIPH_BASE + 0x00012400) -#define ADC_BASE (APBPERIPH_BASE + 0x00012708) -#define SPI1_BASE (APBPERIPH_BASE + 0x00013000) -#define USART1_BASE (APBPERIPH_BASE + 0x00013800) -#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800) +#define EXTI_BASE (APBPERIPH_BASE + 0x00010400U) +#define TIM21_BASE (APBPERIPH_BASE + 0x00010800U) +#define TIM22_BASE (APBPERIPH_BASE + 0x00011400U) +#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00U) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400U) +#define ADC_BASE (APBPERIPH_BASE + 0x00012708U) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000U) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800U) +#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800U) -#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080) -#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8) +#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8U) -#define RCC_BASE (AHBPERIPH_BASE + 0x00001000) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */ +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */ #define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */ -#define CRC_BASE (AHBPERIPH_BASE + 0x00003000) -#define TSC_BASE (AHBPERIPH_BASE + 0x00004000) -#define RNG_BASE (AHBPERIPH_BASE + 0x00005000) +#define FLASHSIZE_BASE ((uint32_t)0x1FF8007CU) /*!< FLASH Size register base address */ +#define UID_BASE ((uint32_t)0x1FF80050U) /*!< Unique device ID register base address */ +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) +#define TSC_BASE (AHBPERIPH_BASE + 0x00004000U) +#define RNG_BASE (AHBPERIPH_BASE + 0x00005000U) -#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000) -#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400) -#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800) -#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00) -#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00) +#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000U) +#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400U) +#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800U) +#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00U) +#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00U) /** * @} @@ -782,91 +786,173 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for ADC_ISR register ******************/ -#define ADC_ISR_EOCAL ((uint32_t)0x00000800U) /*!< End of calibration flag */ -#define ADC_ISR_AWD ((uint32_t)0x00000080U) /*!< Analog watchdog flag */ -#define ADC_ISR_OVR ((uint32_t)0x00000010U) /*!< Overrun flag */ -#define ADC_ISR_EOSEQ ((uint32_t)0x00000008U) /*!< End of Sequence flag */ -#define ADC_ISR_EOC ((uint32_t)0x00000004U) /*!< End of Conversion */ -#define ADC_ISR_EOSMP ((uint32_t)0x00000002U) /*!< End of sampling flag */ -#define ADC_ISR_ADRDY ((uint32_t)0x00000001U) /*!< ADC Ready */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1U << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */ +#define ADC_ISR_AWD_Pos (7U) +#define ADC_ISR_AWD_Msk (0x1U << ADC_ISR_AWD_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */ +#define ADC_ISR_EOSEQ_Pos (3U) +#define ADC_ISR_EOSEQ_Msk (0x1U << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */ /* Old EOSEQ bit definition, maintained for legacy purpose */ #define ADC_ISR_EOS ADC_ISR_EOSEQ /******************** Bits definition for ADC_IER register ******************/ -#define ADC_IER_EOCALIE ((uint32_t)0x00000800U) /*!< Enf Of Calibration interrupt enable */ -#define ADC_IER_AWDIE ((uint32_t)0x00000080U) /*!< Analog Watchdog interrupt enable */ -#define ADC_IER_OVRIE ((uint32_t)0x00000010U) /*!< Overrun interrupt enable */ -#define ADC_IER_EOSEQIE ((uint32_t)0x00000008U) /*!< End of Sequence of conversion interrupt enable */ -#define ADC_IER_EOCIE ((uint32_t)0x00000004U) /*!< End of Conversion interrupt enable */ -#define ADC_IER_EOSMPIE ((uint32_t)0x00000002U) /*!< End of sampling interrupt enable */ -#define ADC_IER_ADRDYIE ((uint32_t)0x00000001U) /*!< ADC Ready interrupt enable */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1U << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */ +#define ADC_IER_AWDIE_Pos (7U) +#define ADC_IER_AWDIE_Msk (0x1U << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */ +#define ADC_IER_EOSEQIE_Pos (3U) +#define ADC_IER_EOSEQIE_Msk (0x1U << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */ /* Old EOSEQIE bit definition, maintained for legacy purpose */ #define ADC_IER_EOSIE ADC_IER_EOSEQIE /******************** Bits definition for ADC_CR register *******************/ -#define ADC_CR_ADCAL ((uint32_t)0x80000000U) /*!< ADC calibration */ -#define ADC_CR_ADVREGEN ((uint32_t)0x10000000U) /*!< ADC Voltage Regulator Enable */ -#define ADC_CR_ADSTP ((uint32_t)0x00000010U) /*!< ADC stop of conversion command */ -#define ADC_CR_ADSTART ((uint32_t)0x00000004U) /*!< ADC start of conversion */ -#define ADC_CR_ADDIS ((uint32_t)0x00000002U) /*!< ADC disable command */ -#define ADC_CR_ADEN ((uint32_t)0x00000001U) /*!< ADC enable control */ /*#### TBV */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */ /******************* Bits definition for ADC_CFGR1 register *****************/ -#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000U) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000U) /*!< Bit 0 */ -#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000U) /*!< Bit 1 */ -#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000U) /*!< Bit 2 */ -#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000U) /*!< Bit 3 */ -#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000U) /*!< Bit 4 */ -#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000U) /*!< Analog watchdog enable on regular channels */ -#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000U) /*!< Enable the watchdog on a single channel or on all channels */ -#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000U) /*!< Discontinuous mode on regular channels */ -#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000U) /*!< ADC auto power off */ -#define ADC_CFGR1_WAIT ((uint32_t)0x00004000U) /*!< ADC wait conversion mode */ -#define ADC_CFGR1_CONT ((uint32_t)0x00002000U) /*!< Continuous Conversion */ -#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000U) /*!< Overrun mode */ -#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00U) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ -#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ -#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ -#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0U) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ -#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ -#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100U) /*!< Bit 2 */ -#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020U) /*!< Data Alignment */ -#define ADC_CFGR1_RES ((uint32_t)0x00000018U) /*!< RES[1:0] bits (Resolution) */ -#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ -#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004U) /*!< Sequence scan direction */ -#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002U) /*!< Direct memory access configuration */ -#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001U) /*!< Direct memory access enable */ +#define ADC_CFGR1_AWDCH_Pos (26U) +#define ADC_CFGR1_AWDCH_Msk (0x1FU << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CFGR1_AWDCH_0 (0x01U << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWDCH_1 (0x02U << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWDCH_2 (0x04U << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWDCH_3 (0x08U << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWDCH_4 (0x10U << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ +#define ADC_CFGR1_AWDEN_Pos (23U) +#define ADC_CFGR1_AWDEN_Msk (0x1U << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */ +#define ADC_CFGR1_AWDSGL_Pos (22U) +#define ADC_CFGR1_AWDSGL_Msk (0x1U << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */ +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */ +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ +#define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */ +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */ /* Old WAIT bit definition, maintained for legacy purpose */ #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT /******************* Bits definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_TOVS ((uint32_t)0x80000200U) /*!< Triggered Oversampling */ -#define ADC_CFGR2_OVSS ((uint32_t)0x000001E0U) /*!< OVSS [3:0] bits (Oversampling shift) */ -#define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ -#define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ -#define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ -#define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ -#define ADC_CFGR2_OVSR ((uint32_t)0x0000001CU) /*!< OVSR [2:0] bits (Oversampling ratio) */ -#define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004U) /*!< Bit 0 */ -#define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008U) /*!< Bit 1 */ -#define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010U) /*!< Bit 2 */ -#define ADC_CFGR2_OVSE ((uint32_t)0x00000001U) /*!< Oversampler Enable */ -#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000U) /*!< CKMODE [1:0] bits (ADC clock mode) */ -#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000U) /*!< Bit 0 */ -#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000U) /*!< Bit 1 */ +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x400001U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */ +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */ +#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */ +#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1U << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */ +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */ +#define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ /****************** Bit definition for ADC_SMPR register ********************/ -#define ADC_SMPR_SMP ((uint32_t)0x00000007U) /*!< SMPR[2:0] bits (Sampling time selection) */ -#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ -#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ -#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SMPR_SMP_Pos (0U) +#define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */ +#define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ /* Legacy defines */ #define ADC_SMPR_SMPR ADC_SMPR_SMP @@ -875,47 +961,105 @@ typedef struct #define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2 /******************* Bit definition for ADC_TR register ********************/ -#define ADC_TR_HT ((uint32_t)0x0FFF0000U) /*!< Analog watchdog high threshold */ -#define ADC_TR_LT ((uint32_t)0x00000FFFU) /*!< Analog watchdog low threshold */ +#define ADC_TR_HT_Pos (16U) +#define ADC_TR_HT_Msk (0xFFFU << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */ +#define ADC_TR_LT_Pos (0U) +#define ADC_TR_LT_Msk (0xFFFU << ADC_TR_LT_Pos) /*!< 0x00000FFF */ +#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */ /****************** Bit definition for ADC_CHSELR register ******************/ -#define ADC_CHSELR_CHSEL ((uint32_t)0x0007FFFFU) /*!< ADC group regular sequencer channels */ -#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000U) /*!< Channel 18 selection */ -#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000U) /*!< Channel 17 selection */ -#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000U) /*!< Channel 16 selection */ -#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000U) /*!< Channel 15 selection */ -#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000U) /*!< Channel 14 selection */ -#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000U) /*!< Channel 13 selection */ -#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000U) /*!< Channel 12 selection */ -#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800U) /*!< Channel 11 selection */ -#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400U) /*!< Channel 10 selection */ -#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200U) /*!< Channel 9 selection */ -#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100U) /*!< Channel 8 selection */ -#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080U) /*!< Channel 7 selection */ -#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040U) /*!< Channel 6 selection */ -#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020U) /*!< Channel 5 selection */ -#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010U) /*!< Channel 4 selection */ -#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008U) /*!< Channel 3 selection */ -#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004U) /*!< Channel 2 selection */ -#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002U) /*!< Channel 1 selection */ -#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001U) /*!< Channel 0 selection */ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1U << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< Channel 16 selection */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFFU) /*!< Regular data */ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */ /******************** Bit definition for ADC_CALFACT register ********************/ -#define ADC_CALFACT_CALFACT ((uint32_t)0x0000007FU) /*!< Calibration factor */ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FU << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */ /******************* Bit definition for ADC_CCR register ********************/ -#define ADC_CCR_LFMEN ((uint32_t)0x02000000U) /*!< Low Frequency Mode enable */ -#define ADC_CCR_VLCDEN ((uint32_t)0x01000000U) /*!< Voltage LCD enable */ -#define ADC_CCR_TSEN ((uint32_t)0x00800000U) /*!< Temperature sensore enable */ -#define ADC_CCR_VREFEN ((uint32_t)0x00400000U) /*!< Vrefint enable */ -#define ADC_CCR_PRESC ((uint32_t)0x003C0000U) /*!< PRESC [3:0] bits (ADC prescaler) */ -#define ADC_CCR_PRESC_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ -#define ADC_CCR_PRESC_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ -#define ADC_CCR_PRESC_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ -#define ADC_CCR_PRESC_3 ((uint32_t)0x00200000U) /*!< Bit 3 */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1U << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */ +#define ADC_CCR_VLCDEN_Pos (24U) +#define ADC_CCR_VLCDEN_Msk (0x1U << ADC_CCR_VLCDEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VLCDEN ADC_CCR_VLCDEN_Msk /*!< Voltage LCD enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */ +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */ +#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ /******************************************************************************/ /* */ @@ -924,37 +1068,77 @@ typedef struct /******************************************************************************/ /************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/ /* COMP1 bits definition */ -#define COMP_CSR_COMP1EN ((uint32_t)0x00000001U) /*!< COMP1 enable */ -#define COMP_CSR_COMP1INNSEL ((uint32_t)0x00000030U) /*!< COMP1 inverting input select */ -#define COMP_CSR_COMP1INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP1 inverting input select bit 0 */ -#define COMP_CSR_COMP1INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP1 inverting input select bit 1 */ -#define COMP_CSR_COMP1WM ((uint32_t)0x00000100U) /*!< Comparators window mode enable */ -#define COMP_CSR_COMP1LPTIM1IN1 ((uint32_t)0x00001000U) /*!< COMP1 LPTIM1 IN1 connection */ -#define COMP_CSR_COMP1POLARITY ((uint32_t)0x00008000U) /*!< COMP1 output polarity */ -#define COMP_CSR_COMP1VALUE ((uint32_t)0x40000000U) /*!< COMP1 output level */ -#define COMP_CSR_COMP1LOCK ((uint32_t)0x80000000U) /*!< COMP1 lock */ +#define COMP_CSR_COMP1EN_Pos (0U) +#define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */ +#define COMP_CSR_COMP1INNSEL_Pos (4U) +#define COMP_CSR_COMP1INNSEL_Msk (0x3U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */ +#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */ +#define COMP_CSR_COMP1INNSEL_0 (0x1U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_COMP1INNSEL_1 (0x2U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_COMP1WM_Pos (8U) +#define COMP_CSR_COMP1WM_Msk (0x1U << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */ +#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */ +#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U) +#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */ +#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */ +#define COMP_CSR_COMP1POLARITY_Pos (15U) +#define COMP_CSR_COMP1POLARITY_Msk (0x1U << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */ +#define COMP_CSR_COMP1VALUE_Pos (30U) +#define COMP_CSR_COMP1VALUE_Msk (0x1U << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */ +#define COMP_CSR_COMP1LOCK_Pos (31U) +#define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */ /* COMP2 bits definition */ -#define COMP_CSR_COMP2EN ((uint32_t)0x00000001U) /*!< COMP2 enable */ -#define COMP_CSR_COMP2SPEED ((uint32_t)0x00000008U) /*!< COMP2 power mode */ -#define COMP_CSR_COMP2INNSEL ((uint32_t)0x00000070U) /*!< COMP2 inverting input select */ -#define COMP_CSR_COMP2INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP2 inverting input select bit 0 */ -#define COMP_CSR_COMP2INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP2 inverting input select bit 1 */ -#define COMP_CSR_COMP2INNSEL_2 ((uint32_t)0x00000040U) /*!< COMP2 inverting input select bit 2 */ -#define COMP_CSR_COMP2INPSEL ((uint32_t)0x00000700U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2INPSEL_0 ((uint32_t)0x00000100U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2INPSEL_1 ((uint32_t)0x00000200U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2INPSEL_2 ((uint32_t)0x00000400U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2LPTIM1IN2 ((uint32_t)0x00001000U) /*!< COMP2 LPTIM1 IN2 connection */ -#define COMP_CSR_COMP2LPTIM1IN1 ((uint32_t)0x00002000U) /*!< COMP2 LPTIM1 IN1 connection */ -#define COMP_CSR_COMP2POLARITY ((uint32_t)0x00008000U) /*!< COMP2 output polarity */ -#define COMP_CSR_COMP2VALUE ((uint32_t)0x40000000U) /*!< COMP2 output level */ -#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000U) /*!< COMP2 lock */ +#define COMP_CSR_COMP2EN_Pos (0U) +#define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */ +#define COMP_CSR_COMP2SPEED_Pos (3U) +#define COMP_CSR_COMP2SPEED_Msk (0x1U << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */ +#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */ +#define COMP_CSR_COMP2INNSEL_Pos (4U) +#define COMP_CSR_COMP2INNSEL_Msk (0x7U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */ +#define COMP_CSR_COMP2INNSEL_0 (0x1U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_COMP2INNSEL_1 (0x2U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_COMP2INNSEL_2 (0x4U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_COMP2INPSEL_Pos (8U) +#define COMP_CSR_COMP2INPSEL_Msk (0x7U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */ +#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */ +#define COMP_CSR_COMP2INPSEL_0 (0x1U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_COMP2INPSEL_1 (0x2U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */ +#define COMP_CSR_COMP2INPSEL_2 (0x4U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */ +#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U) +#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */ +#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */ +#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U) +#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */ +#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */ +#define COMP_CSR_COMP2POLARITY_Pos (15U) +#define COMP_CSR_COMP2POLARITY_Msk (0x1U << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */ +#define COMP_CSR_COMP2VALUE_Pos (30U) +#define COMP_CSR_COMP2VALUE_Msk (0x1U << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */ +#define COMP_CSR_COMP2LOCK_Pos (31U) +#define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */ /********************** Bit definition for COMP_CSR register common ****************/ -#define COMP_CSR_COMPxEN ((uint32_t)0x00000001U) /*!< COMPx enable */ -#define COMP_CSR_COMPxPOLARITY ((uint32_t)0x00008000U) /*!< COMPx output polarity */ -#define COMP_CSR_COMPxOUTVALUE ((uint32_t)0x40000000U) /*!< COMPx output level */ -#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000U) /*!< COMPx lock */ +#define COMP_CSR_COMPxEN_Pos (0U) +#define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */ +#define COMP_CSR_COMPxPOLARITY_Pos (15U) +#define COMP_CSR_COMPxPOLARITY_Msk (0x1U << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */ +#define COMP_CSR_COMPxOUTVALUE_Pos (30U) +#define COMP_CSR_COMPxOUTVALUE_Msk (0x1U << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */ +#define COMP_CSR_COMPxLOCK_Pos (31U) +#define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */ /* Reference defines */ #define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ @@ -965,26 +1149,40 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ +#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET the CRC computation unit bit */ -#define CRC_CR_POLYSIZE ((uint32_t)0x00000018U) /*!< Polynomial size bits */ -#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008U) /*!< Polynomial size bit 0 */ -#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010U) /*!< Polynomial size bit 1 */ -#define CRC_CR_REV_IN ((uint32_t)0x00000060U) /*!< REV_IN Reverse Input Data bits */ -#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ -#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ -#define CRC_CR_REV_OUT ((uint32_t)0x00000080U) /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ /******************* Bit definition for CRC_INIT register *******************/ -#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFFU) /*!< Initial CRC value bits */ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ -#define CRC_POL_POL ((uint32_t)0xFFFFFFFFU) /*!< Coefficients of the polynomial */ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ /******************************************************************************/ /* */ @@ -993,46 +1191,98 @@ typedef struct /******************************************************************************/ /******************* Bit definition for CRS_CR register *********************/ -#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001U) /* SYNC event OK interrupt enable */ -#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002U) /* SYNC warning interrupt enable */ -#define CRS_CR_ERRIE ((uint32_t)0x00000004U) /* SYNC error interrupt enable */ -#define CRS_CR_ESYNCIE ((uint32_t)0x00000008U) /* Expected SYNC(ESYNCF) interrupt Enable*/ -#define CRS_CR_CEN ((uint32_t)0x00000020U) /* Frequency error counter enable */ -#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040U) /* Automatic trimming enable */ -#define CRS_CR_SWSYNC ((uint32_t)0x00000080U) /* A Software SYNC event is generated */ -#define CRS_CR_TRIM ((uint32_t)0x00003F00U) /* HSI48 oscillator smooth trimming */ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ -#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFFU) /* Counter reload value */ -#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000U) /* Frequency error limit */ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */ -#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000U) /* SYNC divider */ -#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000U) /* Bit 0 */ -#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000U) /* Bit 1 */ -#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000U) /* Bit 2 */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ -#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000U) /* SYNC signal source selection */ -#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000U) /* Bit 0 */ -#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000U) /* Bit 1 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ -#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000U) /* SYNC polarity selection */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */ /******************* Bit definition for CRS_ISR register *********************/ -#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001U) /* SYNC event OK flag */ -#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002U) /* SYNC warning */ -#define CRS_ISR_ERRF ((uint32_t)0x00000004U) /* SYNC error flag */ -#define CRS_ISR_ESYNCF ((uint32_t)0x00000008U) /* Expected SYNC flag */ -#define CRS_ISR_SYNCERR ((uint32_t)0x00000100U) /* SYNC error */ -#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200U) /* SYNC missed */ -#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400U) /* Trimming overflow or underflow */ -#define CRS_ISR_FEDIR ((uint32_t)0x00008000U) /* Frequency error direction */ -#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000U) /* Frequency error capture */ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */ /******************* Bit definition for CRS_ICR register *********************/ -#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001U) /* SYNC event OK clear flag */ -#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002U) /* SYNC warning clear flag */ -#define CRS_ICR_ERRC ((uint32_t)0x00000004U) /* Error clear flag */ -#define CRS_ICR_ESYNCC ((uint32_t)0x00000008U) /* Expected SYNC clear flag */ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */ /******************************************************************************/ /* */ @@ -1046,45 +1296,71 @@ typedef struct /* Note: No specific macro feature on this device */ /******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((uint32_t)0x00000001U) /*!< DAC channel1 enable */ -#define DAC_CR_BOFF1 ((uint32_t)0x00000002U) /*!< DAC channel1 output buffer disable */ -#define DAC_CR_TEN1 ((uint32_t)0x00000004U) /*!< DAC channel1 Trigger enable */ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ +#define DAC_CR_BOFF1_Pos (1U) +#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ +#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */ +#define DAC_CR_TEN1_Pos (2U) +#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ +#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */ -#define DAC_CR_TSEL1 ((uint32_t)0x00000038U) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ -#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ +#define DAC_CR_TSEL1_Pos (3U) +#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ +#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ +#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ +#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ -#define DAC_CR_WAVE1 ((uint32_t)0x000000C0U) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ -#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ +#define DAC_CR_WAVE1_Pos (6U) +#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ +#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ +#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ -#define DAC_CR_MAMP1 ((uint32_t)0x00000F00U) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ -#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */ -#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */ -#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */ -#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800U) /*!< Bit 3 */ +#define DAC_CR_MAMP1_Pos (8U) +#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ +#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ +#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ +#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ +#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ -#define DAC_CR_DMAEN1 ((uint32_t)0x00001000U) /*!< DAC channel1 DMA enable */ -#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA Underrun interrupt enable */ +#define DAC_CR_DMAEN1_Pos (12U) +#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ +#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ +#define DAC_CR_DMAUDRIE1_Pos (13U) +#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ +#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun interrupt enable */ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001U) /*!< DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */ /***************** Bit definition for DAC_DHR12R1 register ******************/ -#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFFU) /*!< DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12R1_DACC1DHR_Pos (0U) +#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ /***************** Bit definition for DAC_DHR12L1 register ******************/ -#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0U) /*!< DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12L1_DACC1DHR_Pos (4U) +#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ /****************** Bit definition for DAC_DHR8R1 register ******************/ -#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FFU) /*!< DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8R1_DACC1DHR_Pos (0U) +#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ /******************* Bit definition for DAC_DOR1 register *******************/ -#define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFFU) /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFFU) /*!< DAC channel1 data output */ /******************** Bit definition for DAC_SR register ********************/ -#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_DMAUDR1_Pos (13U) +#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ +#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ /******************************************************************************/ /* */ @@ -1093,44 +1369,76 @@ typedef struct /******************************************************************************/ /**************** Bit definition for DBGMCU_IDCODE register *****************/ -#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU) /*!< Device Identifier */ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ -#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U) /*!< REV_ID[15:0] bits (Revision Identifier) */ -#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ -#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ -#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000U) /*!< Bit 2 */ -#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000U) /*!< Bit 3 */ -#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000U) /*!< Bit 4 */ -#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000U) /*!< Bit 5 */ -#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000U) /*!< Bit 6 */ -#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000U) /*!< Bit 7 */ -#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000U) /*!< Bit 8 */ -#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000U) /*!< Bit 9 */ -#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000U) /*!< Bit 10 */ -#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000U) /*!< Bit 11 */ -#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000U) /*!< Bit 12 */ -#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000U) /*!< Bit 13 */ -#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000U) /*!< Bit 14 */ -#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000U) /*!< Bit 15 */ +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ +#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ +#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ +#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ +#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ +#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ +#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ +#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ +#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ +#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ +#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ +#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ +#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ +#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ +#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ +#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ +#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ /****************** Bit definition for DBGMCU_CR register *******************/ -#define DBGMCU_CR_DBG ((uint32_t)0x00000007U) /*!< Debug mode mask */ -#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001U) /*!< Debug Sleep Mode */ -#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U) /*!< Debug Stop Mode */ -#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U) /*!< Debug Standby mode */ +#define DBGMCU_CR_DBG_Pos (0U) +#define DBGMCU_CR_DBG_Msk (0x7U << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */ +#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */ +#define DBGMCU_CR_DBG_SLEEP_Pos (0U) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ /****************** Bit definition for DBGMCU_APB1_FZ register **************/ -#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001U) /*!< TIM2 counter stopped when core is halted */ -#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010U) /*!< TIM6 counter stopped when core is halted */ -#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400U) /*!< RTC Calendar frozen when core is halted */ -#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800U) /*!< Debug Window Watchdog stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000U) /*!< Debug Independent Watchdog stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_I2C1_STOP ((uint32_t)0x00200000U) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_I2C2_STOP ((uint32_t)0x00400000U) /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP ((uint32_t)0x80000000U) /*!< LPTIM1 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) +#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) +#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */ +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U) +#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U) +#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */ +#define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U) +#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */ +#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */ /****************** Bit definition for DBGMCU_APB2_FZ register **************/ -#define DBGMCU_APB2_FZ_DBG_TIM22_STOP ((uint32_t)0x00000020U) /*!< TIM22 counter stopped when core is halted */ -#define DBGMCU_APB2_FZ_DBG_TIM21_STOP ((uint32_t)0x00000004U) /*!< TIM21 counter stopped when core is halted */ +#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U) +#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */ +#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U) +#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */ /******************************************************************************/ /* */ @@ -1139,108 +1447,263 @@ typedef struct /******************************************************************************/ /******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error flag */ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ /******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt clear */ -#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error clear */ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ /******************* Bit definition for DMA_CCR register ********************/ -#define DMA_CCR_EN ((uint32_t)0x00000001U) /*!< Channel enable */ -#define DMA_CCR_TCIE ((uint32_t)0x00000002U) /*!< Transfer complete interrupt enable */ -#define DMA_CCR_HTIE ((uint32_t)0x00000004U) /*!< Half Transfer interrupt enable */ -#define DMA_CCR_TEIE ((uint32_t)0x00000008U) /*!< Transfer error interrupt enable */ -#define DMA_CCR_DIR ((uint32_t)0x00000010U) /*!< Data transfer direction */ -#define DMA_CCR_CIRC ((uint32_t)0x00000020U) /*!< Circular mode */ -#define DMA_CCR_PINC ((uint32_t)0x00000040U) /*!< Peripheral increment mode */ -#define DMA_CCR_MINC ((uint32_t)0x00000080U) /*!< Memory increment mode */ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ -#define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */ -#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */ +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ -#define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ -#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ -#define DMA_CCR_PL ((uint32_t)0x00003000U) /*!< PL[1:0] bits(Channel Priority level)*/ -#define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ -#define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ -#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /*!< Memory to memory mode */ +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ /****************** Bit definition for DMA_CNDTR register *******************/ -#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ /****************** Bit definition for DMA_CPAR register ********************/ -#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ /****************** Bit definition for DMA_CMAR register ********************/ -#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ /******************* Bit definition for DMA_CSELR register *******************/ -#define DMA_CSELR_C1S ((uint32_t)0x0000000FU) /*!< Channel 1 Selection */ -#define DMA_CSELR_C2S ((uint32_t)0x000000F0U) /*!< Channel 2 Selection */ -#define DMA_CSELR_C3S ((uint32_t)0x00000F00U) /*!< Channel 3 Selection */ -#define DMA_CSELR_C4S ((uint32_t)0x0000F000U) /*!< Channel 4 Selection */ -#define DMA_CSELR_C5S ((uint32_t)0x000F0000U) /*!< Channel 5 Selection */ -#define DMA_CSELR_C6S ((uint32_t)0x00F00000U) /*!< Channel 6 Selection */ -#define DMA_CSELR_C7S ((uint32_t)0x0F000000U) /*!< Channel 7 Selection */ - +#define DMA_CSELR_C1S_Pos (0U) +#define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */ +#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */ +#define DMA_CSELR_C2S_Pos (4U) +#define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */ +#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */ +#define DMA_CSELR_C3S_Pos (8U) +#define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */ +#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */ +#define DMA_CSELR_C4S_Pos (12U) +#define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */ +#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */ +#define DMA_CSELR_C5S_Pos (16U) +#define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */ +#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */ +#define DMA_CSELR_C6S_Pos (20U) +#define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */ +#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */ +#define DMA_CSELR_C7S_Pos (24U) +#define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */ +#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */ /******************************************************************************/ /* */ @@ -1249,88 +1712,248 @@ typedef struct /******************************************************************************/ /******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_IM0 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_IM1 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_IM2 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_IM3 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_IM4 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_IM5 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_IM6 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_IM7 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_IM8 ((uint32_t)0x00000100U) /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_IM9 ((uint32_t)0x00000200U) /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_IM10 ((uint32_t)0x00000400U) /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_IM11 ((uint32_t)0x00000800U) /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_IM12 ((uint32_t)0x00001000U) /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_IM13 ((uint32_t)0x00002000U) /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_IM14 ((uint32_t)0x00004000U) /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_IM15 ((uint32_t)0x00008000U) /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_IM16 ((uint32_t)0x00010000U) /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_IM17 ((uint32_t)0x00020000U) /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_IM18 ((uint32_t)0x00040000U) /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_IM19 ((uint32_t)0x00080000U) /*!< Interrupt Mask on line 19 */ -#define EXTI_IMR_IM20 ((uint32_t)0x00100000U) /*!< Interrupt Mask on line 20 */ -#define EXTI_IMR_IM21 ((uint32_t)0x00200000U) /*!< Interrupt Mask on line 21 */ -#define EXTI_IMR_IM22 ((uint32_t)0x00400000U) /*!< Interrupt Mask on line 22 */ -#define EXTI_IMR_IM23 ((uint32_t)0x00800000U) /*!< Interrupt Mask on line 23 */ -#define EXTI_IMR_IM25 ((uint32_t)0x02000000U) /*!< Interrupt Mask on line 25 */ -#define EXTI_IMR_IM26 ((uint32_t)0x04000000U) /*!< Interrupt Mask on line 26 */ -#define EXTI_IMR_IM28 ((uint32_t)0x10000000U) /*!< Interrupt Mask on line 28 */ -#define EXTI_IMR_IM29 ((uint32_t)0x20000000U) /*!< Interrupt Mask on line 29 */ +#define EXTI_IMR_IM0_Pos (0U) +#define EXTI_IMR_IM0_Msk (0x1U << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_IM1_Pos (1U) +#define EXTI_IMR_IM1_Msk (0x1U << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_IM2_Pos (2U) +#define EXTI_IMR_IM2_Msk (0x1U << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_IM3_Pos (3U) +#define EXTI_IMR_IM3_Msk (0x1U << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_IM4_Pos (4U) +#define EXTI_IMR_IM4_Msk (0x1U << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_IM5_Pos (5U) +#define EXTI_IMR_IM5_Msk (0x1U << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_IM6_Pos (6U) +#define EXTI_IMR_IM6_Msk (0x1U << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_IM7_Pos (7U) +#define EXTI_IMR_IM7_Msk (0x1U << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_IM8_Pos (8U) +#define EXTI_IMR_IM8_Msk (0x1U << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_IM9_Pos (9U) +#define EXTI_IMR_IM9_Msk (0x1U << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_IM10_Pos (10U) +#define EXTI_IMR_IM10_Msk (0x1U << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_IM11_Pos (11U) +#define EXTI_IMR_IM11_Msk (0x1U << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_IM12_Pos (12U) +#define EXTI_IMR_IM12_Msk (0x1U << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_IM13_Pos (13U) +#define EXTI_IMR_IM13_Msk (0x1U << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_IM14_Pos (14U) +#define EXTI_IMR_IM14_Msk (0x1U << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_IM15_Pos (15U) +#define EXTI_IMR_IM15_Msk (0x1U << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_IM16_Pos (16U) +#define EXTI_IMR_IM16_Msk (0x1U << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_IM17_Pos (17U) +#define EXTI_IMR_IM17_Msk (0x1U << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_IM18_Pos (18U) +#define EXTI_IMR_IM18_Msk (0x1U << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_IM19_Pos (19U) +#define EXTI_IMR_IM19_Msk (0x1U << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR_IM20_Pos (20U) +#define EXTI_IMR_IM20_Msk (0x1U << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */ +#define EXTI_IMR_IM21_Pos (21U) +#define EXTI_IMR_IM21_Msk (0x1U << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */ +#define EXTI_IMR_IM22_Pos (22U) +#define EXTI_IMR_IM22_Msk (0x1U << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */ +#define EXTI_IMR_IM23_Pos (23U) +#define EXTI_IMR_IM23_Msk (0x1U << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR_IM25_Pos (25U) +#define EXTI_IMR_IM25_Msk (0x1U << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR_IM26_Pos (26U) +#define EXTI_IMR_IM26_Msk (0x1U << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */ +#define EXTI_IMR_IM28_Pos (28U) +#define EXTI_IMR_IM28_Msk (0x1U << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */ +#define EXTI_IMR_IM29_Pos (29U) +#define EXTI_IMR_IM29_Msk (0x1U << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */ + +#define EXTI_IMR_IM_Pos (0U) +#define EXTI_IMR_IM_Msk (0x36FFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */ +#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ /****************** Bit definition for EXTI_EMR register ********************/ -#define EXTI_EMR_EM0 ((uint32_t)0x00000001U) /*!< Event Mask on line 0 */ -#define EXTI_EMR_EM1 ((uint32_t)0x00000002U) /*!< Event Mask on line 1 */ -#define EXTI_EMR_EM2 ((uint32_t)0x00000004U) /*!< Event Mask on line 2 */ -#define EXTI_EMR_EM3 ((uint32_t)0x00000008U) /*!< Event Mask on line 3 */ -#define EXTI_EMR_EM4 ((uint32_t)0x00000010U) /*!< Event Mask on line 4 */ -#define EXTI_EMR_EM5 ((uint32_t)0x00000020U) /*!< Event Mask on line 5 */ -#define EXTI_EMR_EM6 ((uint32_t)0x00000040U) /*!< Event Mask on line 6 */ -#define EXTI_EMR_EM7 ((uint32_t)0x00000080U) /*!< Event Mask on line 7 */ -#define EXTI_EMR_EM8 ((uint32_t)0x00000100U) /*!< Event Mask on line 8 */ -#define EXTI_EMR_EM9 ((uint32_t)0x00000200U) /*!< Event Mask on line 9 */ -#define EXTI_EMR_EM10 ((uint32_t)0x00000400U) /*!< Event Mask on line 10 */ -#define EXTI_EMR_EM11 ((uint32_t)0x00000800U) /*!< Event Mask on line 11 */ -#define EXTI_EMR_EM12 ((uint32_t)0x00001000U) /*!< Event Mask on line 12 */ -#define EXTI_EMR_EM13 ((uint32_t)0x00002000U) /*!< Event Mask on line 13 */ -#define EXTI_EMR_EM14 ((uint32_t)0x00004000U) /*!< Event Mask on line 14 */ -#define EXTI_EMR_EM15 ((uint32_t)0x00008000U) /*!< Event Mask on line 15 */ -#define EXTI_EMR_EM16 ((uint32_t)0x00010000U) /*!< Event Mask on line 16 */ -#define EXTI_EMR_EM17 ((uint32_t)0x00020000U) /*!< Event Mask on line 17 */ -#define EXTI_EMR_EM18 ((uint32_t)0x00040000U) /*!< Event Mask on line 18 */ -#define EXTI_EMR_EM19 ((uint32_t)0x00080000U) /*!< Event Mask on line 19 */ -#define EXTI_EMR_EM20 ((uint32_t)0x00100000U) /*!< Event Mask on line 20 */ -#define EXTI_EMR_EM21 ((uint32_t)0x00200000U) /*!< Event Mask on line 21 */ -#define EXTI_EMR_EM22 ((uint32_t)0x00400000U) /*!< Event Mask on line 22 */ -#define EXTI_EMR_EM23 ((uint32_t)0x00800000U) /*!< Event Mask on line 23 */ -#define EXTI_EMR_EM25 ((uint32_t)0x02000000U) /*!< Event Mask on line 25 */ -#define EXTI_EMR_EM26 ((uint32_t)0x04000000U) /*!< Event Mask on line 26 */ -#define EXTI_EMR_EM28 ((uint32_t)0x10000000U) /*!< Event Mask on line 28 */ -#define EXTI_EMR_EM29 ((uint32_t)0x20000000U) /*!< Event Mask on line 29 */ +#define EXTI_EMR_EM0_Pos (0U) +#define EXTI_EMR_EM0_Msk (0x1U << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR_EM1_Pos (1U) +#define EXTI_EMR_EM1_Msk (0x1U << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR_EM2_Pos (2U) +#define EXTI_EMR_EM2_Msk (0x1U << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR_EM3_Pos (3U) +#define EXTI_EMR_EM3_Msk (0x1U << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR_EM4_Pos (4U) +#define EXTI_EMR_EM4_Msk (0x1U << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR_EM5_Pos (5U) +#define EXTI_EMR_EM5_Msk (0x1U << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR_EM6_Pos (6U) +#define EXTI_EMR_EM6_Msk (0x1U << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR_EM7_Pos (7U) +#define EXTI_EMR_EM7_Msk (0x1U << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR_EM8_Pos (8U) +#define EXTI_EMR_EM8_Msk (0x1U << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR_EM9_Pos (9U) +#define EXTI_EMR_EM9_Msk (0x1U << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR_EM10_Pos (10U) +#define EXTI_EMR_EM10_Msk (0x1U << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR_EM11_Pos (11U) +#define EXTI_EMR_EM11_Msk (0x1U << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR_EM12_Pos (12U) +#define EXTI_EMR_EM12_Msk (0x1U << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR_EM13_Pos (13U) +#define EXTI_EMR_EM13_Msk (0x1U << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR_EM14_Pos (14U) +#define EXTI_EMR_EM14_Msk (0x1U << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR_EM15_Pos (15U) +#define EXTI_EMR_EM15_Msk (0x1U << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR_EM16_Pos (16U) +#define EXTI_EMR_EM16_Msk (0x1U << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR_EM17_Pos (17U) +#define EXTI_EMR_EM17_Msk (0x1U << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR_EM18_Pos (18U) +#define EXTI_EMR_EM18_Msk (0x1U << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */ +#define EXTI_EMR_EM19_Pos (19U) +#define EXTI_EMR_EM19_Msk (0x1U << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR_EM20_Pos (20U) +#define EXTI_EMR_EM20_Msk (0x1U << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */ +#define EXTI_EMR_EM21_Pos (21U) +#define EXTI_EMR_EM21_Msk (0x1U << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */ +#define EXTI_EMR_EM22_Pos (22U) +#define EXTI_EMR_EM22_Msk (0x1U << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */ +#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */ +#define EXTI_EMR_EM23_Pos (23U) +#define EXTI_EMR_EM23_Msk (0x1U << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR_EM25_Pos (25U) +#define EXTI_EMR_EM25_Msk (0x1U << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR_EM26_Pos (26U) +#define EXTI_EMR_EM26_Msk (0x1U << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */ +#define EXTI_EMR_EM28_Pos (28U) +#define EXTI_EMR_EM28_Msk (0x1U << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */ +#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */ +#define EXTI_EMR_EM29_Pos (29U) +#define EXTI_EMR_EM29_Msk (0x1U << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */ +#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */ /******************* Bit definition for EXTI_RTSR register ******************/ -#define EXTI_RTSR_RT0 ((uint32_t)0x00000001U) /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_RT1 ((uint32_t)0x00000002U) /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_RT2 ((uint32_t)0x00000004U) /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_RT3 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_RT4 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_RT5 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_RT6 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_RT7 ((uint32_t)0x00000080U) /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_RT8 ((uint32_t)0x00000100U) /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_RT9 ((uint32_t)0x00000200U) /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_RT10 ((uint32_t)0x00000400U) /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_RT11 ((uint32_t)0x00000800U) /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_RT12 ((uint32_t)0x00001000U) /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_RT13 ((uint32_t)0x00002000U) /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_RT14 ((uint32_t)0x00004000U) /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_RT15 ((uint32_t)0x00008000U) /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_RT16 ((uint32_t)0x00010000U) /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_RT17 ((uint32_t)0x00020000U) /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_RT19 ((uint32_t)0x00080000U) /*!< Rising trigger event configuration bit of line 19 */ -#define EXTI_RTSR_RT20 ((uint32_t)0x00100000U) /*!< Rising trigger event configuration bit of line 20 */ -#define EXTI_RTSR_RT21 ((uint32_t)0x00200000U) /*!< Rising trigger event configuration bit of line 21 */ -#define EXTI_RTSR_RT22 ((uint32_t)0x00400000U) /*!< Rising trigger event configuration bit of line 22 */ +#define EXTI_RTSR_RT0_Pos (0U) +#define EXTI_RTSR_RT0_Msk (0x1U << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_RT1_Pos (1U) +#define EXTI_RTSR_RT1_Msk (0x1U << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_RT2_Pos (2U) +#define EXTI_RTSR_RT2_Msk (0x1U << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_RT3_Pos (3U) +#define EXTI_RTSR_RT3_Msk (0x1U << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_RT4_Pos (4U) +#define EXTI_RTSR_RT4_Msk (0x1U << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_RT5_Pos (5U) +#define EXTI_RTSR_RT5_Msk (0x1U << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_RT6_Pos (6U) +#define EXTI_RTSR_RT6_Msk (0x1U << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_RT7_Pos (7U) +#define EXTI_RTSR_RT7_Msk (0x1U << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_RT8_Pos (8U) +#define EXTI_RTSR_RT8_Msk (0x1U << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_RT9_Pos (9U) +#define EXTI_RTSR_RT9_Msk (0x1U << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_RT10_Pos (10U) +#define EXTI_RTSR_RT10_Msk (0x1U << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_RT11_Pos (11U) +#define EXTI_RTSR_RT11_Msk (0x1U << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_RT12_Pos (12U) +#define EXTI_RTSR_RT12_Msk (0x1U << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_RT13_Pos (13U) +#define EXTI_RTSR_RT13_Msk (0x1U << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_RT14_Pos (14U) +#define EXTI_RTSR_RT14_Msk (0x1U << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_RT15_Pos (15U) +#define EXTI_RTSR_RT15_Msk (0x1U << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_RT16_Pos (16U) +#define EXTI_RTSR_RT16_Msk (0x1U << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_RT17_Pos (17U) +#define EXTI_RTSR_RT17_Msk (0x1U << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_RT19_Pos (19U) +#define EXTI_RTSR_RT19_Msk (0x1U << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */ +#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_RTSR_RT20_Pos (20U) +#define EXTI_RTSR_RT20_Msk (0x1U << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */ +#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ +#define EXTI_RTSR_RT21_Pos (21U) +#define EXTI_RTSR_RT21_Msk (0x1U << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */ +#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ +#define EXTI_RTSR_RT22_Pos (22U) +#define EXTI_RTSR_RT22_Msk (0x1U << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */ +#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */ /* Legacy defines */ #define EXTI_RTSR_TR0 EXTI_RTSR_RT0 @@ -1357,28 +1980,72 @@ typedef struct #define EXTI_RTSR_TR22 EXTI_RTSR_RT22 /******************* Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_FT0 ((uint32_t)0x00000001U) /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_FT1 ((uint32_t)0x00000002U) /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_FT2 ((uint32_t)0x00000004U) /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_FT3 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_FT4 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_FT5 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_FT6 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_FT7 ((uint32_t)0x00000080U) /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_FT8 ((uint32_t)0x00000100U) /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_FT9 ((uint32_t)0x00000200U) /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_FT10 ((uint32_t)0x00000400U) /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_FT11 ((uint32_t)0x00000800U) /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_FT12 ((uint32_t)0x00001000U) /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_FT13 ((uint32_t)0x00002000U) /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_FT14 ((uint32_t)0x00004000U) /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_FT15 ((uint32_t)0x00008000U) /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_FT16 ((uint32_t)0x00010000U) /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_FT17 ((uint32_t)0x00020000U) /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_FT19 ((uint32_t)0x00080000U) /*!< Falling trigger event configuration bit of line 19 */ -#define EXTI_FTSR_FT20 ((uint32_t)0x00100000U) /*!< Falling trigger event configuration bit of line 20 */ -#define EXTI_FTSR_FT21 ((uint32_t)0x00200000U) /*!< Falling trigger event configuration bit of line 21 */ -#define EXTI_FTSR_FT22 ((uint32_t)0x00400000U) /*!< Falling trigger event configuration bit of line 22 */ +#define EXTI_FTSR_FT0_Pos (0U) +#define EXTI_FTSR_FT0_Msk (0x1U << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_FT1_Pos (1U) +#define EXTI_FTSR_FT1_Msk (0x1U << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_FT2_Pos (2U) +#define EXTI_FTSR_FT2_Msk (0x1U << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_FT3_Pos (3U) +#define EXTI_FTSR_FT3_Msk (0x1U << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_FT4_Pos (4U) +#define EXTI_FTSR_FT4_Msk (0x1U << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_FT5_Pos (5U) +#define EXTI_FTSR_FT5_Msk (0x1U << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_FT6_Pos (6U) +#define EXTI_FTSR_FT6_Msk (0x1U << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_FT7_Pos (7U) +#define EXTI_FTSR_FT7_Msk (0x1U << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_FT8_Pos (8U) +#define EXTI_FTSR_FT8_Msk (0x1U << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_FT9_Pos (9U) +#define EXTI_FTSR_FT9_Msk (0x1U << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_FT10_Pos (10U) +#define EXTI_FTSR_FT10_Msk (0x1U << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_FT11_Pos (11U) +#define EXTI_FTSR_FT11_Msk (0x1U << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_FT12_Pos (12U) +#define EXTI_FTSR_FT12_Msk (0x1U << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_FT13_Pos (13U) +#define EXTI_FTSR_FT13_Msk (0x1U << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_FT14_Pos (14U) +#define EXTI_FTSR_FT14_Msk (0x1U << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_FT15_Pos (15U) +#define EXTI_FTSR_FT15_Msk (0x1U << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_FT16_Pos (16U) +#define EXTI_FTSR_FT16_Msk (0x1U << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_FT17_Pos (17U) +#define EXTI_FTSR_FT17_Msk (0x1U << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_FT19_Pos (19U) +#define EXTI_FTSR_FT19_Msk (0x1U << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */ +#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_FTSR_FT20_Pos (20U) +#define EXTI_FTSR_FT20_Msk (0x1U << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */ +#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */ +#define EXTI_FTSR_FT21_Pos (21U) +#define EXTI_FTSR_FT21_Msk (0x1U << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */ +#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ +#define EXTI_FTSR_FT22_Pos (22U) +#define EXTI_FTSR_FT22_Msk (0x1U << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */ +#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */ /* Legacy defines */ #define EXTI_FTSR_TR0 EXTI_FTSR_FT0 @@ -1405,28 +2072,72 @@ typedef struct #define EXTI_FTSR_TR22 EXTI_FTSR_FT22 /******************* Bit definition for EXTI_SWIER register *******************/ -#define EXTI_SWIER_SWI0 ((uint32_t)0x00000001U) /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWI1 ((uint32_t)0x00000002U) /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWI2 ((uint32_t)0x00000004U) /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWI3 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWI4 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWI5 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWI6 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWI7 ((uint32_t)0x00000080U) /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWI8 ((uint32_t)0x00000100U) /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWI9 ((uint32_t)0x00000200U) /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWI10 ((uint32_t)0x00000400U) /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWI11 ((uint32_t)0x00000800U) /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWI12 ((uint32_t)0x00001000U) /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWI13 ((uint32_t)0x00002000U) /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWI14 ((uint32_t)0x00004000U) /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWI15 ((uint32_t)0x00008000U) /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWI16 ((uint32_t)0x00010000U) /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWI17 ((uint32_t)0x00020000U) /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWI19 ((uint32_t)0x00080000U) /*!< Software Interrupt on line 19 */ -#define EXTI_SWIER_SWI20 ((uint32_t)0x00100000U) /*!< Software Interrupt on line 20 */ -#define EXTI_SWIER_SWI21 ((uint32_t)0x00200000U) /*!< Software Interrupt on line 21 */ -#define EXTI_SWIER_SWI22 ((uint32_t)0x00400000U) /*!< Software Interrupt on line 22 */ +#define EXTI_SWIER_SWI0_Pos (0U) +#define EXTI_SWIER_SWI0_Msk (0x1U << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWI1_Pos (1U) +#define EXTI_SWIER_SWI1_Msk (0x1U << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWI2_Pos (2U) +#define EXTI_SWIER_SWI2_Msk (0x1U << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWI3_Pos (3U) +#define EXTI_SWIER_SWI3_Msk (0x1U << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWI4_Pos (4U) +#define EXTI_SWIER_SWI4_Msk (0x1U << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWI5_Pos (5U) +#define EXTI_SWIER_SWI5_Msk (0x1U << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWI6_Pos (6U) +#define EXTI_SWIER_SWI6_Msk (0x1U << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWI7_Pos (7U) +#define EXTI_SWIER_SWI7_Msk (0x1U << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWI8_Pos (8U) +#define EXTI_SWIER_SWI8_Msk (0x1U << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWI9_Pos (9U) +#define EXTI_SWIER_SWI9_Msk (0x1U << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWI10_Pos (10U) +#define EXTI_SWIER_SWI10_Msk (0x1U << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWI11_Pos (11U) +#define EXTI_SWIER_SWI11_Msk (0x1U << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWI12_Pos (12U) +#define EXTI_SWIER_SWI12_Msk (0x1U << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWI13_Pos (13U) +#define EXTI_SWIER_SWI13_Msk (0x1U << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWI14_Pos (14U) +#define EXTI_SWIER_SWI14_Msk (0x1U << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWI15_Pos (15U) +#define EXTI_SWIER_SWI15_Msk (0x1U << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWI16_Pos (16U) +#define EXTI_SWIER_SWI16_Msk (0x1U << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWI17_Pos (17U) +#define EXTI_SWIER_SWI17_Msk (0x1U << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWI19_Pos (19U) +#define EXTI_SWIER_SWI19_Msk (0x1U << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */ +#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */ +#define EXTI_SWIER_SWI20_Pos (20U) +#define EXTI_SWIER_SWI20_Msk (0x1U << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */ +#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */ +#define EXTI_SWIER_SWI21_Pos (21U) +#define EXTI_SWIER_SWI21_Msk (0x1U << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */ +#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */ +#define EXTI_SWIER_SWI22_Pos (22U) +#define EXTI_SWIER_SWI22_Msk (0x1U << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */ +#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */ /* Legacy defines */ #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0 @@ -1453,28 +2164,72 @@ typedef struct #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22 /****************** Bit definition for EXTI_PR register *********************/ -#define EXTI_PR_PIF0 ((uint32_t)0x00000001U) /*!< Pending bit 0 */ -#define EXTI_PR_PIF1 ((uint32_t)0x00000002U) /*!< Pending bit 1 */ -#define EXTI_PR_PIF2 ((uint32_t)0x00000004U) /*!< Pending bit 2 */ -#define EXTI_PR_PIF3 ((uint32_t)0x00000008U) /*!< Pending bit 3 */ -#define EXTI_PR_PIF4 ((uint32_t)0x00000010U) /*!< Pending bit 4 */ -#define EXTI_PR_PIF5 ((uint32_t)0x00000020U) /*!< Pending bit 5 */ -#define EXTI_PR_PIF6 ((uint32_t)0x00000040U) /*!< Pending bit 6 */ -#define EXTI_PR_PIF7 ((uint32_t)0x00000080U) /*!< Pending bit 7 */ -#define EXTI_PR_PIF8 ((uint32_t)0x00000100U) /*!< Pending bit 8 */ -#define EXTI_PR_PIF9 ((uint32_t)0x00000200U) /*!< Pending bit 9 */ -#define EXTI_PR_PIF10 ((uint32_t)0x00000400U) /*!< Pending bit 10 */ -#define EXTI_PR_PIF11 ((uint32_t)0x00000800U) /*!< Pending bit 11 */ -#define EXTI_PR_PIF12 ((uint32_t)0x00001000U) /*!< Pending bit 12 */ -#define EXTI_PR_PIF13 ((uint32_t)0x00002000U) /*!< Pending bit 13 */ -#define EXTI_PR_PIF14 ((uint32_t)0x00004000U) /*!< Pending bit 14 */ -#define EXTI_PR_PIF15 ((uint32_t)0x00008000U) /*!< Pending bit 15 */ -#define EXTI_PR_PIF16 ((uint32_t)0x00010000U) /*!< Pending bit 16 */ -#define EXTI_PR_PIF17 ((uint32_t)0x00020000U) /*!< Pending bit 17 */ -#define EXTI_PR_PIF19 ((uint32_t)0x00080000U) /*!< Pending bit 19 */ -#define EXTI_PR_PIF20 ((uint32_t)0x00100000U) /*!< Pending bit 20 */ -#define EXTI_PR_PIF21 ((uint32_t)0x00200000U) /*!< Pending bit 21 */ -#define EXTI_PR_PIF22 ((uint32_t)0x00400000U) /*!< Pending bit 22 */ +#define EXTI_PR_PIF0_Pos (0U) +#define EXTI_PR_PIF0_Msk (0x1U << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */ +#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */ +#define EXTI_PR_PIF1_Pos (1U) +#define EXTI_PR_PIF1_Msk (0x1U << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */ +#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */ +#define EXTI_PR_PIF2_Pos (2U) +#define EXTI_PR_PIF2_Msk (0x1U << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */ +#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */ +#define EXTI_PR_PIF3_Pos (3U) +#define EXTI_PR_PIF3_Msk (0x1U << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */ +#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */ +#define EXTI_PR_PIF4_Pos (4U) +#define EXTI_PR_PIF4_Msk (0x1U << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */ +#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */ +#define EXTI_PR_PIF5_Pos (5U) +#define EXTI_PR_PIF5_Msk (0x1U << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */ +#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */ +#define EXTI_PR_PIF6_Pos (6U) +#define EXTI_PR_PIF6_Msk (0x1U << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */ +#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */ +#define EXTI_PR_PIF7_Pos (7U) +#define EXTI_PR_PIF7_Msk (0x1U << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */ +#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */ +#define EXTI_PR_PIF8_Pos (8U) +#define EXTI_PR_PIF8_Msk (0x1U << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */ +#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */ +#define EXTI_PR_PIF9_Pos (9U) +#define EXTI_PR_PIF9_Msk (0x1U << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */ +#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */ +#define EXTI_PR_PIF10_Pos (10U) +#define EXTI_PR_PIF10_Msk (0x1U << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */ +#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */ +#define EXTI_PR_PIF11_Pos (11U) +#define EXTI_PR_PIF11_Msk (0x1U << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */ +#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */ +#define EXTI_PR_PIF12_Pos (12U) +#define EXTI_PR_PIF12_Msk (0x1U << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */ +#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */ +#define EXTI_PR_PIF13_Pos (13U) +#define EXTI_PR_PIF13_Msk (0x1U << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */ +#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */ +#define EXTI_PR_PIF14_Pos (14U) +#define EXTI_PR_PIF14_Msk (0x1U << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */ +#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */ +#define EXTI_PR_PIF15_Pos (15U) +#define EXTI_PR_PIF15_Msk (0x1U << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */ +#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */ +#define EXTI_PR_PIF16_Pos (16U) +#define EXTI_PR_PIF16_Msk (0x1U << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */ +#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */ +#define EXTI_PR_PIF17_Pos (17U) +#define EXTI_PR_PIF17_Msk (0x1U << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */ +#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */ +#define EXTI_PR_PIF19_Pos (19U) +#define EXTI_PR_PIF19_Msk (0x1U << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */ +#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */ +#define EXTI_PR_PIF20_Pos (20U) +#define EXTI_PR_PIF20_Msk (0x1U << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */ +#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */ +#define EXTI_PR_PIF21_Pos (21U) +#define EXTI_PR_PIF21_Msk (0x1U << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */ +#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */ +#define EXTI_PR_PIF22_Pos (22U) +#define EXTI_PR_PIF22_Msk (0x1U << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */ +#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */ /* Legacy defines */ #define EXTI_PR_PR0 EXTI_PR_PIF0 @@ -1507,52 +2262,118 @@ typedef struct /******************************************************************************/ /******************* Bit definition for FLASH_ACR register ******************/ -#define FLASH_ACR_LATENCY ((uint32_t)0x00000001U) /*!< LATENCY bit (Latency) */ -#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002U) /*!< Prefetch Buffer Enable */ -#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008U) /*!< Flash mode during sleep mode */ -#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010U) /*!< Flash mode during RUN mode */ -#define FLASH_ACR_DISAB_BUF ((uint32_t)0x00000020U) /*!< Disable Buffer */ -#define FLASH_ACR_PRE_READ ((uint32_t)0x00000040U) /*!< Pre-read data address */ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */ +#define FLASH_ACR_PRFTEN_Pos (1U) +#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */ +#define FLASH_ACR_SLEEP_PD_Pos (3U) +#define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */ +#define FLASH_ACR_RUN_PD_Pos (4U) +#define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */ +#define FLASH_ACR_DISAB_BUF_Pos (5U) +#define FLASH_ACR_DISAB_BUF_Msk (0x1U << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */ +#define FLASH_ACR_PRE_READ_Pos (6U) +#define FLASH_ACR_PRE_READ_Msk (0x1U << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */ +#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */ /******************* Bit definition for FLASH_PECR register ******************/ -#define FLASH_PECR_PELOCK ((uint32_t)0x00000001U) /*!< FLASH_PECR and Flash data Lock */ -#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002U) /*!< Program matrix Lock */ -#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004U) /*!< Option byte matrix Lock */ -#define FLASH_PECR_PROG ((uint32_t)0x00000008U) /*!< Program matrix selection */ -#define FLASH_PECR_DATA ((uint32_t)0x00000010U) /*!< Data matrix selection */ -#define FLASH_PECR_FIX ((uint32_t)0x00000100U) /*!< Fixed Time Data write for Word/Half Word/Byte programming */ -#define FLASH_PECR_ERASE ((uint32_t)0x00000200U) /*!< Page erasing mode */ -#define FLASH_PECR_FPRG ((uint32_t)0x00000400U) /*!< Fast Page/Half Page programming mode */ -#define FLASH_PECR_EOPIE ((uint32_t)0x00010000U) /*!< End of programming interrupt */ -#define FLASH_PECR_ERRIE ((uint32_t)0x00020000U) /*!< Error interrupt */ -#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000U) /*!< Launch the option byte loading */ -#define FLASH_PECR_HALF_ARRAY ((uint32_t)0x00080000U) /*!< Half array mode */ +#define FLASH_PECR_PELOCK_Pos (0U) +#define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */ +#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */ +#define FLASH_PECR_PRGLOCK_Pos (1U) +#define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */ +#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */ +#define FLASH_PECR_OPTLOCK_Pos (2U) +#define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */ +#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */ +#define FLASH_PECR_PROG_Pos (3U) +#define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */ +#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */ +#define FLASH_PECR_DATA_Pos (4U) +#define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */ +#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */ +#define FLASH_PECR_FIX_Pos (8U) +#define FLASH_PECR_FIX_Msk (0x1U << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */ +#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */ +#define FLASH_PECR_ERASE_Pos (9U) +#define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */ +#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */ +#define FLASH_PECR_FPRG_Pos (10U) +#define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */ +#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */ +#define FLASH_PECR_EOPIE_Pos (16U) +#define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */ +#define FLASH_PECR_ERRIE_Pos (17U) +#define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */ +#define FLASH_PECR_OBL_LAUNCH_Pos (18U) +#define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */ +#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */ +#define FLASH_PECR_HALF_ARRAY_Pos (19U) +#define FLASH_PECR_HALF_ARRAY_Msk (0x1U << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */ +#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */ /****************** Bit definition for FLASH_PDKEYR register ******************/ -#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */ +#define FLASH_PDKEYR_PDKEYR_Pos (0U) +#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */ /****************** Bit definition for FLASH_PEKEYR register ******************/ -#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */ +#define FLASH_PEKEYR_PEKEYR_Pos (0U) +#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */ /****************** Bit definition for FLASH_PRGKEYR register ******************/ -#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFFU) /*!< Program matrix Key */ +#define FLASH_PRGKEYR_PRGKEYR_Pos (0U) +#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */ /****************** Bit definition for FLASH_OPTKEYR register ******************/ -#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFFU) /*!< Option bytes matrix Key */ +#define FLASH_OPTKEYR_OPTKEYR_Pos (0U) +#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */ /****************** Bit definition for FLASH_SR register *******************/ -#define FLASH_SR_BSY ((uint32_t)0x00000001U) /*!< Busy */ -#define FLASH_SR_EOP ((uint32_t)0x00000002U) /*!< End Of Programming*/ -#define FLASH_SR_HVOFF ((uint32_t)0x00000004U) /*!< End of high voltage */ -#define FLASH_SR_READY ((uint32_t)0x00000008U) /*!< Flash ready after low power mode */ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ +#define FLASH_SR_EOP_Pos (1U) +#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000002 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/ +#define FLASH_SR_HVOFF_Pos (2U) +#define FLASH_SR_HVOFF_Msk (0x1U << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */ +#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */ +#define FLASH_SR_READY_Pos (3U) +#define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /*!< 0x00000008 */ +#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */ -#define FLASH_SR_WRPERR ((uint32_t)0x00000100U) /*!< Write protection error */ -#define FLASH_SR_PGAERR ((uint32_t)0x00000200U) /*!< Programming Alignment Error */ -#define FLASH_SR_SIZERR ((uint32_t)0x00000400U) /*!< Size error */ -#define FLASH_SR_OPTVERR ((uint32_t)0x00000800U) /*!< Option Valid error */ -#define FLASH_SR_RDERR ((uint32_t)0x00002000U) /*!< Read protected error */ -#define FLASH_SR_NOTZEROERR ((uint32_t)0x00010000U) /*!< Not Zero error */ -#define FLASH_SR_FWWERR ((uint32_t)0x00020000U) /*!< Write/Errase operation aborted */ +#define FLASH_SR_WRPERR_Pos (8U) +#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */ +#define FLASH_SR_PGAERR_Pos (9U) +#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */ +#define FLASH_SR_SIZERR_Pos (10U) +#define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ +#define FLASH_SR_OPTVERR_Pos (11U) +#define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */ +#define FLASH_SR_RDERR_Pos (13U) +#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */ +#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */ +#define FLASH_SR_NOTZEROERR_Pos (16U) +#define FLASH_SR_NOTZEROERR_Msk (0x1U << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */ +#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */ +#define FLASH_SR_FWWERR_Pos (17U) +#define FLASH_SR_FWWERR_Msk (0x1U << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */ /* Legacy defines */ #define FLASH_SR_FWWER FLASH_SR_FWWERR @@ -1560,17 +2381,35 @@ typedef struct #define FLASH_SR_ENDHV FLASH_SR_HVOFF /****************** Bit definition for FLASH_OPTR register *******************/ -#define FLASH_OPTR_RDPROT ((uint32_t)0x000000FFU) /*!< Read Protection */ -#define FLASH_OPTR_WPRMOD ((uint32_t)0x00000100U) /*!< Selection of protection mode of WPR bits */ -#define FLASH_OPTR_BOR_LEV ((uint32_t)0x000F0000U) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ -#define FLASH_OPTR_IWDG_SW ((uint32_t)0x00100000U) /*!< IWDG_SW */ -#define FLASH_OPTR_nRST_STOP ((uint32_t)0x00200000U) /*!< nRST_STOP */ -#define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00400000U) /*!< nRST_STDBY */ -#define FLASH_OPTR_USER ((uint32_t)0x00700000U) /*!< User Option Bytes */ -#define FLASH_OPTR_BOOT1 ((uint32_t)0x80000000U) /*!< BOOT1 */ +#define FLASH_OPTR_RDPROT_Pos (0U) +#define FLASH_OPTR_RDPROT_Msk (0xFFU << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */ +#define FLASH_OPTR_WPRMOD_Pos (8U) +#define FLASH_OPTR_WPRMOD_Msk (0x1U << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */ +#define FLASH_OPTR_BOR_LEV_Pos (16U) +#define FLASH_OPTR_BOR_LEV_Msk (0xFU << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ +#define FLASH_OPTR_IWDG_SW_Pos (20U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */ +#define FLASH_OPTR_nRST_STOP_Pos (21U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (22U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_USER_Pos (20U) +#define FLASH_OPTR_USER_Msk (0x7U << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */ +#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */ +#define FLASH_OPTR_BOOT1_Pos (31U) +#define FLASH_OPTR_BOOT1_Msk (0x1U << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */ /****************** Bit definition for FLASH_WRPR register ******************/ -#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFFU) /*!< Write Protection bits */ +#define FLASH_WRPR_WRP_Pos (0U) +#define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */ /******************************************************************************/ /* */ @@ -1578,299 +2417,525 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0 ((uint32_t)0x00000003U) -#define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001U) -#define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002U) -#define GPIO_MODER_MODE1 ((uint32_t)0x0000000CU) -#define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004U) -#define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008U) -#define GPIO_MODER_MODE2 ((uint32_t)0x00000030U) -#define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010U) -#define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020U) -#define GPIO_MODER_MODE3 ((uint32_t)0x000000C0U) -#define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040U) -#define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080U) -#define GPIO_MODER_MODE4 ((uint32_t)0x00000300U) -#define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100U) -#define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200U) -#define GPIO_MODER_MODE5 ((uint32_t)0x00000C00U) -#define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400U) -#define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800U) -#define GPIO_MODER_MODE6 ((uint32_t)0x00003000U) -#define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000U) -#define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000U) -#define GPIO_MODER_MODE7 ((uint32_t)0x0000C000U) -#define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000U) -#define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000U) -#define GPIO_MODER_MODE8 ((uint32_t)0x00030000U) -#define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000U) -#define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000U) -#define GPIO_MODER_MODE9 ((uint32_t)0x000C0000U) -#define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000U) -#define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000U) -#define GPIO_MODER_MODE10 ((uint32_t)0x00300000U) -#define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000U) -#define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000U) -#define GPIO_MODER_MODE11 ((uint32_t)0x00C00000U) -#define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000U) -#define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000U) -#define GPIO_MODER_MODE12 ((uint32_t)0x03000000U) -#define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000U) -#define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000U) -#define GPIO_MODER_MODE13 ((uint32_t)0x0C000000U) -#define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000U) -#define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000U) -#define GPIO_MODER_MODE14 ((uint32_t)0x30000000U) -#define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000U) -#define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000U) -#define GPIO_MODER_MODE15 ((uint32_t)0xC0000000U) -#define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000U) -#define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000U) +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_OTYPER register *****************/ -#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001U) -#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002U) -#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004U) -#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008U) -#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010U) -#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020U) -#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040U) -#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080U) -#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100U) -#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200U) -#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400U) -#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800U) -#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000U) -#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000U) -#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000U) -#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000U) +#define GPIO_OTYPER_OT_0 (0x00000001U) +#define GPIO_OTYPER_OT_1 (0x00000002U) +#define GPIO_OTYPER_OT_2 (0x00000004U) +#define GPIO_OTYPER_OT_3 (0x00000008U) +#define GPIO_OTYPER_OT_4 (0x00000010U) +#define GPIO_OTYPER_OT_5 (0x00000020U) +#define GPIO_OTYPER_OT_6 (0x00000040U) +#define GPIO_OTYPER_OT_7 (0x00000080U) +#define GPIO_OTYPER_OT_8 (0x00000100U) +#define GPIO_OTYPER_OT_9 (0x00000200U) +#define GPIO_OTYPER_OT_10 (0x00000400U) +#define GPIO_OTYPER_OT_11 (0x00000800U) +#define GPIO_OTYPER_OT_12 (0x00001000U) +#define GPIO_OTYPER_OT_13 (0x00002000U) +#define GPIO_OTYPER_OT_14 (0x00004000U) +#define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0 ((uint32_t)0x00000003U) -#define GPIO_OSPEEDER_OSPEED0_0 ((uint32_t)0x00000001U) -#define GPIO_OSPEEDER_OSPEED0_1 ((uint32_t)0x00000002U) -#define GPIO_OSPEEDER_OSPEED1 ((uint32_t)0x0000000CU) -#define GPIO_OSPEEDER_OSPEED1_0 ((uint32_t)0x00000004U) -#define GPIO_OSPEEDER_OSPEED1_1 ((uint32_t)0x00000008U) -#define GPIO_OSPEEDER_OSPEED2 ((uint32_t)0x00000030U) -#define GPIO_OSPEEDER_OSPEED2_0 ((uint32_t)0x00000010U) -#define GPIO_OSPEEDER_OSPEED2_1 ((uint32_t)0x00000020U) -#define GPIO_OSPEEDER_OSPEED3 ((uint32_t)0x000000C0U) -#define GPIO_OSPEEDER_OSPEED3_0 ((uint32_t)0x00000040U) -#define GPIO_OSPEEDER_OSPEED3_1 ((uint32_t)0x00000080U) -#define GPIO_OSPEEDER_OSPEED4 ((uint32_t)0x00000300U) -#define GPIO_OSPEEDER_OSPEED4_0 ((uint32_t)0x00000100U) -#define GPIO_OSPEEDER_OSPEED4_1 ((uint32_t)0x00000200U) -#define GPIO_OSPEEDER_OSPEED5 ((uint32_t)0x00000C00U) -#define GPIO_OSPEEDER_OSPEED5_0 ((uint32_t)0x00000400U) -#define GPIO_OSPEEDER_OSPEED5_1 ((uint32_t)0x00000800U) -#define GPIO_OSPEEDER_OSPEED6 ((uint32_t)0x00003000U) -#define GPIO_OSPEEDER_OSPEED6_0 ((uint32_t)0x00001000U) -#define GPIO_OSPEEDER_OSPEED6_1 ((uint32_t)0x00002000U) -#define GPIO_OSPEEDER_OSPEED7 ((uint32_t)0x0000C000U) -#define GPIO_OSPEEDER_OSPEED7_0 ((uint32_t)0x00004000U) -#define GPIO_OSPEEDER_OSPEED7_1 ((uint32_t)0x00008000U) -#define GPIO_OSPEEDER_OSPEED8 ((uint32_t)0x00030000U) -#define GPIO_OSPEEDER_OSPEED8_0 ((uint32_t)0x00010000U) -#define GPIO_OSPEEDER_OSPEED8_1 ((uint32_t)0x00020000U) -#define GPIO_OSPEEDER_OSPEED9 ((uint32_t)0x000C0000U) -#define GPIO_OSPEEDER_OSPEED9_0 ((uint32_t)0x00040000U) -#define GPIO_OSPEEDER_OSPEED9_1 ((uint32_t)0x00080000U) -#define GPIO_OSPEEDER_OSPEED10 ((uint32_t)0x00300000U) -#define GPIO_OSPEEDER_OSPEED10_0 ((uint32_t)0x00100000U) -#define GPIO_OSPEEDER_OSPEED10_1 ((uint32_t)0x00200000U) -#define GPIO_OSPEEDER_OSPEED11 ((uint32_t)0x00C00000U) -#define GPIO_OSPEEDER_OSPEED11_0 ((uint32_t)0x00400000U) -#define GPIO_OSPEEDER_OSPEED11_1 ((uint32_t)0x00800000U) -#define GPIO_OSPEEDER_OSPEED12 ((uint32_t)0x03000000U) -#define GPIO_OSPEEDER_OSPEED12_0 ((uint32_t)0x01000000U) -#define GPIO_OSPEEDER_OSPEED12_1 ((uint32_t)0x02000000U) -#define GPIO_OSPEEDER_OSPEED13 ((uint32_t)0x0C000000U) -#define GPIO_OSPEEDER_OSPEED13_0 ((uint32_t)0x04000000U) -#define GPIO_OSPEEDER_OSPEED13_1 ((uint32_t)0x08000000U) -#define GPIO_OSPEEDER_OSPEED14 ((uint32_t)0x30000000U) -#define GPIO_OSPEEDER_OSPEED14_0 ((uint32_t)0x10000000U) -#define GPIO_OSPEEDER_OSPEED14_1 ((uint32_t)0x20000000U) -#define GPIO_OSPEEDER_OSPEED15 ((uint32_t)0xC0000000U) -#define GPIO_OSPEEDER_OSPEED15_0 ((uint32_t)0x40000000U) -#define GPIO_OSPEEDER_OSPEED15_1 ((uint32_t)0x80000000U) +#define GPIO_OSPEEDER_OSPEED0_Pos (0U) +#define GPIO_OSPEEDER_OSPEED0_Msk (0x3U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0_0 (0x1U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDER_OSPEED0_1 (0x2U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDER_OSPEED1_Pos (2U) +#define GPIO_OSPEEDER_OSPEED1_Msk (0x3U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1_0 (0x1U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDER_OSPEED1_1 (0x2U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDER_OSPEED2_Pos (4U) +#define GPIO_OSPEEDER_OSPEED2_Msk (0x3U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2_0 (0x1U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDER_OSPEED2_1 (0x2U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDER_OSPEED3_Pos (6U) +#define GPIO_OSPEEDER_OSPEED3_Msk (0x3U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3_0 (0x1U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDER_OSPEED3_1 (0x2U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDER_OSPEED4_Pos (8U) +#define GPIO_OSPEEDER_OSPEED4_Msk (0x3U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4_0 (0x1U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDER_OSPEED4_1 (0x2U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDER_OSPEED5_Pos (10U) +#define GPIO_OSPEEDER_OSPEED5_Msk (0x3U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5_0 (0x1U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDER_OSPEED5_1 (0x2U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDER_OSPEED6_Pos (12U) +#define GPIO_OSPEEDER_OSPEED6_Msk (0x3U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6_0 (0x1U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDER_OSPEED6_1 (0x2U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDER_OSPEED7_Pos (14U) +#define GPIO_OSPEEDER_OSPEED7_Msk (0x3U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7_0 (0x1U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDER_OSPEED7_1 (0x2U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDER_OSPEED8_Pos (16U) +#define GPIO_OSPEEDER_OSPEED8_Msk (0x3U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8_0 (0x1U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDER_OSPEED8_1 (0x2U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDER_OSPEED9_Pos (18U) +#define GPIO_OSPEEDER_OSPEED9_Msk (0x3U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9_0 (0x1U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDER_OSPEED9_1 (0x2U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDER_OSPEED10_Pos (20U) +#define GPIO_OSPEEDER_OSPEED10_Msk (0x3U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10_0 (0x1U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDER_OSPEED10_1 (0x2U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDER_OSPEED11_Pos (22U) +#define GPIO_OSPEEDER_OSPEED11_Msk (0x3U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11_0 (0x1U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDER_OSPEED11_1 (0x2U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDER_OSPEED12_Pos (24U) +#define GPIO_OSPEEDER_OSPEED12_Msk (0x3U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12_0 (0x1U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDER_OSPEED12_1 (0x2U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDER_OSPEED13_Pos (26U) +#define GPIO_OSPEEDER_OSPEED13_Msk (0x3U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13_0 (0x1U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDER_OSPEED13_1 (0x2U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDER_OSPEED14_Pos (28U) +#define GPIO_OSPEEDER_OSPEED14_Msk (0x3U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14_0 (0x1U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDER_OSPEED14_1 (0x2U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDER_OSPEED15_Pos (30U) +#define GPIO_OSPEEDER_OSPEED15_Msk (0x3U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15_0 (0x1U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDER_OSPEED15_1 (0x2U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ /******************* Bit definition for GPIO_PUPDR register ******************/ -#define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003U) -#define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001U) -#define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002U) -#define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000CU) -#define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004U) -#define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008U) -#define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030U) -#define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010U) -#define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020U) -#define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0U) -#define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040U) -#define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080U) -#define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300U) -#define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100U) -#define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200U) -#define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00U) -#define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400U) -#define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800U) -#define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000U) -#define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000U) -#define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000U) -#define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000U) -#define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000U) -#define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000U) -#define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000U) -#define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000U) -#define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000U) -#define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000U) -#define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000U) -#define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000U) -#define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000U) -#define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000U) -#define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000U) -#define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000U) -#define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000U) -#define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000U) -#define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000U) -#define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000U) -#define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000U) -#define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000U) -#define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000U) -#define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000U) -#define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000U) -#define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000U) -#define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000U) -#define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000U) -#define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000U) -#define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000U) +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ /******************* Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0 ((uint32_t)0x00000001U) -#define GPIO_IDR_ID1 ((uint32_t)0x00000002U) -#define GPIO_IDR_ID2 ((uint32_t)0x00000004U) -#define GPIO_IDR_ID3 ((uint32_t)0x00000008U) -#define GPIO_IDR_ID4 ((uint32_t)0x00000010U) -#define GPIO_IDR_ID5 ((uint32_t)0x00000020U) -#define GPIO_IDR_ID6 ((uint32_t)0x00000040U) -#define GPIO_IDR_ID7 ((uint32_t)0x00000080U) -#define GPIO_IDR_ID8 ((uint32_t)0x00000100U) -#define GPIO_IDR_ID9 ((uint32_t)0x00000200U) -#define GPIO_IDR_ID10 ((uint32_t)0x00000400U) -#define GPIO_IDR_ID11 ((uint32_t)0x00000800U) -#define GPIO_IDR_ID12 ((uint32_t)0x00001000U) -#define GPIO_IDR_ID13 ((uint32_t)0x00002000U) -#define GPIO_IDR_ID14 ((uint32_t)0x00004000U) -#define GPIO_IDR_ID15 ((uint32_t)0x00008000U) +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk /****************** Bit definition for GPIO_ODR register ********************/ -#define GPIO_ODR_OD0 ((uint32_t)0x00000001U) -#define GPIO_ODR_OD1 ((uint32_t)0x00000002U) -#define GPIO_ODR_OD2 ((uint32_t)0x00000004U) -#define GPIO_ODR_OD3 ((uint32_t)0x00000008U) -#define GPIO_ODR_OD4 ((uint32_t)0x00000010U) -#define GPIO_ODR_OD5 ((uint32_t)0x00000020U) -#define GPIO_ODR_OD6 ((uint32_t)0x00000040U) -#define GPIO_ODR_OD7 ((uint32_t)0x00000080U) -#define GPIO_ODR_OD8 ((uint32_t)0x00000100U) -#define GPIO_ODR_OD9 ((uint32_t)0x00000200U) -#define GPIO_ODR_OD10 ((uint32_t)0x00000400U) -#define GPIO_ODR_OD11 ((uint32_t)0x00000800U) -#define GPIO_ODR_OD12 ((uint32_t)0x00001000U) -#define GPIO_ODR_OD13 ((uint32_t)0x00002000U) -#define GPIO_ODR_OD14 ((uint32_t)0x00004000U) -#define GPIO_ODR_OD15 ((uint32_t)0x00008000U) +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk /****************** Bit definition for GPIO_BSRR register ********************/ -#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001U) -#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002U) -#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004U) -#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008U) -#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010U) -#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020U) -#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040U) -#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080U) -#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100U) -#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200U) -#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400U) -#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800U) -#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000U) -#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000U) -#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000U) -#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000U) -#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000U) -#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000U) -#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000U) -#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000U) -#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000U) -#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000U) -#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000U) -#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000U) -#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000U) -#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000U) -#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000U) -#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000U) -#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000U) -#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000U) -#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000U) -#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000U) +#define GPIO_BSRR_BS_0 (0x00000001U) +#define GPIO_BSRR_BS_1 (0x00000002U) +#define GPIO_BSRR_BS_2 (0x00000004U) +#define GPIO_BSRR_BS_3 (0x00000008U) +#define GPIO_BSRR_BS_4 (0x00000010U) +#define GPIO_BSRR_BS_5 (0x00000020U) +#define GPIO_BSRR_BS_6 (0x00000040U) +#define GPIO_BSRR_BS_7 (0x00000080U) +#define GPIO_BSRR_BS_8 (0x00000100U) +#define GPIO_BSRR_BS_9 (0x00000200U) +#define GPIO_BSRR_BS_10 (0x00000400U) +#define GPIO_BSRR_BS_11 (0x00000800U) +#define GPIO_BSRR_BS_12 (0x00001000U) +#define GPIO_BSRR_BS_13 (0x00002000U) +#define GPIO_BSRR_BS_14 (0x00004000U) +#define GPIO_BSRR_BS_15 (0x00008000U) +#define GPIO_BSRR_BR_0 (0x00010000U) +#define GPIO_BSRR_BR_1 (0x00020000U) +#define GPIO_BSRR_BR_2 (0x00040000U) +#define GPIO_BSRR_BR_3 (0x00080000U) +#define GPIO_BSRR_BR_4 (0x00100000U) +#define GPIO_BSRR_BR_5 (0x00200000U) +#define GPIO_BSRR_BR_6 (0x00400000U) +#define GPIO_BSRR_BR_7 (0x00800000U) +#define GPIO_BSRR_BR_8 (0x01000000U) +#define GPIO_BSRR_BR_9 (0x02000000U) +#define GPIO_BSRR_BR_10 (0x04000000U) +#define GPIO_BSRR_BR_11 (0x08000000U) +#define GPIO_BSRR_BR_12 (0x10000000U) +#define GPIO_BSRR_BR_13 (0x20000000U) +#define GPIO_BSRR_BR_14 (0x40000000U) +#define GPIO_BSRR_BR_15 (0x80000000U) /****************** Bit definition for GPIO_LCKR register ********************/ -#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U) -#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U) -#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U) -#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U) -#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U) -#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U) -#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U) -#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U) -#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U) -#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U) -#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U) -#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U) -#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U) -#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U) -#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U) -#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U) -#define GPIO_LCKR_LCKK ((uint32_t)0x00010000U) +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000FU) -#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0U) -#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00U) -#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000U) -#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000U) -#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000U) -#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000U) -#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000U) +#define GPIO_AFRL_AFRL0_Pos (0U) +#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk +#define GPIO_AFRL_AFRL1_Pos (4U) +#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk +#define GPIO_AFRL_AFRL2_Pos (8U) +#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk +#define GPIO_AFRL_AFRL3_Pos (12U) +#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk +#define GPIO_AFRL_AFRL4_Pos (16U) +#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk +#define GPIO_AFRL_AFRL5_Pos (20U) +#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk +#define GPIO_AFRL_AFRL6_Pos (24U) +#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk +#define GPIO_AFRL_AFRL7_Pos (28U) +#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000FU) -#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0U) -#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00U) -#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000U) -#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000U) -#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000U) -#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000U) -#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000U) +#define GPIO_AFRH_AFRH0_Pos (0U) +#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk +#define GPIO_AFRH_AFRH1_Pos (4U) +#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk +#define GPIO_AFRH_AFRH2_Pos (8U) +#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk +#define GPIO_AFRH_AFRH3_Pos (12U) +#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk +#define GPIO_AFRH_AFRH4_Pos (16U) +#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk +#define GPIO_AFRH_AFRH5_Pos (20U) +#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk +#define GPIO_AFRH_AFRH6_Pos (24U) +#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk +#define GPIO_AFRH_AFRH7_Pos (28U) +#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk /****************** Bit definition for GPIO_BRR register *********************/ -#define GPIO_BRR_BR_0 ((uint32_t)0x00000001U) -#define GPIO_BRR_BR_1 ((uint32_t)0x00000002U) -#define GPIO_BRR_BR_2 ((uint32_t)0x00000004U) -#define GPIO_BRR_BR_3 ((uint32_t)0x00000008U) -#define GPIO_BRR_BR_4 ((uint32_t)0x00000010U) -#define GPIO_BRR_BR_5 ((uint32_t)0x00000020U) -#define GPIO_BRR_BR_6 ((uint32_t)0x00000040U) -#define GPIO_BRR_BR_7 ((uint32_t)0x00000080U) -#define GPIO_BRR_BR_8 ((uint32_t)0x00000100U) -#define GPIO_BRR_BR_9 ((uint32_t)0x00000200U) -#define GPIO_BRR_BR_10 ((uint32_t)0x00000400U) -#define GPIO_BRR_BR_11 ((uint32_t)0x00000800U) -#define GPIO_BRR_BR_12 ((uint32_t)0x00001000U) -#define GPIO_BRR_BR_13 ((uint32_t)0x00002000U) -#define GPIO_BRR_BR_14 ((uint32_t)0x00004000U) -#define GPIO_BRR_BR_15 ((uint32_t)0x00008000U) +#define GPIO_BRR_BR_0 (0x00000001U) +#define GPIO_BRR_BR_1 (0x00000002U) +#define GPIO_BRR_BR_2 (0x00000004U) +#define GPIO_BRR_BR_3 (0x00000008U) +#define GPIO_BRR_BR_4 (0x00000010U) +#define GPIO_BRR_BR_5 (0x00000020U) +#define GPIO_BRR_BR_6 (0x00000040U) +#define GPIO_BRR_BR_7 (0x00000080U) +#define GPIO_BRR_BR_8 (0x00000100U) +#define GPIO_BRR_BR_9 (0x00000200U) +#define GPIO_BRR_BR_10 (0x00000400U) +#define GPIO_BRR_BR_11 (0x00000800U) +#define GPIO_BRR_BR_12 (0x00001000U) +#define GPIO_BRR_BR_13 (0x00002000U) +#define GPIO_BRR_BR_14 (0x00004000U) +#define GPIO_BRR_BR_15 (0x00008000U) /******************************************************************************/ /* */ @@ -1879,110 +2944,276 @@ typedef struct /******************************************************************************/ /******************* Bit definition for I2C_CR1 register *******************/ -#define I2C_CR1_PE ((uint32_t)0x00000001U) /*!< Peripheral enable */ -#define I2C_CR1_TXIE ((uint32_t)0x00000002U) /*!< TX interrupt enable */ -#define I2C_CR1_RXIE ((uint32_t)0x00000004U) /*!< RX interrupt enable */ -#define I2C_CR1_ADDRIE ((uint32_t)0x00000008U) /*!< Address match interrupt enable */ -#define I2C_CR1_NACKIE ((uint32_t)0x00000010U) /*!< NACK received interrupt enable */ -#define I2C_CR1_STOPIE ((uint32_t)0x00000020U) /*!< STOP detection interrupt enable */ -#define I2C_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transfer complete interrupt enable */ -#define I2C_CR1_ERRIE ((uint32_t)0x00000080U) /*!< Errors interrupt enable */ -#define I2C_CR1_DNF ((uint32_t)0x00000F00U) /*!< Digital noise filter */ -#define I2C_CR1_ANFOFF ((uint32_t)0x00001000U) /*!< Analog noise filter OFF */ -#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000U) /*!< DMA transmission requests enable */ -#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000U) /*!< DMA reception requests enable */ -#define I2C_CR1_SBC ((uint32_t)0x00010000U) /*!< Slave byte control */ -#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000U) /*!< Clock stretching disable */ -#define I2C_CR1_WUPEN ((uint32_t)0x00040000U) /*!< Wakeup from STOP enable */ -#define I2C_CR1_GCEN ((uint32_t)0x00080000U) /*!< General call enable */ -#define I2C_CR1_SMBHEN ((uint32_t)0x00100000U) /*!< SMBus host address enable */ -#define I2C_CR1_SMBDEN ((uint32_t)0x00200000U) /*!< SMBus device default address enable */ -#define I2C_CR1_ALERTEN ((uint32_t)0x00400000U) /*!< SMBus alert enable */ -#define I2C_CR1_PECEN ((uint32_t)0x00800000U) /*!< PEC enable */ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ /****************** Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_SADD ((uint32_t)0x000003FFU) /*!< Slave address (master mode) */ -#define I2C_CR2_RD_WRN ((uint32_t)0x00000400U) /*!< Transfer direction (master mode) */ -#define I2C_CR2_ADD10 ((uint32_t)0x00000800U) /*!< 10-bit addressing mode (master mode) */ -#define I2C_CR2_HEAD10R ((uint32_t)0x00001000U) /*!< 10-bit address header only read direction (master mode) */ -#define I2C_CR2_START ((uint32_t)0x00002000U) /*!< START generation */ -#define I2C_CR2_STOP ((uint32_t)0x00004000U) /*!< STOP generation (master mode) */ -#define I2C_CR2_NACK ((uint32_t)0x00008000U) /*!< NACK generation (slave mode) */ -#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000U) /*!< Number of bytes */ -#define I2C_CR2_RELOAD ((uint32_t)0x01000000U) /*!< NBYTES reload mode */ -#define I2C_CR2_AUTOEND ((uint32_t)0x02000000U) /*!< Automatic end mode (master mode) */ -#define I2C_CR2_PECBYTE ((uint32_t)0x04000000U) /*!< Packet error checking byte */ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ /******************* Bit definition for I2C_OAR1 register ******************/ -#define I2C_OAR1_OA1 ((uint32_t)0x000003FFU) /*!< Interface own address 1 */ -#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400U) /*!< Own address 1 10-bit mode */ -#define I2C_OAR1_OA1EN ((uint32_t)0x00008000U) /*!< Own address 1 enable */ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ /******************* Bit definition for I2C_OAR2 register ******************/ -#define I2C_OAR2_OA2 ((uint32_t)0x000000FEU) /*!< Interface own address 2 */ -#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700U) /*!< Own address 2 masks */ -#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000U) /*!< No mask */ -#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100U) /*!< OA2[1] is masked, Only OA2[7:2] are compared */ -#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200U) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ -#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300U) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ -#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400U) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ -#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500U) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ -#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600U) /*!< OA2[6:1] is masked, Only OA2[7] are compared */ -#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700U) /*!< OA2[7:1] is masked, No comparison is done */ -#define I2C_OAR2_OA2EN ((uint32_t)0x00008000U) /*!< Own address 2 enable */ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ /******************* Bit definition for I2C_TIMINGR register *******************/ -#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FFU) /*!< SCL low period (master mode) */ -#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00U) /*!< SCL high period (master mode) */ -#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000U) /*!< Data hold time */ -#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000U) /*!< Data setup time */ -#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000U) /*!< Timings prescaler */ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ /******************* Bit definition for I2C_TIMEOUTR register *******************/ -#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFFU) /*!< Bus timeout A */ -#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000U) /*!< Idle clock timeout detection */ -#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000U) /*!< Clock timeout enable */ -#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000U) /*!< Bus timeout B*/ -#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000U) /*!< Extended clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ /****************** Bit definition for I2C_ISR register *********************/ -#define I2C_ISR_TXE ((uint32_t)0x00000001U) /*!< Transmit data register empty */ -#define I2C_ISR_TXIS ((uint32_t)0x00000002U) /*!< Transmit interrupt status */ -#define I2C_ISR_RXNE ((uint32_t)0x00000004U) /*!< Receive data register not empty */ -#define I2C_ISR_ADDR ((uint32_t)0x00000008U) /*!< Address matched (slave mode)*/ -#define I2C_ISR_NACKF ((uint32_t)0x00000010U) /*!< NACK received flag */ -#define I2C_ISR_STOPF ((uint32_t)0x00000020U) /*!< STOP detection flag */ -#define I2C_ISR_TC ((uint32_t)0x00000040U) /*!< Transfer complete (master mode) */ -#define I2C_ISR_TCR ((uint32_t)0x00000080U) /*!< Transfer complete reload */ -#define I2C_ISR_BERR ((uint32_t)0x00000100U) /*!< Bus error */ -#define I2C_ISR_ARLO ((uint32_t)0x00000200U) /*!< Arbitration lost */ -#define I2C_ISR_OVR ((uint32_t)0x00000400U) /*!< Overrun/Underrun */ -#define I2C_ISR_PECERR ((uint32_t)0x00000800U) /*!< PEC error in reception */ -#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000U) /*!< Timeout or Tlow detection flag */ -#define I2C_ISR_ALERT ((uint32_t)0x00002000U) /*!< SMBus alert */ -#define I2C_ISR_BUSY ((uint32_t)0x00008000U) /*!< Bus busy */ -#define I2C_ISR_DIR ((uint32_t)0x00010000U) /*!< Transfer direction (slave mode) */ -#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000U) /*!< Address match code (slave mode) */ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ /****************** Bit definition for I2C_ICR register *********************/ -#define I2C_ICR_ADDRCF ((uint32_t)0x00000008U) /*!< Address matched clear flag */ -#define I2C_ICR_NACKCF ((uint32_t)0x00000010U) /*!< NACK clear flag */ -#define I2C_ICR_STOPCF ((uint32_t)0x00000020U) /*!< STOP detection clear flag */ -#define I2C_ICR_BERRCF ((uint32_t)0x00000100U) /*!< Bus error clear flag */ -#define I2C_ICR_ARLOCF ((uint32_t)0x00000200U) /*!< Arbitration lost clear flag */ -#define I2C_ICR_OVRCF ((uint32_t)0x00000400U) /*!< Overrun/Underrun clear flag */ -#define I2C_ICR_PECCF ((uint32_t)0x00000800U) /*!< PAC error clear flag */ -#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000U) /*!< Timeout clear flag */ -#define I2C_ICR_ALERTCF ((uint32_t)0x00002000U) /*!< Alert clear flag */ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ /****************** Bit definition for I2C_PECR register *********************/ -#define I2C_PECR_PEC ((uint32_t)0x000000FFU) /*!< PEC register */ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ /****************** Bit definition for I2C_RXDR register *********************/ -#define I2C_RXDR_RXDATA ((uint32_t)0x000000FFU) /*!< 8-bit receive data */ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ /****************** Bit definition for I2C_TXDR register *********************/ -#define I2C_TXDR_TXDATA ((uint32_t)0x000000FFU) /*!< 8-bit transmit data */ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ /******************************************************************************/ /* */ @@ -1990,24 +3221,38 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_KR_KEY ((uint32_t)0x0000FFFFU) /*!< Key value (write only, read 0000h) */ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ /******************* Bit definition for IWDG_PR register ********************/ -#define IWDG_PR_PR ((uint32_t)0x00000007U) /*!< PR[2:0] (Prescaler divider) */ -#define IWDG_PR_PR_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ -#define IWDG_PR_PR_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ -#define IWDG_PR_PR_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define IWDG_PR_PR_Pos (0U) +#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ +#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */ +#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */ +#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */ /******************* Bit definition for IWDG_RLR register *******************/ -#define IWDG_RLR_RL ((uint32_t)0x00000FFFU) /*!< Watchdog counter reload value */ +#define IWDG_RLR_RL_Pos (0U) +#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ +#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ /******************* Bit definition for IWDG_SR register ********************/ -#define IWDG_SR_PVU ((uint32_t)0x00000001U) /*!< Watchdog prescaler value update */ -#define IWDG_SR_RVU ((uint32_t)0x00000002U) /*!< Watchdog counter reload value update */ -#define IWDG_SR_WVU ((uint32_t)0x00000004U) /*!< Watchdog counter window value update */ +#define IWDG_SR_PVU_Pos (0U) +#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ +#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ +#define IWDG_SR_RVU_Pos (1U) +#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ +#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ +#define IWDG_SR_WVU_Pos (2U) +#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ +#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ /******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_WINR_WIN ((uint32_t)0x00000FFFU) /*!< Watchdog counter window value */ +#define IWDG_WINR_WIN_Pos (0U) +#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ +#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ /******************************************************************************/ /* */ @@ -2016,66 +3261,118 @@ typedef struct /******************************************************************************/ /******************* Bit definition for LCD_CR register *********************/ -#define LCD_CR_LCDEN ((uint32_t)0x00000001U) /*!< LCD Enable Bit */ -#define LCD_CR_VSEL ((uint32_t)0x00000002U) /*!< Voltage source selector Bit */ +#define LCD_CR_LCDEN_Pos (0U) +#define LCD_CR_LCDEN_Msk (0x1U << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */ +#define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */ +#define LCD_CR_VSEL_Pos (1U) +#define LCD_CR_VSEL_Msk (0x1U << LCD_CR_VSEL_Pos) /*!< 0x00000002 */ +#define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */ -#define LCD_CR_DUTY ((uint32_t)0x0000001CU) /*!< DUTY[2:0] bits (Duty selector) */ -#define LCD_CR_DUTY_0 ((uint32_t)0x00000004U) /*!< Duty selector Bit 0 */ -#define LCD_CR_DUTY_1 ((uint32_t)0x00000008U) /*!< Duty selector Bit 1 */ -#define LCD_CR_DUTY_2 ((uint32_t)0x00000010U) /*!< Duty selector Bit 2 */ +#define LCD_CR_DUTY_Pos (2U) +#define LCD_CR_DUTY_Msk (0x7U << LCD_CR_DUTY_Pos) /*!< 0x0000001C */ +#define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */ +#define LCD_CR_DUTY_0 (0x1U << LCD_CR_DUTY_Pos) /*!< 0x00000004 */ +#define LCD_CR_DUTY_1 (0x2U << LCD_CR_DUTY_Pos) /*!< 0x00000008 */ +#define LCD_CR_DUTY_2 (0x4U << LCD_CR_DUTY_Pos) /*!< 0x00000010 */ -#define LCD_CR_BIAS ((uint32_t)0x00000060U) /*!< BIAS[1:0] bits (Bias selector) */ -#define LCD_CR_BIAS_0 ((uint32_t)0x00000020U) /*!< Bias selector Bit 0 */ -#define LCD_CR_BIAS_1 ((uint32_t)0x00000040U) /*!< Bias selector Bit 1 */ +#define LCD_CR_BIAS_Pos (5U) +#define LCD_CR_BIAS_Msk (0x3U << LCD_CR_BIAS_Pos) /*!< 0x00000060 */ +#define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */ +#define LCD_CR_BIAS_0 (0x1U << LCD_CR_BIAS_Pos) /*!< 0x00000020 */ +#define LCD_CR_BIAS_1 (0x2U << LCD_CR_BIAS_Pos) /*!< 0x00000040 */ -#define LCD_CR_MUX_SEG ((uint32_t)0x00000080U) /*!< Mux Segment Enable Bit */ +#define LCD_CR_MUX_SEG_Pos (7U) +#define LCD_CR_MUX_SEG_Msk (0x1U << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */ +#define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */ + +#define LCD_CR_BUFEN_Pos (8U) +#define LCD_CR_BUFEN_Msk (0x1U << LCD_CR_BUFEN_Pos) /*!< 0x00000100 */ +#define LCD_CR_BUFEN LCD_CR_BUFEN_Msk /*!< Voltage output buffer enable Bit */ /******************* Bit definition for LCD_FCR register ********************/ -#define LCD_FCR_HD ((uint32_t)0x00000001U) /*!< High Drive Enable Bit */ -#define LCD_FCR_SOFIE ((uint32_t)0x00000002U) /*!< Start of Frame Interrupt Enable Bit */ -#define LCD_FCR_UDDIE ((uint32_t)0x00000008U) /*!< Update Display Done Interrupt Enable Bit */ +#define LCD_FCR_HD_Pos (0U) +#define LCD_FCR_HD_Msk (0x1U << LCD_FCR_HD_Pos) /*!< 0x00000001 */ +#define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */ +#define LCD_FCR_SOFIE_Pos (1U) +#define LCD_FCR_SOFIE_Msk (0x1U << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */ +#define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */ +#define LCD_FCR_UDDIE_Pos (3U) +#define LCD_FCR_UDDIE_Msk (0x1U << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */ +#define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */ -#define LCD_FCR_PON ((uint32_t)0x00000070U) /*!< PON[2:0] bits (Puls ON Duration) */ -#define LCD_FCR_PON_0 ((uint32_t)0x00000010U) /*!< Bit 0 */ -#define LCD_FCR_PON_1 ((uint32_t)0x00000020U) /*!< Bit 1 */ -#define LCD_FCR_PON_2 ((uint32_t)0x00000040U) /*!< Bit 2 */ +#define LCD_FCR_PON_Pos (4U) +#define LCD_FCR_PON_Msk (0x7U << LCD_FCR_PON_Pos) /*!< 0x00000070 */ +#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */ +#define LCD_FCR_PON_0 (0x1U << LCD_FCR_PON_Pos) /*!< 0x00000010 */ +#define LCD_FCR_PON_1 (0x2U << LCD_FCR_PON_Pos) /*!< 0x00000020 */ +#define LCD_FCR_PON_2 (0x4U << LCD_FCR_PON_Pos) /*!< 0x00000040 */ -#define LCD_FCR_DEAD ((uint32_t)0x00000380U) /*!< DEAD[2:0] bits (DEAD Time) */ -#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080U) /*!< Bit 0 */ -#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100U) /*!< Bit 1 */ -#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200U) /*!< Bit 2 */ +#define LCD_FCR_DEAD_Pos (7U) +#define LCD_FCR_DEAD_Msk (0x7U << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */ +#define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */ +#define LCD_FCR_DEAD_0 (0x1U << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */ +#define LCD_FCR_DEAD_1 (0x2U << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */ +#define LCD_FCR_DEAD_2 (0x4U << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */ -#define LCD_FCR_CC ((uint32_t)0x00001C00U) /*!< CC[2:0] bits (Contrast Control) */ -#define LCD_FCR_CC_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ -#define LCD_FCR_CC_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ -#define LCD_FCR_CC_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define LCD_FCR_CC_Pos (10U) +#define LCD_FCR_CC_Msk (0x7U << LCD_FCR_CC_Pos) /*!< 0x00001C00 */ +#define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */ +#define LCD_FCR_CC_0 (0x1U << LCD_FCR_CC_Pos) /*!< 0x00000400 */ +#define LCD_FCR_CC_1 (0x2U << LCD_FCR_CC_Pos) /*!< 0x00000800 */ +#define LCD_FCR_CC_2 (0x4U << LCD_FCR_CC_Pos) /*!< 0x00001000 */ -#define LCD_FCR_BLINKF ((uint32_t)0x0000E000U) /*!< BLINKF[2:0] bits (Blink Frequency) */ -#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000U) /*!< Bit 0 */ -#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000U) /*!< Bit 1 */ -#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000U) /*!< Bit 2 */ +#define LCD_FCR_BLINKF_Pos (13U) +#define LCD_FCR_BLINKF_Msk (0x7U << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */ +#define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */ +#define LCD_FCR_BLINKF_0 (0x1U << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */ +#define LCD_FCR_BLINKF_1 (0x2U << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */ +#define LCD_FCR_BLINKF_2 (0x4U << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */ -#define LCD_FCR_BLINK ((uint32_t)0x00030000U) /*!< BLINK[1:0] bits (Blink Enable) */ -#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ -#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ +#define LCD_FCR_BLINK_Pos (16U) +#define LCD_FCR_BLINK_Msk (0x3U << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */ +#define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */ +#define LCD_FCR_BLINK_0 (0x1U << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */ +#define LCD_FCR_BLINK_1 (0x2U << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */ -#define LCD_FCR_DIV ((uint32_t)0x003C0000U) /*!< DIV[3:0] bits (Divider) */ -#define LCD_FCR_PS ((uint32_t)0x03C00000U) /*!< PS[3:0] bits (Prescaler) */ +#define LCD_FCR_DIV_Pos (18U) +#define LCD_FCR_DIV_Msk (0xFU << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */ +#define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */ +#define LCD_FCR_PS_Pos (22U) +#define LCD_FCR_PS_Msk (0xFU << LCD_FCR_PS_Pos) /*!< 0x03C00000 */ +#define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */ /******************* Bit definition for LCD_SR register *********************/ -#define LCD_SR_ENS ((uint32_t)0x00000001U) /*!< LCD Enabled Bit */ -#define LCD_SR_SOF ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Bit */ -#define LCD_SR_UDR ((uint32_t)0x00000004U) /*!< Update Display Request Bit */ -#define LCD_SR_UDD ((uint32_t)0x00000008U) /*!< Update Display Done Flag Bit */ -#define LCD_SR_RDY ((uint32_t)0x00000010U) /*!< Ready Flag Bit */ -#define LCD_SR_FCRSR ((uint32_t)0x00000020U) /*!< LCD FCR Register Synchronization Flag Bit */ +#define LCD_SR_ENS_Pos (0U) +#define LCD_SR_ENS_Msk (0x1U << LCD_SR_ENS_Pos) /*!< 0x00000001 */ +#define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */ +#define LCD_SR_SOF_Pos (1U) +#define LCD_SR_SOF_Msk (0x1U << LCD_SR_SOF_Pos) /*!< 0x00000002 */ +#define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */ +#define LCD_SR_UDR_Pos (2U) +#define LCD_SR_UDR_Msk (0x1U << LCD_SR_UDR_Pos) /*!< 0x00000004 */ +#define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */ +#define LCD_SR_UDD_Pos (3U) +#define LCD_SR_UDD_Msk (0x1U << LCD_SR_UDD_Pos) /*!< 0x00000008 */ +#define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */ +#define LCD_SR_RDY_Pos (4U) +#define LCD_SR_RDY_Msk (0x1U << LCD_SR_RDY_Pos) /*!< 0x00000010 */ +#define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */ +#define LCD_SR_FCRSR_Pos (5U) +#define LCD_SR_FCRSR_Msk (0x1U << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */ +#define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */ /******************* Bit definition for LCD_CLR register ********************/ -#define LCD_CLR_SOFC ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Clear Bit */ -#define LCD_CLR_UDDC ((uint32_t)0x00000008U) /*!< Update Display Done Flag Clear Bit */ +#define LCD_CLR_SOFC_Pos (1U) +#define LCD_CLR_SOFC_Msk (0x1U << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */ +#define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */ +#define LCD_CLR_UDDC_Pos (3U) +#define LCD_CLR_UDDC_Msk (0x1U << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */ +#define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */ /******************* Bit definition for LCD_RAM register ********************/ -#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFFU) /*!< Segment Data Bits */ +#define LCD_RAM_SEGMENT_DATA_Pos (0U) +#define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */ +#define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */ /******************************************************************************/ /* */ @@ -2083,81 +3380,161 @@ typedef struct /* */ /******************************************************************************/ /****************** Bit definition for LPTIM_ISR register *******************/ -#define LPTIM_ISR_CMPM ((uint32_t)0x00000001U) /*!< Compare match */ -#define LPTIM_ISR_ARRM ((uint32_t)0x00000002U) /*!< Autoreload match */ -#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004U) /*!< External trigger edge event */ -#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008U) /*!< Compare register update OK */ -#define LPTIM_ISR_ARROK ((uint32_t)0x00000010U) /*!< Autoreload register update OK */ -#define LPTIM_ISR_UP ((uint32_t)0x00000020U) /*!< Counter direction change down to up */ -#define LPTIM_ISR_DOWN ((uint32_t)0x00000040U) /*!< Counter direction change up to down */ +#define LPTIM_ISR_CMPM_Pos (0U) +#define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */ +#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */ +#define LPTIM_ISR_ARRM_Pos (1U) +#define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */ +#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */ +#define LPTIM_ISR_EXTTRIG_Pos (2U) +#define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */ +#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */ +#define LPTIM_ISR_CMPOK_Pos (3U) +#define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */ +#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */ +#define LPTIM_ISR_ARROK_Pos (4U) +#define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */ +#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */ +#define LPTIM_ISR_UP_Pos (5U) +#define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */ +#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */ +#define LPTIM_ISR_DOWN_Pos (6U) +#define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */ +#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */ /****************** Bit definition for LPTIM_ICR register *******************/ -#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001U) /*!< Compare match Clear Flag */ -#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002U) /*!< Autoreload match Clear Flag */ -#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004U) /*!< External trigger edge event Clear Flag */ -#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008U) /*!< Compare register update OK Clear Flag */ -#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010U) /*!< Autoreload register update OK Clear Flag */ -#define LPTIM_ICR_UPCF ((uint32_t)0x00000020U) /*!< Counter direction change down to up Clear Flag */ -#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040U) /*!< Counter direction change up to down Clear Flag */ +#define LPTIM_ICR_CMPMCF_Pos (0U) +#define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */ +#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */ +#define LPTIM_ICR_ARRMCF_Pos (1U) +#define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */ +#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */ +#define LPTIM_ICR_EXTTRIGCF_Pos (2U) +#define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */ +#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */ +#define LPTIM_ICR_CMPOKCF_Pos (3U) +#define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */ +#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */ +#define LPTIM_ICR_ARROKCF_Pos (4U) +#define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */ +#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */ +#define LPTIM_ICR_UPCF_Pos (5U) +#define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */ +#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */ +#define LPTIM_ICR_DOWNCF_Pos (6U) +#define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */ +#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */ /****************** Bit definition for LPTIM_IER register ********************/ -#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001U) /*!< Compare match Interrupt Enable */ -#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002U) /*!< Autoreload match Interrupt Enable */ -#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004U) /*!< External trigger edge event Interrupt Enable */ -#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008U) /*!< Compare register update OK Interrupt Enable */ -#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010U) /*!< Autoreload register update OK Interrupt Enable */ -#define LPTIM_IER_UPIE ((uint32_t)0x00000020U) /*!< Counter direction change down to up Interrupt Enable */ -#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040U) /*!< Counter direction change up to down Interrupt Enable */ +#define LPTIM_IER_CMPMIE_Pos (0U) +#define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */ +#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */ +#define LPTIM_IER_ARRMIE_Pos (1U) +#define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */ +#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */ +#define LPTIM_IER_EXTTRIGIE_Pos (2U) +#define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */ +#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */ +#define LPTIM_IER_CMPOKIE_Pos (3U) +#define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */ +#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */ +#define LPTIM_IER_ARROKIE_Pos (4U) +#define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */ +#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */ +#define LPTIM_IER_UPIE_Pos (5U) +#define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */ +#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */ +#define LPTIM_IER_DOWNIE_Pos (6U) +#define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */ +#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */ /****************** Bit definition for LPTIM_CFGR register *******************/ -#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001U) /*!< Clock selector */ +#define LPTIM_CFGR_CKSEL_Pos (0U) +#define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */ +#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */ -#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006U) /*!< CKPOL[1:0] bits (Clock polarity) */ -#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002U) /*!< Bit 0 */ -#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004U) /*!< Bit 1 */ +#define LPTIM_CFGR_CKPOL_Pos (1U) +#define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */ +#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */ +#define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */ +#define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */ -#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018U) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ -#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ +#define LPTIM_CFGR_CKFLT_Pos (3U) +#define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */ +#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ +#define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */ +#define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */ -#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0U) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ -#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ -#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ +#define LPTIM_CFGR_TRGFLT_Pos (6U) +#define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */ +#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ +#define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */ +#define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */ -#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00U) /*!< PRESC[2:0] bits (Clock prescaler) */ -#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200U) /*!< Bit 0 */ -#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400U) /*!< Bit 1 */ -#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800U) /*!< Bit 2 */ +#define LPTIM_CFGR_PRESC_Pos (9U) +#define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */ +#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */ +#define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */ +#define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */ +#define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */ -#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000U) /*!< TRIGSEL[2:0]] bits (Trigger selector) */ -#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000U) /*!< Bit 0 */ -#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000U) /*!< Bit 1 */ -#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000U) /*!< Bit 2 */ +#define LPTIM_CFGR_TRIGSEL_Pos (13U) +#define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */ +#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */ +#define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */ +#define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */ +#define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */ -#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000U) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ -#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000U) /*!< Bit 0 */ -#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000U) /*!< Bit 1 */ +#define LPTIM_CFGR_TRIGEN_Pos (17U) +#define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */ +#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ +#define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */ +#define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */ -#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000U) /*!< Timout enable */ -#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000U) /*!< Waveform shape */ -#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000U) /*!< Waveform shape polarity */ -#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000U) /*!< Reg update mode */ -#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000U) /*!< Counter mode enable */ -#define LPTIM_CFGR_ENC ((uint32_t)0x01000000U) /*!< Encoder mode enable */ +#define LPTIM_CFGR_TIMOUT_Pos (19U) +#define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */ +#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */ +#define LPTIM_CFGR_WAVE_Pos (20U) +#define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */ +#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */ +#define LPTIM_CFGR_WAVPOL_Pos (21U) +#define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */ +#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */ +#define LPTIM_CFGR_PRELOAD_Pos (22U) +#define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */ +#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */ +#define LPTIM_CFGR_COUNTMODE_Pos (23U) +#define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */ +#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */ +#define LPTIM_CFGR_ENC_Pos (24U) +#define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */ +#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */ /****************** Bit definition for LPTIM_CR register ********************/ -#define LPTIM_CR_ENABLE ((uint32_t)0x00000001U) /*!< LPTIMer enable */ -#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002U) /*!< Timer start in single mode */ -#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004U) /*!< Timer start in continuous mode */ +#define LPTIM_CR_ENABLE_Pos (0U) +#define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */ +#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */ +#define LPTIM_CR_SNGSTRT_Pos (1U) +#define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */ +#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */ +#define LPTIM_CR_CNTSTRT_Pos (2U) +#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */ +#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */ /****************** Bit definition for LPTIM_CMP register *******************/ -#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFFU) /*!< Compare register */ +#define LPTIM_CMP_CMP_Pos (0U) +#define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */ +#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */ /****************** Bit definition for LPTIM_ARR register *******************/ -#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!< Auto reload register */ +#define LPTIM_ARR_ARR_Pos (0U) +#define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */ +#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */ /****************** Bit definition for LPTIM_CNT register *******************/ -#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!< Counter register */ +#define LPTIM_CNT_CNT_Pos (0U) +#define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */ +#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */ /******************************************************************************/ /* */ @@ -2166,17 +3543,35 @@ typedef struct /******************************************************************************/ /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */ -#define FW_CSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Code Segment Start Address */ -#define FW_CSL_LENG ((uint32_t)0x003FFF00U) /*!< Code Segment Length */ -#define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Non Volatile Dat Segment Start Address */ -#define FW_NVDSL_LENG ((uint32_t)0x003FFF00U) /*!< Non Volatile Data Segment Length */ -#define FW_VDSSA_ADD ((uint32_t)0x0000FFC0U) /*!< Volatile Data Segment Start Address */ -#define FW_VDSL_LENG ((uint32_t)0x0000FFC0U) /*!< Volatile Data Segment Length */ +#define FW_CSSA_ADD_Pos (8U) +#define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */ +#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */ +#define FW_CSL_LENG_Pos (8U) +#define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */ +#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */ +#define FW_NVDSSA_ADD_Pos (8U) +#define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */ +#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */ +#define FW_NVDSL_LENG_Pos (8U) +#define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */ +#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */ +#define FW_VDSSA_ADD_Pos (6U) +#define FW_VDSSA_ADD_Msk (0x3FFU << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */ +#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */ +#define FW_VDSL_LENG_Pos (6U) +#define FW_VDSL_LENG_Msk (0x3FFU << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */ +#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */ /**************************Bit definition for CR register *********************/ -#define FW_CR_FPA ((uint32_t)0x00000001U) /*!< Firewall Pre Arm*/ -#define FW_CR_VDS ((uint32_t)0x00000002U) /*!< Volatile Data Sharing*/ -#define FW_CR_VDE ((uint32_t)0x00000004U) /*!< Volatile Data Execution*/ +#define FW_CR_FPA_Pos (0U) +#define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */ +#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/ +#define FW_CR_VDS_Pos (1U) +#define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */ +#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/ +#define FW_CR_VDE_Pos (2U) +#define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */ +#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/ /******************************************************************************/ /* */ @@ -2184,48 +3579,90 @@ typedef struct /* */ /******************************************************************************/ -/******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPSDSR ((uint32_t)0x00000001U) /*!< Low-power deepsleep/sleep/low power run */ -#define PWR_CR_PDDS ((uint32_t)0x00000002U) /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF ((uint32_t)0x00000004U) /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF ((uint32_t)0x00000008U) /*!< Clear Standby Flag */ -#define PWR_CR_PVDE ((uint32_t)0x00000010U) /*!< Power Voltage Detector Enable */ +#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */ -#define PWR_CR_PLS ((uint32_t)0x000000E0U) /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ -#define PWR_CR_PLS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ -#define PWR_CR_PLS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPSDSR_Pos (0U) +#define PWR_CR_LPSDSR_Msk (0x1U << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */ +#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */ +#define PWR_CR_PDDS_Pos (1U) +#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ +#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF_Pos (2U) +#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ +#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF_Pos (3U) +#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ +#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ +#define PWR_CR_PVDE_Pos (4U) +#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS_Pos (5U) +#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ +#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ +#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ +#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ /*!< PVD level configuration */ -#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000U) /*!< PVD level 0 */ -#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020U) /*!< PVD level 1 */ -#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040U) /*!< PVD level 2 */ -#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060U) /*!< PVD level 3 */ -#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080U) /*!< PVD level 4 */ -#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0U) /*!< PVD level 5 */ -#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0U) /*!< PVD level 6 */ -#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0U) /*!< PVD level 7 */ +#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ +#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */ +#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */ +#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */ +#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */ +#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */ +#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */ +#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */ -#define PWR_CR_DBP ((uint32_t)0x00000100U) /*!< Disable Backup Domain write protection */ -#define PWR_CR_ULP ((uint32_t)0x00000200U) /*!< Ultra Low Power mode */ -#define PWR_CR_FWU ((uint32_t)0x00000400U) /*!< Fast wakeup */ +#define PWR_CR_DBP_Pos (8U) +#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ +#define PWR_CR_ULP_Pos (9U) +#define PWR_CR_ULP_Msk (0x1U << PWR_CR_ULP_Pos) /*!< 0x00000200 */ +#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */ +#define PWR_CR_FWU_Pos (10U) +#define PWR_CR_FWU_Msk (0x1U << PWR_CR_FWU_Pos) /*!< 0x00000400 */ +#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */ -#define PWR_CR_VOS ((uint32_t)0x00001800U) /*!< VOS[1:0] bits (Voltage scaling range selection) */ -#define PWR_CR_VOS_0 ((uint32_t)0x00000800U) /*!< Bit 0 */ -#define PWR_CR_VOS_1 ((uint32_t)0x00001000U) /*!< Bit 1 */ -#define PWR_CR_DSEEKOFF ((uint32_t)0x00002000U) /*!< Deep Sleep mode with EEPROM kept Off */ -#define PWR_CR_LPRUN ((uint32_t)0x00004000U) /*!< Low power run mode */ +#define PWR_CR_VOS_Pos (11U) +#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x00001800 */ +#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */ +#define PWR_CR_VOS_0 (0x1U << PWR_CR_VOS_Pos) /*!< 0x00000800 */ +#define PWR_CR_VOS_1 (0x2U << PWR_CR_VOS_Pos) /*!< 0x00001000 */ +#define PWR_CR_DSEEKOFF_Pos (13U) +#define PWR_CR_DSEEKOFF_Msk (0x1U << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */ +#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */ +#define PWR_CR_LPRUN_Pos (14U) +#define PWR_CR_LPRUN_Msk (0x1U << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */ +#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */ /******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint32_t)0x00000001U) /*!< Wakeup Flag */ -#define PWR_CSR_SBF ((uint32_t)0x00000002U) /*!< Standby Flag */ -#define PWR_CSR_PVDO ((uint32_t)0x00000004U) /*!< PVD Output */ -#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008U) /*!< Internal voltage reference (VREFINT) ready flag */ -#define PWR_CSR_VOSF ((uint32_t)0x00000010U) /*!< Voltage Scaling select flag */ -#define PWR_CSR_REGLPF ((uint32_t)0x00000020U) /*!< Regulator LP flag */ +#define PWR_CSR_WUF_Pos (0U) +#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ +#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ +#define PWR_CSR_SBF_Pos (1U) +#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ +#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ +#define PWR_CSR_PVDO_Pos (2U) +#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ +#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ +#define PWR_CSR_VREFINTRDYF_Pos (3U) +#define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */ +#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */ +#define PWR_CSR_VOSF_Pos (4U) +#define PWR_CSR_VOSF_Msk (0x1U << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */ +#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */ +#define PWR_CSR_REGLPF_Pos (5U) +#define PWR_CSR_REGLPF_Msk (0x1U << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */ +#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */ -#define PWR_CSR_EWUP1 ((uint32_t)0x00000100U) /*!< Enable WKUP pin 1 */ -#define PWR_CSR_EWUP2 ((uint32_t)0x00000200U) /*!< Enable WKUP pin 2 */ +#define PWR_CSR_EWUP1_Pos (8U) +#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ +#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ +#define PWR_CSR_EWUP2_Pos (9U) +#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ +#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ /******************************************************************************/ /* */ @@ -2233,173 +3670,274 @@ typedef struct /* */ /******************************************************************************/ +#define RCC_HSI48_SUPPORT /*!< HSI48 feature support */ +#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */ + /******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION ((uint32_t)0x00000001U) /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIKERON ((uint32_t)0x00000002U) /*!< Internal High Speed clock enable for some IPs Kernel */ -#define RCC_CR_HSIRDY ((uint32_t)0x00000004U) /*!< Internal High Speed clock ready flag */ -#define RCC_CR_HSIDIVEN ((uint32_t)0x00000008U) /*!< Internal High Speed clock divider enable */ -#define RCC_CR_HSIDIVF ((uint32_t)0x00000010U) /*!< Internal High Speed clock divider flag */ -#define RCC_CR_MSION ((uint32_t)0x00000100U) /*!< Internal Multi Speed clock enable */ -#define RCC_CR_MSIRDY ((uint32_t)0x00000200U) /*!< Internal Multi Speed clock ready flag */ -#define RCC_CR_HSEON ((uint32_t)0x00010000U) /*!< External High Speed clock enable */ -#define RCC_CR_HSERDY ((uint32_t)0x00020000U) /*!< External High Speed clock ready flag */ -#define RCC_CR_HSEBYP ((uint32_t)0x00040000U) /*!< External High Speed clock Bypass */ -#define RCC_CR_CSSHSEON ((uint32_t)0x00080000U) /*!< HSE Clock Security System enable */ -#define RCC_CR_RTCPRE ((uint32_t)0x00300000U) /*!< RTC/LCD prescaler [1:0] bits */ -#define RCC_CR_RTCPRE_0 ((uint32_t)0x00100000U) /*!< RTC/LCD prescaler Bit 0 */ -#define RCC_CR_RTCPRE_1 ((uint32_t)0x00200000U) /*!< RTC/LCD prescaler Bit 1 */ -#define RCC_CR_PLLON ((uint32_t)0x01000000U) /*!< PLL enable */ -#define RCC_CR_PLLRDY ((uint32_t)0x02000000U) /*!< PLL clock ready flag */ +#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIKERON_Pos (1U) +#define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */ +#define RCC_CR_HSIRDY_Pos (2U) +#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSIDIVEN_Pos (3U) +#define RCC_CR_HSIDIVEN_Msk (0x1U << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */ +#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */ +#define RCC_CR_HSIDIVF_Pos (4U) +#define RCC_CR_HSIDIVF_Msk (0x1U << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */ +#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */ +#define RCC_CR_MSION_Pos (8U) +#define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000100 */ +#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */ +#define RCC_CR_MSIRDY_Pos (9U) +#define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */ +#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSHSEON_Pos (19U) +#define RCC_CR_CSSHSEON_Msk (0x1U << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */ +#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */ +#define RCC_CR_RTCPRE_Pos (20U) +#define RCC_CR_RTCPRE_Msk (0x3U << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */ +#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC/LCD prescaler [1:0] bits */ +#define RCC_CR_RTCPRE_0 (0x1U << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */ +#define RCC_CR_RTCPRE_1 (0x2U << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */ +#define RCC_CR_PLLON_Pos (24U) +#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ +#define RCC_CR_PLLRDY_Pos (25U) +#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ /* Reference defines */ #define RCC_CR_CSSON RCC_CR_CSSHSEON /******************** Bit definition for RCC_ICSCR register *****************/ -#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FFU) /*!< Internal High Speed clock Calibration */ -#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00U) /*!< Internal High Speed clock trimming */ +#define RCC_ICSCR_HSICAL_Pos (0U) +#define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */ +#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ +#define RCC_ICSCR_HSITRIM_Pos (8U) +#define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ -#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000U) /*!< Internal Multi Speed clock Range */ -#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000U) /*!< Internal Multi Speed clock Range 65.536 KHz */ -#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000U) /*!< Internal Multi Speed clock Range 131.072 KHz */ -#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000U) /*!< Internal Multi Speed clock Range 262.144 KHz */ -#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000U) /*!< Internal Multi Speed clock Range 524.288 KHz */ -#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000U) /*!< Internal Multi Speed clock Range 1.048 MHz */ -#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000U) /*!< Internal Multi Speed clock Range 2.097 MHz */ -#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000U) /*!< Internal Multi Speed clock Range 4.194 MHz */ -#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000U) /*!< Internal Multi Speed clock Calibration */ -#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000U) /*!< Internal Multi Speed clock trimming */ +#define RCC_ICSCR_MSIRANGE_Pos (13U) +#define RCC_ICSCR_MSIRANGE_Msk (0x7U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */ +#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */ +#define RCC_ICSCR_MSIRANGE_0 (0x0U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */ +#define RCC_ICSCR_MSIRANGE_1 (0x1U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */ +#define RCC_ICSCR_MSIRANGE_2 (0x2U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */ +#define RCC_ICSCR_MSIRANGE_3 (0x3U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */ +#define RCC_ICSCR_MSIRANGE_4 (0x4U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */ +#define RCC_ICSCR_MSIRANGE_5 (0x5U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */ +#define RCC_ICSCR_MSIRANGE_6 (0x6U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */ +#define RCC_ICSCR_MSICAL_Pos (16U) +#define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */ +#define RCC_ICSCR_MSITRIM_Pos (24U) +#define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */ +#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */ /******************** Bit definition for RCC_CRRCR register *****************/ -#define RCC_CRRCR_HSI48ON ((uint32_t)0x00000001U) /*!< HSI 48MHz clock enable */ -#define RCC_CRRCR_HSI48RDY ((uint32_t)0x00000002U) /*!< HSI 48MHz clock ready flag */ -#define RCC_CRRCR_HSI48CAL ((uint32_t)0x0000FF00U) /*!< HSI 48MHz clock Calibration */ +#define RCC_CRRCR_HSI48ON_Pos (0U) +#define RCC_CRRCR_HSI48ON_Msk (0x1U << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */ +#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk /*!< HSI 48MHz clock enable */ +#define RCC_CRRCR_HSI48RDY_Pos (1U) +#define RCC_CRRCR_HSI48RDY_Msk (0x1U << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */ +#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk /*!< HSI 48MHz clock ready flag */ +#define RCC_CRRCR_HSI48CAL_Pos (8U) +#define RCC_CRRCR_HSI48CAL_Msk (0xFFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF00 */ +#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI 48MHz clock Calibration */ /******************* Bit definition for RCC_CFGR register *******************/ /*!< SW configuration */ -#define RCC_CFGR_SW ((uint32_t)0x00000003U) /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ -#define RCC_CFGR_SW_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ -#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000U) /*!< MSI selected as system clock */ -#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001U) /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002U) /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003U) /*!< PLL selected as system clock */ +#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */ +#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */ /*!< SWS configuration */ -#define RCC_CFGR_SWS ((uint32_t)0x0000000CU) /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004U) /*!< Bit 0 */ -#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008U) /*!< Bit 1 */ +#define RCC_CFGR_SWS_Pos (2U) +#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ +#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ -#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004U) /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008U) /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000CU) /*!< PLL used as system clock */ +#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */ /*!< HPRE configuration */ -#define RCC_CFGR_HPRE ((uint32_t)0x000000F0U) /*!< HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010U) /*!< Bit 0 */ -#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020U) /*!< Bit 1 */ -#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040U) /*!< Bit 2 */ -#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080U) /*!< Bit 3 */ +#define RCC_CFGR_HPRE_Pos (4U) +#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ +#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ +#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ -#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000U) /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080U) /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090U) /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0U) /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0U) /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0U) /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0U) /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0U) /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0U) /*!< SYSCLK divided by 512 */ +#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ /*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700U) /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */ -#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */ -#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */ +#define RCC_CFGR_PPRE1_Pos (8U) +#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ +#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ +#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ +#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ -#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400U) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500U) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600U) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700U) /*!< HCLK divided by 16 */ +#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */ /*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800U) /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800U) /*!< Bit 0 */ -#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000U) /*!< Bit 1 */ -#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000U) /*!< Bit 2 */ +#define RCC_CFGR_PPRE2_Pos (11U) +#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ +#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ +#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ +#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ -#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000U) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800U) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000U) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800U) /*!< HCLK divided by 16 */ +#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */ -#define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000U) /*!< Wake Up from Stop Clock selection */ +#define RCC_CFGR_STOPWUCK_Pos (15U) +#define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */ +#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */ /*!< PLL entry clock source*/ -#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000U) /*!< PLL entry clock source */ +#define RCC_CFGR_PLLSRC_Pos (16U) +#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ +#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ -#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000U) /*!< HSI as PLL entry clock source */ -#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000U) /*!< HSE as PLL entry clock source */ +#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */ +#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */ /*!< PLLMUL configuration */ -#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000U) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ -#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ -#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ -#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000U) /*!< Bit 3 */ +#define RCC_CFGR_PLLMUL_Pos (18U) +#define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ -#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000U) /*!< PLL input clock * 3 */ -#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000U) /*!< PLL input clock * 4 */ -#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000U) /*!< PLL input clock * 6 */ -#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000U) /*!< PLL input clock * 8 */ -#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000U) /*!< PLL input clock * 12 */ -#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000U) /*!< PLL input clock * 16 */ -#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000U) /*!< PLL input clock * 24 */ -#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000U) /*!< PLL input clock * 32 */ -#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000U) /*!< PLL input clock * 48 */ +#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */ +#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */ +#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */ +#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */ +#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */ +#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */ +#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */ +#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */ +#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */ /*!< PLLDIV configuration */ -#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000U) /*!< PLLDIV[1:0] bits (PLL Output Division) */ -#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000U) /*!< Bit0 */ -#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000U) /*!< Bit1 */ +#define RCC_CFGR_PLLDIV_Pos (22U) +#define RCC_CFGR_PLLDIV_Msk (0x3U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */ +#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */ +#define RCC_CFGR_PLLDIV_0 (0x1U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_PLLDIV_1 (0x2U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */ -#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000U) /*!< PLL clock output = CKVCO / 2 */ -#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000U) /*!< PLL clock output = CKVCO / 3 */ -#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000U) /*!< PLL clock output = CKVCO / 4 */ +#define RCC_CFGR_PLLDIV2_Pos (22U) +#define RCC_CFGR_PLLDIV2_Msk (0x1U << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */ +#define RCC_CFGR_PLLDIV3_Pos (23U) +#define RCC_CFGR_PLLDIV3_Msk (0x1U << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */ +#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */ +#define RCC_CFGR_PLLDIV4_Pos (22U) +#define RCC_CFGR_PLLDIV4_Msk (0x3U << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */ +#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */ /*!< MCO configuration */ -#define RCC_CFGR_MCOSEL ((uint32_t)0x0F000000U) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ -#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ -#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ -#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000U) /*!< Bit 2 */ -#define RCC_CFGR_MCOSEL_3 ((uint32_t)0x08000000U) /*!< Bit 3 */ +#define RCC_CFGR_MCOSEL_Pos (24U) +#define RCC_CFGR_MCOSEL_Msk (0xFU << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */ +#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */ +#define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ +#define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */ -#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */ -#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000U) /*!< System clock selected as MCO source */ -#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000U) /*!< Internal 16 MHz RC oscillator clock selected */ -#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000U) /*!< Internal Medium Speed RC oscillator clock selected */ -#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000U) /*!< External 1-25 MHz oscillator clock selected */ -#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000U) /*!< PLL clock divided */ -#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000U) /*!< LSI selected */ -#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000U) /*!< LSE selected */ -#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000U) /*!< HSI48 clock selected as MCO source */ +#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */ +#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U) +#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */ +#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */ +#define RCC_CFGR_MCOSEL_HSI_Pos (25U) +#define RCC_CFGR_MCOSEL_HSI_Msk (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */ +#define RCC_CFGR_MCOSEL_MSI_Pos (24U) +#define RCC_CFGR_MCOSEL_MSI_Msk (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */ +#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */ +#define RCC_CFGR_MCOSEL_HSE_Pos (26U) +#define RCC_CFGR_MCOSEL_HSE_Msk (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */ +#define RCC_CFGR_MCOSEL_PLL_Pos (24U) +#define RCC_CFGR_MCOSEL_PLL_Msk (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */ +#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */ +#define RCC_CFGR_MCOSEL_LSI_Pos (25U) +#define RCC_CFGR_MCOSEL_LSI_Msk (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */ +#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */ +#define RCC_CFGR_MCOSEL_LSE_Pos (24U) +#define RCC_CFGR_MCOSEL_LSE_Msk (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */ +#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */ +#define RCC_CFGR_MCOSEL_HSI48_Pos (27U) +#define RCC_CFGR_MCOSEL_HSI48_Msk (0x1U << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */ +#define RCC_CFGR_MCOSEL_HSI48 RCC_CFGR_MCOSEL_HSI48_Msk /*!< HSI48 clock selected as MCO source */ -#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000U) /*!< MCO prescaler */ -#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */ -#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */ -#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000U) /*!< MCO is divided by 8 */ +#define RCC_CFGR_MCOPRE_Pos (28U) +#define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ +#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */ +#define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ +#define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ -#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000U) /*!< MCO is divided by 1 */ -#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */ -#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */ -#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000U) /*!< MCO is divided by 8 */ -#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000U) /*!< MCO is divided by 16 */ +#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ +#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ +#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ +#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ +#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ /* Legacy defines */ +#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK +#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK +#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI +#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI +#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE +#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL +#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI +#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE +#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48 + #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */ #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */ #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */ @@ -2408,53 +3946,115 @@ typedef struct #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */ /*!<****************** Bit definition for RCC_CIER register ********************/ -#define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Enable */ -#define RCC_CIER_LSERDYIE ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Enable */ -#define RCC_CIER_HSIRDYIE ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Enable */ -#define RCC_CIER_HSERDYIE ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Enable */ -#define RCC_CIER_PLLRDYIE ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Enable */ -#define RCC_CIER_MSIRDYIE ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Enable */ -#define RCC_CIER_HSI48RDYIE ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt Enable */ -#define RCC_CIER_CSSLSE ((uint32_t)0x00000080U) /*!< LSE CSS Interrupt Enable */ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ +#define RCC_CIER_HSIRDYIE_Pos (2U) +#define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ +#define RCC_CIER_HSERDYIE_Pos (3U) +#define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ +#define RCC_CIER_PLLRDYIE_Pos (4U) +#define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ +#define RCC_CIER_MSIRDYIE_Pos (5U) +#define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */ +#define RCC_CIER_HSI48RDYIE_Pos (6U) +#define RCC_CIER_HSI48RDYIE_Msk (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk /*!< HSI48 Ready Interrupt Enable */ +#define RCC_CIER_CSSLSE_Pos (7U) +#define RCC_CIER_CSSLSE_Msk (0x1U << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */ /* Reference defines */ #define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE /*!<****************** Bit definition for RCC_CIFR register ********************/ -#define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt flag */ -#define RCC_CIFR_LSERDYF ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt flag */ -#define RCC_CIFR_HSIRDYF ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt flag */ -#define RCC_CIFR_HSERDYF ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt flag */ -#define RCC_CIFR_PLLRDYF ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt flag */ -#define RCC_CIFR_MSIRDYF ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt flag */ -#define RCC_CIFR_HSI48RDYF ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt flag */ -#define RCC_CIFR_CSSLSEF ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt flag */ -#define RCC_CIFR_CSSHSEF ((uint32_t)0x00000100U) /*!< HSE Clock Security System Interrupt flag */ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ +#define RCC_CIFR_HSIRDYF_Pos (2U) +#define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ +#define RCC_CIFR_HSERDYF_Pos (3U) +#define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ +#define RCC_CIFR_PLLRDYF_Pos (4U) +#define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ +#define RCC_CIFR_MSIRDYF_Pos (5U) +#define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */ +#define RCC_CIFR_HSI48RDYF_Pos (6U) +#define RCC_CIFR_HSI48RDYF_Msk (0x1U << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk /*!< HSI48 Ready Interrupt flag */ +#define RCC_CIFR_CSSLSEF_Pos (7U) +#define RCC_CIFR_CSSLSEF_Msk (0x1U << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */ +#define RCC_CIFR_CSSHSEF_Pos (8U) +#define RCC_CIFR_CSSHSEF_Msk (0x1U << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */ /* Reference defines */ #define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF #define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF /*!<****************** Bit definition for RCC_CICR register ********************/ -#define RCC_CICR_LSIRDYC ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Clear */ -#define RCC_CICR_LSERDYC ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Clear */ -#define RCC_CICR_HSIRDYC ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Clear */ -#define RCC_CICR_HSERDYC ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Clear */ -#define RCC_CICR_PLLRDYC ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Clear */ -#define RCC_CICR_MSIRDYC ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Clear */ -#define RCC_CICR_HSI48RDYC ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt Clear */ -#define RCC_CICR_CSSLSEC ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt Clear */ -#define RCC_CICR_CSSHSEC ((uint32_t)0x00000100U) /*!< HSE Clock Security System Interrupt Clear */ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ +#define RCC_CICR_HSIRDYC_Pos (2U) +#define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ +#define RCC_CICR_HSERDYC_Pos (3U) +#define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ +#define RCC_CICR_PLLRDYC_Pos (4U) +#define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ +#define RCC_CICR_MSIRDYC_Pos (5U) +#define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */ +#define RCC_CICR_HSI48RDYC_Pos (6U) +#define RCC_CICR_HSI48RDYC_Msk (0x1U << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk /*!< HSI48 Ready Interrupt Clear */ +#define RCC_CICR_CSSLSEC_Pos (7U) +#define RCC_CICR_CSSLSEC_Msk (0x1U << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */ +#define RCC_CICR_CSSHSEC_Pos (8U) +#define RCC_CICR_CSSHSEC_Msk (0x1U << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */ /* Reference defines */ #define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC #define RCC_CICR_CSSC RCC_CICR_CSSHSEC /***************** Bit definition for RCC_IOPRSTR register ******************/ -#define RCC_IOPRSTR_IOPARST ((uint32_t)0x00000001U) /*!< GPIO port A reset */ -#define RCC_IOPRSTR_IOPBRST ((uint32_t)0x00000002U) /*!< GPIO port B reset */ -#define RCC_IOPRSTR_IOPCRST ((uint32_t)0x00000004U) /*!< GPIO port C reset */ -#define RCC_IOPRSTR_IOPDRST ((uint32_t)0x00000008U) /*!< GPIO port D reset */ -#define RCC_IOPRSTR_IOPHRST ((uint32_t)0x00000080U) /*!< GPIO port H reset */ +#define RCC_IOPRSTR_IOPARST_Pos (0U) +#define RCC_IOPRSTR_IOPARST_Msk (0x1U << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */ +#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */ +#define RCC_IOPRSTR_IOPBRST_Pos (1U) +#define RCC_IOPRSTR_IOPBRST_Msk (0x1U << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */ +#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */ +#define RCC_IOPRSTR_IOPCRST_Pos (2U) +#define RCC_IOPRSTR_IOPCRST_Msk (0x1U << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */ +#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */ +#define RCC_IOPRSTR_IOPDRST_Pos (3U) +#define RCC_IOPRSTR_IOPDRST_Msk (0x1U << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */ +#define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */ +#define RCC_IOPRSTR_IOPHRST_Pos (7U) +#define RCC_IOPRSTR_IOPHRST_Msk (0x1U << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */ +#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */ /* Reference defines */ #define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */ @@ -2465,50 +4065,112 @@ typedef struct /****************** Bit definition for RCC_AHBRST register ******************/ -#define RCC_AHBRSTR_DMARST ((uint32_t)0x00000001U) /*!< DMA1 reset */ -#define RCC_AHBRSTR_MIFRST ((uint32_t)0x00000100U) /*!< Memory interface reset reset */ -#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000U) /*!< CRC reset */ -#define RCC_AHBRSTR_TSCRST ((uint32_t)0x00010000U) /*!< TSC reset */ -#define RCC_AHBRSTR_RNGRST ((uint32_t)0x00100000U) /*!< RNG reset */ +#define RCC_AHBRSTR_DMARST_Pos (0U) +#define RCC_AHBRSTR_DMARST_Msk (0x1U << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */ +#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */ +#define RCC_AHBRSTR_MIFRST_Pos (8U) +#define RCC_AHBRSTR_MIFRST_Msk (0x1U << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */ +#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset reset */ +#define RCC_AHBRSTR_CRCRST_Pos (12U) +#define RCC_AHBRSTR_CRCRST_Msk (0x1U << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */ +#define RCC_AHBRSTR_TSCRST_Pos (16U) +#define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */ +#define RCC_AHBRSTR_RNGRST_Pos (20U) +#define RCC_AHBRSTR_RNGRST_Msk (0x1U << RCC_AHBRSTR_RNGRST_Pos) /*!< 0x00100000 */ +#define RCC_AHBRSTR_RNGRST RCC_AHBRSTR_RNGRST_Msk /*!< RNG reset */ /* Reference defines */ #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */ /***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001U) /*!< SYSCFG clock reset */ -#define RCC_APB2RSTR_TIM21RST ((uint32_t)0x00000004U) /*!< TIM21 clock reset */ -#define RCC_APB2RSTR_TIM22RST ((uint32_t)0x00000020U) /*!< TIM22 clock reset */ -#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200U) /*!< ADC1 clock reset */ -#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000U) /*!< SPI1 clock reset */ -#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000U) /*!< USART1 clock reset */ -#define RCC_APB2RSTR_DBGRST ((uint32_t)0x00400000U) /*!< DBGMCU clock reset */ +#define RCC_APB2RSTR_SYSCFGRST_Pos (0U) +#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ +#define RCC_APB2RSTR_TIM21RST_Pos (2U) +#define RCC_APB2RSTR_TIM21RST_Msk (0x1U << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 clock reset */ +#define RCC_APB2RSTR_TIM22RST_Pos (5U) +#define RCC_APB2RSTR_TIM22RST_Msk (0x1U << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 clock reset */ +#define RCC_APB2RSTR_ADCRST_Pos (9U) +#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 clock reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ +#define RCC_APB2RSTR_DBGRST_Pos (22U) +#define RCC_APB2RSTR_DBGRST_Msk (0x1U << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU clock reset */ /* Reference defines */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 clock reset */ #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU clock reset */ /***************** Bit definition for RCC_APB1RSTR register *****************/ -#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001U) /*!< Timer 2 clock reset */ -#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010U) /*!< Timer 6 clock reset */ -#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200U) /*!< LCD clock reset */ -#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800U) /*!< Window Watchdog clock reset */ -#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000U) /*!< SPI2 clock reset */ -#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000U) /*!< USART 2 clock reset */ -#define RCC_APB1RSTR_LPUART1RST ((uint32_t)0x00040000U) /*!< LPUART1 clock reset */ -#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000U) /*!< I2C 1 clock reset */ -#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000U) /*!< I2C 2 clock reset */ -#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000U) /*!< USB clock reset */ -#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000U) /*!< CRS clock reset */ -#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000U) /*!< PWR clock reset */ -#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000U) /*!< DAC clock reset */ -#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x80000000U) /*!< LPTIM1 clock reset */ +#define RCC_APB1RSTR_TIM2RST_Pos (0U) +#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ +#define RCC_APB1RSTR_TIM6RST_Pos (4U) +#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */ +#define RCC_APB1RSTR_LCDRST_Pos (9U) +#define RCC_APB1RSTR_LCDRST_Msk (0x1U << RCC_APB1RSTR_LCDRST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTR_LCDRST RCC_APB1RSTR_LCDRST_Msk /*!< LCD clock reset */ +#define RCC_APB1RSTR_WWDGRST_Pos (11U) +#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ +#define RCC_APB1RSTR_SPI2RST_Pos (14U) +#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ +#define RCC_APB1RSTR_USART2RST_Pos (17U) +#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ +#define RCC_APB1RSTR_LPUART1RST_Pos (18U) +#define RCC_APB1RSTR_LPUART1RST_Msk (0x1U << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 clock reset */ +#define RCC_APB1RSTR_I2C1RST_Pos (21U) +#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ +#define RCC_APB1RSTR_I2C2RST_Pos (22U) +#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ +#define RCC_APB1RSTR_USBRST_Pos (23U) +#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB clock reset */ +#define RCC_APB1RSTR_CRSRST_Pos (27U) +#define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS clock reset */ +#define RCC_APB1RSTR_PWRRST_Pos (28U) +#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ +#define RCC_APB1RSTR_DACRST_Pos (29U) +#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC clock reset */ +#define RCC_APB1RSTR_LPTIM1RST_Pos (31U) +#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 clock reset */ /***************** Bit definition for RCC_IOPENR register ******************/ -#define RCC_IOPENR_IOPAEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enable */ -#define RCC_IOPENR_IOPBEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enable */ -#define RCC_IOPENR_IOPCEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enable */ -#define RCC_IOPENR_IOPDEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enable */ -#define RCC_IOPENR_IOPHEN ((uint32_t)0x00000080U) /*!< GPIO port H clock enable */ +#define RCC_IOPENR_IOPAEN_Pos (0U) +#define RCC_IOPENR_IOPAEN_Msk (0x1U << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */ +#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */ +#define RCC_IOPENR_IOPBEN_Pos (1U) +#define RCC_IOPENR_IOPBEN_Msk (0x1U << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */ +#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */ +#define RCC_IOPENR_IOPCEN_Pos (2U) +#define RCC_IOPENR_IOPCEN_Msk (0x1U << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */ +#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */ +#define RCC_IOPENR_IOPDEN_Pos (3U) +#define RCC_IOPENR_IOPDEN_Msk (0x1U << RCC_IOPENR_IOPDEN_Pos) /*!< 0x00000008 */ +#define RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk /*!< GPIO port D clock enable */ +#define RCC_IOPENR_IOPHEN_Pos (7U) +#define RCC_IOPENR_IOPHEN_Msk (0x1U << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */ +#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */ /* Reference defines */ #define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */ @@ -2518,24 +4180,50 @@ typedef struct #define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */ /***************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001U) /*!< DMA1 clock enable */ -#define RCC_AHBENR_MIFEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable bit */ -#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000U) /*!< CRC clock enable */ -#define RCC_AHBENR_TSCEN ((uint32_t)0x00010000U) /*!< TSC clock enable */ -#define RCC_AHBENR_RNGEN ((uint32_t)0x00100000U) /*!< RNG clock enable */ +#define RCC_AHBENR_DMAEN_Pos (0U) +#define RCC_AHBENR_DMAEN_Msk (0x1U << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */ +#define RCC_AHBENR_MIFEN_Pos (8U) +#define RCC_AHBENR_MIFEN_Msk (0x1U << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */ +#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */ +#define RCC_AHBENR_CRCEN_Pos (12U) +#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ +#define RCC_AHBENR_TSCEN_Pos (16U) +#define RCC_AHBENR_TSCEN_Msk (0x1U << RCC_AHBENR_TSCEN_Pos) /*!< 0x00010000 */ +#define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TSC clock enable */ +#define RCC_AHBENR_RNGEN_Pos (20U) +#define RCC_AHBENR_RNGEN_Msk (0x1U << RCC_AHBENR_RNGEN_Pos) /*!< 0x00100000 */ +#define RCC_AHBENR_RNGEN RCC_AHBENR_RNGEN_Msk /*!< RNG clock enable */ /* Reference defines */ #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ /***************** Bit definition for RCC_APB2ENR register ******************/ -#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enable */ -#define RCC_APB2ENR_TIM21EN ((uint32_t)0x00000004U) /*!< TIM21 clock enable */ -#define RCC_APB2ENR_TIM22EN ((uint32_t)0x00000020U) /*!< TIM22 clock enable */ -#define RCC_APB2ENR_FWEN ((uint32_t)0x00000080U) /*!< MiFare Firewall clock enable */ -#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200U) /*!< ADC1 clock enable */ -#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000U) /*!< SPI1 clock enable */ -#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000U) /*!< USART1 clock enable */ -#define RCC_APB2ENR_DBGEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enable */ +#define RCC_APB2ENR_SYSCFGEN_Pos (0U) +#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */ +#define RCC_APB2ENR_TIM21EN_Pos (2U) +#define RCC_APB2ENR_TIM21EN_Msk (0x1U << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */ +#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */ +#define RCC_APB2ENR_TIM22EN_Pos (5U) +#define RCC_APB2ENR_TIM22EN_Msk (0x1U << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */ +#define RCC_APB2ENR_FWEN_Pos (7U) +#define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */ +#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */ +#define RCC_APB2ENR_ADCEN_Pos (9U) +#define RCC_APB2ENR_ADCEN_Msk (0x1U << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */ +#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ +#define RCC_APB2ENR_DBGEN_Pos (22U) +#define RCC_APB2ENR_DBGEN_Msk (0x1U << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */ /* Reference defines */ @@ -2544,27 +4232,65 @@ typedef struct #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */ /***************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001U) /*!< Timer 2 clock enable */ -#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010U) /*!< Timer 6 clock enable */ -#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200U) /*!< LCD clock enable */ -#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enable */ -#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000U) /*!< SPI2 clock enable */ -#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000U) /*!< USART2 clock enable */ -#define RCC_APB1ENR_LPUART1EN ((uint32_t)0x00040000U) /*!< LPUART1 clock enable */ -#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000U) /*!< I2C1 clock enable */ -#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000U) /*!< I2C2 clock enable */ -#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000U) /*!< USB clock enable */ -#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000U) /*!< CRS clock enable */ -#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000U) /*!< PWR clock enable */ -#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000U) /*!< DAC clock enable */ -#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enable */ +#define RCC_APB1ENR_TIM2EN_Pos (0U) +#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */ +#define RCC_APB1ENR_TIM6EN_Pos (4U) +#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ +#define RCC_APB1ENR_LCDEN_Pos (9U) +#define RCC_APB1ENR_LCDEN_Msk (0x1U << RCC_APB1ENR_LCDEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1ENR_LCDEN RCC_APB1ENR_LCDEN_Msk /*!< LCD clock enable */ +#define RCC_APB1ENR_WWDGEN_Pos (11U) +#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_SPI2EN_Pos (14U) +#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */ +#define RCC_APB1ENR_USART2EN_Pos (17U) +#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */ +#define RCC_APB1ENR_LPUART1EN_Pos (18U) +#define RCC_APB1ENR_LPUART1EN_Msk (0x1U << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */ +#define RCC_APB1ENR_I2C1EN_Pos (21U) +#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */ +#define RCC_APB1ENR_I2C2EN_Pos (22U) +#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */ +#define RCC_APB1ENR_USBEN_Pos (23U) +#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */ +#define RCC_APB1ENR_CRSEN_Pos (27U) +#define RCC_APB1ENR_CRSEN_Msk (0x1U << RCC_APB1ENR_CRSEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enable */ +#define RCC_APB1ENR_PWREN_Pos (28U) +#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ +#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */ +#define RCC_APB1ENR_DACEN_Pos (29U) +#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ +#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC clock enable */ +#define RCC_APB1ENR_LPTIM1EN_Pos (31U) +#define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */ /****************** Bit definition for RCC_IOPSMENR register ****************/ -#define RCC_IOPSMENR_IOPASMEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enabled in sleep mode */ -#define RCC_IOPSMENR_IOPBSMEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enabled in sleep mode */ -#define RCC_IOPSMENR_IOPCSMEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enabled in sleep mode */ -#define RCC_IOPSMENR_IOPDSMEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enabled in sleep mode */ -#define RCC_IOPSMENR_IOPHSMEN ((uint32_t)0x00000080U) /*!< GPIO port H clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPASMEN_Pos (0U) +#define RCC_IOPSMENR_IOPASMEN_Msk (0x1U << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */ +#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPBSMEN_Pos (1U) +#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1U << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */ +#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPCSMEN_Pos (2U) +#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1U << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */ +#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPDSMEN_Pos (3U) +#define RCC_IOPSMENR_IOPDSMEN_Msk (0x1U << RCC_IOPSMENR_IOPDSMEN_Pos) /*!< 0x00000008 */ +#define RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk /*!< GPIO port D clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPHSMEN_Pos (7U) +#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1U << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */ +#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */ /* Reference defines */ #define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */ @@ -2574,115 +4300,227 @@ typedef struct #define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */ /***************** Bit definition for RCC_AHBSMENR register ******************/ -#define RCC_AHBSMENR_DMASMEN ((uint32_t)0x00000001U) /*!< DMA1 clock enabled in sleep mode */ -#define RCC_AHBSMENR_MIFSMEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable during sleep mode */ -#define RCC_AHBSMENR_SRAMSMEN ((uint32_t)0x00000200U) /*!< SRAM clock enabled in sleep mode */ -#define RCC_AHBSMENR_CRCSMEN ((uint32_t)0x00001000U) /*!< CRC clock enabled in sleep mode */ -#define RCC_AHBSMENR_TSCSMEN ((uint32_t)0x00010000U) /*!< TSC clock enabled in sleep mode */ -#define RCC_AHBSMENR_RNGSMEN ((uint32_t)0x00100000U) /*!< RNG clock enabled in sleep mode */ +#define RCC_AHBSMENR_DMASMEN_Pos (0U) +#define RCC_AHBSMENR_DMASMEN_Msk (0x1U << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */ +#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */ +#define RCC_AHBSMENR_MIFSMEN_Pos (8U) +#define RCC_AHBSMENR_MIFSMEN_Msk (0x1U << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */ +#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */ +#define RCC_AHBSMENR_SRAMSMEN_Pos (9U) +#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1U << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */ +#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */ +#define RCC_AHBSMENR_CRCSMEN_Pos (12U) +#define RCC_AHBSMENR_CRCSMEN_Msk (0x1U << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */ +#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */ +#define RCC_AHBSMENR_TSCSMEN_Pos (16U) +#define RCC_AHBSMENR_TSCSMEN_Msk (0x1U << RCC_AHBSMENR_TSCSMEN_Pos) /*!< 0x00010000 */ +#define RCC_AHBSMENR_TSCSMEN RCC_AHBSMENR_TSCSMEN_Msk /*!< TSC clock enabled in sleep mode */ +#define RCC_AHBSMENR_RNGSMEN_Pos (20U) +#define RCC_AHBSMENR_RNGSMEN_Msk (0x1U << RCC_AHBSMENR_RNGSMEN_Pos) /*!< 0x00100000 */ +#define RCC_AHBSMENR_RNGSMEN RCC_AHBSMENR_RNGSMEN_Msk /*!< RNG clock enabled in sleep mode */ /* Reference defines */ #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */ /***************** Bit definition for RCC_APB2SMENR register ******************/ -#define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enabled in sleep mode */ -#define RCC_APB2SMENR_TIM21SMEN ((uint32_t)0x00000004U) /*!< TIM21 clock enabled in sleep mode */ -#define RCC_APB2SMENR_TIM22SMEN ((uint32_t)0x00000020U) /*!< TIM22 clock enabled in sleep mode */ -#define RCC_APB2SMENR_ADCSMEN ((uint32_t)0x00000200U) /*!< ADC1 clock enabled in sleep mode */ -#define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000U) /*!< SPI1 clock enabled in sleep mode */ -#define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000U) /*!< USART1 clock enabled in sleep mode */ -#define RCC_APB2SMENR_DBGSMEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enabled in sleep mode */ +#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U) +#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */ +#define RCC_APB2SMENR_TIM21SMEN_Pos (2U) +#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1U << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */ +#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */ +#define RCC_APB2SMENR_TIM22SMEN_Pos (5U) +#define RCC_APB2SMENR_TIM22SMEN_Msk (0x1U << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */ +#define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */ +#define RCC_APB2SMENR_ADCSMEN_Pos (9U) +#define RCC_APB2SMENR_ADCSMEN_Msk (0x1U << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */ +#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */ +#define RCC_APB2SMENR_SPI1SMEN_Pos (12U) +#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */ +#define RCC_APB2SMENR_USART1SMEN_Pos (14U) +#define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk /*!< USART1 clock enabled in sleep mode */ +#define RCC_APB2SMENR_DBGSMEN_Pos (22U) +#define RCC_APB2SMENR_DBGSMEN_Msk (0x1U << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */ /* Reference defines */ #define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */ #define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */ /***************** Bit definition for RCC_APB1SMENR register ******************/ -#define RCC_APB1SMENR_TIM2SMEN ((uint32_t)0x00000001U) /*!< Timer 2 clock enabled in sleep mode */ -#define RCC_APB1SMENR_TIM6SMEN ((uint32_t)0x00000010U) /*!< Timer 6 clock enabled in sleep mode */ -#define RCC_APB1SMENR_LCDSMEN ((uint32_t)0x00000200U) /*!< LCD clock enabled in sleep mode */ -#define RCC_APB1SMENR_WWDGSMEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enabled in sleep mode */ -#define RCC_APB1SMENR_SPI2SMEN ((uint32_t)0x00004000U) /*!< SPI2 clock enabled in sleep mode */ -#define RCC_APB1SMENR_USART2SMEN ((uint32_t)0x00020000U) /*!< USART2 clock enabled in sleep mode */ -#define RCC_APB1SMENR_LPUART1SMEN ((uint32_t)0x00040000U) /*!< LPUART1 clock enabled in sleep mode */ -#define RCC_APB1SMENR_I2C1SMEN ((uint32_t)0x00200000U) /*!< I2C1 clock enabled in sleep mode */ -#define RCC_APB1SMENR_I2C2SMEN ((uint32_t)0x00400000U) /*!< I2C2 clock enabled in sleep mode */ -#define RCC_APB1SMENR_USBSMEN ((uint32_t)0x00800000U) /*!< USB clock enabled in sleep mode */ -#define RCC_APB1SMENR_CRSSMEN ((uint32_t)0x08000000U) /*!< CRS clock enabled in sleep mode */ -#define RCC_APB1SMENR_PWRSMEN ((uint32_t)0x10000000U) /*!< PWR clock enabled in sleep mode */ -#define RCC_APB1SMENR_DACSMEN ((uint32_t)0x20000000U) /*!< DAC clock enabled in sleep mode */ -#define RCC_APB1SMENR_LPTIM1SMEN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enabled in sleep mode */ +#define RCC_APB1SMENR_TIM2SMEN_Pos (0U) +#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */ +#define RCC_APB1SMENR_TIM6SMEN_Pos (4U) +#define RCC_APB1SMENR_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR_TIM6SMEN_Pos) /*!< 0x00000010 */ +#define RCC_APB1SMENR_TIM6SMEN RCC_APB1SMENR_TIM6SMEN_Msk /*!< Timer 6 clock enabled in sleep mode */ +#define RCC_APB1SMENR_LCDSMEN_Pos (9U) +#define RCC_APB1SMENR_LCDSMEN_Msk (0x1U << RCC_APB1SMENR_LCDSMEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1SMENR_LCDSMEN RCC_APB1SMENR_LCDSMEN_Msk /*!< LCD clock enabled in sleep mode */ +#define RCC_APB1SMENR_WWDGSMEN_Pos (11U) +#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */ +#define RCC_APB1SMENR_SPI2SMEN_Pos (14U) +#define RCC_APB1SMENR_SPI2SMEN_Msk (0x1U << RCC_APB1SMENR_SPI2SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1SMENR_SPI2SMEN RCC_APB1SMENR_SPI2SMEN_Msk /*!< SPI2 clock enabled in sleep mode */ +#define RCC_APB1SMENR_USART2SMEN_Pos (17U) +#define RCC_APB1SMENR_USART2SMEN_Msk (0x1U << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */ +#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U) +#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */ +#define RCC_APB1SMENR_I2C1SMEN_Pos (21U) +#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */ +#define RCC_APB1SMENR_I2C2SMEN_Pos (22U) +#define RCC_APB1SMENR_I2C2SMEN_Msk (0x1U << RCC_APB1SMENR_I2C2SMEN_Pos) /*!< 0x00400000 */ +#define RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_Msk /*!< I2C2 clock enabled in sleep mode */ +#define RCC_APB1SMENR_USBSMEN_Pos (23U) +#define RCC_APB1SMENR_USBSMEN_Msk (0x1U << RCC_APB1SMENR_USBSMEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1SMENR_USBSMEN RCC_APB1SMENR_USBSMEN_Msk /*!< USB clock enabled in sleep mode */ +#define RCC_APB1SMENR_CRSSMEN_Pos (27U) +#define RCC_APB1SMENR_CRSSMEN_Msk (0x1U << RCC_APB1SMENR_CRSSMEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1SMENR_CRSSMEN RCC_APB1SMENR_CRSSMEN_Msk /*!< CRS clock enabled in sleep mode */ +#define RCC_APB1SMENR_PWRSMEN_Pos (28U) +#define RCC_APB1SMENR_PWRSMEN_Msk (0x1U << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */ +#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */ +#define RCC_APB1SMENR_DACSMEN_Pos (29U) +#define RCC_APB1SMENR_DACSMEN_Msk (0x1U << RCC_APB1SMENR_DACSMEN_Pos) /*!< 0x20000000 */ +#define RCC_APB1SMENR_DACSMEN RCC_APB1SMENR_DACSMEN_Msk /*!< DAC clock enabled in sleep mode */ +#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U) +#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */ +#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */ /******************* Bit definition for RCC_CCIPR register *******************/ /*!< USART1 Clock source selection */ -#define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003U) /*!< USART1SEL[1:0] bits */ -#define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ -#define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define RCC_CCIPR_USART1SEL_Pos (0U) +#define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk /*!< USART1SEL[1:0] bits */ +#define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */ /*!< USART2 Clock source selection */ -#define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000CU) /*!< USART2SEL[1:0] bits */ -#define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004U) /*!< Bit 0 */ -#define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008U) /*!< Bit 1 */ +#define RCC_CCIPR_USART2SEL_Pos (2U) +#define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */ +#define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */ /*!< LPUART1 Clock source selection */ -#define RCC_CCIPR_LPUART1SEL ((uint32_t)0x0000C00) /*!< LPUART1SEL[1:0] bits */ -#define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x0000400) /*!< Bit 0 */ -#define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x0000800) /*!< Bit 1 */ +#define RCC_CCIPR_LPUART1SEL_Pos (10U) +#define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */ +#define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */ +#define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */ /*!< I2C1 Clock source selection */ -#define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000U) /*!< I2C1SEL [1:0] bits */ -#define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ -#define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define RCC_CCIPR_I2C1SEL_Pos (12U) +#define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */ +#define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */ /*!< LPTIM1 Clock source selection */ -#define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000U) /*!< LPTIM1SEL [1:0] bits */ -#define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ -#define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ +#define RCC_CCIPR_LPTIM1SEL_Pos (18U) +#define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */ +#define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */ /*!< HSI48 Clock source selection */ -#define RCC_CCIPR_HSI48SEL ((uint32_t)0x04000000U) /*!< HSI48 RC clock source selection bit for USB and RNG*/ +#define RCC_CCIPR_HSI48SEL_Pos (26U) +#define RCC_CCIPR_HSI48SEL_Msk (0x1U << RCC_CCIPR_HSI48SEL_Pos) /*!< 0x04000000 */ +#define RCC_CCIPR_HSI48SEL RCC_CCIPR_HSI48SEL_Msk /*!< HSI48 RC clock source selection bit for USB and RNG*/ /* Legacy defines */ #define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL /******************* Bit definition for RCC_CSR register *******************/ -#define RCC_CSR_LSION ((uint32_t)0x00000001U) /*!< Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY ((uint32_t)0x00000002U) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_LSEON ((uint32_t)0x00000100U) /*!< External Low Speed oscillator enable */ -#define RCC_CSR_LSERDY ((uint32_t)0x00000200U) /*!< External Low Speed oscillator Ready */ -#define RCC_CSR_LSEBYP ((uint32_t)0x00000400U) /*!< External Low Speed oscillator Bypass */ +#define RCC_CSR_LSEON_Pos (8U) +#define RCC_CSR_LSEON_Msk (0x1U << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */ +#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */ +#define RCC_CSR_LSERDY_Pos (9U) +#define RCC_CSR_LSERDY_Msk (0x1U << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */ +#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ +#define RCC_CSR_LSEBYP_Pos (10U) +#define RCC_CSR_LSEBYP_Msk (0x1U << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ -#define RCC_CSR_LSEDRV ((uint32_t)0x00001800U) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ -#define RCC_CSR_LSEDRV_0 ((uint32_t)0x00000800U) /*!< Bit 0 */ -#define RCC_CSR_LSEDRV_1 ((uint32_t)0x00001000U) /*!< Bit 1 */ +#define RCC_CSR_LSEDRV_Pos (11U) +#define RCC_CSR_LSEDRV_Msk (0x3U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */ +#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ +#define RCC_CSR_LSEDRV_0 (0x1U << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */ +#define RCC_CSR_LSEDRV_1 (0x2U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */ -#define RCC_CSR_LSECSSON ((uint32_t)0x00002000U) /*!< External Low Speed oscillator CSS Enable */ -#define RCC_CSR_LSECSSD ((uint32_t)0x00004000U) /*!< External Low Speed oscillator CSS Detected */ +#define RCC_CSR_LSECSSON_Pos (13U) +#define RCC_CSR_LSECSSON_Msk (0x1U << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */ +#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */ +#define RCC_CSR_LSECSSD_Pos (14U) +#define RCC_CSR_LSECSSD_Msk (0x1U << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ +#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ /*!< RTC congiguration */ -#define RCC_CSR_RTCSEL ((uint32_t)0x00030000U) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ -#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ +#define RCC_CSR_RTCSEL_Pos (16U) +#define RCC_CSR_RTCSEL_Msk (0x3U << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ +#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_CSR_RTCSEL_0 (0x1U << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */ +#define RCC_CSR_RTCSEL_1 (0x2U << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */ -#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */ -#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000U) /*!< LSE oscillator clock used as RTC clock */ -#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000U) /*!< LSI oscillator clock used as RTC clock */ -#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000U) /*!< HSE oscillator clock used as RTC clock */ +#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ +#define RCC_CSR_RTCSEL_LSE_Pos (16U) +#define RCC_CSR_RTCSEL_LSE_Msk (0x1U << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */ +#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */ +#define RCC_CSR_RTCSEL_LSI_Pos (17U) +#define RCC_CSR_RTCSEL_LSI_Msk (0x1U << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */ +#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */ +#define RCC_CSR_RTCSEL_HSE_Pos (16U) +#define RCC_CSR_RTCSEL_HSE_Msk (0x3U << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */ +#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */ -#define RCC_CSR_RTCEN ((uint32_t)0x00040000U) /*!< RTC clock enable */ -#define RCC_CSR_RTCRST ((uint32_t)0x00080000U) /*!< RTC software reset */ +#define RCC_CSR_RTCEN_Pos (18U) +#define RCC_CSR_RTCEN_Msk (0x1U << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */ +#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */ +#define RCC_CSR_RTCRST_Pos (19U) +#define RCC_CSR_RTCRST_Msk (0x1U << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */ +#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */ -#define RCC_CSR_RMVF ((uint32_t)0x00800000U) /*!< Remove reset flag */ -#define RCC_CSR_FWRSTF ((uint32_t)0x01000000U) /*!< Mifare Firewall reset flag */ -#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000U) /*!< OBL reset flag */ -#define RCC_CSR_PINRSTF ((uint32_t)0x04000000U) /*!< PIN reset flag */ -#define RCC_CSR_PORRSTF ((uint32_t)0x08000000U) /*!< POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000U) /*!< Software Reset flag */ -#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000U) /*!< Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000U) /*!< Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000U) /*!< Low-Power reset flag */ +#define RCC_CSR_RMVF_Pos (23U) +#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_CSR_FWRSTF_Pos (24U) +#define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */ +#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */ +#define RCC_CSR_OBLRSTF_Pos (25U) +#define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ +#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */ +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF_Pos (27U) +#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ /* Reference defines */ #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */ @@ -2694,292 +4532,518 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ -#define RNG_CR_RNGEN ((uint32_t)0x00000004U) -#define RNG_CR_IE ((uint32_t)0x00000008U) +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /******************** Bits definition for RNG_SR register *******************/ -#define RNG_SR_DRDY ((uint32_t)0x00000001U) -#define RNG_SR_CECS ((uint32_t)0x00000002U) -#define RNG_SR_SECS ((uint32_t)0x00000004U) -#define RNG_SR_CEIS ((uint32_t)0x00000020U) -#define RNG_SR_SEIS ((uint32_t)0x00000040U) +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk /******************************************************************************/ /* */ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +/* +* @brief Specific device feature definitions +*/ +#define RTC_TAMPER1_SUPPORT +#define RTC_TAMPER2_SUPPORT +#define RTC_WAKEUP_SUPPORT +#define RTC_BACKUP_SUPPORT + /******************** Bits definition for RTC_TR register *******************/ -#define RTC_TR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_TR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_TR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_TR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_TR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_TR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_TR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_TR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_TR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_TR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_TR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_TR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_TR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_TR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_TR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_TR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_TR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_TR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_TR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_TR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_TR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk /*!< */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk /*!< */ +#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk /*!< */ +#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */ +#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */ +#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk /*!< */ +#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk /*!< */ +#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_DR register *******************/ -#define RTC_DR_YT ((uint32_t)0x00F00000U) /*!< */ -#define RTC_DR_YT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_DR_YT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_DR_YT_2 ((uint32_t)0x00400000U) /*!< */ -#define RTC_DR_YT_3 ((uint32_t)0x00800000U) /*!< */ -#define RTC_DR_YU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_DR_YU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_DR_YU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_DR_YU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_DR_YU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_DR_WDU ((uint32_t)0x0000E000U) /*!< */ -#define RTC_DR_WDU_0 ((uint32_t)0x00002000U) /*!< */ -#define RTC_DR_WDU_1 ((uint32_t)0x00004000U) /*!< */ -#define RTC_DR_WDU_2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_DR_MT ((uint32_t)0x00001000U) /*!< */ -#define RTC_DR_MU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_DR_MU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_DR_MU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_DR_MU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_DR_MU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_DR_DT ((uint32_t)0x00000030U) /*!< */ -#define RTC_DR_DT_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_DR_DT_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_DR_DU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_DR_DU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_DR_DU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_DR_DU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_DR_DU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk /*!< */ +#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk /*!< */ +#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */ +#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk /*!< */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk /*!< */ +#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk /*!< */ +#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk /*!< */ +#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_CR register *******************/ -#define RTC_CR_COE ((uint32_t)0x00800000U) /*!< */ -#define RTC_CR_OSEL ((uint32_t)0x00600000U) /*!< */ -#define RTC_CR_OSEL_0 ((uint32_t)0x00200000U) /*!< */ -#define RTC_CR_OSEL_1 ((uint32_t)0x00400000U) /*!< */ -#define RTC_CR_POL ((uint32_t)0x00100000U) /*!< */ -#define RTC_CR_COSEL ((uint32_t)0x00080000U) /*!< */ -#define RTC_CR_BCK ((uint32_t)0x00040000U) /*!< */ -#define RTC_CR_SUB1H ((uint32_t)0x00020000U) /*!< */ -#define RTC_CR_ADD1H ((uint32_t)0x00010000U) /*!< */ -#define RTC_CR_TSIE ((uint32_t)0x00008000U) /*!< */ -#define RTC_CR_WUTIE ((uint32_t)0x00004000U) /*!< */ -#define RTC_CR_ALRBIE ((uint32_t)0x00002000U) /*!< */ -#define RTC_CR_ALRAIE ((uint32_t)0x00001000U) /*!< */ -#define RTC_CR_TSE ((uint32_t)0x00000800U) /*!< */ -#define RTC_CR_WUTE ((uint32_t)0x00000400U) /*!< */ -#define RTC_CR_ALRBE ((uint32_t)0x00000200U) /*!< */ -#define RTC_CR_ALRAE ((uint32_t)0x00000100U) /*!< */ -#define RTC_CR_FMT ((uint32_t)0x00000040U) /*!< */ -#define RTC_CR_BYPSHAD ((uint32_t)0x00000020U) /*!< */ -#define RTC_CR_REFCKON ((uint32_t)0x00000010U) /*!< */ -#define RTC_CR_TSEDGE ((uint32_t)0x00000008U) /*!< */ -#define RTC_CR_WUCKSEL ((uint32_t)0x00000007U) /*!< */ -#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004U) /*!< */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk /*!< */ +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */ +#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< */ +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */ +#define RTC_CR_BCK_Pos (18U) +#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ +#define RTC_CR_BCK RTC_CR_BCK_Msk /*!< */ +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */ +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */ +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */ +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */ +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */ +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */ +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */ +#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_ISR register ******************/ -#define RTC_ISR_RECALPF ((uint32_t)0x00010000U) /*!< */ -#define RTC_ISR_TAMP2F ((uint32_t)0x00004000U) /*!< */ -#define RTC_ISR_TAMP1F ((uint32_t)0x00002000U) /*!< */ -#define RTC_ISR_TSOVF ((uint32_t)0x00001000U) /*!< */ -#define RTC_ISR_TSF ((uint32_t)0x00000800U) /*!< */ -#define RTC_ISR_WUTF ((uint32_t)0x00000400U) /*!< */ -#define RTC_ISR_ALRBF ((uint32_t)0x00000200U) /*!< */ -#define RTC_ISR_ALRAF ((uint32_t)0x00000100U) /*!< */ -#define RTC_ISR_INIT ((uint32_t)0x00000080U) /*!< */ -#define RTC_ISR_INITF ((uint32_t)0x00000040U) /*!< */ -#define RTC_ISR_RSF ((uint32_t)0x00000020U) /*!< */ -#define RTC_ISR_INITS ((uint32_t)0x00000010U) /*!< */ -#define RTC_ISR_SHPF ((uint32_t)0x00000008U) /*!< */ -#define RTC_ISR_WUTWF ((uint32_t)0x00000004U) /*!< */ -#define RTC_ISR_ALRBWF ((uint32_t)0x00000002U) /*!< */ -#define RTC_ISR_ALRAWF ((uint32_t)0x00000001U) /*!< */ +#define RTC_ISR_RECALPF_Pos (16U) +#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */ +#define RTC_ISR_TAMP2F_Pos (14U) +#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ +#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */ +#define RTC_ISR_TAMP1F_Pos (13U) +#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ +#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */ +#define RTC_ISR_TSOVF_Pos (12U) +#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ +#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */ +#define RTC_ISR_TSF_Pos (11U) +#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ +#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */ +#define RTC_ISR_WUTF_Pos (10U) +#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ +#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */ +#define RTC_ISR_ALRBF_Pos (9U) +#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ +#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */ +#define RTC_ISR_ALRAF_Pos (8U) +#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ +#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */ +#define RTC_ISR_INIT_Pos (7U) +#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */ +#define RTC_ISR_INITF_Pos (6U) +#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */ +#define RTC_ISR_RSF_Pos (5U) +#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */ +#define RTC_ISR_INITS_Pos (4U) +#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */ +#define RTC_ISR_SHPF_Pos (3U) +#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */ +#define RTC_ISR_WUTWF_Pos (2U) +#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */ +#define RTC_ISR_ALRBWF_Pos (1U) +#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */ +#define RTC_ISR_ALRAWF_Pos (0U) +#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */ /******************** Bits definition for RTC_PRER register *****************/ -#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000U) /*!< */ -#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFFU) /*!< */ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */ /******************** Bits definition for RTC_WUTR register *****************/ -#define RTC_WUTR_WUT ((uint32_t)0x0000FFFFU) +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000U) /*!< */ -#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000U) /*!< */ -#define RTC_ALRMAR_DT ((uint32_t)0x30000000U) /*!< */ -#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000U) /*!< */ -#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000U) /*!< */ -#define RTC_ALRMAR_DU ((uint32_t)0x0F000000U) /*!< */ -#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000U) /*!< */ -#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000U) /*!< */ -#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000U) /*!< */ -#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000U) /*!< */ -#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000U) /*!< */ -#define RTC_ALRMAR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_ALRMAR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_ALRMAR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_ALRMAR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080U) /*!< */ -#define RTC_ALRMAR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_ALRMAR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */ +#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */ +#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */ +#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */ +#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */ +#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */ +#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */ +#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */ +#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000U) /*!< */ -#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000U) /*!< */ -#define RTC_ALRMBR_DT ((uint32_t)0x30000000U) /*!< */ -#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000U) /*!< */ -#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000U) /*!< */ -#define RTC_ALRMBR_DU ((uint32_t)0x0F000000U) /*!< */ -#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000U) /*!< */ -#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000U) /*!< */ -#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000U) /*!< */ -#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000U) /*!< */ -#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000U) /*!< */ -#define RTC_ALRMBR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_ALRMBR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_ALRMBR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_ALRMBR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080U) /*!< */ -#define RTC_ALRMBR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_ALRMBR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */ +#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */ +#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */ +#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */ +#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */ +#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */ +#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */ +#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */ +#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_WPR register ******************/ -#define RTC_WPR_KEY ((uint32_t)0x000000FFU) /*!< */ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */ /******************** Bits definition for RTC_SSR register ******************/ -#define RTC_SSR_SS ((uint32_t)0x0000FFFFU) /*!< */ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */ /******************** Bits definition for RTC_SHIFTR register ***************/ -#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFFU) /*!< */ -#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000U) /*!< */ +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */ +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */ /******************** Bits definition for RTC_TSTR register *****************/ -#define RTC_TSTR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_TSTR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_TSTR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_TSTR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_TSTR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_TSTR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_TSTR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_TSTR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_TSTR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_TSTR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TSTR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TSTR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_TSTR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_TSTR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_TSTR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_TSTR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_TSTR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_TSTR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_TSTR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_TSTR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */ +#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */ +#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */ +#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */ +#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */ +#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */ +#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_TSDR register *****************/ -#define RTC_TSDR_WDU ((uint32_t)0x0000E000U) /*!< */ -#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_TSDR_MT ((uint32_t)0x00001000U) /*!< */ -#define RTC_TSDR_MU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_TSDR_MU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TSDR_MU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TSDR_MU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TSDR_MU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TSDR_DT ((uint32_t)0x00000030U) /*!< */ -#define RTC_TSDR_DT_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_TSDR_DT_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_TSDR_DU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_TSDR_DU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_TSDR_DU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_TSDR_DU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_TSDR_DU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */ +#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */ +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */ +#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */ +#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */ +#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_TSSSR register ****************/ -#define RTC_TSSSR_SS ((uint32_t)0x0000FFFFU) +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /******************** Bits definition for RTC_CALR register *****************/ -#define RTC_CALR_CALP ((uint32_t)0x00008000U) /*!< */ -#define RTC_CALR_CALW8 ((uint32_t)0x00004000U) /*!< */ -#define RTC_CALR_CALW16 ((uint32_t)0x00002000U) /*!< */ -#define RTC_CALR_CALM ((uint32_t)0x000001FFU) /*!< */ -#define RTC_CALR_CALM_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_CALR_CALM_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_CALR_CALM_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_CALR_CALM_3 ((uint32_t)0x00000008U) /*!< */ -#define RTC_CALR_CALM_4 ((uint32_t)0x00000010U) /*!< */ -#define RTC_CALR_CALM_5 ((uint32_t)0x00000020U) /*!< */ -#define RTC_CALR_CALM_6 ((uint32_t)0x00000040U) /*!< */ -#define RTC_CALR_CALM_7 ((uint32_t)0x00000080U) /*!< */ -#define RTC_CALR_CALM_8 ((uint32_t)0x00000100U) /*!< */ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */ +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */ +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */ +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */ +#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ /* Legacy defines */ #define RTC_CAL_CALP RTC_CALR_CALP @@ -2997,146 +5061,296 @@ typedef struct #define RTC_CAL_CALM_8 RTC_CALR_CALM_8 /******************** Bits definition for RTC_TAMPCR register ****************/ -#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000U) /*!< */ -#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000U) /*!< */ -#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000U) /*!< */ -#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000U) /*!< */ -#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000U) /*!< */ -#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000U) /*!< */ -#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000U) /*!< */ -#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000U) /*!< */ -#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800U) /*!< */ -#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080U) /*!< */ -#define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010U) /*!< */ -#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008U) /*!< */ -#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004U) /*!< */ -#define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002U) /*!< */ -#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001U) /*!< */ +#define RTC_TAMPCR_TAMP2MF_Pos (21U) +#define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */ +#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */ +#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U) +#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */ +#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */ +#define RTC_TAMPCR_TAMP2IE_Pos (19U) +#define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */ +#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */ +#define RTC_TAMPCR_TAMP1MF_Pos (18U) +#define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */ +#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */ +#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U) +#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */ +#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */ +#define RTC_TAMPCR_TAMP1IE_Pos (16U) +#define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ +#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */ +#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) +#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */ +#define RTC_TAMPCR_TAMPPRCH_Pos (13U) +#define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */ +#define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAMPCR_TAMPFLT_Pos (11U) +#define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */ +#define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAMPCR_TAMPFREQ_Pos (8U) +#define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */ +#define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAMPCR_TAMPTS_Pos (7U) +#define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */ +#define RTC_TAMPCR_TAMP2TRG_Pos (4U) +#define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ +#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */ +#define RTC_TAMPCR_TAMP2E_Pos (3U) +#define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ +#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */ +#define RTC_TAMPCR_TAMPIE_Pos (2U) +#define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */ +#define RTC_TAMPCR_TAMP1TRG_Pos (1U) +#define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ +#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */ +#define RTC_TAMPCR_TAMP1E_Pos (0U) +#define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ +#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */ /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000U) -#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000U) -#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000U) -#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000U) -#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000U) -#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFFU) +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000U) -#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000U) -#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000U) -#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000U) -#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000U) -#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFFU) +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT_RMP ((uint32_t)0x00000002U) /*!< */ -#define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001U) /*!< */ +#define RTC_OR_OUT_RMP_Pos (1U) +#define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */ +#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */ +#define RTC_OR_ALARMOUTTYPE_Pos (0U) +#define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */ +#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */ /* Legacy defines */ #define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP /******************** Bits definition for RTC_BKP0R register ****************/ -#define RTC_BKP0R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP0R_Pos (0U) +#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP0R RTC_BKP0R_Msk /*!< */ /******************** Bits definition for RTC_BKP1R register ****************/ -#define RTC_BKP1R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP1R_Pos (0U) +#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP1R RTC_BKP1R_Msk /*!< */ /******************** Bits definition for RTC_BKP2R register ****************/ -#define RTC_BKP2R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP2R_Pos (0U) +#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP2R RTC_BKP2R_Msk /*!< */ /******************** Bits definition for RTC_BKP3R register ****************/ -#define RTC_BKP3R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP3R_Pos (0U) +#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP3R RTC_BKP3R_Msk /*!< */ /******************** Bits definition for RTC_BKP4R register ****************/ -#define RTC_BKP4R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP4R_Pos (0U) +#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP4R RTC_BKP4R_Msk /*!< */ /******************** Number of backup registers ******************************/ -#define RTC_BKP_NUMBER ((uint32_t)0x00000005U) /*!< */ +#define RTC_BKP_NUMBER (0x00000005U) /*!< */ /******************************************************************************/ /* */ /* Serial Peripheral Interface (SPI) */ /* */ /******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32L0 family) + */ +#define SPI_I2S_SUPPORT /*!< I2S support */ + /******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA ((uint32_t)0x00000001U) /*!< Clock Phase */ -#define SPI_CR1_CPOL ((uint32_t)0x00000002U) /*!< Clock Polarity */ -#define SPI_CR1_MSTR ((uint32_t)0x00000004U) /*!< Master Selection */ -#define SPI_CR1_BR ((uint32_t)0x00000038U) /*!< BR[2:0] bits (Baud Rate Control) */ -#define SPI_CR1_BR_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define SPI_CR1_BR_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ -#define SPI_CR1_BR_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ -#define SPI_CR1_SPE ((uint32_t)0x00000040U) /*!< SPI Enable */ -#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080U) /*!< Frame Format */ -#define SPI_CR1_SSI ((uint32_t)0x00000100U) /*!< Internal slave select */ -#define SPI_CR1_SSM ((uint32_t)0x00000200U) /*!< Software slave management */ -#define SPI_CR1_RXONLY ((uint32_t)0x00000400U) /*!< Receive only */ -#define SPI_CR1_DFF ((uint32_t)0x00000800U) /*!< Data Frame Format */ -#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000U) /*!< Transmit CRC next */ -#define SPI_CR1_CRCEN ((uint32_t)0x00002000U) /*!< Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE ((uint32_t)0x00004000U) /*!< Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000U) /*!< Bidirectional data mode enable */ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ +#define SPI_CR1_CPOL_Pos (1U) +#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ +#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ +#define SPI_CR1_MSTR_Pos (2U) +#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ +#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ +#define SPI_CR1_BR_Pos (3U) +#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */ +#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ +#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ +#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ +#define SPI_CR1_SPE_Pos (6U) +#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ +#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ +#define SPI_CR1_LSBFIRST_Pos (7U) +#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ +#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ +#define SPI_CR1_SSI_Pos (8U) +#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ +#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ +#define SPI_CR1_SSM_Pos (9U) +#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ +#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ +#define SPI_CR1_RXONLY_Pos (10U) +#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ +#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ +#define SPI_CR1_DFF_Pos (11U) +#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ +#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ +#define SPI_CR1_CRCNEXT_Pos (12U) +#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ +#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ +#define SPI_CR1_CRCEN_Pos (13U) +#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ +#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE_Pos (14U) +#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ +#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE_Pos (15U) +#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ +#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ /******************* Bit definition for SPI_CR2 register ********************/ -#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001U) /*!< Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002U) /*!< Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE ((uint32_t)0x00000004U) /*!< SS Output Enable */ -#define SPI_CR2_FRF ((uint32_t)0x00000010U) /*!< Frame Format Enable */ -#define SPI_CR2_ERRIE ((uint32_t)0x00000020U) /*!< Error Interrupt Enable */ -#define SPI_CR2_RXNEIE ((uint32_t)0x00000040U) /*!< RX buffer Not Empty Interrupt Enable */ -#define SPI_CR2_TXEIE ((uint32_t)0x00000080U) /*!< Tx buffer Empty Interrupt Enable */ +#define SPI_CR2_RXDMAEN_Pos (0U) +#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ +#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN_Pos (1U) +#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ +#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE_Pos (2U) +#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ +#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ +#define SPI_CR2_FRF_Pos (4U) +#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ +#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ +#define SPI_CR2_ERRIE_Pos (5U) +#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ +#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ +#define SPI_CR2_RXNEIE_Pos (6U) +#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ +#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE_Pos (7U) +#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ +#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ /******************** Bit definition for SPI_SR register ********************/ -#define SPI_SR_RXNE ((uint32_t)0x00000001U) /*!< Receive buffer Not Empty */ -#define SPI_SR_TXE ((uint32_t)0x00000002U) /*!< Transmit buffer Empty */ -#define SPI_SR_CHSIDE ((uint32_t)0x00000004U) /*!< Channel side */ -#define SPI_SR_UDR ((uint32_t)0x00000008U) /*!< Underrun flag */ -#define SPI_SR_CRCERR ((uint32_t)0x00000010U) /*!< CRC Error flag */ -#define SPI_SR_MODF ((uint32_t)0x00000020U) /*!< Mode fault */ -#define SPI_SR_OVR ((uint32_t)0x00000040U) /*!< Overrun flag */ -#define SPI_SR_BSY ((uint32_t)0x00000080U) /*!< Busy flag */ -#define SPI_SR_FRE ((uint32_t)0x00000100U) /*!< TI frame format error */ +#define SPI_SR_RXNE_Pos (0U) +#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ +#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ +#define SPI_SR_TXE_Pos (1U) +#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ +#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ +#define SPI_SR_CHSIDE_Pos (2U) +#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ +#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ +#define SPI_SR_UDR_Pos (3U) +#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */ +#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ +#define SPI_SR_CRCERR_Pos (4U) +#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ +#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ +#define SPI_SR_MODF_Pos (5U) +#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */ +#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ +#define SPI_SR_OVR_Pos (6U) +#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */ +#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ +#define SPI_SR_BSY_Pos (7U) +#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */ +#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ +#define SPI_SR_FRE_Pos (8U) +#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */ +#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ /******************** Bit definition for SPI_DR register ********************/ -#define SPI_DR_DR ((uint32_t)0x0000FFFFU) /*!< Data Register */ +#define SPI_DR_DR_Pos (0U) +#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ +#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ /******************* Bit definition for SPI_CRCPR register ******************/ -#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFFU) /*!< CRC polynomial register */ +#define SPI_CRCPR_CRCPOLY_Pos (0U) +#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ +#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ /****************** Bit definition for SPI_RXCRCR register ******************/ -#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFFU) /*!< Rx CRC Register */ +#define SPI_RXCRCR_RXCRC_Pos (0U) +#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ /****************** Bit definition for SPI_TXCRCR register ******************/ -#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFFU) /*!< Tx CRC Register */ +#define SPI_TXCRCR_TXCRC_Pos (0U) +#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ /****************** Bit definition for SPI_I2SCFGR register *****************/ -#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001U) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -83,15 +83,15 @@ #include "hal_tick.h" #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/ + #define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* MSI_VALUE */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ @@ -115,8 +115,8 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. + This value must be a multiple of 0x100. */ /******************************************************************************/ /** * @} @@ -146,8 +146,9 @@ variable is updated automatically. */ uint32_t SystemCoreClock = 32000000; -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U}; /** * @} @@ -179,25 +180,25 @@ uint8_t SetSysClock_PLL_HSI(void); void SystemInit (void) { /*!< Set MSION bit */ - RCC->CR |= (uint32_t)0x00000100; + RCC->CR |= (uint32_t)0x00000100U; /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ - RCC->CFGR &= (uint32_t) 0x88FF400C; + RCC->CFGR &= (uint32_t) 0x88FF400CU; /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFF6; + RCC->CR &= (uint32_t)0xFEF6FFF6U; /*!< Reset HSI48ON bit */ - RCC->CRRCR &= (uint32_t)0xFFFFFFFE; + RCC->CRRCR &= (uint32_t)0xFFFFFFFEU; /*!< Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; + RCC->CR &= (uint32_t)0xFFFBFFFFU; /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ - RCC->CFGR &= (uint32_t)0xFF02FFFF; + RCC->CFGR &= (uint32_t)0xFF02FFFFU; /*!< Disable all interrupts */ - RCC->CIER = 0x00000000; + RCC->CIER = 0x00000000U; /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM @@ -259,33 +260,33 @@ void SystemInit (void) */ void SystemCoreClockUpdate (void) { - uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; + uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; switch (tmp) { - case 0x00: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); + case 0x00U: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; + SystemCoreClock = (32768U * (1U << (msirange + 1U))); break; - case 0x04: /* HSI used as system clock */ + case 0x04U: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; break; - case 0x08: /* HSE used as system clock */ + case 0x08U: /* HSE used as system clock */ SystemCoreClock = HSE_VALUE; break; - case 0x0C: /* PLL used as system clock */ + case 0x0CU: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; - pllmul = PLLMulTable[(pllmul >> 18)]; - plldiv = (plldiv >> 22) + 1; + pllmul = PLLMulTable[(pllmul >> 18U)]; + plldiv = (plldiv >> 22U) + 1U; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - if (pllsource == 0x00) + if (pllsource == 0x00U) { /* HSI oscillator clock selected as PLL clock entry */ SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); @@ -297,13 +298,13 @@ void SystemCoreClockUpdate (void) } break; default: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; + SystemCoreClock = (32768U * (1U << (msirange + 1U))); break; } /* Compute HCLK clock frequency --------------------------------------------*/ /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/system_stm32l0xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/system_stm32l0xx.h index 4a82de7134..7015debf51 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/system_stm32l0xx.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/system_stm32l0xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32l0xx.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -74,6 +74,11 @@ variable is updated automatically. */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/* +*/ +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/stm32l073xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/stm32l073xx.h index 480e341a54..b446f3ac53 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/stm32l073xx.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/stm32l073xx.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l073xx.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for stm32l073xx devices. @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -651,72 +651,76 @@ typedef struct #define DATA_EEPROM_BANK1_END ((uint32_t)0x08080BFFU) /*!< Program end DATA EEPROM BANK1 address */ #define DATA_EEPROM_BANK2_END ((uint32_t)0x080817FFU) /*!< Program end DATA EEPROM BANK2 address */ #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */ +#define SRAM_SIZE_MAX ((uint32_t)0x00005000U) /*!< maximum SRAM size (up to 20KBytes) */ + #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */ /*!< Peripheral memory map */ #define APBPERIPH_BASE PERIPH_BASE -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) -#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) +#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000U) -#define TIM2_BASE (APBPERIPH_BASE + 0x00000000) -#define TIM3_BASE (APBPERIPH_BASE + 0x00000400) -#define TIM6_BASE (APBPERIPH_BASE + 0x00001000) -#define TIM7_BASE (APBPERIPH_BASE + 0x00001400) -#define LCD_BASE (APBPERIPH_BASE + 0x00002400) -#define RTC_BASE (APBPERIPH_BASE + 0x00002800) -#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00) -#define IWDG_BASE (APBPERIPH_BASE + 0x00003000) -#define SPI2_BASE (APBPERIPH_BASE + 0x00003800) -#define USART2_BASE (APBPERIPH_BASE + 0x00004400) -#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800) -#define USART4_BASE (APBPERIPH_BASE + 0x00004C00) -#define USART5_BASE (APBPERIPH_BASE + 0x00005000) -#define I2C1_BASE (APBPERIPH_BASE + 0x00005400) -#define I2C2_BASE (APBPERIPH_BASE + 0x00005800) -#define CRS_BASE (APBPERIPH_BASE + 0x00006C00) -#define PWR_BASE (APBPERIPH_BASE + 0x00007000) -#define DAC_BASE (APBPERIPH_BASE + 0x00007400) -#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00) -#define I2C3_BASE (APBPERIPH_BASE + 0x00007800) +#define TIM2_BASE (APBPERIPH_BASE + 0x00000000U) +#define TIM3_BASE (APBPERIPH_BASE + 0x00000400U) +#define TIM6_BASE (APBPERIPH_BASE + 0x00001000U) +#define TIM7_BASE (APBPERIPH_BASE + 0x00001400U) +#define LCD_BASE (APBPERIPH_BASE + 0x00002400U) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800U) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00U) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000U) +#define SPI2_BASE (APBPERIPH_BASE + 0x00003800U) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400U) +#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800U) +#define USART4_BASE (APBPERIPH_BASE + 0x00004C00U) +#define USART5_BASE (APBPERIPH_BASE + 0x00005000U) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400U) +#define I2C2_BASE (APBPERIPH_BASE + 0x00005800U) +#define CRS_BASE (APBPERIPH_BASE + 0x00006C00U) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000U) +#define DAC_BASE (APBPERIPH_BASE + 0x00007400U) +#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00U) +#define I2C3_BASE (APBPERIPH_BASE + 0x00007800U) -#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000) -#define COMP1_BASE (APBPERIPH_BASE + 0x00010018) -#define COMP2_BASE (APBPERIPH_BASE + 0x0001001C) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000U) +#define COMP1_BASE (APBPERIPH_BASE + 0x00010018U) +#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CU) #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE) -#define EXTI_BASE (APBPERIPH_BASE + 0x00010400) -#define TIM21_BASE (APBPERIPH_BASE + 0x00010800) -#define TIM22_BASE (APBPERIPH_BASE + 0x00011400) -#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00) -#define ADC1_BASE (APBPERIPH_BASE + 0x00012400) -#define ADC_BASE (APBPERIPH_BASE + 0x00012708) -#define SPI1_BASE (APBPERIPH_BASE + 0x00013000) -#define USART1_BASE (APBPERIPH_BASE + 0x00013800) -#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800) +#define EXTI_BASE (APBPERIPH_BASE + 0x00010400U) +#define TIM21_BASE (APBPERIPH_BASE + 0x00010800U) +#define TIM22_BASE (APBPERIPH_BASE + 0x00011400U) +#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00U) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400U) +#define ADC_BASE (APBPERIPH_BASE + 0x00012708U) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000U) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800U) +#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800U) -#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080) -#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8) +#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8U) -#define RCC_BASE (AHBPERIPH_BASE + 0x00001000) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */ +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */ #define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */ -#define CRC_BASE (AHBPERIPH_BASE + 0x00003000) -#define TSC_BASE (AHBPERIPH_BASE + 0x00004000) -#define RNG_BASE (AHBPERIPH_BASE + 0x00005000) +#define FLASHSIZE_BASE ((uint32_t)0x1FF8007CU) /*!< FLASH Size register base address */ +#define UID_BASE ((uint32_t)0x1FF80050U) /*!< Unique device ID register base address */ +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) +#define TSC_BASE (AHBPERIPH_BASE + 0x00004000U) +#define RNG_BASE (AHBPERIPH_BASE + 0x00005000U) -#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000) -#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400) -#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800) -#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00) -#define GPIOE_BASE (IOPPERIPH_BASE + 0x00001000) -#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00) +#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000U) +#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400U) +#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800U) +#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00U) +#define GPIOE_BASE (IOPPERIPH_BASE + 0x00001000U) +#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00U) /** * @} @@ -811,91 +815,173 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for ADC_ISR register ******************/ -#define ADC_ISR_EOCAL ((uint32_t)0x00000800U) /*!< End of calibration flag */ -#define ADC_ISR_AWD ((uint32_t)0x00000080U) /*!< Analog watchdog flag */ -#define ADC_ISR_OVR ((uint32_t)0x00000010U) /*!< Overrun flag */ -#define ADC_ISR_EOSEQ ((uint32_t)0x00000008U) /*!< End of Sequence flag */ -#define ADC_ISR_EOC ((uint32_t)0x00000004U) /*!< End of Conversion */ -#define ADC_ISR_EOSMP ((uint32_t)0x00000002U) /*!< End of sampling flag */ -#define ADC_ISR_ADRDY ((uint32_t)0x00000001U) /*!< ADC Ready */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1U << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */ +#define ADC_ISR_AWD_Pos (7U) +#define ADC_ISR_AWD_Msk (0x1U << ADC_ISR_AWD_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */ +#define ADC_ISR_EOSEQ_Pos (3U) +#define ADC_ISR_EOSEQ_Msk (0x1U << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */ /* Old EOSEQ bit definition, maintained for legacy purpose */ #define ADC_ISR_EOS ADC_ISR_EOSEQ /******************** Bits definition for ADC_IER register ******************/ -#define ADC_IER_EOCALIE ((uint32_t)0x00000800U) /*!< Enf Of Calibration interrupt enable */ -#define ADC_IER_AWDIE ((uint32_t)0x00000080U) /*!< Analog Watchdog interrupt enable */ -#define ADC_IER_OVRIE ((uint32_t)0x00000010U) /*!< Overrun interrupt enable */ -#define ADC_IER_EOSEQIE ((uint32_t)0x00000008U) /*!< End of Sequence of conversion interrupt enable */ -#define ADC_IER_EOCIE ((uint32_t)0x00000004U) /*!< End of Conversion interrupt enable */ -#define ADC_IER_EOSMPIE ((uint32_t)0x00000002U) /*!< End of sampling interrupt enable */ -#define ADC_IER_ADRDYIE ((uint32_t)0x00000001U) /*!< ADC Ready interrupt enable */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1U << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */ +#define ADC_IER_AWDIE_Pos (7U) +#define ADC_IER_AWDIE_Msk (0x1U << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */ +#define ADC_IER_EOSEQIE_Pos (3U) +#define ADC_IER_EOSEQIE_Msk (0x1U << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */ /* Old EOSEQIE bit definition, maintained for legacy purpose */ #define ADC_IER_EOSIE ADC_IER_EOSEQIE /******************** Bits definition for ADC_CR register *******************/ -#define ADC_CR_ADCAL ((uint32_t)0x80000000U) /*!< ADC calibration */ -#define ADC_CR_ADVREGEN ((uint32_t)0x10000000U) /*!< ADC Voltage Regulator Enable */ -#define ADC_CR_ADSTP ((uint32_t)0x00000010U) /*!< ADC stop of conversion command */ -#define ADC_CR_ADSTART ((uint32_t)0x00000004U) /*!< ADC start of conversion */ -#define ADC_CR_ADDIS ((uint32_t)0x00000002U) /*!< ADC disable command */ -#define ADC_CR_ADEN ((uint32_t)0x00000001U) /*!< ADC enable control */ /*#### TBV */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */ /******************* Bits definition for ADC_CFGR1 register *****************/ -#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000U) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000U) /*!< Bit 0 */ -#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000U) /*!< Bit 1 */ -#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000U) /*!< Bit 2 */ -#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000U) /*!< Bit 3 */ -#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000U) /*!< Bit 4 */ -#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000U) /*!< Analog watchdog enable on regular channels */ -#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000U) /*!< Enable the watchdog on a single channel or on all channels */ -#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000U) /*!< Discontinuous mode on regular channels */ -#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000U) /*!< ADC auto power off */ -#define ADC_CFGR1_WAIT ((uint32_t)0x00004000U) /*!< ADC wait conversion mode */ -#define ADC_CFGR1_CONT ((uint32_t)0x00002000U) /*!< Continuous Conversion */ -#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000U) /*!< Overrun mode */ -#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00U) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ -#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ -#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ -#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0U) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ -#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ -#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100U) /*!< Bit 2 */ -#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020U) /*!< Data Alignment */ -#define ADC_CFGR1_RES ((uint32_t)0x00000018U) /*!< RES[1:0] bits (Resolution) */ -#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ -#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004U) /*!< Sequence scan direction */ -#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002U) /*!< Direct memory access configuration */ -#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001U) /*!< Direct memory access enable */ +#define ADC_CFGR1_AWDCH_Pos (26U) +#define ADC_CFGR1_AWDCH_Msk (0x1FU << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CFGR1_AWDCH_0 (0x01U << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWDCH_1 (0x02U << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWDCH_2 (0x04U << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWDCH_3 (0x08U << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWDCH_4 (0x10U << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ +#define ADC_CFGR1_AWDEN_Pos (23U) +#define ADC_CFGR1_AWDEN_Msk (0x1U << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */ +#define ADC_CFGR1_AWDSGL_Pos (22U) +#define ADC_CFGR1_AWDSGL_Msk (0x1U << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */ +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */ +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ +#define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */ +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */ /* Old WAIT bit definition, maintained for legacy purpose */ #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT /******************* Bits definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_TOVS ((uint32_t)0x80000200U) /*!< Triggered Oversampling */ -#define ADC_CFGR2_OVSS ((uint32_t)0x000001E0U) /*!< OVSS [3:0] bits (Oversampling shift) */ -#define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ -#define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ -#define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ -#define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ -#define ADC_CFGR2_OVSR ((uint32_t)0x0000001CU) /*!< OVSR [2:0] bits (Oversampling ratio) */ -#define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004U) /*!< Bit 0 */ -#define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008U) /*!< Bit 1 */ -#define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010U) /*!< Bit 2 */ -#define ADC_CFGR2_OVSE ((uint32_t)0x00000001U) /*!< Oversampler Enable */ -#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000U) /*!< CKMODE [1:0] bits (ADC clock mode) */ -#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000U) /*!< Bit 0 */ -#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000U) /*!< Bit 1 */ +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x400001U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */ +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */ +#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */ +#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1U << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */ +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */ +#define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ /****************** Bit definition for ADC_SMPR register ********************/ -#define ADC_SMPR_SMP ((uint32_t)0x00000007U) /*!< SMPR[2:0] bits (Sampling time selection) */ -#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ -#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ -#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SMPR_SMP_Pos (0U) +#define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */ +#define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ /* Legacy defines */ #define ADC_SMPR_SMPR ADC_SMPR_SMP @@ -904,47 +990,105 @@ typedef struct #define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2 /******************* Bit definition for ADC_TR register ********************/ -#define ADC_TR_HT ((uint32_t)0x0FFF0000U) /*!< Analog watchdog high threshold */ -#define ADC_TR_LT ((uint32_t)0x00000FFFU) /*!< Analog watchdog low threshold */ +#define ADC_TR_HT_Pos (16U) +#define ADC_TR_HT_Msk (0xFFFU << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */ +#define ADC_TR_LT_Pos (0U) +#define ADC_TR_LT_Msk (0xFFFU << ADC_TR_LT_Pos) /*!< 0x00000FFF */ +#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */ /****************** Bit definition for ADC_CHSELR register ******************/ -#define ADC_CHSELR_CHSEL ((uint32_t)0x0007FFFFU) /*!< ADC group regular sequencer channels */ -#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000U) /*!< Channel 18 selection */ -#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000U) /*!< Channel 17 selection */ -#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000U) /*!< Channel 16 selection */ -#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000U) /*!< Channel 15 selection */ -#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000U) /*!< Channel 14 selection */ -#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000U) /*!< Channel 13 selection */ -#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000U) /*!< Channel 12 selection */ -#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800U) /*!< Channel 11 selection */ -#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400U) /*!< Channel 10 selection */ -#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200U) /*!< Channel 9 selection */ -#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100U) /*!< Channel 8 selection */ -#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080U) /*!< Channel 7 selection */ -#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040U) /*!< Channel 6 selection */ -#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020U) /*!< Channel 5 selection */ -#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010U) /*!< Channel 4 selection */ -#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008U) /*!< Channel 3 selection */ -#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004U) /*!< Channel 2 selection */ -#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002U) /*!< Channel 1 selection */ -#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001U) /*!< Channel 0 selection */ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1U << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< Channel 16 selection */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFFU) /*!< Regular data */ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */ /******************** Bit definition for ADC_CALFACT register ********************/ -#define ADC_CALFACT_CALFACT ((uint32_t)0x0000007FU) /*!< Calibration factor */ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FU << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */ /******************* Bit definition for ADC_CCR register ********************/ -#define ADC_CCR_LFMEN ((uint32_t)0x02000000U) /*!< Low Frequency Mode enable */ -#define ADC_CCR_VLCDEN ((uint32_t)0x01000000U) /*!< Voltage LCD enable */ -#define ADC_CCR_TSEN ((uint32_t)0x00800000U) /*!< Temperature sensore enable */ -#define ADC_CCR_VREFEN ((uint32_t)0x00400000U) /*!< Vrefint enable */ -#define ADC_CCR_PRESC ((uint32_t)0x003C0000U) /*!< PRESC [3:0] bits (ADC prescaler) */ -#define ADC_CCR_PRESC_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ -#define ADC_CCR_PRESC_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ -#define ADC_CCR_PRESC_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ -#define ADC_CCR_PRESC_3 ((uint32_t)0x00200000U) /*!< Bit 3 */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1U << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */ +#define ADC_CCR_VLCDEN_Pos (24U) +#define ADC_CCR_VLCDEN_Msk (0x1U << ADC_CCR_VLCDEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VLCDEN ADC_CCR_VLCDEN_Msk /*!< Voltage LCD enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */ +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */ +#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ /******************************************************************************/ /* */ @@ -953,37 +1097,77 @@ typedef struct /******************************************************************************/ /************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/ /* COMP1 bits definition */ -#define COMP_CSR_COMP1EN ((uint32_t)0x00000001U) /*!< COMP1 enable */ -#define COMP_CSR_COMP1INNSEL ((uint32_t)0x00000030U) /*!< COMP1 inverting input select */ -#define COMP_CSR_COMP1INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP1 inverting input select bit 0 */ -#define COMP_CSR_COMP1INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP1 inverting input select bit 1 */ -#define COMP_CSR_COMP1WM ((uint32_t)0x00000100U) /*!< Comparators window mode enable */ -#define COMP_CSR_COMP1LPTIM1IN1 ((uint32_t)0x00001000U) /*!< COMP1 LPTIM1 IN1 connection */ -#define COMP_CSR_COMP1POLARITY ((uint32_t)0x00008000U) /*!< COMP1 output polarity */ -#define COMP_CSR_COMP1VALUE ((uint32_t)0x40000000U) /*!< COMP1 output level */ -#define COMP_CSR_COMP1LOCK ((uint32_t)0x80000000U) /*!< COMP1 lock */ +#define COMP_CSR_COMP1EN_Pos (0U) +#define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */ +#define COMP_CSR_COMP1INNSEL_Pos (4U) +#define COMP_CSR_COMP1INNSEL_Msk (0x3U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */ +#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */ +#define COMP_CSR_COMP1INNSEL_0 (0x1U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_COMP1INNSEL_1 (0x2U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_COMP1WM_Pos (8U) +#define COMP_CSR_COMP1WM_Msk (0x1U << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */ +#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */ +#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U) +#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */ +#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */ +#define COMP_CSR_COMP1POLARITY_Pos (15U) +#define COMP_CSR_COMP1POLARITY_Msk (0x1U << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */ +#define COMP_CSR_COMP1VALUE_Pos (30U) +#define COMP_CSR_COMP1VALUE_Msk (0x1U << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */ +#define COMP_CSR_COMP1LOCK_Pos (31U) +#define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */ /* COMP2 bits definition */ -#define COMP_CSR_COMP2EN ((uint32_t)0x00000001U) /*!< COMP2 enable */ -#define COMP_CSR_COMP2SPEED ((uint32_t)0x00000008U) /*!< COMP2 power mode */ -#define COMP_CSR_COMP2INNSEL ((uint32_t)0x00000070U) /*!< COMP2 inverting input select */ -#define COMP_CSR_COMP2INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP2 inverting input select bit 0 */ -#define COMP_CSR_COMP2INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP2 inverting input select bit 1 */ -#define COMP_CSR_COMP2INNSEL_2 ((uint32_t)0x00000040U) /*!< COMP2 inverting input select bit 2 */ -#define COMP_CSR_COMP2INPSEL ((uint32_t)0x00000700U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2INPSEL_0 ((uint32_t)0x00000100U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2INPSEL_1 ((uint32_t)0x00000200U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2INPSEL_2 ((uint32_t)0x00000400U) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMP2LPTIM1IN2 ((uint32_t)0x00001000U) /*!< COMP2 LPTIM1 IN2 connection */ -#define COMP_CSR_COMP2LPTIM1IN1 ((uint32_t)0x00002000U) /*!< COMP2 LPTIM1 IN1 connection */ -#define COMP_CSR_COMP2POLARITY ((uint32_t)0x00008000U) /*!< COMP2 output polarity */ -#define COMP_CSR_COMP2VALUE ((uint32_t)0x40000000U) /*!< COMP2 output level */ -#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000U) /*!< COMP2 lock */ +#define COMP_CSR_COMP2EN_Pos (0U) +#define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */ +#define COMP_CSR_COMP2SPEED_Pos (3U) +#define COMP_CSR_COMP2SPEED_Msk (0x1U << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */ +#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */ +#define COMP_CSR_COMP2INNSEL_Pos (4U) +#define COMP_CSR_COMP2INNSEL_Msk (0x7U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */ +#define COMP_CSR_COMP2INNSEL_0 (0x1U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_COMP2INNSEL_1 (0x2U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_COMP2INNSEL_2 (0x4U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_COMP2INPSEL_Pos (8U) +#define COMP_CSR_COMP2INPSEL_Msk (0x7U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */ +#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */ +#define COMP_CSR_COMP2INPSEL_0 (0x1U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_COMP2INPSEL_1 (0x2U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */ +#define COMP_CSR_COMP2INPSEL_2 (0x4U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */ +#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U) +#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */ +#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */ +#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U) +#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */ +#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */ +#define COMP_CSR_COMP2POLARITY_Pos (15U) +#define COMP_CSR_COMP2POLARITY_Msk (0x1U << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */ +#define COMP_CSR_COMP2VALUE_Pos (30U) +#define COMP_CSR_COMP2VALUE_Msk (0x1U << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */ +#define COMP_CSR_COMP2LOCK_Pos (31U) +#define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */ /********************** Bit definition for COMP_CSR register common ****************/ -#define COMP_CSR_COMPxEN ((uint32_t)0x00000001U) /*!< COMPx enable */ -#define COMP_CSR_COMPxPOLARITY ((uint32_t)0x00008000U) /*!< COMPx output polarity */ -#define COMP_CSR_COMPxOUTVALUE ((uint32_t)0x40000000U) /*!< COMPx output level */ -#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000U) /*!< COMPx lock */ +#define COMP_CSR_COMPxEN_Pos (0U) +#define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */ +#define COMP_CSR_COMPxPOLARITY_Pos (15U) +#define COMP_CSR_COMPxPOLARITY_Msk (0x1U << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */ +#define COMP_CSR_COMPxOUTVALUE_Pos (30U) +#define COMP_CSR_COMPxOUTVALUE_Msk (0x1U << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */ +#define COMP_CSR_COMPxLOCK_Pos (31U) +#define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */ /* Reference defines */ #define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ @@ -994,26 +1178,40 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ +#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET the CRC computation unit bit */ -#define CRC_CR_POLYSIZE ((uint32_t)0x00000018U) /*!< Polynomial size bits */ -#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008U) /*!< Polynomial size bit 0 */ -#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010U) /*!< Polynomial size bit 1 */ -#define CRC_CR_REV_IN ((uint32_t)0x00000060U) /*!< REV_IN Reverse Input Data bits */ -#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ -#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ -#define CRC_CR_REV_OUT ((uint32_t)0x00000080U) /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ /******************* Bit definition for CRC_INIT register *******************/ -#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFFU) /*!< Initial CRC value bits */ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ -#define CRC_POL_POL ((uint32_t)0xFFFFFFFFU) /*!< Coefficients of the polynomial */ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ /******************************************************************************/ /* */ @@ -1022,46 +1220,98 @@ typedef struct /******************************************************************************/ /******************* Bit definition for CRS_CR register *********************/ -#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001U) /* SYNC event OK interrupt enable */ -#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002U) /* SYNC warning interrupt enable */ -#define CRS_CR_ERRIE ((uint32_t)0x00000004U) /* SYNC error interrupt enable */ -#define CRS_CR_ESYNCIE ((uint32_t)0x00000008U) /* Expected SYNC(ESYNCF) interrupt Enable*/ -#define CRS_CR_CEN ((uint32_t)0x00000020U) /* Frequency error counter enable */ -#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040U) /* Automatic trimming enable */ -#define CRS_CR_SWSYNC ((uint32_t)0x00000080U) /* A Software SYNC event is generated */ -#define CRS_CR_TRIM ((uint32_t)0x00003F00U) /* HSI48 oscillator smooth trimming */ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ -#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFFU) /* Counter reload value */ -#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000U) /* Frequency error limit */ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */ -#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000U) /* SYNC divider */ -#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000U) /* Bit 0 */ -#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000U) /* Bit 1 */ -#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000U) /* Bit 2 */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ -#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000U) /* SYNC signal source selection */ -#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000U) /* Bit 0 */ -#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000U) /* Bit 1 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ -#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000U) /* SYNC polarity selection */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */ /******************* Bit definition for CRS_ISR register *********************/ -#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001U) /* SYNC event OK flag */ -#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002U) /* SYNC warning */ -#define CRS_ISR_ERRF ((uint32_t)0x00000004U) /* SYNC error flag */ -#define CRS_ISR_ESYNCF ((uint32_t)0x00000008U) /* Expected SYNC flag */ -#define CRS_ISR_SYNCERR ((uint32_t)0x00000100U) /* SYNC error */ -#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200U) /* SYNC missed */ -#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400U) /* Trimming overflow or underflow */ -#define CRS_ISR_FEDIR ((uint32_t)0x00008000U) /* Frequency error direction */ -#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000U) /* Frequency error capture */ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */ /******************* Bit definition for CRS_ICR register *********************/ -#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001U) /* SYNC event OK clear flag */ -#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002U) /* SYNC warning clear flag */ -#define CRS_ICR_ERRC ((uint32_t)0x00000004U) /* Error clear flag */ -#define CRS_ICR_ESYNCC ((uint32_t)0x00000008U) /* Expected SYNC clear flag */ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */ /******************************************************************************/ /* */ @@ -1075,93 +1325,159 @@ typedef struct #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */ /******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((uint32_t)0x00000001U) /*!< DAC channel1 enable */ -#define DAC_CR_BOFF1 ((uint32_t)0x00000002U) /*!< DAC channel1 output buffer disable */ -#define DAC_CR_TEN1 ((uint32_t)0x00000004U) /*!< DAC channel1 Trigger enable */ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ +#define DAC_CR_BOFF1_Pos (1U) +#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ +#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */ +#define DAC_CR_TEN1_Pos (2U) +#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ +#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */ -#define DAC_CR_TSEL1 ((uint32_t)0x00000038U) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ -#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ +#define DAC_CR_TSEL1_Pos (3U) +#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ +#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ +#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ +#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ -#define DAC_CR_WAVE1 ((uint32_t)0x000000C0U) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ -#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ +#define DAC_CR_WAVE1_Pos (6U) +#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ +#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ +#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ -#define DAC_CR_MAMP1 ((uint32_t)0x00000F00U) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ -#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */ -#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */ -#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */ -#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800U) /*!< Bit 3 */ +#define DAC_CR_MAMP1_Pos (8U) +#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ +#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ +#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ +#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ +#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ -#define DAC_CR_DMAEN1 ((uint32_t)0x00001000U) /*!< DAC channel1 DMA enable */ -#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA Underrun interrupt enable */ +#define DAC_CR_DMAEN1_Pos (12U) +#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ +#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ +#define DAC_CR_DMAUDRIE1_Pos (13U) +#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ +#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun interrupt enable */ -#define DAC_CR_EN2 ((uint32_t)0x00010000U) /*!< DAC channel2 enable */ -#define DAC_CR_BOFF2 ((uint32_t)0x00020000U) /*!< DAC channel2 output buffer disable */ -#define DAC_CR_TEN2 ((uint32_t)0x00040000U) /*!< DAC channel2 Trigger enable */ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */ +#define DAC_CR_BOFF2_Pos (17U) +#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ +#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */ +#define DAC_CR_TEN2_Pos (18U) +#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ +#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */ -#define DAC_CR_TSEL2 ((uint32_t)0x00380000U) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ -#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000U) /*!< Bit 0 */ -#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000U) /*!< Bit 1 */ -#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000U) /*!< Bit 2 */ +#define DAC_CR_TSEL2_Pos (19U) +#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ +#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ +#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ +#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ -#define DAC_CR_WAVE2 ((uint32_t)0x00C00000U) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000U) /*!< Bit 0 */ -#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000U) /*!< Bit 1 */ +#define DAC_CR_WAVE2_Pos (22U) +#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ +#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ +#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ -#define DAC_CR_MAMP2 ((uint32_t)0x0F000000U) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ -#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ -#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ -#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000U) /*!< Bit 2 */ -#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000U) /*!< Bit 3 */ +#define DAC_CR_MAMP2_Pos (24U) +#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ +#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ +#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ +#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ +#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ -#define DAC_CR_DMAEN2 ((uint32_t)0x10000000U) /*!< DAC channel2 DMA enabled */ -#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000U) /*!< DAC channel12DMA Underrun interrupt enable */ +#define DAC_CR_DMAEN2_Pos (28U) +#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ +#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */ +#define DAC_CR_DMAUDRIE2_Pos (29U) +#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ +#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel12DMA Underrun interrupt enable */ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001U) /*!< DAC channel1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002U) /*!< DAC channel2 software trigger */ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2_Pos (1U) +#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ +#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */ /***************** Bit definition for DAC_DHR12R1 register ******************/ -#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFFU) /*!< DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12R1_DACC1DHR_Pos (0U) +#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ /***************** Bit definition for DAC_DHR12L1 register ******************/ -#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0U) /*!< DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12L1_DACC1DHR_Pos (4U) +#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ /****************** Bit definition for DAC_DHR8R1 register ******************/ -#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FFU) /*!< DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8R1_DACC1DHR_Pos (0U) +#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ /***************** Bit definition for DAC_DHR12R2 register ******************/ -#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFFU) /*!< DAC channel2 12-bit Right aligned data */ +#define DAC_DHR12R2_DACC2DHR_Pos (0U) +#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ /***************** Bit definition for DAC_DHR12L2 register ******************/ -#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0U) /*!< DAC channel2 12-bit Left aligned data */ +#define DAC_DHR12L2_DACC2DHR_Pos (4U) +#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ /****************** Bit definition for DAC_DHR8R2 register ******************/ -#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FFU) /*!< DAC channel2 8-bit Right aligned data */ +#define DAC_DHR8R2_DACC2DHR_Pos (0U) +#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ /***************** Bit definition for DAC_DHR12RD register ******************/ -#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFFU) /*!< DAC channel1 12-bit Right aligned data */ -#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000U) /*!< DAC channel2 12-bit Right aligned data */ +#define DAC_DHR12RD_DACC1DHR_Pos (0U) +#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12RD_DACC2DHR_Pos (16U) +#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ /***************** Bit definition for DAC_DHR12LD register ******************/ -#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0U) /*!< DAC channel1 12-bit Left aligned data */ -#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000U) /*!< DAC channel2 12-bit Left aligned data */ +#define DAC_DHR12LD_DACC1DHR_Pos (4U) +#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12LD_DACC2DHR_Pos (20U) +#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ /****************** Bit definition for DAC_DHR8RD register ******************/ -#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FFU) /*!< DAC channel1 8-bit Right aligned data */ -#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00U) /*!< DAC channel2 8-bit Right aligned data */ +#define DAC_DHR8RD_DACC1DHR_Pos (0U) +#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8RD_DACC2DHR_Pos (8U) +#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ /******************* Bit definition for DAC_DOR1 register *******************/ -#define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFFU) /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFFU) /*!< DAC channel1 data output */ /******************* Bit definition for DAC_DOR2 register *******************/ -#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFFU) /*!< DAC channel2 data output */ +#define DAC_DOR2_DACC2DOR_Pos (0U) +#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */ /******************** Bit definition for DAC_SR register ********************/ -#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA underrun flag */ -#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000U) /*!< DAC channel2 DMA underrun flag */ +#define DAC_SR_DMAUDR1_Pos (13U) +#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ +#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_DMAUDR2_Pos (29U) +#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ +#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */ /******************************************************************************/ /* */ @@ -1170,49 +1486,91 @@ typedef struct /******************************************************************************/ /**************** Bit definition for DBGMCU_IDCODE register *****************/ -#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU) /*!< Device Identifier */ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ -#define DBGMCU_IDCODE_DIV_ID ((uint32_t)0x0000F000U) /*!< Division Identifier */ -#define DBGMCU_IDCODE_MCD_DIV_ID ((uint32_t)0x00006000U) /*!< MCD divsion ID is 6 */ -#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U) /*!< REV_ID[15:0] bits (Revision Identifier) */ -#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ -#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ -#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000U) /*!< Bit 2 */ -#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000U) /*!< Bit 3 */ -#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000U) /*!< Bit 4 */ -#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000U) /*!< Bit 5 */ -#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000U) /*!< Bit 6 */ -#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000U) /*!< Bit 7 */ -#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000U) /*!< Bit 8 */ -#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000U) /*!< Bit 9 */ -#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000U) /*!< Bit 10 */ -#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000U) /*!< Bit 11 */ -#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000U) /*!< Bit 12 */ -#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000U) /*!< Bit 13 */ -#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000U) /*!< Bit 14 */ -#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000U) /*!< Bit 15 */ +#define DBGMCU_IDCODE_DIV_ID_Pos (12U) +#define DBGMCU_IDCODE_DIV_ID_Msk (0xFU << DBGMCU_IDCODE_DIV_ID_Pos) /*!< 0x0000F000 */ +#define DBGMCU_IDCODE_DIV_ID DBGMCU_IDCODE_DIV_ID_Msk /*!< Division Identifier */ +#define DBGMCU_IDCODE_MCD_DIV_ID_Pos (13U) +#define DBGMCU_IDCODE_MCD_DIV_ID_Msk (0x3U << DBGMCU_IDCODE_MCD_DIV_ID_Pos) /*!< 0x00006000 */ +#define DBGMCU_IDCODE_MCD_DIV_ID DBGMCU_IDCODE_MCD_DIV_ID_Msk /*!< MCD divsion ID is 6 */ +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ +#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ +#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ +#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ +#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ +#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ +#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ +#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ +#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ +#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ +#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ +#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ +#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ +#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ +#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ +#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ +#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ /****************** Bit definition for DBGMCU_CR register *******************/ -#define DBGMCU_CR_DBG ((uint32_t)0x00000007U) /*!< Debug mode mask */ -#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001U) /*!< Debug Sleep Mode */ -#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U) /*!< Debug Stop Mode */ -#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U) /*!< Debug Standby mode */ +#define DBGMCU_CR_DBG_Pos (0U) +#define DBGMCU_CR_DBG_Msk (0x7U << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */ +#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */ +#define DBGMCU_CR_DBG_SLEEP_Pos (0U) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ /****************** Bit definition for DBGMCU_APB1_FZ register **************/ -#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001U) /*!< TIM2 counter stopped when core is halted */ -#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002U) -#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010U) /*!< TIM6 counter stopped when core is halted */ -#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020U) -#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400U) /*!< RTC Calendar frozen when core is halted */ -#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800U) /*!< Debug Window Watchdog stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000U) /*!< Debug Independent Watchdog stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_I2C1_STOP ((uint32_t)0x00200000U) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_I2C2_STOP ((uint32_t)0x00400000U) /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_I2C3_STOP ((uint32_t)0x00800000U) /*!< I2C3 SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP ((uint32_t)0x80000000U) /*!< LPTIM1 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) +#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk +#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) +#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) +#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk +#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) +#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */ +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U) +#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U) +#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */ +#define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos (23U) +#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */ +#define DBGMCU_APB1_FZ_DBG_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U) +#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */ +#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */ /****************** Bit definition for DBGMCU_APB2_FZ register **************/ -#define DBGMCU_APB2_FZ_DBG_TIM22_STOP ((uint32_t)0x00000020U) /*!< TIM22 counter stopped when core is halted */ -#define DBGMCU_APB2_FZ_DBG_TIM21_STOP ((uint32_t)0x00000004U) /*!< TIM21 counter stopped when core is halted */ +#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U) +#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */ +#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U) +#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */ /******************************************************************************/ /* */ @@ -1221,108 +1579,263 @@ typedef struct /******************************************************************************/ /******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error flag */ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ /******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt clear */ -#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error clear */ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ /******************* Bit definition for DMA_CCR register ********************/ -#define DMA_CCR_EN ((uint32_t)0x00000001U) /*!< Channel enable */ -#define DMA_CCR_TCIE ((uint32_t)0x00000002U) /*!< Transfer complete interrupt enable */ -#define DMA_CCR_HTIE ((uint32_t)0x00000004U) /*!< Half Transfer interrupt enable */ -#define DMA_CCR_TEIE ((uint32_t)0x00000008U) /*!< Transfer error interrupt enable */ -#define DMA_CCR_DIR ((uint32_t)0x00000010U) /*!< Data transfer direction */ -#define DMA_CCR_CIRC ((uint32_t)0x00000020U) /*!< Circular mode */ -#define DMA_CCR_PINC ((uint32_t)0x00000040U) /*!< Peripheral increment mode */ -#define DMA_CCR_MINC ((uint32_t)0x00000080U) /*!< Memory increment mode */ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ -#define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */ -#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */ +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ -#define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ -#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ -#define DMA_CCR_PL ((uint32_t)0x00003000U) /*!< PL[1:0] bits(Channel Priority level)*/ -#define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ -#define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ -#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /*!< Memory to memory mode */ +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ /****************** Bit definition for DMA_CNDTR register *******************/ -#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ /****************** Bit definition for DMA_CPAR register ********************/ -#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ /****************** Bit definition for DMA_CMAR register ********************/ -#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ /******************* Bit definition for DMA_CSELR register *******************/ -#define DMA_CSELR_C1S ((uint32_t)0x0000000FU) /*!< Channel 1 Selection */ -#define DMA_CSELR_C2S ((uint32_t)0x000000F0U) /*!< Channel 2 Selection */ -#define DMA_CSELR_C3S ((uint32_t)0x00000F00U) /*!< Channel 3 Selection */ -#define DMA_CSELR_C4S ((uint32_t)0x0000F000U) /*!< Channel 4 Selection */ -#define DMA_CSELR_C5S ((uint32_t)0x000F0000U) /*!< Channel 5 Selection */ -#define DMA_CSELR_C6S ((uint32_t)0x00F00000U) /*!< Channel 6 Selection */ -#define DMA_CSELR_C7S ((uint32_t)0x0F000000U) /*!< Channel 7 Selection */ - +#define DMA_CSELR_C1S_Pos (0U) +#define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */ +#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */ +#define DMA_CSELR_C2S_Pos (4U) +#define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */ +#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */ +#define DMA_CSELR_C3S_Pos (8U) +#define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */ +#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */ +#define DMA_CSELR_C4S_Pos (12U) +#define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */ +#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */ +#define DMA_CSELR_C5S_Pos (16U) +#define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */ +#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */ +#define DMA_CSELR_C6S_Pos (20U) +#define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */ +#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */ +#define DMA_CSELR_C7S_Pos (24U) +#define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */ +#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */ /******************************************************************************/ /* */ @@ -1331,90 +1844,254 @@ typedef struct /******************************************************************************/ /******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_IM0 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_IM1 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_IM2 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_IM3 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_IM4 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_IM5 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_IM6 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_IM7 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_IM8 ((uint32_t)0x00000100U) /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_IM9 ((uint32_t)0x00000200U) /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_IM10 ((uint32_t)0x00000400U) /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_IM11 ((uint32_t)0x00000800U) /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_IM12 ((uint32_t)0x00001000U) /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_IM13 ((uint32_t)0x00002000U) /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_IM14 ((uint32_t)0x00004000U) /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_IM15 ((uint32_t)0x00008000U) /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_IM16 ((uint32_t)0x00010000U) /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_IM17 ((uint32_t)0x00020000U) /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_IM18 ((uint32_t)0x00040000U) /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_IM19 ((uint32_t)0x00080000U) /*!< Interrupt Mask on line 19 */ -#define EXTI_IMR_IM20 ((uint32_t)0x00100000U) /*!< Interrupt Mask on line 20 */ -#define EXTI_IMR_IM21 ((uint32_t)0x00200000U) /*!< Interrupt Mask on line 21 */ -#define EXTI_IMR_IM22 ((uint32_t)0x00400000U) /*!< Interrupt Mask on line 22 */ -#define EXTI_IMR_IM23 ((uint32_t)0x00800000U) /*!< Interrupt Mask on line 23 */ -#define EXTI_IMR_IM24 ((uint32_t)0x01000000U) /*!< Interrupt Mask on line 24 */ -#define EXTI_IMR_IM25 ((uint32_t)0x02000000U) /*!< Interrupt Mask on line 25 */ -#define EXTI_IMR_IM26 ((uint32_t)0x04000000U) /*!< Interrupt Mask on line 26 */ -#define EXTI_IMR_IM28 ((uint32_t)0x10000000U) /*!< Interrupt Mask on line 28 */ -#define EXTI_IMR_IM29 ((uint32_t)0x20000000U) /*!< Interrupt Mask on line 29 */ +#define EXTI_IMR_IM0_Pos (0U) +#define EXTI_IMR_IM0_Msk (0x1U << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_IM1_Pos (1U) +#define EXTI_IMR_IM1_Msk (0x1U << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_IM2_Pos (2U) +#define EXTI_IMR_IM2_Msk (0x1U << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_IM3_Pos (3U) +#define EXTI_IMR_IM3_Msk (0x1U << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_IM4_Pos (4U) +#define EXTI_IMR_IM4_Msk (0x1U << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_IM5_Pos (5U) +#define EXTI_IMR_IM5_Msk (0x1U << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_IM6_Pos (6U) +#define EXTI_IMR_IM6_Msk (0x1U << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_IM7_Pos (7U) +#define EXTI_IMR_IM7_Msk (0x1U << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_IM8_Pos (8U) +#define EXTI_IMR_IM8_Msk (0x1U << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_IM9_Pos (9U) +#define EXTI_IMR_IM9_Msk (0x1U << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_IM10_Pos (10U) +#define EXTI_IMR_IM10_Msk (0x1U << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_IM11_Pos (11U) +#define EXTI_IMR_IM11_Msk (0x1U << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_IM12_Pos (12U) +#define EXTI_IMR_IM12_Msk (0x1U << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_IM13_Pos (13U) +#define EXTI_IMR_IM13_Msk (0x1U << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_IM14_Pos (14U) +#define EXTI_IMR_IM14_Msk (0x1U << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_IM15_Pos (15U) +#define EXTI_IMR_IM15_Msk (0x1U << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_IM16_Pos (16U) +#define EXTI_IMR_IM16_Msk (0x1U << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_IM17_Pos (17U) +#define EXTI_IMR_IM17_Msk (0x1U << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_IM18_Pos (18U) +#define EXTI_IMR_IM18_Msk (0x1U << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_IM19_Pos (19U) +#define EXTI_IMR_IM19_Msk (0x1U << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR_IM20_Pos (20U) +#define EXTI_IMR_IM20_Msk (0x1U << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */ +#define EXTI_IMR_IM21_Pos (21U) +#define EXTI_IMR_IM21_Msk (0x1U << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */ +#define EXTI_IMR_IM22_Pos (22U) +#define EXTI_IMR_IM22_Msk (0x1U << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */ +#define EXTI_IMR_IM23_Pos (23U) +#define EXTI_IMR_IM23_Msk (0x1U << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR_IM24_Pos (24U) +#define EXTI_IMR_IM24_Msk (0x1U << EXTI_IMR_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR_IM24 EXTI_IMR_IM24_Msk /*!< Interrupt Mask on line 24 */ +#define EXTI_IMR_IM25_Pos (25U) +#define EXTI_IMR_IM25_Msk (0x1U << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR_IM26_Pos (26U) +#define EXTI_IMR_IM26_Msk (0x1U << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */ +#define EXTI_IMR_IM28_Pos (28U) +#define EXTI_IMR_IM28_Msk (0x1U << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */ +#define EXTI_IMR_IM29_Pos (29U) +#define EXTI_IMR_IM29_Msk (0x1U << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */ + +#define EXTI_IMR_IM_Pos (0U) +#define EXTI_IMR_IM_Msk (0x37FFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x37FFFFFF */ +#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ /****************** Bit definition for EXTI_EMR register ********************/ -#define EXTI_EMR_EM0 ((uint32_t)0x00000001U) /*!< Event Mask on line 0 */ -#define EXTI_EMR_EM1 ((uint32_t)0x00000002U) /*!< Event Mask on line 1 */ -#define EXTI_EMR_EM2 ((uint32_t)0x00000004U) /*!< Event Mask on line 2 */ -#define EXTI_EMR_EM3 ((uint32_t)0x00000008U) /*!< Event Mask on line 3 */ -#define EXTI_EMR_EM4 ((uint32_t)0x00000010U) /*!< Event Mask on line 4 */ -#define EXTI_EMR_EM5 ((uint32_t)0x00000020U) /*!< Event Mask on line 5 */ -#define EXTI_EMR_EM6 ((uint32_t)0x00000040U) /*!< Event Mask on line 6 */ -#define EXTI_EMR_EM7 ((uint32_t)0x00000080U) /*!< Event Mask on line 7 */ -#define EXTI_EMR_EM8 ((uint32_t)0x00000100U) /*!< Event Mask on line 8 */ -#define EXTI_EMR_EM9 ((uint32_t)0x00000200U) /*!< Event Mask on line 9 */ -#define EXTI_EMR_EM10 ((uint32_t)0x00000400U) /*!< Event Mask on line 10 */ -#define EXTI_EMR_EM11 ((uint32_t)0x00000800U) /*!< Event Mask on line 11 */ -#define EXTI_EMR_EM12 ((uint32_t)0x00001000U) /*!< Event Mask on line 12 */ -#define EXTI_EMR_EM13 ((uint32_t)0x00002000U) /*!< Event Mask on line 13 */ -#define EXTI_EMR_EM14 ((uint32_t)0x00004000U) /*!< Event Mask on line 14 */ -#define EXTI_EMR_EM15 ((uint32_t)0x00008000U) /*!< Event Mask on line 15 */ -#define EXTI_EMR_EM16 ((uint32_t)0x00010000U) /*!< Event Mask on line 16 */ -#define EXTI_EMR_EM17 ((uint32_t)0x00020000U) /*!< Event Mask on line 17 */ -#define EXTI_EMR_EM18 ((uint32_t)0x00040000U) /*!< Event Mask on line 18 */ -#define EXTI_EMR_EM19 ((uint32_t)0x00080000U) /*!< Event Mask on line 19 */ -#define EXTI_EMR_EM20 ((uint32_t)0x00100000U) /*!< Event Mask on line 20 */ -#define EXTI_EMR_EM21 ((uint32_t)0x00200000U) /*!< Event Mask on line 21 */ -#define EXTI_EMR_EM22 ((uint32_t)0x00400000U) /*!< Event Mask on line 22 */ -#define EXTI_EMR_EM23 ((uint32_t)0x00800000U) /*!< Event Mask on line 23 */ -#define EXTI_EMR_EM24 ((uint32_t)0x01000000U) /*!< Event Mask on line 24 */ -#define EXTI_EMR_EM25 ((uint32_t)0x02000000U) /*!< Event Mask on line 25 */ -#define EXTI_EMR_EM26 ((uint32_t)0x04000000U) /*!< Event Mask on line 26 */ -#define EXTI_EMR_EM28 ((uint32_t)0x10000000U) /*!< Event Mask on line 28 */ -#define EXTI_EMR_EM29 ((uint32_t)0x20000000U) /*!< Event Mask on line 29 */ +#define EXTI_EMR_EM0_Pos (0U) +#define EXTI_EMR_EM0_Msk (0x1U << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR_EM1_Pos (1U) +#define EXTI_EMR_EM1_Msk (0x1U << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR_EM2_Pos (2U) +#define EXTI_EMR_EM2_Msk (0x1U << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR_EM3_Pos (3U) +#define EXTI_EMR_EM3_Msk (0x1U << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR_EM4_Pos (4U) +#define EXTI_EMR_EM4_Msk (0x1U << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR_EM5_Pos (5U) +#define EXTI_EMR_EM5_Msk (0x1U << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR_EM6_Pos (6U) +#define EXTI_EMR_EM6_Msk (0x1U << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR_EM7_Pos (7U) +#define EXTI_EMR_EM7_Msk (0x1U << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR_EM8_Pos (8U) +#define EXTI_EMR_EM8_Msk (0x1U << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR_EM9_Pos (9U) +#define EXTI_EMR_EM9_Msk (0x1U << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR_EM10_Pos (10U) +#define EXTI_EMR_EM10_Msk (0x1U << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR_EM11_Pos (11U) +#define EXTI_EMR_EM11_Msk (0x1U << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR_EM12_Pos (12U) +#define EXTI_EMR_EM12_Msk (0x1U << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR_EM13_Pos (13U) +#define EXTI_EMR_EM13_Msk (0x1U << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR_EM14_Pos (14U) +#define EXTI_EMR_EM14_Msk (0x1U << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR_EM15_Pos (15U) +#define EXTI_EMR_EM15_Msk (0x1U << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR_EM16_Pos (16U) +#define EXTI_EMR_EM16_Msk (0x1U << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR_EM17_Pos (17U) +#define EXTI_EMR_EM17_Msk (0x1U << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR_EM18_Pos (18U) +#define EXTI_EMR_EM18_Msk (0x1U << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */ +#define EXTI_EMR_EM19_Pos (19U) +#define EXTI_EMR_EM19_Msk (0x1U << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR_EM20_Pos (20U) +#define EXTI_EMR_EM20_Msk (0x1U << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */ +#define EXTI_EMR_EM21_Pos (21U) +#define EXTI_EMR_EM21_Msk (0x1U << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */ +#define EXTI_EMR_EM22_Pos (22U) +#define EXTI_EMR_EM22_Msk (0x1U << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */ +#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */ +#define EXTI_EMR_EM23_Pos (23U) +#define EXTI_EMR_EM23_Msk (0x1U << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR_EM24_Pos (24U) +#define EXTI_EMR_EM24_Msk (0x1U << EXTI_EMR_EM24_Pos) /*!< 0x01000000 */ +#define EXTI_EMR_EM24 EXTI_EMR_EM24_Msk /*!< Event Mask on line 24 */ +#define EXTI_EMR_EM25_Pos (25U) +#define EXTI_EMR_EM25_Msk (0x1U << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR_EM26_Pos (26U) +#define EXTI_EMR_EM26_Msk (0x1U << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */ +#define EXTI_EMR_EM28_Pos (28U) +#define EXTI_EMR_EM28_Msk (0x1U << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */ +#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */ +#define EXTI_EMR_EM29_Pos (29U) +#define EXTI_EMR_EM29_Msk (0x1U << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */ +#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */ /******************* Bit definition for EXTI_RTSR register ******************/ -#define EXTI_RTSR_RT0 ((uint32_t)0x00000001U) /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_RT1 ((uint32_t)0x00000002U) /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_RT2 ((uint32_t)0x00000004U) /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_RT3 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_RT4 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_RT5 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_RT6 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_RT7 ((uint32_t)0x00000080U) /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_RT8 ((uint32_t)0x00000100U) /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_RT9 ((uint32_t)0x00000200U) /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_RT10 ((uint32_t)0x00000400U) /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_RT11 ((uint32_t)0x00000800U) /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_RT12 ((uint32_t)0x00001000U) /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_RT13 ((uint32_t)0x00002000U) /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_RT14 ((uint32_t)0x00004000U) /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_RT15 ((uint32_t)0x00008000U) /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_RT16 ((uint32_t)0x00010000U) /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_RT17 ((uint32_t)0x00020000U) /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_RT19 ((uint32_t)0x00080000U) /*!< Rising trigger event configuration bit of line 19 */ -#define EXTI_RTSR_RT20 ((uint32_t)0x00100000U) /*!< Rising trigger event configuration bit of line 20 */ -#define EXTI_RTSR_RT21 ((uint32_t)0x00200000U) /*!< Rising trigger event configuration bit of line 21 */ -#define EXTI_RTSR_RT22 ((uint32_t)0x00400000U) /*!< Rising trigger event configuration bit of line 22 */ +#define EXTI_RTSR_RT0_Pos (0U) +#define EXTI_RTSR_RT0_Msk (0x1U << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_RT1_Pos (1U) +#define EXTI_RTSR_RT1_Msk (0x1U << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_RT2_Pos (2U) +#define EXTI_RTSR_RT2_Msk (0x1U << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_RT3_Pos (3U) +#define EXTI_RTSR_RT3_Msk (0x1U << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_RT4_Pos (4U) +#define EXTI_RTSR_RT4_Msk (0x1U << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_RT5_Pos (5U) +#define EXTI_RTSR_RT5_Msk (0x1U << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_RT6_Pos (6U) +#define EXTI_RTSR_RT6_Msk (0x1U << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_RT7_Pos (7U) +#define EXTI_RTSR_RT7_Msk (0x1U << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_RT8_Pos (8U) +#define EXTI_RTSR_RT8_Msk (0x1U << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_RT9_Pos (9U) +#define EXTI_RTSR_RT9_Msk (0x1U << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_RT10_Pos (10U) +#define EXTI_RTSR_RT10_Msk (0x1U << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_RT11_Pos (11U) +#define EXTI_RTSR_RT11_Msk (0x1U << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_RT12_Pos (12U) +#define EXTI_RTSR_RT12_Msk (0x1U << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_RT13_Pos (13U) +#define EXTI_RTSR_RT13_Msk (0x1U << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_RT14_Pos (14U) +#define EXTI_RTSR_RT14_Msk (0x1U << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_RT15_Pos (15U) +#define EXTI_RTSR_RT15_Msk (0x1U << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_RT16_Pos (16U) +#define EXTI_RTSR_RT16_Msk (0x1U << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_RT17_Pos (17U) +#define EXTI_RTSR_RT17_Msk (0x1U << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_RT19_Pos (19U) +#define EXTI_RTSR_RT19_Msk (0x1U << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */ +#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_RTSR_RT20_Pos (20U) +#define EXTI_RTSR_RT20_Msk (0x1U << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */ +#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ +#define EXTI_RTSR_RT21_Pos (21U) +#define EXTI_RTSR_RT21_Msk (0x1U << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */ +#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ +#define EXTI_RTSR_RT22_Pos (22U) +#define EXTI_RTSR_RT22_Msk (0x1U << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */ +#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */ /* Legacy defines */ #define EXTI_RTSR_TR0 EXTI_RTSR_RT0 @@ -1441,28 +2118,72 @@ typedef struct #define EXTI_RTSR_TR22 EXTI_RTSR_RT22 /******************* Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_FT0 ((uint32_t)0x00000001U) /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_FT1 ((uint32_t)0x00000002U) /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_FT2 ((uint32_t)0x00000004U) /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_FT3 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_FT4 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_FT5 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_FT6 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_FT7 ((uint32_t)0x00000080U) /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_FT8 ((uint32_t)0x00000100U) /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_FT9 ((uint32_t)0x00000200U) /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_FT10 ((uint32_t)0x00000400U) /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_FT11 ((uint32_t)0x00000800U) /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_FT12 ((uint32_t)0x00001000U) /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_FT13 ((uint32_t)0x00002000U) /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_FT14 ((uint32_t)0x00004000U) /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_FT15 ((uint32_t)0x00008000U) /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_FT16 ((uint32_t)0x00010000U) /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_FT17 ((uint32_t)0x00020000U) /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_FT19 ((uint32_t)0x00080000U) /*!< Falling trigger event configuration bit of line 19 */ -#define EXTI_FTSR_FT20 ((uint32_t)0x00100000U) /*!< Falling trigger event configuration bit of line 20 */ -#define EXTI_FTSR_FT21 ((uint32_t)0x00200000U) /*!< Falling trigger event configuration bit of line 21 */ -#define EXTI_FTSR_FT22 ((uint32_t)0x00400000U) /*!< Falling trigger event configuration bit of line 22 */ +#define EXTI_FTSR_FT0_Pos (0U) +#define EXTI_FTSR_FT0_Msk (0x1U << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_FT1_Pos (1U) +#define EXTI_FTSR_FT1_Msk (0x1U << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_FT2_Pos (2U) +#define EXTI_FTSR_FT2_Msk (0x1U << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_FT3_Pos (3U) +#define EXTI_FTSR_FT3_Msk (0x1U << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_FT4_Pos (4U) +#define EXTI_FTSR_FT4_Msk (0x1U << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_FT5_Pos (5U) +#define EXTI_FTSR_FT5_Msk (0x1U << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_FT6_Pos (6U) +#define EXTI_FTSR_FT6_Msk (0x1U << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_FT7_Pos (7U) +#define EXTI_FTSR_FT7_Msk (0x1U << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_FT8_Pos (8U) +#define EXTI_FTSR_FT8_Msk (0x1U << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_FT9_Pos (9U) +#define EXTI_FTSR_FT9_Msk (0x1U << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_FT10_Pos (10U) +#define EXTI_FTSR_FT10_Msk (0x1U << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_FT11_Pos (11U) +#define EXTI_FTSR_FT11_Msk (0x1U << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_FT12_Pos (12U) +#define EXTI_FTSR_FT12_Msk (0x1U << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_FT13_Pos (13U) +#define EXTI_FTSR_FT13_Msk (0x1U << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_FT14_Pos (14U) +#define EXTI_FTSR_FT14_Msk (0x1U << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_FT15_Pos (15U) +#define EXTI_FTSR_FT15_Msk (0x1U << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_FT16_Pos (16U) +#define EXTI_FTSR_FT16_Msk (0x1U << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_FT17_Pos (17U) +#define EXTI_FTSR_FT17_Msk (0x1U << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_FT19_Pos (19U) +#define EXTI_FTSR_FT19_Msk (0x1U << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */ +#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_FTSR_FT20_Pos (20U) +#define EXTI_FTSR_FT20_Msk (0x1U << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */ +#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */ +#define EXTI_FTSR_FT21_Pos (21U) +#define EXTI_FTSR_FT21_Msk (0x1U << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */ +#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ +#define EXTI_FTSR_FT22_Pos (22U) +#define EXTI_FTSR_FT22_Msk (0x1U << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */ +#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */ /* Legacy defines */ #define EXTI_FTSR_TR0 EXTI_FTSR_FT0 @@ -1489,28 +2210,72 @@ typedef struct #define EXTI_FTSR_TR22 EXTI_FTSR_FT22 /******************* Bit definition for EXTI_SWIER register *******************/ -#define EXTI_SWIER_SWI0 ((uint32_t)0x00000001U) /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWI1 ((uint32_t)0x00000002U) /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWI2 ((uint32_t)0x00000004U) /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWI3 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWI4 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWI5 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWI6 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWI7 ((uint32_t)0x00000080U) /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWI8 ((uint32_t)0x00000100U) /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWI9 ((uint32_t)0x00000200U) /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWI10 ((uint32_t)0x00000400U) /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWI11 ((uint32_t)0x00000800U) /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWI12 ((uint32_t)0x00001000U) /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWI13 ((uint32_t)0x00002000U) /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWI14 ((uint32_t)0x00004000U) /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWI15 ((uint32_t)0x00008000U) /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWI16 ((uint32_t)0x00010000U) /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWI17 ((uint32_t)0x00020000U) /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWI19 ((uint32_t)0x00080000U) /*!< Software Interrupt on line 19 */ -#define EXTI_SWIER_SWI20 ((uint32_t)0x00100000U) /*!< Software Interrupt on line 20 */ -#define EXTI_SWIER_SWI21 ((uint32_t)0x00200000U) /*!< Software Interrupt on line 21 */ -#define EXTI_SWIER_SWI22 ((uint32_t)0x00400000U) /*!< Software Interrupt on line 22 */ +#define EXTI_SWIER_SWI0_Pos (0U) +#define EXTI_SWIER_SWI0_Msk (0x1U << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWI1_Pos (1U) +#define EXTI_SWIER_SWI1_Msk (0x1U << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWI2_Pos (2U) +#define EXTI_SWIER_SWI2_Msk (0x1U << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWI3_Pos (3U) +#define EXTI_SWIER_SWI3_Msk (0x1U << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWI4_Pos (4U) +#define EXTI_SWIER_SWI4_Msk (0x1U << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWI5_Pos (5U) +#define EXTI_SWIER_SWI5_Msk (0x1U << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWI6_Pos (6U) +#define EXTI_SWIER_SWI6_Msk (0x1U << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWI7_Pos (7U) +#define EXTI_SWIER_SWI7_Msk (0x1U << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWI8_Pos (8U) +#define EXTI_SWIER_SWI8_Msk (0x1U << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWI9_Pos (9U) +#define EXTI_SWIER_SWI9_Msk (0x1U << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWI10_Pos (10U) +#define EXTI_SWIER_SWI10_Msk (0x1U << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWI11_Pos (11U) +#define EXTI_SWIER_SWI11_Msk (0x1U << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWI12_Pos (12U) +#define EXTI_SWIER_SWI12_Msk (0x1U << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWI13_Pos (13U) +#define EXTI_SWIER_SWI13_Msk (0x1U << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWI14_Pos (14U) +#define EXTI_SWIER_SWI14_Msk (0x1U << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWI15_Pos (15U) +#define EXTI_SWIER_SWI15_Msk (0x1U << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWI16_Pos (16U) +#define EXTI_SWIER_SWI16_Msk (0x1U << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWI17_Pos (17U) +#define EXTI_SWIER_SWI17_Msk (0x1U << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWI19_Pos (19U) +#define EXTI_SWIER_SWI19_Msk (0x1U << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */ +#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */ +#define EXTI_SWIER_SWI20_Pos (20U) +#define EXTI_SWIER_SWI20_Msk (0x1U << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */ +#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */ +#define EXTI_SWIER_SWI21_Pos (21U) +#define EXTI_SWIER_SWI21_Msk (0x1U << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */ +#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */ +#define EXTI_SWIER_SWI22_Pos (22U) +#define EXTI_SWIER_SWI22_Msk (0x1U << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */ +#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */ /* Legacy defines */ #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0 @@ -1537,28 +2302,72 @@ typedef struct #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22 /****************** Bit definition for EXTI_PR register *********************/ -#define EXTI_PR_PIF0 ((uint32_t)0x00000001U) /*!< Pending bit 0 */ -#define EXTI_PR_PIF1 ((uint32_t)0x00000002U) /*!< Pending bit 1 */ -#define EXTI_PR_PIF2 ((uint32_t)0x00000004U) /*!< Pending bit 2 */ -#define EXTI_PR_PIF3 ((uint32_t)0x00000008U) /*!< Pending bit 3 */ -#define EXTI_PR_PIF4 ((uint32_t)0x00000010U) /*!< Pending bit 4 */ -#define EXTI_PR_PIF5 ((uint32_t)0x00000020U) /*!< Pending bit 5 */ -#define EXTI_PR_PIF6 ((uint32_t)0x00000040U) /*!< Pending bit 6 */ -#define EXTI_PR_PIF7 ((uint32_t)0x00000080U) /*!< Pending bit 7 */ -#define EXTI_PR_PIF8 ((uint32_t)0x00000100U) /*!< Pending bit 8 */ -#define EXTI_PR_PIF9 ((uint32_t)0x00000200U) /*!< Pending bit 9 */ -#define EXTI_PR_PIF10 ((uint32_t)0x00000400U) /*!< Pending bit 10 */ -#define EXTI_PR_PIF11 ((uint32_t)0x00000800U) /*!< Pending bit 11 */ -#define EXTI_PR_PIF12 ((uint32_t)0x00001000U) /*!< Pending bit 12 */ -#define EXTI_PR_PIF13 ((uint32_t)0x00002000U) /*!< Pending bit 13 */ -#define EXTI_PR_PIF14 ((uint32_t)0x00004000U) /*!< Pending bit 14 */ -#define EXTI_PR_PIF15 ((uint32_t)0x00008000U) /*!< Pending bit 15 */ -#define EXTI_PR_PIF16 ((uint32_t)0x00010000U) /*!< Pending bit 16 */ -#define EXTI_PR_PIF17 ((uint32_t)0x00020000U) /*!< Pending bit 17 */ -#define EXTI_PR_PIF19 ((uint32_t)0x00080000U) /*!< Pending bit 19 */ -#define EXTI_PR_PIF20 ((uint32_t)0x00100000U) /*!< Pending bit 20 */ -#define EXTI_PR_PIF21 ((uint32_t)0x00200000U) /*!< Pending bit 21 */ -#define EXTI_PR_PIF22 ((uint32_t)0x00400000U) /*!< Pending bit 22 */ +#define EXTI_PR_PIF0_Pos (0U) +#define EXTI_PR_PIF0_Msk (0x1U << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */ +#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */ +#define EXTI_PR_PIF1_Pos (1U) +#define EXTI_PR_PIF1_Msk (0x1U << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */ +#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */ +#define EXTI_PR_PIF2_Pos (2U) +#define EXTI_PR_PIF2_Msk (0x1U << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */ +#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */ +#define EXTI_PR_PIF3_Pos (3U) +#define EXTI_PR_PIF3_Msk (0x1U << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */ +#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */ +#define EXTI_PR_PIF4_Pos (4U) +#define EXTI_PR_PIF4_Msk (0x1U << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */ +#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */ +#define EXTI_PR_PIF5_Pos (5U) +#define EXTI_PR_PIF5_Msk (0x1U << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */ +#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */ +#define EXTI_PR_PIF6_Pos (6U) +#define EXTI_PR_PIF6_Msk (0x1U << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */ +#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */ +#define EXTI_PR_PIF7_Pos (7U) +#define EXTI_PR_PIF7_Msk (0x1U << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */ +#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */ +#define EXTI_PR_PIF8_Pos (8U) +#define EXTI_PR_PIF8_Msk (0x1U << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */ +#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */ +#define EXTI_PR_PIF9_Pos (9U) +#define EXTI_PR_PIF9_Msk (0x1U << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */ +#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */ +#define EXTI_PR_PIF10_Pos (10U) +#define EXTI_PR_PIF10_Msk (0x1U << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */ +#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */ +#define EXTI_PR_PIF11_Pos (11U) +#define EXTI_PR_PIF11_Msk (0x1U << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */ +#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */ +#define EXTI_PR_PIF12_Pos (12U) +#define EXTI_PR_PIF12_Msk (0x1U << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */ +#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */ +#define EXTI_PR_PIF13_Pos (13U) +#define EXTI_PR_PIF13_Msk (0x1U << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */ +#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */ +#define EXTI_PR_PIF14_Pos (14U) +#define EXTI_PR_PIF14_Msk (0x1U << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */ +#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */ +#define EXTI_PR_PIF15_Pos (15U) +#define EXTI_PR_PIF15_Msk (0x1U << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */ +#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */ +#define EXTI_PR_PIF16_Pos (16U) +#define EXTI_PR_PIF16_Msk (0x1U << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */ +#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */ +#define EXTI_PR_PIF17_Pos (17U) +#define EXTI_PR_PIF17_Msk (0x1U << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */ +#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */ +#define EXTI_PR_PIF19_Pos (19U) +#define EXTI_PR_PIF19_Msk (0x1U << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */ +#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */ +#define EXTI_PR_PIF20_Pos (20U) +#define EXTI_PR_PIF20_Msk (0x1U << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */ +#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */ +#define EXTI_PR_PIF21_Pos (21U) +#define EXTI_PR_PIF21_Msk (0x1U << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */ +#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */ +#define EXTI_PR_PIF22_Pos (22U) +#define EXTI_PR_PIF22_Msk (0x1U << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */ +#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */ /* Legacy defines */ #define EXTI_PR_PR0 EXTI_PR_PIF0 @@ -1591,54 +2400,124 @@ typedef struct /******************************************************************************/ /******************* Bit definition for FLASH_ACR register ******************/ -#define FLASH_ACR_LATENCY ((uint32_t)0x00000001U) /*!< LATENCY bit (Latency) */ -#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002U) /*!< Prefetch Buffer Enable */ -#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008U) /*!< Flash mode during sleep mode */ -#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010U) /*!< Flash mode during RUN mode */ -#define FLASH_ACR_DISAB_BUF ((uint32_t)0x00000020U) /*!< Disable Buffer */ -#define FLASH_ACR_PRE_READ ((uint32_t)0x00000040U) /*!< Pre-read data address */ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */ +#define FLASH_ACR_PRFTEN_Pos (1U) +#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */ +#define FLASH_ACR_SLEEP_PD_Pos (3U) +#define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */ +#define FLASH_ACR_RUN_PD_Pos (4U) +#define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */ +#define FLASH_ACR_DISAB_BUF_Pos (5U) +#define FLASH_ACR_DISAB_BUF_Msk (0x1U << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */ +#define FLASH_ACR_PRE_READ_Pos (6U) +#define FLASH_ACR_PRE_READ_Msk (0x1U << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */ +#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */ /******************* Bit definition for FLASH_PECR register ******************/ -#define FLASH_PECR_PELOCK ((uint32_t)0x00000001U) /*!< FLASH_PECR and Flash data Lock */ -#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002U) /*!< Program matrix Lock */ -#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004U) /*!< Option byte matrix Lock */ -#define FLASH_PECR_PROG ((uint32_t)0x00000008U) /*!< Program matrix selection */ -#define FLASH_PECR_DATA ((uint32_t)0x00000010U) /*!< Data matrix selection */ -#define FLASH_PECR_FIX ((uint32_t)0x00000100U) /*!< Fixed Time Data write for Word/Half Word/Byte programming */ -#define FLASH_PECR_ERASE ((uint32_t)0x00000200U) /*!< Page erasing mode */ -#define FLASH_PECR_FPRG ((uint32_t)0x00000400U) /*!< Fast Page/Half Page programming mode */ -#define FLASH_PECR_PARALLBANK ((uint32_t)0x00008000U) /*!< Parallel Bank mode */ -#define FLASH_PECR_EOPIE ((uint32_t)0x00010000U) /*!< End of programming interrupt */ -#define FLASH_PECR_ERRIE ((uint32_t)0x00020000U) /*!< Error interrupt */ -#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000U) /*!< Launch the option byte loading */ -#define FLASH_PECR_HALF_ARRAY ((uint32_t)0x00080000U) /*!< Half array mode */ -#define FLASH_PECR_NZDISABLE ((uint32_t)0x00400000U) /*!< Non-Zero check disable */ +#define FLASH_PECR_PELOCK_Pos (0U) +#define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */ +#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */ +#define FLASH_PECR_PRGLOCK_Pos (1U) +#define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */ +#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */ +#define FLASH_PECR_OPTLOCK_Pos (2U) +#define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */ +#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */ +#define FLASH_PECR_PROG_Pos (3U) +#define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */ +#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */ +#define FLASH_PECR_DATA_Pos (4U) +#define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */ +#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */ +#define FLASH_PECR_FIX_Pos (8U) +#define FLASH_PECR_FIX_Msk (0x1U << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */ +#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */ +#define FLASH_PECR_ERASE_Pos (9U) +#define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */ +#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */ +#define FLASH_PECR_FPRG_Pos (10U) +#define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */ +#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */ +#define FLASH_PECR_PARALLBANK_Pos (15U) +#define FLASH_PECR_PARALLBANK_Msk (0x1U << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */ +#define FLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_Msk /*!< Parallel Bank mode */ +#define FLASH_PECR_EOPIE_Pos (16U) +#define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */ +#define FLASH_PECR_ERRIE_Pos (17U) +#define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */ +#define FLASH_PECR_OBL_LAUNCH_Pos (18U) +#define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */ +#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */ +#define FLASH_PECR_HALF_ARRAY_Pos (19U) +#define FLASH_PECR_HALF_ARRAY_Msk (0x1U << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */ +#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */ +#define FLASH_PECR_NZDISABLE_Pos (22U) +#define FLASH_PECR_NZDISABLE_Msk (0x1U << FLASH_PECR_NZDISABLE_Pos) /*!< 0x00400000 */ +#define FLASH_PECR_NZDISABLE FLASH_PECR_NZDISABLE_Msk /*!< Non-Zero check disable */ /****************** Bit definition for FLASH_PDKEYR register ******************/ -#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */ +#define FLASH_PDKEYR_PDKEYR_Pos (0U) +#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */ /****************** Bit definition for FLASH_PEKEYR register ******************/ -#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */ +#define FLASH_PEKEYR_PEKEYR_Pos (0U) +#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */ /****************** Bit definition for FLASH_PRGKEYR register ******************/ -#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFFU) /*!< Program matrix Key */ +#define FLASH_PRGKEYR_PRGKEYR_Pos (0U) +#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */ /****************** Bit definition for FLASH_OPTKEYR register ******************/ -#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFFU) /*!< Option bytes matrix Key */ +#define FLASH_OPTKEYR_OPTKEYR_Pos (0U) +#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */ /****************** Bit definition for FLASH_SR register *******************/ -#define FLASH_SR_BSY ((uint32_t)0x00000001U) /*!< Busy */ -#define FLASH_SR_EOP ((uint32_t)0x00000002U) /*!< End Of Programming*/ -#define FLASH_SR_HVOFF ((uint32_t)0x00000004U) /*!< End of high voltage */ -#define FLASH_SR_READY ((uint32_t)0x00000008U) /*!< Flash ready after low power mode */ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ +#define FLASH_SR_EOP_Pos (1U) +#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000002 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/ +#define FLASH_SR_HVOFF_Pos (2U) +#define FLASH_SR_HVOFF_Msk (0x1U << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */ +#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */ +#define FLASH_SR_READY_Pos (3U) +#define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /*!< 0x00000008 */ +#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */ -#define FLASH_SR_WRPERR ((uint32_t)0x00000100U) /*!< Write protection error */ -#define FLASH_SR_PGAERR ((uint32_t)0x00000200U) /*!< Programming Alignment Error */ -#define FLASH_SR_SIZERR ((uint32_t)0x00000400U) /*!< Size error */ -#define FLASH_SR_OPTVERR ((uint32_t)0x00000800U) /*!< Option Valid error */ -#define FLASH_SR_RDERR ((uint32_t)0x00002000U) /*!< Read protected error */ -#define FLASH_SR_NOTZEROERR ((uint32_t)0x00010000U) /*!< Not Zero error */ -#define FLASH_SR_FWWERR ((uint32_t)0x00020000U) /*!< Write/Errase operation aborted */ +#define FLASH_SR_WRPERR_Pos (8U) +#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */ +#define FLASH_SR_PGAERR_Pos (9U) +#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */ +#define FLASH_SR_SIZERR_Pos (10U) +#define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ +#define FLASH_SR_OPTVERR_Pos (11U) +#define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */ +#define FLASH_SR_RDERR_Pos (13U) +#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */ +#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */ +#define FLASH_SR_NOTZEROERR_Pos (16U) +#define FLASH_SR_NOTZEROERR_Msk (0x1U << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */ +#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */ +#define FLASH_SR_FWWERR_Pos (17U) +#define FLASH_SR_FWWERR_Msk (0x1U << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */ /* Legacy defines */ #define FLASH_SR_FWWER FLASH_SR_FWWERR @@ -1646,18 +2525,38 @@ typedef struct #define FLASH_SR_ENDHV FLASH_SR_HVOFF /****************** Bit definition for FLASH_OPTR register *******************/ -#define FLASH_OPTR_RDPROT ((uint32_t)0x000000FFU) /*!< Read Protection */ -#define FLASH_OPTR_WPRMOD ((uint32_t)0x00000100U) /*!< Selection of protection mode of WPR bits */ -#define FLASH_OPTR_BOR_LEV ((uint32_t)0x000F0000U) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ -#define FLASH_OPTR_IWDG_SW ((uint32_t)0x00100000U) /*!< IWDG_SW */ -#define FLASH_OPTR_nRST_STOP ((uint32_t)0x00200000U) /*!< nRST_STOP */ -#define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00400000U) /*!< nRST_STDBY */ -#define FLASH_OPTR_BFB2 ((uint32_t)0x00800000U) /*!< BFB2 */ -#define FLASH_OPTR_USER ((uint32_t)0x00700000U) /*!< User Option Bytes */ -#define FLASH_OPTR_BOOT1 ((uint32_t)0x80000000U) /*!< BOOT1 */ +#define FLASH_OPTR_RDPROT_Pos (0U) +#define FLASH_OPTR_RDPROT_Msk (0xFFU << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */ +#define FLASH_OPTR_WPRMOD_Pos (8U) +#define FLASH_OPTR_WPRMOD_Msk (0x1U << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */ +#define FLASH_OPTR_BOR_LEV_Pos (16U) +#define FLASH_OPTR_BOR_LEV_Msk (0xFU << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ +#define FLASH_OPTR_IWDG_SW_Pos (20U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */ +#define FLASH_OPTR_nRST_STOP_Pos (21U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (22U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_BFB2_Pos (23U) +#define FLASH_OPTR_BFB2_Msk (0x1U << FLASH_OPTR_BFB2_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk /*!< BFB2 */ +#define FLASH_OPTR_USER_Pos (20U) +#define FLASH_OPTR_USER_Msk (0x7U << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */ +#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */ +#define FLASH_OPTR_BOOT1_Pos (31U) +#define FLASH_OPTR_BOOT1_Msk (0x1U << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */ /****************** Bit definition for FLASH_WRPR register ******************/ -#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFFU) /*!< Write Protection bits */ +#define FLASH_WRPR_WRP_Pos (0U) +#define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */ /******************************************************************************/ /* */ @@ -1665,299 +2564,525 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0 ((uint32_t)0x00000003U) -#define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001U) -#define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002U) -#define GPIO_MODER_MODE1 ((uint32_t)0x0000000CU) -#define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004U) -#define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008U) -#define GPIO_MODER_MODE2 ((uint32_t)0x00000030U) -#define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010U) -#define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020U) -#define GPIO_MODER_MODE3 ((uint32_t)0x000000C0U) -#define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040U) -#define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080U) -#define GPIO_MODER_MODE4 ((uint32_t)0x00000300U) -#define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100U) -#define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200U) -#define GPIO_MODER_MODE5 ((uint32_t)0x00000C00U) -#define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400U) -#define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800U) -#define GPIO_MODER_MODE6 ((uint32_t)0x00003000U) -#define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000U) -#define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000U) -#define GPIO_MODER_MODE7 ((uint32_t)0x0000C000U) -#define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000U) -#define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000U) -#define GPIO_MODER_MODE8 ((uint32_t)0x00030000U) -#define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000U) -#define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000U) -#define GPIO_MODER_MODE9 ((uint32_t)0x000C0000U) -#define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000U) -#define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000U) -#define GPIO_MODER_MODE10 ((uint32_t)0x00300000U) -#define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000U) -#define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000U) -#define GPIO_MODER_MODE11 ((uint32_t)0x00C00000U) -#define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000U) -#define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000U) -#define GPIO_MODER_MODE12 ((uint32_t)0x03000000U) -#define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000U) -#define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000U) -#define GPIO_MODER_MODE13 ((uint32_t)0x0C000000U) -#define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000U) -#define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000U) -#define GPIO_MODER_MODE14 ((uint32_t)0x30000000U) -#define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000U) -#define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000U) -#define GPIO_MODER_MODE15 ((uint32_t)0xC0000000U) -#define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000U) -#define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000U) +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_OTYPER register *****************/ -#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001U) -#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002U) -#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004U) -#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008U) -#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010U) -#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020U) -#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040U) -#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080U) -#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100U) -#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200U) -#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400U) -#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800U) -#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000U) -#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000U) -#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000U) -#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000U) +#define GPIO_OTYPER_OT_0 (0x00000001U) +#define GPIO_OTYPER_OT_1 (0x00000002U) +#define GPIO_OTYPER_OT_2 (0x00000004U) +#define GPIO_OTYPER_OT_3 (0x00000008U) +#define GPIO_OTYPER_OT_4 (0x00000010U) +#define GPIO_OTYPER_OT_5 (0x00000020U) +#define GPIO_OTYPER_OT_6 (0x00000040U) +#define GPIO_OTYPER_OT_7 (0x00000080U) +#define GPIO_OTYPER_OT_8 (0x00000100U) +#define GPIO_OTYPER_OT_9 (0x00000200U) +#define GPIO_OTYPER_OT_10 (0x00000400U) +#define GPIO_OTYPER_OT_11 (0x00000800U) +#define GPIO_OTYPER_OT_12 (0x00001000U) +#define GPIO_OTYPER_OT_13 (0x00002000U) +#define GPIO_OTYPER_OT_14 (0x00004000U) +#define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0 ((uint32_t)0x00000003U) -#define GPIO_OSPEEDER_OSPEED0_0 ((uint32_t)0x00000001U) -#define GPIO_OSPEEDER_OSPEED0_1 ((uint32_t)0x00000002U) -#define GPIO_OSPEEDER_OSPEED1 ((uint32_t)0x0000000CU) -#define GPIO_OSPEEDER_OSPEED1_0 ((uint32_t)0x00000004U) -#define GPIO_OSPEEDER_OSPEED1_1 ((uint32_t)0x00000008U) -#define GPIO_OSPEEDER_OSPEED2 ((uint32_t)0x00000030U) -#define GPIO_OSPEEDER_OSPEED2_0 ((uint32_t)0x00000010U) -#define GPIO_OSPEEDER_OSPEED2_1 ((uint32_t)0x00000020U) -#define GPIO_OSPEEDER_OSPEED3 ((uint32_t)0x000000C0U) -#define GPIO_OSPEEDER_OSPEED3_0 ((uint32_t)0x00000040U) -#define GPIO_OSPEEDER_OSPEED3_1 ((uint32_t)0x00000080U) -#define GPIO_OSPEEDER_OSPEED4 ((uint32_t)0x00000300U) -#define GPIO_OSPEEDER_OSPEED4_0 ((uint32_t)0x00000100U) -#define GPIO_OSPEEDER_OSPEED4_1 ((uint32_t)0x00000200U) -#define GPIO_OSPEEDER_OSPEED5 ((uint32_t)0x00000C00U) -#define GPIO_OSPEEDER_OSPEED5_0 ((uint32_t)0x00000400U) -#define GPIO_OSPEEDER_OSPEED5_1 ((uint32_t)0x00000800U) -#define GPIO_OSPEEDER_OSPEED6 ((uint32_t)0x00003000U) -#define GPIO_OSPEEDER_OSPEED6_0 ((uint32_t)0x00001000U) -#define GPIO_OSPEEDER_OSPEED6_1 ((uint32_t)0x00002000U) -#define GPIO_OSPEEDER_OSPEED7 ((uint32_t)0x0000C000U) -#define GPIO_OSPEEDER_OSPEED7_0 ((uint32_t)0x00004000U) -#define GPIO_OSPEEDER_OSPEED7_1 ((uint32_t)0x00008000U) -#define GPIO_OSPEEDER_OSPEED8 ((uint32_t)0x00030000U) -#define GPIO_OSPEEDER_OSPEED8_0 ((uint32_t)0x00010000U) -#define GPIO_OSPEEDER_OSPEED8_1 ((uint32_t)0x00020000U) -#define GPIO_OSPEEDER_OSPEED9 ((uint32_t)0x000C0000U) -#define GPIO_OSPEEDER_OSPEED9_0 ((uint32_t)0x00040000U) -#define GPIO_OSPEEDER_OSPEED9_1 ((uint32_t)0x00080000U) -#define GPIO_OSPEEDER_OSPEED10 ((uint32_t)0x00300000U) -#define GPIO_OSPEEDER_OSPEED10_0 ((uint32_t)0x00100000U) -#define GPIO_OSPEEDER_OSPEED10_1 ((uint32_t)0x00200000U) -#define GPIO_OSPEEDER_OSPEED11 ((uint32_t)0x00C00000U) -#define GPIO_OSPEEDER_OSPEED11_0 ((uint32_t)0x00400000U) -#define GPIO_OSPEEDER_OSPEED11_1 ((uint32_t)0x00800000U) -#define GPIO_OSPEEDER_OSPEED12 ((uint32_t)0x03000000U) -#define GPIO_OSPEEDER_OSPEED12_0 ((uint32_t)0x01000000U) -#define GPIO_OSPEEDER_OSPEED12_1 ((uint32_t)0x02000000U) -#define GPIO_OSPEEDER_OSPEED13 ((uint32_t)0x0C000000U) -#define GPIO_OSPEEDER_OSPEED13_0 ((uint32_t)0x04000000U) -#define GPIO_OSPEEDER_OSPEED13_1 ((uint32_t)0x08000000U) -#define GPIO_OSPEEDER_OSPEED14 ((uint32_t)0x30000000U) -#define GPIO_OSPEEDER_OSPEED14_0 ((uint32_t)0x10000000U) -#define GPIO_OSPEEDER_OSPEED14_1 ((uint32_t)0x20000000U) -#define GPIO_OSPEEDER_OSPEED15 ((uint32_t)0xC0000000U) -#define GPIO_OSPEEDER_OSPEED15_0 ((uint32_t)0x40000000U) -#define GPIO_OSPEEDER_OSPEED15_1 ((uint32_t)0x80000000U) +#define GPIO_OSPEEDER_OSPEED0_Pos (0U) +#define GPIO_OSPEEDER_OSPEED0_Msk (0x3U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0_0 (0x1U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDER_OSPEED0_1 (0x2U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDER_OSPEED1_Pos (2U) +#define GPIO_OSPEEDER_OSPEED1_Msk (0x3U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1_0 (0x1U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDER_OSPEED1_1 (0x2U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDER_OSPEED2_Pos (4U) +#define GPIO_OSPEEDER_OSPEED2_Msk (0x3U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2_0 (0x1U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDER_OSPEED2_1 (0x2U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDER_OSPEED3_Pos (6U) +#define GPIO_OSPEEDER_OSPEED3_Msk (0x3U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3_0 (0x1U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDER_OSPEED3_1 (0x2U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDER_OSPEED4_Pos (8U) +#define GPIO_OSPEEDER_OSPEED4_Msk (0x3U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4_0 (0x1U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDER_OSPEED4_1 (0x2U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDER_OSPEED5_Pos (10U) +#define GPIO_OSPEEDER_OSPEED5_Msk (0x3U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5_0 (0x1U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDER_OSPEED5_1 (0x2U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDER_OSPEED6_Pos (12U) +#define GPIO_OSPEEDER_OSPEED6_Msk (0x3U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6_0 (0x1U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDER_OSPEED6_1 (0x2U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDER_OSPEED7_Pos (14U) +#define GPIO_OSPEEDER_OSPEED7_Msk (0x3U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7_0 (0x1U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDER_OSPEED7_1 (0x2U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDER_OSPEED8_Pos (16U) +#define GPIO_OSPEEDER_OSPEED8_Msk (0x3U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8_0 (0x1U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDER_OSPEED8_1 (0x2U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDER_OSPEED9_Pos (18U) +#define GPIO_OSPEEDER_OSPEED9_Msk (0x3U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9_0 (0x1U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDER_OSPEED9_1 (0x2U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDER_OSPEED10_Pos (20U) +#define GPIO_OSPEEDER_OSPEED10_Msk (0x3U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10_0 (0x1U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDER_OSPEED10_1 (0x2U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDER_OSPEED11_Pos (22U) +#define GPIO_OSPEEDER_OSPEED11_Msk (0x3U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11_0 (0x1U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDER_OSPEED11_1 (0x2U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDER_OSPEED12_Pos (24U) +#define GPIO_OSPEEDER_OSPEED12_Msk (0x3U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12_0 (0x1U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDER_OSPEED12_1 (0x2U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDER_OSPEED13_Pos (26U) +#define GPIO_OSPEEDER_OSPEED13_Msk (0x3U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13_0 (0x1U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDER_OSPEED13_1 (0x2U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDER_OSPEED14_Pos (28U) +#define GPIO_OSPEEDER_OSPEED14_Msk (0x3U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14_0 (0x1U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDER_OSPEED14_1 (0x2U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDER_OSPEED15_Pos (30U) +#define GPIO_OSPEEDER_OSPEED15_Msk (0x3U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15_0 (0x1U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDER_OSPEED15_1 (0x2U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ /******************* Bit definition for GPIO_PUPDR register ******************/ -#define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003U) -#define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001U) -#define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002U) -#define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000CU) -#define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004U) -#define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008U) -#define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030U) -#define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010U) -#define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020U) -#define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0U) -#define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040U) -#define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080U) -#define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300U) -#define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100U) -#define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200U) -#define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00U) -#define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400U) -#define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800U) -#define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000U) -#define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000U) -#define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000U) -#define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000U) -#define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000U) -#define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000U) -#define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000U) -#define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000U) -#define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000U) -#define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000U) -#define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000U) -#define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000U) -#define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000U) -#define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000U) -#define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000U) -#define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000U) -#define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000U) -#define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000U) -#define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000U) -#define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000U) -#define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000U) -#define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000U) -#define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000U) -#define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000U) -#define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000U) -#define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000U) -#define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000U) -#define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000U) -#define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000U) -#define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000U) +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ /******************* Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0 ((uint32_t)0x00000001U) -#define GPIO_IDR_ID1 ((uint32_t)0x00000002U) -#define GPIO_IDR_ID2 ((uint32_t)0x00000004U) -#define GPIO_IDR_ID3 ((uint32_t)0x00000008U) -#define GPIO_IDR_ID4 ((uint32_t)0x00000010U) -#define GPIO_IDR_ID5 ((uint32_t)0x00000020U) -#define GPIO_IDR_ID6 ((uint32_t)0x00000040U) -#define GPIO_IDR_ID7 ((uint32_t)0x00000080U) -#define GPIO_IDR_ID8 ((uint32_t)0x00000100U) -#define GPIO_IDR_ID9 ((uint32_t)0x00000200U) -#define GPIO_IDR_ID10 ((uint32_t)0x00000400U) -#define GPIO_IDR_ID11 ((uint32_t)0x00000800U) -#define GPIO_IDR_ID12 ((uint32_t)0x00001000U) -#define GPIO_IDR_ID13 ((uint32_t)0x00002000U) -#define GPIO_IDR_ID14 ((uint32_t)0x00004000U) -#define GPIO_IDR_ID15 ((uint32_t)0x00008000U) +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk /****************** Bit definition for GPIO_ODR register ********************/ -#define GPIO_ODR_OD0 ((uint32_t)0x00000001U) -#define GPIO_ODR_OD1 ((uint32_t)0x00000002U) -#define GPIO_ODR_OD2 ((uint32_t)0x00000004U) -#define GPIO_ODR_OD3 ((uint32_t)0x00000008U) -#define GPIO_ODR_OD4 ((uint32_t)0x00000010U) -#define GPIO_ODR_OD5 ((uint32_t)0x00000020U) -#define GPIO_ODR_OD6 ((uint32_t)0x00000040U) -#define GPIO_ODR_OD7 ((uint32_t)0x00000080U) -#define GPIO_ODR_OD8 ((uint32_t)0x00000100U) -#define GPIO_ODR_OD9 ((uint32_t)0x00000200U) -#define GPIO_ODR_OD10 ((uint32_t)0x00000400U) -#define GPIO_ODR_OD11 ((uint32_t)0x00000800U) -#define GPIO_ODR_OD12 ((uint32_t)0x00001000U) -#define GPIO_ODR_OD13 ((uint32_t)0x00002000U) -#define GPIO_ODR_OD14 ((uint32_t)0x00004000U) -#define GPIO_ODR_OD15 ((uint32_t)0x00008000U) +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk /****************** Bit definition for GPIO_BSRR register ********************/ -#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001U) -#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002U) -#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004U) -#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008U) -#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010U) -#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020U) -#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040U) -#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080U) -#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100U) -#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200U) -#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400U) -#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800U) -#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000U) -#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000U) -#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000U) -#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000U) -#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000U) -#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000U) -#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000U) -#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000U) -#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000U) -#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000U) -#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000U) -#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000U) -#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000U) -#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000U) -#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000U) -#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000U) -#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000U) -#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000U) -#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000U) -#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000U) +#define GPIO_BSRR_BS_0 (0x00000001U) +#define GPIO_BSRR_BS_1 (0x00000002U) +#define GPIO_BSRR_BS_2 (0x00000004U) +#define GPIO_BSRR_BS_3 (0x00000008U) +#define GPIO_BSRR_BS_4 (0x00000010U) +#define GPIO_BSRR_BS_5 (0x00000020U) +#define GPIO_BSRR_BS_6 (0x00000040U) +#define GPIO_BSRR_BS_7 (0x00000080U) +#define GPIO_BSRR_BS_8 (0x00000100U) +#define GPIO_BSRR_BS_9 (0x00000200U) +#define GPIO_BSRR_BS_10 (0x00000400U) +#define GPIO_BSRR_BS_11 (0x00000800U) +#define GPIO_BSRR_BS_12 (0x00001000U) +#define GPIO_BSRR_BS_13 (0x00002000U) +#define GPIO_BSRR_BS_14 (0x00004000U) +#define GPIO_BSRR_BS_15 (0x00008000U) +#define GPIO_BSRR_BR_0 (0x00010000U) +#define GPIO_BSRR_BR_1 (0x00020000U) +#define GPIO_BSRR_BR_2 (0x00040000U) +#define GPIO_BSRR_BR_3 (0x00080000U) +#define GPIO_BSRR_BR_4 (0x00100000U) +#define GPIO_BSRR_BR_5 (0x00200000U) +#define GPIO_BSRR_BR_6 (0x00400000U) +#define GPIO_BSRR_BR_7 (0x00800000U) +#define GPIO_BSRR_BR_8 (0x01000000U) +#define GPIO_BSRR_BR_9 (0x02000000U) +#define GPIO_BSRR_BR_10 (0x04000000U) +#define GPIO_BSRR_BR_11 (0x08000000U) +#define GPIO_BSRR_BR_12 (0x10000000U) +#define GPIO_BSRR_BR_13 (0x20000000U) +#define GPIO_BSRR_BR_14 (0x40000000U) +#define GPIO_BSRR_BR_15 (0x80000000U) /****************** Bit definition for GPIO_LCKR register ********************/ -#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U) -#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U) -#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U) -#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U) -#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U) -#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U) -#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U) -#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U) -#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U) -#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U) -#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U) -#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U) -#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U) -#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U) -#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U) -#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U) -#define GPIO_LCKR_LCKK ((uint32_t)0x00010000U) +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000FU) -#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0U) -#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00U) -#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000U) -#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000U) -#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000U) -#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000U) -#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000U) +#define GPIO_AFRL_AFRL0_Pos (0U) +#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk +#define GPIO_AFRL_AFRL1_Pos (4U) +#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk +#define GPIO_AFRL_AFRL2_Pos (8U) +#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk +#define GPIO_AFRL_AFRL3_Pos (12U) +#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk +#define GPIO_AFRL_AFRL4_Pos (16U) +#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk +#define GPIO_AFRL_AFRL5_Pos (20U) +#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk +#define GPIO_AFRL_AFRL6_Pos (24U) +#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk +#define GPIO_AFRL_AFRL7_Pos (28U) +#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000FU) -#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0U) -#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00U) -#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000U) -#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000U) -#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000U) -#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000U) -#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000U) +#define GPIO_AFRH_AFRH0_Pos (0U) +#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk +#define GPIO_AFRH_AFRH1_Pos (4U) +#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk +#define GPIO_AFRH_AFRH2_Pos (8U) +#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk +#define GPIO_AFRH_AFRH3_Pos (12U) +#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk +#define GPIO_AFRH_AFRH4_Pos (16U) +#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk +#define GPIO_AFRH_AFRH5_Pos (20U) +#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk +#define GPIO_AFRH_AFRH6_Pos (24U) +#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk +#define GPIO_AFRH_AFRH7_Pos (28U) +#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk /****************** Bit definition for GPIO_BRR register *********************/ -#define GPIO_BRR_BR_0 ((uint32_t)0x00000001U) -#define GPIO_BRR_BR_1 ((uint32_t)0x00000002U) -#define GPIO_BRR_BR_2 ((uint32_t)0x00000004U) -#define GPIO_BRR_BR_3 ((uint32_t)0x00000008U) -#define GPIO_BRR_BR_4 ((uint32_t)0x00000010U) -#define GPIO_BRR_BR_5 ((uint32_t)0x00000020U) -#define GPIO_BRR_BR_6 ((uint32_t)0x00000040U) -#define GPIO_BRR_BR_7 ((uint32_t)0x00000080U) -#define GPIO_BRR_BR_8 ((uint32_t)0x00000100U) -#define GPIO_BRR_BR_9 ((uint32_t)0x00000200U) -#define GPIO_BRR_BR_10 ((uint32_t)0x00000400U) -#define GPIO_BRR_BR_11 ((uint32_t)0x00000800U) -#define GPIO_BRR_BR_12 ((uint32_t)0x00001000U) -#define GPIO_BRR_BR_13 ((uint32_t)0x00002000U) -#define GPIO_BRR_BR_14 ((uint32_t)0x00004000U) -#define GPIO_BRR_BR_15 ((uint32_t)0x00008000U) +#define GPIO_BRR_BR_0 (0x00000001U) +#define GPIO_BRR_BR_1 (0x00000002U) +#define GPIO_BRR_BR_2 (0x00000004U) +#define GPIO_BRR_BR_3 (0x00000008U) +#define GPIO_BRR_BR_4 (0x00000010U) +#define GPIO_BRR_BR_5 (0x00000020U) +#define GPIO_BRR_BR_6 (0x00000040U) +#define GPIO_BRR_BR_7 (0x00000080U) +#define GPIO_BRR_BR_8 (0x00000100U) +#define GPIO_BRR_BR_9 (0x00000200U) +#define GPIO_BRR_BR_10 (0x00000400U) +#define GPIO_BRR_BR_11 (0x00000800U) +#define GPIO_BRR_BR_12 (0x00001000U) +#define GPIO_BRR_BR_13 (0x00002000U) +#define GPIO_BRR_BR_14 (0x00004000U) +#define GPIO_BRR_BR_15 (0x00008000U) /******************************************************************************/ /* */ @@ -1966,110 +3091,276 @@ typedef struct /******************************************************************************/ /******************* Bit definition for I2C_CR1 register *******************/ -#define I2C_CR1_PE ((uint32_t)0x00000001U) /*!< Peripheral enable */ -#define I2C_CR1_TXIE ((uint32_t)0x00000002U) /*!< TX interrupt enable */ -#define I2C_CR1_RXIE ((uint32_t)0x00000004U) /*!< RX interrupt enable */ -#define I2C_CR1_ADDRIE ((uint32_t)0x00000008U) /*!< Address match interrupt enable */ -#define I2C_CR1_NACKIE ((uint32_t)0x00000010U) /*!< NACK received interrupt enable */ -#define I2C_CR1_STOPIE ((uint32_t)0x00000020U) /*!< STOP detection interrupt enable */ -#define I2C_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transfer complete interrupt enable */ -#define I2C_CR1_ERRIE ((uint32_t)0x00000080U) /*!< Errors interrupt enable */ -#define I2C_CR1_DNF ((uint32_t)0x00000F00U) /*!< Digital noise filter */ -#define I2C_CR1_ANFOFF ((uint32_t)0x00001000U) /*!< Analog noise filter OFF */ -#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000U) /*!< DMA transmission requests enable */ -#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000U) /*!< DMA reception requests enable */ -#define I2C_CR1_SBC ((uint32_t)0x00010000U) /*!< Slave byte control */ -#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000U) /*!< Clock stretching disable */ -#define I2C_CR1_WUPEN ((uint32_t)0x00040000U) /*!< Wakeup from STOP enable */ -#define I2C_CR1_GCEN ((uint32_t)0x00080000U) /*!< General call enable */ -#define I2C_CR1_SMBHEN ((uint32_t)0x00100000U) /*!< SMBus host address enable */ -#define I2C_CR1_SMBDEN ((uint32_t)0x00200000U) /*!< SMBus device default address enable */ -#define I2C_CR1_ALERTEN ((uint32_t)0x00400000U) /*!< SMBus alert enable */ -#define I2C_CR1_PECEN ((uint32_t)0x00800000U) /*!< PEC enable */ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ /****************** Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_SADD ((uint32_t)0x000003FFU) /*!< Slave address (master mode) */ -#define I2C_CR2_RD_WRN ((uint32_t)0x00000400U) /*!< Transfer direction (master mode) */ -#define I2C_CR2_ADD10 ((uint32_t)0x00000800U) /*!< 10-bit addressing mode (master mode) */ -#define I2C_CR2_HEAD10R ((uint32_t)0x00001000U) /*!< 10-bit address header only read direction (master mode) */ -#define I2C_CR2_START ((uint32_t)0x00002000U) /*!< START generation */ -#define I2C_CR2_STOP ((uint32_t)0x00004000U) /*!< STOP generation (master mode) */ -#define I2C_CR2_NACK ((uint32_t)0x00008000U) /*!< NACK generation (slave mode) */ -#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000U) /*!< Number of bytes */ -#define I2C_CR2_RELOAD ((uint32_t)0x01000000U) /*!< NBYTES reload mode */ -#define I2C_CR2_AUTOEND ((uint32_t)0x02000000U) /*!< Automatic end mode (master mode) */ -#define I2C_CR2_PECBYTE ((uint32_t)0x04000000U) /*!< Packet error checking byte */ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ /******************* Bit definition for I2C_OAR1 register ******************/ -#define I2C_OAR1_OA1 ((uint32_t)0x000003FFU) /*!< Interface own address 1 */ -#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400U) /*!< Own address 1 10-bit mode */ -#define I2C_OAR1_OA1EN ((uint32_t)0x00008000U) /*!< Own address 1 enable */ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ /******************* Bit definition for I2C_OAR2 register ******************/ -#define I2C_OAR2_OA2 ((uint32_t)0x000000FEU) /*!< Interface own address 2 */ -#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700U) /*!< Own address 2 masks */ -#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000U) /*!< No mask */ -#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100U) /*!< OA2[1] is masked, Only OA2[7:2] are compared */ -#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200U) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ -#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300U) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ -#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400U) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ -#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500U) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ -#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600U) /*!< OA2[6:1] is masked, Only OA2[7] are compared */ -#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700U) /*!< OA2[7:1] is masked, No comparison is done */ -#define I2C_OAR2_OA2EN ((uint32_t)0x00008000U) /*!< Own address 2 enable */ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ /******************* Bit definition for I2C_TIMINGR register *******************/ -#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FFU) /*!< SCL low period (master mode) */ -#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00U) /*!< SCL high period (master mode) */ -#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000U) /*!< Data hold time */ -#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000U) /*!< Data setup time */ -#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000U) /*!< Timings prescaler */ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ /******************* Bit definition for I2C_TIMEOUTR register *******************/ -#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFFU) /*!< Bus timeout A */ -#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000U) /*!< Idle clock timeout detection */ -#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000U) /*!< Clock timeout enable */ -#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000U) /*!< Bus timeout B*/ -#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000U) /*!< Extended clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ /****************** Bit definition for I2C_ISR register *********************/ -#define I2C_ISR_TXE ((uint32_t)0x00000001U) /*!< Transmit data register empty */ -#define I2C_ISR_TXIS ((uint32_t)0x00000002U) /*!< Transmit interrupt status */ -#define I2C_ISR_RXNE ((uint32_t)0x00000004U) /*!< Receive data register not empty */ -#define I2C_ISR_ADDR ((uint32_t)0x00000008U) /*!< Address matched (slave mode)*/ -#define I2C_ISR_NACKF ((uint32_t)0x00000010U) /*!< NACK received flag */ -#define I2C_ISR_STOPF ((uint32_t)0x00000020U) /*!< STOP detection flag */ -#define I2C_ISR_TC ((uint32_t)0x00000040U) /*!< Transfer complete (master mode) */ -#define I2C_ISR_TCR ((uint32_t)0x00000080U) /*!< Transfer complete reload */ -#define I2C_ISR_BERR ((uint32_t)0x00000100U) /*!< Bus error */ -#define I2C_ISR_ARLO ((uint32_t)0x00000200U) /*!< Arbitration lost */ -#define I2C_ISR_OVR ((uint32_t)0x00000400U) /*!< Overrun/Underrun */ -#define I2C_ISR_PECERR ((uint32_t)0x00000800U) /*!< PEC error in reception */ -#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000U) /*!< Timeout or Tlow detection flag */ -#define I2C_ISR_ALERT ((uint32_t)0x00002000U) /*!< SMBus alert */ -#define I2C_ISR_BUSY ((uint32_t)0x00008000U) /*!< Bus busy */ -#define I2C_ISR_DIR ((uint32_t)0x00010000U) /*!< Transfer direction (slave mode) */ -#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000U) /*!< Address match code (slave mode) */ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ /****************** Bit definition for I2C_ICR register *********************/ -#define I2C_ICR_ADDRCF ((uint32_t)0x00000008U) /*!< Address matched clear flag */ -#define I2C_ICR_NACKCF ((uint32_t)0x00000010U) /*!< NACK clear flag */ -#define I2C_ICR_STOPCF ((uint32_t)0x00000020U) /*!< STOP detection clear flag */ -#define I2C_ICR_BERRCF ((uint32_t)0x00000100U) /*!< Bus error clear flag */ -#define I2C_ICR_ARLOCF ((uint32_t)0x00000200U) /*!< Arbitration lost clear flag */ -#define I2C_ICR_OVRCF ((uint32_t)0x00000400U) /*!< Overrun/Underrun clear flag */ -#define I2C_ICR_PECCF ((uint32_t)0x00000800U) /*!< PAC error clear flag */ -#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000U) /*!< Timeout clear flag */ -#define I2C_ICR_ALERTCF ((uint32_t)0x00002000U) /*!< Alert clear flag */ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ /****************** Bit definition for I2C_PECR register *********************/ -#define I2C_PECR_PEC ((uint32_t)0x000000FFU) /*!< PEC register */ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ /****************** Bit definition for I2C_RXDR register *********************/ -#define I2C_RXDR_RXDATA ((uint32_t)0x000000FFU) /*!< 8-bit receive data */ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ /****************** Bit definition for I2C_TXDR register *********************/ -#define I2C_TXDR_TXDATA ((uint32_t)0x000000FFU) /*!< 8-bit transmit data */ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ /******************************************************************************/ /* */ @@ -2077,24 +3368,38 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_KR_KEY ((uint32_t)0x0000FFFFU) /*!< Key value (write only, read 0000h) */ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ /******************* Bit definition for IWDG_PR register ********************/ -#define IWDG_PR_PR ((uint32_t)0x00000007U) /*!< PR[2:0] (Prescaler divider) */ -#define IWDG_PR_PR_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ -#define IWDG_PR_PR_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ -#define IWDG_PR_PR_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define IWDG_PR_PR_Pos (0U) +#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ +#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */ +#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */ +#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */ /******************* Bit definition for IWDG_RLR register *******************/ -#define IWDG_RLR_RL ((uint32_t)0x00000FFFU) /*!< Watchdog counter reload value */ +#define IWDG_RLR_RL_Pos (0U) +#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ +#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ /******************* Bit definition for IWDG_SR register ********************/ -#define IWDG_SR_PVU ((uint32_t)0x00000001U) /*!< Watchdog prescaler value update */ -#define IWDG_SR_RVU ((uint32_t)0x00000002U) /*!< Watchdog counter reload value update */ -#define IWDG_SR_WVU ((uint32_t)0x00000004U) /*!< Watchdog counter window value update */ +#define IWDG_SR_PVU_Pos (0U) +#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ +#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ +#define IWDG_SR_RVU_Pos (1U) +#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ +#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ +#define IWDG_SR_WVU_Pos (2U) +#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ +#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ /******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_WINR_WIN ((uint32_t)0x00000FFFU) /*!< Watchdog counter window value */ +#define IWDG_WINR_WIN_Pos (0U) +#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ +#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ /******************************************************************************/ /* */ @@ -2103,66 +3408,118 @@ typedef struct /******************************************************************************/ /******************* Bit definition for LCD_CR register *********************/ -#define LCD_CR_LCDEN ((uint32_t)0x00000001U) /*!< LCD Enable Bit */ -#define LCD_CR_VSEL ((uint32_t)0x00000002U) /*!< Voltage source selector Bit */ +#define LCD_CR_LCDEN_Pos (0U) +#define LCD_CR_LCDEN_Msk (0x1U << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */ +#define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */ +#define LCD_CR_VSEL_Pos (1U) +#define LCD_CR_VSEL_Msk (0x1U << LCD_CR_VSEL_Pos) /*!< 0x00000002 */ +#define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */ -#define LCD_CR_DUTY ((uint32_t)0x0000001CU) /*!< DUTY[2:0] bits (Duty selector) */ -#define LCD_CR_DUTY_0 ((uint32_t)0x00000004U) /*!< Duty selector Bit 0 */ -#define LCD_CR_DUTY_1 ((uint32_t)0x00000008U) /*!< Duty selector Bit 1 */ -#define LCD_CR_DUTY_2 ((uint32_t)0x00000010U) /*!< Duty selector Bit 2 */ +#define LCD_CR_DUTY_Pos (2U) +#define LCD_CR_DUTY_Msk (0x7U << LCD_CR_DUTY_Pos) /*!< 0x0000001C */ +#define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */ +#define LCD_CR_DUTY_0 (0x1U << LCD_CR_DUTY_Pos) /*!< 0x00000004 */ +#define LCD_CR_DUTY_1 (0x2U << LCD_CR_DUTY_Pos) /*!< 0x00000008 */ +#define LCD_CR_DUTY_2 (0x4U << LCD_CR_DUTY_Pos) /*!< 0x00000010 */ -#define LCD_CR_BIAS ((uint32_t)0x00000060U) /*!< BIAS[1:0] bits (Bias selector) */ -#define LCD_CR_BIAS_0 ((uint32_t)0x00000020U) /*!< Bias selector Bit 0 */ -#define LCD_CR_BIAS_1 ((uint32_t)0x00000040U) /*!< Bias selector Bit 1 */ +#define LCD_CR_BIAS_Pos (5U) +#define LCD_CR_BIAS_Msk (0x3U << LCD_CR_BIAS_Pos) /*!< 0x00000060 */ +#define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */ +#define LCD_CR_BIAS_0 (0x1U << LCD_CR_BIAS_Pos) /*!< 0x00000020 */ +#define LCD_CR_BIAS_1 (0x2U << LCD_CR_BIAS_Pos) /*!< 0x00000040 */ -#define LCD_CR_MUX_SEG ((uint32_t)0x00000080U) /*!< Mux Segment Enable Bit */ +#define LCD_CR_MUX_SEG_Pos (7U) +#define LCD_CR_MUX_SEG_Msk (0x1U << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */ +#define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */ + +#define LCD_CR_BUFEN_Pos (8U) +#define LCD_CR_BUFEN_Msk (0x1U << LCD_CR_BUFEN_Pos) /*!< 0x00000100 */ +#define LCD_CR_BUFEN LCD_CR_BUFEN_Msk /*!< Voltage output buffer enable Bit */ /******************* Bit definition for LCD_FCR register ********************/ -#define LCD_FCR_HD ((uint32_t)0x00000001U) /*!< High Drive Enable Bit */ -#define LCD_FCR_SOFIE ((uint32_t)0x00000002U) /*!< Start of Frame Interrupt Enable Bit */ -#define LCD_FCR_UDDIE ((uint32_t)0x00000008U) /*!< Update Display Done Interrupt Enable Bit */ +#define LCD_FCR_HD_Pos (0U) +#define LCD_FCR_HD_Msk (0x1U << LCD_FCR_HD_Pos) /*!< 0x00000001 */ +#define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */ +#define LCD_FCR_SOFIE_Pos (1U) +#define LCD_FCR_SOFIE_Msk (0x1U << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */ +#define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */ +#define LCD_FCR_UDDIE_Pos (3U) +#define LCD_FCR_UDDIE_Msk (0x1U << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */ +#define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */ -#define LCD_FCR_PON ((uint32_t)0x00000070U) /*!< PON[2:0] bits (Puls ON Duration) */ -#define LCD_FCR_PON_0 ((uint32_t)0x00000010U) /*!< Bit 0 */ -#define LCD_FCR_PON_1 ((uint32_t)0x00000020U) /*!< Bit 1 */ -#define LCD_FCR_PON_2 ((uint32_t)0x00000040U) /*!< Bit 2 */ +#define LCD_FCR_PON_Pos (4U) +#define LCD_FCR_PON_Msk (0x7U << LCD_FCR_PON_Pos) /*!< 0x00000070 */ +#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */ +#define LCD_FCR_PON_0 (0x1U << LCD_FCR_PON_Pos) /*!< 0x00000010 */ +#define LCD_FCR_PON_1 (0x2U << LCD_FCR_PON_Pos) /*!< 0x00000020 */ +#define LCD_FCR_PON_2 (0x4U << LCD_FCR_PON_Pos) /*!< 0x00000040 */ -#define LCD_FCR_DEAD ((uint32_t)0x00000380U) /*!< DEAD[2:0] bits (DEAD Time) */ -#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080U) /*!< Bit 0 */ -#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100U) /*!< Bit 1 */ -#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200U) /*!< Bit 2 */ +#define LCD_FCR_DEAD_Pos (7U) +#define LCD_FCR_DEAD_Msk (0x7U << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */ +#define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */ +#define LCD_FCR_DEAD_0 (0x1U << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */ +#define LCD_FCR_DEAD_1 (0x2U << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */ +#define LCD_FCR_DEAD_2 (0x4U << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */ -#define LCD_FCR_CC ((uint32_t)0x00001C00U) /*!< CC[2:0] bits (Contrast Control) */ -#define LCD_FCR_CC_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ -#define LCD_FCR_CC_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ -#define LCD_FCR_CC_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define LCD_FCR_CC_Pos (10U) +#define LCD_FCR_CC_Msk (0x7U << LCD_FCR_CC_Pos) /*!< 0x00001C00 */ +#define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */ +#define LCD_FCR_CC_0 (0x1U << LCD_FCR_CC_Pos) /*!< 0x00000400 */ +#define LCD_FCR_CC_1 (0x2U << LCD_FCR_CC_Pos) /*!< 0x00000800 */ +#define LCD_FCR_CC_2 (0x4U << LCD_FCR_CC_Pos) /*!< 0x00001000 */ -#define LCD_FCR_BLINKF ((uint32_t)0x0000E000U) /*!< BLINKF[2:0] bits (Blink Frequency) */ -#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000U) /*!< Bit 0 */ -#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000U) /*!< Bit 1 */ -#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000U) /*!< Bit 2 */ +#define LCD_FCR_BLINKF_Pos (13U) +#define LCD_FCR_BLINKF_Msk (0x7U << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */ +#define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */ +#define LCD_FCR_BLINKF_0 (0x1U << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */ +#define LCD_FCR_BLINKF_1 (0x2U << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */ +#define LCD_FCR_BLINKF_2 (0x4U << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */ -#define LCD_FCR_BLINK ((uint32_t)0x00030000U) /*!< BLINK[1:0] bits (Blink Enable) */ -#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ -#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ +#define LCD_FCR_BLINK_Pos (16U) +#define LCD_FCR_BLINK_Msk (0x3U << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */ +#define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */ +#define LCD_FCR_BLINK_0 (0x1U << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */ +#define LCD_FCR_BLINK_1 (0x2U << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */ -#define LCD_FCR_DIV ((uint32_t)0x003C0000U) /*!< DIV[3:0] bits (Divider) */ -#define LCD_FCR_PS ((uint32_t)0x03C00000U) /*!< PS[3:0] bits (Prescaler) */ +#define LCD_FCR_DIV_Pos (18U) +#define LCD_FCR_DIV_Msk (0xFU << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */ +#define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */ +#define LCD_FCR_PS_Pos (22U) +#define LCD_FCR_PS_Msk (0xFU << LCD_FCR_PS_Pos) /*!< 0x03C00000 */ +#define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */ /******************* Bit definition for LCD_SR register *********************/ -#define LCD_SR_ENS ((uint32_t)0x00000001U) /*!< LCD Enabled Bit */ -#define LCD_SR_SOF ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Bit */ -#define LCD_SR_UDR ((uint32_t)0x00000004U) /*!< Update Display Request Bit */ -#define LCD_SR_UDD ((uint32_t)0x00000008U) /*!< Update Display Done Flag Bit */ -#define LCD_SR_RDY ((uint32_t)0x00000010U) /*!< Ready Flag Bit */ -#define LCD_SR_FCRSR ((uint32_t)0x00000020U) /*!< LCD FCR Register Synchronization Flag Bit */ +#define LCD_SR_ENS_Pos (0U) +#define LCD_SR_ENS_Msk (0x1U << LCD_SR_ENS_Pos) /*!< 0x00000001 */ +#define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */ +#define LCD_SR_SOF_Pos (1U) +#define LCD_SR_SOF_Msk (0x1U << LCD_SR_SOF_Pos) /*!< 0x00000002 */ +#define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */ +#define LCD_SR_UDR_Pos (2U) +#define LCD_SR_UDR_Msk (0x1U << LCD_SR_UDR_Pos) /*!< 0x00000004 */ +#define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */ +#define LCD_SR_UDD_Pos (3U) +#define LCD_SR_UDD_Msk (0x1U << LCD_SR_UDD_Pos) /*!< 0x00000008 */ +#define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */ +#define LCD_SR_RDY_Pos (4U) +#define LCD_SR_RDY_Msk (0x1U << LCD_SR_RDY_Pos) /*!< 0x00000010 */ +#define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */ +#define LCD_SR_FCRSR_Pos (5U) +#define LCD_SR_FCRSR_Msk (0x1U << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */ +#define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */ /******************* Bit definition for LCD_CLR register ********************/ -#define LCD_CLR_SOFC ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Clear Bit */ -#define LCD_CLR_UDDC ((uint32_t)0x00000008U) /*!< Update Display Done Flag Clear Bit */ +#define LCD_CLR_SOFC_Pos (1U) +#define LCD_CLR_SOFC_Msk (0x1U << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */ +#define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */ +#define LCD_CLR_UDDC_Pos (3U) +#define LCD_CLR_UDDC_Msk (0x1U << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */ +#define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */ /******************* Bit definition for LCD_RAM register ********************/ -#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFFU) /*!< Segment Data Bits */ +#define LCD_RAM_SEGMENT_DATA_Pos (0U) +#define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */ +#define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */ /******************************************************************************/ /* */ @@ -2170,81 +3527,161 @@ typedef struct /* */ /******************************************************************************/ /****************** Bit definition for LPTIM_ISR register *******************/ -#define LPTIM_ISR_CMPM ((uint32_t)0x00000001U) /*!< Compare match */ -#define LPTIM_ISR_ARRM ((uint32_t)0x00000002U) /*!< Autoreload match */ -#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004U) /*!< External trigger edge event */ -#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008U) /*!< Compare register update OK */ -#define LPTIM_ISR_ARROK ((uint32_t)0x00000010U) /*!< Autoreload register update OK */ -#define LPTIM_ISR_UP ((uint32_t)0x00000020U) /*!< Counter direction change down to up */ -#define LPTIM_ISR_DOWN ((uint32_t)0x00000040U) /*!< Counter direction change up to down */ +#define LPTIM_ISR_CMPM_Pos (0U) +#define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */ +#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */ +#define LPTIM_ISR_ARRM_Pos (1U) +#define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */ +#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */ +#define LPTIM_ISR_EXTTRIG_Pos (2U) +#define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */ +#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */ +#define LPTIM_ISR_CMPOK_Pos (3U) +#define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */ +#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */ +#define LPTIM_ISR_ARROK_Pos (4U) +#define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */ +#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */ +#define LPTIM_ISR_UP_Pos (5U) +#define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */ +#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */ +#define LPTIM_ISR_DOWN_Pos (6U) +#define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */ +#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */ /****************** Bit definition for LPTIM_ICR register *******************/ -#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001U) /*!< Compare match Clear Flag */ -#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002U) /*!< Autoreload match Clear Flag */ -#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004U) /*!< External trigger edge event Clear Flag */ -#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008U) /*!< Compare register update OK Clear Flag */ -#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010U) /*!< Autoreload register update OK Clear Flag */ -#define LPTIM_ICR_UPCF ((uint32_t)0x00000020U) /*!< Counter direction change down to up Clear Flag */ -#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040U) /*!< Counter direction change up to down Clear Flag */ +#define LPTIM_ICR_CMPMCF_Pos (0U) +#define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */ +#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */ +#define LPTIM_ICR_ARRMCF_Pos (1U) +#define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */ +#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */ +#define LPTIM_ICR_EXTTRIGCF_Pos (2U) +#define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */ +#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */ +#define LPTIM_ICR_CMPOKCF_Pos (3U) +#define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */ +#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */ +#define LPTIM_ICR_ARROKCF_Pos (4U) +#define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */ +#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */ +#define LPTIM_ICR_UPCF_Pos (5U) +#define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */ +#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */ +#define LPTIM_ICR_DOWNCF_Pos (6U) +#define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */ +#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */ /****************** Bit definition for LPTIM_IER register ********************/ -#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001U) /*!< Compare match Interrupt Enable */ -#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002U) /*!< Autoreload match Interrupt Enable */ -#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004U) /*!< External trigger edge event Interrupt Enable */ -#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008U) /*!< Compare register update OK Interrupt Enable */ -#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010U) /*!< Autoreload register update OK Interrupt Enable */ -#define LPTIM_IER_UPIE ((uint32_t)0x00000020U) /*!< Counter direction change down to up Interrupt Enable */ -#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040U) /*!< Counter direction change up to down Interrupt Enable */ +#define LPTIM_IER_CMPMIE_Pos (0U) +#define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */ +#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */ +#define LPTIM_IER_ARRMIE_Pos (1U) +#define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */ +#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */ +#define LPTIM_IER_EXTTRIGIE_Pos (2U) +#define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */ +#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */ +#define LPTIM_IER_CMPOKIE_Pos (3U) +#define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */ +#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */ +#define LPTIM_IER_ARROKIE_Pos (4U) +#define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */ +#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */ +#define LPTIM_IER_UPIE_Pos (5U) +#define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */ +#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */ +#define LPTIM_IER_DOWNIE_Pos (6U) +#define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */ +#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */ /****************** Bit definition for LPTIM_CFGR register *******************/ -#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001U) /*!< Clock selector */ +#define LPTIM_CFGR_CKSEL_Pos (0U) +#define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */ +#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */ -#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006U) /*!< CKPOL[1:0] bits (Clock polarity) */ -#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002U) /*!< Bit 0 */ -#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004U) /*!< Bit 1 */ +#define LPTIM_CFGR_CKPOL_Pos (1U) +#define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */ +#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */ +#define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */ +#define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */ -#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018U) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ -#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ +#define LPTIM_CFGR_CKFLT_Pos (3U) +#define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */ +#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ +#define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */ +#define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */ -#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0U) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ -#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ -#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ +#define LPTIM_CFGR_TRGFLT_Pos (6U) +#define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */ +#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ +#define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */ +#define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */ -#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00U) /*!< PRESC[2:0] bits (Clock prescaler) */ -#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200U) /*!< Bit 0 */ -#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400U) /*!< Bit 1 */ -#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800U) /*!< Bit 2 */ +#define LPTIM_CFGR_PRESC_Pos (9U) +#define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */ +#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */ +#define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */ +#define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */ +#define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */ -#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000U) /*!< TRIGSEL[2:0]] bits (Trigger selector) */ -#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000U) /*!< Bit 0 */ -#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000U) /*!< Bit 1 */ -#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000U) /*!< Bit 2 */ +#define LPTIM_CFGR_TRIGSEL_Pos (13U) +#define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */ +#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */ +#define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */ +#define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */ +#define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */ -#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000U) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ -#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000U) /*!< Bit 0 */ -#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000U) /*!< Bit 1 */ +#define LPTIM_CFGR_TRIGEN_Pos (17U) +#define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */ +#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ +#define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */ +#define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */ -#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000U) /*!< Timout enable */ -#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000U) /*!< Waveform shape */ -#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000U) /*!< Waveform shape polarity */ -#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000U) /*!< Reg update mode */ -#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000U) /*!< Counter mode enable */ -#define LPTIM_CFGR_ENC ((uint32_t)0x01000000U) /*!< Encoder mode enable */ +#define LPTIM_CFGR_TIMOUT_Pos (19U) +#define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */ +#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */ +#define LPTIM_CFGR_WAVE_Pos (20U) +#define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */ +#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */ +#define LPTIM_CFGR_WAVPOL_Pos (21U) +#define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */ +#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */ +#define LPTIM_CFGR_PRELOAD_Pos (22U) +#define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */ +#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */ +#define LPTIM_CFGR_COUNTMODE_Pos (23U) +#define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */ +#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */ +#define LPTIM_CFGR_ENC_Pos (24U) +#define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */ +#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */ /****************** Bit definition for LPTIM_CR register ********************/ -#define LPTIM_CR_ENABLE ((uint32_t)0x00000001U) /*!< LPTIMer enable */ -#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002U) /*!< Timer start in single mode */ -#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004U) /*!< Timer start in continuous mode */ +#define LPTIM_CR_ENABLE_Pos (0U) +#define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */ +#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */ +#define LPTIM_CR_SNGSTRT_Pos (1U) +#define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */ +#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */ +#define LPTIM_CR_CNTSTRT_Pos (2U) +#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */ +#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */ /****************** Bit definition for LPTIM_CMP register *******************/ -#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFFU) /*!< Compare register */ +#define LPTIM_CMP_CMP_Pos (0U) +#define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */ +#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */ /****************** Bit definition for LPTIM_ARR register *******************/ -#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!< Auto reload register */ +#define LPTIM_ARR_ARR_Pos (0U) +#define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */ +#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */ /****************** Bit definition for LPTIM_CNT register *******************/ -#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!< Counter register */ +#define LPTIM_CNT_CNT_Pos (0U) +#define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */ +#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */ /******************************************************************************/ /* */ @@ -2253,17 +3690,35 @@ typedef struct /******************************************************************************/ /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */ -#define FW_CSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Code Segment Start Address */ -#define FW_CSL_LENG ((uint32_t)0x003FFF00U) /*!< Code Segment Length */ -#define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Non Volatile Dat Segment Start Address */ -#define FW_NVDSL_LENG ((uint32_t)0x003FFF00U) /*!< Non Volatile Data Segment Length */ -#define FW_VDSSA_ADD ((uint32_t)0x0000FFC0U) /*!< Volatile Data Segment Start Address */ -#define FW_VDSL_LENG ((uint32_t)0x0000FFC0U) /*!< Volatile Data Segment Length */ +#define FW_CSSA_ADD_Pos (8U) +#define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */ +#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */ +#define FW_CSL_LENG_Pos (8U) +#define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */ +#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */ +#define FW_NVDSSA_ADD_Pos (8U) +#define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */ +#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */ +#define FW_NVDSL_LENG_Pos (8U) +#define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */ +#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */ +#define FW_VDSSA_ADD_Pos (6U) +#define FW_VDSSA_ADD_Msk (0x3FFU << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */ +#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */ +#define FW_VDSL_LENG_Pos (6U) +#define FW_VDSL_LENG_Msk (0x3FFU << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */ +#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */ /**************************Bit definition for CR register *********************/ -#define FW_CR_FPA ((uint32_t)0x00000001U) /*!< Firewall Pre Arm*/ -#define FW_CR_VDS ((uint32_t)0x00000002U) /*!< Volatile Data Sharing*/ -#define FW_CR_VDE ((uint32_t)0x00000004U) /*!< Volatile Data Execution*/ +#define FW_CR_FPA_Pos (0U) +#define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */ +#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/ +#define FW_CR_VDS_Pos (1U) +#define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */ +#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/ +#define FW_CR_VDE_Pos (2U) +#define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */ +#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/ /******************************************************************************/ /* */ @@ -2271,49 +3726,93 @@ typedef struct /* */ /******************************************************************************/ -/******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPSDSR ((uint32_t)0x00000001U) /*!< Low-power deepsleep/sleep/low power run */ -#define PWR_CR_PDDS ((uint32_t)0x00000002U) /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF ((uint32_t)0x00000004U) /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF ((uint32_t)0x00000008U) /*!< Clear Standby Flag */ -#define PWR_CR_PVDE ((uint32_t)0x00000010U) /*!< Power Voltage Detector Enable */ +#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */ -#define PWR_CR_PLS ((uint32_t)0x000000E0U) /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ -#define PWR_CR_PLS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ -#define PWR_CR_PLS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPSDSR_Pos (0U) +#define PWR_CR_LPSDSR_Msk (0x1U << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */ +#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */ +#define PWR_CR_PDDS_Pos (1U) +#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ +#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF_Pos (2U) +#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ +#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF_Pos (3U) +#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ +#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ +#define PWR_CR_PVDE_Pos (4U) +#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS_Pos (5U) +#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ +#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ +#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ +#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ /*!< PVD level configuration */ -#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000U) /*!< PVD level 0 */ -#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020U) /*!< PVD level 1 */ -#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040U) /*!< PVD level 2 */ -#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060U) /*!< PVD level 3 */ -#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080U) /*!< PVD level 4 */ -#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0U) /*!< PVD level 5 */ -#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0U) /*!< PVD level 6 */ -#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0U) /*!< PVD level 7 */ +#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ +#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */ +#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */ +#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */ +#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */ +#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */ +#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */ +#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */ -#define PWR_CR_DBP ((uint32_t)0x00000100U) /*!< Disable Backup Domain write protection */ -#define PWR_CR_ULP ((uint32_t)0x00000200U) /*!< Ultra Low Power mode */ -#define PWR_CR_FWU ((uint32_t)0x00000400U) /*!< Fast wakeup */ +#define PWR_CR_DBP_Pos (8U) +#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ +#define PWR_CR_ULP_Pos (9U) +#define PWR_CR_ULP_Msk (0x1U << PWR_CR_ULP_Pos) /*!< 0x00000200 */ +#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */ +#define PWR_CR_FWU_Pos (10U) +#define PWR_CR_FWU_Msk (0x1U << PWR_CR_FWU_Pos) /*!< 0x00000400 */ +#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */ -#define PWR_CR_VOS ((uint32_t)0x00001800U) /*!< VOS[1:0] bits (Voltage scaling range selection) */ -#define PWR_CR_VOS_0 ((uint32_t)0x00000800U) /*!< Bit 0 */ -#define PWR_CR_VOS_1 ((uint32_t)0x00001000U) /*!< Bit 1 */ -#define PWR_CR_DSEEKOFF ((uint32_t)0x00002000U) /*!< Deep Sleep mode with EEPROM kept Off */ -#define PWR_CR_LPRUN ((uint32_t)0x00004000U) /*!< Low power run mode */ +#define PWR_CR_VOS_Pos (11U) +#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x00001800 */ +#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */ +#define PWR_CR_VOS_0 (0x1U << PWR_CR_VOS_Pos) /*!< 0x00000800 */ +#define PWR_CR_VOS_1 (0x2U << PWR_CR_VOS_Pos) /*!< 0x00001000 */ +#define PWR_CR_DSEEKOFF_Pos (13U) +#define PWR_CR_DSEEKOFF_Msk (0x1U << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */ +#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */ +#define PWR_CR_LPRUN_Pos (14U) +#define PWR_CR_LPRUN_Msk (0x1U << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */ +#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */ /******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint32_t)0x00000001U) /*!< Wakeup Flag */ -#define PWR_CSR_SBF ((uint32_t)0x00000002U) /*!< Standby Flag */ -#define PWR_CSR_PVDO ((uint32_t)0x00000004U) /*!< PVD Output */ -#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008U) /*!< Internal voltage reference (VREFINT) ready flag */ -#define PWR_CSR_VOSF ((uint32_t)0x00000010U) /*!< Voltage Scaling select flag */ -#define PWR_CSR_REGLPF ((uint32_t)0x00000020U) /*!< Regulator LP flag */ +#define PWR_CSR_WUF_Pos (0U) +#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ +#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ +#define PWR_CSR_SBF_Pos (1U) +#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ +#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ +#define PWR_CSR_PVDO_Pos (2U) +#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ +#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ +#define PWR_CSR_VREFINTRDYF_Pos (3U) +#define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */ +#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */ +#define PWR_CSR_VOSF_Pos (4U) +#define PWR_CSR_VOSF_Msk (0x1U << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */ +#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */ +#define PWR_CSR_REGLPF_Pos (5U) +#define PWR_CSR_REGLPF_Msk (0x1U << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */ +#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */ -#define PWR_CSR_EWUP1 ((uint32_t)0x00000100U) /*!< Enable WKUP pin 1 */ -#define PWR_CSR_EWUP2 ((uint32_t)0x00000200U) /*!< Enable WKUP pin 2 */ -#define PWR_CSR_EWUP3 ((uint32_t)0x00000400U) /*!< Enable WKUP pin 3 */ +#define PWR_CSR_EWUP1_Pos (8U) +#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ +#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ +#define PWR_CSR_EWUP2_Pos (9U) +#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ +#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ +#define PWR_CSR_EWUP3_Pos (10U) +#define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */ +#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */ /******************************************************************************/ /* */ @@ -2321,175 +3820,280 @@ typedef struct /* */ /******************************************************************************/ +#define RCC_HSI48_SUPPORT /*!< HSI48 feature support */ +#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */ + /******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION ((uint32_t)0x00000001U) /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIKERON ((uint32_t)0x00000002U) /*!< Internal High Speed clock enable for some IPs Kernel */ -#define RCC_CR_HSIRDY ((uint32_t)0x00000004U) /*!< Internal High Speed clock ready flag */ -#define RCC_CR_HSIDIVEN ((uint32_t)0x00000008U) /*!< Internal High Speed clock divider enable */ -#define RCC_CR_HSIDIVF ((uint32_t)0x00000010U) /*!< Internal High Speed clock divider flag */ -#define RCC_CR_HSIOUTEN ((uint32_t)0x00000020U) /*!< Internal High Speed clock out enable */ -#define RCC_CR_MSION ((uint32_t)0x00000100U) /*!< Internal Multi Speed clock enable */ -#define RCC_CR_MSIRDY ((uint32_t)0x00000200U) /*!< Internal Multi Speed clock ready flag */ -#define RCC_CR_HSEON ((uint32_t)0x00010000U) /*!< External High Speed clock enable */ -#define RCC_CR_HSERDY ((uint32_t)0x00020000U) /*!< External High Speed clock ready flag */ -#define RCC_CR_HSEBYP ((uint32_t)0x00040000U) /*!< External High Speed clock Bypass */ -#define RCC_CR_CSSHSEON ((uint32_t)0x00080000U) /*!< HSE Clock Security System enable */ -#define RCC_CR_RTCPRE ((uint32_t)0x00300000U) /*!< RTC/LCD prescaler [1:0] bits */ -#define RCC_CR_RTCPRE_0 ((uint32_t)0x00100000U) /*!< RTC/LCD prescaler Bit 0 */ -#define RCC_CR_RTCPRE_1 ((uint32_t)0x00200000U) /*!< RTC/LCD prescaler Bit 1 */ -#define RCC_CR_PLLON ((uint32_t)0x01000000U) /*!< PLL enable */ -#define RCC_CR_PLLRDY ((uint32_t)0x02000000U) /*!< PLL clock ready flag */ +#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIKERON_Pos (1U) +#define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */ +#define RCC_CR_HSIRDY_Pos (2U) +#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSIDIVEN_Pos (3U) +#define RCC_CR_HSIDIVEN_Msk (0x1U << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */ +#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */ +#define RCC_CR_HSIDIVF_Pos (4U) +#define RCC_CR_HSIDIVF_Msk (0x1U << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */ +#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */ +#define RCC_CR_HSIOUTEN_Pos (5U) +#define RCC_CR_HSIOUTEN_Msk (0x1U << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */ +#define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */ +#define RCC_CR_MSION_Pos (8U) +#define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000100 */ +#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */ +#define RCC_CR_MSIRDY_Pos (9U) +#define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */ +#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSHSEON_Pos (19U) +#define RCC_CR_CSSHSEON_Msk (0x1U << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */ +#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */ +#define RCC_CR_RTCPRE_Pos (20U) +#define RCC_CR_RTCPRE_Msk (0x3U << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */ +#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC/LCD prescaler [1:0] bits */ +#define RCC_CR_RTCPRE_0 (0x1U << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */ +#define RCC_CR_RTCPRE_1 (0x2U << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */ +#define RCC_CR_PLLON_Pos (24U) +#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ +#define RCC_CR_PLLRDY_Pos (25U) +#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ /* Reference defines */ #define RCC_CR_CSSON RCC_CR_CSSHSEON /******************** Bit definition for RCC_ICSCR register *****************/ -#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FFU) /*!< Internal High Speed clock Calibration */ -#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00U) /*!< Internal High Speed clock trimming */ +#define RCC_ICSCR_HSICAL_Pos (0U) +#define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */ +#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ +#define RCC_ICSCR_HSITRIM_Pos (8U) +#define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ -#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000U) /*!< Internal Multi Speed clock Range */ -#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000U) /*!< Internal Multi Speed clock Range 65.536 KHz */ -#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000U) /*!< Internal Multi Speed clock Range 131.072 KHz */ -#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000U) /*!< Internal Multi Speed clock Range 262.144 KHz */ -#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000U) /*!< Internal Multi Speed clock Range 524.288 KHz */ -#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000U) /*!< Internal Multi Speed clock Range 1.048 MHz */ -#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000U) /*!< Internal Multi Speed clock Range 2.097 MHz */ -#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000U) /*!< Internal Multi Speed clock Range 4.194 MHz */ -#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000U) /*!< Internal Multi Speed clock Calibration */ -#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000U) /*!< Internal Multi Speed clock trimming */ +#define RCC_ICSCR_MSIRANGE_Pos (13U) +#define RCC_ICSCR_MSIRANGE_Msk (0x7U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */ +#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */ +#define RCC_ICSCR_MSIRANGE_0 (0x0U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */ +#define RCC_ICSCR_MSIRANGE_1 (0x1U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */ +#define RCC_ICSCR_MSIRANGE_2 (0x2U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */ +#define RCC_ICSCR_MSIRANGE_3 (0x3U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */ +#define RCC_ICSCR_MSIRANGE_4 (0x4U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */ +#define RCC_ICSCR_MSIRANGE_5 (0x5U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */ +#define RCC_ICSCR_MSIRANGE_6 (0x6U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */ +#define RCC_ICSCR_MSICAL_Pos (16U) +#define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */ +#define RCC_ICSCR_MSITRIM_Pos (24U) +#define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */ +#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */ /******************** Bit definition for RCC_CRRCR register *****************/ -#define RCC_CRRCR_HSI48ON ((uint32_t)0x00000001U) /*!< HSI 48MHz clock enable */ -#define RCC_CRRCR_HSI48RDY ((uint32_t)0x00000002U) /*!< HSI 48MHz clock ready flag */ -#define RCC_CRRCR_HSI48DIV6OUTEN ((uint32_t)0x00000004U) /*!< HSI 48MHz DIV6 out enable */ -#define RCC_CRRCR_HSI48CAL ((uint32_t)0x0000FF00U) /*!< HSI 48MHz clock Calibration */ +#define RCC_CRRCR_HSI48ON_Pos (0U) +#define RCC_CRRCR_HSI48ON_Msk (0x1U << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */ +#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk /*!< HSI 48MHz clock enable */ +#define RCC_CRRCR_HSI48RDY_Pos (1U) +#define RCC_CRRCR_HSI48RDY_Msk (0x1U << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */ +#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk /*!< HSI 48MHz clock ready flag */ +#define RCC_CRRCR_HSI48DIV6OUTEN_Pos (2U) +#define RCC_CRRCR_HSI48DIV6OUTEN_Msk (0x1U << RCC_CRRCR_HSI48DIV6OUTEN_Pos) /*!< 0x00000004 */ +#define RCC_CRRCR_HSI48DIV6OUTEN RCC_CRRCR_HSI48DIV6OUTEN_Msk /*!< HSI 48MHz DIV6 out enable */ +#define RCC_CRRCR_HSI48CAL_Pos (8U) +#define RCC_CRRCR_HSI48CAL_Msk (0xFFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF00 */ +#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI 48MHz clock Calibration */ /******************* Bit definition for RCC_CFGR register *******************/ /*!< SW configuration */ -#define RCC_CFGR_SW ((uint32_t)0x00000003U) /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ -#define RCC_CFGR_SW_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ -#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000U) /*!< MSI selected as system clock */ -#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001U) /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002U) /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003U) /*!< PLL selected as system clock */ +#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */ +#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */ /*!< SWS configuration */ -#define RCC_CFGR_SWS ((uint32_t)0x0000000CU) /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004U) /*!< Bit 0 */ -#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008U) /*!< Bit 1 */ +#define RCC_CFGR_SWS_Pos (2U) +#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ +#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ -#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004U) /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008U) /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000CU) /*!< PLL used as system clock */ +#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */ /*!< HPRE configuration */ -#define RCC_CFGR_HPRE ((uint32_t)0x000000F0U) /*!< HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010U) /*!< Bit 0 */ -#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020U) /*!< Bit 1 */ -#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040U) /*!< Bit 2 */ -#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080U) /*!< Bit 3 */ +#define RCC_CFGR_HPRE_Pos (4U) +#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ +#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ +#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ -#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000U) /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080U) /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090U) /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0U) /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0U) /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0U) /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0U) /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0U) /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0U) /*!< SYSCLK divided by 512 */ +#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ /*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700U) /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */ -#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */ -#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */ +#define RCC_CFGR_PPRE1_Pos (8U) +#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ +#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ +#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ +#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ -#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400U) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500U) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600U) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700U) /*!< HCLK divided by 16 */ +#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */ /*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800U) /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800U) /*!< Bit 0 */ -#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000U) /*!< Bit 1 */ -#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000U) /*!< Bit 2 */ +#define RCC_CFGR_PPRE2_Pos (11U) +#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ +#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ +#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ +#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ -#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000U) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800U) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000U) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800U) /*!< HCLK divided by 16 */ +#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */ -#define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000U) /*!< Wake Up from Stop Clock selection */ +#define RCC_CFGR_STOPWUCK_Pos (15U) +#define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */ +#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */ /*!< PLL entry clock source*/ -#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000U) /*!< PLL entry clock source */ +#define RCC_CFGR_PLLSRC_Pos (16U) +#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ +#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ -#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000U) /*!< HSI as PLL entry clock source */ -#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000U) /*!< HSE as PLL entry clock source */ +#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */ +#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */ /*!< PLLMUL configuration */ -#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000U) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ -#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ -#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ -#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000U) /*!< Bit 3 */ +#define RCC_CFGR_PLLMUL_Pos (18U) +#define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ -#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000U) /*!< PLL input clock * 3 */ -#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000U) /*!< PLL input clock * 4 */ -#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000U) /*!< PLL input clock * 6 */ -#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000U) /*!< PLL input clock * 8 */ -#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000U) /*!< PLL input clock * 12 */ -#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000U) /*!< PLL input clock * 16 */ -#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000U) /*!< PLL input clock * 24 */ -#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000U) /*!< PLL input clock * 32 */ -#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000U) /*!< PLL input clock * 48 */ +#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */ +#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */ +#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */ +#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */ +#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */ +#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */ +#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */ +#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */ +#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */ /*!< PLLDIV configuration */ -#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000U) /*!< PLLDIV[1:0] bits (PLL Output Division) */ -#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000U) /*!< Bit0 */ -#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000U) /*!< Bit1 */ +#define RCC_CFGR_PLLDIV_Pos (22U) +#define RCC_CFGR_PLLDIV_Msk (0x3U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */ +#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */ +#define RCC_CFGR_PLLDIV_0 (0x1U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_PLLDIV_1 (0x2U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */ -#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000U) /*!< PLL clock output = CKVCO / 2 */ -#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000U) /*!< PLL clock output = CKVCO / 3 */ -#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000U) /*!< PLL clock output = CKVCO / 4 */ +#define RCC_CFGR_PLLDIV2_Pos (22U) +#define RCC_CFGR_PLLDIV2_Msk (0x1U << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */ +#define RCC_CFGR_PLLDIV3_Pos (23U) +#define RCC_CFGR_PLLDIV3_Msk (0x1U << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */ +#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */ +#define RCC_CFGR_PLLDIV4_Pos (22U) +#define RCC_CFGR_PLLDIV4_Msk (0x3U << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */ +#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */ /*!< MCO configuration */ -#define RCC_CFGR_MCOSEL ((uint32_t)0x0F000000U) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ -#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ -#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ -#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000U) /*!< Bit 2 */ -#define RCC_CFGR_MCOSEL_3 ((uint32_t)0x08000000U) /*!< Bit 3 */ +#define RCC_CFGR_MCOSEL_Pos (24U) +#define RCC_CFGR_MCOSEL_Msk (0xFU << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */ +#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */ +#define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ +#define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */ -#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */ -#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000U) /*!< System clock selected as MCO source */ -#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000U) /*!< Internal 16 MHz RC oscillator clock selected */ -#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000U) /*!< Internal Medium Speed RC oscillator clock selected */ -#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000U) /*!< External 1-25 MHz oscillator clock selected */ -#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000U) /*!< PLL clock divided */ -#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000U) /*!< LSI selected */ -#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000U) /*!< LSE selected */ -#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000U) /*!< HSI48 clock selected as MCO source */ +#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */ +#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U) +#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */ +#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */ +#define RCC_CFGR_MCOSEL_HSI_Pos (25U) +#define RCC_CFGR_MCOSEL_HSI_Msk (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */ +#define RCC_CFGR_MCOSEL_MSI_Pos (24U) +#define RCC_CFGR_MCOSEL_MSI_Msk (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */ +#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */ +#define RCC_CFGR_MCOSEL_HSE_Pos (26U) +#define RCC_CFGR_MCOSEL_HSE_Msk (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */ +#define RCC_CFGR_MCOSEL_PLL_Pos (24U) +#define RCC_CFGR_MCOSEL_PLL_Msk (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */ +#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */ +#define RCC_CFGR_MCOSEL_LSI_Pos (25U) +#define RCC_CFGR_MCOSEL_LSI_Msk (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */ +#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */ +#define RCC_CFGR_MCOSEL_LSE_Pos (24U) +#define RCC_CFGR_MCOSEL_LSE_Msk (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */ +#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */ +#define RCC_CFGR_MCOSEL_HSI48_Pos (27U) +#define RCC_CFGR_MCOSEL_HSI48_Msk (0x1U << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */ +#define RCC_CFGR_MCOSEL_HSI48 RCC_CFGR_MCOSEL_HSI48_Msk /*!< HSI48 clock selected as MCO source */ -#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000U) /*!< MCO prescaler */ -#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */ -#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */ -#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000U) /*!< MCO is divided by 8 */ +#define RCC_CFGR_MCOPRE_Pos (28U) +#define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ +#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */ +#define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ +#define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ -#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000U) /*!< MCO is divided by 1 */ -#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */ -#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */ -#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000U) /*!< MCO is divided by 8 */ -#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000U) /*!< MCO is divided by 16 */ +#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ +#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ +#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ +#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ +#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ /* Legacy defines */ +#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK +#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK +#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI +#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI +#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE +#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL +#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI +#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE +#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48 + #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */ #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */ #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */ @@ -2498,54 +4102,118 @@ typedef struct #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */ /*!<****************** Bit definition for RCC_CIER register ********************/ -#define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Enable */ -#define RCC_CIER_LSERDYIE ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Enable */ -#define RCC_CIER_HSIRDYIE ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Enable */ -#define RCC_CIER_HSERDYIE ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Enable */ -#define RCC_CIER_PLLRDYIE ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Enable */ -#define RCC_CIER_MSIRDYIE ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Enable */ -#define RCC_CIER_HSI48RDYIE ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt Enable */ -#define RCC_CIER_CSSLSE ((uint32_t)0x00000080U) /*!< LSE CSS Interrupt Enable */ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ +#define RCC_CIER_HSIRDYIE_Pos (2U) +#define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ +#define RCC_CIER_HSERDYIE_Pos (3U) +#define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ +#define RCC_CIER_PLLRDYIE_Pos (4U) +#define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ +#define RCC_CIER_MSIRDYIE_Pos (5U) +#define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */ +#define RCC_CIER_HSI48RDYIE_Pos (6U) +#define RCC_CIER_HSI48RDYIE_Msk (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk /*!< HSI48 Ready Interrupt Enable */ +#define RCC_CIER_CSSLSE_Pos (7U) +#define RCC_CIER_CSSLSE_Msk (0x1U << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */ /* Reference defines */ #define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE /*!<****************** Bit definition for RCC_CIFR register ********************/ -#define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt flag */ -#define RCC_CIFR_LSERDYF ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt flag */ -#define RCC_CIFR_HSIRDYF ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt flag */ -#define RCC_CIFR_HSERDYF ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt flag */ -#define RCC_CIFR_PLLRDYF ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt flag */ -#define RCC_CIFR_MSIRDYF ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt flag */ -#define RCC_CIFR_HSI48RDYF ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt flag */ -#define RCC_CIFR_CSSLSEF ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt flag */ -#define RCC_CIFR_CSSHSEF ((uint32_t)0x00000100U) /*!< HSE Clock Security System Interrupt flag */ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ +#define RCC_CIFR_HSIRDYF_Pos (2U) +#define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ +#define RCC_CIFR_HSERDYF_Pos (3U) +#define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ +#define RCC_CIFR_PLLRDYF_Pos (4U) +#define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ +#define RCC_CIFR_MSIRDYF_Pos (5U) +#define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */ +#define RCC_CIFR_HSI48RDYF_Pos (6U) +#define RCC_CIFR_HSI48RDYF_Msk (0x1U << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk /*!< HSI48 Ready Interrupt flag */ +#define RCC_CIFR_CSSLSEF_Pos (7U) +#define RCC_CIFR_CSSLSEF_Msk (0x1U << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */ +#define RCC_CIFR_CSSHSEF_Pos (8U) +#define RCC_CIFR_CSSHSEF_Msk (0x1U << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */ /* Reference defines */ #define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF #define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF /*!<****************** Bit definition for RCC_CICR register ********************/ -#define RCC_CICR_LSIRDYC ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Clear */ -#define RCC_CICR_LSERDYC ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Clear */ -#define RCC_CICR_HSIRDYC ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Clear */ -#define RCC_CICR_HSERDYC ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Clear */ -#define RCC_CICR_PLLRDYC ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Clear */ -#define RCC_CICR_MSIRDYC ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Clear */ -#define RCC_CICR_HSI48RDYC ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt Clear */ -#define RCC_CICR_CSSLSEC ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt Clear */ -#define RCC_CICR_CSSHSEC ((uint32_t)0x00000100U) /*!< HSE Clock Security System Interrupt Clear */ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ +#define RCC_CICR_HSIRDYC_Pos (2U) +#define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ +#define RCC_CICR_HSERDYC_Pos (3U) +#define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ +#define RCC_CICR_PLLRDYC_Pos (4U) +#define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ +#define RCC_CICR_MSIRDYC_Pos (5U) +#define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */ +#define RCC_CICR_HSI48RDYC_Pos (6U) +#define RCC_CICR_HSI48RDYC_Msk (0x1U << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk /*!< HSI48 Ready Interrupt Clear */ +#define RCC_CICR_CSSLSEC_Pos (7U) +#define RCC_CICR_CSSLSEC_Msk (0x1U << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */ +#define RCC_CICR_CSSHSEC_Pos (8U) +#define RCC_CICR_CSSHSEC_Msk (0x1U << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */ /* Reference defines */ #define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC #define RCC_CICR_CSSC RCC_CICR_CSSHSEC /***************** Bit definition for RCC_IOPRSTR register ******************/ -#define RCC_IOPRSTR_IOPARST ((uint32_t)0x00000001U) /*!< GPIO port A reset */ -#define RCC_IOPRSTR_IOPBRST ((uint32_t)0x00000002U) /*!< GPIO port B reset */ -#define RCC_IOPRSTR_IOPCRST ((uint32_t)0x00000004U) /*!< GPIO port C reset */ -#define RCC_IOPRSTR_IOPDRST ((uint32_t)0x00000008U) /*!< GPIO port D reset */ -#define RCC_IOPRSTR_IOPERST ((uint32_t)0x00000010U) /*!< GPIO port E reset */ -#define RCC_IOPRSTR_IOPHRST ((uint32_t)0x00000080U) /*!< GPIO port H reset */ +#define RCC_IOPRSTR_IOPARST_Pos (0U) +#define RCC_IOPRSTR_IOPARST_Msk (0x1U << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */ +#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */ +#define RCC_IOPRSTR_IOPBRST_Pos (1U) +#define RCC_IOPRSTR_IOPBRST_Msk (0x1U << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */ +#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */ +#define RCC_IOPRSTR_IOPCRST_Pos (2U) +#define RCC_IOPRSTR_IOPCRST_Msk (0x1U << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */ +#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */ +#define RCC_IOPRSTR_IOPDRST_Pos (3U) +#define RCC_IOPRSTR_IOPDRST_Msk (0x1U << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */ +#define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */ +#define RCC_IOPRSTR_IOPERST_Pos (4U) +#define RCC_IOPRSTR_IOPERST_Msk (0x1U << RCC_IOPRSTR_IOPERST_Pos) /*!< 0x00000010 */ +#define RCC_IOPRSTR_IOPERST RCC_IOPRSTR_IOPERST_Msk /*!< GPIO port E reset */ +#define RCC_IOPRSTR_IOPHRST_Pos (7U) +#define RCC_IOPRSTR_IOPHRST_Msk (0x1U << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */ +#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */ /* Reference defines */ #define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */ @@ -2557,56 +4225,130 @@ typedef struct /****************** Bit definition for RCC_AHBRST register ******************/ -#define RCC_AHBRSTR_DMARST ((uint32_t)0x00000001U) /*!< DMA1 reset */ -#define RCC_AHBRSTR_MIFRST ((uint32_t)0x00000100U) /*!< Memory interface reset reset */ -#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000U) /*!< CRC reset */ -#define RCC_AHBRSTR_TSCRST ((uint32_t)0x00010000U) /*!< TSC reset */ -#define RCC_AHBRSTR_RNGRST ((uint32_t)0x00100000U) /*!< RNG reset */ +#define RCC_AHBRSTR_DMARST_Pos (0U) +#define RCC_AHBRSTR_DMARST_Msk (0x1U << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */ +#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */ +#define RCC_AHBRSTR_MIFRST_Pos (8U) +#define RCC_AHBRSTR_MIFRST_Msk (0x1U << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */ +#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset reset */ +#define RCC_AHBRSTR_CRCRST_Pos (12U) +#define RCC_AHBRSTR_CRCRST_Msk (0x1U << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */ +#define RCC_AHBRSTR_TSCRST_Pos (16U) +#define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */ +#define RCC_AHBRSTR_RNGRST_Pos (20U) +#define RCC_AHBRSTR_RNGRST_Msk (0x1U << RCC_AHBRSTR_RNGRST_Pos) /*!< 0x00100000 */ +#define RCC_AHBRSTR_RNGRST RCC_AHBRSTR_RNGRST_Msk /*!< RNG reset */ /* Reference defines */ #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */ /***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001U) /*!< SYSCFG clock reset */ -#define RCC_APB2RSTR_TIM21RST ((uint32_t)0x00000004U) /*!< TIM21 clock reset */ -#define RCC_APB2RSTR_TIM22RST ((uint32_t)0x00000020U) /*!< TIM22 clock reset */ -#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200U) /*!< ADC1 clock reset */ -#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000U) /*!< SPI1 clock reset */ -#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000U) /*!< USART1 clock reset */ -#define RCC_APB2RSTR_DBGRST ((uint32_t)0x00400000U) /*!< DBGMCU clock reset */ +#define RCC_APB2RSTR_SYSCFGRST_Pos (0U) +#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ +#define RCC_APB2RSTR_TIM21RST_Pos (2U) +#define RCC_APB2RSTR_TIM21RST_Msk (0x1U << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 clock reset */ +#define RCC_APB2RSTR_TIM22RST_Pos (5U) +#define RCC_APB2RSTR_TIM22RST_Msk (0x1U << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 clock reset */ +#define RCC_APB2RSTR_ADCRST_Pos (9U) +#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 clock reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ +#define RCC_APB2RSTR_DBGRST_Pos (22U) +#define RCC_APB2RSTR_DBGRST_Msk (0x1U << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU clock reset */ /* Reference defines */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 clock reset */ #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU clock reset */ /***************** Bit definition for RCC_APB1RSTR register *****************/ -#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001U) /*!< Timer 2 clock reset */ -#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002U) /*!< Timer 3 clock reset */ -#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010U) /*!< Timer 6 clock reset */ -#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020U) /*!< Timer 7 clock reset */ -#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200U) /*!< LCD clock reset */ -#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800U) /*!< Window Watchdog clock reset */ -#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000U) /*!< SPI2 clock reset */ -#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000U) /*!< USART 2 clock reset */ -#define RCC_APB1RSTR_LPUART1RST ((uint32_t)0x00040000U) /*!< LPUART1 clock reset */ -#define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000U) /*!< USART4 clock reset */ -#define RCC_APB1RSTR_USART5RST ((uint32_t)0x00100000U) /*!< USART5 clock reset */ -#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000U) /*!< I2C 1 clock reset */ -#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000U) /*!< I2C 2 clock reset */ -#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000U) /*!< USB clock reset */ -#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000U) /*!< CRS clock reset */ -#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000U) /*!< PWR clock reset */ -#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000U) /*!< DAC clock reset */ -#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000U) /*!< I2C 3 clock reset */ -#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x80000000U) /*!< LPTIM1 clock reset */ +#define RCC_APB1RSTR_TIM2RST_Pos (0U) +#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ +#define RCC_APB1RSTR_TIM3RST_Pos (1U) +#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ +#define RCC_APB1RSTR_TIM6RST_Pos (4U) +#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */ +#define RCC_APB1RSTR_TIM7RST_Pos (5U) +#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 clock reset */ +#define RCC_APB1RSTR_LCDRST_Pos (9U) +#define RCC_APB1RSTR_LCDRST_Msk (0x1U << RCC_APB1RSTR_LCDRST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTR_LCDRST RCC_APB1RSTR_LCDRST_Msk /*!< LCD clock reset */ +#define RCC_APB1RSTR_WWDGRST_Pos (11U) +#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ +#define RCC_APB1RSTR_SPI2RST_Pos (14U) +#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ +#define RCC_APB1RSTR_USART2RST_Pos (17U) +#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ +#define RCC_APB1RSTR_LPUART1RST_Pos (18U) +#define RCC_APB1RSTR_LPUART1RST_Msk (0x1U << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 clock reset */ +#define RCC_APB1RSTR_USART4RST_Pos (19U) +#define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART4 clock reset */ +#define RCC_APB1RSTR_USART5RST_Pos (20U) +#define RCC_APB1RSTR_USART5RST_Msk (0x1U << RCC_APB1RSTR_USART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTR_USART5RST RCC_APB1RSTR_USART5RST_Msk /*!< USART5 clock reset */ +#define RCC_APB1RSTR_I2C1RST_Pos (21U) +#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ +#define RCC_APB1RSTR_I2C2RST_Pos (22U) +#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ +#define RCC_APB1RSTR_USBRST_Pos (23U) +#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB clock reset */ +#define RCC_APB1RSTR_CRSRST_Pos (27U) +#define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS clock reset */ +#define RCC_APB1RSTR_PWRRST_Pos (28U) +#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ +#define RCC_APB1RSTR_DACRST_Pos (29U) +#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC clock reset */ +#define RCC_APB1RSTR_I2C3RST_Pos (30U) +#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk /*!< I2C 3 clock reset */ +#define RCC_APB1RSTR_LPTIM1RST_Pos (31U) +#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 clock reset */ /***************** Bit definition for RCC_IOPENR register ******************/ -#define RCC_IOPENR_IOPAEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enable */ -#define RCC_IOPENR_IOPBEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enable */ -#define RCC_IOPENR_IOPCEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enable */ -#define RCC_IOPENR_IOPDEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enable */ -#define RCC_IOPENR_IOPEEN ((uint32_t)0x00000010U) /*!< GPIO port E clock enable */ -#define RCC_IOPENR_IOPHEN ((uint32_t)0x00000080U) /*!< GPIO port H clock enable */ +#define RCC_IOPENR_IOPAEN_Pos (0U) +#define RCC_IOPENR_IOPAEN_Msk (0x1U << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */ +#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */ +#define RCC_IOPENR_IOPBEN_Pos (1U) +#define RCC_IOPENR_IOPBEN_Msk (0x1U << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */ +#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */ +#define RCC_IOPENR_IOPCEN_Pos (2U) +#define RCC_IOPENR_IOPCEN_Msk (0x1U << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */ +#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */ +#define RCC_IOPENR_IOPDEN_Pos (3U) +#define RCC_IOPENR_IOPDEN_Msk (0x1U << RCC_IOPENR_IOPDEN_Pos) /*!< 0x00000008 */ +#define RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk /*!< GPIO port D clock enable */ +#define RCC_IOPENR_IOPEEN_Pos (4U) +#define RCC_IOPENR_IOPEEN_Msk (0x1U << RCC_IOPENR_IOPEEN_Pos) /*!< 0x00000010 */ +#define RCC_IOPENR_IOPEEN RCC_IOPENR_IOPEEN_Msk /*!< GPIO port E clock enable */ +#define RCC_IOPENR_IOPHEN_Pos (7U) +#define RCC_IOPENR_IOPHEN_Msk (0x1U << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */ +#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */ /* Reference defines */ #define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */ @@ -2617,24 +4359,50 @@ typedef struct #define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */ /***************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001U) /*!< DMA1 clock enable */ -#define RCC_AHBENR_MIFEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable bit */ -#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000U) /*!< CRC clock enable */ -#define RCC_AHBENR_TSCEN ((uint32_t)0x00010000U) /*!< TSC clock enable */ -#define RCC_AHBENR_RNGEN ((uint32_t)0x00100000U) /*!< RNG clock enable */ +#define RCC_AHBENR_DMAEN_Pos (0U) +#define RCC_AHBENR_DMAEN_Msk (0x1U << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */ +#define RCC_AHBENR_MIFEN_Pos (8U) +#define RCC_AHBENR_MIFEN_Msk (0x1U << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */ +#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */ +#define RCC_AHBENR_CRCEN_Pos (12U) +#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ +#define RCC_AHBENR_TSCEN_Pos (16U) +#define RCC_AHBENR_TSCEN_Msk (0x1U << RCC_AHBENR_TSCEN_Pos) /*!< 0x00010000 */ +#define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TSC clock enable */ +#define RCC_AHBENR_RNGEN_Pos (20U) +#define RCC_AHBENR_RNGEN_Msk (0x1U << RCC_AHBENR_RNGEN_Pos) /*!< 0x00100000 */ +#define RCC_AHBENR_RNGEN RCC_AHBENR_RNGEN_Msk /*!< RNG clock enable */ /* Reference defines */ #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ /***************** Bit definition for RCC_APB2ENR register ******************/ -#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enable */ -#define RCC_APB2ENR_TIM21EN ((uint32_t)0x00000004U) /*!< TIM21 clock enable */ -#define RCC_APB2ENR_TIM22EN ((uint32_t)0x00000020U) /*!< TIM22 clock enable */ -#define RCC_APB2ENR_FWEN ((uint32_t)0x00000080U) /*!< MiFare Firewall clock enable */ -#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200U) /*!< ADC1 clock enable */ -#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000U) /*!< SPI1 clock enable */ -#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000U) /*!< USART1 clock enable */ -#define RCC_APB2ENR_DBGEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enable */ +#define RCC_APB2ENR_SYSCFGEN_Pos (0U) +#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */ +#define RCC_APB2ENR_TIM21EN_Pos (2U) +#define RCC_APB2ENR_TIM21EN_Msk (0x1U << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */ +#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */ +#define RCC_APB2ENR_TIM22EN_Pos (5U) +#define RCC_APB2ENR_TIM22EN_Msk (0x1U << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */ +#define RCC_APB2ENR_FWEN_Pos (7U) +#define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */ +#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */ +#define RCC_APB2ENR_ADCEN_Pos (9U) +#define RCC_APB2ENR_ADCEN_Msk (0x1U << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */ +#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ +#define RCC_APB2ENR_DBGEN_Pos (22U) +#define RCC_APB2ENR_DBGEN_Msk (0x1U << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */ /* Reference defines */ @@ -2643,33 +4411,83 @@ typedef struct #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */ /***************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001U) /*!< Timer 2 clock enable */ -#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002U) /*!< Timer 3 clock enable */ -#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010U) /*!< Timer 6 clock enable */ -#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020U) /*!< Timer 7 clock enable */ -#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200U) /*!< LCD clock enable */ -#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enable */ -#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000U) /*!< SPI2 clock enable */ -#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000U) /*!< USART2 clock enable */ -#define RCC_APB1ENR_LPUART1EN ((uint32_t)0x00040000U) /*!< LPUART1 clock enable */ -#define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000U) /*!< USART4 clock enable */ -#define RCC_APB1ENR_USART5EN ((uint32_t)0x00100000U) /*!< USART5 clock enable */ -#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000U) /*!< I2C1 clock enable */ -#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000U) /*!< I2C2 clock enable */ -#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000U) /*!< USB clock enable */ -#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000U) /*!< CRS clock enable */ -#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000U) /*!< PWR clock enable */ -#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000U) /*!< DAC clock enable */ -#define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000U) /*!< I2C3 clock enable */ -#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enable */ +#define RCC_APB1ENR_TIM2EN_Pos (0U) +#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */ +#define RCC_APB1ENR_TIM3EN_Pos (1U) +#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_TIM6EN_Pos (4U) +#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ +#define RCC_APB1ENR_TIM7EN_Pos (5U) +#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ +#define RCC_APB1ENR_LCDEN_Pos (9U) +#define RCC_APB1ENR_LCDEN_Msk (0x1U << RCC_APB1ENR_LCDEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1ENR_LCDEN RCC_APB1ENR_LCDEN_Msk /*!< LCD clock enable */ +#define RCC_APB1ENR_WWDGEN_Pos (11U) +#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_SPI2EN_Pos (14U) +#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */ +#define RCC_APB1ENR_USART2EN_Pos (17U) +#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */ +#define RCC_APB1ENR_LPUART1EN_Pos (18U) +#define RCC_APB1ENR_LPUART1EN_Msk (0x1U << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */ +#define RCC_APB1ENR_USART4EN_Pos (19U) +#define RCC_APB1ENR_USART4EN_Msk (0x1U << RCC_APB1ENR_USART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENR_USART4EN RCC_APB1ENR_USART4EN_Msk /*!< USART4 clock enable */ +#define RCC_APB1ENR_USART5EN_Pos (20U) +#define RCC_APB1ENR_USART5EN_Msk (0x1U << RCC_APB1ENR_USART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENR_USART5EN RCC_APB1ENR_USART5EN_Msk /*!< USART5 clock enable */ +#define RCC_APB1ENR_I2C1EN_Pos (21U) +#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */ +#define RCC_APB1ENR_I2C2EN_Pos (22U) +#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */ +#define RCC_APB1ENR_USBEN_Pos (23U) +#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */ +#define RCC_APB1ENR_CRSEN_Pos (27U) +#define RCC_APB1ENR_CRSEN_Msk (0x1U << RCC_APB1ENR_CRSEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enable */ +#define RCC_APB1ENR_PWREN_Pos (28U) +#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ +#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */ +#define RCC_APB1ENR_DACEN_Pos (29U) +#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ +#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC clock enable */ +#define RCC_APB1ENR_I2C3EN_Pos (30U) +#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C3 clock enable */ +#define RCC_APB1ENR_LPTIM1EN_Pos (31U) +#define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */ /****************** Bit definition for RCC_IOPSMENR register ****************/ -#define RCC_IOPSMENR_IOPASMEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enabled in sleep mode */ -#define RCC_IOPSMENR_IOPBSMEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enabled in sleep mode */ -#define RCC_IOPSMENR_IOPCSMEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enabled in sleep mode */ -#define RCC_IOPSMENR_IOPDSMEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enabled in sleep mode */ -#define RCC_IOPSMENR_IOPESMEN ((uint32_t)0x00000010U) /*!< GPIO port E clock enabled in sleep mode */ -#define RCC_IOPSMENR_IOPHSMEN ((uint32_t)0x00000080U) /*!< GPIO port H clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPASMEN_Pos (0U) +#define RCC_IOPSMENR_IOPASMEN_Msk (0x1U << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */ +#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPBSMEN_Pos (1U) +#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1U << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */ +#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPCSMEN_Pos (2U) +#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1U << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */ +#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPDSMEN_Pos (3U) +#define RCC_IOPSMENR_IOPDSMEN_Msk (0x1U << RCC_IOPSMENR_IOPDSMEN_Pos) /*!< 0x00000008 */ +#define RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk /*!< GPIO port D clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPESMEN_Pos (4U) +#define RCC_IOPSMENR_IOPESMEN_Msk (0x1U << RCC_IOPSMENR_IOPESMEN_Pos) /*!< 0x00000010 */ +#define RCC_IOPSMENR_IOPESMEN RCC_IOPSMENR_IOPESMEN_Msk /*!< GPIO port E clock enabled in sleep mode */ +#define RCC_IOPSMENR_IOPHSMEN_Pos (7U) +#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1U << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */ +#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */ /* Reference defines */ #define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */ @@ -2680,124 +4498,248 @@ typedef struct #define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */ /***************** Bit definition for RCC_AHBSMENR register ******************/ -#define RCC_AHBSMENR_DMASMEN ((uint32_t)0x00000001U) /*!< DMA1 clock enabled in sleep mode */ -#define RCC_AHBSMENR_MIFSMEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable during sleep mode */ -#define RCC_AHBSMENR_SRAMSMEN ((uint32_t)0x00000200U) /*!< SRAM clock enabled in sleep mode */ -#define RCC_AHBSMENR_CRCSMEN ((uint32_t)0x00001000U) /*!< CRC clock enabled in sleep mode */ -#define RCC_AHBSMENR_TSCSMEN ((uint32_t)0x00010000U) /*!< TSC clock enabled in sleep mode */ -#define RCC_AHBSMENR_RNGSMEN ((uint32_t)0x00100000U) /*!< RNG clock enabled in sleep mode */ +#define RCC_AHBSMENR_DMASMEN_Pos (0U) +#define RCC_AHBSMENR_DMASMEN_Msk (0x1U << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */ +#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */ +#define RCC_AHBSMENR_MIFSMEN_Pos (8U) +#define RCC_AHBSMENR_MIFSMEN_Msk (0x1U << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */ +#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */ +#define RCC_AHBSMENR_SRAMSMEN_Pos (9U) +#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1U << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */ +#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */ +#define RCC_AHBSMENR_CRCSMEN_Pos (12U) +#define RCC_AHBSMENR_CRCSMEN_Msk (0x1U << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */ +#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */ +#define RCC_AHBSMENR_TSCSMEN_Pos (16U) +#define RCC_AHBSMENR_TSCSMEN_Msk (0x1U << RCC_AHBSMENR_TSCSMEN_Pos) /*!< 0x00010000 */ +#define RCC_AHBSMENR_TSCSMEN RCC_AHBSMENR_TSCSMEN_Msk /*!< TSC clock enabled in sleep mode */ +#define RCC_AHBSMENR_RNGSMEN_Pos (20U) +#define RCC_AHBSMENR_RNGSMEN_Msk (0x1U << RCC_AHBSMENR_RNGSMEN_Pos) /*!< 0x00100000 */ +#define RCC_AHBSMENR_RNGSMEN RCC_AHBSMENR_RNGSMEN_Msk /*!< RNG clock enabled in sleep mode */ /* Reference defines */ #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */ /***************** Bit definition for RCC_APB2SMENR register ******************/ -#define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enabled in sleep mode */ -#define RCC_APB2SMENR_TIM21SMEN ((uint32_t)0x00000004U) /*!< TIM21 clock enabled in sleep mode */ -#define RCC_APB2SMENR_TIM22SMEN ((uint32_t)0x00000020U) /*!< TIM22 clock enabled in sleep mode */ -#define RCC_APB2SMENR_ADCSMEN ((uint32_t)0x00000200U) /*!< ADC1 clock enabled in sleep mode */ -#define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000U) /*!< SPI1 clock enabled in sleep mode */ -#define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000U) /*!< USART1 clock enabled in sleep mode */ -#define RCC_APB2SMENR_DBGSMEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enabled in sleep mode */ +#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U) +#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */ +#define RCC_APB2SMENR_TIM21SMEN_Pos (2U) +#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1U << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */ +#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */ +#define RCC_APB2SMENR_TIM22SMEN_Pos (5U) +#define RCC_APB2SMENR_TIM22SMEN_Msk (0x1U << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */ +#define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */ +#define RCC_APB2SMENR_ADCSMEN_Pos (9U) +#define RCC_APB2SMENR_ADCSMEN_Msk (0x1U << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */ +#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */ +#define RCC_APB2SMENR_SPI1SMEN_Pos (12U) +#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */ +#define RCC_APB2SMENR_USART1SMEN_Pos (14U) +#define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk /*!< USART1 clock enabled in sleep mode */ +#define RCC_APB2SMENR_DBGSMEN_Pos (22U) +#define RCC_APB2SMENR_DBGSMEN_Msk (0x1U << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */ /* Reference defines */ #define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */ #define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */ /***************** Bit definition for RCC_APB1SMENR register ******************/ -#define RCC_APB1SMENR_TIM2SMEN ((uint32_t)0x00000001U) /*!< Timer 2 clock enabled in sleep mode */ -#define RCC_APB1SMENR_TIM3SMEN ((uint32_t)0x00000002U) /*!< Timer 3 clock enabled in sleep mode */ -#define RCC_APB1SMENR_TIM6SMEN ((uint32_t)0x00000010U) /*!< Timer 6 clock enabled in sleep mode */ -#define RCC_APB1SMENR_TIM7SMEN ((uint32_t)0x00000020U) /*!< Timer 7 clock enabled in sleep mode */ -#define RCC_APB1SMENR_LCDSMEN ((uint32_t)0x00000200U) /*!< LCD clock enabled in sleep mode */ -#define RCC_APB1SMENR_WWDGSMEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enabled in sleep mode */ -#define RCC_APB1SMENR_SPI2SMEN ((uint32_t)0x00004000U) /*!< SPI2 clock enabled in sleep mode */ -#define RCC_APB1SMENR_USART2SMEN ((uint32_t)0x00020000U) /*!< USART2 clock enabled in sleep mode */ -#define RCC_APB1SMENR_LPUART1SMEN ((uint32_t)0x00040000U) /*!< LPUART1 clock enabled in sleep mode */ -#define RCC_APB1SMENR_USART4SMEN ((uint32_t)0x00080000U) /*!< USART4 clock enabled in sleep mode */ -#define RCC_APB1SMENR_USART5SMEN ((uint32_t)0x00100000U) /*!< USART5 clock enabled in sleep mode */ -#define RCC_APB1SMENR_I2C1SMEN ((uint32_t)0x00200000U) /*!< I2C1 clock enabled in sleep mode */ -#define RCC_APB1SMENR_I2C2SMEN ((uint32_t)0x00400000U) /*!< I2C2 clock enabled in sleep mode */ -#define RCC_APB1SMENR_USBSMEN ((uint32_t)0x00800000U) /*!< USB clock enabled in sleep mode */ -#define RCC_APB1SMENR_CRSSMEN ((uint32_t)0x08000000U) /*!< CRS clock enabled in sleep mode */ -#define RCC_APB1SMENR_PWRSMEN ((uint32_t)0x10000000U) /*!< PWR clock enabled in sleep mode */ -#define RCC_APB1SMENR_DACSMEN ((uint32_t)0x20000000U) /*!< DAC clock enabled in sleep mode */ -#define RCC_APB1SMENR_I2C3SMEN ((uint32_t)0x40000000U) /*!< I2C3 clock enabled in sleep mode */ -#define RCC_APB1SMENR_LPTIM1SMEN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enabled in sleep mode */ +#define RCC_APB1SMENR_TIM2SMEN_Pos (0U) +#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */ +#define RCC_APB1SMENR_TIM3SMEN_Pos (1U) +#define RCC_APB1SMENR_TIM3SMEN_Msk (0x1U << RCC_APB1SMENR_TIM3SMEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1SMENR_TIM3SMEN RCC_APB1SMENR_TIM3SMEN_Msk /*!< Timer 3 clock enabled in sleep mode */ +#define RCC_APB1SMENR_TIM6SMEN_Pos (4U) +#define RCC_APB1SMENR_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR_TIM6SMEN_Pos) /*!< 0x00000010 */ +#define RCC_APB1SMENR_TIM6SMEN RCC_APB1SMENR_TIM6SMEN_Msk /*!< Timer 6 clock enabled in sleep mode */ +#define RCC_APB1SMENR_TIM7SMEN_Pos (5U) +#define RCC_APB1SMENR_TIM7SMEN_Msk (0x1U << RCC_APB1SMENR_TIM7SMEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1SMENR_TIM7SMEN RCC_APB1SMENR_TIM7SMEN_Msk /*!< Timer 7 clock enabled in sleep mode */ +#define RCC_APB1SMENR_LCDSMEN_Pos (9U) +#define RCC_APB1SMENR_LCDSMEN_Msk (0x1U << RCC_APB1SMENR_LCDSMEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1SMENR_LCDSMEN RCC_APB1SMENR_LCDSMEN_Msk /*!< LCD clock enabled in sleep mode */ +#define RCC_APB1SMENR_WWDGSMEN_Pos (11U) +#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */ +#define RCC_APB1SMENR_SPI2SMEN_Pos (14U) +#define RCC_APB1SMENR_SPI2SMEN_Msk (0x1U << RCC_APB1SMENR_SPI2SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1SMENR_SPI2SMEN RCC_APB1SMENR_SPI2SMEN_Msk /*!< SPI2 clock enabled in sleep mode */ +#define RCC_APB1SMENR_USART2SMEN_Pos (17U) +#define RCC_APB1SMENR_USART2SMEN_Msk (0x1U << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */ +#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U) +#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */ +#define RCC_APB1SMENR_USART4SMEN_Pos (19U) +#define RCC_APB1SMENR_USART4SMEN_Msk (0x1U << RCC_APB1SMENR_USART4SMEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1SMENR_USART4SMEN RCC_APB1SMENR_USART4SMEN_Msk /*!< USART4 clock enabled in sleep mode */ +#define RCC_APB1SMENR_USART5SMEN_Pos (20U) +#define RCC_APB1SMENR_USART5SMEN_Msk (0x1U << RCC_APB1SMENR_USART5SMEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1SMENR_USART5SMEN RCC_APB1SMENR_USART5SMEN_Msk /*!< USART5 clock enabled in sleep mode */ +#define RCC_APB1SMENR_I2C1SMEN_Pos (21U) +#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */ +#define RCC_APB1SMENR_I2C2SMEN_Pos (22U) +#define RCC_APB1SMENR_I2C2SMEN_Msk (0x1U << RCC_APB1SMENR_I2C2SMEN_Pos) /*!< 0x00400000 */ +#define RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_Msk /*!< I2C2 clock enabled in sleep mode */ +#define RCC_APB1SMENR_USBSMEN_Pos (23U) +#define RCC_APB1SMENR_USBSMEN_Msk (0x1U << RCC_APB1SMENR_USBSMEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1SMENR_USBSMEN RCC_APB1SMENR_USBSMEN_Msk /*!< USB clock enabled in sleep mode */ +#define RCC_APB1SMENR_CRSSMEN_Pos (27U) +#define RCC_APB1SMENR_CRSSMEN_Msk (0x1U << RCC_APB1SMENR_CRSSMEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1SMENR_CRSSMEN RCC_APB1SMENR_CRSSMEN_Msk /*!< CRS clock enabled in sleep mode */ +#define RCC_APB1SMENR_PWRSMEN_Pos (28U) +#define RCC_APB1SMENR_PWRSMEN_Msk (0x1U << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */ +#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */ +#define RCC_APB1SMENR_DACSMEN_Pos (29U) +#define RCC_APB1SMENR_DACSMEN_Msk (0x1U << RCC_APB1SMENR_DACSMEN_Pos) /*!< 0x20000000 */ +#define RCC_APB1SMENR_DACSMEN RCC_APB1SMENR_DACSMEN_Msk /*!< DAC clock enabled in sleep mode */ +#define RCC_APB1SMENR_I2C3SMEN_Pos (30U) +#define RCC_APB1SMENR_I2C3SMEN_Msk (0x1U << RCC_APB1SMENR_I2C3SMEN_Pos) /*!< 0x40000000 */ +#define RCC_APB1SMENR_I2C3SMEN RCC_APB1SMENR_I2C3SMEN_Msk /*!< I2C3 clock enabled in sleep mode */ +#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U) +#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */ +#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */ /******************* Bit definition for RCC_CCIPR register *******************/ /*!< USART1 Clock source selection */ -#define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003U) /*!< USART1SEL[1:0] bits */ -#define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ -#define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define RCC_CCIPR_USART1SEL_Pos (0U) +#define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk /*!< USART1SEL[1:0] bits */ +#define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */ /*!< USART2 Clock source selection */ -#define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000CU) /*!< USART2SEL[1:0] bits */ -#define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004U) /*!< Bit 0 */ -#define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008U) /*!< Bit 1 */ +#define RCC_CCIPR_USART2SEL_Pos (2U) +#define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */ +#define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */ /*!< LPUART1 Clock source selection */ -#define RCC_CCIPR_LPUART1SEL ((uint32_t)0x0000C00) /*!< LPUART1SEL[1:0] bits */ -#define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x0000400) /*!< Bit 0 */ -#define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x0000800) /*!< Bit 1 */ +#define RCC_CCIPR_LPUART1SEL_Pos (10U) +#define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */ +#define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */ +#define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */ /*!< I2C1 Clock source selection */ -#define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000U) /*!< I2C1SEL [1:0] bits */ -#define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ -#define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define RCC_CCIPR_I2C1SEL_Pos (12U) +#define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */ +#define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */ /*!< I2C3 Clock source selection */ -#define RCC_CCIPR_I2C3SEL ((uint32_t)0x00030000U) /*!< I2C3SEL [1:0] bits */ -#define RCC_CCIPR_I2C3SEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ -#define RCC_CCIPR_I2C3SEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ +#define RCC_CCIPR_I2C3SEL_Pos (16U) +#define RCC_CCIPR_I2C3SEL_Msk (0x3U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk /*!< I2C3SEL [1:0] bits */ +#define RCC_CCIPR_I2C3SEL_0 (0x1U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR_I2C3SEL_1 (0x2U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */ /*!< LPTIM1 Clock source selection */ -#define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000U) /*!< LPTIM1SEL [1:0] bits */ -#define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ -#define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ +#define RCC_CCIPR_LPTIM1SEL_Pos (18U) +#define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */ +#define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */ /*!< HSI48 Clock source selection */ -#define RCC_CCIPR_HSI48SEL ((uint32_t)0x04000000U) /*!< HSI48 RC clock source selection bit for USB and RNG*/ +#define RCC_CCIPR_HSI48SEL_Pos (26U) +#define RCC_CCIPR_HSI48SEL_Msk (0x1U << RCC_CCIPR_HSI48SEL_Pos) /*!< 0x04000000 */ +#define RCC_CCIPR_HSI48SEL RCC_CCIPR_HSI48SEL_Msk /*!< HSI48 RC clock source selection bit for USB and RNG*/ /* Legacy defines */ #define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL /******************* Bit definition for RCC_CSR register *******************/ -#define RCC_CSR_LSION ((uint32_t)0x00000001U) /*!< Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY ((uint32_t)0x00000002U) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_LSEON ((uint32_t)0x00000100U) /*!< External Low Speed oscillator enable */ -#define RCC_CSR_LSERDY ((uint32_t)0x00000200U) /*!< External Low Speed oscillator Ready */ -#define RCC_CSR_LSEBYP ((uint32_t)0x00000400U) /*!< External Low Speed oscillator Bypass */ +#define RCC_CSR_LSEON_Pos (8U) +#define RCC_CSR_LSEON_Msk (0x1U << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */ +#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */ +#define RCC_CSR_LSERDY_Pos (9U) +#define RCC_CSR_LSERDY_Msk (0x1U << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */ +#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ +#define RCC_CSR_LSEBYP_Pos (10U) +#define RCC_CSR_LSEBYP_Msk (0x1U << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ -#define RCC_CSR_LSEDRV ((uint32_t)0x00001800U) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ -#define RCC_CSR_LSEDRV_0 ((uint32_t)0x00000800U) /*!< Bit 0 */ -#define RCC_CSR_LSEDRV_1 ((uint32_t)0x00001000U) /*!< Bit 1 */ +#define RCC_CSR_LSEDRV_Pos (11U) +#define RCC_CSR_LSEDRV_Msk (0x3U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */ +#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ +#define RCC_CSR_LSEDRV_0 (0x1U << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */ +#define RCC_CSR_LSEDRV_1 (0x2U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */ -#define RCC_CSR_LSECSSON ((uint32_t)0x00002000U) /*!< External Low Speed oscillator CSS Enable */ -#define RCC_CSR_LSECSSD ((uint32_t)0x00004000U) /*!< External Low Speed oscillator CSS Detected */ +#define RCC_CSR_LSECSSON_Pos (13U) +#define RCC_CSR_LSECSSON_Msk (0x1U << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */ +#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */ +#define RCC_CSR_LSECSSD_Pos (14U) +#define RCC_CSR_LSECSSD_Msk (0x1U << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ +#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ /*!< RTC congiguration */ -#define RCC_CSR_RTCSEL ((uint32_t)0x00030000U) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ -#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ +#define RCC_CSR_RTCSEL_Pos (16U) +#define RCC_CSR_RTCSEL_Msk (0x3U << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ +#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_CSR_RTCSEL_0 (0x1U << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */ +#define RCC_CSR_RTCSEL_1 (0x2U << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */ -#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */ -#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000U) /*!< LSE oscillator clock used as RTC clock */ -#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000U) /*!< LSI oscillator clock used as RTC clock */ -#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000U) /*!< HSE oscillator clock used as RTC clock */ +#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ +#define RCC_CSR_RTCSEL_LSE_Pos (16U) +#define RCC_CSR_RTCSEL_LSE_Msk (0x1U << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */ +#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */ +#define RCC_CSR_RTCSEL_LSI_Pos (17U) +#define RCC_CSR_RTCSEL_LSI_Msk (0x1U << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */ +#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */ +#define RCC_CSR_RTCSEL_HSE_Pos (16U) +#define RCC_CSR_RTCSEL_HSE_Msk (0x3U << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */ +#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */ -#define RCC_CSR_RTCEN ((uint32_t)0x00040000U) /*!< RTC clock enable */ -#define RCC_CSR_RTCRST ((uint32_t)0x00080000U) /*!< RTC software reset */ +#define RCC_CSR_RTCEN_Pos (18U) +#define RCC_CSR_RTCEN_Msk (0x1U << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */ +#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */ +#define RCC_CSR_RTCRST_Pos (19U) +#define RCC_CSR_RTCRST_Msk (0x1U << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */ +#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */ -#define RCC_CSR_RMVF ((uint32_t)0x00800000U) /*!< Remove reset flag */ -#define RCC_CSR_FWRSTF ((uint32_t)0x01000000U) /*!< Mifare Firewall reset flag */ -#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000U) /*!< OBL reset flag */ -#define RCC_CSR_PINRSTF ((uint32_t)0x04000000U) /*!< PIN reset flag */ -#define RCC_CSR_PORRSTF ((uint32_t)0x08000000U) /*!< POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000U) /*!< Software Reset flag */ -#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000U) /*!< Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000U) /*!< Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000U) /*!< Low-Power reset flag */ +#define RCC_CSR_RMVF_Pos (23U) +#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_CSR_FWRSTF_Pos (24U) +#define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */ +#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */ +#define RCC_CSR_OBLRSTF_Pos (25U) +#define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ +#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */ +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF_Pos (27U) +#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ /* Reference defines */ #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */ @@ -2809,293 +4751,522 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ -#define RNG_CR_RNGEN ((uint32_t)0x00000004U) -#define RNG_CR_IE ((uint32_t)0x00000008U) +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk /******************** Bits definition for RNG_SR register *******************/ -#define RNG_SR_DRDY ((uint32_t)0x00000001U) -#define RNG_SR_CECS ((uint32_t)0x00000002U) -#define RNG_SR_SECS ((uint32_t)0x00000004U) -#define RNG_SR_CEIS ((uint32_t)0x00000020U) -#define RNG_SR_SEIS ((uint32_t)0x00000040U) +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk /******************************************************************************/ /* */ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +/* +* @brief Specific device feature definitions +*/ +#define RTC_TAMPER1_SUPPORT +#define RTC_TAMPER2_SUPPORT +#define RTC_TAMPER3_SUPPORT +#define RTC_WAKEUP_SUPPORT +#define RTC_BACKUP_SUPPORT + /******************** Bits definition for RTC_TR register *******************/ -#define RTC_TR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_TR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_TR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_TR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_TR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_TR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_TR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_TR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_TR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_TR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_TR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_TR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_TR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_TR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_TR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_TR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_TR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_TR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_TR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_TR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_TR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk /*!< */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk /*!< */ +#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk /*!< */ +#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */ +#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */ +#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk /*!< */ +#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk /*!< */ +#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_DR register *******************/ -#define RTC_DR_YT ((uint32_t)0x00F00000U) /*!< */ -#define RTC_DR_YT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_DR_YT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_DR_YT_2 ((uint32_t)0x00400000U) /*!< */ -#define RTC_DR_YT_3 ((uint32_t)0x00800000U) /*!< */ -#define RTC_DR_YU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_DR_YU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_DR_YU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_DR_YU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_DR_YU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_DR_WDU ((uint32_t)0x0000E000U) /*!< */ -#define RTC_DR_WDU_0 ((uint32_t)0x00002000U) /*!< */ -#define RTC_DR_WDU_1 ((uint32_t)0x00004000U) /*!< */ -#define RTC_DR_WDU_2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_DR_MT ((uint32_t)0x00001000U) /*!< */ -#define RTC_DR_MU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_DR_MU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_DR_MU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_DR_MU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_DR_MU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_DR_DT ((uint32_t)0x00000030U) /*!< */ -#define RTC_DR_DT_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_DR_DT_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_DR_DU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_DR_DU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_DR_DU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_DR_DU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_DR_DU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk /*!< */ +#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk /*!< */ +#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */ +#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk /*!< */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk /*!< */ +#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk /*!< */ +#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk /*!< */ +#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_CR register *******************/ -#define RTC_CR_COE ((uint32_t)0x00800000U) /*!< */ -#define RTC_CR_OSEL ((uint32_t)0x00600000U) /*!< */ -#define RTC_CR_OSEL_0 ((uint32_t)0x00200000U) /*!< */ -#define RTC_CR_OSEL_1 ((uint32_t)0x00400000U) /*!< */ -#define RTC_CR_POL ((uint32_t)0x00100000U) /*!< */ -#define RTC_CR_COSEL ((uint32_t)0x00080000U) /*!< */ -#define RTC_CR_BCK ((uint32_t)0x00040000U) /*!< */ -#define RTC_CR_SUB1H ((uint32_t)0x00020000U) /*!< */ -#define RTC_CR_ADD1H ((uint32_t)0x00010000U) /*!< */ -#define RTC_CR_TSIE ((uint32_t)0x00008000U) /*!< */ -#define RTC_CR_WUTIE ((uint32_t)0x00004000U) /*!< */ -#define RTC_CR_ALRBIE ((uint32_t)0x00002000U) /*!< */ -#define RTC_CR_ALRAIE ((uint32_t)0x00001000U) /*!< */ -#define RTC_CR_TSE ((uint32_t)0x00000800U) /*!< */ -#define RTC_CR_WUTE ((uint32_t)0x00000400U) /*!< */ -#define RTC_CR_ALRBE ((uint32_t)0x00000200U) /*!< */ -#define RTC_CR_ALRAE ((uint32_t)0x00000100U) /*!< */ -#define RTC_CR_FMT ((uint32_t)0x00000040U) /*!< */ -#define RTC_CR_BYPSHAD ((uint32_t)0x00000020U) /*!< */ -#define RTC_CR_REFCKON ((uint32_t)0x00000010U) /*!< */ -#define RTC_CR_TSEDGE ((uint32_t)0x00000008U) /*!< */ -#define RTC_CR_WUCKSEL ((uint32_t)0x00000007U) /*!< */ -#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004U) /*!< */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk /*!< */ +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */ +#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk /*!< */ +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */ +#define RTC_CR_BCK_Pos (18U) +#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ +#define RTC_CR_BCK RTC_CR_BCK_Msk /*!< */ +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */ +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */ +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */ +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */ +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */ +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */ +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */ +#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_ISR register ******************/ -#define RTC_ISR_RECALPF ((uint32_t)0x00010000U) /*!< */ -#define RTC_ISR_TAMP3F ((uint32_t)0x00008000U) /*!< */ -#define RTC_ISR_TAMP2F ((uint32_t)0x00004000U) /*!< */ -#define RTC_ISR_TAMP1F ((uint32_t)0x00002000U) /*!< */ -#define RTC_ISR_TSOVF ((uint32_t)0x00001000U) /*!< */ -#define RTC_ISR_TSF ((uint32_t)0x00000800U) /*!< */ -#define RTC_ISR_WUTF ((uint32_t)0x00000400U) /*!< */ -#define RTC_ISR_ALRBF ((uint32_t)0x00000200U) /*!< */ -#define RTC_ISR_ALRAF ((uint32_t)0x00000100U) /*!< */ -#define RTC_ISR_INIT ((uint32_t)0x00000080U) /*!< */ -#define RTC_ISR_INITF ((uint32_t)0x00000040U) /*!< */ -#define RTC_ISR_RSF ((uint32_t)0x00000020U) /*!< */ -#define RTC_ISR_INITS ((uint32_t)0x00000010U) /*!< */ -#define RTC_ISR_SHPF ((uint32_t)0x00000008U) /*!< */ -#define RTC_ISR_WUTWF ((uint32_t)0x00000004U) /*!< */ -#define RTC_ISR_ALRBWF ((uint32_t)0x00000002U) /*!< */ -#define RTC_ISR_ALRAWF ((uint32_t)0x00000001U) /*!< */ +#define RTC_ISR_RECALPF_Pos (16U) +#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */ +#define RTC_ISR_TAMP3F_Pos (15U) +#define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */ +#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */ +#define RTC_ISR_TAMP2F_Pos (14U) +#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ +#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */ +#define RTC_ISR_TAMP1F_Pos (13U) +#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ +#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */ +#define RTC_ISR_TSOVF_Pos (12U) +#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ +#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */ +#define RTC_ISR_TSF_Pos (11U) +#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ +#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */ +#define RTC_ISR_WUTF_Pos (10U) +#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ +#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */ +#define RTC_ISR_ALRBF_Pos (9U) +#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ +#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */ +#define RTC_ISR_ALRAF_Pos (8U) +#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ +#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */ +#define RTC_ISR_INIT_Pos (7U) +#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */ +#define RTC_ISR_INITF_Pos (6U) +#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */ +#define RTC_ISR_RSF_Pos (5U) +#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */ +#define RTC_ISR_INITS_Pos (4U) +#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */ +#define RTC_ISR_SHPF_Pos (3U) +#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */ +#define RTC_ISR_WUTWF_Pos (2U) +#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */ +#define RTC_ISR_ALRBWF_Pos (1U) +#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */ +#define RTC_ISR_ALRAWF_Pos (0U) +#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */ /******************** Bits definition for RTC_PRER register *****************/ -#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000U) /*!< */ -#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFFU) /*!< */ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */ /******************** Bits definition for RTC_WUTR register *****************/ -#define RTC_WUTR_WUT ((uint32_t)0x0000FFFFU) +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000U) /*!< */ -#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000U) /*!< */ -#define RTC_ALRMAR_DT ((uint32_t)0x30000000U) /*!< */ -#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000U) /*!< */ -#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000U) /*!< */ -#define RTC_ALRMAR_DU ((uint32_t)0x0F000000U) /*!< */ -#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000U) /*!< */ -#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000U) /*!< */ -#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000U) /*!< */ -#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000U) /*!< */ -#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000U) /*!< */ -#define RTC_ALRMAR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_ALRMAR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_ALRMAR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_ALRMAR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080U) /*!< */ -#define RTC_ALRMAR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_ALRMAR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */ +#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */ +#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */ +#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */ +#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */ +#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */ +#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */ +#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */ +#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000U) /*!< */ -#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000U) /*!< */ -#define RTC_ALRMBR_DT ((uint32_t)0x30000000U) /*!< */ -#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000U) /*!< */ -#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000U) /*!< */ -#define RTC_ALRMBR_DU ((uint32_t)0x0F000000U) /*!< */ -#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000U) /*!< */ -#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000U) /*!< */ -#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000U) /*!< */ -#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000U) /*!< */ -#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000U) /*!< */ -#define RTC_ALRMBR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_ALRMBR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_ALRMBR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_ALRMBR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080U) /*!< */ -#define RTC_ALRMBR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_ALRMBR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */ +#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */ +#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */ +#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */ +#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */ +#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */ +#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */ +#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */ +#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_WPR register ******************/ -#define RTC_WPR_KEY ((uint32_t)0x000000FFU) /*!< */ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */ /******************** Bits definition for RTC_SSR register ******************/ -#define RTC_SSR_SS ((uint32_t)0x0000FFFFU) /*!< */ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */ /******************** Bits definition for RTC_SHIFTR register ***************/ -#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFFU) /*!< */ -#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000U) /*!< */ +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */ +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */ /******************** Bits definition for RTC_TSTR register *****************/ -#define RTC_TSTR_PM ((uint32_t)0x00400000U) /*!< */ -#define RTC_TSTR_HT ((uint32_t)0x00300000U) /*!< */ -#define RTC_TSTR_HT_0 ((uint32_t)0x00100000U) /*!< */ -#define RTC_TSTR_HT_1 ((uint32_t)0x00200000U) /*!< */ -#define RTC_TSTR_HU ((uint32_t)0x000F0000U) /*!< */ -#define RTC_TSTR_HU_0 ((uint32_t)0x00010000U) /*!< */ -#define RTC_TSTR_HU_1 ((uint32_t)0x00020000U) /*!< */ -#define RTC_TSTR_HU_2 ((uint32_t)0x00040000U) /*!< */ -#define RTC_TSTR_HU_3 ((uint32_t)0x00080000U) /*!< */ -#define RTC_TSTR_MNT ((uint32_t)0x00007000U) /*!< */ -#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000U) /*!< */ -#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TSTR_MNU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TSTR_ST ((uint32_t)0x00000070U) /*!< */ -#define RTC_TSTR_ST_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_TSTR_ST_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_TSTR_ST_2 ((uint32_t)0x00000040U) /*!< */ -#define RTC_TSTR_SU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_TSTR_SU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_TSTR_SU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_TSTR_SU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_TSTR_SU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */ +#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */ +#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */ +#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */ +#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */ +#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */ +#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_TSDR register *****************/ -#define RTC_TSDR_WDU ((uint32_t)0x0000E000U) /*!< */ -#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000U) /*!< */ -#define RTC_TSDR_MT ((uint32_t)0x00001000U) /*!< */ -#define RTC_TSDR_MU ((uint32_t)0x00000F00U) /*!< */ -#define RTC_TSDR_MU_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TSDR_MU_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TSDR_MU_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TSDR_MU_3 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TSDR_DT ((uint32_t)0x00000030U) /*!< */ -#define RTC_TSDR_DT_0 ((uint32_t)0x00000010U) /*!< */ -#define RTC_TSDR_DT_1 ((uint32_t)0x00000020U) /*!< */ -#define RTC_TSDR_DU ((uint32_t)0x0000000FU) /*!< */ -#define RTC_TSDR_DU_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_TSDR_DU_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_TSDR_DU_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_TSDR_DU_3 ((uint32_t)0x00000008U) /*!< */ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */ +#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */ +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */ +#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */ +#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */ +#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_TSSSR register ****************/ -#define RTC_TSSSR_SS ((uint32_t)0x0000FFFFU) +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /******************** Bits definition for RTC_CALR register *****************/ -#define RTC_CALR_CALP ((uint32_t)0x00008000U) /*!< */ -#define RTC_CALR_CALW8 ((uint32_t)0x00004000U) /*!< */ -#define RTC_CALR_CALW16 ((uint32_t)0x00002000U) /*!< */ -#define RTC_CALR_CALM ((uint32_t)0x000001FFU) /*!< */ -#define RTC_CALR_CALM_0 ((uint32_t)0x00000001U) /*!< */ -#define RTC_CALR_CALM_1 ((uint32_t)0x00000002U) /*!< */ -#define RTC_CALR_CALM_2 ((uint32_t)0x00000004U) /*!< */ -#define RTC_CALR_CALM_3 ((uint32_t)0x00000008U) /*!< */ -#define RTC_CALR_CALM_4 ((uint32_t)0x00000010U) /*!< */ -#define RTC_CALR_CALM_5 ((uint32_t)0x00000020U) /*!< */ -#define RTC_CALR_CALM_6 ((uint32_t)0x00000040U) /*!< */ -#define RTC_CALR_CALM_7 ((uint32_t)0x00000080U) /*!< */ -#define RTC_CALR_CALM_8 ((uint32_t)0x00000100U) /*!< */ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */ +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */ +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */ +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */ +#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ /* Legacy defines */ #define RTC_CAL_CALP RTC_CALR_CALP @@ -3113,152 +5284,314 @@ typedef struct #define RTC_CAL_CALM_8 RTC_CALR_CALM_8 /******************** Bits definition for RTC_TAMPCR register ****************/ -#define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000U) /*!< */ -#define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000U) /*!< */ -#define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000U) /*!< */ -#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000U) /*!< */ -#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000U) /*!< */ -#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000U) /*!< */ -#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000U) /*!< */ -#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000U) /*!< */ -#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000U) /*!< */ -#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000U) /*!< */ -#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000U) /*!< */ -#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000U) /*!< */ -#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000U) /*!< */ -#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800U) /*!< */ -#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800U) /*!< */ -#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200U) /*!< */ -#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400U) /*!< */ -#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080U) /*!< */ -#define RTC_TAMPCR_TAMP3TRG ((uint32_t)0x00000040U) /*!< */ -#define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020U) /*!< */ -#define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010U) /*!< */ -#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008U) /*!< */ -#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004U) /*!< */ -#define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002U) /*!< */ -#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001U) /*!< */ +#define RTC_TAMPCR_TAMP3MF_Pos (24U) +#define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ +#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */ +#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U) +#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */ +#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */ +#define RTC_TAMPCR_TAMP3IE_Pos (22U) +#define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */ +#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */ +#define RTC_TAMPCR_TAMP2MF_Pos (21U) +#define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */ +#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */ +#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U) +#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */ +#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */ +#define RTC_TAMPCR_TAMP2IE_Pos (19U) +#define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */ +#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */ +#define RTC_TAMPCR_TAMP1MF_Pos (18U) +#define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */ +#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */ +#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U) +#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */ +#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */ +#define RTC_TAMPCR_TAMP1IE_Pos (16U) +#define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ +#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */ +#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) +#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */ +#define RTC_TAMPCR_TAMPPRCH_Pos (13U) +#define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */ +#define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAMPCR_TAMPFLT_Pos (11U) +#define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */ +#define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAMPCR_TAMPFREQ_Pos (8U) +#define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */ +#define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAMPCR_TAMPTS_Pos (7U) +#define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */ +#define RTC_TAMPCR_TAMP3TRG_Pos (6U) +#define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ +#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */ +#define RTC_TAMPCR_TAMP3E_Pos (5U) +#define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ +#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */ +#define RTC_TAMPCR_TAMP2TRG_Pos (4U) +#define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ +#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */ +#define RTC_TAMPCR_TAMP2E_Pos (3U) +#define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ +#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */ +#define RTC_TAMPCR_TAMPIE_Pos (2U) +#define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */ +#define RTC_TAMPCR_TAMP1TRG_Pos (1U) +#define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ +#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */ +#define RTC_TAMPCR_TAMP1E_Pos (0U) +#define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ +#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */ /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000U) -#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000U) -#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000U) -#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000U) -#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000U) -#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFFU) +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000U) -#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000U) -#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000U) -#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000U) -#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000U) -#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFFU) +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT_RMP ((uint32_t)0x00000002U) /*!< */ -#define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001U) /*!< */ +#define RTC_OR_OUT_RMP_Pos (1U) +#define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */ +#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */ +#define RTC_OR_ALARMOUTTYPE_Pos (0U) +#define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */ +#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */ /* Legacy defines */ #define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP /******************** Bits definition for RTC_BKP0R register ****************/ -#define RTC_BKP0R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP0R_Pos (0U) +#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP0R RTC_BKP0R_Msk /*!< */ /******************** Bits definition for RTC_BKP1R register ****************/ -#define RTC_BKP1R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP1R_Pos (0U) +#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP1R RTC_BKP1R_Msk /*!< */ /******************** Bits definition for RTC_BKP2R register ****************/ -#define RTC_BKP2R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP2R_Pos (0U) +#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP2R RTC_BKP2R_Msk /*!< */ /******************** Bits definition for RTC_BKP3R register ****************/ -#define RTC_BKP3R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP3R_Pos (0U) +#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP3R RTC_BKP3R_Msk /*!< */ /******************** Bits definition for RTC_BKP4R register ****************/ -#define RTC_BKP4R ((uint32_t)0xFFFFFFFFU) /*!< */ +#define RTC_BKP4R_Pos (0U) +#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP4R RTC_BKP4R_Msk /*!< */ /******************** Number of backup registers ******************************/ -#define RTC_BKP_NUMBER ((uint32_t)0x00000005U) /*!< */ +#define RTC_BKP_NUMBER (0x00000005U) /*!< */ /******************************************************************************/ /* */ /* Serial Peripheral Interface (SPI) */ /* */ /******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32L0 family) + */ +#define SPI_I2S_SUPPORT /*!< I2S support */ + /******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA ((uint32_t)0x00000001U) /*!< Clock Phase */ -#define SPI_CR1_CPOL ((uint32_t)0x00000002U) /*!< Clock Polarity */ -#define SPI_CR1_MSTR ((uint32_t)0x00000004U) /*!< Master Selection */ -#define SPI_CR1_BR ((uint32_t)0x00000038U) /*!< BR[2:0] bits (Baud Rate Control) */ -#define SPI_CR1_BR_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define SPI_CR1_BR_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ -#define SPI_CR1_BR_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ -#define SPI_CR1_SPE ((uint32_t)0x00000040U) /*!< SPI Enable */ -#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080U) /*!< Frame Format */ -#define SPI_CR1_SSI ((uint32_t)0x00000100U) /*!< Internal slave select */ -#define SPI_CR1_SSM ((uint32_t)0x00000200U) /*!< Software slave management */ -#define SPI_CR1_RXONLY ((uint32_t)0x00000400U) /*!< Receive only */ -#define SPI_CR1_DFF ((uint32_t)0x00000800U) /*!< Data Frame Format */ -#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000U) /*!< Transmit CRC next */ -#define SPI_CR1_CRCEN ((uint32_t)0x00002000U) /*!< Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE ((uint32_t)0x00004000U) /*!< Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000U) /*!< Bidirectional data mode enable */ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ +#define SPI_CR1_CPOL_Pos (1U) +#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ +#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ +#define SPI_CR1_MSTR_Pos (2U) +#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ +#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ +#define SPI_CR1_BR_Pos (3U) +#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */ +#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ +#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ +#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ +#define SPI_CR1_SPE_Pos (6U) +#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ +#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ +#define SPI_CR1_LSBFIRST_Pos (7U) +#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ +#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ +#define SPI_CR1_SSI_Pos (8U) +#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ +#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ +#define SPI_CR1_SSM_Pos (9U) +#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ +#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ +#define SPI_CR1_RXONLY_Pos (10U) +#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ +#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ +#define SPI_CR1_DFF_Pos (11U) +#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ +#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ +#define SPI_CR1_CRCNEXT_Pos (12U) +#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ +#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ +#define SPI_CR1_CRCEN_Pos (13U) +#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ +#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE_Pos (14U) +#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ +#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE_Pos (15U) +#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ +#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ /******************* Bit definition for SPI_CR2 register ********************/ -#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001U) /*!< Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002U) /*!< Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE ((uint32_t)0x00000004U) /*!< SS Output Enable */ -#define SPI_CR2_FRF ((uint32_t)0x00000010U) /*!< Frame Format Enable */ -#define SPI_CR2_ERRIE ((uint32_t)0x00000020U) /*!< Error Interrupt Enable */ -#define SPI_CR2_RXNEIE ((uint32_t)0x00000040U) /*!< RX buffer Not Empty Interrupt Enable */ -#define SPI_CR2_TXEIE ((uint32_t)0x00000080U) /*!< Tx buffer Empty Interrupt Enable */ +#define SPI_CR2_RXDMAEN_Pos (0U) +#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ +#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN_Pos (1U) +#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ +#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE_Pos (2U) +#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ +#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ +#define SPI_CR2_FRF_Pos (4U) +#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ +#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ +#define SPI_CR2_ERRIE_Pos (5U) +#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ +#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ +#define SPI_CR2_RXNEIE_Pos (6U) +#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ +#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE_Pos (7U) +#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ +#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ /******************** Bit definition for SPI_SR register ********************/ -#define SPI_SR_RXNE ((uint32_t)0x00000001U) /*!< Receive buffer Not Empty */ -#define SPI_SR_TXE ((uint32_t)0x00000002U) /*!< Transmit buffer Empty */ -#define SPI_SR_CHSIDE ((uint32_t)0x00000004U) /*!< Channel side */ -#define SPI_SR_UDR ((uint32_t)0x00000008U) /*!< Underrun flag */ -#define SPI_SR_CRCERR ((uint32_t)0x00000010U) /*!< CRC Error flag */ -#define SPI_SR_MODF ((uint32_t)0x00000020U) /*!< Mode fault */ -#define SPI_SR_OVR ((uint32_t)0x00000040U) /*!< Overrun flag */ -#define SPI_SR_BSY ((uint32_t)0x00000080U) /*!< Busy flag */ -#define SPI_SR_FRE ((uint32_t)0x00000100U) /*!< TI frame format error */ +#define SPI_SR_RXNE_Pos (0U) +#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ +#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ +#define SPI_SR_TXE_Pos (1U) +#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ +#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ +#define SPI_SR_CHSIDE_Pos (2U) +#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ +#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ +#define SPI_SR_UDR_Pos (3U) +#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */ +#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ +#define SPI_SR_CRCERR_Pos (4U) +#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ +#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ +#define SPI_SR_MODF_Pos (5U) +#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */ +#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ +#define SPI_SR_OVR_Pos (6U) +#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */ +#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ +#define SPI_SR_BSY_Pos (7U) +#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */ +#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ +#define SPI_SR_FRE_Pos (8U) +#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */ +#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ /******************** Bit definition for SPI_DR register ********************/ -#define SPI_DR_DR ((uint32_t)0x0000FFFFU) /*!< Data Register */ +#define SPI_DR_DR_Pos (0U) +#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ +#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ /******************* Bit definition for SPI_CRCPR register ******************/ -#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFFU) /*!< CRC polynomial register */ +#define SPI_CRCPR_CRCPOLY_Pos (0U) +#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ +#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ /****************** Bit definition for SPI_RXCRCR register ******************/ -#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFFU) /*!< Rx CRC Register */ +#define SPI_RXCRCR_RXCRC_Pos (0U) +#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ /****************** Bit definition for SPI_TXCRCR register ******************/ -#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFFU) /*!< Tx CRC Register */ +#define SPI_TXCRCR_TXCRC_Pos (0U) +#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ /****************** Bit definition for SPI_I2SCFGR register *****************/ -#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001U) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -83,15 +83,15 @@ #include "hal_tick.h" #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/ + #define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* MSI_VALUE */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ @@ -115,8 +115,8 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. + This value must be a multiple of 0x100. */ /******************************************************************************/ /** * @} @@ -146,8 +146,9 @@ variable is updated automatically. */ uint32_t SystemCoreClock = 32000000; -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U}; /** * @} @@ -179,25 +180,25 @@ uint8_t SetSysClock_PLL_HSI(void); void SystemInit (void) { /*!< Set MSION bit */ - RCC->CR |= (uint32_t)0x00000100; + RCC->CR |= (uint32_t)0x00000100U; /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ - RCC->CFGR &= (uint32_t) 0x88FF400C; + RCC->CFGR &= (uint32_t) 0x88FF400CU; /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFF6; + RCC->CR &= (uint32_t)0xFEF6FFF6U; /*!< Reset HSI48ON bit */ - RCC->CRRCR &= (uint32_t)0xFFFFFFFE; + RCC->CRRCR &= (uint32_t)0xFFFFFFFEU; /*!< Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; + RCC->CR &= (uint32_t)0xFFFBFFFFU; /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ - RCC->CFGR &= (uint32_t)0xFF02FFFF; + RCC->CFGR &= (uint32_t)0xFF02FFFFU; /*!< Disable all interrupts */ - RCC->CIER = 0x00000000; + RCC->CIER = 0x00000000U; /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM @@ -259,33 +260,33 @@ void SystemInit (void) */ void SystemCoreClockUpdate (void) { - uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; + uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; switch (tmp) { - case 0x00: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); + case 0x00U: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; + SystemCoreClock = (32768U * (1U << (msirange + 1U))); break; - case 0x04: /* HSI used as system clock */ + case 0x04U: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; break; - case 0x08: /* HSE used as system clock */ + case 0x08U: /* HSE used as system clock */ SystemCoreClock = HSE_VALUE; break; - case 0x0C: /* PLL used as system clock */ + case 0x0CU: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; - pllmul = PLLMulTable[(pllmul >> 18)]; - plldiv = (plldiv >> 22) + 1; + pllmul = PLLMulTable[(pllmul >> 18U)]; + plldiv = (plldiv >> 22U) + 1U; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - if (pllsource == 0x00) + if (pllsource == 0x00U) { /* HSI oscillator clock selected as PLL clock entry */ SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); @@ -297,13 +298,13 @@ void SystemCoreClockUpdate (void) } break; default: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; + SystemCoreClock = (32768U * (1U << (msirange + 1U))); break; } /* Compute HCLK clock frequency --------------------------------------------*/ /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/system_stm32l0xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/system_stm32l0xx.h index c79c720226..fcf7649569 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/system_stm32l0xx.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/system_stm32l0xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32l0xx.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -74,6 +74,11 @@ variable is updated automatically. */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/* +*/ +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/Release_Notes_stm32l0xx_hal.html b/targets/TARGET_STM/TARGET_STM32L0/device/Release_Notes_stm32l0xx_hal.html index 23e4eee14d..d5e838120d 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/Release_Notes_stm32l0xx_hal.html +++ b/targets/TARGET_STM/TARGET_STM32L0/device/Release_Notes_stm32l0xx_hal.html @@ -677,8 +677,32 @@ Notes for STM32L0xx HAL Drivers

Update History

-

V1.5.0/ 8-January-2016

-
+

V1.7.0 / 31-May-2016

+ +
Main +Changes
+ +
  • Maintenance release to fix known defects.
+
  • HAL/LL COMP update
    • Added +missing definition for COMP_INPUT_PLUS_IO6 and +LL_COMP_INPUT_PLUS_IO6, supported by STM32L0 Category1 (STM32L011xx, +STM32L021xx).
    • Removed COMP_INVERTINGINPUT_IO3 definition.
    • Renamed COMP_INVERTINGINPUT_IO2 to COMP_INPUT_MINUS_DAC1_CH2.
    • The EXTI set-up is now managed by HAL_COMP_Init() function, using updated definitions of +COMP_TRIGGERMODE_xxx.
      Therefore, the functions  HAL_COMP_Start_IT() and HAH_COMP_Stop_IT() have been removed.
      In any mode, the application must use HAL_COMP_Start() and HAL_COMP_Stop().
      • For information, this update was already available in V1.6.0.
  • HAL RTC update
    • Updated HAL_RTCEx_SetWakeUpTimer_IT() function by adding clear of Wake-Up flag before enabling the interrupt.
  • HAL LCD update
    • Corrected SYSCFG LCD External Capacitors definitions.
    • Added new __HAL_SYSCFG_VLCD_CAPA_CONFIG() macro to configure the VLCD Decoupling capacitance connection.
    • Added new __HAL_SYSCFG_GET_VLCD_CAPA_CONFIG() macro to return the decoupling of LCD capacitance
      configured by user.
    • Added LCD Voltage output buffer enable macro definitions.

V1.6.0/ 15-April-2016

+ +
Main +Changes
+ +
  • First official release supporting the Low Level drivers for the STM32L0xx family: 
    • Low +Layer drivers APIs provide register level programming: they require +deep knowledge of peripherals described in STM32L0xx Reference Manual.
    • Low +Layer drivers are available for: ADC, COMP, CORTEX, CRC, CRS,DAC, DMA, +EXTI, GPIO, I2C, IWDG, LPTIM, LPUART, PWR, RCC, RNG, RTC, SPI, TIM, +USART, WWDG peripherals and additional Low Level Bus, System and +Utilities APIs.
    • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32l0xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32l0xx_ll_ppp.h file must be included in user code.

  • Updates of the HAL : 
    • HAL_SYSCFG_EnableVREFINT() and HAL_SYSCFG_DisableVREFINT() functions and HAL_VREFINT_Cmd macro suppressed since VREFINT is managed by the system.
    • Several updates on dedicated HAL as specified in the list below. The major changes concerns HAL_COMP and HAL_UART.


List of HAL updates or corrections provided by this release:
  • HAL update
    • Change the way the APB AHB prescaler table is defined inside the HAL.
    • Change the variable 'uwTick' from 'static' to 'global'.
    • Compliancy with MISRA C 2004 rule 10.6 (A "U" suffix shall be applied to all constants of unsigned type)
    • Compliancy +with MISRA C 2004 rule 16.4. (The identifiers used in the declaration +and definition of a function shall be identical) 
  • HAL COMP update
    • Major rework on the lock and on the state machine associated to the COMP HAL.
    • Optimization of several functions and uniformization of the driver within the whole STM32 family.
  • HAL CRYPT update
    • Correct the usage of several compilation switches related to STM32L081xx.
  • HAL DMA update
    • Add the following macro : HAL_DMA_GET_COUNTER.
  • HAL FLASH update
    • Update the two following macros : __HAL_FLASH_PREFETCH_BUFFER_ENABLE and __HAL_FLASH_PREFETCH_BUFFER_DISABLE.
  • HAL IRDA update
    • Improve management of the EIE bits for Tx and Rx transfers.
  • HAL I2C update
    • Allow I2C transmission with data size equal to 0.
    • Add new macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE.
  • HAL LPTIM update
    • Update of the LPTIM driver in order to support the exti line 23.
  • HAL UART update
    • Improve UART state machine behavior in case of interrupts.
    • Update the macros +UART_DIV_SAMPLING8 and UART_DIV_SAMPLING16 to correct UART baudrate calculation
    • Add an RXDATA flush request inside the UART_Receive_IT function when the RxState is not in reception state.
  • HAL RCC update
    • Correct the setup of the global variable 'SystemCoreClock'. 
    • Update of the CRS interrupt sources.
    • Renamed RCC_CRS_SYNCWARM  into RCC_CRS_SYNCWARN and renamed RCC_CRS_TRIMOV into RCC_CRS_TRIMOVF.

V1.5.0/ 8-January-2016

+
Main Changes
diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32_hal_legacy.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32_hal_legacy.h index eaf479b2dd..48b38f6d3b 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32_hal_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32_hal_legacy.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** @@ -129,7 +129,6 @@ /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose * @{ */ - #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 @@ -144,6 +143,72 @@ #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR #endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif /** * @} */ @@ -384,6 +449,7 @@ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH #endif /* STM32F0 || STM32F3 || STM32F1 */ +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 /** * @} */ @@ -424,7 +490,7 @@ #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX @@ -488,6 +554,11 @@ /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose * @{ */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + #define NAND_AddressTypedef NAND_AddressTypeDef #define __ARRAY_ADDRESS ARRAY_ADDRESS @@ -551,6 +622,9 @@ * @{ */ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS +#if defined(STM32F7) + #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif /** * @} */ @@ -646,7 +720,7 @@ */ - /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose * @{ */ #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE @@ -664,7 +738,7 @@ * @} */ - /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose * @{ */ #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE @@ -848,11 +922,82 @@ #define ETH_MMCTGFCR ((uint32_t)0x00000168U) #define ETH_MMCRFCECR ((uint32_t)0x00000194U) #define ETH_MMCRFAECR ((uint32_t)0x00000198U) -#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U) +#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U) + +#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */ +#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */ /** * @} */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ + defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4xx || STM32F7*/ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ @@ -910,7 +1055,10 @@ #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) /** @@ -935,8 +1083,10 @@ /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose * @{ */ -#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter -#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) /** @@ -1037,7 +1187,7 @@ */ - /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose * @{ */ @@ -1412,10 +1562,28 @@ #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif /** * @} */ +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose * @{ */ @@ -2459,7 +2627,7 @@ #endif #if defined(STM32F7) -#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK #endif @@ -2573,6 +2741,34 @@ #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE + /** * @} */ @@ -2861,6 +3057,8 @@ #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 /** * @} */ @@ -2900,14 +3098,15 @@ #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE #define SAI_STREOMODE SAI_STEREOMODE -#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY -#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL -#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL -#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL -#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL -#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL -#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE - +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal.c index 4a0cd1fa74..00ebc15bbc 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -68,23 +68,36 @@ * @{ */ + +/** @defgroup SysTick System Tick + * @{ + */ +/** + * @brief uwTick_variable uwTick variable + */ +__IO uint32_t uwTick; + +/** + * @} + */ + /** @defgroup HAL_Version HAL Version * @{ */ /** - * @brief STM32L0xx HAL Driver version number V1.5.0 + * @brief STM32L0xx HAL Driver version number V1.7.0 */ -#define __STM32L0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L0xx_HAL_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ -#define __STM32L0xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32L0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L0xx_HAL_VERSION ((__STM32L0xx_HAL_VERSION_MAIN << 24)\ - |(__STM32L0xx_HAL_VERSION_SUB1 << 16)\ - |(__STM32L0xx_HAL_VERSION_SUB2 << 8 )\ +#define __STM32L0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32L0xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ +#define __STM32L0xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32L0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32L0xx_HAL_VERSION ((__STM32L0xx_HAL_VERSION_MAIN << 24U)\ + |(__STM32L0xx_HAL_VERSION_SUB1 << 16U)\ + |(__STM32L0xx_HAL_VERSION_SUB2 << 8U )\ |(__STM32L0xx_HAL_VERSION_RC)) -#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFFU) /** * @} @@ -96,7 +109,7 @@ /** @defgroup HAL_Private HAL Private * @{ */ -static __IO uint32_t uwTick; + /** * @} @@ -247,10 +260,10 @@ __weak void HAL_MspDeInit(void) __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { /*Configure the SysTick to have interrupt in 1ms time basis*/ - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); + HAL_SYSTICK_Config(SystemCoreClock/1000U); /*Configure the SysTick IRQ priority */ - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0); + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U); /* Return function status */ return HAL_OK; @@ -319,7 +332,7 @@ __weak uint32_t HAL_GetTick(void) */ __weak void HAL_Delay(__IO uint32_t Delay) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; tickstart = HAL_GetTick(); while((HAL_GetTick() - tickstart) < Delay) { @@ -373,7 +386,7 @@ uint32_t HAL_GetHalVersion(void) */ uint32_t HAL_GetREVID(void) { - return((DBGMCU->IDCODE) >> 16); + return((DBGMCU->IDCODE) >> 16U); } /** @@ -487,25 +500,6 @@ uint32_t HAL_SYSCFG_GetBootMode(void) return (SYSCFG->CFGR1 & SYSCFG_CFGR1_BOOT_MODE); } -/** - * @brief Enables the VREFINT. - * @retval None - */ -void HAL_SYSCFG_EnableVREFINT(void) -{ - /* Enable the VREFINT by setting EN_VREFINT bit in the CFGR3 register */ - SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_EN_VREFINT); -} - -/** - * @brief Disables the VREFINT. - * @retval None - */ -void HAL_SYSCFG_DisableVREFINT(void) -{ - /* Disable the VREFINT by setting EN_VREFINT bit in the CFGR3 register */ - CLEAR_BIT(SYSCFG->CFGR3,SYSCFG_CFGR3_EN_VREFINT); -} /** * @brief Selects the output of internal reference voltage (VREFINT). * The VREFINT output can be routed to(PB0) or diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal.h index 79ae666a70..5e27c77b7a 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** @@ -61,7 +61,7 @@ /** @defgroup SYSCFG_BootMode Boot Mode * @{ */ -#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000) +#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000U) #define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_CFGR1_BOOT_MODE_0) #define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_CFGR1_BOOT_MODE) @@ -75,7 +75,7 @@ #define DBGMCU_SLEEP DBGMCU_CR_DBG_SLEEP #define DBGMCU_STOP DBGMCU_CR_DBG_STOP #define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY -#define IS_DBGMCU_PERIPH(__PERIPH__) ((((__PERIPH__) & (~(DBGMCU_CR_DBG))) == 0x00) && ((__PERIPH__) != 0x00)) +#define IS_DBGMCU_PERIPH(__PERIPH__) ((((__PERIPH__) & (~(DBGMCU_CR_DBG))) == 0x00U) && ((__PERIPH__) != 0x00U)) /** @@ -89,9 +89,9 @@ #define SYSCFG_LCD_EXT_CAPA SYSCFG_CFGR2_CAPA /*!< Connection of internal Vlcd rail to external capacitors */ #define SYSCFG_VLCD_PB2_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_0 /*!< Connection on PB2 */ #define SYSCFG_VLCD_PB12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_1 /*!< Connection on PB12 */ -#define SYSCFG_VLCD_PE11_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_2 /*!< Connection on PB0 */ +#define SYSCFG_VLCD_PB0_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_2 /*!< Connection on PB0 */ #if defined (SYSCFG_CFGR2_CAPA_3) -#define SYSCFG_VLCD_PB0_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_3 /*!< Connection on PE11 */ +#define SYSCFG_VLCD_PE11_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_3 /*!< Connection on PE11 */ #endif #if defined (SYSCFG_CFGR2_CAPA_4) #define SYSCFG_VLCD_PE12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_4 /*!< Connection on PE12 */ @@ -105,7 +105,7 @@ /** @defgroup SYSCFG_VREFINT_OUT_SELECT SYSCFG VREFINT Out Selection * @{ */ -#define SYSCFG_VREFINT_OUT_NONE ((uint32_t)0x00000000) /* no pad connected */ +#define SYSCFG_VREFINT_OUT_NONE ((uint32_t)0x00000000U) /* no pad connected */ #define SYSCFG_VREFINT_OUT_PB0 SYSCFG_CFGR3_VREF_OUT_0 /* Selects PBO as output for the Vrefint */ #define SYSCFG_VREFINT_OUT_PB1 SYSCFG_CFGR3_VREF_OUT_1 /* Selects PB1 as output for the Vrefint */ #define SYSCFG_VREFINT_OUT_PB0_PB1 SYSCFG_CFGR3_VREF_OUT /* Selects PBO and PB1 as output for the Vrefint */ @@ -291,6 +291,36 @@ #define __HAL_SYSCFG_DBG_LP_CONFIG(__DBGLPMODE__) do {assert_param(IS_DBGMCU_PERIPH(__DBGLPMODE__)); \ MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG, (__DBGLPMODE__)); \ } while (0) + +#if defined (LCD_BASE) /* STM32L0x3xx only */ + +/** @brief Macro to configure the VLCD Decoupling capacitance connection. + * + * @param __SYSCFG_VLCD_CAPA__: specifies the decoupling of LCD capacitance for rails connection on GPIO. + * This parameter can be a combination of following values (when available): + * @arg SYSCFG_VLCD_PB2_EXT_CAPA_ON: Connection on PB2 + * @arg SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12 + * @arg SYSCFG_VLCD_PB0_EXT_CAPA_ON: Connection on PB0 + * @arg SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11 + * @arg SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12 + * @retval None + */ +#define __HAL_SYSCFG_VLCD_CAPA_CONFIG(__SYSCFG_VLCD_CAPA__) \ + MODIFY_REG(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA, (uint32_t)(__SYSCFG_VLCD_CAPA__)) + +/** + * @brief Returns the decoupling of LCD capacitance configured by user. + * @retval The LCD capacitance connection as configured by user. The returned can be a combination of : + * SYSCFG_VLCD_PB2_EXT_CAPA_ON: Connection on PB2 + * SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12 + * SYSCFG_VLCD_PB0_EXT_CAPA_ON: Connection on PB0 + * SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11 + * SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12 + */ +#define __HAL_SYSCFG_GET_VLCD_CAPA_CONFIG() READ_BIT(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA) + +#endif + /** * @brief Returns the boot mode as configured by user. * @retval The boot mode as configured by user. The returned can be a value of : @@ -372,8 +402,6 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void); void HAL_DBGMCU_DBG_EnableLowPowerConfig(uint32_t Periph); void HAL_DBGMCU_DBG_DisableLowPowerConfig(uint32_t Periph); uint32_t HAL_SYSCFG_GetBootMode(void); -void HAL_SYSCFG_EnableVREFINT(void); -void HAL_SYSCFG_DisableVREFINT(void); void HAL_SYSCFG_Enable_Lock_VREFINT(void); void HAL_SYSCFG_Disable_Lock_VREFINT(void); void HAL_SYSCFG_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.c index 3774fdcdad..575b3b930c 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_adc.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: @@ -283,12 +283,12 @@ /* Delay for ADC stabilization time. */ /* Maximum delay is 1us (refer to device datasheet, parameter tSTART). */ /* Unit: us */ -#define ADC_STAB_DELAY_US ((uint32_t) 1) +#define ADC_STAB_DELAY_US ((uint32_t) 1U) /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ /* Unit: us */ -#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10) +#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U) /** * @} */ @@ -374,12 +374,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTime)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); - assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); + assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerFrequencyMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff)); @@ -581,7 +581,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) * @note For devices with several ADCs: reset of ADC common registers is done * only if all ADCs sharing the same common group are disabled. * If this is not the case, reset of these common parameters reset is - * bypassed without error reporting: it can be the intended behaviour in + * bypassed without error reporting: it can be the intended behavior in * case of reset of a single ADC while the other ADCs sharing the same * common group is still running. * @param hadc: ADC handle @@ -934,7 +934,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -1009,7 +1009,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti */ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1024,7 +1024,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -1578,7 +1578,7 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) */ /** @addtogroup ADC_Exported_Functions_Group3 - * @brief Peripheral Control functions + * @brief Peripheral Control functions * @verbatim =============================================================================== @@ -1722,7 +1722,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf * "ADC_AnalogWDGConfTypeDef". * @param hadc: ADC handle * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration - * @retval HAL status + * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) { @@ -1882,7 +1882,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) */ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ @@ -1941,7 +1941,7 @@ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) */ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ @@ -1997,7 +1997,7 @@ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) */ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2143,9 +2143,9 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma) static void ADC_DelayMicroSecond(uint32_t microSecond) { /* Compute number of CPU cycles to wait for */ - __IO uint32_t waitLoopIndex = (microSecond * (SystemCoreClock / 1000000)); + __IO uint32_t waitLoopIndex = (microSecond * (SystemCoreClock / 1000000U)); - while(waitLoopIndex != 0) + while(waitLoopIndex != 0U) { waitLoopIndex--; } diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.h index a4987fc57f..4021cf7cc9 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_adc.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief This file contains all the functions prototypes for the ADC firmware * library. ****************************************************************************** @@ -64,36 +64,36 @@ * @brief HAL ADC state machine: ADC states definition (bitfields) */ /* States of ADC global scope */ -#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */ -#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */ -#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */ -#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */ +#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */ +#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /*!< TimeOut occurrence */ /* States of ADC errors */ -#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */ -#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */ -#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */ +#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error occurrence */ /* States of ADC group regular */ -#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, +#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on, multimode ADC master control) */ -#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */ -#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */ -#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32F0 device: End Of Sampling flag raised */ +#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /*!< Overrun occurrence */ +#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800U) /*!< Not available on STM32F0 device: End Of Sampling flag raised */ /* States of ADC group injected */ -#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode, +#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on, multimode ADC master control) */ -#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Not available on STM32F0 device: Conversion data available on group injected */ -#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */ +#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /*!< Not available on STM32F0 device: Conversion data available on group injected */ +#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000U) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */ /* States of ADC analog watchdogs */ -#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */ -#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */ -#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */ +#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */ /* States of ADC multi-mode */ -#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */ /** @@ -114,7 +114,7 @@ typedef struct * @brief ADC Init structure definition * @note The setting of these parameters with function HAL_ADC_Init() is conditioned by the ADC state. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting (as it can be the expected behaviour in case of intended action to update antother parameter (which fullfills the ADC state condition) on the fly). + * without error reporting (as it can be the expected behavior in case of intended action to update antother parameter (which fullfills the ADC state condition) on the fly). */ typedef struct { @@ -255,11 +255,11 @@ typedef struct /** @defgroup ADC_Error_Code ADC Error Code * @{ */ -#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking, - enable/disable, erroneous state */ -#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< OVR error */ -#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */ +#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking, + enable/disable, erroneous state */ +#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< OVR error */ +#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */ /** * @} */ @@ -273,13 +273,13 @@ typedef struct /* Values defined to be higher than worst cases: low clocks freq, */ /* maximum prescalers. */ /* Unit: ms */ -#define ADC_ENABLE_TIMEOUT 10 -#define ADC_DISABLE_TIMEOUT 10 -#define ADC_STOP_CONVERSION_TIMEOUT 10 +#define ADC_ENABLE_TIMEOUT 10U +#define ADC_DISABLE_TIMEOUT 10U +#define ADC_STOP_CONVERSION_TIMEOUT 10U /* Delay of 10us fixed to worst case: maximum CPU frequency 180MHz to have */ /* the minimum number of CPU cycles to fulfill this delay */ - #define ADC_DELAY_10US_MIN_CPU_CYCLES 1800 + #define ADC_DELAY_10US_MIN_CPU_CYCLES 1800U /** * @} */ @@ -287,7 +287,7 @@ typedef struct /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler * @{ */ -#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode divided by 1 */ +#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U) /*!< ADC Asynchronous clock mode divided by 1 */ #define ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ #define ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */ #define ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ @@ -314,7 +314,7 @@ typedef struct /** @defgroup ADC_Resolution ADC Resolution * @{ */ -#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */ +#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC 12-bit resolution */ #define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */ #define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */ #define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */ @@ -325,7 +325,7 @@ typedef struct /** @defgroup ADC_data_align ADC Data Align * @{ */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN) /** @@ -335,7 +335,7 @@ typedef struct /** @defgroup ADC_Regular_External_Trigger_Source_Edge ADC External Trigger Source Edge for Regular Group * @{ */ -#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U) #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0) #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1) #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN) @@ -356,7 +356,7 @@ typedef struct /** @defgroup ADC_Overrun ADC Overrun * @{ */ -#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000) +#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000U) #define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD) /** * @} @@ -366,8 +366,8 @@ typedef struct /** @defgroup ADC_rank ADC rank * @{ */ -#define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ -#define ADC_RANK_NONE ((uint32_t)0x00001001) /*!< Disable the selected rank (selected channel) from sequencer */ +#define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000U) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ +#define ADC_RANK_NONE ((uint32_t)0x00001001U) /*!< Disable the selected rank (selected channel) from sequencer */ /** * @} */ @@ -411,8 +411,8 @@ typedef struct /** @defgroup ADC_Channel_AWD_Masks ADC Channel Masks * @{ */ -#define ADC_CHANNEL_MASK ((uint32_t)0x0007FFFF) -#define ADC_CHANNEL_AWD_MASK ((uint32_t)0x7C000000) +#define ADC_CHANNEL_MASK ((uint32_t)0x0007FFFFU) +#define ADC_CHANNEL_AWD_MASK ((uint32_t)0x7C000000U) /** * @} */ @@ -422,7 +422,7 @@ typedef struct * @{ */ -#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< ADC sampling time 1.5 cycle */ +#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000U) /*!< ADC sampling time 1.5 cycle */ #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_0) /*!< ADC sampling time 7.5 CYCLES */ #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_1) /*!< ADC sampling time 13.5 CYCLES */ #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 28.5 CYCLES */ @@ -449,8 +449,8 @@ typedef struct /* Scan direction backward is considered as additional setting. */ /* In case of migration from another STM32 device, the user will be */ /* warned of change of setting choices with assert check. */ -#define ADC_SCAN_DIRECTION_FORWARD ((uint32_t)0x00000001) /*!< Scan direction forward: from channel 0 to channel 18 */ -#define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002) /*!< Scan direction backward: from channel 18 to channel 0 */ +#define ADC_SCAN_DIRECTION_FORWARD ((uint32_t)0x00000001U) /*!< Scan direction forward: from channel 0 to channel 18 */ +#define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002U) /*!< Scan direction backward: from channel 18 to channel 0 */ #define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */ /** @@ -461,14 +461,14 @@ typedef struct * @{ */ -#define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000) /*!< ADC Oversampling ratio 2x */ -#define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)0x00000004) /*!< ADC Oversampling ratio 4x */ -#define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)0x00000008) /*!< ADC Oversampling ratio 8x */ -#define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)0x0000000C) /*!< ADC Oversampling ratio 16x */ -#define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)0x00000010) /*!< ADC Oversampling ratio 32x */ -#define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)0x00000014) /*!< ADC Oversampling ratio 64x */ -#define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)0x00000018) /*!< ADC Oversampling ratio 128x */ -#define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)0x0000001C) /*!< ADC Oversampling ratio 256x */ +#define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000U) /*!< ADC Oversampling ratio 2x */ +#define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)0x00000004U) /*!< ADC Oversampling ratio 4x */ +#define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)0x00000008U) /*!< ADC Oversampling ratio 8x */ +#define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)0x0000000CU) /*!< ADC Oversampling ratio 16x */ +#define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)0x00000010U) /*!< ADC Oversampling ratio 32x */ +#define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)0x00000014U) /*!< ADC Oversampling ratio 64x */ +#define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)0x00000018U) /*!< ADC Oversampling ratio 128x */ +#define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)0x0000001CU) /*!< ADC Oversampling ratio 256x */ /** * @} */ @@ -476,15 +476,15 @@ typedef struct /** @defgroup ADC_Right_Bit_Shift ADC Right Bit Shift * @{ */ -#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */ -#define ADC_RIGHTBITSHIFT_1 ((uint32_t)0x00000020) /*!< ADC 1 bit shift for oversampling */ -#define ADC_RIGHTBITSHIFT_2 ((uint32_t)0x00000040) /*!< ADC 2 bits shift for oversampling */ -#define ADC_RIGHTBITSHIFT_3 ((uint32_t)0x00000060) /*!< ADC 3 bits shift for oversampling */ -#define ADC_RIGHTBITSHIFT_4 ((uint32_t)0x00000080) /*!< ADC 4 bits shift for oversampling */ -#define ADC_RIGHTBITSHIFT_5 ((uint32_t)0x000000A0) /*!< ADC 5 bits shift for oversampling */ -#define ADC_RIGHTBITSHIFT_6 ((uint32_t)0x000000C0) /*!< ADC 6 bits shift for oversampling */ -#define ADC_RIGHTBITSHIFT_7 ((uint32_t)0x000000E0) /*!< ADC 7 bits shift for oversampling */ -#define ADC_RIGHTBITSHIFT_8 ((uint32_t)0x00000100) /*!< ADC 8 bits shift for oversampling */ +#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000U) /*!< ADC No bit shift for oversampling */ +#define ADC_RIGHTBITSHIFT_1 ((uint32_t)0x00000020U) /*!< ADC 1 bit shift for oversampling */ +#define ADC_RIGHTBITSHIFT_2 ((uint32_t)0x00000040U) /*!< ADC 2 bits shift for oversampling */ +#define ADC_RIGHTBITSHIFT_3 ((uint32_t)0x00000060U) /*!< ADC 3 bits shift for oversampling */ +#define ADC_RIGHTBITSHIFT_4 ((uint32_t)0x00000080U) /*!< ADC 4 bits shift for oversampling */ +#define ADC_RIGHTBITSHIFT_5 ((uint32_t)0x000000A0U) /*!< ADC 5 bits shift for oversampling */ +#define ADC_RIGHTBITSHIFT_6 ((uint32_t)0x000000C0U) /*!< ADC 6 bits shift for oversampling */ +#define ADC_RIGHTBITSHIFT_7 ((uint32_t)0x000000E0U) /*!< ADC 7 bits shift for oversampling */ +#define ADC_RIGHTBITSHIFT_8 ((uint32_t)0x00000100U) /*!< ADC 8 bits shift for oversampling */ /** * @} */ @@ -492,8 +492,8 @@ typedef struct /** @defgroup ADC_Triggered_Oversampling_Mode ADC Triggered Oversampling Mode * @{ */ -#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */ -#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)0x00000200) /*!< ADC No bit shift for oversampling */ +#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000U) /*!< ADC No bit shift for oversampling */ +#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)0x00000200U) /*!< ADC No bit shift for oversampling */ /** * @} */ @@ -501,7 +501,7 @@ typedef struct /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode * @{ */ -#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000) +#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000U) #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN)) #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN) /** @@ -654,7 +654,7 @@ typedef struct * @param _CONTINUOUS_MODE_: Continuous mode. * @retval None */ -#define ADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13) +#define ADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U) /** * @brief Enable ADC scan mode to convert multiple ranks with sequencer. @@ -663,7 +663,7 @@ typedef struct */ #define ADC_SCANDIR(_SCAN_MODE_) \ ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \ - )? (ADC_CFGR1_SCANDIR) : (0x00000000) \ + )? (ADC_CFGR1_SCANDIR) : (0x00000000U) \ ) /** @@ -671,42 +671,42 @@ typedef struct * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. * @retval None */ -#define __HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << 17) +#define __HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U) /** * @brief Enable the ADC DMA continuous request. * @param _DMAContReq_MODE_: DMA continuous request mode. * @retval None */ -#define ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1) +#define ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1U) /** * @brief Enable the ADC Auto Delay. * @param _AutoDelay_: Auto delay bit enable or disable. * @retval None */ -#define __HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14) +#define __HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14U) /** * @brief Enable the ADC LowPowerAutoPowerOff. * @param _AUTOFF_: AutoOff bit enable or disable. * @retval None */ -#define __HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15) +#define __HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15U) /** * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. * @param _Threshold_: Threshold value * @retval None */ -#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16) +#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U) /** * @brief Enable the ADC Low Frequency mode. * @param _LOW_FREQUENCY_MODE_: Low Frequency mode. * @retval None */ -#define __HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25) +#define __HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25U) /** * @brief Shift the offset in function of the selected ADC resolution. @@ -721,7 +721,7 @@ typedef struct * @retval None */ #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \ - ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3)*2)) + ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3U)*2U)) /** * @brief Shift the AWD1 threshold in function of the selected ADC resolution. @@ -736,7 +736,7 @@ typedef struct * @retval None */ #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ - ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3)*2)) + ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U)) /** * @brief Shift the value on the left, less significant are set to 0. @@ -973,10 +973,10 @@ typedef struct * @{ */ #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ - ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \ - (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \ - (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \ - (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F)))) + ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFFU))) || \ + (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FFU))) || \ + (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FFU))) || \ + (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003FU)))) /** * @} */ @@ -984,7 +984,7 @@ typedef struct /** @defgroup ADC_regular_nb_conv_verification ADC Regular Nb Conversion Verification * @{ */ -#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16))) +#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)16U))) /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc_ex.c index 8835a8d961..d9758db350 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: @@ -83,17 +83,17 @@ /* Values defined to be higher than worst cases: low clock frequency, */ /* maximum prescaler. */ /* Unit: ms */ - #define ADC_CALIBRATION_TIMEOUT 10 + #define ADC_CALIBRATION_TIMEOUT 10U /* Delay for VREFINT stabilization time. */ /* Internal reference startup time max value is 3ms (refer to device datasheet, parameter TVREFINT). */ /* Unit: ms */ -#define SYSCFG_BUF_VREFINT_ENABLE_TIMEOUT ((uint32_t) 3) +#define SYSCFG_BUF_VREFINT_ENABLE_TIMEOUT ((uint32_t) 3U) /* Delay for TEMPSENSOR stabilization time. */ -/* Temperature sensor startup time max value is 10µs (refer to device datasheet, parameter tSTART). */ +/* Temperature sensor startup time max value is 10us (refer to device datasheet, parameter tSTART). */ /* Unit: ms */ -#define SYSCFG_BUF_TEMPSENSOR_ENABLE_TIMEOUT ((uint32_t) 1) +#define SYSCFG_BUF_TEMPSENSOR_ENABLE_TIMEOUT ((uint32_t) 1U) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -138,7 +138,7 @@ This subsection provides functions allowing to: HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tickstart=0; + uint32_t tickstart=0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -211,7 +211,7 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t Single assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Return the ADC calibration value */ - return ((hadc->Instance->CALFACT) & 0x0000007F); + return ((hadc->Instance->CALFACT) & 0x0000007FU); } /** @@ -272,16 +272,16 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32 */ HAL_StatusTypeDef HAL_ADCEx_EnableVREFINT(void) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; - /* Enable the Buffer for the ADC by setting EN_VREFINT bit and the ENBUF_SENSOR_ADC in the CFGR3 register */ - SET_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENBUF_VREFINT_ADC | SYSCFG_CFGR3_EN_VREFINT)); + /* Enable the Buffer for the ADC by setting ENBUF_SENSOR_ADC bit in the CFGR3 register */ + SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC); /* Wait for Vrefint buffer effectively enabled */ /* Get tick count */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_ADC_RDYF)) + while(HAL_IS_BIT_CLR(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_RDYF)) { if((HAL_GetTick() - tickstart) > SYSCFG_BUF_VREFINT_ENABLE_TIMEOUT) { @@ -299,8 +299,8 @@ HAL_StatusTypeDef HAL_ADCEx_EnableVREFINT(void) */ void HAL_ADCEx_DisableVREFINT(void) { - /* Disable the Vrefint by resetting EN_VREFINT bit and the ENBUF_SENSOR_ADC in the CFGR3 register */ - CLEAR_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENBUF_VREFINT_ADC | SYSCFG_CFGR3_EN_VREFINT)); + /* Disable the Vrefint by resetting ENBUF_SENSOR_ADC bit in the CFGR3 register */ + CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC); } /** @@ -313,16 +313,16 @@ void HAL_ADCEx_DisableVREFINT(void) */ HAL_StatusTypeDef HAL_ADCEx_EnableVREFINTTempSensor(void) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; - /* Enable the Buffer for the ADC by setting EN_VREFINT bit and the ENBUF_SENSOR_ADC in the CFGR3 register */ - SET_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENBUF_SENSOR_ADC | SYSCFG_CFGR3_EN_VREFINT)); + /* Enable the Buffer for the ADC by setting ENBUF_SENSOR_ADC bit in the CFGR3 register */ + SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC); /* Wait for Vrefint buffer effectively enabled */ /* Get tick count */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_ADC_RDYF)) + while(HAL_IS_BIT_CLR(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_RDYF)) { if((HAL_GetTick() - tickstart) > SYSCFG_BUF_TEMPSENSOR_ENABLE_TIMEOUT) { @@ -334,14 +334,14 @@ HAL_StatusTypeDef HAL_ADCEx_EnableVREFINTTempSensor(void) } /** - * @brief Disables the VEREFINT and Sensor for the ADC. + * @brief Disables the VREFINT and Sensor for the ADC. * @note This is functional only if the LOCK is not set. * @retval None */ void HAL_ADCEx_DisableVREFINTTempSensor(void) { - /* Disable the Vrefint by resetting EN_VREFINT bit and the ENBUF_SENSOR_ADC in the CFGR3 register */ - CLEAR_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENBUF_SENSOR_ADC | SYSCFG_CFGR3_EN_VREFINT)); + /* Disable the Vrefint by resetting ENBUF_SENSOR_ADC bit in the CFGR3 register */ + CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC); } /** diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc_ex.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc_ex.h index 69f32e6c3f..e886b9d759 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_adc_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief This file contains all the functions prototypes for the ADC firmware * library. ****************************************************************************** @@ -65,7 +65,7 @@ /** @defgroup ADCEx_Channel_Mode ADC Single Ended * @{ */ -#define ADC_SINGLE_ENDED (uint32_t)0x00000000 /* dummy value */ +#define ADC_SINGLE_ENDED (uint32_t)0x00000000U /* dummy value */ /** * @} */ @@ -73,7 +73,7 @@ /** @defgroup ADC_External_trigger_Source ADC External Trigger Source * @{ */ -#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)0x00000000U) #define ADC_EXTERNALTRIGCONV_T21_CC2 (ADC_CFGR1_EXTSEL_0) #define ADC_EXTERNALTRIGCONV_T2_TRGO (ADC_CFGR1_EXTSEL_1) #define ADC_EXTERNALTRIGCONV_T2_CC4 (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0) @@ -108,7 +108,7 @@ /** @defgroup ADC_SYSCFG_internal_paths_flags_definition ADC SYSCFG internal paths Flags Definition * @{ */ -#define ADC_FLAG_SENSOR SYSCFG_CFGR3_SENSOR_ADC_RDYF +#define ADC_FLAG_SENSOR SYSCFG_CFGR3_VREFINT_RDYF #define ADC_FLAG_VREFINT SYSCFG_VREFINT_ADC_RDYF /** * @} @@ -130,11 +130,11 @@ * @{ */ /** - * @brief Calibration factor lenght verification (7 bits maximum) + * @brief Calibration factor length verification (7 bits maximum) * @param _Calibration_Factor_: Calibration factor value * @retval None */ -#define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= ((uint32_t)0x7F)) +#define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= ((uint32_t)0x7FU)) /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp.c index 7b48cffce5..0c6748bf20 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp.c @@ -2,16 +2,16 @@ ****************************************************************************** * @file stm32l0xx_hal_comp.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief COMP HAL module driver. - * * This file provides firmware functions to manage the following * functionalities of the COMP peripheral: - * + Initialization/de-initialization functions - * + I/O operation functions - * + Peripheral Control functions - * + Peripheral State functions + * + Initialization and de-initialization functions + * + Start/Stop operation functions in polling mode + * + Start/Stop operation functions in interrupt mode (through EXTI interrupt) + * + Peripheral control functions + * + Peripheral state functions * @verbatim ================================================================================ @@ -19,85 +19,106 @@ ================================================================================ [..] - The STM32L0xx device family integrates 2 analog comparators COMP1 and COMP2: - (#) The non inverting input and inverting input can be set to GPIO pins - as shown in table1. COMP Inputs below. + The STM32L0xx device family integrates two analog comparators instances + COMP1 and COMP2: + (#) The COMP input minus (inverting input) and input plus (non inverting input) + can be set to internal references or to GPIO pins + (refer to GPIO list in reference manual). - (#) The COMP output is available using HAL_COMP_GetOutputLevel() - and can be set on GPIO pins. Refer to table 2. COMP Outputs below. + (#) The COMP output level is available using HAL_COMP_GetOutputLevel() + and can be redirected to other peripherals: GPIO pins (in mode + alternate functions for comparator), timers. + (refer to GPIO list in reference manual). - (#) The COMP output can be redirected to embedded timers (TIM2, TIM21, TIM22...) and LPTIM - Refer to TIM and LPTIM drivers. + (#) Pairs of comparators instances can be combined in window mode + (2 consecutive instances odd and even COMP and COMP). - (#) The comparators COMP1 and COMP2 can be combined in window mode and only COMP2 non inverting input can be used as non-inverting input. - - (#) The 2 comparators have interrupt capability with wake-up - from Sleep and Stop modes (through the EXTI controller): + (#) The comparators have interrupt capability through the EXTI controller + with wake-up from sleep and stop modes: (++) COMP1 is internally connected to EXTI Line 21 (++) COMP2 is internally connected to EXTI Line 22 - From the corresponding IRQ handler, the right interrupt source can be retrieved with the - macro __HAL_COMP_EXTI_GET_FLAG(). Possible values are: - (++) COMP_EXTI_LINE_COMP1 - (++) COMP_EXTI_LINE_COMP2 + From the corresponding IRQ handler, the right interrupt source can be retrieved + using macro __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG(). - -[..] Table 1. COMP Inputs for the STM32L0xx devices - +--------------------------------------------------+ - | | | COMP1 | COMP2 | - |-----------------|----------------|---------------| - | | 1/4 VREFINT | -- | OK | - | | 1/2 VREFINT | -- | OK | - | | 3/4 VREFINT | -- | OK | - | Inverting Input | VREFINT | OK | OK | - | | DAC OUT (PA4) | OK | OK | - | | IO1 | PA0 | PA2 | - | | IO2 | PA5 | PA5 | - | | IO3 | --- | PB3 | - |-----------------|----------------|-------|-------| - | Non Inverting | IO1 | PA1 | PA3 | - | Input | IO2 | --- | PB4 | - | | IO3 | --- | PB5 | - | | IO4 | --- | PB6 | - | | IO5 | --- | PB7 | - +--------------------------------------------------+ - - [..] Table 2. COMP Outputs for the STM32L0xx devices - +---------------+ - | COMP1 | COMP2 | - |-------|-------| - | PA0 | PA2 | - | PA6 | PA7 | - | PA11 | PA12 | - +---------------+ - - ##### How to use this driver ##### ================================================================================ [..] - This driver provides functions to configure and program the Comparators of all STM32L0xx devices. + This driver provides functions to configure and program the comparator instances + of STM32L0xx devices. To use the comparator, perform the following steps: - - (#) Initialize the COMP low level resources by implementing the HAL_COMP_MspInit(). - (++) Configure the comparator input in analog mode using HAL_GPIO_Init(). - (++) Configure the comparator output in alternate function mode using HAL_GPIO_Init() to map the comparator - output to the GPIO pin. - (++) If required enable the VREFINT reference using HAL_VREFINT_Cmd() and HAL_COMP_EnableBuffer_Cmd(). + + (#) Initialize the COMP low level resources by implementing the HAL_COMP_MspInit(): + (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode + using HAL_GPIO_Init(). + (++) If needed, configure the GPIO connected to comparator output in alternate function mode + using HAL_GPIO_Init(). (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator interrupt vector using HAL_NVIC_EnableIRQ() function. - + (#) Configure the comparator using HAL_COMP_Init() function: - (++) Select the inverting input - (++) Select the non-inverting input + (++) Select the input minus (inverting input) + (++) Select the input plus (non-inverting input) (++) Select the output polarity (++) Select the power mode (++) Select the window mode + + -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE() + to enable internal control clock of the comparators. + However, this is a legacy strategy. In future STM32 families, + COMP clock enable must be implemented by user in "HAL_COMP_MspInit()". + Therefore, for compatibility anticipation, it is recommended to + implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()". + + (#) Reconfiguration on-the-fly of comparator can be done by calling again + function HAL_COMP_Init() with new input structure parameters values. + + (#) Enable the comparator using HAL_COMP_Start() function. + + (#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions + to manage comparator outputs (events and output level). + + (#) Disable the comparator using HAL_COMP_Stop() function. + + (#) De-initialize the comparator using HAL_COMP_DeInit() function. + + (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function. + The only way to unlock the comparator is a device hardware reset. - (#) Enable the comparator using HAL_COMP_Start() function - @endverbatim + ****************************************************************************** + + Table 1. COMP inputs and output for STM32L0xx devices + +---------------------------------------------------------+ + | | | COMP1 | COMP2 | + |----------------|----------------|-----------|-----------| + | | IO1 | PA1 | PA3 | + | Input plus | IO2 | --- | PA4 | + | | IO3 | --- | PB5 | + | | IO4 | --- | PB6 | + | | IO5 | --- | PB7 | + |----------------|----------------|-----------------------| + | | 1/4 VrefInt | --- | Available | + | | 1/2 VrefInt | --- | Available | + | | 3/4 VrefInt | --- | Available | + | Input minus | VrefInt | Available | Available | + | | DAC1 channel 1 | Available | Available | + | | DAC1 channel 2 | Available | Available | + | | IO1 | PA0 | PA2 | + | | IO2 | PA5 | PA5 | + | | IO3 | --- | PB3 | + +---------------------------------------------------------+ + | Output | | PA0 (1) | PA2 (1) | + | | | PA6 (1) | PA7 (1) | + | | | PA11 (1) | PA12 (1) | + | | | LPTIM | LPTIM | + | | | TIM (2) | TIM (2) | + +-----------------------------------------------------------+ + (1) GPIO must be set to alternate function for comparator + (2) Comparators output to timers is set in timers instances. + ****************************************************************************** * @attention * @@ -135,38 +156,57 @@ * @{ */ -#ifdef HAL_COMP_MODULE_ENABLED - -/** @addtogroup COMP +/** @defgroup COMP COMP * @brief COMP HAL module driver * @{ */ -/** @addtogroup COMP_Private - * @{ - */ +#ifdef HAL_COMP_MODULE_ENABLED + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* CSR register reset value */ -#define COMP_CSR_RESET_VALUE ((uint32_t)0x00000000) +/** @addtogroup COMP_Private_Constants + * @{ + */ -#define C_REV_ID_A 0x1000 //Cut1.0 -#define C_REV_ID_Z 0x1008 //Cut1.1 -#define C_REV_ID_Y 0x1003 //Cut1.2 +/* Delay for COMP startup time. */ +/* Note: Delay required to reach propagation delay specification. */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSTART"). */ +/* Unit: us */ +#define COMP_DELAY_STARTUP_US ((uint32_t) 25U) /*!< Delay for COMP startup time */ + +/* Delay for COMP voltage scaler stabilization time (voltage from VrefInt, */ +/* delay based on VrefInt startup time). */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "TVREFINT"). */ +/* Unit: us */ +#define COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t)3000U) /*!< Delay for COMP voltage scaler stabilization time */ + +#define COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t) 30U) + +#define C_REV_ID_A 0x1000U /* Cut1.0 */ +#define C_REV_ID_Z 0x1008U /* Cut1.1 */ +#define C_REV_ID_Y 0x1003U /* Cut1.2 */ + +#define C_DEV_ID_L073 0x447U +#define C_DEV_ID_L053 0x417U -#define C_DEV_ID_L073 0x447 -#define C_DEV_ID_L053 0x417 /** * @} */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ -/** @addtogroup COMP_Exported_Functions +/** @defgroup COMP_Exported_Functions COMP Exported Functions * @{ */ -/** @addtogroup COMP_Exported_Functions_Group1 - * @brief Initialization and Configuration functions +/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and de-initialization functions. * @verbatim =============================================================================== @@ -179,74 +219,113 @@ */ /** - * @brief Initializes the COMP according to the specified - * parameters in the COMP_InitTypeDef and create the associated handle. + * @brief Initialize the COMP according to the specified + * parameters in the COMP_InitTypeDef and initialize the associated handle. * @note If the selected comparator is locked, initialization can't be performed. * To unlock the configuration, perform a system reset. * @note When the LPTIM connection is enabled, the following pins LPTIM_IN1(PB5, PC0) - and LPTIM_IN2(PB7, PC2) should not be configured in AF. - * @param hcomp: COMP handle + and LPTIM_IN2(PB7, PC2) should not be configured in alternate function. + * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { - HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp_csr = 0U; + uint32_t exti_line = 0U; + uint32_t comp_voltage_scaler_not_initialized = 0U; + __IO uint32_t wait_loop_index = 0U; + HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != 0x00)) + if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp))) { status = HAL_ERROR; } else { - /* Check the parameter */ + /* Check the parameters */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - assert_param(IS_COMP_INVERTINGINPUT(hcomp->Init.InvertingInput)); - assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput)); + assert_param(IS_COMP_INPUT_PLUS(hcomp->Instance, hcomp->Init.NonInvertingInput)); + assert_param(IS_COMP_INPUT_MINUS(hcomp->Instance, hcomp->Init.InvertingInput)); assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol)); - assert_param(IS_COMP_MODE(hcomp->Init.Mode)); - - if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE) - { - assert_param(IS_COMP_WINDOWMODE_INSTANCE(hcomp->Instance)); - assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); - } + assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode)); + assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); + assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); if(hcomp->State == HAL_COMP_STATE_RESET) { /* Allocate lock resource and initialize it */ hcomp->Lock = HAL_UNLOCKED; + /* Init SYSCFG and the low level hardware to access comparators */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - /* Init the low level hardware : SYSCFG to access comparators */ + /* Note: HAL_COMP_Init() calls __HAL_RCC_SYSCFG_CLK_ENABLE() */ + /* to enable internal control clock of the comparators. */ + /* However, this is a legacy strategy. In future STM32 families, */ + /* COMP clock enable must be implemented by user */ + /* in "HAL_COMP_MspInit()". */ + /* Therefore, for compatibility anticipation, it is recommended */ + /* to implement __HAL_RCC_SYSCFG_CLK_ENABLE() */ + /* in "HAL_COMP_MspInit()". */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Init the low level hardware */ HAL_COMP_MspInit(hcomp); } - /* Change COMP peripheral state */ - hcomp->State = HAL_COMP_STATE_BUSY; - - /* Set COMP parameters */ - /* Set COMPxINSEL bits according to hcomp->Init.InvertingInput value */ - /* Set COMPxNONINSEL bits according to hcomp->Init.NonInvertingInput value */ - /* Set COMPxLPTIMCONNECTION bits according to hcomp->Init.LPTIMConnection value */ - /* Set COMPxPOL bit according to hcomp->Init.OutputPol value */ - /* Set COMPxMODE bits according to hcomp->Init.Mode value */ - /* Set COMP1WM bit according to hcomp->Init.WindowMode value */ - - /* No LPTIM connexion requested */ - if (hcomp->Init.LPTIMConnection == COMP_LPTIMCONNECTION_DISABLED) + /* Set COMP parameters */ + tmp_csr = (hcomp->Init.InvertingInput | + hcomp->Init.OutputPol ); + + /* Configuration specific to comparator instance: COMP2 */ + if ((hcomp->Instance) == COMP2) { - MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \ - hcomp->Init.InvertingInput | \ - hcomp->Init.NonInvertingInput | \ - hcomp->Init.OutputPol | \ - hcomp->Init.Mode | \ - hcomp->Init.WindowMode); + /* Comparator input plus configuration is available on COMP2 only */ + /* Comparator power mode configuration is available on COMP2 only */ + tmp_csr |= (hcomp->Init.NonInvertingInput | + hcomp->Init.Mode ); + + /* COMP2 specificity: when using VrefInt or subdivision of VrefInt, */ + /* specific path must be enabled. */ + if((hcomp->Init.InvertingInput == COMP_INPUT_MINUS_VREFINT) || + (hcomp->Init.InvertingInput == COMP_INPUT_MINUS_1_4VREFINT) || + (hcomp->Init.InvertingInput == COMP_INPUT_MINUS_1_2VREFINT) || + (hcomp->Init.InvertingInput == COMP_INPUT_MINUS_3_4VREFINT) ) + { + /* Memorize voltage scaler state before initialization */ + comp_voltage_scaler_not_initialized = (READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP) == 0U); + + SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP ); + + /* Delay for COMP scaler bridge voltage stabilization */ + /* Apply the delay if voltage scaler bridge is enabled for the first time */ + if (comp_voltage_scaler_not_initialized != 0U) + { + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles. */ + wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000U * 2U))); + while(wait_loop_index != 0U) + { + wait_loop_index--; + } + } + } } - else + + /* Set comparator output connection to LPTIM */ + if (hcomp->Init.LPTIMConnection != COMP_LPTIMCONNECTION_DISABLED) { - /* LPTIM connexion requested on COMP2*/ - if ((hcomp->Instance) == COMP2) + /* LPTIM connexion requested on COMP1 */ + if ((hcomp->Instance) == COMP1) + { + /* Note : COMP1 can be connected to the input 1 of LPTIM if requested */ + assert_param(IS_COMP1_LPTIMCONNECTION(hcomp->Init.LPTIMConnection)); + if (hcomp->Init.LPTIMConnection == COMP_LPTIMCONNECTION_IN1_ENABLED) + { + tmp_csr |= (COMP_CSR_COMP1LPTIM1IN1); + } + } + else { /* Check the MCU_ID in order to allow or not the COMP2 connection to LPTIM-input2 */ if (((HAL_GetDEVID() == C_DEV_ID_L073) && (HAL_GetREVID() == C_REV_ID_A)) @@ -257,14 +336,10 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { /* Note : COMP2 can be connected only to input 1 of LPTIM if requested */ assert_param(IS_COMP2_LPTIMCONNECTION_RESTRICTED(hcomp->Init.LPTIMConnection)); - MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \ - hcomp->Init.InvertingInput | \ - hcomp->Init.NonInvertingInput | \ - COMP_CSR_COMP2LPTIM1IN1 | \ - hcomp->Init.OutputPol | \ - hcomp->Init.Mode | \ - hcomp->Init.WindowMode); + + tmp_csr |= (COMP_CSR_COMP2LPTIM1IN1); } + /* LPTIM connexion requested on COMP2 */ else { /* Note : COMP2 can be connected to input 1 or input2 of LPTIM if requested */ @@ -272,77 +347,130 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) switch (hcomp->Init.LPTIMConnection) { case COMP_LPTIMCONNECTION_IN1_ENABLED : - MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \ - hcomp->Init.InvertingInput | \ - hcomp->Init.NonInvertingInput | \ - COMP_CSR_COMP2LPTIM1IN1 | \ - hcomp->Init.OutputPol | \ - hcomp->Init.Mode | \ - hcomp->Init.WindowMode); + tmp_csr |= (COMP_CSR_COMP2LPTIM1IN1); break; case COMP_LPTIMCONNECTION_IN2_ENABLED : - MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \ - hcomp->Init.InvertingInput | \ - hcomp->Init.NonInvertingInput | \ - COMP_CSR_COMP2LPTIM1IN2 | \ - hcomp->Init.OutputPol | \ - hcomp->Init.Mode | \ - hcomp->Init.WindowMode); + tmp_csr |= (COMP_CSR_COMP2LPTIM1IN2); break; default : - MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \ - hcomp->Init.InvertingInput | \ - hcomp->Init.NonInvertingInput | \ - hcomp->Init.OutputPol | \ - hcomp->Init.Mode | \ - hcomp->Init.WindowMode); break; } } } - else - /* LPTIM connexion requested on COMP1 */ + } + + /* Update comparator register */ + if ((hcomp->Instance) == COMP1) + { + MODIFY_REG(hcomp->Instance->CSR, + COMP_CSR_COMP1INNSEL | COMP_CSR_COMP1WM | + COMP_CSR_COMP1LPTIM1IN1 | COMP_CSR_COMP1POLARITY , + tmp_csr + ); + } + else /* Instance == COMP2 */ + { + MODIFY_REG(hcomp->Instance->CSR, + COMP_CSR_COMP2SPEED | COMP_CSR_COMP2INNSEL | + COMP_CSR_COMP2INPSEL | COMP_CSR_COMP2POLARITY | + COMP_CSR_COMP2LPTIM1IN2 | COMP_CSR_COMP2LPTIM1IN1 , + tmp_csr + ); + } + + /* Set window mode */ + /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */ + /* instances. Therefore, this function can update another COMP */ + /* instance that the one currently selected. */ + if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) + { + SET_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE); + } + else + { + CLEAR_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE); + } + + /* Get the EXTI line corresponding to the selected COMP instance */ + exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); + + /* Manage EXTI settings */ + if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != RESET) + { + /* Configure EXTI rising edge */ + if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != RESET) { - /* Note : COMP1 can be connected to the input 1 of LPTIM if requested */ - assert_param(IS_COMP1_LPTIMCONNECTION(hcomp->Init.LPTIMConnection)); - if (hcomp->Init.LPTIMConnection == COMP_LPTIMCONNECTION_IN1_ENABLED) - MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \ - hcomp->Init.InvertingInput | \ - hcomp->Init.NonInvertingInput | \ - COMP_CSR_COMP1LPTIM1IN1 | \ - hcomp->Init.OutputPol | \ - hcomp->Init.Mode | \ - hcomp->Init.WindowMode); - else - MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \ - hcomp->Init.InvertingInput | \ - hcomp->Init.NonInvertingInput | \ - hcomp->Init.OutputPol | \ - hcomp->Init.Mode | \ - hcomp->Init.WindowMode); + SET_BIT(EXTI->RTSR, exti_line); + } + else + { + CLEAR_BIT(EXTI->RTSR, exti_line); + } + + /* Configure EXTI falling edge */ + if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != RESET) + { + SET_BIT(EXTI->FTSR, exti_line); + } + else + { + CLEAR_BIT(EXTI->FTSR, exti_line); + } + + /* Clear COMP EXTI pending bit (if any) */ + WRITE_REG(EXTI->PR, exti_line); + + /* Configure EXTI event mode */ + if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != RESET) + { + SET_BIT(EXTI->EMR, exti_line); + } + else + { + CLEAR_BIT(EXTI->EMR, exti_line); + } + + /* Configure EXTI interrupt mode */ + if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != RESET) + { + SET_BIT(EXTI->IMR, exti_line); + } + else + { + CLEAR_BIT(EXTI->IMR, exti_line); } } - /* Initialize the COMP state*/ - hcomp->State = HAL_COMP_STATE_READY; - + else + { + /* Disable EXTI event generation */ + CLEAR_BIT(EXTI->EMR, exti_line); + } + + /* Set HAL COMP handle state */ + /* Note: Transition from state reset to state ready, */ + /* otherwise (coming from state ready or busy) no state update. */ + if (hcomp->State == HAL_COMP_STATE_RESET) + { + hcomp->State = HAL_COMP_STATE_READY; + } } return status; } /** - * @brief DeInitializes the COMP peripheral - * @note Deinitialization can't be performed if the COMP configuration is locked. + * @brief DeInitialize the COMP peripheral. + * @note Deinitialization cannot be performed if the COMP configuration is locked. * To unlock the configuration, perform a system reset. - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != 0x00)) + if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp))) { status = HAL_ERROR; } @@ -350,13 +478,14 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - + /* Set COMP_CSR register to reset value */ - WRITE_REG(hcomp->Instance->CSR, COMP_CSR_RESET_VALUE); - + WRITE_REG(hcomp->Instance->CSR, 0x00000000U); + /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */ HAL_COMP_MspDeInit(hcomp); - + + /* Set HAL COMP handle state */ hcomp->State = HAL_COMP_STATE_RESET; /* Release Lock */ @@ -367,32 +496,32 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) } /** - * @brief Initializes the COMP MSP. - * @param hcomp: COMP handle + * @brief Initialize the COMP MSP. + * @param hcomp COMP handle * @retval None */ __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcomp); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_COMP_MspInit could be implenetd in the user file + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_COMP_MspInit could be implemented in the user file */ } /** - * @brief DeInitializes COMP MSP. - * @param hcomp: COMP handle + * @brief DeInitialize the COMP MSP. + * @param hcomp COMP handle * @retval None */ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcomp); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_COMP_MspDeInit could be implenetd in the user file + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_COMP_MspDeInit could be implemented in the user file */ } @@ -400,33 +529,33 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) * @} */ -/** @addtogroup COMP_Exported_Functions_Group2 - * @brief Data transfers functions +/** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions + * @brief Start-Stop operation functions. * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the COMP data - transfers. + [..] This section provides functions allowing to: + (+) Start a comparator instance. + (+) Stop a comparator instance. @endverbatim * @{ */ /** - * @brief Start the comparator - * @param hcomp: COMP handle + * @brief Start the comparator. + * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) -{ +{ + __IO uint32_t wait_loop_index = 0U; HAL_StatusTypeDef status = HAL_OK; - uint32_t extiline = 0; /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != 0x00)) + if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp))) { status = HAL_ERROR; } @@ -437,73 +566,21 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) if(hcomp->State == HAL_COMP_STATE_READY) { - /* Check the Exti Line output configuration */ - extiline = COMP_GET_EXTI_LINE(hcomp->Instance); - - /* Configure the rising edge */ - if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_EVENT_RISING) != 0x0) - { - if (extiline == COMP_EXTI_LINE_COMP1) - { - __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); - } - else - { - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); - } - } - else - { - if (extiline == COMP_EXTI_LINE_COMP1) - { - __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); - } - else - { - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); - } - } - - /* Configure the falling edge */ - if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_EVENT_FALLING) != 0x0) - { - if (extiline == COMP_EXTI_LINE_COMP1) - { - __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); - } - else - { - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); - } - } - else - { - if (extiline == COMP_EXTI_LINE_COMP1) - { - __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); - } - else - { - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); - } - } - - /* Configure the COMP module */ - if (extiline == COMP_EXTI_LINE_COMP1) - { - /* Clear COMP Exti pending bit */ - __HAL_COMP_COMP1_EXTI_CLEAR_FLAG(); - } - else - { - /* Clear COMP Exti pending bit */ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG(); - } - /* Enable the selected comparator */ - __HAL_COMP_ENABLE(hcomp); - - hcomp->State = HAL_COMP_STATE_BUSY; + SET_BIT(hcomp->Instance->CSR, COMP_CSR_COMPxEN); + + /* Set HAL COMP handle state */ + hcomp->State = HAL_COMP_STATE_BUSY; + + /* Delay for COMP startup time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles. */ + wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000U * 2U))); + while(wait_loop_index != 0U) + { + wait_loop_index--; + } } else { @@ -515,16 +592,16 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) } /** - * @brief Stop the comparator - * @param hcomp: COMP handle + * @brief Stop the comparator. + * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) -{ +{ HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != 0x00)) + if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp))) { status = HAL_ERROR; } @@ -532,12 +609,14 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - - if(hcomp->State == HAL_COMP_STATE_BUSY) + + if((hcomp->State == HAL_COMP_STATE_BUSY) || + (hcomp->State == HAL_COMP_STATE_READY) ) { /* Disable the selected comparator */ - __HAL_COMP_DISABLE(hcomp); + CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_COMPxEN); + /* Set HAL COMP handle state */ hcomp->State = HAL_COMP_STATE_READY; } else @@ -550,163 +629,23 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) } /** - * @brief Enables the interrupt and starts the comparator - * @param hcomp: COMP handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t extiline = 0; - - /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != 0x00)) - { - status = HAL_ERROR; - } - else - { - /* Check the parameter */ - assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - - if(hcomp->State == HAL_COMP_STATE_READY) - { - /* Check the Exti Line output configuration */ - extiline = COMP_GET_EXTI_LINE(hcomp->Instance); - - /* Configure the rising edge */ - if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != 0x0) - { - if (extiline == COMP_EXTI_LINE_COMP1) - { - __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); - } - else - { - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); - } - } - else - { - if (extiline == COMP_EXTI_LINE_COMP1) - { - __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); - } - else - { - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); - } - } - - /* Configure the falling edge */ - if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != 0x0) - { - if (extiline == COMP_EXTI_LINE_COMP1) - { - __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); - } - else - { - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); - } - } - else - { - if (extiline == COMP_EXTI_LINE_COMP1) - { - __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); - } - else - { - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); - } - } - - /* Configure the COMP module */ - if (extiline == COMP_EXTI_LINE_COMP1) - { - /* Clear COMP Exti pending bit */ - __HAL_COMP_COMP1_EXTI_CLEAR_FLAG(); - /* Enable Exti interrupt mode */ - __HAL_COMP_COMP1_EXTI_ENABLE_IT(); - } - else - { - /* Clear COMP Exti pending bit */ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG(); - /* Enable Exti interrupt mode */ - __HAL_COMP_COMP2_EXTI_ENABLE_IT(); - } - - /* Enable the selected comparator */ - __HAL_COMP_ENABLE(hcomp); - - hcomp->State = HAL_COMP_STATE_BUSY; - } - else - { - status = HAL_ERROR; - } - } - - return status; -} - -/** - * @brief Disable the interrupt and Stop the comparator - * @param hcomp: COMP handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (COMP_GET_EXTI_LINE(hcomp->Instance) == COMP_EXTI_LINE_COMP1) - { - __HAL_COMP_COMP1_EXTI_DISABLE_IT(); - } - if (COMP_GET_EXTI_LINE(hcomp->Instance) == COMP_EXTI_LINE_COMP2) - { - __HAL_COMP_COMP2_EXTI_DISABLE_IT(); - } - - status = HAL_COMP_Stop(hcomp); - - return status; -} - -/** - * @brief Comparator IRQ Handler - * @param hcomp: COMP handle - * @retval HAL status + * @brief Comparator IRQ handler. + * @param hcomp COMP handle + * @retval None */ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) { - /* Check which exti line is involved */ - uint32_t extiline = COMP_GET_EXTI_LINE(hcomp->Instance); - - /* Manage COMP1 Exti line */ - if (extiline == COMP_EXTI_LINE_COMP1) + /* Get the EXTI line corresponding to the selected COMP instance */ + uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); + + /* Check COMP EXTI flag */ + if(READ_BIT(EXTI->PR, exti_line) != RESET) { - if(__HAL_COMP_COMP1_EXTI_GET_FLAG() != RESET) - { - /* Clear COMP Exti pending bit */ - __HAL_COMP_COMP1_EXTI_CLEAR_FLAG(); - /* COMP trigger user callback */ - HAL_COMP_TriggerCallback(hcomp); - } - } - - /* Manage COMP2 Exti line */ - if (extiline == COMP_EXTI_LINE_COMP2) - { - if(__HAL_COMP_COMP2_EXTI_GET_FLAG() != RESET) - { - /* Clear COMP Exti pending bit */ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG(); - /* COMP trigger user callback */ - HAL_COMP_TriggerCallback(hcomp); - } + /* Clear COMP EXTI pending bit */ + WRITE_REG(EXTI->PR, exti_line); + + /* COMP trigger user callback */ + HAL_COMP_TriggerCallback(hcomp); } } @@ -714,54 +653,44 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) * @} */ -/** @addtogroup COMP_Exported_Functions_Group3 - * @brief management functions +/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions + * @brief Management functions. * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] - This subsection provides a set of functions allowing to control the COMP data - transfers. + This subsection provides a set of functions allowing to control the comparators. @endverbatim * @{ */ /** - * @brief Lock the selected comparator configuration. - * @param hcomp: COMP handle + * @brief Lock the selected comparator configuration. + * @note A system reset is required to unlock the comparator configuration. + * @note Locking the comparator from reset state is possible + * if __HAL_RCC_SYSCFG_CLK_ENABLE() is being called before. + * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != 0x00)) + if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp))) { status = HAL_ERROR; } else { - /* Check the parameter */ + /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - - /* Set lock flag on state */ - switch(hcomp->State) - { - case HAL_COMP_STATE_BUSY: - hcomp->State = HAL_COMP_STATE_BUSY_LOCKED; - break; - case HAL_COMP_STATE_READY: - hcomp->State = HAL_COMP_STATE_READY_LOCKED; - break; - default: - /* unexpected state */ - status = HAL_ERROR; - break; - } + + /* Set HAL COMP handle state */ + hcomp->State = ((HAL_COMP_StateTypeDef)(hcomp->State | COMP_STATE_BITFIELD_LOCK)); } if(status == HAL_OK) @@ -777,17 +706,19 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) * @brief Return the output level (high or low) of the selected comparator. * The output level depends on the selected polarity. * If the polarity is not inverted: - * - Comparator output is low when the non-inverting input is at a lower - * voltage than the inverting input - * - Comparator output is high when the non-inverting input is at a higher - * voltage than the inverting input + * - Comparator output is low when the input plus is at a lower + * voltage than the input minus + * - Comparator output is high when the input plus is at a higher + * voltage than the input minus * If the polarity is inverted: - * - Comparator output is high when the non-inverting input is at a lower - * voltage than the inverting input - * - Comparator output is low when the non-inverting input is at a higher - * voltage than the inverting input - * @param hcomp: COMP handle - * @retval Returns the selected comparator output level: COMP_OUTPUTLEVEL_LOW or COMP_OUTPUTLEVEL_HIGH. + * - Comparator output is high when the input plus is at a lower + * voltage than the input minus + * - Comparator output is low when the input plus is at a higher + * voltage than the input minus + * @param hcomp COMP handle + * @retval Returns the selected comparator output level: + * @arg @ref COMP_OUTPUT_LEVEL_LOW + * @arg @ref COMP_OUTPUT_LEVEL_HIGH * */ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) @@ -795,19 +726,20 @@ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - return((uint32_t)(hcomp->Instance->CSR & COMP_OUTPUTLEVEL_HIGH)); + return (uint32_t)(READ_BIT(hcomp->Instance->CSR, COMP_CSR_COMPxOUTVALUE) + >> COMP_OUTPUT_LEVEL_BITOFFSET_POS); } /** * @brief Comparator callback. - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval None */ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcomp); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_COMP_TriggerCallback should be implemented in the user file */ @@ -818,24 +750,23 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) * @} */ -/** @addtogroup COMP_Exported_Functions_Group4 - * @brief Peripheral State functions +/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions. * @verbatim =============================================================================== ##### Peripheral State functions ##### =============================================================================== [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. + This subsection permit to get in run-time the status of the peripheral. @endverbatim * @{ */ /** - * @brief Return the COMP state - * @param hcomp : COMP handle + * @brief Return the COMP handle state. + * @param hcomp COMP handle * @retval HAL state */ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) @@ -849,14 +780,10 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + /* Return HAL COMP handle state */ return hcomp->State; } -/** - * @} - */ - - /** * @} */ @@ -866,10 +793,12 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) */ #endif /* HAL_COMP_MODULE_ENABLED */ +/** + * @} + */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp.h index 478a57f679..d2ba7e2141 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_comp.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of COMP HAL module. ****************************************************************************** * @attention @@ -50,78 +50,65 @@ * @{ */ -/** @defgroup COMP COMP +/** @addtogroup COMP * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ - /** @defgroup COMP_Exported_Types COMP Exported Types * @{ */ - /** @defgroup COMP_Init COMP init configuration structure - * @{ - */ /** * @brief COMP Init structure definition */ - typedef struct { - uint32_t InvertingInput; /*!< Selects the inverting input of the comparator. - This parameter can be a value of @ref COMP_InvertingInput */ - - uint32_t NonInvertingInput; /*!< Selects the non inverting input of the comparator. - This parameter can be a value of @ref COMP_NonInvertingInput */ - - uint32_t LPTIMConnection; /*!< Selects if the COMP connection to the LPTIM is established or not. - This parameter can be a value of @ref COMP_LPTIMConnection */ - - uint32_t OutputPol; /*!< Selects the output polarity of the comparator. - This parameter can be a value of @ref COMP_OutputPolarity */ - - uint32_t Mode; /*!< Selects the operating comsumption mode of the comparator - to adjust the speed/consumption. - This parameter can be a value of @ref COMP_Mode */ - - uint32_t WindowMode; /*!< Selects the window mode of the comparator. + uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances + (2 consecutive instances odd and even COMP and COMP). + Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode. This parameter can be a value of @ref COMP_WindowMode */ - uint32_t TriggerMode; /*!< Selects the trigger mode of the comparator (interrupt mode). - This parameter can be a value of @ref COMP_TriggerMode */ - + uint32_t Mode; /*!< Set comparator operating mode to adjust power and speed. + Note: For the characteritics of comparator power modes + (propagation delay and power consumption), refer to device datasheet. + This parameter can be a value of @ref COMP_PowerMode */ + + uint32_t NonInvertingInput; /*!< Set comparator input plus (non-inverting input). + This parameter can be a value of @ref COMP_InputPlus */ + + uint32_t InvertingInput; /*!< Set comparator input minus (inverting input). + This parameter can be a value of @ref COMP_InputMinus */ + + uint32_t OutputPol; /*!< Set comparator output polarity. + This parameter can be a value of @ref COMP_OutputPolarity */ + + uint32_t LPTIMConnection; /*!< Set comparator output connection to LPTIM peripheral. + This parameter can be a value of @ref COMP_LPTIMConnection */ + + uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI). + This parameter can be a value of @ref COMP_EXTI_TriggerMode */ + }COMP_InitTypeDef; /** - * @} + * @brief HAL COMP state machine: HAL COMP states definition */ - -/** @defgroup COMP_state COMP state definition - * @{ - */ -/** - * @brief HAL State structures definition - */ +#define COMP_STATE_BITFIELD_LOCK ((uint32_t)0x10) typedef enum { - HAL_COMP_STATE_RESET = 0x00, /*!< COMP not yet initialized or disabled */ - HAL_COMP_STATE_READY = 0x01, /*!< COMP initialized and ready for use */ - HAL_COMP_STATE_READY_LOCKED = 0x11, /*!< COMP initialized but the configuration is locked */ - HAL_COMP_STATE_BUSY = 0x02, /*!< COMP is running */ - HAL_COMP_STATE_BUSY_LOCKED = 0x12 /*!< COMP is running and the configuration is locked */ + HAL_COMP_STATE_RESET = 0x00U, /*!< COMP not yet initialized */ + HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */ + HAL_COMP_STATE_READY = 0x01U, /*!< COMP initialized and ready for use */ + HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */ + HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */ + HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */ }HAL_COMP_StateTypeDef; -/** - * @} - */ -/** @defgroup COMP_handle COMP handler - * @{ - */ /** - * @brief COMP Handle Structure definition - */ + * @brief COMP Handle Structure definition + */ typedef struct { COMP_TypeDef *Instance; /*!< Register base address */ @@ -130,9 +117,6 @@ typedef struct __IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */ } COMP_HandleTypeDef; -/** - * @} - */ /** * @} */ @@ -142,108 +126,457 @@ typedef struct * @{ */ -/** @defgroup COMP_OutputPolarity COMP output polarity definitions +/** @defgroup COMP_WindowMode COMP Window Mode * @{ */ -#define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */ -#define COMP_OUTPUTPOL_INVERTED COMP_CSR_COMPxPOLARITY /*!< COMP output on GPIO is inverted */ -#define IS_COMP_OUTPUTPOL(POL) (((POL) == COMP_OUTPUTPOL_NONINVERTED) || \ - ((POL) == COMP_OUTPUTPOL_INVERTED)) -/** - * @} - */ - - -/** @defgroup COMP_InvertingInput COMP inverting input definitions - * @{ - */ - -/* Inverting Input specific to COMP1 */ -#define COMP_INVERTINGINPUT_VREFINT ((uint32_t)0x00000000) /*!< VREFINT connected to comparator1 inverting input */ -#define COMP_INVERTINGINPUT_IO1 ((uint32_t)0x00000010) /*!< I/O1 connected to comparator inverting input (PA0) for COMP1 and (PA2) for COMP2*/ -#define COMP_INVERTINGINPUT_DAC1 ((uint32_t)0x00000020) /*!< DAC1_OUT (PA4) connected to comparator inverting input */ -#define COMP_INVERTINGINPUT_IO2 ((uint32_t)0x00000030) /*!< I/O2 (PA5) connected to comparator inverting input */ - -/* Inverting Input specific to COMP2 */ -#define COMP_INVERTINGINPUT_1_4VREFINT ((uint32_t)0x00000040) /*!< 1/4 VREFINT connected to comparator inverting input */ -#define COMP_INVERTINGINPUT_1_2VREFINT ((uint32_t)0x00000050) /*!< 1/2 VREFINT connected to comparator inverting input */ -#define COMP_INVERTINGINPUT_3_4VREFINT ((uint32_t)0x00000060) /*!< 3/4 VREFINT connected to comparator inverting input */ -#define COMP_INVERTINGINPUT_IO3 ((uint32_t)0x00000070) /*!< I/O3 (PB3) for COMP2 connected to comparator inverting input */ - - -#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \ - ((INPUT) == COMP_INVERTINGINPUT_IO1) || \ - ((INPUT) == COMP_INVERTINGINPUT_DAC1) || \ - ((INPUT) == COMP_INVERTINGINPUT_IO2) || \ - ((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \ - ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \ - ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \ - ((INPUT) == COMP_INVERTINGINPUT_IO3)) - -/** - * @} - */ - - -/** @defgroup COMP_NonInvertingInput COMP non inverting input definitions - * @{ - */ - -#define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< I/O1 (PA3) connected to comparator non inverting input */ -#define COMP_NONINVERTINGINPUT_IO2 ((uint32_t)0x00000100) /*!< I/O2 (PB4) connected to comparator non inverting input */ -#define COMP_NONINVERTINGINPUT_IO3 ((uint32_t)0x00000200) /*!< I/O3 (PB5) connected to comparator non inverting input */ -#define COMP_NONINVERTINGINPUT_IO4 ((uint32_t)0x00000300) /*!< I/O1 (PB6) connected to comparator non inverting input */ -#define COMP_NONINVERTINGINPUT_IO5 ((uint32_t)0x00000400) /*!< I/O3 (PB7) connected to comparator non inverting input */ -#define COMP_NONINVERTINGINPUT_IO6 ((uint32_t)0x00000500) /*!< I/O3 (PA7) connected to comparator non inverting input */ -#define COMP_NONINVERTINGINPUT_IO7 ((uint32_t)0x00000600) /*!< Reserved */ -#define COMP_NONINVERTINGINPUT_IO8 ((uint32_t)0x00000700) /*!< Reserved */ - -#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_IO2) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_IO3) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_IO4) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_IO5) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_IO6)) -/** - * @} - */ - - -/** @defgroup COMP_Mode COMP mode definition - * @{ - */ -/* Please refer to the electrical characteristics in the device datasheet for - the power consumption values */ -#define COMP_MODE_HIGHSPEED COMP_CSR_COMP2SPEED /*!< High Speed */ -#define COMP_MODE_LOWSPEED ((uint32_t)0x00000000) /*!< Low Speed */ - -#define IS_COMP_MODE(SPEED) (((SPEED) == COMP_MODE_HIGHSPEED) || \ - ((SPEED) == COMP_MODE_LOWSPEED)) +#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000U) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */ +#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_COMP1WM) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */ /** * @} */ -/** @defgroup COMP_WindowMode COMP window mode definition +/** @defgroup COMP_PowerMode COMP power mode * @{ */ -#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disabled (Plus input of comparator 1 connected to PA1)*/ -#define COMP_WINDOWMODE_ENABLE COMP_CSR_COMP1WM /*!< Window mode enabled: Plus input of comparator 1 shorted with Plus input of comparator 2 */ -#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \ - ((WINDOWMODE) == COMP_WINDOWMODE_ENABLE)) - -#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP1) - +/* Note: For the characteritics of comparator power modes */ +/* (propagation delay and power consumption), */ +/* refer to device datasheet. */ +#define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_COMP2SPEED) /*!< COMP power mode to low power (indicated as "high speed" in reference manual) (only for COMP instance: COMP2) */ +#define COMP_POWERMODE_ULTRALOWPOWER ((uint32_t)0x00000000U) /*!< COMP power mode to ultra low power (indicated as "low speed" in reference manual) (only for COMP instance: COMP2) */ /** * @} */ +/** @defgroup COMP_InputPlus COMP input plus (non-inverting input) + * @{ + */ +#define COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA3 for COMP2) */ +#define COMP_INPUT_PLUS_IO2 (COMP_CSR_COMP2INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB4 for COMP2) (only for COMP instance: COMP2) */ +#define COMP_INPUT_PLUS_IO3 (COMP_CSR_COMP2INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA5 for COMP2) (only for COMP instance: COMP2) */ +#define COMP_INPUT_PLUS_IO4 (COMP_CSR_COMP2INPSEL_0 | COMP_CSR_COMP2INPSEL_1) /*!< Comparator input plus connected to IO4 (pin PB6 for COMP2) (only for COMP instance: COMP2) */ +#define COMP_INPUT_PLUS_IO5 (COMP_CSR_COMP2INPSEL_2) /*!< Comparator input plus connected to IO5 (pin PB7 for COMP2) (only for COMP instance: COMP2) */ +#if defined (STM32L011xx) || defined (STM32L021xx) +#define COMP_INPUT_PLUS_IO6 (COMP_CSR_COMP2INPSEL_2 | COMP_CSR_COMP2INPSEL_0) /*!< Comparator input plus connected to IO6 (pin PA7 for COMP2) (only for COMP instance: COMP2) (Available only on devices STM32L0 category 1) */ +#endif +/** + * @} + */ + +/** @defgroup COMP_InputMinus COMP input minus (inverting input) + * @{ + */ +#define COMP_INPUT_MINUS_1_4VREFINT (COMP_CSR_COMP2INNSEL_2 ) /*!< Comparator input minus connected to 1/4 VREFINT (only for COMP instance: COMP2) */ +#define COMP_INPUT_MINUS_1_2VREFINT (COMP_CSR_COMP2INNSEL_2 | COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to 1/2 VREFINT (only for COMP instance: COMP2) */ +#define COMP_INPUT_MINUS_3_4VREFINT (COMP_CSR_COMP2INNSEL_2 | COMP_CSR_COMP2INNSEL_1 ) /*!< Comparator input minus connected to 3/4 VREFINT (only for COMP instance: COMP2) */ +#define COMP_INPUT_MINUS_VREFINT ((uint32_t)0x00000000U) /*!< Comparator input minus connected to VrefInt */ +#define COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CSR_COMP2INNSEL_1 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */ +#define COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CSR_COMP2INNSEL_1 | COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */ +#define COMP_INPUT_MINUS_IO1 ( COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to IO1 (pin PA0 for COMP1, pin PA2 for COMP2) */ +#define COMP_INPUT_MINUS_IO2 (COMP_CSR_COMP2INNSEL_2 | COMP_CSR_COMP2INNSEL_1 | COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to IO2 (pin PB3 for COMP2) (only for COMP instance: COMP2) */ +/** + * @} + */ + + /** @defgroup COMP_LPTIMConnection COMP Low power timer connection definition * @{ */ -#define COMP_LPTIMCONNECTION_DISABLED ((uint32_t)0x00000000) /*!< COMPx signal is gated */ -#define COMP_LPTIMCONNECTION_IN1_ENABLED ((uint32_t)0x00000001) /*!< COMPx signal is connected to LPTIM input 1 */ -#define COMP_LPTIMCONNECTION_IN2_ENABLED ((uint32_t)0x00000002) /*!< COMPx signal is connected to LPTIM input 2 */ +#define COMP_LPTIMCONNECTION_DISABLED ((uint32_t)0x00000000U) /*!< COMPx signal is gated */ +#define COMP_LPTIMCONNECTION_IN1_ENABLED ((uint32_t)0x00000001U) /*!< COMPx signal is connected to LPTIM input 1 */ +#define COMP_LPTIMCONNECTION_IN2_ENABLED ((uint32_t)0x00000002U) /*!< COMPx signal is connected to LPTIM input 2 */ +/** + * @} + */ + +/** @defgroup COMP_OutputPolarity COMP output Polarity + * @{ + */ +#define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000U) /*!< COMP output on GPIO isn't inverted */ +#define COMP_OUTPUTPOL_INVERTED COMP_CSR_COMPxPOLARITY /*!< COMP output on GPIO is inverted */ +/** + * @} + */ + +/** @defgroup COMP_OutputLevel COMP Output Level + * @{ + */ +/* Note: Comparator output level values are fixed to "0" and "1", */ +/* corresponding COMP register bit is managed by HAL function to match */ +/* with these values (independently of bit position in register). */ + +/* When output polarity is not inverted, comparator output is low when + the input plus is at a lower voltage than the input minus */ +#define COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000U) +/* When output polarity is not inverted, comparator output is high when + the input plus is at a higher voltage than the input minus */ +#define COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001U) +/** + * @} + */ + +/** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI + * @{ + */ +#define COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000U) /*!< Comparator output triggering no External Interrupt Line */ +#define COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */ +#define COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */ +#define COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */ +#define COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */ +#define COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */ +#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup COMP_Exported_Macros COMP Exported Macros + * @{ + */ + +/** @defgroup COMP_Handle_Management COMP Handle Management + * @{ + */ + +/** @brief Reset COMP handle state. + * @param __HANDLE__ COMP handle + * @retval None + */ +#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) + +/** + * @brief Enable the specified comparator. + * @param __HANDLE__ COMP handle + * @retval None + */ +#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxEN) + +/** + * @brief Disable the specified comparator. + * @param __HANDLE__ COMP handle + * @retval None + */ +#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxEN) + +/** + * @brief Lock the specified comparator configuration. + * @note Using this macro induce HAL COMP handle state machine being no + * more in line with COMP instance state. + * To keep HAL COMP handle state machine updated, it is recommended + * to use function "HAL_COMP_Lock')". + * @param __HANDLE__ COMP handle + * @retval None + */ +#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxLOCK) + +/** + * @brief Check whether the specified comparator is locked. + * @param __HANDLE__ COMP handle + * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked + */ +#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxLOCK) == COMP_CSR_COMPxLOCK) + +/** + * @} + */ + +/** @defgroup COMP_Exti_Management COMP external interrupt line management + * @{ + */ + +/** + * @brief Enable the COMP1 EXTI line rising edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Disable the COMP1 EXTI line rising edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Enable the COMP1 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Disable the COMP1 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Enable the COMP1 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the COMP1 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Enable the COMP1 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Disable the COMP1 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Generate a software interrupt on the COMP1 EXTI line. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP1) + +/** + * @brief Enable the COMP1 EXTI line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Disable the COMP1 EXTI line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Check whether the COMP1 EXTI line flag is set. + * @retval RESET or SET + */ +#define __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Clear the COMP1 EXTI flag. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Enable the COMP2 EXTI line rising edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Disable the COMP2 EXTI line rising edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Enable the COMP2 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Disable the COMP2 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Enable the COMP2 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the COMP2 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Enable the COMP2 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Disable the COMP2 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Generate a software interrupt on the COMP2 EXTI line. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP2) + +/** + * @brief Enable the COMP2 EXTI line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Disable the COMP2 EXTI line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Check whether the COMP2 EXTI line flag is set. + * @retval RESET or SET + */ +#define __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Clear the COMP2 EXTI flag. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2) + +/** + * @} + */ + +/** + * @} + */ + + +/* Private types -------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup COMP_Private_Constants COMP Private Constants + * @{ + */ +/** @defgroup COMP_ExtiLine COMP EXTI Lines + * @{ + */ +#define COMP_EXTI_LINE_COMP1 (EXTI_IMR_IM21) /*!< EXTI line 21 connected to COMP1 output */ +#define COMP_EXTI_LINE_COMP2 (EXTI_IMR_IM22) /*!< EXTI line 22 connected to COMP2 output */ +/** + * @} + */ + +/** @defgroup COMP_ExtiLine COMP EXTI Lines + * @{ + */ +#define COMP_EXTI_IT ((uint32_t) 0x01U) /*!< EXTI line event with interruption */ +#define COMP_EXTI_EVENT ((uint32_t) 0x02U) /*!< EXTI line event only (without interruption) */ +#define COMP_EXTI_RISING ((uint32_t) 0x10U) /*!< EXTI line event on rising edge */ +#define COMP_EXTI_FALLING ((uint32_t) 0x20U) /*!< EXTI line event on falling edge */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup COMP_Private_Macros COMP Private Macros + * @{ + */ + +/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators + * @{ + */ +/** + * @brief Get the specified EXTI line for a comparator instance. + * @param __INSTANCE__ specifies the COMP instance. + * @retval value of @ref COMP_ExtiLine + */ +#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? \ + COMP_EXTI_LINE_COMP1 : COMP_EXTI_LINE_COMP2) +/** + * @} + */ + +/** @defgroup COMP_IS_COMP_Definitions COMP private macros to check input parameters + * @{ + */ +#define IS_COMP_WINDOWMODE(__WINDOWMODE__) (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \ + ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) ) + +#define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) || \ + ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER) ) + +#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP1) + +#if defined (STM32L011xx) || defined (STM32L021xx) +#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \ + (((__COMP_INSTANCE__) == COMP1) \ + ? ( \ + (__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1 \ + ) \ + : \ + ( \ + ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) \ + || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) \ + || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3) \ + || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO4) \ + || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO5) \ + || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO6) \ + ) \ + ) +#else +#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \ + (((__COMP_INSTANCE__) == COMP1) \ + ? ( \ + (__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1 \ + ) \ + : \ + ( \ + ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) \ + || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) \ + || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3) \ + || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO4) \ + || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO5) \ + ) \ + ) +#endif + +#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ + (((__COMP_INSTANCE__) == COMP1) \ + ? ( \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) \ + || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) \ + || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) \ + || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) \ + ) \ + : \ + ( \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) \ + || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) \ + || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) \ + || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) \ + || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) \ + || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) \ + || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) \ + || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) \ + ) \ + ) #define IS_COMP1_LPTIMCONNECTION(LPTIMCONNECTION) (((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_DISABLED) || \ ((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN1_ENABLED)) @@ -254,231 +587,26 @@ typedef struct #define IS_COMP2_LPTIMCONNECTION_RESTRICTED(LPTIMCONNECTION) (((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_DISABLED) || \ ((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN2_ENABLED)) -/** - * @} - */ -/** @defgroup COMP_OutputLevel COMP output level definition - * @{ - */ -/* When output polarity is not inverted, comparator output is low when - the non-inverting input is at a lower voltage than the inverting input*/ -#define COMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000) -/* When output polarity is not inverted, comparator output is high when - the non-inverting input is at a higher voltage than the inverting input */ -#define COMP_OUTPUTLEVEL_HIGH COMP_CSR_COMPxOUTVALUE -/** - * @} - */ +#define IS_COMP_OUTPUTPOL(POL) (((POL) == COMP_OUTPUTPOL_NONINVERTED) || \ + ((POL) == COMP_OUTPUTPOL_INVERTED)) -/* CSR register Mask */ -#define COMP_CSR_UPDATE_PARAMETERS_MASK ((uint32_t)0xC0008779) - -#define COMP_LOCK_DISABLE ((uint32_t)0x00000000) -#define COMP_LOCK_ENABLE COMP_CSR_COMPxLOCK +#define IS_COMP_TRIGGERMODE(__TRIGGERMODE__) (((__TRIGGERMODE__) == COMP_TRIGGERMODE_NONE) || \ + ((__TRIGGERMODE__) == COMP_TRIGGERMODE_IT_RISING) || \ + ((__TRIGGERMODE__) == COMP_TRIGGERMODE_IT_FALLING) || \ + ((__TRIGGERMODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \ + ((__TRIGGERMODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \ + ((__TRIGGERMODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \ + ((__TRIGGERMODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING) ) -#define COMP_STATE_BIT_LOCK ((uint32_t)0x10) -/** @defgroup COMP_TriggerMode COMP trigger mode definition - * @{ - */ -#define COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000) /*!< No External Interrupt trigger detection */ -#define COMP_TRIGGERMODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define COMP_TRIGGERMODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define COMP_TRIGGERMODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ - -#define COMP_TRIGGERMODE_EVENT_RISING ((uint32_t)0x00000010) /*!< Event Mode with Rising edge trigger detection */ -#define COMP_TRIGGERMODE_EVENT_FALLING ((uint32_t)0x00000020) /*!< Event Mode with Falling edge trigger detection */ -#define COMP_TRIGGERMODE_EVENT_RISING_FALLING ((uint32_t)0x00000030) /*!< Event Mode with Rising/Falling edge trigger detection */ +#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW) || \ + ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH)) /** * @} - */ - -/** @defgroup COMP_ExtiLineEvent COMP EXTI line definition - * @{ */ -#define COMP_EXTI_LINE_COMP2 (EXTI_IMR_IM22) /*!< External interrupt line 22 Connected to COMP2 */ -#define COMP_EXTI_LINE_COMP1 (EXTI_IMR_IM21) /*!< External interrupt line 21 Connected to COMP1 */ - - -/** - * @} - */ -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @brief Reset COMP handle state - * @param __HANDLE__: COMP handle. - * @retval None - */ - -/** @defgroup COMP_Exported_Macro COMP Exported Macros - * @{ - */ -/** - * @brief Reset the state machine associated to the handler - * @param __HANDLE__: COMP handle. - * @retval None. - */ - -#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) - -/** - * @brief Enables the specified comparator - * @param __HANDLE__: COMP handle. - * @retval None. - */ -#define __HAL_COMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CSR |= (COMP_CSR_COMPxEN)) - -/** - * @brief Disables the specified comparator - * @param __HANDLE__: COMP handle. - * @retval None. - */ -#define __HAL_COMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CSR &= ~(COMP_CSR_COMPxEN)) - -/** - * @brief Lock the specified comparator configuration - * @param __HANDLE__: COMP handle. - * @retval None. - */ -#define __HAL_COMP_LOCK(__HANDLE__) ((__HANDLE__)->Instance->CSR |= COMP_CSR_COMPxLOCK) - -/** @brief Checks whether the specified COMP flag is set or not. - * @param __HANDLE__: COMP handle. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg COMP_FLAG_LOCK: lock flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->CSR & (__FLAG__)) == (__FLAG__)) - -/** - * @brief Enable the Exti Line rising edge trigger. - */ -#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1) -#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2) - -/** - * @brief Disable the Exti Line rising edge trigger. - */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1) -#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2) - -/** - * @brief Enable the Exti Line falling edge trigger. - * @retval None. - */ -#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1) -#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2) - -/** - * @brief Disable the Exti Line falling edge trigger. - */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1) -#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2) - -/** - * @brief Enable the COMP1 EXTI line rising & falling edge trigger. - * @retval None. - */ -#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the COMP1 EXTI line rising & falling edge trigger. - * @retval None. - */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Enable the COMP2 EXTI line rising & falling edge trigger. - * @retval None. - */ -#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the COMP2 EXTI line rising & falling edge trigger. - * @retval None. - */ -#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Get the specified EXTI line for a comparator instance - * @param __INSTANCE__: specifies the COMP instance. - * @retval value of @ref COMP_ExtiLineEvent - */ -#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \ - COMP_EXTI_LINE_COMP2) - -/** - * @brief Enable the COMP Exti Line. - * @retval None. - */ - -#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1) -#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2) - -/** - * @brief Disable the COMP Exti Line. - * @retval None. - */ - -#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1) -#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2) - -/** - * @brief Generate a software interrupt on the COMP EXTI line. - * @retval None - */ -#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP1) -#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP2) - - -/** - * @brief Enable the COMP EXTI Line in event mode - * @retval None - */ -#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1) -#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2) - -/** - * @brief Disable the COMP EXTI Line in event mode. - * @retval None - */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1) -#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2) -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @retval The state of __FLAG__ (SET or RESET). - */ - -#define __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP1) -#define __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP2) - -/** - * @brief Clear the COMP Exti flags. - * @retval None. - */ -#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP1) -#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2) - - /** * @} */ @@ -487,73 +615,54 @@ typedef struct #include "stm32l0xx_hal_comp_ex.h" /* Exported functions --------------------------------------------------------*/ -/** @defgroup COMP_Exported_Functions COMP Exported Functions +/** @addtogroup COMP_Exported_Functions * @{ */ -/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions +/** @addtogroup COMP_Exported_Functions_Group1 * @{ */ -/* Initialization/de-initialization functions **********************************/ +/* Initialization and de-initialization functions **********************************/ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp); HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp); -void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp); -void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp); +void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp); +void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp); /** * @} */ -/** @defgroup COMP_Exported_Functions_Group2 I/O operation functions +/* IO operation functions *****************************************************/ +/** @addtogroup COMP_Exported_Functions_Group2 * @{ */ -/* I/O operation functions *****************************************************/ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp); HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp); -HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp); -HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp); -void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); +void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); /** * @} */ -/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ /* Peripheral Control functions ************************************************/ +/** @addtogroup COMP_Exported_Functions_Group3 + * @{ + */ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp); -uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp); - -/* Callback in Interrupt mode */ -void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp); +/* Callback in interrupt mode */ +void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); /** * @} */ -/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions - * @{ - */ /* Peripheral State functions **************************************************/ -HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); - -/** - * @} - */ - - -/** - * @} - */ - -/* Define the private group ***********************************/ -/**************************************************************/ -/** @defgroup COMP_Private COMP Private +/** @addtogroup COMP_Exported_Functions_Group4 * @{ */ +HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); /** * @} */ -/**************************************************************/ /** * @} @@ -561,7 +670,11 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); /** * @} - */ + */ + +/** + * @} + */ #ifdef __cplusplus } @@ -570,4 +683,3 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); #endif /* __STM32L0xx_HAL_COMP_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp_ex.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp_ex.c index 8c5b1d154e..98fc39e07b 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp_ex.c @@ -2,11 +2,12 @@ ****************************************************************************** * @file stm32l0xx_hal_comp_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Extended COMP HAL module driver. - * @brief This file provides firmware functions to manage the VREFINT - * which can act as input to the comparator. + * @brief This file provides firmware functions to manage voltage reference + * VrefInt that must be specifically controled for comparator + * instance COMP2. @verbatim ============================================================================== ##### COMP peripheral Extended features ##### @@ -75,28 +76,29 @@ */ /** - * @brief Enables the Buffer Vrefint for the COMP. - * @note This is functional only if the LOCK bit is not set - + * @brief Enable Vrefint and path to comparator, used by comparator + * instance COMP2 input based on VrefInt or subdivision of VrefInt. + * @note The equivalent of this function is managed automatically when + * using function "HAL_COMP_Init()". + * @note VrefInt requires a startup time + * (refer to device datasheet, parameter "TVREFINT"). * @retval None */ void HAL_COMPEx_EnableVREFINT(void) { - /* Enable the Buffer for the COMP by setting EN_VREFINT bit and the ENBUFLP_VREFINT_COMP in the CFGR3 register */ - - SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP | SYSCFG_CFGR3_EN_VREFINT); + /* Enable the Buffer for the COMP by setting ENBUFLP_VREFINT_COMP bit in the CFGR3 register */ + SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP); } /** - * @brief Disables the Buffer Vrefint for the COMP. - * @note This is functional only if the LOCK bit is not set + * @brief Disable Vrefint and path to comparator, used by comparator + * instance COMP2 input based on VrefInt or subdivision of VrefInt. * @retval None */ void HAL_COMPEx_DisableVREFINT(void) { - /* Disable the Vrefint by resetting ENBUFLP_BGAP_COMP bit and the EN_VREFINT bit in the CFGR3 register */ - - SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP | SYSCFG_CFGR3_EN_VREFINT)); + /* Disable the Vrefint by resetting ENBUFLP_VREFINT_COMP bit in the CFGR3 register */ + SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP)); } /** diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp_ex.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp_ex.h index 2b7486d7ef..4aef262655 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_comp_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of COMP HAL Extended module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cortex.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cortex.c index 82c4fc57f0..04cdf09992 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cortex.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cortex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_cortex.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: @@ -47,7 +47,7 @@ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). (++) Enables the SysTick Interrupt. (++) Starts the SysTick Counter. - + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the function HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() function is defined @@ -356,7 +356,7 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); /* Set the base adsress and set the 4 LSB to 0 */ - MPU->RBAR = (MPU_Init->BaseAddress) & 0xfffffff0; + MPU->RBAR = (MPU_Init->BaseAddress) & 0xfffffff0U; /* Fill the field RASR */ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | @@ -370,8 +370,8 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) } else { - MPU->RBAR = 0x00; - MPU->RASR = 0x00; + MPU->RBAR = 0x00U; + MPU->RASR = 0x00U; } } #endif /* __MPU_PRESENT */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cortex.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cortex.h index 3fde982daf..69f00d4f1c 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cortex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_cortex.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention @@ -106,15 +106,15 @@ typedef struct */ -#define IS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__) ((__PRIORITY__) < 0x4) +#define IS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__) ((__PRIORITY__) < 0x4U) -#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x0) /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick Clock Source * @{ */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) #define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \ ((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8)) /** @@ -125,10 +125,10 @@ typedef struct /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control * @{ */ -#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) -#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) -#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) -#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) +#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) +#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U) +#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U) +#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U) /** * @} */ @@ -136,8 +136,8 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable * @{ */ -#define MPU_REGION_ENABLE ((uint8_t)0x01) -#define MPU_REGION_DISABLE ((uint8_t)0x00) +#define MPU_REGION_ENABLE ((uint8_t)0x01U) +#define MPU_REGION_DISABLE ((uint8_t)0x00U) /** * @} */ @@ -145,8 +145,8 @@ typedef struct /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access * @{ */ -#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) -#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U) /** * @} */ @@ -154,8 +154,8 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable * @{ */ -#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U) /** * @} */ @@ -163,8 +163,8 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable * @{ */ -#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U) /** * @} */ @@ -172,8 +172,8 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable * @{ */ -#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U) /** * @} */ @@ -181,34 +181,34 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size * @{ */ -#define MPU_REGION_SIZE_32B ((uint8_t)0x04) -#define MPU_REGION_SIZE_64B ((uint8_t)0x05) -#define MPU_REGION_SIZE_128B ((uint8_t)0x06) -#define MPU_REGION_SIZE_256B ((uint8_t)0x07) -#define MPU_REGION_SIZE_512B ((uint8_t)0x08) -#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) -#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) -#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) -#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) -#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) -#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) -#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) -#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) -#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) -#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) -#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) -#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) -#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) -#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) -#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) -#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) -#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) -#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) -#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) -#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) -#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) -#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) -#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +#define MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) /** * @} */ @@ -216,12 +216,12 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ -#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) -#define MPU_REGION_PRIV_RW ((uint8_t)0x01) -#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) -#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) -#define MPU_REGION_PRIV_RO ((uint8_t)0x05) -#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01U) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05U) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U) /** * @} */ @@ -229,14 +229,14 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number * @{ */ -#define MPU_REGION_NUMBER0 ((uint8_t)0x00) -#define MPU_REGION_NUMBER1 ((uint8_t)0x01) -#define MPU_REGION_NUMBER2 ((uint8_t)0x02) -#define MPU_REGION_NUMBER3 ((uint8_t)0x03) -#define MPU_REGION_NUMBER4 ((uint8_t)0x04) -#define MPU_REGION_NUMBER5 ((uint8_t)0x05) -#define MPU_REGION_NUMBER6 ((uint8_t)0x06) -#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +#define MPU_REGION_NUMBER0 ((uint8_t)0x00U) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01U) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02U) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03U) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04U) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05U) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06U) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07U) /** * @} */ @@ -391,7 +391,7 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); ((SIZE) == MPU_REGION_SIZE_2GB) || \ ((SIZE) == MPU_REGION_SIZE_4GB)) -#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) #endif /* __MPU_PRESENT */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc.c index f95ef65d3a..b5b778e00e 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_crc.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief CRC HAL module driver. * * This file provides firmware functions to manage the following @@ -315,8 +315,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) */ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { - uint32_t index = 0; /* CRC input data buffer index */ - uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ + uint32_t index = 0U; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ /* Process locked */ __HAL_LOCK(hcrc); @@ -328,7 +328,7 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ { case CRC_INPUTDATA_FORMAT_WORDS: /* Enter Data to the CRC calculator */ - for(index = 0; index < BufferLength; index++) + for(index = 0U; index < BufferLength; index++) { hcrc->Instance->DR = pBuffer[index]; } @@ -374,8 +374,8 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ */ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { - uint32_t index = 0; /* CRC input data buffer index */ - uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ + uint32_t index = 0U; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ /* Process locked */ __HAL_LOCK(hcrc); @@ -391,7 +391,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t { case CRC_INPUTDATA_FORMAT_WORDS: /* Enter 32-bit input data to the CRC calculator */ - for(index = 0; index < BufferLength; index++) + for(index = 0U; index < BufferLength; index++) { hcrc->Instance->DR = pBuffer[index]; } @@ -472,30 +472,30 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) { - uint32_t i = 0; /* input data buffer index */ + uint32_t i = 0U; /* input data buffer index */ /* Processing time optimization: 4 bytes are entered in a row with a single word write, * last bytes must be carefully fed to the CRC calculator to ensure a correct type * handling by the IP */ - for(i = 0; i < (BufferLength/4); i++) + for(i = 0U; i < (BufferLength/4U); i++) { - hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24) | ((uint32_t)pBuffer[4*i+1]<<16) | ((uint32_t)pBuffer[4*i+2]<<8) | (uint32_t)pBuffer[4*i+3]; + hcrc->Instance->DR = ((uint32_t)pBuffer[4U*i]<<24U) | ((uint32_t)pBuffer[4U*i+1U]<<16U) | ((uint32_t)pBuffer[4U*i+2U]<<8U) | (uint32_t)pBuffer[4U*i+3U]; } /* last bytes specific handling */ - if ((BufferLength%4) != 0) + if ((BufferLength%4U) != 0U) { - if (BufferLength%4 == 1) + if (BufferLength%4U == 1U) { - *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i]; + *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4U*i]; } - if (BufferLength%4 == 2) + if (BufferLength%4U == 2U) { - *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1]; + *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4U*i]<<8U) | (uint32_t)pBuffer[4U*i+1U]; } - if (BufferLength%4 == 3) + if (BufferLength%4U == 3U) { - *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1]; - *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; + *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4U*i]<<8U) | (uint32_t)pBuffer[4U*i+1U]; + *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4U*i+2U]; } } @@ -513,18 +513,18 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) { - uint32_t i = 0; /* input data buffer index */ + uint32_t i = 0U; /* input data buffer index */ /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * a correct type handling by the IP */ - for(i = 0; i < (BufferLength/2); i++) + for(i = 0U; i < (BufferLength/2U); i++) { - hcrc->Instance->DR = ((uint32_t)pBuffer[2*i]<<16) | (uint32_t)pBuffer[2*i+1]; + hcrc->Instance->DR = ((uint32_t)pBuffer[2U*i]<<16U) | (uint32_t)pBuffer[2U*i+1U]; } - if ((BufferLength%2) != 0) + if ((BufferLength%2U) != 0U) { - *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i]; + *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2U*i]; } /* Return the CRC computed value */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc.h index 2d9d66c7a1..61a817c371 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_crc.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention @@ -64,11 +64,11 @@ */ typedef enum { - HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */ - HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */ - HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */ - HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */ - HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */ + HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */ + HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */ + HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */ + HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */ + HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */ }HAL_CRC_StateTypeDef; @@ -151,7 +151,7 @@ typedef struct /** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial * @{ */ -#define DEFAULT_CRC32_POLY 0x04C11DB7 +#define DEFAULT_CRC32_POLY 0x04C11DB7U /** * @} @@ -160,7 +160,7 @@ typedef struct /** @defgroup CRC_Default_InitValue Default CRC computation initialization value * @{ */ -#define DEFAULT_CRC_INITVALUE 0xFFFFFFFF +#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /** * @} @@ -169,8 +169,8 @@ typedef struct /** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used * @{ */ -#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00) -#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01) +#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) +#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /** * @} @@ -179,8 +179,8 @@ typedef struct /** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used * @{ */ -#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00) -#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01) +#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) +#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /** @@ -190,7 +190,7 @@ typedef struct /** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP * @{ */ -#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000) +#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000U) #define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0) #define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1) #define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE) @@ -201,10 +201,10 @@ typedef struct /** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions * @{ */ -#define HAL_CRC_LENGTH_32B 32 -#define HAL_CRC_LENGTH_16B 16 -#define HAL_CRC_LENGTH_8B 8 -#define HAL_CRC_LENGTH_7B 7 +#define HAL_CRC_LENGTH_32B 32U +#define HAL_CRC_LENGTH_16B 16U +#define HAL_CRC_LENGTH_8B 8U +#define HAL_CRC_LENGTH_7B 7U /** * @} @@ -217,10 +217,10 @@ typedef struct * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for * the CRC APIs to provide a correct result */ -#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000) -#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001) -#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002) -#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003) +#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000U) +#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001U) +#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002U) +#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003U) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc_ex.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc_ex.c index 1dce0e5d02..91e899f15f 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_crc_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Extended CRC HAL module driver. * * This file provides firmware functions to manage the following @@ -108,7 +108,7 @@ This subsection provides function allowing to: */ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) { - uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */ + uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); @@ -120,7 +120,7 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol * Look for MSB position: msb will contain the degree of * the second to the largest polynomial member. E.g., for * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ - while (((Pol & ((uint32_t)(0x1) << msb)) == 0) && (msb-- > 0)); + while (((Pol & ((uint32_t)(0x1U) << msb)) == 0U) && (msb-- > 0U)); switch (PolyLength) { diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc_ex.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc_ex.h index bd4f7dd3d4..e8a203d177 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_crc_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of CRC HAL extension module. ****************************************************************************** * @attention @@ -64,7 +64,7 @@ /** @defgroup CRCEx_Input_Data_Inversion CRC Extended input data inversion modes * @{ */ -#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000) +#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000U) #define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0) #define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1) #define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN) @@ -76,7 +76,7 @@ /** @defgroup CRCEx_Output_Data_Inversion CRC Extended output data inversion modes * @{ */ -#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000) +#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000U) #define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp.c index bb9935b8b8..46c5516627 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_cryp.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief CRYP HAL module driver. * * This file provides firmware functions to manage the following @@ -97,7 +97,7 @@ ****************************************************************************** */ -#if defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) +#if defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal.h" @@ -208,8 +208,8 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); /* Reset CrypInCount and CrypOutCount */ - hcryp->CrypInCount = 0; - hcryp->CrypOutCount = 0; + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; @@ -252,8 +252,8 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) hcryp->Phase = HAL_CRYP_PHASE_READY; /* Reset CrypInCount and CrypOutCount */ - hcryp->CrypInCount = 0; - hcryp->CrypOutCount = 0; + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; /* Disable the CRYP Peripheral Clock */ __HAL_CRYP_DISABLE(hcryp); @@ -341,7 +341,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP __HAL_LOCK(hcryp); /* Check that data aligned on u32 and Size multiple of 16*/ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U)) { /* Process Locked */ __HAL_UNLOCK(hcryp); @@ -417,7 +417,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP __HAL_LOCK(hcryp); /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U)) { /* Process Locked */ __HAL_UNLOCK(hcryp); @@ -496,7 +496,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP __HAL_LOCK(hcryp); /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U)) { /* Process Locked */ __HAL_UNLOCK(hcryp); @@ -575,7 +575,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC __HAL_LOCK(hcryp); /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U)) { /* Process Locked */ __HAL_UNLOCK(hcryp); @@ -651,7 +651,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC __HAL_LOCK(hcryp); /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U)) { /* Process Locked */ __HAL_UNLOCK(hcryp); @@ -730,7 +730,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC __HAL_LOCK(hcryp); /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U)) { /* Process Locked */ __HAL_UNLOCK(hcryp); @@ -791,10 +791,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) { - uint32_t inputaddr = 0; + uint32_t inputaddr = 0U; /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U)) { /* Process Locked */ __HAL_UNLOCK(hcryp); @@ -844,14 +844,14 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; + hcryp->pCrypInBuffPtr += 16U; + hcryp->CrypInCount -= 16U; /* Return function status */ return HAL_OK; @@ -877,10 +877,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) { - uint32_t inputaddr = 0; + uint32_t inputaddr = 0U; /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U)) { /* Process Locked */ __HAL_UNLOCK(hcryp); @@ -933,14 +933,14 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; + hcryp->pCrypInBuffPtr += 16U; + hcryp->CrypInCount -= 16U; /* Return function status */ return HAL_OK; @@ -966,10 +966,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) { - uint32_t inputaddr = 0; + uint32_t inputaddr = 0U; /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U)) { /* Process Locked */ __HAL_UNLOCK(hcryp); @@ -1022,14 +1022,14 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; + hcryp->pCrypInBuffPtr += 16U; + hcryp->CrypInCount -= 16U; /* Return function status */ return HAL_OK; @@ -1055,10 +1055,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) { - uint32_t inputaddr = 0; + uint32_t inputaddr = 0U; /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U)) { /* Process Locked */ __HAL_UNLOCK(hcryp); @@ -1108,14 +1108,14 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; + hcryp->pCrypInBuffPtr += 16U; + hcryp->CrypInCount -= 16U; /* Return function status */ return HAL_OK; @@ -1141,10 +1141,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) { - uint32_t inputaddr = 0; + uint32_t inputaddr = 0U; /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U)) { /* Process Locked */ __HAL_UNLOCK(hcryp); @@ -1197,14 +1197,14 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; + hcryp->pCrypInBuffPtr += 16U; + hcryp->CrypInCount -= 16U; /* Return function status */ return HAL_OK; @@ -1230,10 +1230,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) { - uint32_t inputaddr = 0; + uint32_t inputaddr = 0U; /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U)) { /* Process Locked */ __HAL_UNLOCK(hcryp); @@ -1286,14 +1286,14 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; + hcryp->pCrypInBuffPtr += 16U; + hcryp->CrypInCount -= 16U; /* Return function status */ return HAL_OK; @@ -1319,10 +1319,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) { - uint32_t inputaddr = 0, outputaddr = 0; + uint32_t inputaddr = 0U, outputaddr = 0U; /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U)) { /* Process Locked */ __HAL_UNLOCK(hcryp); @@ -1384,10 +1384,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) { - uint32_t inputaddr = 0, outputaddr = 0; + uint32_t inputaddr = 0U, outputaddr = 0U; /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U)) { /* Process Locked */ __HAL_UNLOCK(hcryp); @@ -1452,10 +1452,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) { - uint32_t inputaddr = 0, outputaddr = 0; + uint32_t inputaddr = 0U, outputaddr = 0U; /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U)) { /* Process Locked */ __HAL_UNLOCK(hcryp); @@ -1521,10 +1521,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) { - uint32_t inputaddr = 0, outputaddr = 0; + uint32_t inputaddr = 0U, outputaddr = 0U; /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U)) { /* Process Locked */ __HAL_UNLOCK(hcryp); @@ -1590,10 +1590,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) { - uint32_t inputaddr = 0, outputaddr = 0; + uint32_t inputaddr = 0U, outputaddr = 0U; /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U)) { /* Process Locked */ __HAL_UNLOCK(hcryp); @@ -1662,10 +1662,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) { - uint32_t inputaddr = 0, outputaddr = 0; + uint32_t inputaddr = 0U, outputaddr = 0U; /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U)) { /* Process Locked */ __HAL_UNLOCK(hcryp); @@ -1903,25 +1903,25 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) */ static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp) { - uint32_t inputaddr = 0, outputaddr = 0; + uint32_t inputaddr = 0U, outputaddr = 0U; /* Get the last Output data adress */ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; /* Read the Output block from the Output Register */ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; + hcryp->pCrypOutBuffPtr += 16U; + hcryp->CrypOutCount -= 16U; /* Check if all input text is encrypted or decrypted */ - if(hcryp->CrypOutCount == 0) + if(hcryp->CrypOutCount == 0U) { /* Disable Computation Complete Interrupt */ __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CC); @@ -1943,14 +1943,14 @@ static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp) /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; + hcryp->pCrypInBuffPtr += 16U; + hcryp->CrypInCount -= 16U; } return HAL_OK; } @@ -2026,11 +2026,11 @@ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key) uint32_t keyaddr = (uint32_t)Key; hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr)); } @@ -2052,11 +2052,11 @@ static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector) uint32_t ivaddr = (uint32_t)InitVector; hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr)); } @@ -2072,23 +2072,23 @@ static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector) */ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; - uint32_t index = 0; + uint32_t index = 0U; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; - for(index=0; (index < Ilength); index += 16) + for(index=0U; (index < Ilength); index += 16U) { /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; /* Get timeout */ tickstart = HAL_GetTick(); @@ -2098,7 +2098,7 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Change state */ hcryp->State = HAL_CRYP_STATE_TIMEOUT; @@ -2115,13 +2115,13 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In /* Read the Output block from the Data Output Register */ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; } /* Return function status */ return HAL_OK; diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp.h index 1165dd0d10..280b6a248c 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_cryp.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of CRYP HAL module. ****************************************************************************** * @attention @@ -82,11 +82,11 @@ typedef struct */ typedef enum { - HAL_CRYP_STATE_RESET = 0x00, /*!< CRYP not yet initialized or disabled */ - HAL_CRYP_STATE_READY = 0x01, /*!< CRYP initialized and ready for use */ - HAL_CRYP_STATE_BUSY = 0x02, /*!< CRYP internal processing is ongoing */ - HAL_CRYP_STATE_TIMEOUT = 0x03, /*!< CRYP timeout state */ - HAL_CRYP_STATE_ERROR = 0x04 /*!< CRYP error state */ + HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */ + HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */ + HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP internal processing is ongoing */ + HAL_CRYP_STATE_TIMEOUT = 0x03U, /*!< CRYP timeout state */ + HAL_CRYP_STATE_ERROR = 0x04U /*!< CRYP error state */ }HAL_CRYP_STATETypeDef; @@ -95,8 +95,8 @@ typedef enum */ typedef enum { - HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */ - HAL_CRYP_PHASE_PROCESS = 0x02, /*!< CRYP peripheral is in processing phase */ + HAL_CRYP_PHASE_READY = 0x01U, /*!< CRYP peripheral is ready for initialization. */ + HAL_CRYP_PHASE_PROCESS = 0x02U, /*!< CRYP peripheral is in processing phase */ }HAL_PhaseTypeDef; /** @@ -143,7 +143,7 @@ typedef struct /** @defgroup CRYP_Data_Type CRYP Data Type * @{ */ -#define CRYP_DATATYPE_32B ((uint32_t)0x00000000) +#define CRYP_DATATYPE_32B ((uint32_t)0x00000000U) #define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 #define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 #define CRYP_DATATYPE_1B AES_CR_DATATYPE @@ -161,7 +161,7 @@ typedef struct */ #define CRYP_CR_ALGOMODE_DIRECTION (uint32_t)(AES_CR_MODE|AES_CR_CHMOD) -#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT ((uint32_t)0x00000000) +#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT ((uint32_t)0x00000000U) #define CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT (AES_CR_MODE) #define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT (AES_CR_CHMOD_0) #define CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT ((uint32_t)(AES_CR_CHMOD_0|AES_CR_MODE)) diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp_ex.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp_ex.c index f2313b0619..88872c064a 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_cryp_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief CRYPEx HAL module driver. * * This file provides firmware functions to manage the following @@ -40,7 +40,7 @@ ****************************************************************************** */ -#if defined (STM32L021xx) ||defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) +#if defined (STM32L021xx) ||defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal.h" diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp_ex.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp_ex.h index a93ca3219f..959eabf100 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_cryp_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of CRYPEx HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac.c index f8313a67d4..375384a140 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_dac.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: @@ -481,7 +481,7 @@ __weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) /* Function content is located into file stm32l0xx_hal_dac_ex.c */ /* Return function status */ - return 0; + return 0U; } /** @@ -596,7 +596,7 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) { - uint32_t tmpreg1 = 0, tmpreg2 = 0; + uint32_t tmpreg1 = 0U, tmpreg2 = 0U; /* Check the DAC parameters */ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac.h index 8924dc2062..42ab17c5c4 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_dac.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention @@ -67,11 +67,11 @@ */ typedef enum { - HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */ - HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */ - HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */ - HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */ - HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */ + HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ + HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ + HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ + HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ + HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ }HAL_DAC_StateTypeDef; @@ -122,12 +122,12 @@ typedef struct /** @defgroup DAC_Error_Code DAC Error Code * @{ */ -#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */ +#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */ #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) -#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */ #endif -#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */ +#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */ /** * @} */ @@ -135,7 +135,7 @@ typedef struct /** @defgroup DAC_trigger_selection DAC trigger selection * @{ */ -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ +#define DAC_TRIGGER_NONE ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_TRIGGER_T6_TRGO ((uint32_t) DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T21_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM21 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ @@ -173,7 +173,7 @@ typedef struct /** @defgroup DAC_output_buffer DAC output buffer * @{ */ -#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000) +#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000U) #define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1) #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ @@ -185,9 +185,9 @@ typedef struct /** @defgroup DAC_Channel_selection DAC Channel selection * @{ */ -#define DAC_CHANNEL_1 ((uint32_t)0x00000000) +#define DAC_CHANNEL_1 ((uint32_t)0x00000000U) #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) -#define DAC_CHANNEL_2 ((uint32_t)0x00000010) +#define DAC_CHANNEL_2 ((uint32_t)0x00000010U) #endif #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) @@ -203,9 +203,9 @@ typedef struct /** @defgroup DAC_data_alignement DAC data alignement * @{ */ -#define DAC_ALIGN_12B_R ((uint32_t)0x00000000) -#define DAC_ALIGN_12B_L ((uint32_t)0x00000004) -#define DAC_ALIGN_8B_R ((uint32_t)0x00000008) +#define DAC_ALIGN_12B_R ((uint32_t)0x00000000U) +#define DAC_ALIGN_12B_L ((uint32_t)0x00000004U) +#define DAC_ALIGN_8B_R ((uint32_t)0x00000008U) #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ ((ALIGN) == DAC_ALIGN_12B_L) || \ @@ -217,7 +217,7 @@ typedef struct /** @defgroup DAC_data DAC data * @{ */ -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) /** * @} */ @@ -332,19 +332,19 @@ CLEAR_BIT((__HANDLE__)->Instance->CR, __INTERRUPT__) * @param __ALIGNEMENT__: specifies the DAC alignement * @retval None */ -#define DAC_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__)) +#define DAC_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008U) + (__ALIGNEMENT__)) /** @brief Set DHR12R2 alignment * @param __ALIGNEMENT__: specifies the DAC alignement * @retval None */ -#define DAC_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__)) +#define DAC_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014U) + (__ALIGNEMENT__)) /** @brief Set DHR12RD alignment * @param __ALIGNEMENT__: specifies the DAC alignement * @retval None */ -#define DAC_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__)) +#define DAC_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020U) + (__ALIGNEMENT__)) /** @brief Enable the DAC interrupt * @param __HANDLE__: specifies the DAC handle diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac_ex.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac_ex.c index e9772fe5f4..b1f4e4cc8b 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Extended DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of DAC extension peripheral: @@ -110,11 +110,11 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); */ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) { - uint32_t tmp = 0; + uint32_t tmp = 0U; tmp |= hdac->Instance->DOR1; - tmp |= hdac->Instance->DOR2 << 16; + tmp |= hdac->Instance->DOR2 << 16U; /* Returns the DAC channel data output register value */ return tmp; @@ -238,7 +238,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t */ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) { - uint32_t data = 0, tmp = 0; + uint32_t data = 0U, tmp = 0U; /* Check the parameters */ assert_param(IS_DAC_ALIGN(Alignment)); @@ -248,11 +248,11 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align /* Calculate and set dual DAC data holding register value */ if (Alignment == DAC_ALIGN_8B_R) { - data = ((uint32_t)Data2 << 8) | Data1; + data = ((uint32_t)Data2 << 8U) | Data1; } else { - data = ((uint32_t)Data2 << 16) | Data1; + data = ((uint32_t)Data2 << 16U) | Data1; } tmp = (uint32_t)hdac->Instance; @@ -342,7 +342,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) { - uint32_t tmp1 = 0, tmp2 = 0; + uint32_t tmp1 = 0U, tmp2 = 0U; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -408,7 +408,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) */ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -658,7 +658,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { - __IO uint32_t tmp = 0; + __IO uint32_t tmp = 0U; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -694,7 +694,7 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) { - uint32_t tmp1 = 0, tmp2 = 0; + uint32_t tmp1 = 0U, tmp2 = 0U; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -745,7 +745,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) */ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -910,7 +910,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { - __IO uint32_t tmp = 0; + __IO uint32_t tmp = 0U; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac_ex.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac_ex.h index 928b814a2e..0772beb06b 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_dac_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention @@ -67,7 +67,7 @@ /** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude * @{ */ -#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ #define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ @@ -79,7 +79,7 @@ #define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000U) /*!< Select max triangle amplitude of 1 */ #define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ #define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */ #define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_def.h index 9868461a12..303a39a12b 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_def.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_def.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** @@ -56,10 +56,10 @@ */ typedef enum { - HAL_OK = 0x00, - HAL_ERROR = 0x01, - HAL_BUSY = 0x02, - HAL_TIMEOUT = 0x03 + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U } HAL_StatusTypeDef; /** @@ -67,15 +67,15 @@ typedef enum */ typedef enum { - HAL_UNLOCKED = 0x00, - HAL_LOCKED = 0x01 + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U } HAL_LockTypeDef; /* Exported macro ------------------------------------------------------------*/ #define UNUSED(x) ((void)(x)) -#define HAL_MAX_DELAY 0xFFFFFFFF +#define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) @@ -101,7 +101,7 @@ typedef enum * HAL_PPP_MspInit() which will reconfigure the low level hardware. * @retval None */ -#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) #if (USE_RTOS == 1) diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dma.c index 3a15edd043..843ae4b677 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dma.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dma.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_dma.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief DMA HAL module driver. * * This file provides firmware functions to manage the following @@ -104,7 +104,7 @@ * * @{ */ -#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */ +#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000U) /* 1s */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); @@ -140,7 +140,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { - uint32_t tmp = 0; + uint32_t tmp = 0U; /* Check the DMA peripheral state */ if(hdma == NULL) @@ -200,7 +200,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S; /* Configure request selection for DMA1 Channel2 */ - DMA1_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << 4); + DMA1_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << 4U); } else if (hdma->Instance == DMA1_Channel3) { @@ -208,7 +208,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S; /* Configure request selection for DMA1 Channel3 */ - DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 8); + DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 8U); } else if (hdma->Instance == DMA1_Channel4) { @@ -216,7 +216,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S; /* Configure request selection for DMA1 Channel4 */ - DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 12); + DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 12U); } else if (hdma->Instance == DMA1_Channel5) { @@ -224,7 +224,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S; /* Configure request selection for DMA1 Channel5 */ - DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 16); + DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 16U); } #if !defined (STM32L011xx) && !defined (STM32L021xx) else if (hdma->Instance == DMA1_Channel6) @@ -233,7 +233,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S; /* Configure request selection for DMA1 Channel6 */ - DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 20); + DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 20U); } else if (hdma->Instance == DMA1_Channel7) { @@ -241,7 +241,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S; /* Configure request selection for DMA1 Channel7 */ - DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 24); + DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 24U); } #endif /* Initialize the DMA state*/ @@ -274,16 +274,16 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) __HAL_DMA_DISABLE(hdma); /* Reset DMA Channel control register */ - hdma->Instance->CCR = 0; + hdma->Instance->CCR = 0U; /* Reset DMA Channel Number of Data to Transfer register */ - hdma->Instance->CNDTR = 0; + hdma->Instance->CNDTR = 0U; /* Reset DMA Channel peripheral address register */ - hdma->Instance->CPAR = 0; + hdma->Instance->CPAR = 0U; /* Reset DMA Channel memory address register */ - hdma->Instance->CMAR = 0; + hdma->Instance->CMAR = 0U; /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); @@ -445,7 +445,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Disable the channel */ __HAL_DMA_DISABLE(hdma); @@ -454,7 +454,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) tickstart = HAL_GetTick(); /* Check if the DMA Channel is effectively disabled */ - while((hdma->Instance->CCR & DMA_CCR_EN) != 0) + while((hdma->Instance->CCR & DMA_CCR_EN) != 0U) { /* Check for the Timeout */ if( (HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) @@ -491,7 +491,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) { uint32_t temp; - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Get the level transfer complete flag */ if(CompleteLevel == HAL_DMA_FULL_TRANSFER) @@ -529,7 +529,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); @@ -614,7 +614,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); @@ -638,7 +638,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) { - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { /* Disable the transfer complete interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dma.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dma.h index a1c6a78346..d2890943cf 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dma.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dma.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_dma.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention @@ -101,8 +101,8 @@ typedef struct */ typedef enum { - DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */ - DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */ + DMA_MODE = 0U, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */ + DMA_PRIORITY = 1U, /*!< Control related priority level Parameter in DMA_InitTypeDef */ } DMA_ControlTypeDef; @@ -111,12 +111,12 @@ typedef enum */ typedef enum { - HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */ - HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ - HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ - HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ - HAL_DMA_STATE_READY_HALF = 0x05, /*!< DMA Half process success */ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA process success and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ + HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ + HAL_DMA_STATE_READY_HALF = 0x05U, /*!< DMA Half process success */ }HAL_DMA_StateTypeDef; /** @@ -124,8 +124,8 @@ typedef enum */ typedef enum { - HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ - HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ }HAL_DMA_LevelCompleteTypeDef; @@ -168,9 +168,9 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Error_Code DMA Error Codes * @{ */ -#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ -#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ +#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ +#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ #if defined (STM32L011xx) || defined (STM32L021xx) #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ @@ -200,22 +200,22 @@ typedef struct __DMA_HandleTypeDef #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) -#define DMA_REQUEST_0 ((uint32_t)0x00000000) -#define DMA_REQUEST_1 ((uint32_t)0x00000001) -#define DMA_REQUEST_2 ((uint32_t)0x00000002) -#define DMA_REQUEST_3 ((uint32_t)0x00000003) -#define DMA_REQUEST_4 ((uint32_t)0x00000004) -#define DMA_REQUEST_5 ((uint32_t)0x00000005) -#define DMA_REQUEST_6 ((uint32_t)0x00000006) -#define DMA_REQUEST_7 ((uint32_t)0x00000007) -#define DMA_REQUEST_8 ((uint32_t)0x00000008) -#define DMA_REQUEST_9 ((uint32_t)0x00000009) -#define DMA_REQUEST_10 ((uint32_t)0x0000000A) -#define DMA_REQUEST_11 ((uint32_t)0x0000000B) -#define DMA_REQUEST_12 ((uint32_t)0x0000000C) -#define DMA_REQUEST_13 ((uint32_t)0x0000000D) -#define DMA_REQUEST_14 ((uint32_t)0x0000000E) -#define DMA_REQUEST_15 ((uint32_t)0x0000000F) +#define DMA_REQUEST_0 ((uint32_t)0x00000000U) +#define DMA_REQUEST_1 ((uint32_t)0x00000001U) +#define DMA_REQUEST_2 ((uint32_t)0x00000002U) +#define DMA_REQUEST_3 ((uint32_t)0x00000003U) +#define DMA_REQUEST_4 ((uint32_t)0x00000004U) +#define DMA_REQUEST_5 ((uint32_t)0x00000005U) +#define DMA_REQUEST_6 ((uint32_t)0x00000006U) +#define DMA_REQUEST_7 ((uint32_t)0x00000007U) +#define DMA_REQUEST_8 ((uint32_t)0x00000008U) +#define DMA_REQUEST_9 ((uint32_t)0x00000009U) +#define DMA_REQUEST_10 ((uint32_t)0x0000000AU) +#define DMA_REQUEST_11 ((uint32_t)0x0000000BU) +#define DMA_REQUEST_12 ((uint32_t)0x0000000CU) +#define DMA_REQUEST_13 ((uint32_t)0x0000000DU) +#define DMA_REQUEST_14 ((uint32_t)0x0000000EU) +#define DMA_REQUEST_15 ((uint32_t)0x0000000FU) #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ ((REQUEST) == DMA_REQUEST_1) || \ @@ -236,17 +236,17 @@ typedef struct __DMA_HandleTypeDef #else /* #if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ -#define DMA_REQUEST_0 ((uint32_t)0x00000000) -#define DMA_REQUEST_1 ((uint32_t)0x00000001) -#define DMA_REQUEST_2 ((uint32_t)0x00000002) -#define DMA_REQUEST_3 ((uint32_t)0x00000003) -#define DMA_REQUEST_4 ((uint32_t)0x00000004) -#define DMA_REQUEST_5 ((uint32_t)0x00000005) -#define DMA_REQUEST_6 ((uint32_t)0x00000006) -#define DMA_REQUEST_7 ((uint32_t)0x00000007) -#define DMA_REQUEST_8 ((uint32_t)0x00000008) -#define DMA_REQUEST_9 ((uint32_t)0x00000009) -#define DMA_REQUEST_11 ((uint32_t)0x0000000B) +#define DMA_REQUEST_0 ((uint32_t)0x00000000U) +#define DMA_REQUEST_1 ((uint32_t)0x00000001U) +#define DMA_REQUEST_2 ((uint32_t)0x00000002U) +#define DMA_REQUEST_3 ((uint32_t)0x00000003U) +#define DMA_REQUEST_4 ((uint32_t)0x00000004U) +#define DMA_REQUEST_5 ((uint32_t)0x00000005U) +#define DMA_REQUEST_6 ((uint32_t)0x00000006U) +#define DMA_REQUEST_7 ((uint32_t)0x00000007U) +#define DMA_REQUEST_8 ((uint32_t)0x00000008U) +#define DMA_REQUEST_9 ((uint32_t)0x00000009U) +#define DMA_REQUEST_11 ((uint32_t)0x0000000BU) #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ ((REQUEST) == DMA_REQUEST_1) || \ @@ -268,7 +268,7 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Data_transfer_direction DMA Data Transfer directions * @{ */ -#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ +#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ @@ -291,7 +291,7 @@ typedef struct __DMA_HandleTypeDef * @{ */ #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ -#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ +#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */ #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ ((STATE) == DMA_PINC_DISABLE)) @@ -303,7 +303,7 @@ typedef struct __DMA_HandleTypeDef * @{ */ #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ -#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ +#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */ #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ ((STATE) == DMA_MINC_DISABLE)) @@ -314,7 +314,7 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Peripheral_data_size DMA Peripheral Data Size Alignment * @{ */ -#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */ +#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte */ #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ @@ -329,7 +329,7 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Memory_data_size DMA Memory Data Size Alignment * @{ */ -#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */ +#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte */ #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ @@ -343,7 +343,7 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_mode DMA Mode * @{ */ -#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */ +#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal Mode */ #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ @@ -355,7 +355,7 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Priority_level DMA Priority Level * @{ */ -#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ +#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level : Low */ #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ @@ -385,34 +385,34 @@ typedef struct __DMA_HandleTypeDef * @{ */ -#define DMA_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA_FLAG_GL1 ((uint32_t)0x00000001U) +#define DMA_FLAG_TC1 ((uint32_t)0x00000002U) +#define DMA_FLAG_HT1 ((uint32_t)0x00000004U) +#define DMA_FLAG_TE1 ((uint32_t)0x00000008U) +#define DMA_FLAG_GL2 ((uint32_t)0x00000010U) +#define DMA_FLAG_TC2 ((uint32_t)0x00000020U) +#define DMA_FLAG_HT2 ((uint32_t)0x00000040U) +#define DMA_FLAG_TE2 ((uint32_t)0x00000080U) +#define DMA_FLAG_GL3 ((uint32_t)0x00000100U) +#define DMA_FLAG_TC3 ((uint32_t)0x00000200U) +#define DMA_FLAG_HT3 ((uint32_t)0x00000400U) +#define DMA_FLAG_TE3 ((uint32_t)0x00000800U) +#define DMA_FLAG_GL4 ((uint32_t)0x00001000U) +#define DMA_FLAG_TC4 ((uint32_t)0x00002000U) +#define DMA_FLAG_HT4 ((uint32_t)0x00004000U) +#define DMA_FLAG_TE4 ((uint32_t)0x00008000U) +#define DMA_FLAG_GL5 ((uint32_t)0x00010000U) +#define DMA_FLAG_TC5 ((uint32_t)0x00020000U) +#define DMA_FLAG_HT5 ((uint32_t)0x00040000U) +#define DMA_FLAG_TE5 ((uint32_t)0x00080000U) +#define DMA_FLAG_GL6 ((uint32_t)0x00100000U) +#define DMA_FLAG_TC6 ((uint32_t)0x00200000U) +#define DMA_FLAG_HT6 ((uint32_t)0x00400000U) +#define DMA_FLAG_TE6 ((uint32_t)0x00800000U) +#define DMA_FLAG_GL7 ((uint32_t)0x01000000U) +#define DMA_FLAG_TC7 ((uint32_t)0x02000000U) +#define DMA_FLAG_HT7 ((uint32_t)0x04000000U) +#define DMA_FLAG_TE7 ((uint32_t)0x08000000U) /** @@ -605,6 +605,14 @@ typedef struct __DMA_HandleTypeDef */ #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) +/** + * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. + * @param __HANDLE__: DMA handle + * + * @retval The number of remaining data units in the current DMA Channel transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_firewall.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_firewall.c index 7e0a1fc46c..9c85825034 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_firewall.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_firewall.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_firewall.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief FIREWALL HAL module driver. * This file provides firmware functions to manage the Firewall * Peripheral initialization and enabling. @@ -133,19 +133,19 @@ HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init) /* Check Firewall configuration addresses and lengths when segment is protected */ /* Code segment */ - if (fw_init->CodeSegmentLength != 0) + if (fw_init->CodeSegmentLength != 0U) { assert_param(IS_FIREWALL_CODE_SEGMENT_ADDRESS(fw_init->CodeSegmentStartAddress)); assert_param(IS_FIREWALL_CODE_SEGMENT_LENGTH(fw_init->CodeSegmentStartAddress, fw_init->CodeSegmentLength)); } /* Non volatile data segment */ - if (fw_init->NonVDataSegmentLength != 0) + if (fw_init->NonVDataSegmentLength != 0U) { assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(fw_init->NonVDataSegmentStartAddress)); assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(fw_init->NonVDataSegmentStartAddress, fw_init->NonVDataSegmentLength)); } /* Volatile data segment */ - if (fw_init->VDataSegmentLength != 0) + if (fw_init->VDataSegmentLength != 0U) { assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(fw_init->VDataSegmentStartAddress)); assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(fw_init->VDataSegmentStartAddress, fw_init->VDataSegmentLength)); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_firewall.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_firewall.h index b38099d3cc..197de1c285 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_firewall.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_firewall.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_firewall.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of FIREWALL HAL module. ****************************************************************************** * @attention @@ -108,7 +108,7 @@ typedef struct /** @defgroup FIREWALL_VolatileData_Executable FIREWALL volatile data segment execution status * @{ */ -#define FIREWALL_VOLATILEDATA_NOT_EXECUTABLE ((uint32_t)0x0000) +#define FIREWALL_VOLATILEDATA_NOT_EXECUTABLE ((uint32_t)0x0000U) #define FIREWALL_VOLATILEDATA_EXECUTABLE ((uint32_t)FW_CR_VDE) /** * @} @@ -117,7 +117,7 @@ typedef struct /** @defgroup FIREWALL_VolatileData_Shared FIREWALL volatile data segment share status * @{ */ -#define FIREWALL_VOLATILEDATA_NOT_SHARED ((uint32_t)0x0000) +#define FIREWALL_VOLATILEDATA_NOT_SHARED ((uint32_t)0x0000U) #define FIREWALL_VOLATILEDATA_SHARED ((uint32_t)FW_CR_VDS) /** * @} @@ -126,7 +126,7 @@ typedef struct /** @defgroup FIREWALL_Pre_Arm FIREWALL pre arm status * @{ */ -#define FIREWALL_PRE_ARM_RESET ((uint32_t)0x0000) +#define FIREWALL_PRE_ARM_RESET ((uint32_t)0x0000U) #define FIREWALL_PRE_ARM_SET ((uint32_t)FW_CR_FPA) /** @@ -147,7 +147,7 @@ typedef struct #define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE))) #define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE)) -#define IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= SRAM_BASE) && ((ADDRESS) < (SRAM_BASE + SRAM1_SIZE_MAX))) +#define IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= SRAM_BASE) && ((ADDRESS) < (SRAM_BASE + SRAM_SIZE_MAX))) #define IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (SRAM_BASE + SRAM_SIZE_MAX)) diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash.c index 7972cb7101..ee51155216 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_flash.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: @@ -315,12 +315,12 @@ void HAL_FLASH_IRQHandler(void) /* Check FLASH operation error flags */ /* WARNING : On the first cut of STM32L031xx and STM32L041xx devices, - * (RevID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving + * (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving * as expected. If the user run an application using the first * cut of the STM32L031xx device or the first cut of the STM32L041xx * device, the check on the FLASH_FLAG_OPTVERR bit should be ignored. * - * Note :The RevID of the device can be retrieved via the HAL_GetREVID() + * Note :The revId of the device can be retrieved via the HAL_GetREVID() * function. * */ @@ -332,7 +332,7 @@ void HAL_FLASH_IRQHandler(void) { /* Return the faulty sector */ temp = ProcFlash.Page; - ProcFlash.Page = 0xFFFFFFFF; + ProcFlash.Page = 0xFFFFFFFFU; } else { @@ -365,7 +365,7 @@ void HAL_FLASH_IRQHandler(void) ProcFlash.NbPagesToErase--; /* Check if there are still sectors to erase */ - if(ProcFlash.NbPagesToErase != 0) + if(ProcFlash.NbPagesToErase != 0U) { temp = ProcFlash.Page; /* Indicate user which sector has been erased */ @@ -384,7 +384,7 @@ void HAL_FLASH_IRQHandler(void) { /* No more sectors to Erase, user callback can be called */ /* Reset Sector and stop Erase sectors procedure */ - ProcFlash.Page = temp = 0xFFFFFFFF; + ProcFlash.Page = temp = 0xFFFFFFFFU; ProcFlash.ProcedureOnGoing = FLASH_PROC_NONE; /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(temp); @@ -634,7 +634,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { return HAL_TIMEOUT; } @@ -745,7 +745,7 @@ void FLASH_ErasePage(uint32_t Page_Address) SET_BIT(FLASH->PECR, FLASH_PECR_PROG); /* Write 00000000h to the first word of the program page to erase */ - *(__IO uint32_t *)Page_Address = 0x00000000; + *(__IO uint32_t *)Page_Address = 0x00000000U; } /** diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash.h index 7fca38b9b6..96afb4a1b7 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_flash.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of Flash HAL module. ****************************************************************************** * @attention @@ -63,7 +63,7 @@ */ typedef enum { - FLASH_PROC_NONE = 0, + FLASH_PROC_NONE = 0U, FLASH_PROC_PAGEERASE, FLASH_PROC_PROGRAM } FLASH_ProcedureTypeDef; @@ -117,8 +117,8 @@ typedef struct extern FLASH_ProcessTypeDef ProcFlash; -#define FLASH_TIMEOUT_VALUE ((uint32_t)50000) /* 50 s */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FF8007C) +#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U) /* 50 s */ +#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FF8007CU) /** * @} */ @@ -131,13 +131,13 @@ extern FLASH_ProcessTypeDef ProcFlash; /** * @brief FLASH size information */ -#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER) * 1024) -#define FLASH_PAGE_SIZE ((uint32_t)128) +#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER) * 1024U) +#define FLASH_PAGE_SIZE ((uint32_t)128U) /** @defgroup FLASH_Type_Program FLASH Type Program * @{ */ -#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02) /*!NbPages)); assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U)); /* Erase by sector by sector to be done*/ for(index = pEraseInit->PageAddress; index < ((pEraseInit->NbPages * FLASH_PAGE_SIZE)+ pEraseInit->PageAddress); index += FLASH_PAGE_SIZE) @@ -243,7 +243,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) assert_param(IS_NBPAGES(pEraseInit->NbPages)); assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U)); /* Clean the error context */ ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE; @@ -458,7 +458,7 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) pAdvOBInit->OptionType = OPTIONBYTE_PCROP; #endif /* Get PCROP state */ - pAdvOBInit->PCROPState = (FLASH->OPTR & FLASH_OPTR_WPRMOD) >> 8; + pAdvOBInit->PCROPState = (FLASH->OPTR & FLASH_OPTR_WPRMOD) >> 8U; /* Get PCROP protected sector */ pAdvOBInit->PCROPSector = FLASH->WRPR; @@ -467,7 +467,7 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) pAdvOBInit->PCROPSector2 = FLASH->WRPR2; /* Get boot bank config */ - pAdvOBInit->BootConfig = (FLASH->OPTR & FLASH_OPTR_BFB2) >> 23; + pAdvOBInit->BootConfig = (FLASH->OPTR & FLASH_OPTR_BFB2) >> 23U; #endif } @@ -479,7 +479,7 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) */ HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) { - return (FLASH_OB_PCROPSelectionConfig(1)); + return (FLASH_OB_PCROPSelectionConfig(1U)); } /** @@ -490,7 +490,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) */ HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) { - return (FLASH_OB_PCROPSelectionConfig(0)); + return (FLASH_OB_PCROPSelectionConfig(0U)); } /** @@ -578,7 +578,7 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t Address) ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Write "00000000h" to valid address in the data memory" */ - *(__IO uint32_t *) Address = 0x00000000; + *(__IO uint32_t *) Address = 0x00000000U; status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); } @@ -680,7 +680,7 @@ void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void) static uint8_t FLASH_OB_GetUser(void) { /* Return the User Option Byte */ - return (uint8_t)((FLASH->OPTR & FLASH_OPTR_USER) >> 16); + return (uint8_t)((FLASH->OPTR & FLASH_OPTR_USER) >> 16U); } /** @@ -699,7 +699,7 @@ static uint8_t FLASH_OB_GetRDP(void) static uint8_t FLASH_OB_GetBOR(void) { /* Return the BOR level */ - return (uint8_t)((FLASH->OPTR & (uint32_t)FLASH_OPTR_BOR_LEV) >> 16); + return (uint8_t)((FLASH->OPTR & (uint32_t)FLASH_OPTR_BOR_LEV) >> 16U); } /** @@ -709,7 +709,7 @@ static uint8_t FLASH_OB_GetBOR(void) static uint8_t FLASH_OB_GetBOOTBit1(void) { /* Return the BOR level */ - return (FLASH->OPTR & FLASH_OPTR_BOOT1) >> 31; + return (FLASH->OPTR & FLASH_OPTR_BOOT1) >> 31U; } @@ -754,7 +754,7 @@ static uint32_t FLASH_OB_GetWRP2(void) static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) { HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp = 0, tmp1 = 0, OB_Bits = (uint32_t) (OB_IWDG | OB_STOP | OB_STDBY); + uint32_t tmp = 0U, tmp1 = 0U, OB_Bits = (uint32_t) (OB_IWDG | OB_STOP | OB_STDBY); /* Check the parameters */ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); @@ -765,10 +765,10 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, u ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Get the User Option byte register */ - tmp1 = OB->USER & ((~FLASH_OPTR_USER) >> 16); + tmp1 = OB->USER & ((~FLASH_OPTR_USER) >> 16U); /* Calculate the user option byte to write */ - tmp = (~(OB_Bits | tmp1)) << 16; + tmp = (~(OB_Bits | tmp1)) << 16U; tmp |= OB_Bits | tmp1; /* Wait for last operation to be completed */ @@ -803,14 +803,14 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, u static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP) { HAL_StatusTypeDef status; - uint32_t tmp = 0, tmp1 = 0, OB_Bits = (uint32_t) OB_RDP; + uint32_t tmp = 0U, tmp1 = 0U, OB_Bits = (uint32_t) OB_RDP; /* Check the parameters */ assert_param(IS_OB_RDP(OB_RDP)); /* Calculate the option byte to write */ - tmp = (OB->RDP & ((~FLASH_OPTR_RDPROT) & 0x0000FFFF)) | OB_Bits; - tmp1 = (~tmp << 16) | tmp; + tmp = (OB->RDP & ((~FLASH_OPTR_RDPROT) & 0x0000FFFFU)) | OB_Bits; + tmp1 = (~tmp << 16U) | tmp; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); @@ -843,16 +843,16 @@ static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP) static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR) { HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp = 0, tmp1 = 0, OB_Bits = (uint32_t) OB_BOR; + uint32_t tmp = 0U, tmp1 = 0U, OB_Bits = (uint32_t) OB_BOR; /* Check the parameters */ assert_param(IS_OB_BOR_LEVEL(OB_BOR)); /* Get the User Option byte register */ - tmp1 = OB->USER & ((~FLASH_OPTR_BOR_LEV) >> 16); + tmp1 = OB->USER & ((~FLASH_OPTR_BOR_LEV) >> 16U); /* Calculate the user option byte to write */ - tmp = (~(OB_Bits | tmp1)) << 16; + tmp = (~(OB_Bits | tmp1)) << 16U; tmp |= OB_Bits | tmp1; /* Wait for last operation to be completed */ @@ -882,16 +882,16 @@ static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR) static HAL_StatusTypeDef FLASH_OB_BOOTBit1Config(uint8_t OB_BOOT_BIT1) { HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp = 0, tmp1 = 0, OB_Bits = ((uint32_t) OB_BOOT_BIT1) << 15; + uint32_t tmp = 0U, tmp1 = 0U, OB_Bits = ((uint32_t) OB_BOOT_BIT1) << 15U; /* Check the parameters */ assert_param(IS_OB_BOOT1(OB_BOOT_BIT1)); /* Get the User Option byte register */ - tmp1 = OB->USER & ((~FLASH_OPTR_BOOT1) >> 16); + tmp1 = OB->USER & ((~FLASH_OPTR_BOOT1) >> 16U); /* Calculate the user option byte to write */ - tmp = (~(OB_Bits | tmp1)) << 16; + tmp = (~(OB_Bits | tmp1)) << 16U; tmp |= OB_Bits | tmp1; /* Wait for last operation to be completed */ @@ -923,13 +923,13 @@ static HAL_StatusTypeDef FLASH_OB_BOOTBit1Config(uint8_t OB_BOOT_BIT1) static HAL_StatusTypeDef FLASH_OB_PCROPSelectionConfig(uint32_t WPRMOD) { HAL_StatusTypeDef status; - uint32_t tmp = 0, tmp1 = 0, OB_Bits = ((uint32_t) WPRMOD) << 8; + uint32_t tmp = 0U, tmp1 = 0U, OB_Bits = ((uint32_t) WPRMOD) << 8U; /* Get the User Option byte register */ - tmp1 = OB->USER & ((~FLASH_OPTR_WPRMOD) >> 16); + tmp1 = OB->USER & ((~FLASH_OPTR_WPRMOD) >> 16U); /* Calculate the user option byte to write */ - tmp = (~(OB_Bits | tmp1)) << 16; + tmp = (~(OB_Bits | tmp1)) << 16U; tmp |= OB_Bits | tmp1; /* Wait for last operation to be completed */ @@ -960,16 +960,16 @@ static HAL_StatusTypeDef FLASH_OB_PCROPSelectionConfig(uint32_t WPRMOD) static HAL_StatusTypeDef FLASH_OB_BFB2Config(uint8_t OB_BFB2) { HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp = 0, tmp1 = 0, OB_Bits = ((uint32_t) OB_BFB2) << 7; + uint32_t tmp = 0U, tmp1 = 0U, OB_Bits = ((uint32_t) OB_BFB2) << 7U; /* Check the parameters */ assert_param(IS_OB_BOOT_BANK(OB_BFB2)); /* Get the User Option byte register */ - tmp1 = OB->USER & ((~FLASH_OPTR_BFB2) >> 16); + tmp1 = OB->USER & ((~FLASH_OPTR_BFB2) >> 16U); /* Calculate the user option byte to write */ - tmp = (~(OB_Bits | tmp1)) << 16; + tmp = (~(OB_Bits | tmp1)) << 16U; tmp |= OB_Bits | tmp1; /* Wait for last operation to be completed */ @@ -1013,7 +1013,7 @@ static HAL_StatusTypeDef FLASH_OB_ProtectedSectorsConfig(uint32_t Sector, uint32 #endif { HAL_StatusTypeDef status = HAL_OK; - uint32_t WRP_Data = 0; + uint32_t WRP_Data = 0U; uint32_t OB_WRP = Sector; /* Check the parameters */ @@ -1027,46 +1027,46 @@ static HAL_StatusTypeDef FLASH_OB_ProtectedSectorsConfig(uint32_t Sector, uint32 /* Clean the error context */ ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - if (OB_WRP & 0x0000FFFF) + if (OB_WRP & 0x0000FFFFU) { if (NewState != OB_WRPSTATE_DISABLE) { WRP_Data = (uint16_t)(((OB_WRP & WRP_MASK_LOW) | OB->WRP01)); - OB->WRP01 = (uint32_t)(~(WRP_Data) << 16) | (WRP_Data); + OB->WRP01 = (uint32_t)(~(WRP_Data) << 16U) | (WRP_Data); } else { WRP_Data = (uint16_t)(~OB_WRP & (WRP_MASK_LOW & OB->WRP01)); - OB->WRP01 = (uint32_t)((~WRP_Data) << 16) | (WRP_Data); + OB->WRP01 = (uint32_t)((~WRP_Data) << 16U) | (WRP_Data); } } #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) - if (OB_WRP & 0xFFFF0000) + if (OB_WRP & 0xFFFF0000U) { if (NewState != OB_WRPSTATE_DISABLE) { - WRP_Data = (uint16_t)((((OB_WRP & WRP_MASK_HIGH) >> 16 | OB->WRP23))); - OB->WRP23 = (uint32_t)(~(WRP_Data) << 16) | (WRP_Data); + WRP_Data = (uint16_t)((((OB_WRP & WRP_MASK_HIGH) >> 16U | OB->WRP23))); + OB->WRP23 = (uint32_t)(~(WRP_Data) << 16U) | (WRP_Data); } else { - WRP_Data = (uint16_t)((((~OB_WRP & WRP_MASK_HIGH) >> 16 & OB->WRP23))); - OB->WRP23 = (uint32_t)((~WRP_Data) << 16) | (WRP_Data); + WRP_Data = (uint16_t)((((~OB_WRP & WRP_MASK_HIGH) >> 16U & OB->WRP23))); + OB->WRP23 = (uint32_t)((~WRP_Data) << 16U) | (WRP_Data); } } OB_WRP = Sector2; - if (OB_WRP & 0x0000FFFF) + if (OB_WRP & 0x0000FFFFU) { if (NewState != OB_WRPSTATE_DISABLE) { WRP_Data = (uint16_t)(((OB_WRP & WRP_MASK_LOW) | OB->WRP45)); - OB->WRP45 =(uint32_t)(~(WRP_Data) << 16) | (WRP_Data); + OB->WRP45 =(uint32_t)(~(WRP_Data) << 16U) | (WRP_Data); } else { WRP_Data = (uint16_t)(~OB_WRP & (WRP_MASK_LOW & OB->WRP45)); - OB->WRP45 = (uint32_t)((~WRP_Data) << 16) | (WRP_Data); + OB->WRP45 = (uint32_t)((~WRP_Data) << 16U) | (WRP_Data); } } #endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ex.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ex.h index 68a3dafd13..db945bb585 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of FLash HAL Extension module. ****************************************************************************** * @attention @@ -126,7 +126,7 @@ typedef struct /** @defgroup FLASHEx_Type_Erase FLASH Type Erase * @{ */ -#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!< Page erase only */ +#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00U) /*!< Page erase only */ /** * @} */ @@ -134,11 +134,11 @@ typedef struct /** @defgroup FLASHEx_Option_Type FLASH Option Type * @{ */ -#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */ -#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */ -#define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */ -#define OPTIONBYTE_BOR ((uint32_t)0x08) /*!< BOR option byte configuration */ -#define OPTIONBYTE_BOOT_BIT1 ((uint32_t)0x10) /*!< BOOT PIN1 option byte configuration*/ +#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */ +#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */ +#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */ +#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */ +#define OPTIONBYTE_BOOT_BIT1 ((uint32_t)0x10U) /*!< BOOT PIN1 option byte configuration*/ /** * @} */ @@ -146,8 +146,8 @@ typedef struct /** @defgroup FLASHEx_WRP_State FLASH WRP State * @{ */ -#define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable the write protection of the desired sectors */ -#define OB_WRPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable the write protection of the desired sectors */ +#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired sectors */ +#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired sectors */ /** * @} */ @@ -155,8 +155,8 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_ReadWrite_Mask FLASH Option Bytes Write Mask * @{ */ -#define WRP_MASK_LOW ((uint32_t)0x0000FFFF) -#define WRP_MASK_HIGH ((uint32_t)0xFFFF0000) +#define WRP_MASK_LOW ((uint32_t)0x0000FFFFU) +#define WRP_MASK_HIGH ((uint32_t)0xFFFF0000U) /** * @} */ @@ -165,15 +165,15 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection * @{ */ -#define OB_WRP_Pages0to31 ((uint32_t)0x00000001) /* Write protection of Sector0 */ -#define OB_WRP_Pages32to63 ((uint32_t)0x00000002) /* Write protection of Sector1 */ -#define OB_WRP_Pages64to95 ((uint32_t)0x00000004) /* Write protection of Sector2 */ -#define OB_WRP_Pages96to127 ((uint32_t)0x00000008) /* Write protection of Sector3 */ -#define OB_WRP_Pages128to159 ((uint32_t)0x00000010) /* Write protection of Sector4 */ -#define OB_WRP_Pages160to191 ((uint32_t)0x00000020) /* Write protection of Sector5 */ -#define OB_WRP_Pages192to223 ((uint32_t)0x00000040) /* Write protection of Sector6 */ -#define OB_WRP_Pages224to255 ((uint32_t)0x00000080) /* Write protection of Sector7 */ -#define OB_WRP_AllPages ((uint32_t)0x000000FF) /*!< Write protection of all Sectors */ +#define OB_WRP_Pages0to31 ((uint32_t)0x00000001U) /* Write protection of Sector0 */ +#define OB_WRP_Pages32to63 ((uint32_t)0x00000002U) /* Write protection of Sector1 */ +#define OB_WRP_Pages64to95 ((uint32_t)0x00000004U) /* Write protection of Sector2 */ +#define OB_WRP_Pages96to127 ((uint32_t)0x00000008U) /* Write protection of Sector3 */ +#define OB_WRP_Pages128to159 ((uint32_t)0x00000010U) /* Write protection of Sector4 */ +#define OB_WRP_Pages160to191 ((uint32_t)0x00000020U) /* Write protection of Sector5 */ +#define OB_WRP_Pages192to223 ((uint32_t)0x00000040U) /* Write protection of Sector6 */ +#define OB_WRP_Pages224to255 ((uint32_t)0x00000080U) /* Write protection of Sector7 */ +#define OB_WRP_AllPages ((uint32_t)0x000000FFU) /*!< Write protection of all Sectors */ /** * @} */ @@ -181,23 +181,23 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection * @{ */ -#define OB_WRP_Pages0to31 ((uint32_t)0x00000001) /* Write protection of Sector0 */ -#define OB_WRP_Pages32to63 ((uint32_t)0x00000002) /* Write protection of Sector1 */ -#define OB_WRP_Pages64to95 ((uint32_t)0x00000004) /* Write protection of Sector2 */ -#define OB_WRP_Pages96to127 ((uint32_t)0x00000008) /* Write protection of Sector3 */ -#define OB_WRP_Pages128to159 ((uint32_t)0x00000010) /* Write protection of Sector4 */ -#define OB_WRP_Pages160to191 ((uint32_t)0x00000020) /* Write protection of Sector5 */ -#define OB_WRP_Pages192to223 ((uint32_t)0x00000040) /* Write protection of Sector6 */ -#define OB_WRP_Pages224to255 ((uint32_t)0x00000080) /* Write protection of Sector7 */ -#define OB_WRP_Pages256to287 ((uint32_t)0x00000100) /* Write protection of Sector8 */ -#define OB_WRP_Pages288to319 ((uint32_t)0x00000200) /* Write protection of Sector9 */ -#define OB_WRP_Pages320to351 ((uint32_t)0x00000400) /* Write protection of Sector10 */ -#define OB_WRP_Pages352to383 ((uint32_t)0x00000800) /* Write protection of Sector11 */ -#define OB_WRP_Pages384to415 ((uint32_t)0x00001000) /* Write protection of Sector12 */ -#define OB_WRP_Pages416to447 ((uint32_t)0x00002000) /* Write protection of Sector13 */ -#define OB_WRP_Pages448to479 ((uint32_t)0x00004000) /* Write protection of Sector14 */ -#define OB_WRP_Pages480to511 ((uint32_t)0x00008000) /* Write protection of Sector15 */ -#define OB_WRP_AllPages ((uint32_t)0x0000FFFF) /*!< Write protection of all Sectors */ +#define OB_WRP_Pages0to31 ((uint32_t)0x00000001U) /* Write protection of Sector0 */ +#define OB_WRP_Pages32to63 ((uint32_t)0x00000002U) /* Write protection of Sector1 */ +#define OB_WRP_Pages64to95 ((uint32_t)0x00000004U) /* Write protection of Sector2 */ +#define OB_WRP_Pages96to127 ((uint32_t)0x00000008U) /* Write protection of Sector3 */ +#define OB_WRP_Pages128to159 ((uint32_t)0x00000010U) /* Write protection of Sector4 */ +#define OB_WRP_Pages160to191 ((uint32_t)0x00000020U) /* Write protection of Sector5 */ +#define OB_WRP_Pages192to223 ((uint32_t)0x00000040U) /* Write protection of Sector6 */ +#define OB_WRP_Pages224to255 ((uint32_t)0x00000080U) /* Write protection of Sector7 */ +#define OB_WRP_Pages256to287 ((uint32_t)0x00000100U) /* Write protection of Sector8 */ +#define OB_WRP_Pages288to319 ((uint32_t)0x00000200U) /* Write protection of Sector9 */ +#define OB_WRP_Pages320to351 ((uint32_t)0x00000400U) /* Write protection of Sector10 */ +#define OB_WRP_Pages352to383 ((uint32_t)0x00000800U) /* Write protection of Sector11 */ +#define OB_WRP_Pages384to415 ((uint32_t)0x00001000U) /* Write protection of Sector12 */ +#define OB_WRP_Pages416to447 ((uint32_t)0x00002000U) /* Write protection of Sector13 */ +#define OB_WRP_Pages448to479 ((uint32_t)0x00004000U) /* Write protection of Sector14 */ +#define OB_WRP_Pages480to511 ((uint32_t)0x00008000U) /* Write protection of Sector15 */ +#define OB_WRP_AllPages ((uint32_t)0x0000FFFFU) /*!< Write protection of all Sectors */ /** * @} */ @@ -206,39 +206,39 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write ProtectionP * @{ */ -#define OB_WRP_Pages0to31 ((uint32_t)0x00000001) /* Write protection of Sector0 */ -#define OB_WRP_Pages32to63 ((uint32_t)0x00000002) /* Write protection of Sector1 */ -#define OB_WRP_Pages64to95 ((uint32_t)0x00000004) /* Write protection of Sector2 */ -#define OB_WRP_Pages96to127 ((uint32_t)0x00000008) /* Write protection of Sector3 */ -#define OB_WRP_Pages128to159 ((uint32_t)0x00000010) /* Write protection of Sector4 */ -#define OB_WRP_Pages160to191 ((uint32_t)0x00000020) /* Write protection of Sector5 */ -#define OB_WRP_Pages192to223 ((uint32_t)0x00000040) /* Write protection of Sector6 */ -#define OB_WRP_Pages224to255 ((uint32_t)0x00000080) /* Write protection of Sector7 */ -#define OB_WRP_Pages256to287 ((uint32_t)0x00000100) /* Write protection of Sector8 */ -#define OB_WRP_Pages288to319 ((uint32_t)0x00000200) /* Write protection of Sector9 */ -#define OB_WRP_Pages320to351 ((uint32_t)0x00000400) /* Write protection of Sector10 */ -#define OB_WRP_Pages352to383 ((uint32_t)0x00000800) /* Write protection of Sector11 */ -#define OB_WRP_Pages384to415 ((uint32_t)0x00001000) /* Write protection of Sector12 */ -#define OB_WRP_Pages416to447 ((uint32_t)0x00002000) /* Write protection of Sector13 */ -#define OB_WRP_Pages448to479 ((uint32_t)0x00004000) /* Write protection of Sector14 */ -#define OB_WRP_Pages480to511 ((uint32_t)0x00008000) /* Write protection of Sector15 */ -#define OB_WRP_Pages512to543 ((uint32_t)0x00010000) /* Write protection of Sector16 */ -#define OB_WRP_Pages544to575 ((uint32_t)0x00020000) /* Write protection of Sector17 */ -#define OB_WRP_Pages576to607 ((uint32_t)0x00040000) /* Write protection of Sector18 */ -#define OB_WRP_Pages608to639 ((uint32_t)0x00080000) /* Write protection of Sector19 */ -#define OB_WRP_Pages640to671 ((uint32_t)0x00100000) /* Write protection of Sector20 */ -#define OB_WRP_Pages672to703 ((uint32_t)0x00200000) /* Write protection of Sector21 */ -#define OB_WRP_Pages704to735 ((uint32_t)0x00400000) /* Write protection of Sector22 */ -#define OB_WRP_Pages736to767 ((uint32_t)0x00800000) /* Write protection of Sector23 */ -#define OB_WRP_Pages768to799 ((uint32_t)0x01000000) /* Write protection of Sector24 */ -#define OB_WRP_Pages800to831 ((uint32_t)0x02000000) /* Write protection of Sector25 */ -#define OB_WRP_Pages832to863 ((uint32_t)0x04000000) /* Write protection of Sector26 */ -#define OB_WRP_Pages864to895 ((uint32_t)0x08000000) /* Write protection of Sector27 */ -#define OB_WRP_Pages896to927 ((uint32_t)0x10000000) /* Write protection of Sector28 */ -#define OB_WRP_Pages928to959 ((uint32_t)0x20000000) /* Write protection of Sector29 */ -#define OB_WRP_Pages960to991 ((uint32_t)0x40000000) /* Write protection of Sector30 */ -#define OB_WRP_Pages992to1023 ((uint32_t)0x80000000) /* Write protection of Sector31 */ -#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!ACR), FLASH_ACR_PRFTEN) -#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN) +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN) +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN) /** * @brief Enable/Disable the FLASH Buffer cache. @@ -632,7 +632,7 @@ void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void); #define IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || \ ((__VALUE__) == OB_WRPSTATE_ENABLE)) -#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000)) +#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U)) #define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0)||\ ((__LEVEL__) == OB_RDP_LEVEL_1)||\ @@ -654,7 +654,7 @@ void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void); #define IS_PCROPSTATE(VALUE)(((VALUE) == OB_PCROP_STATE_DISABLE) || \ ((VALUE) == OB_PCROP_STATE_ENABLE)) -#define IS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000)) +#define IS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000U)) #define IS_OB_BOOT1(__BOOT_BIT1__) (((__BOOT_BIT1__) == OB_BOOT_BIT1_RESET) || ((__BOOT_BIT1__) == OB_BOOT_BIT1_SET)) diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ramfunc.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ramfunc.c index 07a67cc468..137fb2c37c 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ramfunc.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ramfunc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_flash_ramfunc.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief FLASH RAMFUNC driver. * This file provides a Flash firmware functions which should be * executed from internal SRAM @@ -177,9 +177,9 @@ __RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_A SET_BIT(FLASH->PECR, FLASH_PECR_PROG); /* Write 00000000h to the first word of the first program page to erase */ - *(__IO uint32_t *)Page_Address1 = 0x00000000; + *(__IO uint32_t *)Page_Address1 = 0x00000000U; /* Write 00000000h to the first word of the second program page to erase */ - *(__IO uint32_t *)Page_Address2 = 0x00000000; + *(__IO uint32_t *)Page_Address2 = 0x00000000U; /* Wait for last operation to be completed */ status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); @@ -245,12 +245,12 @@ __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuf { /* Write one half page, Address1 doesn't need to be increased */ - count = 0; + count = 0U; /* Disable all IRQs */ __disable_irq(); - while(count < 16) + while(count < 16U) { *(__IO uint32_t*) Address1 = *pBuffer1; pBuffer1++; @@ -259,8 +259,8 @@ __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuf /* Write the second half page, Address2 doesn't need to be increased */ - count = 0; - while(count < 16) + count = 0U; + while(count < 16U) { *(__IO uint32_t*) Address2 = *pBuffer2; pBuffer2++; @@ -328,14 +328,14 @@ __RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t *pBuffer) SET_BIT(FLASH->PECR, FLASH_PECR_PROG); - count = 0; + count = 0U; /* Write one half page, Address doesn't need to be increased */ /* Disable all IRQs */ __disable_irq(); - while(count < 16) + while(count < 16U) { *(__IO uint32_t*) Address = *pBuffer; pBuffer++; @@ -407,10 +407,10 @@ static __RAM_FUNC FLASHRAM_SetErrorCode(void) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) { /* WARNING : On the first cut of STM32L031xx and STM32L041xx devices, - * (RevID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving + * (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving * as expected. If the user run an application using the first * cut of the STM32L031xx device or the first cut of the STM32L041xx - * device, this error should be ignored. The RevID of the device + * device, this error should be ignored. The revId of the device * can be retrieved via the HAL_GetREVID() function. * */ @@ -449,12 +449,12 @@ static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout) Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00)) + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00U)) { Timeout--; } - if(Timeout == 0x00 ) + if(Timeout == 0x00U ) { return HAL_TIMEOUT; } diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ramfunc.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ramfunc.h index d8a336d81b..70f62a756f 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ramfunc.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ramfunc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_flash_ramfunc.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of FLASH RAMFUNC driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_gpio.c index c5b46b6c65..c929efea34 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_gpio.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_gpio.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: @@ -145,15 +145,15 @@ /* Private define ------------------------------------------------------------*/ -#define GPIO_MODE ((uint32_t)0x00000003) -#define EXTI_MODE ((uint32_t)0x10000000) -#define GPIO_MODE_IT ((uint32_t)0x00010000) -#define GPIO_MODE_EVT ((uint32_t)0x00020000) -#define RISING_EDGE ((uint32_t)0x00100000) -#define FALLING_EDGE ((uint32_t)0x00200000) -#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) +#define GPIO_MODE ((uint32_t)0x00000003U) +#define EXTI_MODE ((uint32_t)0x10000000U) +#define GPIO_MODE_IT ((uint32_t)0x00010000U) +#define GPIO_MODE_EVT ((uint32_t)0x00020000U) +#define RISING_EDGE ((uint32_t)0x00100000U) +#define FALLING_EDGE ((uint32_t)0x00200000U) +#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U) -#define GPIO_NUMBER ((uint32_t)16) +#define GPIO_NUMBER ((uint32_t)16U) /** * @} @@ -184,9 +184,9 @@ */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - uint32_t position = 0x00; - uint32_t iocurrent = 0x00; - uint32_t temp = 0x00; + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t temp = 0x00U; /* Check the parameters */ assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); @@ -197,7 +197,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) while ((GPIO_Init->Pin) >> position) { /* Get the IO position */ - iocurrent = (GPIO_Init->Pin) & (1 << position); + iocurrent = (GPIO_Init->Pin) & (1U << position); if(iocurrent) { @@ -208,10 +208,10 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Check if the Alternate function is compliant with the GPIO in use */ assert_param(IS_GPIO_AF_AVAILABLE(GPIOx,(GPIO_Init->Alternate))); /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3]; - temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)) ; - GPIOx->AFR[position >> 3] = temp; + temp = GPIOx->AFR[position >> 3U]; + temp &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U)) ; + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07U) * 4U)) ; + GPIOx->AFR[position >> 3U] = temp; } /* In case of Output or Alternate function mode selection */ @@ -222,27 +222,27 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; - temp &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2)); - temp |= (GPIO_Init->Speed << (position * 2)); + temp &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U)); + temp |= (GPIO_Init->Speed << (position * 2U)); GPIOx->OSPEEDR = temp; /* Configure the IO Output Type */ temp= GPIOx->OTYPER; temp &= ~(GPIO_OTYPER_OT_0 << position) ; - temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); + temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); GPIOx->OTYPER = temp; } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODE0 << (position * 2)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); GPIOx->MODER = temp; /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; - temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2)); - temp |= ((GPIO_Init->Pull) << (position * 2)); + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + temp |= ((GPIO_Init->Pull) << (position * 2U)); GPIOx->PUPDR = temp; /*--------------------- EXTI Mode Configuration ------------------------*/ @@ -252,10 +252,10 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - temp = SYSCFG->EXTICR[position >> 2]; - temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); - temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); - SYSCFG->EXTICR[position >> 2] = temp; + temp = SYSCFG->EXTICR[position >> 2U]; + temp &= ~(((uint32_t)0x0FU) << (4U * (position & 0x03U))); + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); + SYSCFG->EXTICR[position >> 2U] = temp; /* Clear EXTI line configuration */ temp = EXTI->IMR; @@ -307,9 +307,9 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { - uint32_t position = 0x00; - uint32_t iocurrent = 0x00; - uint32_t tmp = 0x00; + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t tmp = 0x00U; /* Check the parameters */ assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin)); @@ -318,35 +318,35 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) while (GPIO_Pin >> position) { /* Get the IO position */ - iocurrent = (GPIO_Pin) & (1 << position); + iocurrent = (GPIO_Pin) & (1U << position); if(iocurrent) { /*------------------------- GPIO Mode Configuration --------------------*/ /* Configure IO Direction in Input Floting Mode */ - GPIOx->MODER &= ~(GPIO_MODER_MODE0 << (position * 2)); + GPIOx->MODER &= ~(GPIO_MODER_MODE0 << (position * 2U)); /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + GPIOx->AFR[position >> 3U] &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U)) ; /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2)); + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U)); /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; /* Deactivate the Pull-up oand Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2)); + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ - tmp = SYSCFG->EXTICR[position >> 2]; - tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); - if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)))) + tmp = SYSCFG->EXTICR[position >> 2U]; + tmp &= (((uint32_t)0x0FU) << (4U * (position & 0x03U))); + if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) { - tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); - SYSCFG->EXTICR[position >> 2] &= ~tmp; + tmp = ((uint32_t)0x0FU) << (4U * (position & 0x03U)); + SYSCFG->EXTICR[position >> 2U] &= ~tmp; /* Clear EXTI line configuration */ EXTI->IMR &= ~((uint32_t)iocurrent); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_gpio.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_gpio.h index af7776efc2..c8e6e8ba8b 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_gpio.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_gpio.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention @@ -96,7 +96,7 @@ typedef struct */ typedef enum { - GPIO_PIN_RESET = 0, + GPIO_PIN_RESET = 0U, GPIO_PIN_SET }GPIO_PinState; /** @@ -120,29 +120,29 @@ typedef enum /** @defgroup GPIO_pins_define Pin definition * @{ */ -#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ +#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */ /** * @} */ -#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ -#define IS_GPIO_PIN(__PIN__) (((__PIN__) & GPIO_PIN_MASK ) != (uint32_t)0x00) +#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */ +#define IS_GPIO_PIN(__PIN__) (((__PIN__) & GPIO_PIN_MASK ) != (uint32_t)0x00U) /** @defgroup GPIO_mode_define Mode definition * @brief GPIO Configuration Mode @@ -154,21 +154,21 @@ typedef enum * - Z : IO Direction mode (Input, Output, Alternate or Analog) * @{ */ -#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /*!< Alternate Function Open Drain Mode */ -#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */ +#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog Mode */ -#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */ /** * @} @@ -192,10 +192,10 @@ typedef enum * @brief GPIO Output Maximum frequency * @{ */ -#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000) /*!< range up to 0.4 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001) /*!< range 0.4 MHz to 2 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002) /*!< range 2 MHz to 10 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003) /*!< range 10 MHz to 35 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< range up to 0.4 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< range 0.4 MHz to 2 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< range 2 MHz to 10 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< range 10 MHz to 35 MHz, please refer to the product datasheet */ /** * @} @@ -209,9 +209,9 @@ typedef enum * @brief GPIO Pull-Up or Pull-Down Activation * @{ */ -#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */ -#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */ +#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */ +#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_gpio_ex.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_gpio_ex.h index 8f5c97b5b1..82347ccdee 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_gpio_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_gpio_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention @@ -177,20 +177,20 @@ /* * Alternate function AF0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */ -#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF0_TIM22 ((uint8_t)0x00) /* TIM22 Alternate Function mapping */ -#define GPIO_AF0_LPUART1 ((uint8_t)0x00) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ -#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */ -#define GPIO_AF0_USB ((uint8_t)0x00) /* USB Alternate Function mapping */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_TIM21 ((uint8_t)0x00U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /* SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /* SWCLK Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /* USART1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM22 ((uint8_t)0x00U) /* TIM22 Alternate Function mapping */ +#define GPIO_AF0_LPUART1 ((uint8_t)0x00U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00U) /* USART2 Alternate Function mapping */ +#define GPIO_AF0_TIM2 ((uint8_t)0x00U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF0_USB ((uint8_t)0x00U) /* USB Alternate Function mapping */ /** * */ @@ -198,10 +198,10 @@ /* * Alternate function AF1 */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ -#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */ -#define GPIO_AF1_TIM21 ((uint8_t)0x01) /* TIM21 Alternate Function mapping */ -#define GPIO_AF1_LCD ((uint8_t)0x01) /* LCD Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM21 ((uint8_t)0x01U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF1_LCD ((uint8_t)0x01U) /* LCD Alternate Function mapping */ /** * */ @@ -209,17 +209,17 @@ /* * Alternate function AF2 */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF2_MCO ((uint8_t)0x02) /* MCO Alternate Function mapping */ -#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC Alternate Function mapping */ -#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */ -#define GPIO_AF2_USART5 ((uint8_t)0x02) /* USART5 Alternate Function mapping */ -#define GPIO_AF2_SPI1 ((uint8_t)0x02) /* SPI1 Alternate Function mapping */ -#define GPIO_AF2_USB ((uint8_t)0x00) /* USB Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_LPUART1 ((uint8_t)0x02U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF2_MCO ((uint8_t)0x02U) /* MCO Alternate Function mapping */ +#define GPIO_AF2_RTC ((uint8_t)0x02U) /* RTC Alternate Function mapping */ +#define GPIO_AF2_SPI2 ((uint8_t)0x02U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF2_USART5 ((uint8_t)0x02U) /* USART5 Alternate Function mapping */ +#define GPIO_AF2_SPI1 ((uint8_t)0x02U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x00U) /* USB Alternate Function mapping */ /** * */ @@ -227,9 +227,9 @@ /* * Alternate function AF3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */ -#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ /** * */ @@ -237,13 +237,13 @@ /* * Alternate function AF4 */ -#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ -#define GPIO_AF4_LPUART1 ((uint8_t)0x04) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ -#define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping*/ -#define GPIO_AF4_TIM22 ((uint8_t)0x04) /* TIM22 Alternate Function mapping */ -#define GPIO_AF4_TIM3 ((uint8_t)0x04) /* TIM3 Alternate Function mapping */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_USART2 ((uint8_t)0x04U) /* USART2 Alternate Function mapping */ +#define GPIO_AF4_LPUART1 ((uint8_t)0x04U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04U) /* USART1 Alternate Function mapping */ +#define GPIO_AF4_EVENTOUT ((uint8_t)0x04U) /* EVENTOUT Alternate Function mapping*/ +#define GPIO_AF4_TIM22 ((uint8_t)0x04U) /* TIM22 Alternate Function mapping */ +#define GPIO_AF4_TIM3 ((uint8_t)0x04U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ /** * */ @@ -251,12 +251,12 @@ /* * Alternate function AF5 */ -#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */ -#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */ -#define GPIO_AF5_TIM22 ((uint8_t)0x05) /* TIM22 Alternate Function mapping */ -#define GPIO_AF5_USART1 ((uint8_t)0x05) /* USART1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ -#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */ +#define GPIO_AF5_TIM2 ((uint8_t)0x05U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF5_TIM21 ((uint8_t)0x05U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF5_TIM22 ((uint8_t)0x05U) /* TIM22 Alternate Function mapping */ +#define GPIO_AF5_USART1 ((uint8_t)0x05U) /* USART1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /* I2C2 Alternate Function mapping */ /** * */ @@ -265,13 +265,13 @@ * Alternate function AF6 */ -#define GPIO_AF6_USART4 ((uint8_t)0x06) /* USART4 Alternate Function mapping */ -#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF6_I2C1 ((uint8_t)0x06) /* I2C1 Alternate Function mapping */ -#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */ -#define GPIO_AF6_USART5 ((uint8_t)0x06) /* USART5 Alternate Function mapping */ -#define GPIO_AF6_TIM21 ((uint8_t)0x06) /* TIM21 Alternate Function mapping */ +#define GPIO_AF6_USART4 ((uint8_t)0x06U) /* USART4 Alternate Function mapping */ +#define GPIO_AF6_LPUART1 ((uint8_t)0x06U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF6_USART5 ((uint8_t)0x06U) /* USART5 Alternate Function mapping */ +#define GPIO_AF6_TIM21 ((uint8_t)0x06U) /* TIM21 Alternate Function mapping */ /** * */ @@ -279,10 +279,10 @@ /* * Alternate function AF7 */ -#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */ -#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */ -#define GPIO_AF7_I2C3 ((uint8_t)0x07) /* I2C3 Alternate Function mapping */ -#define GPIO_AF7_LPUART1 ((uint8_t)0x07) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /* COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /* COMP2 Alternate Function mapping */ +#define GPIO_AF7_I2C3 ((uint8_t)0x07U) /* I2C3 Alternate Function mapping */ +#define GPIO_AF7_LPUART1 ((uint8_t)0x07U) /* LPUART1 Alternate Function mapping */ /** * */ @@ -482,20 +482,20 @@ /* * Alternate function AF0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */ -#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF0_TIM22 ((uint8_t)0x00) /* TIM22 Alternate Function mapping */ -#define GPIO_AF0_LPUART1 ((uint8_t)0x00) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ -#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */ -#define GPIO_AF0_USB ((uint8_t)0x00) /* USB Alternate Function mapping */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_TIM21 ((uint8_t)0x00U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /* SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /* SWCLK Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /* USART1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM22 ((uint8_t)0x00U) /* TIM22 Alternate Function mapping */ +#define GPIO_AF0_LPUART1 ((uint8_t)0x00U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00U) /* USART2 Alternate Function mapping */ +#define GPIO_AF0_TIM2 ((uint8_t)0x00U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF0_USB ((uint8_t)0x00U) /* USB Alternate Function mapping */ /** * */ @@ -503,9 +503,9 @@ /* * Alternate function AF1 */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ -#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */ -#define GPIO_AF1_TIM21 ((uint8_t)0x01) /* TIM21 Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM21 ((uint8_t)0x01U) /* TIM21 Alternate Function mapping */ /** * */ @@ -513,17 +513,17 @@ /* * Alternate function AF2 */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF2_MCO ((uint8_t)0x02) /* MCO Alternate Function mapping */ -#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC Alternate Function mapping */ -#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */ -#define GPIO_AF2_USART5 ((uint8_t)0x02) /* USART5 Alternate Function mapping */ -#define GPIO_AF2_SPI1 ((uint8_t)0x02) /* SPI1 Alternate Function mapping */ -#define GPIO_AF2_USB ((uint8_t)0x00) /* USB Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_LPUART1 ((uint8_t)0x02U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF2_MCO ((uint8_t)0x02U) /* MCO Alternate Function mapping */ +#define GPIO_AF2_RTC ((uint8_t)0x02U) /* RTC Alternate Function mapping */ +#define GPIO_AF2_SPI2 ((uint8_t)0x02U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF2_USART5 ((uint8_t)0x02U) /* USART5 Alternate Function mapping */ +#define GPIO_AF2_SPI1 ((uint8_t)0x02U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x00U) /* USB Alternate Function mapping */ /** * */ @@ -531,9 +531,9 @@ /* * Alternate function AF3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */ -#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ /** * */ @@ -541,13 +541,13 @@ /* * Alternate function AF4 */ -#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ -#define GPIO_AF4_LPUART1 ((uint8_t)0x04) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ -#define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF4_TIM22 ((uint8_t)0x04) /* TIM22 Alternate Function mapping */ -#define GPIO_AF4_TIM3 ((uint8_t)0x04) /* TIM3 Alternate Function mapping */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_USART2 ((uint8_t)0x04U) /* USART2 Alternate Function mapping */ +#define GPIO_AF4_LPUART1 ((uint8_t)0x04U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04U) /* USART1 Alternate Function mapping */ +#define GPIO_AF4_EVENTOUT ((uint8_t)0x04U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF4_TIM22 ((uint8_t)0x04U) /* TIM22 Alternate Function mapping */ +#define GPIO_AF4_TIM3 ((uint8_t)0x04U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ /** * */ @@ -555,12 +555,12 @@ /* * Alternate function AF5 */ -#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */ -#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */ -#define GPIO_AF5_TIM22 ((uint8_t)0x05) /* TIM22 Alternate Function mapping */ -#define GPIO_AF5_USART1 ((uint8_t)0x05) /* USART1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ -#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */ +#define GPIO_AF5_TIM2 ((uint8_t)0x05U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF5_TIM21 ((uint8_t)0x05U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF5_TIM22 ((uint8_t)0x05U) /* TIM22 Alternate Function mapping */ +#define GPIO_AF5_USART1 ((uint8_t)0x05U) /* USART1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /* I2C2 Alternate Function mapping */ /** * */ @@ -568,13 +568,13 @@ /* * Alternate function AF6 */ -#define GPIO_AF6_USART4 ((uint8_t)0x06) /* USART4 Alternate Function mapping */ -#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF6_I2C1 ((uint8_t)0x06) /* I2C1 Alternate Function mapping */ -#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */ -#define GPIO_AF6_USART5 ((uint8_t)0x06) /* USART5 Alternate Function mapping */ -#define GPIO_AF6_TIM21 ((uint8_t)0x06) /* TIM21 Alternate Function mapping */ +#define GPIO_AF6_USART4 ((uint8_t)0x06U) /* USART4 Alternate Function mapping */ +#define GPIO_AF6_LPUART1 ((uint8_t)0x06U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF6_USART5 ((uint8_t)0x06U) /* USART5 Alternate Function mapping */ +#define GPIO_AF6_TIM21 ((uint8_t)0x06U) /* TIM21 Alternate Function mapping */ /** * */ @@ -582,10 +582,10 @@ /* * Alternate function AF7 */ -#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */ -#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */ -#define GPIO_AF7_I2C3 ((uint8_t)0x07) /* I2C3 Alternate Function mapping */ -#define GPIO_AF7_LPUART1 ((uint8_t)0x07) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /* COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /* COMP2 Alternate Function mapping */ +#define GPIO_AF7_I2C3 ((uint8_t)0x07U) /* I2C3 Alternate Function mapping */ +#define GPIO_AF7_LPUART1 ((uint8_t)0x07U) /* LPUART1 Alternate Function mapping */ /** * */ @@ -784,19 +784,19 @@ * Alternate function AF0 * */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */ -#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF0_TIM22 ((uint8_t)0x00) /* TIM22 Alternate Function mapping */ -#define GPIO_AF0_LPUART1 ((uint8_t)0x00) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ -#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_TIM21 ((uint8_t)0x00U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /* SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /* SWCLK Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /* USART1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM22 ((uint8_t)0x00U) /* TIM22 Alternate Function mapping */ +#define GPIO_AF0_LPUART1 ((uint8_t)0x00U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00U) /* USART2 Alternate Function mapping */ +#define GPIO_AF0_TIM2 ((uint8_t)0x00U) /* TIM2 Alternate Function mapping */ /** * */ @@ -805,9 +805,9 @@ * Alternate function AF1 * */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ -#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */ -#define GPIO_AF1_TIM21 ((uint8_t)0x01) /* TIM21 Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM21 ((uint8_t)0x01U) /* TIM21 Alternate Function mapping */ /** * */ @@ -816,16 +816,16 @@ * Alternate function AF2 * */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF2_MCO ((uint8_t)0x02) /* MCO Alternate Function mapping */ -#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC Alternate Function mapping */ -#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */ -#define GPIO_AF2_USART5 ((uint8_t)0x02) /* USART5 Alternate Function mapping */ -#define GPIO_AF2_SPI1 ((uint8_t)0x02) /* SPI1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_LPUART1 ((uint8_t)0x02U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF2_MCO ((uint8_t)0x02U) /* MCO Alternate Function mapping */ +#define GPIO_AF2_RTC ((uint8_t)0x02U) /* RTC Alternate Function mapping */ +#define GPIO_AF2_SPI2 ((uint8_t)0x02U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF2_USART5 ((uint8_t)0x02U) /* USART5 Alternate Function mapping */ +#define GPIO_AF2_SPI1 ((uint8_t)0x02U) /* SPI1 Alternate Function mapping */ /** * */ @@ -834,8 +834,8 @@ * Alternate function AF3 * @{ */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /* I2C1 Alternate Function mapping */ /** * */ @@ -844,13 +844,13 @@ * Alternate function AF4 * */ -#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ -#define GPIO_AF4_LPUART1 ((uint8_t)0x04) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ -#define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF4_TIM22 ((uint8_t)0x04) /* TIM22 Alternate Function mapping */ -#define GPIO_AF4_TIM3 ((uint8_t)0x04) /* TIM3 Alternate Function mapping */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_USART2 ((uint8_t)0x04U) /* USART2 Alternate Function mapping */ +#define GPIO_AF4_LPUART1 ((uint8_t)0x04U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04U) /* USART1 Alternate Function mapping */ +#define GPIO_AF4_EVENTOUT ((uint8_t)0x04U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF4_TIM22 ((uint8_t)0x04U) /* TIM22 Alternate Function mapping */ +#define GPIO_AF4_TIM3 ((uint8_t)0x04U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ /** * */ @@ -859,12 +859,12 @@ * Alternate function AF5 * */ -#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */ -#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */ -#define GPIO_AF5_TIM22 ((uint8_t)0x05) /* TIM22 Alternate Function mapping */ -#define GPIO_AF5_USART1 ((uint8_t)0x05) /* USART1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ -#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */ +#define GPIO_AF5_TIM2 ((uint8_t)0x05U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF5_TIM21 ((uint8_t)0x05U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF5_TIM22 ((uint8_t)0x05U) /* TIM22 Alternate Function mapping */ +#define GPIO_AF5_USART1 ((uint8_t)0x05U) /* USART1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /* I2C2 Alternate Function mapping */ /** * */ @@ -873,13 +873,13 @@ * Alternate function AF6 * */ -#define GPIO_AF6_USART4 ((uint8_t)0x06) /* USART4 Alternate Function mapping */ -#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF6_I2C1 ((uint8_t)0x06) /* I2C1 Alternate Function mapping */ -#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */ -#define GPIO_AF6_USART5 ((uint8_t)0x06) /* USART5 Alternate Function mapping */ -#define GPIO_AF6_TIM21 ((uint8_t)0x06) /* TIM21 Alternate Function mapping */ +#define GPIO_AF6_USART4 ((uint8_t)0x06U) /* USART4 Alternate Function mapping */ +#define GPIO_AF6_LPUART1 ((uint8_t)0x06U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF6_USART5 ((uint8_t)0x06U) /* USART5 Alternate Function mapping */ +#define GPIO_AF6_TIM21 ((uint8_t)0x06U) /* TIM21 Alternate Function mapping */ /** * */ @@ -888,10 +888,10 @@ * Alternate function AF7 * */ -#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */ -#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */ -#define GPIO_AF7_I2C3 ((uint8_t)0x07) /* I2C3 Alternate Function mapping */ -#define GPIO_AF7_LPUART1 ((uint8_t)0x07) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /* COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /* COMP2 Alternate Function mapping */ +#define GPIO_AF7_I2C3 ((uint8_t)0x07U) /* I2C3 Alternate Function mapping */ +#define GPIO_AF7_LPUART1 ((uint8_t)0x07U) /* LPUART1 Alternate Function mapping */ /** * */ @@ -1048,21 +1048,21 @@ /* * Alternate function AF0 */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */ -#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ -#define GPIO_AF0_LPUART1 ((uint8_t)0x00) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF0_USB ((uint8_t)0x00) /* USB Alternate Function mapping */ -#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF0_TSC ((uint8_t)0x00) /* TSC Alternate Function mapping */ -#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */ -#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */ -#define GPIO_AF0_TIM22 ((uint8_t)0x00) /* TIM22 Alternate Function mapping */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /* USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00U) /* USART2 Alternate Function mapping */ +#define GPIO_AF0_LPUART1 ((uint8_t)0x00U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF0_USB ((uint8_t)0x00U) /* USB Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_TSC ((uint8_t)0x00U) /* TSC Alternate Function mapping */ +#define GPIO_AF0_TIM2 ((uint8_t)0x00U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF0_TIM21 ((uint8_t)0x00U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF0_TIM22 ((uint8_t)0x00U) /* TIM22 Alternate Function mapping */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /* SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /* SWCLK Alternate Function mapping */ /** * */ @@ -1070,10 +1070,10 @@ /* * Alternate function AF1 */ -#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */ -#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ -#define GPIO_AF1_LCD ((uint8_t)0x01) /* LCD Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF1_LCD ((uint8_t)0x01U) /* LCD Alternate Function mapping */ /** * */ @@ -1081,13 +1081,13 @@ /* * Alternate function AF2 */ -#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */ -#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF2_USB ((uint8_t)0x02) /* USB Alternate Function mapping */ -#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC Alternate Function mapping */ +#define GPIO_AF2_SPI2 ((uint8_t)0x02U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF2_LPUART1 ((uint8_t)0x02U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02U) /* USB Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_RTC ((uint8_t)0x02U) /* RTC Alternate Function mapping */ /** * */ @@ -1095,9 +1095,9 @@ /* * Alternate function AF3 */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */ -#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /* EVENTOUT Alternate Function mapping */ /** * */ @@ -1105,12 +1105,12 @@ /* * Alternate function AF4 */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ -#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ -#define GPIO_AF4_LPUART1 ((uint8_t)0x04) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF4_TIM22 ((uint8_t)0x04) /* TIM22 Alternate Function mapping */ -#define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04U) /* USART1 Alternate Function mapping */ +#define GPIO_AF4_USART2 ((uint8_t)0x04U) /* USART2 Alternate Function mapping */ +#define GPIO_AF4_LPUART1 ((uint8_t)0x04U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF4_TIM22 ((uint8_t)0x04U) /* TIM22 Alternate Function mapping */ +#define GPIO_AF4_EVENTOUT ((uint8_t)0x04U) /* EVENTOUT Alternate Function mapping */ /** * */ @@ -1118,11 +1118,11 @@ /* * Alternate function AF5 */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ -#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */ -#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */ -#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */ -#define GPIO_AF5_TIM22 ((uint8_t)0x05) /* TIM22 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF5_TIM2 ((uint8_t)0x05U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF5_TIM21 ((uint8_t)0x05U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF5_TIM22 ((uint8_t)0x05U) /* TIM22 Alternate Function mapping */ /** * */ @@ -1130,9 +1130,9 @@ /* * Alternate function AF6 */ -#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */ -#define GPIO_AF6_TIM21 ((uint8_t)0x06) /* TIM21 Alternate Function mapping */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF6_TIM21 ((uint8_t)0x06U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /* EVENTOUT Alternate Function mapping */ /** * */ @@ -1140,8 +1140,8 @@ /* * Alternate function AF7 */ -#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */ -#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /* COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /* COMP2 Alternate Function mapping */ /** * */ @@ -1293,21 +1293,21 @@ /* * Alternate function AF0 */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */ -#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ -#define GPIO_AF0_LPUART1 ((uint8_t)0x00) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF0_USB ((uint8_t)0x00) /* USB Alternate Function mapping */ -#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF0_TSC ((uint8_t)0x00) /* TSC Alternate Function mapping */ -#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */ -#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */ -#define GPIO_AF0_TIM22 ((uint8_t)0x00) /* TIM22 Alternate Function mapping */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /* USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00U) /* USART2 Alternate Function mapping */ +#define GPIO_AF0_LPUART1 ((uint8_t)0x00U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF0_USB ((uint8_t)0x00U) /* USB Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_TSC ((uint8_t)0x00U) /* TSC Alternate Function mapping */ +#define GPIO_AF0_TIM2 ((uint8_t)0x00U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF0_TIM21 ((uint8_t)0x00U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF0_TIM22 ((uint8_t)0x00U) /* TIM22 Alternate Function mapping */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /* SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /* SWCLK Alternate Function mapping */ /** * */ @@ -1315,9 +1315,9 @@ /* * Alternate function AF1 */ -#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */ -#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /* I2C1 Alternate Function mapping */ /** * */ @@ -1325,13 +1325,13 @@ /** * Alternate function AF2 */ -#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */ -#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF2_USB ((uint8_t)0x02) /* USB Alternate Function mapping */ -#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC Alternate Function mapping */ +#define GPIO_AF2_SPI2 ((uint8_t)0x02U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF2_LPUART1 ((uint8_t)0x02U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02U) /* USB Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_RTC ((uint8_t)0x02U) /* RTC Alternate Function mapping */ /** * */ @@ -1339,9 +1339,9 @@ /* * Alternate function AF3 */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */ -#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /* EVENTOUT Alternate Function mapping */ /** * */ @@ -1349,12 +1349,12 @@ /* * Alternate function AF4 */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ -#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ -#define GPIO_AF4_LPUART1 ((uint8_t)0x04) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF4_TIM22 ((uint8_t)0x04) /* TIM22 Alternate Function mapping */ -#define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04U) /* USART1 Alternate Function mapping */ +#define GPIO_AF4_USART2 ((uint8_t)0x04U) /* USART2 Alternate Function mapping */ +#define GPIO_AF4_LPUART1 ((uint8_t)0x04U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF4_TIM22 ((uint8_t)0x04U) /* TIM22 Alternate Function mapping */ +#define GPIO_AF4_EVENTOUT ((uint8_t)0x04U) /* EVENTOUT Alternate Function mapping */ /** * */ @@ -1362,11 +1362,11 @@ /* * Alternate function AF5 */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ -#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */ -#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */ -#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */ -#define GPIO_AF5_TIM22 ((uint8_t)0x05) /* TIM22 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF5_TIM2 ((uint8_t)0x05U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF5_TIM21 ((uint8_t)0x05U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF5_TIM22 ((uint8_t)0x05U) /* TIM22 Alternate Function mapping */ /** * */ @@ -1374,9 +1374,9 @@ /* * Alternate function AF6 */ -#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */ -#define GPIO_AF6_TIM21 ((uint8_t)0x06) /* TIM21 Alternate Function mapping */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF6_TIM21 ((uint8_t)0x06U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /* EVENTOUT Alternate Function mapping */ /** * */ @@ -1384,8 +1384,8 @@ /* * Alternate function AF7 */ -#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */ -#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /* COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /* COMP2 Alternate Function mapping */ /** * */ @@ -1531,19 +1531,19 @@ /* * Alternate function AF0 */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */ -#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ -#define GPIO_AF0_LPUART1 ((uint8_t)0x00) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */ -#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */ -#define GPIO_AF0_TIM22 ((uint8_t)0x00) /* TIM22 Alternate Function mapping */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /* USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00U) /* USART2 Alternate Function mapping */ +#define GPIO_AF0_LPUART1 ((uint8_t)0x00U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM2 ((uint8_t)0x00U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF0_TIM21 ((uint8_t)0x00U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF0_TIM22 ((uint8_t)0x00U) /* TIM22 Alternate Function mapping */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /* SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /* SWCLK Alternate Function mapping */ /** * */ @@ -1551,9 +1551,9 @@ /* * Alternate function AF1 */ -#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */ -#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /* I2C1 Alternate Function mapping */ /** * */ @@ -1561,13 +1561,13 @@ /* * Alternate function AF2 */ -#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */ -#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF2_USB ((uint8_t)0x02) /* USB Alternate Function mapping */ -#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC Alternate Function mapping */ +#define GPIO_AF2_SPI2 ((uint8_t)0x02U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF2_LPUART1 ((uint8_t)0x02U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02U) /* USB Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_RTC ((uint8_t)0x02U) /* RTC Alternate Function mapping */ /** * */ @@ -1575,8 +1575,8 @@ /* * Alternate function AF3 */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /* EVENTOUT Alternate Function mapping */ /** * */ @@ -1584,12 +1584,12 @@ /* * Alternate function AF4 */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ -#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ -#define GPIO_AF4_LPUART1 ((uint8_t)0x04) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF4_TIM22 ((uint8_t)0x04) /* TIM22 Alternate Function mapping */ -#define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04U) /* USART1 Alternate Function mapping */ +#define GPIO_AF4_USART2 ((uint8_t)0x04U) /* USART2 Alternate Function mapping */ +#define GPIO_AF4_LPUART1 ((uint8_t)0x04U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF4_TIM22 ((uint8_t)0x04U) /* TIM22 Alternate Function mapping */ +#define GPIO_AF4_EVENTOUT ((uint8_t)0x04U) /* EVENTOUT Alternate Function mapping */ /** * */ @@ -1597,11 +1597,11 @@ /* * Alternate function AF5 */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ -#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */ -#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */ -#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */ -#define GPIO_AF5_TIM22 ((uint8_t)0x05) /* TIM22 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF5_TIM2 ((uint8_t)0x05U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF5_TIM21 ((uint8_t)0x05U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF5_TIM22 ((uint8_t)0x05U) /* TIM22 Alternate Function mapping */ /** * */ @@ -1609,9 +1609,9 @@ /* * Alternate function AF6 */ -#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */ -#define GPIO_AF6_TIM21 ((uint8_t)0x06) /* TIM21 Alternate Function mapping */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF6_TIM21 ((uint8_t)0x06U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /* EVENTOUT Alternate Function mapping */ /** * */ @@ -1619,8 +1619,8 @@ /* * Alternate function AF7 */ -#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */ -#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /* COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /* COMP2 Alternate Function mapping */ /** * */ @@ -1749,14 +1749,14 @@ /* * Alternate function AF0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ -#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ -#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_TIM21 ((uint8_t)0x00U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00U) /* USART2 Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /* SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /* SWCLK Alternate Function mapping */ /** * */ @@ -1764,9 +1764,9 @@ /* * Alternate function AF1 */ -#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ -#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01U) /* LPTIM1 Alternate Function mapping */ /** * */ @@ -1774,11 +1774,11 @@ /* * Alternate function AF2 */ -#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_MCO ((uint8_t)0x02) /* MCO Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_MCO ((uint8_t)0x02U) /* MCO Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_RTC ((uint8_t)0x02U) /* RTC Alternate Function mapping */ /** * */ @@ -1786,8 +1786,8 @@ /* * Alternate function AF3 */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /* EVENTOUT Alternate Function mapping */ /** * */ @@ -1795,11 +1795,11 @@ /* * Alternate function AF4 */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ -#define GPIO_AF4_LPUART1 ((uint8_t)0x04) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF4_TIM22 ((uint8_t)0x04) /* TIM22 Alternate Function mapping */ -#define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_USART2 ((uint8_t)0x04U) /* USART2 Alternate Function mapping */ +#define GPIO_AF4_LPUART1 ((uint8_t)0x04U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF4_TIM22 ((uint8_t)0x04U) /* TIM22 Alternate Function mapping */ +#define GPIO_AF4_EVENTOUT ((uint8_t)0x04U) /* EVENTOUT Alternate Function mapping */ /** * */ @@ -1807,9 +1807,9 @@ /* * Alternate function AF5 */ -#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */ -#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */ -#define GPIO_AF5_TIM22 ((uint8_t)0x05) /* TIM22 Alternate Function mapping */ +#define GPIO_AF5_TIM2 ((uint8_t)0x05U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF5_TIM21 ((uint8_t)0x05U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF5_TIM22 ((uint8_t)0x05U) /* TIM22 Alternate Function mapping */ /** * */ @@ -1817,8 +1817,8 @@ /* * Alternate function AF6 */ -#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF6_LPUART1 ((uint8_t)0x06U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /* EVENTOUT Alternate Function mapping */ /** * */ @@ -1826,8 +1826,8 @@ /* * Alternate function AF7 */ -#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */ -#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /* COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /* COMP2 Alternate Function mapping */ /** * */ @@ -1956,13 +1956,13 @@ /* * Alternate function AF0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ -#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_TIM21 ((uint8_t)0x00U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00U) /* USART2 Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /* SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /* SWCLK Alternate Function mapping */ /** * */ @@ -1970,9 +1970,9 @@ /* * Alternate function AF1 */ -#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ -#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01U) /* LPTIM1 Alternate Function mapping */ /** * */ @@ -1980,10 +1980,10 @@ /* Alternate function AF2 * */ -#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_RTC ((uint8_t)0x02U) /* RTC Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /* EVENTOUT Alternate Function mapping */ /** * */ @@ -1991,8 +1991,8 @@ /* * Alternate function AF3 */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /* EVENTOUT Alternate Function mapping */ /** * */ @@ -2000,10 +2000,10 @@ /* * Alternate function AF4 */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ -#define GPIO_AF4_LPUART1 ((uint8_t)0x04) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_USART2 ((uint8_t)0x04U) /* USART2 Alternate Function mapping */ +#define GPIO_AF4_LPUART1 ((uint8_t)0x04U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF4_EVENTOUT ((uint8_t)0x04U) /* EVENTOUT Alternate Function mapping */ /** * */ @@ -2011,9 +2011,9 @@ /* * Alternate function AF5 */ -#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */ -#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_TIM2 ((uint8_t)0x05U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF5_TIM21 ((uint8_t)0x05U) /* TIM21 Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ /** * */ @@ -2021,8 +2021,8 @@ /* * Alternate function AF6 */ -#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF6_LPUART1 ((uint8_t)0x06U) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /* EVENTOUT Alternate Function mapping */ /** * */ @@ -2030,8 +2030,8 @@ /* * Alternate function AF7 */ -#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */ -#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /* COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /* COMP2 Alternate Function mapping */ /** * */ @@ -2139,12 +2139,12 @@ ((__GPIOx__) == (GPIOH))? 5U : 6U) #define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \ - ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE)))) + ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE)))) /** * @} */ @@ -2178,10 +2178,10 @@ #define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \ - ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE)))) + ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE)))) /** * @} @@ -2217,9 +2217,9 @@ #define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \ - ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE)))) + ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE)))) /** * @} */ @@ -2255,11 +2255,11 @@ ((__GPIOx__) == (GPIOH))? 5U : 6U) #define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \ - ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE)))) + ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0U) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE)))) /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.c index d91f9b29c6..d521d645fc 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_i2c.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief I2C HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: @@ -197,16 +197,16 @@ /** @addtogroup I2C_Private * @{ */ -#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*Instance->OAR1 &= ~I2C_OAR1_OA1EN; - if(hi2c->Init.OwnAddress1 != 0) + if(hi2c->Init.OwnAddress1 != 0U) { if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) { @@ -507,15 +507,11 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t sizetmp = 0; + uint32_t sizetmp = 0U; if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; @@ -530,10 +526,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Send Slave Address */ /* Set NBYTES to write and reload if size > 255 and generate RESTART */ /* Size > 255, need to set RELOAD bit */ - if(Size > 255) + if(Size > 255U) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - sizetmp = 255; + I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + sizetmp = 255U; } else { @@ -560,7 +556,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA sizetmp--; Size--; - if((sizetmp == 0)&&(Size!=0)) + if((sizetmp == 0U)&&(Size!=0U)) { /* Wait until TCR flag is set */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) @@ -568,10 +564,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA return HAL_TIMEOUT; } - if(Size > 255) + if(Size > 255U) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - sizetmp = 255; + I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + sizetmp = 255U; } else { @@ -580,7 +576,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA } } - }while(Size > 0); + }while(Size > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ @@ -627,15 +623,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA */ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t sizetmp = 0; + uint32_t sizetmp = 0U; if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - + { if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; @@ -650,10 +641,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Send Slave Address */ /* Set NBYTES to write and reload if size > 255 and generate RESTART */ /* Size > 255, need to set RELOAD bit */ - if(Size > 255) + if(Size > 255U) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - sizetmp = 255; + I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + sizetmp = 255U; } else { @@ -681,7 +672,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd sizetmp--; Size--; - if((sizetmp == 0)&&(Size!=0)) + if((sizetmp == 0U)&&(Size!=0U)) { /* Wait until TCR flag is set */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) @@ -689,10 +680,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd return HAL_TIMEOUT; } - if(Size > 255) + if(Size > 255U) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - sizetmp = 255; + I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + sizetmp = 255U; } else { @@ -701,7 +692,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd } } - }while(Size > 0); + }while(Size > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ @@ -749,7 +740,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -818,7 +809,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData /* Read data from TXDR */ hi2c->Instance->TXDR = (*pData++); Size--; - }while(Size > 0); + }while(Size > 0U); /* Wait until STOP flag is set */ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) @@ -878,7 +869,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -911,7 +902,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, return HAL_TIMEOUT; } - while(Size > 0) + while(Size > 0U) { /* Wait until RXNE flag is set */ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) @@ -998,7 +989,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1016,9 +1007,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->pBuffPtr = pData; hi2c->XferCount = Size; - if(Size > 255) + if(Size > 255U) { - hi2c->XferSize = 255; + hi2c->XferSize = 255U; } else { @@ -1027,7 +1018,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Send Slave Address */ /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) ) { I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); } @@ -1070,7 +1061,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1088,9 +1079,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De hi2c->pBuffPtr = pData; hi2c->XferCount = Size; - if(Size > 255) + if(Size > 255U) { - hi2c->XferSize = 255; + hi2c->XferSize = 255U; } else { @@ -1099,7 +1090,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Send Slave Address */ /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) ) { I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } @@ -1140,7 +1131,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1190,7 +1181,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1241,7 +1232,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1259,9 +1250,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t hi2c->pBuffPtr = pData; hi2c->XferCount = Size; - if(Size > 255) + if(Size > 255U) { - hi2c->XferSize = 255; + hi2c->XferSize = 255U; } else { @@ -1279,7 +1270,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Send Slave Address */ /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) ) { I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); } @@ -1335,7 +1326,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1353,9 +1344,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->pBuffPtr = pData; hi2c->XferCount = Size; - if(Size > 255) + if(Size > 255U) { - hi2c->XferSize = 255; + hi2c->XferSize = 255U; } else { @@ -1373,7 +1364,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Send Slave Address */ /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) ) { I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } @@ -1424,7 +1415,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1510,7 +1501,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1583,14 +1574,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD */ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t Sizetmp = 0; + uint32_t Sizetmp = 0U; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1625,10 +1616,10 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Set NBYTES to write and reload if size > 255 */ /* Size > 255, need to set RELOAD bit */ - if(Size > 255) + if(Size > 255U) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - Sizetmp = 255; + I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + Sizetmp = 255U; } else { @@ -1656,7 +1647,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress Sizetmp--; Size--; - if((Sizetmp == 0)&&(Size!=0)) + if((Sizetmp == 0U)&&(Size!=0U)) { /* Wait until TCR flag is set */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) @@ -1665,10 +1656,10 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } - if(Size > 255) + if(Size > 255U) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - Sizetmp = 255; + I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + Sizetmp = 255U; } else { @@ -1677,7 +1668,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } } - }while(Size > 0); + }while(Size > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ @@ -1726,14 +1717,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress */ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t Sizetmp = 0; + uint32_t Sizetmp = 0U; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1769,10 +1760,10 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Send Slave Address */ /* Set NBYTES to write and reload if size > 255 and generate RESTART */ /* Size > 255, need to set RELOAD bit */ - if(Size > 255) + if(Size > 255U) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - Sizetmp = 255; + I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + Sizetmp = 255U; } else { @@ -1795,7 +1786,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, Sizetmp--; Size--; - if((Sizetmp == 0)&&(Size!=0)) + if((Sizetmp == 0U)&&(Size!=0U)) { /* Wait until TCR flag is set */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) @@ -1803,10 +1794,10 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, return HAL_TIMEOUT; } - if(Size > 255) + if(Size > 255U) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - Sizetmp = 255; + I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + Sizetmp = 255U; } else { @@ -1815,7 +1806,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, } } - }while(Size > 0); + }while(Size > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ @@ -1868,7 +1859,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1886,9 +1877,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->pBuffPtr = pData; hi2c->XferCount = Size; - if(Size > 255) + if(Size > 255U) { - hi2c->XferSize = 255; + hi2c->XferSize = 255U; } else { @@ -1914,7 +1905,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Set NBYTES to write and reload if size > 255 */ /* Size > 255, need to set RELOAD bit */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) ) { I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } @@ -1961,7 +1952,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1978,9 +1969,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre hi2c->pBuffPtr = pData; hi2c->XferCount = Size; - if(Size > 255) + if(Size > 255U) { - hi2c->XferSize = 255; + hi2c->XferSize = 255U; } else { @@ -2006,7 +1997,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Set NBYTES to write and reload if size > 255 and generate RESTART */ /* Size > 255, need to set RELOAD bit */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) ) { I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } @@ -2053,7 +2044,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -2071,9 +2062,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->pBuffPtr = pData; hi2c->XferCount = Size; - if(Size > 255) + if(Size > 255U) { - hi2c->XferSize = 255; + hi2c->XferSize = 255U; } else { @@ -2108,7 +2099,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Send Slave Address */ /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) ) { I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } @@ -2162,7 +2153,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -2179,9 +2170,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->pBuffPtr = pData; hi2c->XferCount = Size; - if(Size > 255) + if(Size > 255U) { - hi2c->XferSize = 255; + hi2c->XferSize = 255U; } else { @@ -2215,7 +2206,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) ) { I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } @@ -2256,9 +2247,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr */ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; - __IO uint32_t I2C_Trials = 0; + __IO uint32_t I2C_Trials = 0U; if(hi2c->State == HAL_I2C_STATE_READY) { @@ -2285,7 +2276,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Device is ready */ hi2c->State = HAL_I2C_STATE_READY; @@ -2645,14 +2636,14 @@ static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c) } else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) { - if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0)) + if((hi2c->XferSize == 0U)&&(hi2c->XferCount!=0U)) { DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - if(hi2c->XferCount > 255) + if(hi2c->XferCount > 255U) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - hi2c->XferSize = 255; + I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + hi2c->XferSize = 255U; } else { @@ -2672,7 +2663,7 @@ static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c) } else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) { - if(hi2c->XferCount == 0) + if(hi2c->XferCount == 0U) { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; @@ -2783,14 +2774,14 @@ static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c) } else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) { - if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0)) + if((hi2c->XferSize == 0U)&&(hi2c->XferCount!=0U)) { DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - if(hi2c->XferCount > 255) + if(hi2c->XferCount > 255U) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - hi2c->XferSize = 255; + I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + hi2c->XferSize = 255U; } else { @@ -2810,7 +2801,7 @@ static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c) } else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) { - if(hi2c->XferCount == 0) + if(hi2c->XferCount == 0U) { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; @@ -2911,7 +2902,7 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c) /* if yes, normal usecase, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ - if(hi2c->XferCount == 0) + if(hi2c->XferCount == 0U) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -2966,7 +2957,7 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ - if(hi2c->XferCount > 0) + if(hi2c->XferCount > 0U) { /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); @@ -3181,7 +3172,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) /* Check if last DMA request was done with RELOAD */ /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) ) { /* Wait until TCR flag is set */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) @@ -3215,7 +3206,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) /* Clear Configuration Register 2 */ __I2C_RESET_CR2(hi2c); - hi2c->XferCount = 0; + hi2c->XferCount = 0U; hi2c->State = HAL_I2C_STATE_READY; HAL_I2C_ErrorCallback(hi2c); @@ -3224,9 +3215,9 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { hi2c->pBuffPtr += hi2c->XferSize; hi2c->XferCount -= hi2c->XferSize; - if(hi2c->XferCount > 255) + if(hi2c->XferCount > 255U) { - hi2c->XferSize = 255; + hi2c->XferSize = 255U; } else { @@ -3240,7 +3231,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) /* Send Slave Address */ /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) ) { I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } @@ -3272,7 +3263,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) /* Clear Configuration Register 2 */ __I2C_RESET_CR2(hi2c); - hi2c->XferCount = 0; + hi2c->XferCount = 0U; hi2c->State = HAL_I2C_STATE_READY; HAL_I2C_ErrorCallback(hi2c); @@ -3309,7 +3300,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - hi2c->XferCount = 0; + hi2c->XferCount = 0U; hi2c->State = HAL_I2C_STATE_READY; @@ -3361,7 +3352,7 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - hi2c->XferCount = 0; + hi2c->XferCount = 0U; hi2c->State = HAL_I2C_STATE_READY; @@ -3388,7 +3379,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) /* Check if last DMA request was done with RELOAD */ /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) ) { /* Wait until TCR flag is set */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) @@ -3422,7 +3413,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) /* Clear Configuration Register 2 */ __I2C_RESET_CR2(hi2c); - hi2c->XferCount = 0; + hi2c->XferCount = 0U; hi2c->State = HAL_I2C_STATE_READY; HAL_I2C_ErrorCallback(hi2c); @@ -3431,9 +3422,9 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { hi2c->pBuffPtr += hi2c->XferSize; hi2c->XferCount -= hi2c->XferSize; - if(hi2c->XferCount > 255) + if(hi2c->XferCount > 255U) { - hi2c->XferSize = 255; + hi2c->XferSize = 255U; } else { @@ -3447,7 +3438,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) /* Send Slave Address */ /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) ) { I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } @@ -3485,7 +3476,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) /* Clear Configuration Register 2 */ __I2C_RESET_CR2(hi2c); - hi2c->XferCount = 0; + hi2c->XferCount = 0U; hi2c->State = HAL_I2C_STATE_READY; @@ -3523,7 +3514,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - hi2c->XferCount = 0; + hi2c->XferCount = 0U; hi2c->State = HAL_I2C_STATE_READY; @@ -3576,7 +3567,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - hi2c->XferCount = 0; + hi2c->XferCount = 0U; hi2c->State = HAL_I2C_STATE_READY; @@ -3603,7 +3594,7 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) /* Check if last DMA request was done with RELOAD */ /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) ) { /* Wait until TCR flag is set */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) @@ -3637,7 +3628,7 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) /* Clear Configuration Register 2 */ __I2C_RESET_CR2(hi2c); - hi2c->XferCount = 0; + hi2c->XferCount = 0U; hi2c->State = HAL_I2C_STATE_READY; HAL_I2C_ErrorCallback(hi2c); @@ -3646,9 +3637,9 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) { hi2c->pBuffPtr += hi2c->XferSize; hi2c->XferCount -= hi2c->XferSize; - if(hi2c->XferCount > 255) + if(hi2c->XferCount > 255U) { - hi2c->XferSize = 255; + hi2c->XferSize = 255U; } else { @@ -3662,7 +3653,7 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) /* Send Slave Address */ /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) ) { I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } @@ -3694,7 +3685,7 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) /* Clear Configuration Register 2 */ __I2C_RESET_CR2(hi2c); - hi2c->XferCount = 0; + hi2c->XferCount = 0U; hi2c->State = HAL_I2C_STATE_READY; HAL_I2C_ErrorCallback(hi2c); @@ -3731,7 +3722,7 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - hi2c->XferCount = 0; + hi2c->XferCount = 0U; hi2c->State = HAL_I2C_STATE_READY; @@ -3759,7 +3750,7 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) /* Check if last DMA request was done with RELOAD */ /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) ) { /* Wait until TCR flag is set */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) @@ -3793,7 +3784,7 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) /* Clear Configuration Register 2 */ __I2C_RESET_CR2(hi2c); - hi2c->XferCount = 0; + hi2c->XferCount = 0U; hi2c->State = HAL_I2C_STATE_READY; HAL_I2C_ErrorCallback(hi2c); @@ -3802,9 +3793,9 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) { hi2c->pBuffPtr += hi2c->XferSize; hi2c->XferCount -= hi2c->XferSize; - if(hi2c->XferCount > 255) + if(hi2c->XferCount > 255U) { - hi2c->XferSize = 255; + hi2c->XferSize = 255U; } else { @@ -3818,7 +3809,7 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) /* Send Slave Address */ /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) ) { I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } @@ -3856,7 +3847,7 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) /* Clear Configuration Register 2 */ __I2C_RESET_CR2(hi2c); - hi2c->XferCount = 0; + hi2c->XferCount = 0U; hi2c->State = HAL_I2C_STATE_READY; HAL_I2C_ErrorCallback(hi2c); @@ -3893,7 +3884,7 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - hi2c->XferCount = 0; + hi2c->XferCount = 0U; hi2c->State = HAL_I2C_STATE_READY; @@ -3921,7 +3912,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - hi2c->XferCount = 0; + hi2c->XferCount = 0U; hi2c->State = HAL_I2C_STATE_READY; @@ -3951,7 +3942,7 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hi2c->State= HAL_I2C_STATE_READY; /* Process Unlocked */ @@ -3968,7 +3959,7 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hi2c->State= HAL_I2C_STATE_READY; /* Process Unlocked */ @@ -4003,7 +3994,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State= HAL_I2C_STATE_READY; @@ -4027,7 +4018,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, */ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) { - uint32_t tickstart = 0x00; + uint32_t tickstart = 0x00U; tickstart = HAL_GetTick(); while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) @@ -4039,7 +4030,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } /* Check for the Timeout */ - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State= HAL_I2C_STATE_READY; @@ -4062,7 +4053,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, */ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) { - uint32_t tickstart = 0x00; + uint32_t tickstart = 0x00U; tickstart = HAL_GetTick(); while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) @@ -4091,7 +4082,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } /* Check for the Timeout */ - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State= HAL_I2C_STATE_READY; @@ -4114,7 +4105,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, */ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout) { - uint32_t tickstart = 0x00; + uint32_t tickstart = 0x00U; tickstart = HAL_GetTick(); if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) @@ -4139,7 +4130,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hi2c->State= HAL_I2C_STATE_READY; /* Process Unlocked */ @@ -4195,7 +4186,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); @@ -4209,7 +4200,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \ + tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U ) & I2C_CR2_NBYTES) | \ (uint32_t)Mode | (uint32_t)Request); /* update CR2 register */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.h index 97a70c1481..4d13726bb6 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_i2c.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention @@ -103,17 +103,17 @@ typedef struct typedef enum { - HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */ - HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */ - HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */ - HAL_I2C_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */ - HAL_I2C_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */ - HAL_I2C_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */ - HAL_I2C_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */ - HAL_I2C_STATE_MEM_BUSY_TX = 0x52, /*!< Memory Data Transmission process is ongoing */ - HAL_I2C_STATE_MEM_BUSY_RX = 0x62, /*!< Memory Data Reception process is ongoing */ - HAL_I2C_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ + HAL_I2C_STATE_RESET = 0x00U, /*!< I2C not yet initialized or disabled */ + HAL_I2C_STATE_READY = 0x01U, /*!< I2C initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x02U, /*!< I2C internal process is ongoing */ + HAL_I2C_STATE_MASTER_BUSY_TX = 0x12U, /*!< Master Data Transmission process is ongoing */ + HAL_I2C_STATE_MASTER_BUSY_RX = 0x22U, /*!< Master Data Reception process is ongoing */ + HAL_I2C_STATE_SLAVE_BUSY_TX = 0x32U, /*!< Slave Data Transmission process is ongoing */ + HAL_I2C_STATE_SLAVE_BUSY_RX = 0x42U, /*!< Slave Data Reception process is ongoing */ + HAL_I2C_STATE_MEM_BUSY_TX = 0x52U, /*!< Memory Data Transmission process is ongoing */ + HAL_I2C_STATE_MEM_BUSY_RX = 0x62U, /*!< Memory Data Reception process is ongoing */ + HAL_I2C_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ }HAL_I2C_StateTypeDef; /** @@ -124,14 +124,14 @@ typedef enum * @brief I2C Error Code * @{ */ -#define HAL_I2C_ERROR_NONE 0x00 /*!< No error */ -#define HAL_I2C_ERROR_BERR 0x01 /*!< BERR error */ -#define HAL_I2C_ERROR_ARLO 0x02 /*!< ARLO error */ -#define HAL_I2C_ERROR_AF 0x04 /*!< ACKF error */ -#define HAL_I2C_ERROR_OVR 0x08 /*!< OVR error */ -#define HAL_I2C_ERROR_DMA 0x10 /*!< DMA transfer error */ -#define HAL_I2C_ERROR_TIMEOUT 0x20 /*!< Timeout error */ -#define HAL_I2C_ERROR_SIZE 0x40 /*!< Size Management error */ +#define HAL_I2C_ERROR_NONE 0x00U /*!< No error */ +#define HAL_I2C_ERROR_BERR 0x01U /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO 0x02U /*!< ARLO error */ +#define HAL_I2C_ERROR_AF 0x04U /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR 0x08U /*!< OVR error */ +#define HAL_I2C_ERROR_DMA 0x10U /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT 0x20U /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE 0x40U /*!< Size Management error */ /** * @} */ @@ -179,8 +179,8 @@ typedef struct /** @defgroup I2C_addressing_mode I2C addressing mode * @{ */ -#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001) -#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002) +#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002U) /** * @} */ @@ -188,7 +188,7 @@ typedef struct /** @defgroup I2C_dual_addressing_mode I2C dual addressing mode * @{ */ -#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000) +#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U) #define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN /** * @} @@ -197,14 +197,14 @@ typedef struct /** @defgroup I2C_own_address2_masks I2C own address2 masks * @{ */ -#define I2C_OA2_NOMASK ((uint8_t)0x00) -#define I2C_OA2_MASK01 ((uint8_t)0x01) -#define I2C_OA2_MASK02 ((uint8_t)0x02) -#define I2C_OA2_MASK03 ((uint8_t)0x03) -#define I2C_OA2_MASK04 ((uint8_t)0x04) -#define I2C_OA2_MASK05 ((uint8_t)0x05) -#define I2C_OA2_MASK06 ((uint8_t)0x06) -#define I2C_OA2_MASK07 ((uint8_t)0x07) +#define I2C_OA2_NOMASK ((uint8_t)0x00U) +#define I2C_OA2_MASK01 ((uint8_t)0x01U) +#define I2C_OA2_MASK02 ((uint8_t)0x02U) +#define I2C_OA2_MASK03 ((uint8_t)0x03U) +#define I2C_OA2_MASK04 ((uint8_t)0x04U) +#define I2C_OA2_MASK05 ((uint8_t)0x05U) +#define I2C_OA2_MASK06 ((uint8_t)0x06U) +#define I2C_OA2_MASK07 ((uint8_t)0x07U) /** * @} */ @@ -212,7 +212,7 @@ typedef struct /** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode * @{ */ -#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000) +#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U) #define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN /** * @} @@ -221,7 +221,7 @@ typedef struct /** @defgroup I2C_nostretch_mode I2C nostretch mode * @{ */ -#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000) +#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U) #define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH /** * @} @@ -230,8 +230,8 @@ typedef struct /** @defgroup I2C_Memory_Address_Size I2C Memory Address Size * @{ */ -#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001) -#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002) +#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U) +#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002U) /** * @} */ @@ -241,7 +241,7 @@ typedef struct */ #define I2C_RELOAD_MODE I2C_CR2_RELOAD #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND -#define I2C_SOFTEND_MODE ((uint32_t)0x00000000) +#define I2C_SOFTEND_MODE ((uint32_t)0x00000000U) /** * @} */ @@ -249,7 +249,7 @@ typedef struct /** @defgroup I2C_StartStopMode_definition I2C StartStopMode definition * @{ */ -#define I2C_NO_STARTSTOP ((uint32_t)0x00000000) +#define I2C_NO_STARTSTOP ((uint32_t)0x00000000U) #define I2C_GENERATE_STOP I2C_CR2_STOP #define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) #define I2C_GENERATE_START_WRITE I2C_CR2_START @@ -469,11 +469,11 @@ typedef struct #define __I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FFU) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) -#define __I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) -#define __I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) +#define __I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8))) +#define __I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) #define __I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c_ex.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c_ex.c index 512a2e6e91..61f7e60033 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_i2c_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief I2C Extended HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2C Extended peripheral: @@ -153,7 +153,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); @@ -180,7 +180,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ tmpreg &= ~(I2C_CR1_DNF); /* Set I2Cx DNF coefficient */ - tmpreg |= DigitalFilter << 8; + tmpreg |= DigitalFilter << 8U; /* Store the new register value */ hi2c->Instance->CR1 = tmpreg; @@ -204,7 +204,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c) { /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX)) @@ -243,7 +243,7 @@ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c) HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c) { /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX)) diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c_ex.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c_ex.h index 66bb42c992..ffca458bd0 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of I2C HAL Extension module. ****************************************************************************** * @attention @@ -64,7 +64,7 @@ /** @defgroup I2CEx_Analog_Filter I2C Analog Filter Enabling * @{ */ -#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000) +#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U) #define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /** * @} @@ -124,7 +124,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ ((FILTER) == I2C_ANALOGFILTER_DISABLE)) -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) #if defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L011xx) || defined(STM32L021xx) #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.c index 1c98566321..c1c3fad6fc 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_i2s.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral: @@ -214,8 +214,8 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, */ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) { - uint32_t i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0, i2sclk = 0, tmpreg = 0; + uint32_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U; + uint32_t tmp = 0U, i2sclk = 0U, tmpreg = 0U; /* Check the I2S handle allocation */ if(hi2s == NULL) @@ -246,8 +246,8 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT) { - i2sodd = (uint32_t)0; - i2sdiv = (uint32_t)2; + i2sodd = (uint32_t)0U; + i2sdiv = (uint32_t)2U; } /* If the requested audio frequency is not the default, compute the prescaler */ else @@ -256,12 +256,12 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) { /* Packet length is 16 bits */ - packetlength = 1; + packetlength = 1U; } else { /* Packet length is 32 bits */ - packetlength = 2; + packetlength = 2U; } /* Get the source clock value: based on System Clock value */ @@ -271,33 +271,33 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) { /* MCLK output is enabled */ - tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5); + tmp = (uint32_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U); } else { /* MCLK output is disabled */ - tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5); + tmp = (uint32_t)(((((i2sclk / (32U * packetlength)) *10U ) / hi2s->Init.AudioFreq)) + 5U); } /* Remove the flatting point */ - tmp = tmp / 10; + tmp = tmp / 10U; /* Check the parity of the divider */ - i2sodd = (uint32_t)(tmp & (uint32_t)1); + i2sodd = (uint32_t)(tmp & (uint32_t)1U); /* Compute the i2sdiv prescaler */ - i2sdiv = (uint32_t)((tmp - i2sodd) / 2); + i2sdiv = (uint32_t)((tmp - i2sodd) / 2U); /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint32_t) (i2sodd << 8); + i2sodd = (uint32_t) (i2sodd << 8U); } /* Test if the divider is 1 or 0 or greater than 0xFF */ - if((i2sdiv < 2) || (i2sdiv > 0xFF)) + if((i2sdiv < 2U) || (i2sdiv > 0xFFU)) { /* Set the default values */ - i2sdiv = 2; - i2sodd = 0; + i2sdiv = 2U; + i2sodd = 0U; } /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/ @@ -467,7 +467,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) */ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -480,8 +480,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->TxXferSize = (Size << 1); - hi2s->TxXferCount = (Size << 1); + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); } else { @@ -501,7 +501,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin __HAL_I2S_ENABLE(hi2s); } - while(hi2s->TxXferCount > 0) + while(hi2s->TxXferCount > 0U) { /* Wait until TXE flag is set */ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK) @@ -562,7 +562,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin */ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -575,8 +575,8 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->RxXferSize = (Size << 1); - hi2s->RxXferCount = (Size << 1); + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); } else { @@ -605,7 +605,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint } /* Receive data */ - while(hi2s->RxXferCount > 0) + while(hi2s->RxXferCount > 0U) { /* Wait until RXNE flag is set */ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK) @@ -649,7 +649,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint */ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -666,8 +666,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->TxXferSize = (Size << 1); - hi2s->TxXferCount = (Size << 1); + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); } else { @@ -717,7 +717,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, */ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -734,8 +734,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->RxXferSize = (Size << 1); - hi2s->RxXferCount = (Size << 1); + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); } else { @@ -782,7 +782,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u */ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -799,8 +799,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->TxXferSize = (Size << 1); - hi2s->TxXferCount = (Size << 1); + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); } else { @@ -863,7 +863,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, */ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -880,8 +880,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->RxXferSize = (Size << 1); - hi2s->RxXferCount = (Size << 1); + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); } else { @@ -1243,7 +1243,7 @@ static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) /* Disable Tx DMA Request */ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - hi2s->TxXferCount = 0; + hi2s->TxXferCount = 0U; hi2s->State = HAL_I2S_STATE_READY; } HAL_I2S_TxCpltCallback(hi2s); @@ -1276,7 +1276,7 @@ static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) { /* Disable Rx DMA Request */ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - hi2s->RxXferCount = 0; + hi2s->RxXferCount = 0U; hi2s->State = HAL_I2S_STATE_READY; } HAL_I2S_RxCpltCallback(hi2s); @@ -1307,8 +1307,8 @@ static void I2S_DMAError(DMA_HandleTypeDef *hdma) /* Disable Rx and Tx DMA Request */ CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); - hi2s->TxXferCount = 0; - hi2s->RxXferCount = 0; + hi2s->TxXferCount = 0U; + hi2s->RxXferCount = 0U; hi2s->State= HAL_I2S_STATE_READY; @@ -1329,7 +1329,7 @@ static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); hi2s->TxXferCount--; - if(hi2s->TxXferCount == 0) + if(hi2s->TxXferCount == 0U) { /* Disable TXE and ERR interrupt */ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); @@ -1350,7 +1350,7 @@ static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; hi2s->RxXferCount--; - if(hi2s->RxXferCount == 0) + if(hi2s->RxXferCount == 0U) { /* Disable RXNE and ERR interrupt */ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); @@ -1372,7 +1372,7 @@ static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) */ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Get tick */ tickstart = HAL_GetTick(); @@ -1384,7 +1384,7 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Set the I2S State ready */ hi2s->State= HAL_I2S_STATE_READY; @@ -1403,7 +1403,7 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Set the I2S State ready */ hi2s->State= HAL_I2S_STATE_READY; diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.h index b891315c7e..e8a0004e1c 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_i2s.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention @@ -90,13 +90,13 @@ typedef struct */ typedef enum { - HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */ - HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */ - HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */ - HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S timeout state */ - HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */ + HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */ + HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */ + HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */ + HAL_I2S_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_I2S_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2S_STATE_TIMEOUT = 0x03U, /*!< I2S timeout state */ + HAL_I2S_STATE_ERROR = 0x04U /*!< I2S error state */ }HAL_I2S_StateTypeDef; /** @@ -149,11 +149,11 @@ typedef struct * @defgroup I2S_ErrorCode I2S Error Code * @{ */ -#define HAL_I2S_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_I2S_ERROR_UDR ((uint32_t)0x01) /*!< I2S Underrun error */ -#define HAL_I2S_ERROR_OVR ((uint32_t)0x02) /*!< I2S Overrun error */ -#define HAL_I2S_ERROR_FRE ((uint32_t)0x04) /*!< I2S Frame format error */ -#define HAL_I2S_ERROR_DMA ((uint32_t)0x08) /*!< DMA transfer error */ +#define HAL_I2S_ERROR_NONE ((uint32_t)0x00U) /*!< No error */ +#define HAL_I2S_ERROR_UDR ((uint32_t)0x01U) /*!< I2S Underrun error */ +#define HAL_I2S_ERROR_OVR ((uint32_t)0x02U) /*!< I2S Overrun error */ +#define HAL_I2S_ERROR_FRE ((uint32_t)0x04U) /*!< I2S Frame format error */ +#define HAL_I2S_ERROR_DMA ((uint32_t)0x08U) /*!< DMA transfer error */ /** * @} */ @@ -161,7 +161,7 @@ typedef struct /** @defgroup I2S_Mode I2S Mode * @{ */ -#define I2S_MODE_SLAVE_TX ((uint32_t) 0x00000000) +#define I2S_MODE_SLAVE_TX ((uint32_t) 0x00000000U) #define I2S_MODE_SLAVE_RX ((uint32_t) SPI_I2SCFGR_I2SCFG_0) #define I2S_MODE_MASTER_TX ((uint32_t) SPI_I2SCFGR_I2SCFG_1) #define I2S_MODE_MASTER_RX ((uint32_t)(SPI_I2SCFGR_I2SCFG_0 |\ @@ -173,7 +173,7 @@ typedef struct /** @defgroup I2S_Standard I2S Standard * @{ */ -#define I2S_STANDARD_PHILIPS ((uint32_t) 0x00000000) +#define I2S_STANDARD_PHILIPS ((uint32_t) 0x00000000U) #define I2S_STANDARD_MSB ((uint32_t) SPI_I2SCFGR_I2SSTD_0) #define I2S_STANDARD_LSB ((uint32_t) SPI_I2SCFGR_I2SSTD_1) #define I2S_STANDARD_PCM_SHORT ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\ @@ -196,7 +196,7 @@ typedef struct /** @defgroup I2S_Data_Format I2S Data Format * @{ */ -#define I2S_DATAFORMAT_16B ((uint32_t) 0x00000000) +#define I2S_DATAFORMAT_16B ((uint32_t) 0x00000000U) #define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t) SPI_I2SCFGR_CHLEN) #define I2S_DATAFORMAT_24B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)) #define I2S_DATAFORMAT_32B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)) @@ -208,7 +208,7 @@ typedef struct * @{ */ #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE) -#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000) +#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -216,16 +216,16 @@ typedef struct /** @defgroup I2S_Audio_Frequency I2S Audio Frequency * @{ */ -#define I2S_AUDIOFREQ_192K ((uint32_t)192000) -#define I2S_AUDIOFREQ_96K ((uint32_t)96000) -#define I2S_AUDIOFREQ_48K ((uint32_t)48000) -#define I2S_AUDIOFREQ_44K ((uint32_t)44100) -#define I2S_AUDIOFREQ_32K ((uint32_t)32000) -#define I2S_AUDIOFREQ_22K ((uint32_t)22050) -#define I2S_AUDIOFREQ_16K ((uint32_t)16000) -#define I2S_AUDIOFREQ_11K ((uint32_t)11025) -#define I2S_AUDIOFREQ_8K ((uint32_t)8000) -#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2) +#define I2S_AUDIOFREQ_192K ((uint32_t)192000U) +#define I2S_AUDIOFREQ_96K ((uint32_t)96000U) +#define I2S_AUDIOFREQ_48K ((uint32_t)48000U) +#define I2S_AUDIOFREQ_44K ((uint32_t)44100U) +#define I2S_AUDIOFREQ_32K ((uint32_t)32000U) +#define I2S_AUDIOFREQ_22K ((uint32_t)22050U) +#define I2S_AUDIOFREQ_16K ((uint32_t)16000U) +#define I2S_AUDIOFREQ_11K ((uint32_t)11025U) +#define I2S_AUDIOFREQ_8K ((uint32_t)8000U) +#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2U) /** * @} */ @@ -233,7 +233,7 @@ typedef struct /** @defgroup I2S_Clock_Polarity I2S Clock Polarity * @{ */ -#define I2S_CPOL_LOW ((uint32_t)0x00000000) +#define I2S_CPOL_LOW ((uint32_t)0x00000000U) #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.c index 0de2199c1c..06bd6981c2 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_irda.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief IRDA HAL module driver. * * This file provides firmware functions to manage the following @@ -147,8 +147,8 @@ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#define TEACK_REACK_TIMEOUT 1000 -#define HAL_IRDA_TXDMA_TIMEOUTVALUE 22000 +#define TEACK_REACK_TIMEOUT 1000U +#define HAL_IRDA_TXDMA_TIMEOUTVALUE 22000U #define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \ | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /* Private macro -------------------------------------------------------------*/ @@ -187,9 +187,21 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); (++) Word Length (++) Parity: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits) - or by the M1 and M0 bits (7-bit, 8-bit or 9-bit), - the possible IRDA frame formats are as listed in the following table: + (++) Power mode + (++) Prescaler setting + (++) Receiver/transmitter modes + + [..] + The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures + (details for the procedures are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M bit (8-bits or 9-bits) + or by the M1 and M0 bits (7-bit, 8-bit or 9-bit), + the possible IRDA frame formats are as listed in the following table: + + Table 1. IRDA frame format. +---------------------------------------------------------------+ | M1M0 bits | PCE bit | IRDA frame | |-----------|-----------|---------------------------------------| @@ -205,16 +217,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); |-----------|-----------|---------------------------------------| | 10 | 1 | | SB | 6-bit data | PB | STB | | +---------------------------------------------------------------+ - - (++) Power mode - (++) Prescaler setting - (++) Receiver/transmitter modes - [..] - The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures - (details for the procedures are available in reference manual). - -@endverbatim * @{ */ @@ -396,7 +399,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -416,7 +419,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u hirda->TxXferSize = Size; hirda->TxXferCount = Size; - while(hirda->TxXferCount > 0) + while(hirda->TxXferCount > 0U) { hirda->TxXferCount--; @@ -427,12 +430,12 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { tmp = (uint16_t*) pData; - hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF); + hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU); pData +=2; } else { - hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF); + hirda->Instance->TDR = (*pData++ & (uint8_t)0xFFU); } } @@ -476,7 +479,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -503,7 +506,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui uhMask = hirda->Mask; /* Check data remaining to be received */ - while(hirda->RxXferCount > 0) + while(hirda->RxXferCount > 0U) { hirda->RxXferCount--; @@ -515,7 +518,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui { tmp = (uint16_t*) pData ; *tmp = (uint16_t)(hirda->Instance->RDR & uhMask); - pData +=2; + pData +=2U; } else { @@ -554,7 +557,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData { if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -576,9 +579,6 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData hirda->State = HAL_IRDA_STATE_BUSY_TX; } - /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR); - /* Process Unlocked */ __HAL_UNLOCK(hirda); @@ -604,7 +604,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, { if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -663,7 +663,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -732,7 +732,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1097,8 +1097,8 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) */ static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda) { - uint32_t tmpreg = 0x00000000; - uint32_t clocksource = 0x00000000; + uint32_t tmpreg = 0x00000000U; + uint32_t clocksource = 0x00000000U; /* Check the communication parameters */ assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); @@ -1127,19 +1127,19 @@ static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda) switch (clocksource) { case IRDA_CLOCKSOURCE_PCLK1: - hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hirda->Init.BaudRate); + hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate); break; case IRDA_CLOCKSOURCE_PCLK2: - hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK2Freq() / hirda->Init.BaudRate); + hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate); break; case IRDA_CLOCKSOURCE_HSI: - hirda->Instance->BRR = (uint16_t)(HSI_VALUE / hirda->Init.BaudRate); + hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate); break; case IRDA_CLOCKSOURCE_SYSCLK: - hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hirda->Init.BaudRate); + hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate); break; case IRDA_CLOCKSOURCE_LSE: - hirda->Instance->BRR = (uint16_t)(LSE_VALUE / hirda->Init.BaudRate); + hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate); break; default: break; @@ -1194,7 +1194,7 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) */ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { - uint32_t tickstart = 0x00; + uint32_t tickstart = 0x00U; tickstart = HAL_GetTick(); /* Wait until flag is set */ @@ -1205,7 +1205,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); @@ -1230,7 +1230,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); @@ -1265,7 +1265,7 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) if((hirda->State == HAL_IRDA_STATE_BUSY_TX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)) { - if(hirda->TxXferCount == 0) + if(hirda->TxXferCount == 0U) { /* Disable the IRDA Transmit Data Register Empty Interrupt */ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); @@ -1280,12 +1280,12 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { tmp = (uint16_t*) hirda->pTxBuffPtr; - hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF); - hirda->pTxBuffPtr += 2; + hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + hirda->pTxBuffPtr += 2U; } else { - hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF); + hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFFU); } hirda->TxXferCount--; return HAL_OK; @@ -1343,32 +1343,32 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) { tmp = (uint16_t*) hirda->pRxBuffPtr ; *tmp = (uint16_t)(hirda->Instance->RDR & uhMask); - hirda->pRxBuffPtr +=2; + hirda->pRxBuffPtr +=2U; } else { *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); } - if(--hirda->RxXferCount == 0) + if(--hirda->RxXferCount == 0U) { while(HAL_IS_BIT_SET(hirda->Instance->ISR, IRDA_FLAG_RXNE)) { } __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); + + /* Disable the IRDA Parity Error Interrupt */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); + /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) { hirda->State = HAL_IRDA_STATE_BUSY_TX; } else { - /* Disable the IRDA Parity Error Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); - - /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - hirda->State = HAL_IRDA_STATE_READY; } @@ -1397,7 +1397,7 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* DMA Normal mode */ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { - hirda->TxXferCount = 0; + hirda->TxXferCount = 0U; /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the IRDA CR3 register */ @@ -1435,9 +1435,9 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { - hirda->RxXferCount = 0; + hirda->RxXferCount = 0U; /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the IRDA CR3 register */ @@ -1477,8 +1477,8 @@ static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) static void IRDA_DMAError(DMA_HandleTypeDef *hdma) { IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hirda->RxXferCount = 0; - hirda->TxXferCount = 0; + hirda->RxXferCount = 0U; + hirda->TxXferCount = 0U; hirda->State= HAL_IRDA_STATE_READY; hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; HAL_IRDA_ErrorCallback(hirda); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.h index 15ea2f0629..91f2b35663 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_irda.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of IRDA HAL module. ****************************************************************************** * @attention @@ -94,14 +94,14 @@ typedef struct */ typedef enum { - HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */ - HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_IRDA_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */ + HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_IRDA_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_IRDA_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_IRDA_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_IRDA_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ + HAL_IRDA_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_IRDA_STATE_ERROR = 0x04U /*!< Error */ }HAL_IRDA_StateTypeDef; @@ -159,29 +159,29 @@ typedef struct * @brief HAL IRDA Error Code definition */ -#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_IRDA_ERROR_PE ((uint32_t)0x01) /*!< Parity error */ -#define HAL_IRDA_ERROR_NE ((uint32_t)0x02) /*!< Noise error */ -#define HAL_IRDA_ERROR_FE ((uint32_t)0x04) /*!< frame error */ -#define HAL_IRDA_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */ -#define HAL_IRDA_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ +#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00U) /*!< No error */ +#define HAL_IRDA_ERROR_PE ((uint32_t)0x01U) /*!< Parity error */ +#define HAL_IRDA_ERROR_NE ((uint32_t)0x02U) /*!< Noise error */ +#define HAL_IRDA_ERROR_FE ((uint32_t)0x04U) /*!< frame error */ +#define HAL_IRDA_ERROR_ORE ((uint32_t)0x08U) /*!< Overrun error */ +#define HAL_IRDA_ERROR_DMA ((uint32_t)0x10U) /*!< DMA transfer error */ /** * @brief IRDA clock sources definition */ typedef enum { - IRDA_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - IRDA_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - IRDA_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - IRDA_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - IRDA_CLOCKSOURCE_LSE = 0x08 /*!< LSE clock source */ + IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + IRDA_CLOCKSOURCE_LSE = 0x08U /*!< LSE clock source */ }IRDA_ClockSourceTypeDef; /** @defgroup IRDA_Parity IRDA Parity * @{ */ -#define IRDA_PARITY_NONE ((uint32_t)0x0000) +#define IRDA_PARITY_NONE ((uint32_t)0x0000U) #define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) #define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) #define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \ @@ -206,7 +206,7 @@ typedef enum /** @defgroup IRDA_Low_Power IRDA low power * @{ */ -#define IRDA_POWERMODE_NORMAL ((uint32_t)0x0000) +#define IRDA_POWERMODE_NORMAL ((uint32_t)0x0000U) #define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) #define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \ ((MODE) == IRDA_POWERMODE_NORMAL)) @@ -217,7 +217,7 @@ typedef enum /** @defgroup IRDA_State IRDA State * @{ */ -#define IRDA_STATE_DISABLE ((uint32_t)0x0000) +#define IRDA_STATE_DISABLE ((uint32_t)0x0000U) #define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE) #define IS_IRDA_STATE(STATE) (((STATE) == IRDA_STATE_DISABLE) || \ ((STATE) == IRDA_STATE_ENABLE)) @@ -228,7 +228,7 @@ typedef enum /** @defgroup IRDA_Mode IRDA Mode * @{ */ -#define IRDA_MODE_DISABLE ((uint32_t)0x0000) +#define IRDA_MODE_DISABLE ((uint32_t)0x0000U) #define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN) #define IS_IRDA_MODE(STATE) (((STATE) == IRDA_MODE_DISABLE) || \ ((STATE) == IRDA_MODE_ENABLE)) @@ -239,7 +239,7 @@ typedef enum /** @defgroup IRDA_One_Bit IRDA One bit * @{ */ -#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) +#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U) #define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) #define IS_IRDA_ONE_BIT_SAMPLE(ONEBIT) (((ONEBIT) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \ ((ONEBIT) == IRDA_ONE_BIT_SAMPLE_ENABLE)) @@ -250,7 +250,7 @@ typedef enum /** @defgroup IRDA_DMA_Tx IRDA DMA TX * @{ */ -#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000) +#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000U) #define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) #define IS_IRDA_DMA_TX(DMATX) (((DMATX) == IRDA_DMA_TX_DISABLE) || \ ((DMATX) == IRDA_DMA_TX_ENABLE)) @@ -261,7 +261,7 @@ typedef enum /** @defgroup IRDA_DMA_Rx IRDA DMA RX * @{ */ -#define IRDA_DMA_RX_DISABLE ((uint32_t)0x0000) +#define IRDA_DMA_RX_DISABLE ((uint32_t)0x0000U) #define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) #define IS_IRDA_DMA_RX(DMARX) (((DMARX) == IRDA_DMA_RX_DISABLE) || \ ((DMARX) == IRDA_DMA_RX_ENABLE)) @@ -300,11 +300,11 @@ typedef enum * - ZZZZ : Flag position in the ISR register(4bits) * @{ */ -#define IRDA_IT_PE ((uint16_t)0x0028) -#define IRDA_IT_TXE ((uint16_t)0x0727) -#define IRDA_IT_TC ((uint16_t)0x0626) -#define IRDA_IT_RXNE ((uint16_t)0x0525) -#define IRDA_IT_IDLE ((uint16_t)0x0424) +#define IRDA_IT_PE ((uint16_t)0x0028U) +#define IRDA_IT_TXE ((uint16_t)0x0727U) +#define IRDA_IT_TC ((uint16_t)0x0626U) +#define IRDA_IT_RXNE ((uint16_t)0x0525U) +#define IRDA_IT_IDLE ((uint16_t)0x0424U) @@ -315,14 +315,14 @@ typedef enum * - 10: CR2 register * - 11: CR3 register */ -#define IRDA_IT_ERR ((uint16_t)0x0060) +#define IRDA_IT_ERR ((uint16_t)0x0060U) /** Elements values convention: 0000ZZZZ00000000b * - ZZZZ : Flag position in the ISR register(4bits) */ -#define IRDA_IT_ORE ((uint16_t)0x0300) -#define IRDA_IT_NE ((uint16_t)0x0200) -#define IRDA_IT_FE ((uint16_t)0x0100) +#define IRDA_IT_ORE ((uint16_t)0x0300U) +#define IRDA_IT_NE ((uint16_t)0x0200U) +#define IRDA_IT_FE ((uint16_t)0x0100U) /** * @} */ @@ -360,7 +360,7 @@ typedef enum /** @defgroup IRDA_Interruption_Mask IRDA Interruption mask * @{ */ -#define IRDA_IT_MASK ((uint16_t)0x001F) +#define IRDA_IT_MASK ((uint16_t)0x001FU) /** * @} */ @@ -477,9 +477,9 @@ typedef enum * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK)))) +#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Disable the specified IRDA interrupt. * @param __HANDLE__: specifies the IRDA Handle. @@ -494,8 +494,8 @@ typedef enum * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \ +#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Check whether the specified IRDA interrupt has occurred or not. @@ -513,7 +513,7 @@ typedef enum * @arg IRDA_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) +#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08U))) /** @brief Check whether the specified IRDA interrupt source is enabled. * @param __HANDLE__: specifies the IRDA Handle. @@ -530,8 +530,8 @@ typedef enum * @arg IRDA_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK))) +#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \ + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1U << (((uint16_t)(__IT__)) & IRDA_IT_MASK))) /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. * @param __HANDLE__: specifies the IRDA Handle. @@ -591,13 +591,13 @@ typedef enum * @param __BAUDRATE__: specifies the IRDA Baudrate set by the user. * @retval True or False */ -#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201) +#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U) /** @brief Ensure that IRDA prescaler value is strictly larger than 0 * @param __PRESCALER__: specifies the IRDA prescaler value set by the user. * @retval True or False */ -#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0) +#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda_ex.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda_ex.h index 5d554b8a2f..1c3fcb94a1 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_irda_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of IRDA HAL Extension module. ****************************************************************************** * @attention @@ -64,7 +64,7 @@ * @{ */ #define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) -#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) +#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000U) #define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) #define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_7B) || \ ((LENGTH) == IRDA_WORDLENGTH_8B) || \ @@ -211,33 +211,33 @@ { \ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x01FF ; \ + (__HANDLE__)->Mask = 0x01FFU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x00FF ; \ + (__HANDLE__)->Mask = 0x00FFU ; \ } \ } \ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \ { \ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x00FF ; \ + (__HANDLE__)->Mask = 0x00FFU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x007F ; \ + (__HANDLE__)->Mask = 0x007FU ; \ } \ } \ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \ { \ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x007F ; \ + (__HANDLE__)->Mask = 0x007FU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x003F ; \ + (__HANDLE__)->Mask = 0x003FU ; \ } \ } \ } while(0) diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_iwdg.c index 855e8c1301..cefc29a86c 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_iwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_iwdg.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: @@ -129,7 +129,7 @@ * @{ */ /* TimeOut value */ -#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000 +#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000U /* Local define used to check the SR status register */ #define IWDG_SR_FLAGS (IWDG_FLAG_PVU | IWDG_FLAG_RVU | IWDG_FLAG_WVU) @@ -172,7 +172,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the IWDG handle allocation */ if(hiwdg == NULL) @@ -186,7 +186,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); /* Check pending flag, if previous update not done, return error */ - if(((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0) + if(((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0U) { return HAL_ERROR; } @@ -217,7 +217,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) tickstart = HAL_GetTick(); /* Wait for register to be updated */ - while (((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0) + while (((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0U) { if((HAL_GetTick()-tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) { @@ -281,7 +281,7 @@ __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) */ HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Process locked */ __HAL_LOCK(hiwdg); @@ -301,7 +301,7 @@ HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg) tickstart = HAL_GetTick(); /* Wait until PVU, RVU, WVU flag are RESET */ - while (((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0) + while (((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0U) { if((HAL_GetTick()-tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) { @@ -332,7 +332,7 @@ HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg) */ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Process Locked */ __HAL_LOCK(hiwdg); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_iwdg.h index 9707e16cfb..d8d0541023 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_iwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_iwdg.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention @@ -68,11 +68,11 @@ */ typedef enum { - HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */ - HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */ - HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */ - HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */ - HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */ + HAL_IWDG_STATE_RESET = 0x00U, /*!< IWDG not yet initialized or disabled */ + HAL_IWDG_STATE_READY = 0x01U, /*!< IWDG initialized and ready for use */ + HAL_IWDG_STATE_BUSY = 0x02U, /*!< IWDG internal process is ongoing */ + HAL_IWDG_STATE_TIMEOUT = 0x03U, /*!< IWDG timeout state */ + HAL_IWDG_STATE_ERROR = 0x04U /*!< IWDG error state */ }HAL_IWDG_StateTypeDef; /** @@ -138,10 +138,10 @@ typedef struct */ /* --- KR Register ---*/ /* KR register bit mask */ -#define IWDG_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG Reload Counter Enable */ -#define IWDG_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG Peripheral Enable */ -#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x5555) /*!< IWDG KR Write Access Enable */ -#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x0000) /*!< IWDG KR Write Access Disable */ +#define IWDG_KEY_RELOAD ((uint32_t)0xAAAAU) /*!< IWDG Reload Counter Enable */ +#define IWDG_KEY_ENABLE ((uint32_t)0xCCCCU) /*!< IWDG Peripheral Enable */ +#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x5555U) /*!< IWDG KR Write Access Enable */ +#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x0000U) /*!< IWDG KR Write Access Disable */ /** * @} */ @@ -165,7 +165,7 @@ typedef struct /** @defgroup IWDG_Prescaler IWDG Prescaler * @{ */ -#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */ +#define IWDG_PRESCALER_4 ((uint8_t)0x00U) /*!< IWDG prescaler set to 4 */ #define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */ #define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */ #define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */ @@ -184,16 +184,16 @@ typedef struct ((__PRESCALER__) == IWDG_PRESCALER_256)) /* Check for reload value */ -#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF) +#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFFU) /* Check for window value */ -#define IS_IWDG_WINDOW(__VALUE__) ((__VALUE__) <= 0xFFF) +#define IS_IWDG_WINDOW(__VALUE__) ((__VALUE__) <= 0xFFFU) /** @defgroup IWDG_Disable IWDG Disable * @{ */ -#define IWDG_WINDOW_DISABLE 0xFFF +#define IWDG_WINDOW_DISABLE 0xFFFU /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lcd.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lcd.c index a8618de50d..9895942611 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lcd.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_lcd.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief LCD Controller HAL module driver. * This file provides firmware functions to manage the following * functionalities of the LCD Controller (LCD) peripheral: @@ -108,7 +108,7 @@ /** @addtogroup LCD_Private * @{ */ -#define LCD_TIMEOUT_VALUE 1000 +#define LCD_TIMEOUT_VALUE 1000U /** * @} */ @@ -186,8 +186,8 @@ HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd) */ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) { - uint32_t tickstart = 0x00; - uint8_t counter = 0; + uint32_t tickstart = 0x00U; + uint8_t counter = 0U; /* Check the LCD handle allocation */ if(hlcd == NULL) @@ -228,7 +228,7 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) in the LCD_SR register */ for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++) { - hlcd->Instance->RAM[counter] = 0; + hlcd->Instance->RAM[counter] = 0U; } /* Enable the display request */ SET_BIT(hlcd->Instance->SR, LCD_SR_UDR); @@ -394,7 +394,7 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) */ HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data) { - uint32_t tickstart = 0x00; + uint32_t tickstart = 0x00U; if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY)) { @@ -440,8 +440,8 @@ HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterInd */ HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd) { - uint32_t tickstart = 0x00; - uint32_t counter = 0; + uint32_t tickstart = 0x00U; + uint32_t counter = 0U; if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY)) { @@ -469,7 +469,7 @@ HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd) /* Clear the LCD_RAM registers */ for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++) { - hlcd->Instance->RAM[counter] = 0; + hlcd->Instance->RAM[counter] = 0U; } /* Update the LCD display */ @@ -499,7 +499,7 @@ HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd) */ HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd) { - uint32_t tickstart = 0x00; + uint32_t tickstart = 0x00U; /* Clear the Update Display Done flag before starting the update display request */ __HAL_LCD_CLEAR_FLAG(hlcd, LCD_FLAG_UDD); @@ -591,7 +591,7 @@ uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd) */ HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd) { - uint32_t tickstart = 0x00; + uint32_t tickstart = 0x00U; /* Get timeout */ tickstart = HAL_GetTick(); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lcd.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lcd.h index c856ec9dd9..bf6d0eb9e1 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lcd.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lcd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_lcd.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of LCD Controller HAL module. ****************************************************************************** * @attention @@ -99,11 +99,11 @@ typedef struct */ typedef enum { - HAL_LCD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */ - HAL_LCD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_LCD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_LCD_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_LCD_STATE_ERROR = 0x04 /*!< Error */ + HAL_LCD_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_LCD_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_LCD_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_LCD_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_LCD_STATE_ERROR = 0x04U /*!< Error */ }HAL_LCD_StateTypeDef; /** @@ -136,12 +136,12 @@ typedef struct /** @defgroup LCD_ErrorCode LCD Error Code * @{ */ -#define HAL_LCD_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_LCD_ERROR_FCRSF ((uint32_t)0x01) /*!< Synchro flag timeout error */ -#define HAL_LCD_ERROR_UDR ((uint32_t)0x02) /*!< Update display request flag timeout error */ -#define HAL_LCD_ERROR_UDD ((uint32_t)0x04) /*!< Update display done flag timeout error */ -#define HAL_LCD_ERROR_ENS ((uint32_t)0x08) /*!< LCD enabled status flag timeout error */ -#define HAL_LCD_ERROR_RDY ((uint32_t)0x10) /*!< LCD Booster ready timeout error */ +#define HAL_LCD_ERROR_NONE ((uint32_t)0x00U) /*!< No error */ +#define HAL_LCD_ERROR_FCRSF ((uint32_t)0x01U) /*!< Synchro flag timeout error */ +#define HAL_LCD_ERROR_UDR ((uint32_t)0x02U) /*!< Update display request flag timeout error */ +#define HAL_LCD_ERROR_UDD ((uint32_t)0x04U) /*!< Update display done flag timeout error */ +#define HAL_LCD_ERROR_ENS ((uint32_t)0x08U) /*!< LCD enabled status flag timeout error */ +#define HAL_LCD_ERROR_RDY ((uint32_t)0x10U) /*!< LCD Booster ready timeout error */ /** * @} */ @@ -150,21 +150,21 @@ typedef struct * @{ */ -#define LCD_PRESCALER_1 ((uint32_t)0x00000000) /*!< CLKPS = LCDCLK */ -#define LCD_PRESCALER_2 ((uint32_t)0x00400000) /*!< CLKPS = LCDCLK/2 */ -#define LCD_PRESCALER_4 ((uint32_t)0x00800000) /*!< CLKPS = LCDCLK/4 */ -#define LCD_PRESCALER_8 ((uint32_t)0x00C00000) /*!< CLKPS = LCDCLK/8 */ -#define LCD_PRESCALER_16 ((uint32_t)0x01000000) /*!< CLKPS = LCDCLK/16 */ -#define LCD_PRESCALER_32 ((uint32_t)0x01400000) /*!< CLKPS = LCDCLK/32 */ -#define LCD_PRESCALER_64 ((uint32_t)0x01800000) /*!< CLKPS = LCDCLK/64 */ -#define LCD_PRESCALER_128 ((uint32_t)0x01C00000) /*!< CLKPS = LCDCLK/128 */ -#define LCD_PRESCALER_256 ((uint32_t)0x02000000) /*!< CLKPS = LCDCLK/256 */ -#define LCD_PRESCALER_512 ((uint32_t)0x02400000) /*!< CLKPS = LCDCLK/512 */ -#define LCD_PRESCALER_1024 ((uint32_t)0x02800000) /*!< CLKPS = LCDCLK/1024 */ -#define LCD_PRESCALER_2048 ((uint32_t)0x02C00000) /*!< CLKPS = LCDCLK/2048 */ -#define LCD_PRESCALER_4096 ((uint32_t)0x03000000) /*!< CLKPS = LCDCLK/4096 */ -#define LCD_PRESCALER_8192 ((uint32_t)0x03400000) /*!< CLKPS = LCDCLK/8192 */ -#define LCD_PRESCALER_16384 ((uint32_t)0x03800000) /*!< CLKPS = LCDCLK/16384 */ +#define LCD_PRESCALER_1 ((uint32_t)0x00000000U) /*!< CLKPS = LCDCLK */ +#define LCD_PRESCALER_2 ((uint32_t)0x00400000U) /*!< CLKPS = LCDCLK/2 */ +#define LCD_PRESCALER_4 ((uint32_t)0x00800000U) /*!< CLKPS = LCDCLK/4 */ +#define LCD_PRESCALER_8 ((uint32_t)0x00C00000U) /*!< CLKPS = LCDCLK/8 */ +#define LCD_PRESCALER_16 ((uint32_t)0x01000000U) /*!< CLKPS = LCDCLK/16 */ +#define LCD_PRESCALER_32 ((uint32_t)0x01400000U) /*!< CLKPS = LCDCLK/32 */ +#define LCD_PRESCALER_64 ((uint32_t)0x01800000U) /*!< CLKPS = LCDCLK/64 */ +#define LCD_PRESCALER_128 ((uint32_t)0x01C00000U) /*!< CLKPS = LCDCLK/128 */ +#define LCD_PRESCALER_256 ((uint32_t)0x02000000U) /*!< CLKPS = LCDCLK/256 */ +#define LCD_PRESCALER_512 ((uint32_t)0x02400000U) /*!< CLKPS = LCDCLK/512 */ +#define LCD_PRESCALER_1024 ((uint32_t)0x02800000U) /*!< CLKPS = LCDCLK/1024 */ +#define LCD_PRESCALER_2048 ((uint32_t)0x02C00000U) /*!< CLKPS = LCDCLK/2048 */ +#define LCD_PRESCALER_4096 ((uint32_t)0x03000000U) /*!< CLKPS = LCDCLK/4096 */ +#define LCD_PRESCALER_8192 ((uint32_t)0x03400000U) /*!< CLKPS = LCDCLK/8192 */ +#define LCD_PRESCALER_16384 ((uint32_t)0x03800000U) /*!< CLKPS = LCDCLK/16384 */ #define LCD_PRESCALER_32768 ((uint32_t)LCD_FCR_PS) /*!< CLKPS = LCDCLK/32768 */ #define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1) || \ @@ -192,21 +192,21 @@ typedef struct * @{ */ -#define LCD_DIVIDER_16 ((uint32_t)0x00000000) /*!< LCD frequency = CLKPS/16 */ -#define LCD_DIVIDER_17 ((uint32_t)0x00040000) /*!< LCD frequency = CLKPS/17 */ -#define LCD_DIVIDER_18 ((uint32_t)0x00080000) /*!< LCD frequency = CLKPS/18 */ -#define LCD_DIVIDER_19 ((uint32_t)0x000C0000) /*!< LCD frequency = CLKPS/19 */ -#define LCD_DIVIDER_20 ((uint32_t)0x00100000) /*!< LCD frequency = CLKPS/20 */ -#define LCD_DIVIDER_21 ((uint32_t)0x00140000) /*!< LCD frequency = CLKPS/21 */ -#define LCD_DIVIDER_22 ((uint32_t)0x00180000) /*!< LCD frequency = CLKPS/22 */ -#define LCD_DIVIDER_23 ((uint32_t)0x001C0000) /*!< LCD frequency = CLKPS/23 */ -#define LCD_DIVIDER_24 ((uint32_t)0x00200000) /*!< LCD frequency = CLKPS/24 */ -#define LCD_DIVIDER_25 ((uint32_t)0x00240000) /*!< LCD frequency = CLKPS/25 */ -#define LCD_DIVIDER_26 ((uint32_t)0x00280000) /*!< LCD frequency = CLKPS/26 */ -#define LCD_DIVIDER_27 ((uint32_t)0x002C0000) /*!< LCD frequency = CLKPS/27 */ -#define LCD_DIVIDER_28 ((uint32_t)0x00300000) /*!< LCD frequency = CLKPS/28 */ -#define LCD_DIVIDER_29 ((uint32_t)0x00340000) /*!< LCD frequency = CLKPS/29 */ -#define LCD_DIVIDER_30 ((uint32_t)0x00380000) /*!< LCD frequency = CLKPS/30 */ +#define LCD_DIVIDER_16 ((uint32_t)0x00000000U) /*!< LCD frequency = CLKPS/16 */ +#define LCD_DIVIDER_17 ((uint32_t)0x00040000U) /*!< LCD frequency = CLKPS/17 */ +#define LCD_DIVIDER_18 ((uint32_t)0x00080000U) /*!< LCD frequency = CLKPS/18 */ +#define LCD_DIVIDER_19 ((uint32_t)0x000C0000U) /*!< LCD frequency = CLKPS/19 */ +#define LCD_DIVIDER_20 ((uint32_t)0x00100000U) /*!< LCD frequency = CLKPS/20 */ +#define LCD_DIVIDER_21 ((uint32_t)0x00140000U) /*!< LCD frequency = CLKPS/21 */ +#define LCD_DIVIDER_22 ((uint32_t)0x00180000U) /*!< LCD frequency = CLKPS/22 */ +#define LCD_DIVIDER_23 ((uint32_t)0x001C0000U) /*!< LCD frequency = CLKPS/23 */ +#define LCD_DIVIDER_24 ((uint32_t)0x00200000U) /*!< LCD frequency = CLKPS/24 */ +#define LCD_DIVIDER_25 ((uint32_t)0x00240000U) /*!< LCD frequency = CLKPS/25 */ +#define LCD_DIVIDER_26 ((uint32_t)0x00280000U) /*!< LCD frequency = CLKPS/26 */ +#define LCD_DIVIDER_27 ((uint32_t)0x002C0000U) /*!< LCD frequency = CLKPS/27 */ +#define LCD_DIVIDER_28 ((uint32_t)0x00300000U) /*!< LCD frequency = CLKPS/28 */ +#define LCD_DIVIDER_29 ((uint32_t)0x00340000U) /*!< LCD frequency = CLKPS/29 */ +#define LCD_DIVIDER_30 ((uint32_t)0x00380000U) /*!< LCD frequency = CLKPS/30 */ #define LCD_DIVIDER_31 ((uint32_t)LCD_FCR_DIV) /*!< LCD frequency = CLKPS/31 */ #define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \ @@ -235,7 +235,7 @@ typedef struct * @{ */ -#define LCD_DUTY_STATIC ((uint32_t)0x00000000) /*!< Static duty */ +#define LCD_DUTY_STATIC ((uint32_t)0x00000000U) /*!< Static duty */ #define LCD_DUTY_1_2 (LCD_CR_DUTY_0) /*!< 1/2 duty */ #define LCD_DUTY_1_3 (LCD_CR_DUTY_1) /*!< 1/3 duty */ #define LCD_DUTY_1_4 ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty */ @@ -256,7 +256,7 @@ typedef struct * @{ */ -#define LCD_BIAS_1_4 ((uint32_t)0x00000000) /*!< 1/4 Bias */ +#define LCD_BIAS_1_4 ((uint32_t)0x00000000U) /*!< 1/4 Bias */ #define LCD_BIAS_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */ #define LCD_BIAS_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */ @@ -271,7 +271,7 @@ typedef struct * @{ */ -#define LCD_VOLTAGESOURCE_INTERNAL ((uint32_t)0x00000000) /*!< Internal voltage source for the LCD */ +#define LCD_VOLTAGESOURCE_INTERNAL ((uint32_t)0x00000000U) /*!< Internal voltage source for the LCD */ #define LCD_VOLTAGESOURCE_EXTERNAL LCD_CR_VSEL /*!< External voltage source for the LCD */ #define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \ @@ -295,7 +295,7 @@ typedef struct * @{ */ -#define LCD_PULSEONDURATION_0 ((uint32_t)0x00000000) /*!< Pulse ON duration = 0 pulse */ +#define LCD_PULSEONDURATION_0 ((uint32_t)0x00000000U) /*!< Pulse ON duration = 0 pulse */ #define LCD_PULSEONDURATION_1 (LCD_FCR_PON_0) /*!< Pulse ON duration = 1/CK_PS */ #define LCD_PULSEONDURATION_2 (LCD_FCR_PON_1) /*!< Pulse ON duration = 2/CK_PS */ #define LCD_PULSEONDURATION_3 (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS */ @@ -320,7 +320,7 @@ typedef struct * @{ */ -#define LCD_HIGHDRIVE_0 ((uint32_t)0x00000000) /*!< Low resistance Drive */ +#define LCD_HIGHDRIVE_0 ((uint32_t)0x00000000U) /*!< Low resistance Drive */ #define LCD_HIGHDRIVE_1 (LCD_FCR_HD) /*!< High resistance Drive */ #define IS_LCD_HIGHDRIVE(__HIGHDRIVE__) (((__HIGHDRIVE__) == LCD_HIGHDRIVE_0) || \ @@ -333,7 +333,7 @@ typedef struct * @{ */ -#define LCD_DEADTIME_0 ((uint32_t)0x00000000) /*!< No dead Time */ +#define LCD_DEADTIME_0 ((uint32_t)0x00000000U) /*!< No dead Time */ #define LCD_DEADTIME_1 (LCD_FCR_DEAD_0) /*!< One Phase between different couple of Frame */ #define LCD_DEADTIME_2 (LCD_FCR_DEAD_1) /*!< Two Phase between different couple of Frame */ #define LCD_DEADTIME_3 (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */ @@ -358,7 +358,7 @@ typedef struct * @{ */ -#define LCD_BLINKMODE_OFF ((uint32_t)0x00000000) /*!< Blink disabled */ +#define LCD_BLINKMODE_OFF ((uint32_t)0x00000000U) /*!< Blink disabled */ #define LCD_BLINKMODE_SEG0_COM0 (LCD_FCR_BLINK_0) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */ #define LCD_BLINKMODE_SEG0_ALLCOM (LCD_FCR_BLINK_1) /*!< Blink enabled on SEG[0], all COM (up to 8 pixels according to the programmed duty) */ @@ -376,7 +376,7 @@ typedef struct * @{ */ -#define LCD_BLINKFREQUENCY_DIV8 ((uint32_t)0x00000000) /*!< The Blink frequency = fLCD/8 */ +#define LCD_BLINKFREQUENCY_DIV8 ((uint32_t)0x00000000U) /*!< The Blink frequency = fLCD/8 */ #define LCD_BLINKFREQUENCY_DIV16 (LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/16 */ #define LCD_BLINKFREQUENCY_DIV32 (LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/32 */ #define LCD_BLINKFREQUENCY_DIV64 (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64 */ @@ -401,7 +401,7 @@ typedef struct * @{ */ -#define LCD_CONTRASTLEVEL_0 ((uint32_t)0x00000000) /*!< Maximum Voltage = 2.60V */ +#define LCD_CONTRASTLEVEL_0 ((uint32_t)0x00000000U) /*!< Maximum Voltage = 2.60V */ #define LCD_CONTRASTLEVEL_1 (LCD_FCR_CC_0) /*!< Maximum Voltage = 2.73V */ #define LCD_CONTRASTLEVEL_2 (LCD_FCR_CC_1) /*!< Maximum Voltage = 2.86V */ #define LCD_CONTRASTLEVEL_3 (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V */ @@ -426,7 +426,7 @@ typedef struct * @{ */ -#define LCD_MUXSEGMENT_DISABLE ((uint32_t)0x00000000) /*!< SEG pin multiplexing disabled */ +#define LCD_MUXSEGMENT_DISABLE ((uint32_t)0x00000000U) /*!< SEG pin multiplexing disabled */ #define LCD_MUXSEGMENT_ENABLE (LCD_CR_MUX_SEG) /*!< SEG[31:28] are multiplexed with SEG[43:40] */ #define IS_LCD_MUXSEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \ @@ -435,6 +435,19 @@ typedef struct * @} */ +/** @defgroup LCD_BUFEN LCD Voltage output buffer enable + * @{ + */ + +#define LCD_VOLTBUFOUT_DISABLE ((uint32_t)0x00000000U) /*!< Voltage output buffer disabled */ +#define LCD_VOLTBUFOUT_ENABLE (LCD_CR_BUFEN) /*!< BUFEN[1] Voltage output buffer enabled */ + +#define IS_LCD_VOLTBUFOUT(__VALUE__) (((__VALUE__) == LCD_VOLTBUFOUT_ENABLE) || \ + ((__VALUE__) == LCD_VOLTBUFOUT_DISABLE)) +/** + * @} + */ + /** @defgroup LCD_Flag LCD Flag * @{ */ @@ -454,22 +467,22 @@ typedef struct * @{ */ -#define LCD_RAM_REGISTER0 ((uint32_t)0x00000000) /*!< LCD RAM Register 0 */ -#define LCD_RAM_REGISTER1 ((uint32_t)0x00000001) /*!< LCD RAM Register 1 */ -#define LCD_RAM_REGISTER2 ((uint32_t)0x00000002) /*!< LCD RAM Register 2 */ -#define LCD_RAM_REGISTER3 ((uint32_t)0x00000003) /*!< LCD RAM Register 3 */ -#define LCD_RAM_REGISTER4 ((uint32_t)0x00000004) /*!< LCD RAM Register 4 */ -#define LCD_RAM_REGISTER5 ((uint32_t)0x00000005) /*!< LCD RAM Register 5 */ -#define LCD_RAM_REGISTER6 ((uint32_t)0x00000006) /*!< LCD RAM Register 6 */ -#define LCD_RAM_REGISTER7 ((uint32_t)0x00000007) /*!< LCD RAM Register 7 */ -#define LCD_RAM_REGISTER8 ((uint32_t)0x00000008) /*!< LCD RAM Register 8 */ -#define LCD_RAM_REGISTER9 ((uint32_t)0x00000009) /*!< LCD RAM Register 9 */ -#define LCD_RAM_REGISTER10 ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */ -#define LCD_RAM_REGISTER11 ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */ -#define LCD_RAM_REGISTER12 ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */ -#define LCD_RAM_REGISTER13 ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */ -#define LCD_RAM_REGISTER14 ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */ -#define LCD_RAM_REGISTER15 ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */ +#define LCD_RAM_REGISTER0 ((uint32_t)0x00000000U) /*!< LCD RAM Register 0 */ +#define LCD_RAM_REGISTER1 ((uint32_t)0x00000001U) /*!< LCD RAM Register 1 */ +#define LCD_RAM_REGISTER2 ((uint32_t)0x00000002U) /*!< LCD RAM Register 2 */ +#define LCD_RAM_REGISTER3 ((uint32_t)0x00000003U) /*!< LCD RAM Register 3 */ +#define LCD_RAM_REGISTER4 ((uint32_t)0x00000004U) /*!< LCD RAM Register 4 */ +#define LCD_RAM_REGISTER5 ((uint32_t)0x00000005U) /*!< LCD RAM Register 5 */ +#define LCD_RAM_REGISTER6 ((uint32_t)0x00000006U) /*!< LCD RAM Register 6 */ +#define LCD_RAM_REGISTER7 ((uint32_t)0x00000007U) /*!< LCD RAM Register 7 */ +#define LCD_RAM_REGISTER8 ((uint32_t)0x00000008U) /*!< LCD RAM Register 8 */ +#define LCD_RAM_REGISTER9 ((uint32_t)0x00000009U) /*!< LCD RAM Register 9 */ +#define LCD_RAM_REGISTER10 ((uint32_t)0x0000000AU) /*!< LCD RAM Register 10 */ +#define LCD_RAM_REGISTER11 ((uint32_t)0x0000000BU) /*!< LCD RAM Register 11 */ +#define LCD_RAM_REGISTER12 ((uint32_t)0x0000000CU) /*!< LCD RAM Register 12 */ +#define LCD_RAM_REGISTER13 ((uint32_t)0x0000000DU) /*!< LCD RAM Register 13 */ +#define LCD_RAM_REGISTER14 ((uint32_t)0x0000000EU) /*!< LCD RAM Register 14 */ +#define LCD_RAM_REGISTER15 ((uint32_t)0x0000000FU) /*!< LCD RAM Register 15 */ #define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0) || \ ((__REGISTER__) == LCD_RAM_REGISTER1) || \ @@ -515,6 +528,13 @@ typedef struct #define __HAL_LCD_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)) #define __HAL_LCD_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)) +/** @brief macros to enables or disables the Voltage output buffer + * @param __HANDLE__: specifies the LCD Handle. + * @retval None + */ +#define __HAL_LCD_VOLTOUTBUFFER_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)) +#define __HAL_LCD_VOLTOUTBUFFER_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)) + /** @brief Macros to enable or disable the low resistance divider. Displays with high * internal resistance may need a longer drive time to achieve * satisfactory contrast. This function is useful in this case if some diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lptim.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lptim.c index db6858b87a..0202b86434 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lptim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_lptim.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief LPTIM HAL module driver. * * This file provides firmware functions to manage the following @@ -165,7 +165,7 @@ */ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) { - uint32_t tmpcfgr = 0; + uint32_t tmpcfgr = 0U; /* Check the LPTIM handle allocation */ if(hlptim == NULL) @@ -851,7 +851,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) */ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period) { - uint32_t tmpcfgr = 0; + uint32_t tmpcfgr = 0U; /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -930,7 +930,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) */ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period) { - uint32_t tmpcfgr = 0; + uint32_t tmpcfgr = 0U; /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -1102,6 +1102,12 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; + /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); + + /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); + /* Set TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; @@ -1140,6 +1146,12 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; + /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); + + /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -1236,6 +1248,12 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; + /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); + + /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); + /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { @@ -1280,6 +1298,12 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; + /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); + + /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -1470,6 +1494,8 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) HAL_LPTIM_DirectionDownCallback(hlptim); } } + + __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG(); } /** diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lptim.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lptim.h index b77fd3f658..a290b1b1df 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lptim.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_lptim.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of LPTIM HAL module. ****************************************************************************** * @attention @@ -62,6 +62,8 @@ /** @defgroup LPTIM_Clock_Configuration LPTIM Clock configuration structure * @{ */ +#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_IM29) /*!< External interrupt line 29 Connected to the LPTIM EXTI Line */ + /** * @brief LPTIM Clock configuration definition */ @@ -111,7 +113,7 @@ typedef struct typedef struct { uint32_t Source; /*!< Selects the Trigger source. - This parameter can be a value of @ref LPTIM_Trigger_Source */ + This parameter can be a value of @ref LPTIMEx_Trigger_Source */ uint32_t ActiveEdge; /*!< Selects the Trigger active edge. Note: This parameter is used only when an external trigger is used. @@ -162,11 +164,11 @@ typedef struct */ typedef enum __HAL_LPTIM_StateTypeDef { - HAL_LPTIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ - HAL_LPTIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_LPTIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_LPTIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_LPTIM_STATE_ERROR = 0x04 /*!< Internal Process is ongoing */ + HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */ }HAL_LPTIM_StateTypeDef; /** * @} @@ -206,15 +208,15 @@ typedef struct */ /* Check autoreload value */ -#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFF) +#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFU) /* Check compare value */ -#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFF) +#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFU) /** @defgroup LPTIM_Clock_Source Clock source * @{ */ -#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00) +#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00U) #define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL /** * @} @@ -226,7 +228,7 @@ typedef struct /** @defgroup LPTIM_Clock_Prescaler Prescaler * @{ */ -#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000) +#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000U) #define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 #define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 #define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)) @@ -253,7 +255,7 @@ typedef struct /** @defgroup LPTIM_Output_Polarity Output polarity * @{ */ -#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000) +#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U) #define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL) /** * @} @@ -264,7 +266,7 @@ typedef struct /** @defgroup LPTIM_Clock_Sample_Time Clock sample time * @{ */ -#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000) +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U) #define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0 #define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1 #define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT @@ -279,7 +281,7 @@ typedef struct /** @defgroup LPTIM_Clock_Polarity Clock polarity * @{ */ -#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000) +#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000U) #define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0 #define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /** @@ -306,7 +308,7 @@ typedef struct /** @defgroup LPTIM_Trigger_Sample_Time Trigger sample time * @{ */ -#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000) +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U) #define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0 #define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1 #define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT @@ -323,7 +325,7 @@ typedef struct * @{ */ -#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000) +#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000U) #define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /** * @} @@ -336,7 +338,7 @@ typedef struct /** @defgroup LPTIM_Counter_Source Counter source * @{ */ -#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000) +#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000U) #define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE /** * @} @@ -347,10 +349,10 @@ typedef struct /* Check for period value */ -#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFF) +#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFU) /* Check for pulse value */ -#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFF) +#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFU) /** @defgroup LPTIM_Flag_Definition Flag definition * @{ @@ -510,6 +512,88 @@ typedef struct #define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +/** + * @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line. + * @retval None + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line. + * @retval None + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable event on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable event on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\ + }while(0) + +/** + * @brief Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\ + __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\ + }while(0) + +/** + * @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not. + * @retval Line Status. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Clear the LPTIM Wake-up Timer associated Exti line flag. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lptim_ex.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lptim_ex.h index e158ecc155..03414db723 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lptim_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lptim_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_lptim_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of LPTIM Extended HAL module. ****************************************************************************** * @attention @@ -61,11 +61,11 @@ */ -/** @defgroup LPTIM_Trigger_Source Trigger source +/** @defgroup LPTIMEx_Trigger_Source Trigger source * @{ */ -#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFF) -#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000) +#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFFU) +#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000U) #define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0) #define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1 #define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1) diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd.c index 3aa08bfa30..e942635e9b 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_pcd.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -91,7 +91,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#define BTABLE_ADDRESS (0x000) +#define BTABLE_ADDRESS (0x000U) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -130,9 +130,9 @@ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { - uint32_t i = 0; + uint32_t i = 0U; - uint32_t wInterrupt_Mask = 0; + uint32_t wInterrupt_Mask = 0U; /* Check the PCD handle allocation */ if(hpcd == NULL) @@ -155,27 +155,27 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->State = HAL_PCD_STATE_BUSY; /* Init endpoints structures */ - for (i = 0; i < hpcd->Init.dev_endpoints ; i++) + for (i = 0U; i < hpcd->Init.dev_endpoints ; i++) { /* Init ep structure */ - hpcd->IN_ep[i].is_in = 1; + hpcd->IN_ep[i].is_in = 1U; hpcd->IN_ep[i].num = i; /* Control until ep is actvated */ hpcd->IN_ep[i].type = PCD_EP_TYPE_CTRL; - hpcd->IN_ep[i].maxpacket = 0; - hpcd->IN_ep[i].xfer_buff = 0; - hpcd->IN_ep[i].xfer_len = 0; + hpcd->IN_ep[i].maxpacket = 0U; + hpcd->IN_ep[i].xfer_buff = 0U; + hpcd->IN_ep[i].xfer_len = 0U; } - for (i = 0; i < hpcd->Init.dev_endpoints ; i++) + for (i = 0U; i < hpcd->Init.dev_endpoints ; i++) { - hpcd->OUT_ep[i].is_in = 0; + hpcd->OUT_ep[i].is_in = 0U; hpcd->OUT_ep[i].num = i; /* Control until ep is activated */ hpcd->OUT_ep[i].type = PCD_EP_TYPE_CTRL; - hpcd->OUT_ep[i].maxpacket = 0; - hpcd->OUT_ep[i].xfer_buff = 0; - hpcd->OUT_ep[i].xfer_len = 0; + hpcd->OUT_ep[i].maxpacket = 0U; + hpcd->OUT_ep[i].xfer_buff = 0U; + hpcd->OUT_ep[i].xfer_len = 0U; } /* Init Device */ @@ -183,10 +183,10 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->Instance->CNTR = USB_CNTR_FRES; /*CNTR_FRES = 0*/ - hpcd->Instance->CNTR = 0; + hpcd->Instance->CNTR = 0U; /*Clear pending interrupts*/ - hpcd->Instance->ISTR = 0; + hpcd->Instance->ISTR = 0U; /*Set Btable Adress*/ hpcd->Instance->BTABLE = BTABLE_ADDRESS; @@ -198,7 +198,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /*Set interrupt mask*/ hpcd->Instance->CNTR = wInterrupt_Mask; - hpcd->USB_Address = 0; + hpcd->USB_Address = 0U; hpcd->State= HAL_PCD_STATE_READY; return HAL_OK; @@ -305,7 +305,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) hpcd->Instance->CNTR = USB_CNTR_FRES; /* clear interrupt status register */ - hpcd->Instance->ISTR = 0; + hpcd->Instance->ISTR = 0U; /* switch-off device */ hpcd->Instance->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN); @@ -321,7 +321,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { - uint32_t wInterrupt_Mask = 0; + uint32_t wInterrupt_Mask = 0U; if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR)) { @@ -334,7 +334,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); HAL_PCD_ResetCallback(hpcd); - HAL_PCD_SetAddress(hpcd, 0); + HAL_PCD_SetAddress(hpcd, 0U); } if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR)) @@ -373,7 +373,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) hpcd->Instance->CNTR |= USB_CNTR_FSUSP; hpcd->Instance->CNTR |= USB_CNTR_LPMODE; - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0) + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0U) { HAL_PCD_SuspendCallback(hpcd); } @@ -626,7 +626,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { __HAL_LOCK(hpcd); - if(address == 0) + if(address == 0U) { /* set device address and enable function */ hpcd->Instance->DADDR = USB_DADDR_EF; @@ -652,17 +652,17 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; - if ((ep_addr & 0x80) == 0x80) + if ((ep_addr & 0x80U) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; } else { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; } - ep->num = ep_addr & 0x7F; + ep->num = ep_addr & 0x7FU; - ep->is_in = (0x80 & ep_addr) != 0; + ep->is_in = (0x80U & ep_addr) != 0U; ep->maxpacket = ep_mps; ep->type = ep_type; @@ -687,7 +687,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num); - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { if (ep->is_in) { @@ -716,7 +716,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint /*Set buffer address for double buffered mode*/ PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1); - if (ep->is_in==0) + if (ep->is_in==0U) { /* Clear the data toggle bits for the endpoint IN/OUT*/ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); @@ -755,21 +755,21 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { PCD_EPTypeDef *ep; - if ((ep_addr & 0x80) == 0x80) + if ((ep_addr & 0x80U) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; } else { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; } - ep->num = ep_addr & 0x7F; + ep->num = ep_addr & 0x7FU; - ep->is_in = (0x80 & ep_addr) != 0; + ep->is_in = (0x80U & ep_addr) != 0U; __HAL_LOCK(hpcd); - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { if (ep->is_in) { @@ -787,7 +787,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) /*Double Buffer*/ else { - if (ep->is_in==0) + if (ep->is_in==0U) { /* Clear the data toggle bits for the endpoint IN/OUT*/ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); @@ -829,14 +829,14 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u PCD_EPTypeDef *ep; - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; /*setup and start the Xfer */ ep->xfer_buff = pBuf; ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 0; - ep->num = ep_addr & 0x7F; + ep->xfer_count = 0U; + ep->is_in = 0U; + ep->num = ep_addr & 0x7FU; __HAL_LOCK(hpcd); @@ -849,11 +849,11 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u else { len=ep->xfer_len; - ep->xfer_len =0; + ep->xfer_len =0U; } /* configure and validate Rx endpoint */ - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { /*Set RX buffer count*/ PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len); @@ -879,7 +879,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u */ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count; + return hpcd->OUT_ep[ep_addr & 0x7FU].xfer_count; } /** * @brief Send an amount of data @@ -892,16 +892,16 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { PCD_EPTypeDef *ep; - uint16_t pmabuffer = 0; + uint16_t pmabuffer = 0U; - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; /*setup and start the Xfer */ ep->xfer_buff = pBuf; ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 1; - ep->num = ep_addr & 0x7F; + ep->xfer_count = 0U; + ep->is_in = 1U; + ep->num = ep_addr & 0x7FU; __HAL_LOCK(hpcd); @@ -914,11 +914,11 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, else { len=ep->xfer_len; - ep->xfer_len =0; + ep->xfer_len =0U; } /* configure and validate Tx endpoint */ - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, len); PCD_SET_EP_TX_CNT(hpcd->Instance, ep->num, len); @@ -961,20 +961,20 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) __HAL_LOCK(hpcd); - if ((0x80 & ep_addr) == 0x80) + if ((0x80U & ep_addr) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; } else { ep = &hpcd->OUT_ep[ep_addr]; } - ep->is_stall = 1; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); + ep->is_stall = 1U; + ep->num = ep_addr & 0x7FU; + ep->is_in = ((ep_addr & 0x80U) == 0x80U); - if (ep->num == 0) + if (ep->num == 0U) { /* This macro sets STALL status for RX & TX*/ PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); @@ -1005,18 +1005,18 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { PCD_EPTypeDef *ep; - if ((0x80 & ep_addr) == 0x80) + if ((0x80U & ep_addr) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; } else { ep = &hpcd->OUT_ep[ep_addr]; } - ep->is_stall = 0; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); + ep->is_stall = 0U; + ep->num = ep_addr & 0x7FU; + ep->is_in = ((ep_addr & 0x80U) == 0x80U); __HAL_LOCK(hpcd); @@ -1120,17 +1120,17 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) */ void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { - uint32_t n = (wNBytes + 1) >> 1; + uint32_t n = (wNBytes + 1U) >> 1U; uint32_t i; uint16_t temp1, temp2; uint16_t *pdwVal; - pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400); + pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400U); - for (i = n; i != 0; i--) + for (i = n; i != 0U; i--) { temp1 = (uint16_t) * pbUsrBuf; pbUsrBuf++; - temp2 = temp1 | (uint16_t) * pbUsrBuf << 8; + temp2 = temp1 | (uint16_t) * pbUsrBuf << 8U; *pdwVal++ = temp2; pbUsrBuf++; } @@ -1146,11 +1146,11 @@ void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, u */ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { - uint32_t n = (wNBytes + 1) >> 1; + uint32_t n = (wNBytes + 1U) >> 1U; uint32_t i; uint16_t *pdwVal; - pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400); - for (i = n; i != 0; i--) + pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400U); + for (i = n; i != 0U; i--) { *(uint16_t*)pbUsrBuf++ = *pdwVal++; pbUsrBuf++; @@ -1164,23 +1164,23 @@ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { PCD_EPTypeDef *ep; - uint16_t count=0; + uint16_t count=0U; uint8_t EPindex; __IO uint16_t wIstr; - __IO uint16_t wEPVal = 0; + __IO uint16_t wEPVal = 0U; /* stay in loop while pending interrupts */ - while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0) + while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0U) { /* extract highest priority endpoint number */ EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); - if (EPindex == 0) + if (EPindex == 0U) { /* Decode and service control endpoint interrupt */ /* DIR bit = origin of the interrupt */ - if ((wIstr & USB_ISTR_DIR) == 0) + if ((wIstr & USB_ISTR_DIR) == 0U) { /* DIR = 0 */ @@ -1193,13 +1193,13 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) ep->xfer_buff += ep->xfer_count; /* TX COMPLETE */ - HAL_PCD_DataInStageCallback(hpcd, 0); + HAL_PCD_DataInStageCallback(hpcd, 0U); - if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0)) + if((hpcd->USB_Address > 0U)&& ( ep->xfer_len == 0U)) { hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF); - hpcd->USB_Address = 0; + hpcd->USB_Address = 0U; } } @@ -1212,7 +1212,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) ep = &hpcd->OUT_ep[0]; wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - if ((wEPVal & USB_EP_SETUP) != 0) + if ((wEPVal & USB_EP_SETUP) != 0U) { /* Get SETUP Packet*/ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); @@ -1224,20 +1224,20 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) HAL_PCD_SetupStageCallback(hpcd); } - else if ((wEPVal & USB_EP_CTR_RX) != 0) + else if ((wEPVal & USB_EP_CTR_RX) != 0U) { PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); /* Get Control Data OUT Packet*/ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) + if (ep->xfer_count != 0U) { PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); ep->xfer_buff+=ep->xfer_count; } /* Process Control Data OUT Packet*/ - HAL_PCD_DataOutStageCallback(hpcd, 0); + HAL_PCD_DataOutStageCallback(hpcd, 0U); PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); @@ -1251,17 +1251,17 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* process related endpoint register */ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex); - if ((wEPVal & USB_EP_CTR_RX) != 0) + if ((wEPVal & USB_EP_CTR_RX) != 0U) { /* clear int flag */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex); ep = &hpcd->OUT_ep[EPindex]; /* OUT double Buffering*/ - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if (count != 0) + if (count != 0U) { PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); } @@ -1272,7 +1272,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { /*read from endpoint BUF0Addr buffer*/ count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (count != 0) + if (count != 0U) { PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); } @@ -1281,7 +1281,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { /*read from endpoint BUF1Addr buffer*/ count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (count != 0) + if (count != 0U) { PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); } @@ -1292,7 +1292,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) ep->xfer_count+=count; ep->xfer_buff+=count; - if ((ep->xfer_len == 0) || (count < ep->maxpacket)) + if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) { /* RX COMPLETE */ HAL_PCD_DataOutStageCallback(hpcd, ep->num); @@ -1304,7 +1304,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } /* if((wEPVal & EP_CTR_RX) */ - if ((wEPVal & USB_EP_CTR_TX) != 0) + if ((wEPVal & USB_EP_CTR_TX) != 0U) { ep = &hpcd->IN_ep[EPindex]; @@ -1312,10 +1312,10 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex); /* IN double Buffering*/ - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) + if (ep->xfer_count != 0U) { PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); } @@ -1326,7 +1326,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { /*read from endpoint BUF0Addr buffer*/ ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) + if (ep->xfer_count != 0U) { PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count); } @@ -1335,7 +1335,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { /*read from endpoint BUF1Addr buffer*/ ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) + if (ep->xfer_count != 0U) { PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); } @@ -1347,7 +1347,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) ep->xfer_buff+=ep->xfer_count; /* Zero Length Packet? */ - if (ep->xfer_len == 0) + if (ep->xfer_len == 0U) { /* TX COMPLETE */ HAL_PCD_DataInStageCallback(hpcd, ep->num); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd.h index d585f6b285..6b0507633e 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_pcd.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention @@ -67,11 +67,11 @@ */ typedef enum { - HAL_PCD_STATE_RESET = 0x00, - HAL_PCD_STATE_READY = 0x01, - HAL_PCD_STATE_ERROR = 0x02, - HAL_PCD_STATE_BUSY = 0x03, - HAL_PCD_STATE_TIMEOUT = 0x04 + HAL_PCD_STATE_RESET = 0x00U, + HAL_PCD_STATE_READY = 0x01U, + HAL_PCD_STATE_ERROR = 0x02U, + HAL_PCD_STATE_BUSY = 0x03U, + HAL_PCD_STATE_TIMEOUT = 0x04U } PCD_StateTypeDef; typedef enum @@ -199,18 +199,18 @@ typedef struct */ -#define PCD_ENDP0 ((uint8_t)0) -#define PCD_ENDP1 ((uint8_t)1) -#define PCD_ENDP2 ((uint8_t)2) -#define PCD_ENDP3 ((uint8_t)3) -#define PCD_ENDP4 ((uint8_t)4) -#define PCD_ENDP5 ((uint8_t)5) -#define PCD_ENDP6 ((uint8_t)6) -#define PCD_ENDP7 ((uint8_t)7) +#define PCD_ENDP0 ((uint8_t)0U) +#define PCD_ENDP1 ((uint8_t)1U) +#define PCD_ENDP2 ((uint8_t)2U) +#define PCD_ENDP3 ((uint8_t)3U) +#define PCD_ENDP4 ((uint8_t)4U) +#define PCD_ENDP5 ((uint8_t)5U) +#define PCD_ENDP6 ((uint8_t)6U) +#define PCD_ENDP7 ((uint8_t)7U) /* Endpoint Kind */ -#define PCD_SNG_BUF 0 -#define PCD_DBL_BUF 1 +#define PCD_SNG_BUF 0U +#define PCD_DBL_BUF 1U #define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE @@ -222,8 +222,8 @@ typedef struct /** @defgroup PCD_Speed PCD Speed * @{ */ -#define PCD_SPEED_HIGH 0 /* Not Supported */ -#define PCD_SPEED_FULL 2 +#define PCD_SPEED_HIGH 0U /* Not Supported */ +#define PCD_SPEED_FULL 2U /** * @} */ @@ -231,7 +231,7 @@ typedef struct /** @defgroup PCD_USB_Core_PHY PCD USB Core PHY * @{ */ -#define PCD_PHY_EMBEDDED 2 +#define PCD_PHY_EMBEDDED 2U /** * @} */ @@ -239,10 +239,10 @@ typedef struct /** @defgroup PCD_USB_EP0_MPS PCD USB EP0 MPS * @{ */ -#define DEP0CTL_MPS_64 0 -#define DEP0CTL_MPS_32 1 -#define DEP0CTL_MPS_16 2 -#define DEP0CTL_MPS_8 3 +#define DEP0CTL_MPS_64 0U +#define DEP0CTL_MPS_32 1U +#define DEP0CTL_MPS_16 2U +#define DEP0CTL_MPS_8 3U #define PCD_EP0MPS_64 DEP0CTL_MPS_64 #define PCD_EP0MPS_32 DEP0CTL_MPS_32 @@ -255,10 +255,10 @@ typedef struct /** @defgroup PCD_USB_EP_Type PCD USB EP Type * @{ */ -#define PCD_EP_TYPE_CTRL 0 -#define PCD_EP_TYPE_ISOC 1 -#define PCD_EP_TYPE_BULK 2 -#define PCD_EP_TYPE_INTR 3 +#define PCD_EP_TYPE_CTRL 0U +#define PCD_EP_TYPE_ISOC 1U +#define PCD_EP_TYPE_BULK 2U +#define PCD_EP_TYPE_INTR 3U /** * @} */ @@ -282,10 +282,10 @@ typedef struct /* Internal macros -----------------------------------------------------------*/ /* SetENDPOINT */ -#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&USBx->EP0R + bEpNum * 2)= (uint16_t)wRegValue) +#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&USBx->EP0R + bEpNum * 2U)= (uint16_t)wRegValue) /* GetENDPOINT */ -#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&USBx->EP0R + bEpNum * 2)) +#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&USBx->EP0R + bEpNum * 2U)) @@ -336,9 +336,9 @@ do {\ */ #define PCD_GET_DB_DIR(USBx, bEpNum)\ do {\ - if ((uint16_t)(*PCD_EP_RX_CNT(USBx, bEpNum) & 0xFC00) != 0)\ + if ((uint16_t)(*PCD_EP_RX_CNT(USBx, bEpNum) & 0xFC00U) != 0U)\ return(PCD_EP_DBUF_OUT);\ - else if (((uint16_t)(*PCD_EP_TX_CNT(USBx, bEpNum)) & 0x03FF) != 0)\ + else if (((uint16_t)(*PCD_EP_TX_CNT(USBx, bEpNum)) & 0x03FFU) != 0U)\ return(PCD_EP_DBUF_IN);\ else\ return(PCD_EP_DBUF_ERR);\ @@ -356,10 +356,10 @@ do {\ \ _wRegVal = PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPTX_DTOGMASK;\ /* toggle first bit ? */ \ - if((USB_EPTX_DTOG1 & wState)!= 0) \ + if((USB_EPTX_DTOG1 & wState)!= 0U) \ _wRegVal ^= USB_EPTX_DTOG1; \ /* toggle second bit ? */ \ - if((USB_EPTX_DTOG2 & wState)!= 0) \ + if((USB_EPTX_DTOG2 & wState)!= 0U) \ _wRegVal ^= USB_EPTX_DTOG2; \ PCD_SET_ENDPOINT(USBx, bEpNum, (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ } while(0) /* PCD_SET_EP_TX_STATUS */ @@ -376,10 +376,10 @@ do {\ \ _wRegVal = PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPRX_DTOGMASK;\ /* toggle first bit ? */ \ - if((USB_EPRX_DTOG1 & wState)!= 0) \ + if((USB_EPRX_DTOG1 & wState)!= 0U) \ _wRegVal ^= USB_EPRX_DTOG1; \ /* toggle second bit ? */ \ - if((USB_EPRX_DTOG2 & wState)!= 0) \ + if((USB_EPRX_DTOG2 & wState)!= 0U) \ _wRegVal ^= USB_EPRX_DTOG2; \ PCD_SET_ENDPOINT(USBx, bEpNum, (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ } while(0) /* PCD_SET_EP_RX_STATUS */ @@ -397,16 +397,16 @@ do {\ \ _wRegVal = PCD_GET_ENDPOINT(USBx, bEpNum) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\ /* toggle first bit ? */ \ - if((USB_EPRX_DTOG1 & wStaterx)!= 0) \ + if((USB_EPRX_DTOG1 & wStaterx)!= 0U) \ _wRegVal ^= USB_EPRX_DTOG1; \ /* toggle second bit ? */ \ - if((USB_EPRX_DTOG2 & wStaterx)!= 0) \ + if((USB_EPRX_DTOG2 & wStaterx)!= 0U) \ _wRegVal ^= USB_EPRX_DTOG2; \ /* toggle first bit ? */ \ - if((USB_EPTX_DTOG1 & wStatetx)!= 0) \ + if((USB_EPTX_DTOG1 & wStatetx)!= 0U) \ _wRegVal ^= USB_EPTX_DTOG1; \ /* toggle second bit ? */ \ - if((USB_EPTX_DTOG2 & wStatetx)!= 0) \ + if((USB_EPTX_DTOG2 & wStatetx)!= 0U) \ _wRegVal ^= USB_EPTX_DTOG2; \ PCD_SET_ENDPOINT(USBx, bEpNum, _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \ } while(0) /* PCD_SET_EP_TXRX_STATUS */ @@ -479,9 +479,9 @@ do {\ * @retval None */ #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT(USBx, bEpNum,\ - PCD_GET_ENDPOINT(USBx, bEpNum) & 0x7FFF & USB_EPREG_MASK)) + PCD_GET_ENDPOINT(USBx, bEpNum) & 0x7FFFU & USB_EPREG_MASK)) #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT(USBx, bEpNum,\ - PCD_GET_ENDPOINT(USBx, bEpNum) & 0xFF7F & USB_EPREG_MASK)) + PCD_GET_ENDPOINT(USBx, bEpNum) & 0xFF7FU & USB_EPREG_MASK)) /** * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. @@ -522,10 +522,10 @@ do {\ * @retval None */ #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPADDR_FIELD)) -#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8)+ ((uint32_t)USBx + 0x400))) -#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8+2)+ ((uint32_t)USBx + 0x400))) -#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8+4)+ ((uint32_t)USBx + 0x400))) -#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8+6)+ ((uint32_t)USBx + 0x400))) +#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8U)+ ((uint32_t)USBx + 0x400U))) +#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8U+2U)+ ((uint32_t)USBx + 0x400U))) +#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8U+4U)+ ((uint32_t)USBx + 0x400U))) +#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8U+6U)+ ((uint32_t)USBx + 0x400U))) /** * @brief sets address of the tx/rx buffer. @@ -534,8 +534,8 @@ do {\ * @param wAddr: address to be set (must be word aligned). * @retval None */ -#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS(USBx, bEpNum) = ((wAddr >> 1) << 1)) -#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS(USBx, bEpNum) = ((wAddr >> 1) << 1)) +#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS(USBx, bEpNum) = ((wAddr >> 1U) << 1U)) +#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS(USBx, bEpNum) = ((wAddr >> 1U) << 1U)) /** * @brief Gets address of the tx/rx buffer. @@ -557,14 +557,14 @@ do {\ wNBlocks = wCount >> 5;\ if((wCount & 0x1f) == 0)\ wNBlocks--;\ - *pdwReg = (uint16_t)((wNBlocks << 10) | 0x8000);\ + *pdwReg = (uint16_t)((wNBlocks << 10U) | 0x8000U);\ } while(0) /* PCD_CALC_BLK32 */ #define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) do {\ wNBlocks = wCount >> 1;\ if((wCount & 0x1) != 0)\ wNBlocks++;\ - *pdwReg = (uint16_t)(wNBlocks << 10);\ + *pdwReg = (uint16_t)(wNBlocks << 10U);\ } while(0) /* PCD_CALC_BLK2 */ #define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) do {\ @@ -596,8 +596,8 @@ do {\ * @param bEpNum: Endpoint Number. * @retval Counter value */ -#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT(USBx, bEpNum)) & 0x3ff) -#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT(USBx, bEpNum)) & 0x3ff) +#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT(USBx, bEpNum)) & 0x3ffU) +#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT(USBx, bEpNum)) & 0x3ffU) /** * @brief Sets buffer 0/1 address in a double buffer endpoint. diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd_ex.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd_ex.c index ad3eadf29b..ba0309c8a2 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Extended PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -104,9 +104,9 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep; /* initialize ep structure*/ - if ((0x80 & ep_addr) == 0x80) + if ((0x80U & ep_addr) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; } else { @@ -117,17 +117,17 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, if (ep_kind == PCD_SNG_BUF) { /*Single Buffer*/ - ep->doublebuffer = 0; + ep->doublebuffer = 0U; /*Configure te PMA*/ ep->pmaadress = (uint16_t)pmaadress; } else /*USB_DBL_BUF*/ { /*Double Buffer Endpoint*/ - ep->doublebuffer = 1; + ep->doublebuffer = 1U; /*Configure the PMA*/ - ep->pmaaddr0 = pmaadress & 0xFFFF; - ep->pmaaddr1 = (pmaadress & 0xFFFF0000) >> 16; + ep->pmaaddr0 = pmaadress & 0xFFFFU; + ep->pmaaddr1 = (pmaadress & 0xFFFF0000U) >> 16U; } return HAL_OK; diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd_ex.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd_ex.h index 61598dfa63..4e5f617280 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_pcd.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr.c index e8efb5415e..cb88010464 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_pwr.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief PWR HAL module driver. * * This file provides firmware functions to manage the following @@ -60,10 +60,10 @@ /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask * @{ */ -#define PVD_MODE_IT ((uint32_t)0x00010000) -#define PVD_MODE_EVT ((uint32_t)0x00020000) -#define PVD_RISING_EDGE ((uint32_t)0x00000001) -#define PVD_FALLING_EDGE ((uint32_t)0x00000002) +#define PVD_MODE_IT ((uint32_t)0x00010000U) +#define PVD_MODE_EVT ((uint32_t)0x00020000U) +#define PVD_RISING_EDGE ((uint32_t)0x00000001U) +#define PVD_FALLING_EDGE ((uint32_t)0x00000002U) /** * @} */ @@ -477,7 +477,7 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) */ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); @@ -538,7 +538,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) */ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr.h index 9fd21a4b71..f4ab593778 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_pwr.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention @@ -120,13 +120,13 @@ typedef struct /** @defgroup PWR_PVD_Mode PWR PVD Mode * @{ */ -#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ -#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ /** * @} @@ -135,7 +135,7 @@ typedef struct /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode * @{ */ -#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) +#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U) #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR /** @@ -145,8 +145,8 @@ typedef struct /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry * @{ */ -#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) -#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) /** * @} */ @@ -154,8 +154,8 @@ typedef struct /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry * @{ */ -#define PWR_STOPENTRY_WFI ((uint8_t)0x01) -#define PWR_STOPENTRY_WFE ((uint8_t)0x02) +#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) /** * @} */ @@ -251,7 +251,7 @@ typedef struct * @arg PWR_FLAG_WU: Wake Up flag * @arg PWR_FLAG_SB: StandBy flag */ -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, (__FLAG__) << 2) +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, (__FLAG__) << 2U) /** * @brief Enable interrupt on PVD Exti Line 16. diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr_ex.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr_ex.c index 05cc00ea9f..69534a393d 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -59,7 +59,7 @@ /** @defgroup PWR_Extended_TimeOut_Value PWREx Flag Setting Time Out Value * @{ */ -#define PWR_FLAG_SETTING_DELAY_US 50 +#define PWR_FLAG_SETTING_DELAY_US 50U /** * @} */ @@ -153,16 +153,16 @@ void HAL_PWREx_EnableLowPowerRunMode(void) */ HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) { - uint32_t wait_loop_index = 0; + uint32_t wait_loop_index = 0U; /* Exit the Low Power Run mode */ CLEAR_BIT(PWR->CR, PWR_CR_LPRUN); CLEAR_BIT(PWR->CR, PWR_CR_LPSDSR); /* Wait until REGLPF is reset */ - wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); + wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000U)); - while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->CSR, PWR_CSR_REGLPF))) + while ((wait_loop_index != 0U) && (HAL_IS_BIT_SET(PWR->CSR, PWR_CSR_REGLPF))) { wait_loop_index--; } diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr_ex.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr_ex.h index 4241f1cf2a..aa88fa8754 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of PWR HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.c index 7c3061a6bd..91bff130e3 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_rcc.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.4.0 + * @date 01-October-2015 * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: @@ -122,8 +122,6 @@ #endif extern const uint8_t PLLMulTable[]; /* Defined in CMSIS (system_stm32l0xx.c)*/ -static const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; - /** * @} @@ -187,20 +185,23 @@ static const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, (#) For the STM32L0xx devices, the maximum frequency of the SYSCLK ,HCLK, APB1 and APB2 is 32 MHz. Depending on the device voltage range, the maximum frequency should - be adapted accordingly: - ---------------------------------------------------------------- - | Wait states | HCLK clock frequency (MHz) | - | |------------------------------------------------| - | (Latency) | voltage range | voltage range | - | | 1.65 V - 3.6 V | 2.0 V - 3.6 V | - | |----------------|---------------|---------------| - | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V | - |-------------- |----------------|---------------|---------------| - |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 | - |---------------|----------------|---------------|---------------| - |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32| - ---------------------------------------------------------------- + be adapted accordingly. Refer to the Reference Manual for more details. + @endverbatim + + Table 1. HCLK clock frequency. + +----------------------------------------------------------------+ + | Wait states | HCLK clock frequency (MHz) | + | |------------------------------------------------| + | (Latency) | voltage range | voltage range | + | | 1.65 V - 3.6 V | 2.0 V - 3.6 V | + | |----------------|---------------|---------------| + | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V | + |-------------- |----------------|---------------|---------------| + |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 | + |---------------|----------------|---------------|---------------| + |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32| + +----------------------------------------------------------------+ * @{ */ @@ -209,7 +210,7 @@ static const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, * @note The default reset state of the clock configuration is given below: * - MSI ON and used as system clock source (MSI range is not modified * - by this function, it keep the value configured by user application) - * - HSI, HSE and PLL OFF + * - HSI, HSI_OUT, HSE and PLL OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS and MCO OFF * - All interrupts disabled @@ -218,9 +219,43 @@ static const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, * @note -HSI48, LSI, LSE and RTC clocks * @retval None */ -__weak void HAL_RCC_DeInit(void) +void HAL_RCC_DeInit(void) { - /* This function is now defined in the file stm32L0xx_rcc_ex.c */ + __IO uint32_t tmpreg; + + /* Set MSION bit */ + SET_BIT(RCC->CR, RCC_CR_MSION); + +#if defined(STM32L073xx) || defined(STM32L083xx) || \ + defined(STM32L072xx) || defined(STM32L082xx) || \ + defined(STM32L071xx) || defined(STM32L081xx) || \ + defined(STM32L031xx) || defined(STM32L041xx) + /* Reset HSE, HSI, CSS, PLL */ + CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \ + RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON); +#elif defined(STM32L011xx) || defined(STM32L021xx) + CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \ + RCC_CR_HSEON | RCC_CR_PLLON); +#else + CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \ + RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON); +#endif + + /* Delay after an RCC peripheral clock */ \ + tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); \ + UNUSED(tmpreg); + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIER); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = MSI_VALUE; } /** @@ -240,7 +275,7 @@ __weak void HAL_RCC_DeInit(void) HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(RCC_OscInitStruct != NULL); @@ -382,6 +417,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); } @@ -701,7 +739,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(RCC_ClkInitStruct != NULL); @@ -850,6 +888,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); } + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); @@ -1000,26 +1041,26 @@ void HAL_RCC_EnableCSS(void) */ uint32_t HAL_RCC_GetSysClockFreq(void) { - uint32_t pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; - uint32_t sysclockfreq = 0; + uint32_t pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; + uint32_t sysclockfreq = 0U; /* Get SYSCLK source -------------------------------------------------------*/ /*MSI frequency range in HZ*/ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; switch (RCC->CFGR & RCC_CFGR_SWS) { case RCC_CFGR_SWS_MSI: /* MSI used as system clock */ { - sysclockfreq = (32768 * (1 << (msirange + 1))); + sysclockfreq = (32768U * (1U << (msirange + 1U))); break; } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock */ { - if ((RCC->CR & RCC_CR_HSIDIVF) != 0) + if ((RCC->CR & RCC_CR_HSIDIVF) != 0U) { - sysclockfreq = (HSI_VALUE >> 2); + sysclockfreq = (HSI_VALUE >> 2U); } else { @@ -1037,17 +1078,17 @@ uint32_t HAL_RCC_GetSysClockFreq(void) /* Get PLL clock source and multiplication factor ----------------------*/ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; - pllmul = PLLMulTable[(pllmul >> 18)]; - plldiv = (plldiv >> 22) + 1; + pllmul = PLLMulTable[(pllmul >> 18U)]; + plldiv = (plldiv >> 22U) + 1U; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; if (pllsource == RCC_CFGR_PLLSRC_HSI) { /* HSI oscillator clock selected as PLL clock source */ - if ((RCC->CR & RCC_CR_HSIDIVF) != 0) + if ((RCC->CR & RCC_CR_HSIDIVF) != 0U) { - sysclockfreq = (((HSI_VALUE >> 2) * pllmul) / plldiv); + sysclockfreq = (((HSI_VALUE >> 2U) * pllmul) / plldiv); } else { @@ -1063,7 +1104,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void) } default: /* MSI used as system clock */ { - sysclockfreq = (32768 * (1 << (msirange + 1))); + sysclockfreq = (32768U * (1U << (msirange + 1U))); break; } } @@ -1081,10 +1122,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void) */ uint32_t HAL_RCC_GetHCLKFreq(void) { - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - return (SystemCoreClock); - } /** @@ -1096,7 +1134,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void) uint32_t HAL_RCC_GetPCLK1Freq(void) { - return ( HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[((RCC->CFGR & RCC_CFGR_PPRE1) >> 8)]); + return ( HAL_RCC_GetHCLKFreq() >> APBPrescTable[((RCC->CFGR & RCC_CFGR_PPRE1) >> 8U)]); } @@ -1109,7 +1147,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) uint32_t HAL_RCC_GetPCLK2Freq(void) { - return ( HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[((RCC->CFGR & RCC_CFGR_PPRE2) >> 11)]); + return ( HAL_RCC_GetHCLKFreq() >> APBPrescTable[((RCC->CFGR & RCC_CFGR_PPRE2) >> 11U)]); } @@ -1153,8 +1191,8 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->MSIState = RCC_MSI_OFF; } - RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->CR &RCC_ICSCR_MSITRIM) >> 24); - RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR &RCC_ICSCR_MSIRANGE) >> 13); + RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->CR &RCC_ICSCR_MSITRIM) >> 24U); + RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR &RCC_ICSCR_MSIRANGE) >> 13U); #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) /* Get the HSI48 configuration -----------------------------------------------*/ @@ -1178,7 +1216,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR &RCC_ICSCR_HSITRIM) >> 8); + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR &RCC_ICSCR_HSITRIM) >> 8U); /* Get the LSE configuration -----------------------------------------------*/ if((RCC->CSR &RCC_CSR_LSEBYP) == RCC_CSR_LSEBYP) @@ -1214,8 +1252,8 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; } RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); - RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL) >> 18; - RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV) >> 22; + RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL) >> 18U; + RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV) >> 22U; } @@ -1242,7 +1280,7 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); /* Get the APB2 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.h index f072112aba..28706b47f9 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_rcc.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention @@ -153,18 +153,18 @@ typedef struct #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) /* --- CR Register ---*/ /* Alias word address of HSION bit */ -#define RCC_CR_OFFSET (RCC_OFFSET + 0x00) +#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U) /* --- CFGR Register ---*/ /* Alias word address of I2SSRC bit */ -#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08) +#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U) /* --- CSR Register ---*/ -#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74) +#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U) /* CR register byte 3 (Bits[23:16]) base address */ -#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802) +#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802U) /* CIER register byte 0 (Bits[0:8]) base address */ -#define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10 + 0x00)) +#define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10U + 0x00U)) /** * @} @@ -178,7 +178,7 @@ typedef struct /** @defgroup RCC_Timeout_Value Timeout Values * @{ */ -#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100U) /* 100 ms */ #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT #define RCC_HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT /** @@ -188,14 +188,14 @@ typedef struct /** @defgroup RCC_Oscillator_Type Oscillator Type * @{ */ -#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) /*!< Oscillator configuration unchanged */ -#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) /*!< HSE to configure */ -#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) /*!< HSI to configure */ -#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) /*!< LSE to configure */ -#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) /*!< LSI to configure */ -#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010) /*!< MSI to configure */ +#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) /*!< Oscillator configuration unchanged */ +#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) /*!< HSE to configure */ +#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) /*!< HSI to configure */ +#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) /*!< LSE to configure */ +#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) /*!< LSI to configure */ +#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010U) /*!< MSI to configure */ #if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) -#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020) +#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020U) #endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */ /** @@ -205,7 +205,7 @@ typedef struct /** @defgroup RCC_HSE_Config RCC HSE Config * @{ */ -#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_OFF ((uint32_t)0x00000000U) #define RCC_HSE_ON RCC_CR_HSEON #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) @@ -216,7 +216,7 @@ typedef struct /** @defgroup RCC_LSE_Config RCC LSE Config * @{ */ -#define RCC_LSE_OFF ((uint32_t)0x00000000) +#define RCC_LSE_OFF ((uint32_t)0x00000000U) #define RCC_LSE_ON RCC_CSR_LSEON #define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP | RCC_CSR_LSEON)) @@ -229,8 +229,8 @@ typedef struct /** @defgroup RCC_LSI_Config RCC LSI Config * @{ */ -#define RCC_LSI_OFF ((uint8_t)0x00) -#define RCC_LSI_ON ((uint8_t)0x01) +#define RCC_LSI_OFF ((uint8_t)0x00U) +#define RCC_LSI_ON ((uint8_t)0x01U) #define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /* Default MSI calibration trimming value */ @@ -242,10 +242,10 @@ typedef struct /** @defgroup RCC_MSI_Config RCC MSI Config * @{ */ -#define RCC_MSI_OFF ((uint8_t)0x00) -#define RCC_MSI_ON ((uint8_t)0x01) +#define RCC_MSI_OFF ((uint8_t)0x00U) +#define RCC_MSI_ON ((uint8_t)0x01U) -#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */ +#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */ /** * @} @@ -255,8 +255,8 @@ typedef struct /** @defgroup RCC_HSI48_Config RCC HSI48 Configuration * @{ */ -#define RCC_HSI48_OFF ((uint8_t)0x00) -#define RCC_HSI48_ON ((uint8_t)0x01) +#define RCC_HSI48_OFF ((uint8_t)0x00U) +#define RCC_HSI48_ON ((uint8_t)0x01U) /** * @} @@ -266,9 +266,9 @@ typedef struct /** @defgroup RCC_PLL_Config RCC PLL Config * @{ */ -#define RCC_PLL_NONE ((uint8_t)0x00) -#define RCC_PLL_OFF ((uint8_t)0x01) -#define RCC_PLL_ON ((uint8_t)0x02) +#define RCC_PLL_NONE ((uint8_t)0x00U) +#define RCC_PLL_OFF ((uint8_t)0x01U) +#define RCC_PLL_ON ((uint8_t)0x02U) /** * @} @@ -335,10 +335,10 @@ typedef struct /** @defgroup RCC_System_Clock_Type RCC System Clock Type * @{ */ -#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */ -#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */ -#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */ -#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /*!< PCLK2 to configure */ +#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) /*!< PCLK1 to configure */ +#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) /*!< PCLK2 to configure */ /** * @} */ @@ -396,7 +396,7 @@ typedef struct /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source * @{ */ -#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) +#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U) #define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE #define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI #define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE @@ -454,11 +454,11 @@ typedef struct /** @defgroup RCC_MCO_Index RCC MCO Index * @{ */ -#define RCC_MCO1 ((uint32_t)0x00000000) -#define RCC_MCO2 ((uint32_t)0x00000001) +#define RCC_MCO1 ((uint32_t)0x00000000U) +#define RCC_MCO2 ((uint32_t)0x00000001U) #if defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L073xx) || defined(STM32L083xx) || \ defined(STM32L072xx) || defined(STM32L082xx) || defined(STM32L071xx) || defined(STM32L081xx) -#define RCC_MCO3 ((uint32_t)0x00000002) +#define RCC_MCO3 ((uint32_t)0x00000002U) #endif /** @@ -495,28 +495,28 @@ typedef struct * @{ */ /* Flags in the CR register */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x22) -#define RCC_FLAG_HSIDIV ((uint8_t)0x24) -#define RCC_FLAG_MSIRDY ((uint8_t)0x29) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_HSIRDY ((uint8_t)0x22U) +#define RCC_FLAG_HSIDIV ((uint8_t)0x24U) +#define RCC_FLAG_MSIRDY ((uint8_t)0x29U) +#define RCC_FLAG_HSERDY ((uint8_t)0x31U) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39U) /* Flags in the CSR register */ -#define RCC_FLAG_LSERDY ((uint8_t)0x49) -#define RCC_FLAG_LSECSS ((uint8_t)0x4E) -#define RCC_FLAG_LSIRDY ((uint8_t)0x41) -#define RCC_FLAG_FWRST ((uint8_t)0x58) -#define RCC_FLAG_OBLRST ((uint8_t)0x59) -#define RCC_FLAG_PINRST ((uint8_t)0x5A) -#define RCC_FLAG_PORRST ((uint8_t)0x5B) -#define RCC_FLAG_SFTRST ((uint8_t)0x5C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x5D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x5E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x5F) +#define RCC_FLAG_LSERDY ((uint8_t)0x49U) +#define RCC_FLAG_LSECSS ((uint8_t)0x4EU) +#define RCC_FLAG_LSIRDY ((uint8_t)0x41U) +#define RCC_FLAG_FWRST ((uint8_t)0x58U) +#define RCC_FLAG_OBLRST ((uint8_t)0x59U) +#define RCC_FLAG_PINRST ((uint8_t)0x5AU) +#define RCC_FLAG_PORRST ((uint8_t)0x5BU) +#define RCC_FLAG_SFTRST ((uint8_t)0x5CU) +#define RCC_FLAG_IWDGRST ((uint8_t)0x5DU) +#define RCC_FLAG_WWDGRST ((uint8_t)0x5EU) +#define RCC_FLAG_LPWRRST ((uint8_t)0x5FU) #if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) /* Flags in the CRRCR register */ -#define RCC_FLAG_HSI48RDY ((uint8_t)0x61) +#define RCC_FLAG_HSI48RDY ((uint8_t)0x61U) #endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */ @@ -718,12 +718,12 @@ typedef struct * @brief Force or release AHB peripheral reset. * @{ */ -#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF) +#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST)) #define __HAL_RCC_MIF_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST)) #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST)) -#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) +#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00U) #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST)) #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST)) #define __HAL_RCC_MIF_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST)) @@ -735,13 +735,13 @@ typedef struct * @brief Force or release IOPORT peripheral reset. * @{ */ -#define __HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFF) +#define __HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFFU) #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST)) #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST)) #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST)) #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST)) -#define __HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00) +#define __HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00U) #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST)) #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST)) #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST)) @@ -755,11 +755,11 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ -#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) #define __HAL_RCC_WWDG_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST)) -#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) #define __HAL_RCC_WWDG_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST)) @@ -771,11 +771,11 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST)) #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST)) -#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) #define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST)) #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST)) /** @@ -980,7 +980,7 @@ typedef struct * This parameter must be a number between 0 and 0x1F. */ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\ - RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << 8)) + RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << 8U)) /** @brief Macro to enable or disable the Internal High Speed oscillator (HSI). * @note After enabling the HSI, the application software should wait on @@ -1030,7 +1030,7 @@ typedef struct * This parameter must be a number between 0 and 0xFF. */ #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\ - RCC_ICSCR_MSITRIM, (uint32_t)(__MSICalibrationValue__) << 24)) + RCC_ICSCR_MSITRIM, (uint32_t)(__MSICalibrationValue__) << 24U)) /** * @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range. @@ -1064,7 +1064,7 @@ typedef struct */ #define __HAL_RCC_GET_MSI_RANGE() \ - ((uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE) >> 12)) + ((uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE) >> 12U)) /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). * @note After enabling the LSI, the application software should wait on @@ -1207,10 +1207,10 @@ typedef struct * @brief Get the RTC and LCD clock (RTCCLK / LCDCLK). * * @retval The clock source can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() + * @arg RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock + * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSOURCE_HSE_DIVX: HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() * */ #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL))) @@ -1219,14 +1219,15 @@ typedef struct * @brief Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK). * * @retval Returned value can be one of the following values: - * @arg @ref RCC_RTC_HSE_DIV_2: HSE divided by 2 selected as RTC clock - * @arg @ref RCC_RTC_HSE_DIV_4: HSE divided by 4 selected as RTC clock - * @arg @ref RCC_RTC_HSE_DIV_8: HSE divided by 8 selected as RTC clock - * @arg @ref RCC_RTC_HSE_DIV_16: HSE divided by 16 selected as RTC clock + * @arg RCC_RTC_HSE_DIV_2: HSE divided by 2 selected as RTC clock + * @arg RCC_RTC_HSE_DIV_4: HSE divided by 4 selected as RTC clock + * @arg RCC_RTC_HSE_DIV_8: HSE divided by 8 selected as RTC clock + * @arg RCC_RTC_HSE_DIV_16: HSE divided by 16 selected as RTC clock * */ #define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE))) + /** @brief Macros to enable or disable the main PLL. * @note After enabling the main PLL, the application software should wait on * PLLRDY flag to be set indicating that PLL clock is stable and can @@ -1428,8 +1429,8 @@ typedef struct * @arg RCC_FLAG_LPWRRST: Low Power reset * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->CSR :((((__FLAG__) >> 5) == 3)? \ - RCC->CRRCR :RCC->CIFR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 ) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->CSR :((((__FLAG__) >> 5U) == 3U)? \ + RCC->CRRCR :RCC->CIFR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U ) ? 1U : 0U ) /** * @} @@ -1445,7 +1446,7 @@ typedef struct * @{ */ /* Defines used for Flags */ -#define RCC_FLAG_MASK ((uint8_t)0x1F) +#define RCC_FLAG_MASK ((uint8_t)0x1FU) /** * @} @@ -1457,9 +1458,9 @@ typedef struct */ #if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) -#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x3F) +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x3FU) #else -#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x1F) +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x1FU) #endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */ #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ @@ -1493,7 +1494,7 @@ typedef struct #define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLLDIV_2) || ((__DIV__) == RCC_PLLDIV_3) || \ ((__DIV__) == RCC_PLLDIV_4)) -#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15)) +#define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U)) #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.c index f3dff8ec89..7466e9989a 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Extended RCC HAL module driver. * * This file provides firmware functions to manage the following @@ -105,9 +105,9 @@ * @{ */ /* Bit position in register */ -#define CRS_CFGR_FELIM_BITNUMBER 16 -#define CRS_CR_TRIM_BITNUMBER 8 -#define CRS_ISR_FECAP_BITNUMBER 16 +#define CRS_CFGR_FELIM_BITNUMBER 16U +#define CRS_CR_TRIM_BITNUMBER 8U +#define CRS_ISR_FECAP_BITNUMBER 16U #if defined(USB) extern const uint8_t PLLMulTable[]; @@ -135,56 +135,6 @@ extern const uint8_t PLLMulTable[]; * @{ */ -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - MSI ON and used as system clock source (MSI range is not modified - * - by this function, it keep the value configured by user application) - * - HSI, HSI_OUT, HSE and PLL OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS and MCO OFF - * - All interrupts disabled - * @note This function does not modify the configuration of the - * @note -Peripheral clocks - * @note -HSI48, LSI, LSE and RTC clocks - * @retval None - */ -void HAL_RCC_DeInit(void) -{ - __IO uint32_t tmpreg; - - /* Set MSION bit */ - SET_BIT(RCC->CR, RCC_CR_MSION); - -#if defined(STM32L073xx) || defined(STM32L083xx) || \ - defined(STM32L072xx) || defined(STM32L082xx) || \ - defined(STM32L071xx) || defined(STM32L081xx) || \ - defined(STM32L031xx) || defined(STM32L041xx) - /* Reset HSE, HSI, CSS, PLL */ - CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \ - RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON); -#elif defined(STM32L011xx) || defined(STM32L021xx) - CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \ - RCC_CR_HSEON | RCC_CR_PLLON); -#else - CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \ - RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON); -#endif - - /* Delay after an RCC peripheral clock */ \ - tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); \ - UNUSED(tmpreg); - - /* Reset HSEBYP bit */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); - - /* Reset CFGR register */ - CLEAR_REG(RCC->CFGR); - - /* Disable all interrupts */ - CLEAR_REG(RCC->CIER); -} - /** * @brief Initializes the RCC extended peripherals clocks * @note Initializes the RCC extended peripherals clocks according to the specified parameters in the @@ -198,8 +148,8 @@ void HAL_RCC_DeInit(void) */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { - uint32_t tickstart = 0; - uint32_t tmpreg = 0; + uint32_t tickstart = 0U; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); @@ -448,9 +398,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { - uint32_t srcclk = 0, clkprediv = 0, frequency = 0; + uint32_t srcclk = 0U, clkprediv = 0U, frequency = 0U; #if defined(USB) - uint32_t pllmul = 0, plldiv = 0, pllvco = 0; + uint32_t pllmul = 0U, plldiv = 0U, pllvco = 0U; #endif /* USB */ /* Check the parameters */ @@ -483,22 +433,22 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */ { - frequency = HSE_VALUE / 16; + frequency = HSE_VALUE / 16U; break; } case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */ { - frequency = HSE_VALUE / 8; + frequency = HSE_VALUE / 8U; break; } case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */ { - frequency = HSE_VALUE / 4; + frequency = HSE_VALUE / 4U; break; } default: { - frequency = HSE_VALUE / 2; + frequency = HSE_VALUE / 2U; break; } } @@ -506,7 +456,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for RTC*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -538,22 +488,22 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */ { - frequency = HSE_VALUE / 16; + frequency = HSE_VALUE / 16U; break; } case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */ { - frequency = HSE_VALUE / 8; + frequency = HSE_VALUE / 8U; break; } case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */ { - frequency = HSE_VALUE / 4; + frequency = HSE_VALUE / 4U; break; } default: { - frequency = HSE_VALUE / 2; + frequency = HSE_VALUE / 2U; break; } } @@ -561,12 +511,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for LCD*/ else { - frequency = 0; + frequency = 0U; } break; } #endif /* LCD */ + #if defined(USB) case RCC_PERIPHCLK_USB: { @@ -578,15 +529,15 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get PLL clock source and multiplication factor ----------------------*/ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; - pllmul = PLLMulTable[(pllmul >> 18)]; - plldiv = (plldiv >> 22) + 1; + pllmul = PLLMulTable[(pllmul >> 18U)]; + plldiv = (plldiv >> 22U) + 1U; /* Compute PLL clock input */ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) { - if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0) + if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) { - pllvco = (HSI_VALUE >> 2); + pllvco = (HSI_VALUE >> 2U); } else { @@ -608,7 +559,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else /* RCC_USBCLKSOURCE_NONE */ { - frequency = 0; + frequency = 0U; } break; } @@ -642,7 +593,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for USART1*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -675,7 +626,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for USART2*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -707,7 +658,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for LPUART1*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -734,7 +685,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for I2C1*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -749,7 +700,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - frequency = 0; + frequency = 0U; } break; } @@ -779,7 +730,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for I2C3*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -966,15 +917,15 @@ void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo * This parameter can be a combination of the following values: * @arg RCC_CRS_TIMEOUT * @arg RCC_CRS_SYNCOK -* @arg RCC_CRS_SYNCWARM +* @arg RCC_CRS_SYNCWARN * @arg RCC_CRS_SYNCERR * @arg RCC_CRS_SYNCMISS -* @arg RCC_CRS_TRIMOV +* @arg RCC_CRS_TRIMOVF */ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) { uint32_t crsstatus = RCC_CRS_NONE; - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Get timeout */ tickstart = HAL_GetTick(); @@ -984,7 +935,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { crsstatus = RCC_CRS_TIMEOUT; } @@ -1003,7 +954,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) { /* CRS SYNC warning */ - crsstatus |= RCC_CRS_SYNCWARM; + crsstatus |= RCC_CRS_SYNCWARN; /* Clear CRS SYNCWARN bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); @@ -1013,7 +964,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) { /* CRS SYNC Error */ - crsstatus |= RCC_CRS_TRIMOV; + crsstatus |= RCC_CRS_TRIMOVF; /* Clear CRS Error bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); @@ -1056,9 +1007,8 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) */ void HAL_RCCEx_EnableHSI48_VREFINT(void) { - /* Enable the Buffer for the ADC by setting EN_VREFINT bit */ - /* and the SYSCFG_CFGR3_ENREF_HSI48 in the CFGR3 register */ - SET_BIT (SYSCFG->CFGR3, (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT)); + /* Enable the Buffer for the ADC by setting SYSCFG_CFGR3_ENREF_HSI48 bit in SYSCFG_CFGR3 register */ + SET_BIT (SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48); } /** @@ -1068,9 +1018,8 @@ void HAL_RCCEx_EnableHSI48_VREFINT(void) */ void HAL_RCCEx_DisableHSI48_VREFINT(void) { - /* Disable the Vrefint by resetting SYSCFG_CFGR3_ENREF_HSI48 bit */ - /* and the EN_VREFINT bit in the CFGR3 register */ - CLEAR_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT)); + /* Disable the Vrefint by resetting SYSCFG_CFGR3_ENREF_HSI48 bit in SYSCFG_CFGR3 register */ + CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48); } #endif /* !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.h index 42d32b8a38..255e3f41e9 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention @@ -153,13 +153,13 @@ typedef struct * @brief RCC CRS Status definition */ -#define RCC_CRS_NONE ((uint32_t) 0x00000000) -#define RCC_CRS_TIMEOUT ((uint32_t) 0x00000001) -#define RCC_CRS_SYNCOK ((uint32_t) 0x00000002) -#define RCC_CRS_SYNCWARM ((uint32_t) 0x00000004) -#define RCC_CRS_SYNCERR ((uint32_t) 0x00000008) -#define RCC_CRS_SYNCMISS ((uint32_t) 0x00000010) -#define RCC_CRS_TRIMOV ((uint32_t) 0x00000020) +#define RCC_CRS_NONE ((uint32_t) 0x00000000U) +#define RCC_CRS_TIMEOUT ((uint32_t) 0x00000001U) +#define RCC_CRS_SYNCOK ((uint32_t) 0x00000002U) +#define RCC_CRS_SYNCWARN ((uint32_t) 0x00000004U) +#define RCC_CRS_SYNCERR ((uint32_t) 0x00000008U) +#define RCC_CRS_SYNCMISS ((uint32_t) 0x00000010U) +#define RCC_CRS_TRIMOVF ((uint32_t) 0x00000020U) /** * @} @@ -232,37 +232,37 @@ typedef struct */ #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) -#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) -#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010) -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020) -#define RCC_PERIPHCLK_USB ((uint32_t)0x00000040) -#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080) +#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001U) +#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002U) +#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004U) +#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008U) +#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010U) +#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U) +#define RCC_PERIPHCLK_USB ((uint32_t)0x00000040U) +#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080U) #if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) -#define RCC_PERIPHCLK_LCD ((uint32_t)0x00000800) +#define RCC_PERIPHCLK_LCD ((uint32_t)0x00000800U) #endif #if defined (STM32L072xx) || defined(STM32L073xx) || defined(STM32L082xx) || defined(STM32L083xx) -#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100) +#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100U) #endif #else /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */ #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) +#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001U) #endif -#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) -#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008) +#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002U) +#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004U) +#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008U) #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010) +#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010U) #endif -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020) -#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080) +#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U) +#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080U) #if defined(STM32L071xx) || defined(STM32L081xx) -#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100) +#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100U) #endif #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */ @@ -273,7 +273,7 @@ typedef struct /** @defgroup RCCEx_USART1_Clock_Source RCC USART1 Clock Source * @{ */ -#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000) +#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) @@ -285,7 +285,7 @@ typedef struct /** @defgroup RCCEx_USART2_Clock_Source RCC USART2 Clock Source * @{ */ -#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) @@ -297,7 +297,7 @@ typedef struct /** @defgroup RCCEx_LPUART1_Clock_Source RCC LPUART Clock Source * @{ */ -#define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) @@ -309,7 +309,7 @@ typedef struct /** @defgroup RCCEx_I2C1_Clock_Source RCC I2C1 Clock Source * @{ */ -#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 @@ -322,7 +322,7 @@ typedef struct /** @defgroup RCCEx_I2C3_Clock_Source RCC I2C3 Clock Source * @{ */ -#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 @@ -336,8 +336,8 @@ typedef struct /** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM Prescaler Selection * @{ */ -#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00) -#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01) +#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00U) +#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01U) /** * @} */ @@ -347,7 +347,7 @@ typedef struct * @{ */ #define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL -#define RCC_USBCLKSOURCE_PLL ((uint32_t)0x00000000) +#define RCC_USBCLKSOURCE_PLL ((uint32_t)0x00000000U) /** * @} @@ -357,7 +357,7 @@ typedef struct * @{ */ #define RCC_RNGCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL -#define RCC_RNGCLKSOURCE_PLLCLK ((uint32_t)0x00000000) +#define RCC_RNGCLKSOURCE_PLLCLK ((uint32_t)0x00000000U) /** * @} @@ -366,9 +366,9 @@ typedef struct /** @defgroup RCCEx_HSI48M_Clock_Source RCC HSI48M Clock Source * @{ */ -#define RCC_FLAG_HSI48 SYSCFG_CFGR3_REF_HSI48_RDYF +#define RCC_FLAG_HSI48 SYSCFG_CFGR3_VREFINT_RDYF -#define RCC_HSI48M_PLL ((uint32_t)0x00000000) +#define RCC_HSI48M_PLL ((uint32_t)0x00000000U) #define RCC_HSI48M_HSI48 RCC_CCIPR_HSI48SEL @@ -380,7 +380,7 @@ typedef struct /** @defgroup RCC_HSI_Config RCC HSI Configuration * @{ */ -#define RCC_HSI_OFF ((uint8_t)0x00) +#define RCC_HSI_OFF ((uint8_t)0x00U) #define RCC_HSI_ON RCC_CR_HSION #define RCC_HSI_DIV4 (RCC_CR_HSIDIVEN | RCC_CR_HSION) #if defined(STM32L073xx) || defined(STM32L083xx) || \ @@ -396,7 +396,7 @@ typedef struct /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source * @{ */ -#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000) +#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U) #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL @@ -409,7 +409,7 @@ typedef struct * @{ */ -#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00) +#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00U) #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /** @@ -420,7 +420,7 @@ typedef struct * @{ */ -#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000) +#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) #define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1 #define RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV @@ -441,7 +441,7 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroSource RCC CRS Synchro Source * @{ */ -#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /*!< Synchro Signal source GPIO */ +#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal source GPIO */ #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ @@ -452,7 +452,7 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroDivider RCC CRS Synchro Divider * @{ */ -#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /*!< Synchro Signal not divided (default) */ +#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */ #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ @@ -468,7 +468,7 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroPolarity RCC CRS Synchro Polarity * @{ */ -#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */ +#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */ #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ /** @@ -478,7 +478,7 @@ typedef struct /** @defgroup RCCEx_CRS_ReloadValueDefault RCC CRS Reload Default Value * @{ */ -#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds +#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU) /*!< The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ /** @@ -488,7 +488,7 @@ typedef struct /** @defgroup RCCEx_CRS_ErrorLimitDefault RCC CRS Error Limit Default * @{ */ -#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */ +#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U) /*!< Default Frequency error limit */ /** * @} @@ -497,7 +497,7 @@ typedef struct /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCC CRS HSI48 Calibration Default * @{ */ -#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval. +#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency */ @@ -508,7 +508,7 @@ typedef struct /** @defgroup RCCEx_CRS_FreqErrorDirection RCC CRS Frequency Error Direction * @{ */ -#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */ +#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */ #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ /** @@ -518,13 +518,13 @@ typedef struct /** @defgroup RCCEx_CRS_Interrupt_Sources RCC CRS Interrupt Sources * @{ */ -#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */ -#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */ -#define RCC_CRS_IT_ERR CRS_ISR_ERRF /*!< error */ -#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */ -#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ -#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ -#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ +#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ +#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ +#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< error */ +#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ +#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ +#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ +#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed*/ /** * @} @@ -1626,10 +1626,10 @@ typedef struct */ #define __HAL_RCC_HSI48_ENABLE() do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \ RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; \ - SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT); \ + SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENREF_HSI48); \ } while (0) #define __HAL_RCC_HSI48_DISABLE() do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \ - SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT)); \ + SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENREF_HSI48)); \ } while (0) /** @brief Enable or disable the HSI48M DIV6 OUT . * @note After reset, the HSI48Mhz (divided by 6) output is not available @@ -1784,11 +1784,11 @@ void HAL_RCCEx_DisableHSI48_VREFINT(void); #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) -#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFF)) +#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) -#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFF)) +#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) -#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3F)) +#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rng.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rng.c index 296b794af3..7fbf06bd29 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rng.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rng.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_rng.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief RNG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Random Number Generator (RNG) peripheral: @@ -78,7 +78,7 @@ /** @addtogroup RNG_Private * @{ */ -#define RNG_TIMEOUT_VALUE 1000 +#define RNG_TIMEOUT_VALUE 1000U /** * @} */ @@ -245,7 +245,7 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; HAL_StatusTypeDef status = HAL_OK; /* Process Locked */ @@ -396,7 +396,7 @@ uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng) } else { - return 0; + return 0U; } } @@ -409,7 +409,7 @@ uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng) */ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng) { - uint32_t random32bit = 0; + uint32_t random32bit = 0U; /* Process locked */ __HAL_LOCK(hrng); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rng.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rng.h index 96e98dccc3..d5f54c58d9 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rng.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rng.h @@ -3,8 +3,8 @@ * @file stm32l0xx_hal_rng.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of RNG HAL module. ****************************************************************************** * @attention @@ -70,11 +70,11 @@ */ typedef enum { - HAL_RNG_STATE_RESET = 0x00, /*!< RNG not yet initialized or disabled */ - HAL_RNG_STATE_READY = 0x01, /*!< RNG initialized and ready for use */ - HAL_RNG_STATE_BUSY = 0x02, /*!< RNG internal process is ongoing */ - HAL_RNG_STATE_TIMEOUT = 0x03, /*!< RNG timeout state */ - HAL_RNG_STATE_ERROR = 0x04 /*!< RNG error state */ + HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */ + HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */ + HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */ + HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */ + HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */ }HAL_RNG_StateTypeDef; diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc.c index 4c1344faca..98f55a03b7 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_rtc.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) peripheral: @@ -228,7 +228,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Configure the RTC PRER */ hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); - hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16); + hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U); /* Exit Initialization mode */ hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); @@ -254,7 +254,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) */ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); @@ -279,7 +279,7 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) else { /* Reset TR, DR and CR registers */ - hrtc->Instance->TR = (uint32_t)0x00000000; + hrtc->Instance->TR = (uint32_t)0x00000000U; hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); /* Reset All CR bits except CR[2:0] */ hrtc->Instance->CR &= RTC_CR_WUCKSEL; @@ -302,24 +302,24 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) } /* Reset all RTC CR register bits */ - hrtc->Instance->CR &= (uint32_t)0x00000000; + hrtc->Instance->CR &= (uint32_t)0x00000000U; hrtc->Instance->WUTR = RTC_WUTR_WUT; - hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FF)); - hrtc->Instance->ALRMAR = (uint32_t)0x00000000; - hrtc->Instance->ALRMBR = (uint32_t)0x00000000; - hrtc->Instance->SHIFTR = (uint32_t)0x00000000; - hrtc->Instance->CALR = (uint32_t)0x00000000; - hrtc->Instance->ALRMASSR = (uint32_t)0x00000000; - hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000; + hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU)); + hrtc->Instance->ALRMAR = (uint32_t)0x00000000U; + hrtc->Instance->ALRMBR = (uint32_t)0x00000000U; + hrtc->Instance->SHIFTR = (uint32_t)0x00000000U; + hrtc->Instance->CALR = (uint32_t)0x00000000U; + hrtc->Instance->ALRMASSR = (uint32_t)0x00000000U; + hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000U; /* Reset ISR register and exit initialization mode */ - hrtc->Instance->ISR = (uint32_t)0x00000000; + hrtc->Instance->ISR = (uint32_t)0x00000000U; /* Reset Tamper configuration register */ - hrtc->Instance->TAMPCR = 0x00000000; + hrtc->Instance->TAMPCR = 0x00000000U; /* Reset Option register */ - hrtc->Instance->OR = 0x00000000; + hrtc->Instance->OR = 0x00000000U; /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) @@ -410,7 +410,7 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) */ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -431,16 +431,16 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim } else { - sTime->TimeFormat = 0x00; + sTime->TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(sTime->Hours)); } assert_param(IS_RTC_MINUTES(sTime->Minutes)); assert_param(IS_RTC_SECONDS(sTime->Seconds)); - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \ + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \ ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ - (((uint32_t)sTime->TimeFormat) << 16)); + (((uint32_t)sTime->TimeFormat) << 16U)); } else { @@ -452,15 +452,15 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim } else { - sTime->TimeFormat = 0x00; + sTime->TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); } assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); - tmpreg = (((uint32_t)(sTime->Hours) << 16) | \ - ((uint32_t)(sTime->Minutes) << 8) | \ + tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \ + ((uint32_t)(sTime->Minutes) << 8U) | \ ((uint32_t)sTime->Seconds) | \ - ((uint32_t)(sTime->TimeFormat) << 16)); + ((uint32_t)(sTime->TimeFormat) << 16U)); } UNUSED(tmpreg); /* Disable the write protection for RTC registers */ @@ -545,7 +545,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim */ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -560,10 +560,10 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); /* Fill the structure fields with the read parameters */ - sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); - sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); + sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U); + sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8U); sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); + sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U); /* Check the input parameters format */ if(Format == RTC_FORMAT_BIN) @@ -589,7 +589,7 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim */ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { - uint32_t datetmpreg = 0; + uint32_t datetmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -599,9 +599,9 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat hrtc->State = HAL_RTC_STATE_BUSY; - if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10)) + if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) { - sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A); + sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); } assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); @@ -612,10 +612,10 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat assert_param(IS_RTC_MONTH(sDate->Month)); assert_param(IS_RTC_DATE(sDate->Date)); - datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \ + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \ ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ - ((uint32_t)sDate->WeekDay << 13)); + ((uint32_t)sDate->WeekDay << 13U)); } else { @@ -625,10 +625,10 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat datetmpreg = RTC_Bcd2ToByte(sDate->Date); assert_param(IS_RTC_DATE(datetmpreg)); - datetmpreg = ((((uint32_t)sDate->Year) << 16) | \ - (((uint32_t)sDate->Month) << 8) | \ + datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \ + (((uint32_t)sDate->Month) << 8U) | \ ((uint32_t)sDate->Date) | \ - (((uint32_t)sDate->WeekDay) << 13)); + (((uint32_t)sDate->WeekDay) << 13U)); } /* Disable the write protection for RTC registers */ @@ -700,7 +700,7 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat */ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { - uint32_t datetmpreg = 0; + uint32_t datetmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -709,10 +709,10 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); /* Fill the structure fields with the read parameters */ - sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); - sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); + sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U); + sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U); sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU)); - sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); + sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U); /* Check the input parameters format */ if(Format == RTC_FORMAT_BIN) @@ -754,8 +754,8 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat */ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { - uint32_t tickstart = 0; - uint32_t tmpreg = 0, subsecondtmpreg = 0; + uint32_t tickstart = 0U; + uint32_t tmpreg = 0U, subsecondtmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -779,7 +779,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } else { - sAlarm->AlarmTime.TimeFormat = 0x00; + sAlarm->AlarmTime.TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); } assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); @@ -794,11 +794,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); } - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } @@ -812,7 +812,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } else { - sAlarm->AlarmTime.TimeFormat = 0x00; + sAlarm->AlarmTime.TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); } @@ -830,11 +830,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } @@ -938,8 +938,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA */ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { - uint32_t tickstart = 0; - uint32_t tmpreg = 0, subsecondtmpreg = 0; + uint32_t tickstart = 0U; + uint32_t tmpreg = 0U, subsecondtmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -963,7 +963,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } else { - sAlarm->AlarmTime.TimeFormat = 0x00; + sAlarm->AlarmTime.TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); } assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); @@ -977,11 +977,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); } - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } @@ -995,7 +995,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } else { - sAlarm->AlarmTime.TimeFormat = 0x00; + sAlarm->AlarmTime.TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); } @@ -1012,11 +1012,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } @@ -1123,7 +1123,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef */ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_RTC_ALARM(Alarm)); @@ -1217,7 +1217,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar */ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) { - uint32_t tmpreg = 0, subsecondtmpreg = 0; + uint32_t tmpreg = 0U, subsecondtmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -1232,12 +1232,12 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS); /* Fill the structure with the read parameters */ - sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16); - sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8); + sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U); + sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U); sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); - sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); + sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U); sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; - sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); + sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U); sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); } @@ -1249,12 +1249,12 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS); /* Fill the structure with the read parameters */ - sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> 16); - sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> 8); + sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> 16U); + sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> 8U); sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMBR_ST | RTC_ALRMBR_SU)); - sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMBR_PM) >> 16); + sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMBR_PM) >> 16U); sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; - sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> 24); + sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> 24U); sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMBR_WDSEL); sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); } @@ -1342,7 +1342,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -1394,7 +1394,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Clear RSF flag */ hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; @@ -1461,7 +1461,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) */ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check if the Initialization mode is set */ if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) @@ -1491,15 +1491,15 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) */ uint8_t RTC_ByteToBcd2(uint8_t Value) { - uint32_t bcdhigh = 0; + uint32_t bcdhigh = 0U; - while(Value >= 10) + while(Value >= 10U) { bcdhigh++; - Value -= 10; + Value -= 10U; } - return ((uint8_t)(bcdhigh << 4) | Value); + return ((uint8_t)(bcdhigh << 4U) | Value); } /** @@ -1509,9 +1509,9 @@ uint8_t RTC_ByteToBcd2(uint8_t Value) */ uint8_t RTC_Bcd2ToByte(uint8_t Value) { - uint32_t tmp = 0; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); + uint32_t tmp = 0U; + tmp = ((uint8_t)(Value & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U; + return (tmp + (Value & (uint8_t)0x0FU)); } /** diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc.h index 0feb2b6364..a189a43d35 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_rtc.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention @@ -64,11 +64,11 @@ */ typedef enum { - HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */ - HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */ - HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */ - HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */ - HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */ + HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ + HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ + HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ + HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ + HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ }HAL_RTCStateTypeDef; @@ -204,7 +204,7 @@ typedef struct /** @defgroup RTC_Hour_Formats RTC Hour Formats * @{ */ -#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000) +#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000U) #define RTC_HOURFORMAT_12 ((uint32_t)RTC_CR_FMT) /** @@ -215,7 +215,7 @@ typedef struct /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions * @{ */ -#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000) +#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000U) #define RTC_OUTPUT_POLARITY_LOW ((uint32_t)RTC_CR_POL) /** @@ -225,7 +225,7 @@ typedef struct /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT * @{ */ -#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000) +#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U) #define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE) /** @@ -235,7 +235,7 @@ typedef struct /** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap * @{ */ -#define RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000) +#define RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000U) #define RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP) /** * @} @@ -244,8 +244,8 @@ typedef struct /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions * @{ */ -#define RTC_HOURFORMAT12_AM ((uint8_t)0x00) -#define RTC_HOURFORMAT12_PM ((uint8_t)0x40) +#define RTC_HOURFORMAT12_AM ((uint8_t)0x00U) +#define RTC_HOURFORMAT12_PM ((uint8_t)0x40U) /** * @} @@ -256,7 +256,7 @@ typedef struct */ #define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)RTC_CR_SUB1H) #define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)RTC_CR_ADD1H) -#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000) +#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000U) /** * @} @@ -265,19 +265,18 @@ typedef struct /** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions * @{ */ -#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000) +#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000U) #define RTC_STOREOPERATION_SET ((uint32_t)RTC_CR_BCK) /** * @} */ - -/** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions +/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions * @{ */ -#define RTC_FORMAT_BIN ((uint32_t)0x000000000) -#define RTC_FORMAT_BCD ((uint32_t)0x000000001) +#define RTC_FORMAT_BIN ((uint32_t)0x000000000U) +#define RTC_FORMAT_BCD ((uint32_t)0x000000001U) /** * @} @@ -288,18 +287,18 @@ typedef struct */ /* Coded in BCD format */ -#define RTC_MONTH_JANUARY ((uint8_t)0x01) -#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) -#define RTC_MONTH_MARCH ((uint8_t)0x03) -#define RTC_MONTH_APRIL ((uint8_t)0x04) -#define RTC_MONTH_MAY ((uint8_t)0x05) -#define RTC_MONTH_JUNE ((uint8_t)0x06) -#define RTC_MONTH_JULY ((uint8_t)0x07) -#define RTC_MONTH_AUGUST ((uint8_t)0x08) -#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) -#define RTC_MONTH_OCTOBER ((uint8_t)0x10) -#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) -#define RTC_MONTH_DECEMBER ((uint8_t)0x12) +#define RTC_MONTH_JANUARY ((uint8_t)0x01U) +#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U) +#define RTC_MONTH_MARCH ((uint8_t)0x03U) +#define RTC_MONTH_APRIL ((uint8_t)0x04U) +#define RTC_MONTH_MAY ((uint8_t)0x05U) +#define RTC_MONTH_JUNE ((uint8_t)0x06U) +#define RTC_MONTH_JULY ((uint8_t)0x07U) +#define RTC_MONTH_AUGUST ((uint8_t)0x08U) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10U) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12U) /** * @} @@ -308,13 +307,13 @@ typedef struct /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions * @{ */ -#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) -#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) -#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) -#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) -#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) -#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) -#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) /** * @} @@ -323,7 +322,7 @@ typedef struct /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions * @{ */ -#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000) +#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U) #define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /** @@ -333,7 +332,7 @@ typedef struct /** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions * @{ */ -#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000) +#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000U) #define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 #define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 #define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 @@ -362,7 +361,7 @@ typedef struct /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions * @{ */ -#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. +#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000U) /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */ #define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] are don't care in Alarm @@ -402,11 +401,11 @@ typedef struct /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions * @{ */ -#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE) -#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE) -#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE) -#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE) -#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /* Used only to Enable the Tamper Interrupt */ +#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE) /*!< Enable Timestamp Interrupt */ +#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE) /*!< Enable Wakeup timer Interrupt */ +#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE) /*!< Enable Alarm A Interrupt */ +#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE) /*!< Enable Alarm B Interrupt */ +#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /*!< Enable all Tamper Interrupt */ #if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\ @@ -414,14 +413,14 @@ typedef struct defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ defined (STM32L031xx) || defined (STM32L041xx) -#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE) +#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE) /*!< Enable Tamper 1 Interrupt */ #endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) || * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) || * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || * (STM32L031xx) || (STM32L041xx) */ -#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE) +#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE) /*!< Enable Tamper 2 Interrupt */ /** * @} */ @@ -483,9 +482,9 @@ typedef struct */ #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ do{ \ - (__HANDLE__)->Instance->WPR = 0xCA; \ - (__HANDLE__)->Instance->WPR = 0x53; \ - } while(0) + (__HANDLE__)->Instance->WPR = 0xCAU; \ + (__HANDLE__)->Instance->WPR = 0x53U; \ + } while(0U) /** * @brief Enable the write protection for RTC registers. @@ -494,8 +493,8 @@ typedef struct */ #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ do{ \ - (__HANDLE__)->Instance->WPR = 0xFF; \ - } while(0) + (__HANDLE__)->Instance->WPR = 0xFFU; \ + } while(0U) /** * @brief Enable the RTC ALARMA peripheral. @@ -556,7 +555,7 @@ typedef struct * @arg RTC_IT_ALRB: Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET) +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET) /** * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. @@ -645,13 +644,19 @@ typedef struct * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line. * @retval None. */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); } while(0); +#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line. * @retval None. */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); } while(0); +#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not. @@ -757,10 +762,10 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define RTC_DR_RESERVED_MASK ((uint32_t) (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \ RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \ RTC_DR_DU)) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) +#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU) #define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF)) -#define RTC_TIMEOUT_VALUE 1000 +#define RTC_TIMEOUT_VALUE 1000U #define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_IM17) /*!< External interrupt line 17 Connected to the RTC Alarm event */ @@ -801,11 +806,11 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) -#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99) +#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99U) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12)) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1U) && ((MONTH) <= (uint32_t)12U)) -#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31)) +#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1U) && ((DATE) <= (uint32_t)31U)) #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ @@ -815,7 +820,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31)) +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t)0U) && ((DATE) <= (uint32_t)31U)) #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ @@ -851,17 +856,17 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \ ((MASK) == RTC_ALARMSUBSECONDMASK_NONE)) -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F) +#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FU) -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF) +#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFFU) -#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12)) +#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0U) && ((HOUR) <= (uint32_t)12U)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23U) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59U) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59U) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc_ex.c index 4f855d36c9..d728e41c63 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Extended RTC HAL module driver. * * This file provides firmware functions to manage the following @@ -170,7 +170,7 @@ */ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); @@ -225,7 +225,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS */ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); @@ -275,7 +275,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti */ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Process Locked */ __HAL_LOCK(hrtc); @@ -319,7 +319,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) */ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format) { - uint32_t tmptime = 0, tmpdate = 0; + uint32_t tmptime = 0U, tmpdate = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -329,17 +329,17 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK); /* Fill the Time structure fields with the read parameters */ - sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); - sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); + sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U); + sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U); sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); + sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U); sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR; /* Fill the Date structure fields with the read parameters */ - sTimeStampDate->Year = 0; - sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); + sTimeStampDate->Year = 0U; + sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U); sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); + sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U); /* Check the input parameters format */ if(Format == RTC_FORMAT_BIN) @@ -370,7 +370,7 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe */ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param( IS_RTC_TAMPER(sTamper->Tamper)); @@ -391,19 +391,19 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef /* Configure the tamper trigger */ if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); + sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U); } if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) { - sTamper->NoErase = 0; + sTamper->NoErase = 0U; #if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\ defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ defined (STM32L031xx) || defined (STM32L041xx) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) + if((sTamper->Tamper & RTC_TAMPER_1) != 0U) { sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; } @@ -414,7 +414,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef * (STM32L031xx) || (STM32L041xx) */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) + if((sTamper->Tamper & RTC_TAMPER_2) != 0U) { sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; } @@ -422,7 +422,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) + if((sTamper->Tamper & RTC_TAMPER_3) != 0U) { sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; } @@ -434,7 +434,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) { - sTamper->MaskFlag = 0; + sTamper->MaskFlag = 0U; #if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\ @@ -442,7 +442,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ defined (STM32L031xx) || defined (STM32L041xx) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) + if((sTamper->Tamper & RTC_TAMPER_1) != 0U) { sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; } @@ -453,7 +453,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef * (STM32L031xx) || (STM32L041xx) */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) + if((sTamper->Tamper & RTC_TAMPER_2) != 0U) { sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; } @@ -461,7 +461,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) + if((sTamper->Tamper & RTC_TAMPER_3) != 0U) { sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; } @@ -477,7 +477,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef #if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) - hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\ + hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | RTC_TAMPCR_TAMPTS |\ RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\ RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1IE |\ RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP1NOERASE | RTC_TAMPCR_TAMP2NOERASE|\ @@ -486,7 +486,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef #elif defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ defined (STM32L031xx) || defined (STM32L041xx) - hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\ + hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | RTC_TAMPCR_TAMPTS |\ RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\ RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1IE |\ RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP3IE | RTC_TAMPCR_TAMP1NOERASE |\ @@ -494,7 +494,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef RTC_TAMPCR_TAMP2MF | RTC_TAMPCR_TAMP3MF)); #elif defined (STM32L011xx) || defined (STM32L021xx) - hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\ + hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | RTC_TAMPCR_TAMPTS |\ RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\ RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE |\ RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP3IE |\ @@ -523,7 +523,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef */ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param( IS_RTC_TAMPER(sTamper->Tamper)); @@ -545,12 +545,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType /* Configure the tamper trigger */ if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); + sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U); } if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) { - sTamper->NoErase = 0; + sTamper->NoErase = 0U; #if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\ @@ -558,7 +558,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ defined (STM32L031xx) || defined (STM32L041xx) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) + if((sTamper->Tamper & RTC_TAMPER_1) != 0U) { sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; } @@ -570,7 +570,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) + if((sTamper->Tamper & RTC_TAMPER_2) != 0U) { sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; } @@ -578,7 +578,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) + if((sTamper->Tamper & RTC_TAMPER_3) != 0U) { sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; } @@ -589,14 +589,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) { - sTamper->MaskFlag = 0; + sTamper->MaskFlag = 0U; #if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\ defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ defined (STM32L031xx) || defined (STM32L041xx) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) + if((sTamper->Tamper & RTC_TAMPER_1) != 0U) { sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; } @@ -607,7 +607,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType * (STM32L031xx) || (STM32L041xx) */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) + if((sTamper->Tamper & RTC_TAMPER_2) != 0U) { sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; } @@ -615,7 +615,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) + if((sTamper->Tamper & RTC_TAMPER_3) != 0U) { sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; } @@ -631,7 +631,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType #if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) - hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\ + hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | RTC_TAMPCR_TAMPTS |\ RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\ RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1IE |\ RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP1NOERASE | RTC_TAMPCR_TAMP2NOERASE |\ @@ -640,7 +640,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType #elif defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ defined (STM32L031xx) || defined (STM32L041xx) - hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\ + hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | RTC_TAMPCR_TAMPTS |\ RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\ RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1IE |\ RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP3IE | RTC_TAMPCR_TAMP1NOERASE |\ @@ -648,7 +648,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType RTC_TAMPCR_TAMP2MF | RTC_TAMPCR_TAMP3MF); #elif defined (STM32L011xx) || defined (STM32L021xx) - hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\ + hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | RTC_TAMPCR_TAMPTS |\ RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\ RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE |\ RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP3IE |\ @@ -698,7 +698,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ defined (STM32L031xx) || defined (STM32L041xx) - if ((Tamper & RTC_TAMPER_1) != 0) + if ((Tamper & RTC_TAMPER_1) != 0U) { /* Disable the Tamper1 interrupt */ hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1)); @@ -711,7 +711,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T * (STM32L031xx) || (STM32L041xx) */ - if ((Tamper & RTC_TAMPER_2) != 0) + if ((Tamper & RTC_TAMPER_2) != 0U) { /* Disable the Tamper2 interrupt */ hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2)); @@ -721,7 +721,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx) - if ((Tamper & RTC_TAMPER_3) != 0) + if ((Tamper & RTC_TAMPER_3) != 0U) { /* Disable the Tamper3 interrupt */ hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3)); @@ -925,7 +925,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -959,7 +959,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_ { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -997,7 +997,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_ { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -1034,7 +1034,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_ { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -1081,7 +1081,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_ */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); @@ -1170,7 +1170,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); @@ -1205,9 +1205,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t } } } - + /* Disable the Wake-Up timer */ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + /* Clear flag Wake-Up */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + tickstart = HAL_GetTick(); /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ @@ -1265,7 +1268,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t */ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Process Locked */ __HAL_LOCK(hrtc); @@ -1376,7 +1379,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; @@ -1436,13 +1439,13 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin */ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) { - uint32_t tmp = 0; + uint32_t tmp = 0U; /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); tmp = (uint32_t)&(hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4); + tmp += (BackupRegister * 4U); /* Write the specified register */ *(__IO uint32_t *)tmp = (uint32_t)Data; @@ -1458,13 +1461,13 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3 */ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) { - uint32_t tmp = 0; + uint32_t tmp = 0U; /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); tmp = (uint32_t)&(hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4); + tmp += (BackupRegister * 4U); /* Read the specified register */ return (*(__IO uint32_t *)tmp); @@ -1491,7 +1494,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) */ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); @@ -1559,7 +1562,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo */ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); @@ -1922,7 +1925,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc_ex.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc_ex.h index 6a8350685d..35f7aff352 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of RTC HAL Extended module. ****************************************************************************** * @attention @@ -107,7 +107,7 @@ typedef struct /** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition * @{ */ -#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000) +#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000U) #define RTC_OUTPUT_ALARMA ((uint32_t)RTC_CR_OSEL_0) #define RTC_OUTPUT_ALARMB ((uint32_t)RTC_CR_OSEL_1) #define RTC_OUTPUT_WAKEUP ((uint32_t)RTC_CR_OSEL) @@ -119,11 +119,11 @@ typedef struct /** @defgroup RTCEx_Backup_Registers_Definitions RTCEx Backup Registers Definition * @{ */ -#define RTC_BKP_DR0 ((uint32_t)0x00000000) -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) +#define RTC_BKP_DR0 ((uint32_t)0x00000000U) +#define RTC_BKP_DR1 ((uint32_t)0x00000001U) +#define RTC_BKP_DR2 ((uint32_t)0x00000002U) +#define RTC_BKP_DR3 ((uint32_t)0x00000003U) +#define RTC_BKP_DR4 ((uint32_t)0x00000004U) /** * @} */ @@ -132,7 +132,7 @@ typedef struct /** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition * @{ */ -#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000) +#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000U) #define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE /** @@ -142,7 +142,7 @@ typedef struct /** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection * @{ */ -#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000) +#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000U) /** * @} @@ -222,8 +222,8 @@ typedef struct /** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definitions * @{ */ -#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000) -#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002) +#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000U) +#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002U) #define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE #define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE @@ -234,8 +234,8 @@ typedef struct /** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTCEx Tamper EraseBackUp Definitions * @{ */ -#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000) -#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000) +#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000U) +#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000U) /** * @} */ @@ -243,8 +243,8 @@ typedef struct /** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTCEx Tamper MaskFlag Definitions * @{ */ -#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000) -#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000) +#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000U) +#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000U) /** * @} @@ -253,7 +253,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions * @{ */ -#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ +#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000U) /*!< Tamper filter is disabled */ #define RTC_TAMPERFILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ @@ -269,7 +269,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions * @{ */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAMPCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ @@ -294,7 +294,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions * @{ */ -#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000U) /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ #define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ @@ -311,7 +311,7 @@ typedef struct * @{ */ #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_TAMPCR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U) /*!< TimeStamp on Tamper Detection event is not saved */ /** * @} @@ -320,7 +320,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definitions * @{ */ -#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before sampling */ +#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000U) /*!< Tamper pins are pre-charged before sampling */ #define RTC_TAMPER_PULLUP_DISABLE RTC_TAMPCR_TAMPPUDIS /*!< Tamper pins pre-charge is disabled */ /** @@ -330,7 +330,7 @@ typedef struct /** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions * @{ */ -#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000U) #define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0 #define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1 #define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t) (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)) @@ -343,7 +343,7 @@ typedef struct /** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions * @{ */ -#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibation +#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000U) /*!< If RTCCLK = 32768 Hz, Smooth calibation period is 32s, else 2exp20 RTCCLK pulses */ #define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibation period is 16s, else 2exp19 RTCCLK pulses */ @@ -360,7 +360,7 @@ typedef struct #define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0] with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited +#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000U) /*!< The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0] */ /** @@ -369,7 +369,7 @@ typedef struct /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions * @{ */ -#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000) +#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000U) #define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL /** @@ -380,7 +380,7 @@ typedef struct /** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definitions * @{ */ -#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000) +#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000U) #define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S /** * @} @@ -475,7 +475,7 @@ typedef struct * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET) ? SET : RESET) /** * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. @@ -562,14 +562,20 @@ typedef struct * @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. * @retval None. */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); } while(0); +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. * This parameter can be: * @retval None. */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); } while(0); +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not. @@ -638,7 +644,7 @@ typedef struct * @arg RTC_IT_TS: TimeStamp interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET) ? SET : RESET) /** * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. @@ -847,8 +853,8 @@ typedef struct * @arg RTC_IT_TAMP2: Tamper2 interrupt * @retval None */ -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \ - ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET)) +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != RESET) ? SET : RESET) : \ + ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != RESET) ? SET : RESET)) #elif defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \ @@ -864,9 +870,9 @@ typedef struct * @arg RTC_IT_TAMP3: Tamper3 interrupt * @retval None */ -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \ - ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \ - ((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET)) +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != RESET) ? SET : RESET) : \ + ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != RESET) ? SET : RESET) : \ + ((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7U)) != RESET) ? SET : RESET)) #elif defined (STM32L011xx) || defined (STM32L021xx) @@ -879,8 +885,8 @@ typedef struct * @arg RTC_IT_TAMP3: Tamper3 interrupt * @retval None */ -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \ - ((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET)) +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != RESET) ? SET : RESET) : \ + ((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7U)) != RESET) ? SET : RESET)) #endif /* (STM32L011xx) || (STM32L021xx) @@ -1075,14 +1081,20 @@ typedef struct * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. * @retval None. */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); } while(0); +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. * This parameter can be: * @retval None. */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); } while(0); +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not. @@ -1338,9 +1350,9 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t #define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) -#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXE))) == 0x00) && ((TAMPER) != (uint32_t)RESET)) +#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXE))) == 0x00U) && ((TAMPER) != (uint32_t)RESET)) -#define IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXIE)) == 0x00) && ((INTERRUPT) != (uint32_t)RESET)) +#define IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXIE)) == 0x00U) && ((INTERRUPT) != (uint32_t)RESET)) #define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT)) @@ -1380,7 +1392,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t #define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \ ((STATE) == RTC_TAMPER_PULLUP_DISABLE)) -#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ +#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard.c index dda0f12370..a33f92310c 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_smartcard.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief SMARTCARD HAL module driver. * * This file provides firmware functions to manage the following @@ -106,8 +106,8 @@ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#define TEACK_REACK_TIMEOUT 1000 -#define HAL_SMARTCARD_TXDMA_TIMEOUTVALUE 22000 +#define TEACK_REACK_TIMEOUT 1000U +#define HAL_SMARTCARD_TXDMA_TIMEOUTVALUE 22000U #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) #define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) @@ -146,14 +146,7 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc); associated to the SmartCard. (+) These parameters can be configured: (++) Baud Rate - (++) Parity: parity should be enabled, - Frame Length is fixed to 8 bits plus parity: - the USART frame format is given in the following table: - +---------------------------------------------------------------+ - | M1M0 bits | PCE bit | USART frame | - |-----------------------|---------------------------------------| - | 01 | 1 | | SB | 8 bit data | PB | STB | | - +---------------------------------------------------------------+ + (++) Parity: parity should be enabled,frame Length is fixed to 8 bits plus parity. (++) Receiver/transmitter modes (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters) (++) Prescaler value @@ -176,6 +169,15 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc); (details for the procedures are available in reference manual). @endverbatim + + The USART frame format is given in the following table: + + Table 1. USART frame format. + +---------------------------------------------------------------+ + | M1M0 bits | PCE bit | USART frame | + |-----------------------|---------------------------------------| + | 01 | 1 | | SB | 8 bit data | PB | STB | | + +---------------------------------------------------------------+ * @{ */ @@ -356,7 +358,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t * { if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -376,14 +378,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t * hsc->TxXferSize = Size; hsc->TxXferCount = Size; - while(hsc->TxXferCount > 0) + while(hsc->TxXferCount > 0U) { hsc->TxXferCount--; if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - hsc->Instance->TDR = (*pData++ & (uint8_t)0xFF); + hsc->Instance->TDR = (*pData++ & (uint8_t)0xFFU); } if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK) { @@ -422,7 +424,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p { if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -444,14 +446,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p hsc->RxXferSize = Size; hsc->RxXferCount = Size; /* Check the remain data to be received */ - while(hsc->RxXferCount > 0) + while(hsc->RxXferCount > 0U) { hsc->RxXferCount--; if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - *pData++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0x00FF); + *pData++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0x00FFU); } /* Check if a non-blocking transmit Process is ongoing or not */ @@ -486,7 +488,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_ { if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -537,7 +539,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t { if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -593,7 +595,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8 if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -659,7 +661,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_ if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -892,7 +894,7 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc) { if((hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)) { - if(hsc->TxXferCount == 0) + if(hsc->TxXferCount == 0U) { /* Disable the SMARTCARD Transmit Complete Interrupt */ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TC); @@ -916,7 +918,7 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc) } else { - hsc->Instance->TDR = (*hsc->pTxBuffPtr++ & (uint8_t)0xFF); + hsc->Instance->TDR = (*hsc->pTxBuffPtr++ & (uint8_t)0xFFU); hsc->TxXferCount--; return HAL_OK; @@ -939,9 +941,9 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc) { if((hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)) { - *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0xFF); + *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0xFFU); - if(--hsc->RxXferCount == 0) + if(--hsc->RxXferCount == 0U) { while(HAL_IS_BIT_SET(hsc->Instance->ISR, SMARTCARD_FLAG_RXNE)) { @@ -983,8 +985,8 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc) */ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) { - uint32_t tmpreg = 0x00000000; - uint32_t clocksource = 0x00000000; + uint32_t tmpreg = 0x00000000U; + uint32_t clocksource = 0x00000000U; /* Check the parameters */ assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance)); @@ -1056,19 +1058,19 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) switch (clocksource) { case SMARTCARD_CLOCKSOURCE_PCLK1: - hsc->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hsc->Init.BaudRate); + hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsc->Init.BaudRate/2U)) / hsc->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_PCLK2: - hsc->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK2Freq() / hsc->Init.BaudRate); + hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsc->Init.BaudRate/2U)) / hsc->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_HSI: - hsc->Instance->BRR = (uint16_t)(HSI_VALUE / hsc->Init.BaudRate); + hsc->Instance->BRR = (uint16_t)((HSI_VALUE + (hsc->Init.BaudRate/2U)) / hsc->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_SYSCLK: - hsc->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hsc->Init.BaudRate); + hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsc->Init.BaudRate/2U)) / hsc->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_LSE: - hsc->Instance->BRR = (uint16_t)(LSE_VALUE / hsc->Init.BaudRate); + hsc->Instance->BRR = (uint16_t)((LSE_VALUE + (hsc->Init.BaudRate/2U)) / hsc->Init.BaudRate); break; default: break; @@ -1184,7 +1186,7 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc) */ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { - uint32_t tickstart = 0x00; + uint32_t tickstart = 0x00U; tickstart = HAL_GetTick(); /* Wait until flag is set */ @@ -1195,7 +1197,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE); @@ -1220,7 +1222,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE); @@ -1249,7 +1251,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) { SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hsmartcard->TxXferCount = 0; + hsmartcard->TxXferCount = 0U; /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the SMARTCARD associated USART CR3 register */ @@ -1267,7 +1269,7 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hsc->RxXferCount = 0; + hsc->RxXferCount = 0U; /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the SMARTCARD associated USART CR3 register */ @@ -1294,8 +1296,8 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) { SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hsc->RxXferCount = 0; - hsc->TxXferCount = 0; + hsc->RxXferCount = 0U; + hsc->TxXferCount = 0U; hsc->State= HAL_SMARTCARD_STATE_READY; hsc->ErrorCode |= HAL_SMARTCARD_ERROR_DMA; HAL_SMARTCARD_ErrorCallback(hsc); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard.h index 565ab51a7e..d7b86640a6 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_smartcard.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention @@ -157,14 +157,14 @@ typedef struct */ typedef enum { - HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */ - HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */ + HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_SMARTCARD_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_SMARTCARD_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_SMARTCARD_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ + HAL_SMARTCARD_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_SMARTCARD_STATE_ERROR = 0x04U /*!< Error */ }HAL_SMARTCARD_StateTypeDef; @@ -174,11 +174,11 @@ typedef enum */ typedef enum { - SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - SMARTCARD_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - SMARTCARD_CLOCKSOURCE_LSE = 0x08 /*!< LSE clock source */ + SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + SMARTCARD_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + SMARTCARD_CLOCKSOURCE_LSE = 0x08U /*!< LSE clock source */ }SMARTCARD_ClockSourceTypeDef; /** @@ -231,13 +231,13 @@ typedef struct /** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code * @{ */ -#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x01) /*!< Parity error */ -#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x02) /*!< Noise error */ -#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x04) /*!< frame error */ -#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */ -#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ -#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x20) /*!< Receiver TimeOut error */ +#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00U) /*!< No error */ +#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x01U) /*!< Parity error */ +#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x02U) /*!< Noise error */ +#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x04U) /*!< frame error */ +#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x08U) /*!< Overrun error */ +#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x10U) /*!< DMA transfer error */ +#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x20U) /*!< Receiver TimeOut error */ /** * @} @@ -288,7 +288,7 @@ typedef struct /** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity * @{ */ -#define SMARTCARD_POLARITY_LOW ((uint32_t)0x0000) +#define SMARTCARD_POLARITY_LOW ((uint32_t)0x0000U) #define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) #define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH)) /** @@ -298,7 +298,7 @@ typedef struct /** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase * @{ */ -#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x0000) +#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x0000U) #define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) #define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE)) /** @@ -308,7 +308,7 @@ typedef struct /** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit * @{ */ -#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x0000) +#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x0000U) #define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) #define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \ ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE)) @@ -319,7 +319,7 @@ typedef struct /** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD OneBit Sampling * @{ */ -#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x0000) +#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x0000U) #define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) #define IS_SMARTCARD_ONE_BIT_SAMPLE(ONEBIT) (((ONEBIT) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \ ((ONEBIT) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE)) @@ -332,7 +332,7 @@ typedef struct * @{ */ #define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) -#define SMARTCARD_NACK_DISABLE ((uint32_t)0x0000) +#define SMARTCARD_NACK_DISABLE ((uint32_t)0x0000U) #define IS_SMARTCARD_NACK(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \ ((NACK) == SMARTCARD_NACK_DISABLE)) /** @@ -342,7 +342,7 @@ typedef struct /** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable * @{ */ -#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000U) #define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) #define IS_SMARTCARD_TIMEOUT(TIMEOUT) (((TIMEOUT) == SMARTCARD_TIMEOUT_DISABLE) || \ ((TIMEOUT) == SMARTCARD_TIMEOUT_ENABLE)) @@ -364,14 +364,14 @@ typedef struct /** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD Advanced Features Initialization * @{ */ -#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) -#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) -#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) -#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) -#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) -#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) -#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) -#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) +#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000U) +#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001U) +#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002U) +#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004U) +#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008U) +#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010U) +#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020U) +#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080U) #define IS_SMARTCARD_ADVFEATURE_INIT(INIT) ((INIT) <= (SMARTCARD_ADVFEATURE_NO_INIT | \ SMARTCARD_ADVFEATURE_TXINVERT_INIT | \ SMARTCARD_ADVFEATURE_RXINVERT_INIT | \ @@ -387,7 +387,7 @@ typedef struct /** @defgroup SMARTCARD_Tx_Inv SMARTCARD Tx Inv * @{ */ -#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000U) #define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) #define IS_SMARTCARD_ADVFEATURE_TXINV(TXINV) (((TXINV) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \ ((TXINV) == SMARTCARD_ADVFEATURE_TXINV_ENABLE)) @@ -398,7 +398,7 @@ typedef struct /** @defgroup SMARTCARD_Rx_Inv SMARTCARD Rx Inv * @{ */ -#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000U) #define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) #define IS_SMARTCARD_ADVFEATURE_RXINV(RXINV) (((RXINV) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \ ((RXINV) == SMARTCARD_ADVFEATURE_RXINV_ENABLE)) @@ -409,7 +409,7 @@ typedef struct /** @defgroup SMARTCARD_Data_Inv SMARTCARD Data Inv * @{ */ -#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000U) #define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) #define IS_SMARTCARD_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \ ((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE)) @@ -420,7 +420,7 @@ typedef struct /** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD Rx Tx Swap * @{ */ -#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000U) #define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) #define IS_SMARTCARD_ADVFEATURE_SWAP(SWAP) (((SWAP) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \ ((SWAP) == SMARTCARD_ADVFEATURE_SWAP_ENABLE)) @@ -431,7 +431,7 @@ typedef struct /** @defgroup SMARTCARD_Overrun_Disable SMARTCARD Overrun Enabling * @{ */ -#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000U) #define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) #define IS_SMARTCARD_OVERRUN(OVERRUN) (((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \ ((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE)) @@ -442,7 +442,7 @@ typedef struct /** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD DMA on Rx Error * @{ */ -#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000U) #define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) #define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \ ((DMA) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR)) @@ -453,7 +453,7 @@ typedef struct /** @defgroup SMARTCARD_MSB_First SMARTCARD MSB First * @{ */ -#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000U) #define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) #define IS_SMARTCARD_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \ ((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE)) @@ -495,19 +495,19 @@ typedef struct * @{ */ -#define SMARTCARD_IT_PE ((uint16_t)0x0028) /*!< SMARTCARD parity error interruption */ -#define SMARTCARD_IT_TXE ((uint16_t)0x0727) /*!< SMARTCARD transmit data register empty interruption */ -#define SMARTCARD_IT_TC ((uint16_t)0x0626) /*!< SMARTCARD transmission complete interruption */ -#define SMARTCARD_IT_RXNE ((uint16_t)0x0525) /*!< SMARTCARD read data register not empty interruption */ -#define SMARTCARD_IT_IDLE ((uint16_t)0x0424) /*!< SMARTCARD idle line detection interruption */ +#define SMARTCARD_IT_PE ((uint16_t)0x0028U) /*!< SMARTCARD parity error interruption */ +#define SMARTCARD_IT_TXE ((uint16_t)0x0727U) /*!< SMARTCARD transmit data register empty interruption */ +#define SMARTCARD_IT_TC ((uint16_t)0x0626U) /*!< SMARTCARD transmission complete interruption */ +#define SMARTCARD_IT_RXNE ((uint16_t)0x0525U) /*!< SMARTCARD read data register not empty interruption */ +#define SMARTCARD_IT_IDLE ((uint16_t)0x0424U) /*!< SMARTCARD idle line detection interruption */ -#define SMARTCARD_IT_ERR ((uint16_t)0x0060) /*!< SMARTCARD error interruption */ -#define SMARTCARD_IT_ORE ((uint16_t)0x0300) /*!< SMARTCARD overrun error interruption */ -#define SMARTCARD_IT_NE ((uint16_t)0x0200) /*!< SMARTCARD noise error interruption */ -#define SMARTCARD_IT_FE ((uint16_t)0x0100) /*!< SMARTCARD frame error interruption */ +#define SMARTCARD_IT_ERR ((uint16_t)0x0060U) /*!< SMARTCARD error interruption */ +#define SMARTCARD_IT_ORE ((uint16_t)0x0300U) /*!< SMARTCARD overrun error interruption */ +#define SMARTCARD_IT_NE ((uint16_t)0x0200U) /*!< SMARTCARD noise error interruption */ +#define SMARTCARD_IT_FE ((uint16_t)0x0100U) /*!< SMARTCARD frame error interruption */ -#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B) /*!< SMARTCARD end of block interruption */ -#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A) /*!< SMARTCARD receiver timeout interruption */ +#define SMARTCARD_IT_EOB ((uint16_t)0x0C3BU) /*!< SMARTCARD end of block interruption */ +#define SMARTCARD_IT_RTO ((uint16_t)0x0B3AU) /*!< SMARTCARD receiver timeout interruption */ /** * @} */ @@ -543,7 +543,7 @@ typedef struct /** @defgroup SMARTCARD_CR3_SCAR_CNT_LSB_POS SMARTCARD CR3 LSB Position * @{ */ -#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17) +#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17U) /** * @} */ @@ -551,7 +551,7 @@ typedef struct /** @defgroup SMARTCARD_GTPR_GT_LSBPOS SMARTCARD GTPR GT LSB Position * @{ */ -#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8) +#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8U) /** * @} */ @@ -559,7 +559,7 @@ typedef struct /** @defgroup SMARTCARD_RTOR_BLEN_LSBPOS SMARTCARD RTOR BLEN LSB Position * @{ */ -#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24) +#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24U) /** * @} */ @@ -567,7 +567,7 @@ typedef struct /** @defgroup SMARTCARD_Interruption_Mask SMARTCARD Interruption Mask * @{ */ -#define SMARTCARD_IT_MASK ((uint16_t)0x001F) +#define SMARTCARD_IT_MASK ((uint16_t)0x001FU) /** * @} */ @@ -682,9 +682,9 @@ typedef struct * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Disables the specified SmartCard interrupt. * @param __HANDLE__: specifies the SMARTCARD Handle. * The Handle Instance which can be USART1 or USART2. @@ -700,8 +700,8 @@ typedef struct * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Checks whether the specified SmartCard interrupt has occurred or not. @@ -721,7 +721,7 @@ typedef struct * @arg SMARTCARD_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08U))) /** @brief Checks whether the specified SmartCard interrupt interrupt source is enabled. * @param __HANDLE__: specifies the SMARTCARD Handle. @@ -740,8 +740,8 @@ typedef struct * @arg SMARTCARD_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \ +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \ + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1U << \ (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK))) @@ -819,27 +819,27 @@ typedef struct * @param __BAUDRATE__: Baud rate set by the configuration function. * @retval Test result (TRUE or FALSE) */ -#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001) +#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001U) /** @brief Check the block length range. The maximum SMARTCARD block length is 0xFF. * @param __LENGTH__: block length. * @retval Test result (TRUE or FALSE) */ -#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF) +#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU) /** @brief Check the receiver timeout value. The maximum SMARTCARD receiver timeout * value is 0xFFFFFF. * @param __TIMEOUTVALUE__: receiver timeout value. * @retval Test result (TRUE or FALSE) */ -#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF) +#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) /** @brief Check the SMARTCARD autoretry counter value. The maximum number of * retransmissions is 0x7. * @param __COUNT__: number of retransmissions * @retval Test result (TRUE or FALSE) */ -#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7) +#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard_ex.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard_ex.c index 8a686f790b..c77bb8d615 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_smartcard_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief SMARTCARD HAL module driver. * * This file provides extended firmware functions to manage the following diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard_ex.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard_ex.h index ac2bfb677a..291cb3c102 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_smartcard_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smbus.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smbus.c index 2efbeec405..afbf8e9346 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smbus.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smbus.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_smbus.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief SMBUS HAL module driver. * * This file provides firmware functions to manage the following @@ -145,16 +145,16 @@ * @{ */ /* Private define ------------------------------------------------------------*/ -#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*Instance->ISR) @@ -268,7 +268,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /*---------------------------- SMBUSx OAR1 Configuration -------------------*/ /* Configure SMBUSx: Own Address1 and ack own address1 mode */ hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - if(hsmbus->Init.OwnAddress1 != 0) + if(hsmbus->Init.OwnAddress1 != 0U) { if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) { @@ -632,7 +632,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_ /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP); /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -673,7 +673,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -697,7 +697,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 hsmbus->XferOptions = XferOptions; /* Set NBYTE to transmit */ - SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus,0U,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ @@ -744,7 +744,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -772,13 +772,13 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ - if((hsmbus->XferSize == 1) || ((hsmbus->XferSize == 2) && (__SMBUS_GET_PEC_MODE(hsmbus) != RESET))) + if((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (__SMBUS_GET_PEC_MODE(hsmbus) != RESET))) { - SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus,0U,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } else { - SMBUS_TransferConfig(hsmbus,0,/*hsmbus->XferSize*/1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus,0U,/*hsmbus->XferSize*/1U, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP); } /* Clear ADDR flag after prepare the transfer parameters */ @@ -888,8 +888,8 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) */ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) { - uint32_t tickstart = 0x00; - __IO uint32_t SMBUS_Trials = 0x00; + uint32_t tickstart = 0x00U; + __IO uint32_t SMBUS_Trials = 0x00U; if(hsmbus->State == HAL_SMBUS_STATE_READY) { @@ -914,7 +914,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t tickstart = HAL_GetTick(); while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT)) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hsmbus->State = HAL_SMBUS_STATE_TIMEOUT; } @@ -993,7 +993,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t */ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) { - uint32_t tmpisrvalue = 0; + uint32_t tmpisrvalue = 0U; /* Use a local variable to store the current ISR flags */ /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */ @@ -1381,7 +1381,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) } else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET) { - if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0)) + if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount!=0U)) { DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD); @@ -1403,7 +1403,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) hsmbus->XferSize = hsmbus->XferCount; } } - else if((hsmbus->XferSize == 0)&&(hsmbus->XferCount==0)) + else if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount==0U)) { /* Call TxCpltCallback if no stop mode is set */ if(__SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) @@ -1437,7 +1437,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) } else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET) { - if(hsmbus->XferCount == 0) + if(hsmbus->XferCount == 0U) { /* Specific use case for Quick command */ if(hsmbus->pBuffPtr == NULL) @@ -1493,8 +1493,8 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) */ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) { - uint8_t TransferDirection = 0; - uint16_t SlaveAddrCode = 0; + uint8_t TransferDirection = 0U; + uint16_t SlaveAddrCode = 0U; /* Process Locked */ __HAL_LOCK(hsmbus); @@ -1505,7 +1505,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ - if(hsmbus->XferCount == 0) + if(hsmbus->XferCount == 0U) { /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); @@ -1560,15 +1560,15 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) hsmbus->XferSize--; hsmbus->XferCount--; - if(hsmbus->XferCount == 1) + if(hsmbus->XferCount == 1U) { /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */ /* or only the last Byte of Transfer */ /* So reset the RELOAD bit mode */ hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE; - SMBUS_TransferConfig(hsmbus,0 ,1 , hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus,0U ,1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } - else if(hsmbus->XferCount == 0) + else if(hsmbus->XferCount == 0U) { /* Last Byte is received, disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); @@ -1586,7 +1586,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) else { /* Set Reload for next Bytes */ - SMBUS_TransferConfig(hsmbus,0, 1, SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus,0U, 1U, SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP); /* Ack last Byte Read */ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; @@ -1599,7 +1599,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Check if all Datas have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if(hsmbus->XferCount > 0) + if(hsmbus->XferCount > 0U) { /* Write data to TXDR */ hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); @@ -1607,7 +1607,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) hsmbus->XferSize--; } - if(hsmbus->XferSize == 0) + if(hsmbus->XferSize == 0U) { /* Last Byte is Transmitted */ /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */ @@ -1646,7 +1646,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Clear ADDR flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); - hsmbus->XferOptions = 0; + hsmbus->XferOptions = 0U; hsmbus->PreviousState = hsmbus->State; hsmbus->State = HAL_SMBUS_STATE_READY; @@ -1673,7 +1673,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) */ static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) { - uint32_t tmpisr = 0; + uint32_t tmpisr = 0U; if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) { @@ -1715,7 +1715,7 @@ static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t */ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) { - uint32_t tmpisr = 0; + uint32_t tmpisr = 0U; if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) ) { @@ -1791,7 +1791,7 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t */ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { - uint32_t tickstart = 0x00; + uint32_t tickstart = 0x00U; tickstart = HAL_GetTick(); /* Wait until flag is set */ @@ -1802,7 +1802,7 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hsmbus->PreviousState = hsmbus->State; hsmbus->State= HAL_SMBUS_STATE_READY; @@ -1822,7 +1822,7 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hsmbus->PreviousState = hsmbus->State; hsmbus->State= HAL_SMBUS_STATE_READY; @@ -1860,7 +1860,7 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu */ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance)); @@ -1874,7 +1874,7 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)); /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \ + tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U ) & I2C_CR2_NBYTES) | \ (uint32_t)Mode | (uint32_t)Request); /* update CR2 register */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smbus.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smbus.h index 248d1a9203..97adc81684 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smbus.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smbus.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_smbus.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of SMBUS HAL module. ****************************************************************************** * @attention @@ -108,16 +108,16 @@ typedef struct * @brief HAL States definition * @{ */ -#define HAL_SMBUS_STATE_RESET 0x00 /*!< SMBUS not yet initialized or disabled */ -#define HAL_SMBUS_STATE_READY 0x01 /*!< SMBUS initialized and ready for use */ -#define HAL_SMBUS_STATE_BUSY 0x02 /*!< SMBUS internal process is ongoing */ -#define HAL_SMBUS_STATE_MASTER_BUSY_TX 0x12 /*!< Master Data Transmission process is ongoing */ -#define HAL_SMBUS_STATE_MASTER_BUSY_RX 0x22 /*!< Master Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_SLAVE_BUSY_TX 0x32 /*!< Slave Data Transmission process is ongoing */ -#define HAL_SMBUS_STATE_SLAVE_BUSY_RX 0x42 /*!< Slave Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_TIMEOUT 0x03 /*!< Timeout state */ -#define HAL_SMBUS_STATE_ERROR 0x04 /*!< Reception process is ongoing */ -#define HAL_SMBUS_STATE_LISTEN 0x08 /*!< Address Listen Mode is ongoing */ +#define HAL_SMBUS_STATE_RESET 0x00U /*!< SMBUS not yet initialized or disabled */ +#define HAL_SMBUS_STATE_READY 0x01U /*!< SMBUS initialized and ready for use */ +#define HAL_SMBUS_STATE_BUSY 0x02U /*!< SMBUS internal process is ongoing */ +#define HAL_SMBUS_STATE_MASTER_BUSY_TX 0x12U /*!< Master Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_MASTER_BUSY_RX 0x22U /*!< Master Data Reception process is ongoing */ +#define HAL_SMBUS_STATE_SLAVE_BUSY_TX 0x32U /*!< Slave Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_SLAVE_BUSY_RX 0x42U /*!< Slave Data Reception process is ongoing */ +#define HAL_SMBUS_STATE_TIMEOUT 0x03U /*!< Timeout state */ +#define HAL_SMBUS_STATE_ERROR 0x04U /*!< Reception process is ongoing */ +#define HAL_SMBUS_STATE_LISTEN 0x08U /*!< Address Listen Mode is ongoing */ /** * @} */ @@ -126,15 +126,15 @@ typedef struct * @brief SMBUS Error Code * @{ */ -#define HAL_SMBUS_ERROR_NONE 0x00 /*!< No error */ -#define HAL_SMBUS_ERROR_BERR 0x01 /*!< BERR error */ -#define HAL_SMBUS_ERROR_ARLO 0x02 /*!< ARLO error */ -#define HAL_SMBUS_ERROR_ACKF 0x04 /*!< ACKF error */ -#define HAL_SMBUS_ERROR_OVR 0x08 /*!< OVR error */ -#define HAL_SMBUS_ERROR_HALTIMEOUT 0x10 /*!< Timeout error */ -#define HAL_SMBUS_ERROR_BUSTIMEOUT 0x20 /*!< Bus Timeout error */ -#define HAL_SMBUS_ERROR_ALERT 0x40 /*!< Alert error */ -#define HAL_SMBUS_ERROR_PECERR 0x80 /*!< PEC error */ +#define HAL_SMBUS_ERROR_NONE 0x00U /*!< No error */ +#define HAL_SMBUS_ERROR_BERR 0x01U /*!< BERR error */ +#define HAL_SMBUS_ERROR_ARLO 0x02U /*!< ARLO error */ +#define HAL_SMBUS_ERROR_ACKF 0x04U /*!< ACKF error */ +#define HAL_SMBUS_ERROR_OVR 0x08U /*!< OVR error */ +#define HAL_SMBUS_ERROR_HALTIMEOUT 0x10U /*!< Timeout error */ +#define HAL_SMBUS_ERROR_BUSTIMEOUT 0x20U /*!< Bus Timeout error */ +#define HAL_SMBUS_ERROR_ALERT 0x40U /*!< Alert error */ +#define HAL_SMBUS_ERROR_PECERR 0x80U /*!< PEC error */ /** * @} */ @@ -179,7 +179,7 @@ typedef struct /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter * @{ */ -#define SMBUS_ANALOGFILTER_ENABLE ((uint32_t)0x00000000) +#define SMBUS_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U) #define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ @@ -191,8 +191,8 @@ typedef struct /** @defgroup SMBUS_addressing_mode SMBUS Addressing Mode * @{ */ -#define SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001) -#define SMBUS_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002) +#define SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001U) +#define SMBUS_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002U) #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) @@ -204,7 +204,7 @@ typedef struct * @{ */ -#define SMBUS_DUALADDRESS_DISABLE ((uint32_t)0x00000000) +#define SMBUS_DUALADDRESS_DISABLE ((uint32_t)0x00000000U) #define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ @@ -217,14 +217,14 @@ typedef struct * @{ */ -#define SMBUS_OA2_NOMASK ((uint8_t)0x00) -#define SMBUS_OA2_MASK01 ((uint8_t)0x01) -#define SMBUS_OA2_MASK02 ((uint8_t)0x02) -#define SMBUS_OA2_MASK03 ((uint8_t)0x03) -#define SMBUS_OA2_MASK04 ((uint8_t)0x04) -#define SMBUS_OA2_MASK05 ((uint8_t)0x05) -#define SMBUS_OA2_MASK06 ((uint8_t)0x06) -#define SMBUS_OA2_MASK07 ((uint8_t)0x07) +#define SMBUS_OA2_NOMASK ((uint8_t)0x00U) +#define SMBUS_OA2_MASK01 ((uint8_t)0x01U) +#define SMBUS_OA2_MASK02 ((uint8_t)0x02U) +#define SMBUS_OA2_MASK03 ((uint8_t)0x03U) +#define SMBUS_OA2_MASK04 ((uint8_t)0x04U) +#define SMBUS_OA2_MASK05 ((uint8_t)0x05U) +#define SMBUS_OA2_MASK06 ((uint8_t)0x06U) +#define SMBUS_OA2_MASK07 ((uint8_t)0x07U) #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ ((MASK) == SMBUS_OA2_MASK01) || \ @@ -242,7 +242,7 @@ typedef struct /** @defgroup SMBUS_general_call_addressing_mode SMBUS General Call Enabling * @{ */ -#define SMBUS_GENERALCALL_DISABLE ((uint32_t)0x00000000) +#define SMBUS_GENERALCALL_DISABLE ((uint32_t)0x00000000U) #define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ @@ -254,7 +254,7 @@ typedef struct /** @defgroup SMBUS_nostretch_mode SMBUS Nostretch Enabling * @{ */ -#define SMBUS_NOSTRETCH_DISABLE ((uint32_t)0x00000000) +#define SMBUS_NOSTRETCH_DISABLE ((uint32_t)0x00000000U) #define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ @@ -266,7 +266,7 @@ typedef struct /** @defgroup SMBUS_packet_error_check_mode SMBUS Packet Error Check Enabling * @{ */ -#define SMBUS_PEC_DISABLE ((uint32_t)0x00000000) +#define SMBUS_PEC_DISABLE ((uint32_t)0x00000000U) #define SMBUS_PEC_ENABLE I2C_CR1_PECEN #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ @@ -279,7 +279,7 @@ typedef struct * @{ */ #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBHEN) -#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (uint32_t)(0x00000000) +#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (uint32_t)(0x00000000U) #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBDEN) #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ @@ -293,7 +293,7 @@ typedef struct * @{ */ -#define SMBUS_SOFTEND_MODE ((uint32_t)0x00000000) +#define SMBUS_SOFTEND_MODE ((uint32_t)0x00000000U) #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE @@ -313,7 +313,7 @@ typedef struct * @{ */ -#define SMBUS_NO_STARTSTOP ((uint32_t)0x00000000) +#define SMBUS_NO_STARTSTOP ((uint32_t)0x00000000U) #define SMBUS_GENERATE_STOP I2C_CR2_STOP #define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) #define SMBUS_GENERATE_START_WRITE I2C_CR2_START @@ -471,7 +471,7 @@ typedef struct * @arg SMBUS_FLAG_DIR: Transfer direction (slave mode) * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define SMBUS_FLAG_MASK ((uint32_t)0x0001FFFF) +#define SMBUS_FLAG_MASK ((uint32_t)0x0001FFFFU) #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) /** @brief Clears the SMBUS pending flags which are cleared by writing 1 in a specific bit. @@ -502,15 +502,15 @@ typedef struct #define __SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) -#define __SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17) -#define __SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16) +#define __SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) +#define __SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) #define __SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) #define __SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) #define __SMBUS_GET_ALERT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= I2C_CR2_NACK) -#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) -#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) +#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FFU) +#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_spi.c index 652f95e07b..3b4553d383 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_spi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_spi.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief SPI HAL module driver. * * This file provides firmware functions to manage the following @@ -164,7 +164,7 @@ /** @addtogroup SPI_Private * @{ */ -#define SPI_TIMEOUT_VALUE 10 +#define SPI_TIMEOUT_VALUE 10U /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -277,7 +277,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) ); /* Configure : NSS management */ - WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode)); + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode)); /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ /* Configure : CRC Polynomial */ @@ -429,7 +429,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if(hspi->State == HAL_SPI_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -449,11 +449,11 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint hspi->TxXferCount = Size; /*Init field not used in handle to zero */ - hspi->TxISR = 0; - hspi->RxISR = 0; + hspi->TxISR = 0U; + hspi->RxISR = 0U; hspi->pRxBuffPtr = NULL; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; /* Reset CRC Calculation */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) @@ -477,13 +477,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Transmit data in 8 Bit mode */ if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) { - if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01)) + if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01U)) { hspi->Instance->DR = (*hspi->pTxBuffPtr++); hspi->TxXferCount--; } - while(hspi->TxXferCount > 0) + while(hspi->TxXferCount > 0U) { /* Wait until TXE flag is set to send data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) @@ -502,14 +502,14 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Transmit data in 16 Bit mode */ else { - if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) + if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) { hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr+=2; + hspi->pTxBuffPtr+=2U; hspi->TxXferCount--; } - while(hspi->TxXferCount > 0) + while(hspi->TxXferCount > 0U) { /* Wait until TXE flag is set to send data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) @@ -517,7 +517,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint return HAL_TIMEOUT; } hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr+=2; + hspi->pTxBuffPtr+=2U; hspi->TxXferCount--; } /* Enable CRC Transmission */ @@ -571,11 +571,11 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - __IO uint16_t tmpreg = 0; + __IO uint16_t tmpreg = 0U; if(hspi->State == HAL_SPI_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -592,11 +592,11 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 hspi->RxXferCount = Size; /*Init field not used in handle to zero */ - hspi->RxISR = 0; - hspi->TxISR = 0; + hspi->RxISR = 0U; + hspi->TxISR = 0U; hspi->pTxBuffPtr = NULL; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) @@ -629,7 +629,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Receive data in 8 Bit mode */ if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) { - while(hspi->RxXferCount > 1) + while(hspi->RxXferCount > 1U) { /* Wait until RXNE flag is set */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) @@ -649,7 +649,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Receive data in 16 Bit mode */ else { - while(hspi->RxXferCount > 1) + while(hspi->RxXferCount > 1U) { /* Wait until RXNE flag is set to read data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) @@ -658,7 +658,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; + hspi->pRxBuffPtr+=2U; hspi->RxXferCount--; } /* Enable CRC Reception */ @@ -683,7 +683,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 else { *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; + hspi->pRxBuffPtr+=2U; } hspi->RxXferCount--; @@ -747,11 +747,11 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { - __IO uint16_t tmpreg = 0; + __IO uint16_t tmpreg = 0U; if((hspi->State == HAL_SPI_STATE_READY) || (hspi->State == HAL_SPI_STATE_BUSY_RX)) { - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -780,8 +780,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->TxXferCount = Size; /*Init field not used in handle to zero */ - hspi->RxISR = 0; - hspi->TxISR = 0; + hspi->RxISR = 0U; + hspi->TxISR = 0U; /* Reset CRC Calculation */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) @@ -799,13 +799,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Transmit and Receive data in 16 Bit mode */ if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) { - if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) + if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01U))) { hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr+=2; + hspi->pTxBuffPtr+=2U; hspi->TxXferCount--; } - if(hspi->TxXferCount == 0) + if(hspi->TxXferCount == 0U) { /* Enable CRC Transmission */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) @@ -820,12 +820,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; + hspi->pRxBuffPtr+=2U; hspi->RxXferCount--; } else { - while(hspi->TxXferCount > 0) + while(hspi->TxXferCount > 0U) { /* Wait until TXE flag is set to send data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) @@ -834,11 +834,11 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr+=2; + hspi->pTxBuffPtr+=2U; hspi->TxXferCount--; /* Enable CRC Transmission */ - if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } @@ -850,7 +850,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; + hspi->pRxBuffPtr+=2U; hspi->RxXferCount--; } /* Receive the last byte */ @@ -863,7 +863,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; + hspi->pRxBuffPtr+=2U; hspi->RxXferCount--; } } @@ -871,12 +871,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Transmit and Receive data in 8 Bit mode */ else { - if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) + if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01U))) { hspi->Instance->DR = (*hspi->pTxBuffPtr++); hspi->TxXferCount--; } - if(hspi->TxXferCount == 0) + if(hspi->TxXferCount == 0U) { /* Enable CRC Transmission */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) @@ -895,7 +895,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } else { - while(hspi->TxXferCount > 0) + while(hspi->TxXferCount > 0U) { /* Wait until TXE flag is set to send data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) @@ -907,7 +907,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->TxXferCount--; /* Enable CRC Transmission */ - if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } @@ -994,7 +994,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u { if(hspi->State == HAL_SPI_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1015,10 +1015,10 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u hspi->TxXferCount = Size; /*Init field not used in handle to zero */ - hspi->RxISR = 0; + hspi->RxISR = 0U; hspi->pRxBuffPtr = NULL; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) @@ -1071,7 +1071,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui { if(hspi->State == HAL_SPI_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1089,10 +1089,10 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui hspi->RxXferCount = Size ; /*Init field not used in handle to zero */ - hspi->TxISR = 0; + hspi->TxISR = 0U; hspi->pTxBuffPtr = NULL; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) @@ -1154,7 +1154,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p if((hspi->State == HAL_SPI_STATE_READY) || \ ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) { - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -1223,7 +1223,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, { if(hspi->State == HAL_SPI_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { /* Process Unlocked */ __HAL_UNLOCK(hspi); @@ -1245,12 +1245,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, hspi->TxXferCount = Size; /*Init field not used in handle to zero */ - hspi->TxISR = 0; - hspi->RxISR = 0; + hspi->TxISR = 0U; + hspi->RxISR = 0U; hspi->pRxBuffPtr = NULL; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) @@ -1317,7 +1317,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u { if(hspi->State == HAL_SPI_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { /* Process Unlocked */ __HAL_UNLOCK(hspi); @@ -1336,12 +1336,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u hspi->RxXferCount = Size; /*Init field not used in handle to zero */ - hspi->RxISR = 0; - hspi->TxISR = 0; + hspi->RxISR = 0U; + hspi->TxISR = 0U; hspi->pTxBuffPtr = NULL; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) @@ -1418,7 +1418,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * if((hspi->State == HAL_SPI_STATE_READY) || \ ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) { - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -1447,8 +1447,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * hspi->RxXferCount = Size; /*Init field not used in handle to zero */ - hspi->RxISR = 0; - hspi->TxISR = 0; + hspi->RxISR = 0U; + hspi->TxISR = 0U; /* Reset CRC Calculation */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) @@ -1902,11 +1902,11 @@ static void SPI_TxISR(SPI_HandleTypeDef *hspi) else { hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr+=2; + hspi->pTxBuffPtr+=2U; } hspi->TxXferCount--; - if(hspi->TxXferCount == 0) + if(hspi->TxXferCount == 0U) { if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { @@ -1925,7 +1925,7 @@ static void SPI_TxISR(SPI_HandleTypeDef *hspi) */ static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi) { - __IO uint16_t tmpreg = 0; + __IO uint16_t tmpreg = 0U; if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { @@ -2014,11 +2014,11 @@ static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi) else { *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; + hspi->pRxBuffPtr+=2U; } hspi->RxXferCount--; - if(hspi->RxXferCount==0) + if(hspi->RxXferCount==0U) { SPI_RxCloseIRQHandler(hspi); } @@ -2041,18 +2041,18 @@ static void SPI_RxISR(SPI_HandleTypeDef *hspi) else { *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; + hspi->pRxBuffPtr+=2U; } hspi->RxXferCount--; /* Enable CRC Transmission */ - if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { /* Set CRC Next to calculate CRC on Rx side */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } - if(hspi->RxXferCount == 0) + if(hspi->RxXferCount == 0U) { SPI_RxCloseIRQHandler(hspi); } @@ -2070,7 +2070,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* DMA Normal Mode */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { /* Wait until TXE flag is set to send data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) @@ -2087,7 +2087,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } - hspi->TxXferCount = 0; + hspi->TxXferCount = 0U; hspi->State = HAL_SPI_STATE_READY; } @@ -2116,12 +2116,12 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - __IO uint16_t tmpreg = 0; + __IO uint16_t tmpreg = 0U; SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { /* Disable Rx DMA Request */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); @@ -2162,7 +2162,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) __HAL_SPI_DISABLE(hspi); } - hspi->RxXferCount = 0; + hspi->RxXferCount = 0U; hspi->State = HAL_SPI_STATE_READY; /* Check if Errors has been detected during transfer */ @@ -2189,10 +2189,10 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - __IO uint16_t tmpreg = 0; + __IO uint16_t tmpreg = 0U; SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { /* CRC Calculation handling */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) @@ -2236,8 +2236,8 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) /* Disable Rx DMA Request */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - hspi->TxXferCount = 0; - hspi->RxXferCount = 0; + hspi->TxXferCount = 0U; + hspi->RxXferCount = 0U; hspi->State = HAL_SPI_STATE_READY; @@ -2305,8 +2305,8 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) static void SPI_DMAError(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hspi->TxXferCount = 0; - hspi->RxXferCount = 0; + hspi->TxXferCount = 0U; + hspi->RxXferCount = 0U; hspi->State= HAL_SPI_STATE_READY; SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); HAL_SPI_ErrorCallback(hspi); @@ -2323,7 +2323,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Get tick */ tickstart = HAL_GetTick(); @@ -2335,7 +2335,7 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master @@ -2369,7 +2369,7 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_spi.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_spi.h index 8a3d0fea18..42dfde9b1b 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_spi.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_spi.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_spi.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention @@ -108,13 +108,13 @@ typedef struct */ typedef enum { - HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */ - HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */ - HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */ - HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */ + HAL_SPI_STATE_RESET = 0x00U, /*!< SPI not yet initialized or disabled */ + HAL_SPI_STATE_READY = 0x01U, /*!< SPI initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02U, /*!< SPI process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x03U /*!< SPI error state */ }HAL_SPI_StateTypeDef; @@ -169,13 +169,13 @@ typedef struct __SPI_HandleTypeDef * @defgroup SPI_ErrorCode SPI Error Code * @{ */ -#define HAL_SPI_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_SPI_ERROR_MODF ((uint32_t)0x01) /*!< MODF error */ -#define HAL_SPI_ERROR_CRC ((uint32_t)0x02) /*!< CRC error */ -#define HAL_SPI_ERROR_OVR ((uint32_t)0x04) /*!< OVR error */ -#define HAL_SPI_ERROR_FRE ((uint32_t)0x08) /*!< FRE error */ -#define HAL_SPI_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ -#define HAL_SPI_ERROR_FLAG ((uint32_t)0x20) /*!< Flag: RXNE,TXE, BSY */ +#define HAL_SPI_ERROR_NONE ((uint32_t)0x00U) /*!< No error */ +#define HAL_SPI_ERROR_MODF ((uint32_t)0x01U) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC ((uint32_t)0x02U) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR ((uint32_t)0x04U) /*!< OVR error */ +#define HAL_SPI_ERROR_FRE ((uint32_t)0x08U) /*!< FRE error */ +#define HAL_SPI_ERROR_DMA ((uint32_t)0x10U) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG ((uint32_t)0x20U) /*!< Flag: RXNE,TXE, BSY */ /** * @} */ @@ -183,7 +183,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_mode SPI mode * @{ */ -#define SPI_MODE_SLAVE ((uint32_t)0x00000000) +#define SPI_MODE_SLAVE ((uint32_t)0x00000000U) #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /** @@ -193,7 +193,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Direction_mode SPI Direction mode * @{ */ -#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) +#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000U) #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE @@ -204,7 +204,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_data_size SPI data size * @{ */ -#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000) +#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000U) #define SPI_DATASIZE_16BIT SPI_CR1_DFF /** @@ -214,7 +214,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Clock_Polarity SPI Clock Polarity * @{ */ -#define SPI_POLARITY_LOW ((uint32_t)0x00000000) +#define SPI_POLARITY_LOW ((uint32_t)0x00000000U) #define SPI_POLARITY_HIGH SPI_CR1_CPOL /** @@ -224,7 +224,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Clock_Phase SPI Clock Phase * @{ */ -#define SPI_PHASE_1EDGE ((uint32_t)0x00000000) +#define SPI_PHASE_1EDGE ((uint32_t)0x00000000U) #define SPI_PHASE_2EDGE SPI_CR1_CPHA /** @@ -235,8 +235,8 @@ typedef struct __SPI_HandleTypeDef * @{ */ #define SPI_NSS_SOFT SPI_CR1_SSM -#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) -#define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16)) +#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) +#define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16U)) /** * @} @@ -245,7 +245,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler * @{ */ -#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000) +#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000U) #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0) #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1) #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0) @@ -261,7 +261,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission * @{ */ -#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000) +#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000U) #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST /** @@ -271,7 +271,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_TI_mode SPI TI mode * @{ */ -#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000) +#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000U) #define SPI_TIMODE_ENABLE SPI_CR2_FRF /** @@ -281,7 +281,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_CRC_Calculation SPI CRC Calculation * @{ */ -#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000) +#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN /** @@ -554,7 +554,7 @@ typedef struct __SPI_HandleTypeDef * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 * @retval None */ -#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1) && ((__POLYNOMIAL__) <= 0xFFFF)) +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU)) /** @brief Sets the SPI transmit-only mode. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim.c index 05274a65d6..1708b3964a 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_tim.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief TIM HAL module driver. * @brief This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -402,7 +402,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat } else if((htim->State == HAL_TIM_STATE_READY)) { - if((pData == 0 ) && (Length > 0)) + if((pData == 0U ) && (Length > 0U)) { return HAL_ERROR; } @@ -773,7 +773,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else if((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if(((uint32_t)pData == 0U ) && (Length > 0U)) { return HAL_ERROR; } @@ -1251,7 +1251,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } else if((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if(((uint32_t)pData == 0U ) && (Length > 0U)) { return HAL_ERROR; } @@ -1722,7 +1722,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else if((htim->State == HAL_TIM_STATE_READY)) { - if((pData == 0 ) && (Length > 0)) + if((pData == 0U ) && (Length > 0U)) { return HAL_ERROR; } @@ -2162,9 +2162,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) { - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpsmcr = 0U; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; /* Check the TIM handle allocation */ if(htim == NULL) @@ -2218,18 +2218,18 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); - tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8)); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); - tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8); - tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); - tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; @@ -2513,7 +2513,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch } else if((htim->State == HAL_TIM_STATE_READY)) { - if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) + if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U)) { return HAL_ERROR; } @@ -2694,7 +2694,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00) + if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) { HAL_TIM_IC_CaptureCallback(htim); } @@ -2716,7 +2716,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00) + if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) { HAL_TIM_IC_CaptureCallback(htim); } @@ -2737,7 +2737,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00) + if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) { HAL_TIM_IC_CaptureCallback(htim); } @@ -2758,7 +2758,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00) + if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) { HAL_TIM_IC_CaptureCallback(htim); } @@ -2817,7 +2817,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) * parameters in the TIM_OC_InitTypeDef. * @param htim : TIM handle * @param sConfig: TIM Output Compare configuration structure - * @param Channel: TIM Channels to be enabled. + * @param Channel: TIM Channel to be configure. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2832,7 +2832,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - /* Check input state */ + /* Process lock */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; @@ -2935,7 +2935,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; /* Set the IC2PSC value */ - htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8); + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); } else if (Channel == TIM_CHANNEL_3) { @@ -2967,7 +2967,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; /* Set the IC4PSC value */ - htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8); + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } htim->State = HAL_TIM_STATE_READY; @@ -2982,7 +2982,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT * parameters in the TIM_OC_InitTypeDef. * @param htim : TIM handle * @param sConfig: TIM PWM configuration structure - * @param Channel: TIM Channels to be enabled. + * @param Channel: TIM Channel to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3030,7 +3030,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_Init /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; } break; @@ -3060,7 +3060,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_Init /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; } break; @@ -3235,7 +3235,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t } else if((htim->State == HAL_TIM_STATE_READY)) { - if((BurstBuffer == 0 ) && (BurstLength > 0)) + if((BurstBuffer == 0U ) && (BurstLength > 0U)) { return HAL_ERROR; } @@ -3267,7 +3267,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC2: @@ -3279,7 +3279,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC3: @@ -3291,7 +3291,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC4: @@ -3303,7 +3303,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_TRIGGER: @@ -3315,7 +3315,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); } break; default: @@ -3437,7 +3437,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B } else if((htim->State == HAL_TIM_STATE_READY)) { - if((BurstBuffer == 0 ) && (BurstLength > 0)) + if((BurstBuffer == 0U ) && (BurstLength > 0U)) { return HAL_ERROR; } @@ -3457,7 +3457,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC1: @@ -3469,7 +3469,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC2: @@ -3481,7 +3481,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC3: @@ -3493,7 +3493,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC4: @@ -3505,7 +3505,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_TRIGGER: @@ -3517,7 +3517,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; default: @@ -3750,7 +3750,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) { - uint32_t tmpsmcr = 0; + uint32_t tmpsmcr = 0U; /* Process Locked */ __HAL_LOCK(htim); @@ -3896,7 +3896,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo */ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) { - uint32_t tmpcr2 = 0; + uint32_t tmpcr2 = 0U; /* Check the parameters */ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); @@ -4003,7 +4003,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, */ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; __HAL_LOCK(htim); @@ -4386,7 +4386,7 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) */ static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { - uint32_t tmpcr1 = 0; + uint32_t tmpcr1 = 0U; tmpcr1 = TIMx->CR1; /* Set TIM Time Base Unit parameters ---------------------------------------*/ @@ -4424,9 +4424,9 @@ static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structur */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; @@ -4471,9 +4471,9 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) */ static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; @@ -4491,12 +4491,12 @@ static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpccmrx &= ~TIM_CCMR1_CC2S; /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); + tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 4); + tmpccer |= (OC_Config->OCPolarity << 4U); /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; @@ -4519,9 +4519,9 @@ static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; @@ -4543,7 +4543,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 8); + tmpccer |= (OC_Config->OCPolarity << 8U); /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; @@ -4566,9 +4566,9 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; @@ -4586,12 +4586,12 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpccmrx &= ~TIM_CCMR2_CC4S; /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); + tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 12); + tmpccer |= (OC_Config->OCPolarity << 12U); /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; @@ -4626,8 +4626,8 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; @@ -4648,7 +4648,7 @@ static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F); + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); @@ -4673,8 +4673,8 @@ static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; @@ -4683,7 +4683,7 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= (TIM_ICFilter << 4); + tmpccmr1 |= (TIM_ICFilter << 4U); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); @@ -4714,8 +4714,8 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; @@ -4724,15 +4724,15 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; - tmpccmr1 |= (TIM_ICSelection << 8); + tmpccmr1 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F); + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; @@ -4753,8 +4753,8 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; @@ -4763,11 +4763,11 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= (TIM_ICFilter << 12); + tmpccmr1 |= (TIM_ICFilter << 12U); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (TIM_ICPolarity << 4); + tmpccer |= (TIM_ICPolarity << 4U); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; @@ -4794,8 +4794,8 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { - uint32_t tmpccmr2 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr2 = 0U; + uint32_t tmpccer = 0U; /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; @@ -4808,11 +4808,11 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC3F; - tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F); + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); /* Select the Polarity and set the CC3E Bit */ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; @@ -4839,8 +4839,8 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { - uint32_t tmpccmr2 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr2 = 0U; + uint32_t tmpccer = 0U; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; @@ -4849,15 +4849,15 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; - tmpccmr2 |= (TIM_ICSelection << 8); + tmpccmr2 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC4F; - tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F); + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); /* Select the Polarity and set the CC4E Bit */ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; @@ -4881,7 +4881,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) { - uint32_t tmpsmcr = 0; + uint32_t tmpsmcr = 0U; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; @@ -4912,7 +4912,7 @@ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { - uint32_t tmpsmcr = 0; + uint32_t tmpsmcr = 0U; tmpsmcr = TIMx->SMCR; @@ -4941,7 +4941,7 @@ static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, */ static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) { - uint32_t tmp = 0; + uint32_t tmp = 0U; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(TIMx,Channel)); @@ -4966,9 +4966,9 @@ static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Chan static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) { - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpsmcr = 0U; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; @@ -5017,7 +5017,7 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); /* Write to TIMx CCMR1 and CCER registers */ htim->Instance->CCMR1 = tmpccmr1; diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim.h index 51412ff105..e9e47f720f 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_tim.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention @@ -284,11 +284,11 @@ typedef struct { */ typedef enum { - HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ - HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ }HAL_TIM_StateTypeDef; /** * @} @@ -302,11 +302,11 @@ typedef enum */ typedef enum { - HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ - HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ - HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ }HAL_TIM_ActiveChannel; /** * @} @@ -341,15 +341,15 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ -#define IS_TIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0xFFFF) +#define IS_TIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0xFFFFU) -#define IS_TIM_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFF) +#define IS_TIM_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFFU) /** @defgroup TIM_Input_Channel_Polarity Input channel polarity * @{ */ -#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U) /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ /** @@ -360,7 +360,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state * @{ */ #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000U) /*!< Polarity for ETR source */ /** * @} */ @@ -368,7 +368,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /** @defgroup TIM_ETR_Prescaler ETR prescaler * @{ */ -#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000U) /*!< No prescaler is used */ #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ @@ -379,7 +379,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /** @defgroup TIM_Counter_Mode Counter mode * @{ */ -#define TIM_COUNTERMODE_UP ((uint32_t)0x0000) +#define TIM_COUNTERMODE_UP ((uint32_t)0x0000U) #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 @@ -399,7 +399,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /** @defgroup TIM_ClockDivision Clock division * @{ */ -#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) +#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000U) #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) /** @@ -413,7 +413,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /** @defgroup TIM_Output_Compare_and_PWM_modes Output compare and PWM modes * @{ */ -#define TIM_OCMODE_TIMING ((uint32_t)0x0000) +#define TIM_OCMODE_TIMING ((uint32_t)0x0000U) #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) @@ -439,7 +439,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /** @defgroup TIM_Output_Compare_State Output compare state * @{ */ -#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) +#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000U) #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) /** * @} @@ -448,7 +448,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /** @defgroup TIM_Output_Fast_State Output fast state * @{ */ -#define TIM_OCFAST_DISABLE ((uint32_t)0x0000) +#define TIM_OCFAST_DISABLE ((uint32_t)0x0000U) #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) /** * @} @@ -459,7 +459,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /** @defgroup TIM_Output_Compare_N_State Output compare N state * @{ */ -#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) +#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000U) #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) /** * @} @@ -468,7 +468,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /** @defgroup TIM_Output_Compare_Polarity Output compare polarity * @{ */ -#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) +#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000U) #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) /** * @} @@ -479,11 +479,11 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /** @defgroup TIM_Channel TIM channels * @{ */ -#define TIM_CHANNEL_1 ((uint32_t)0x0000) -#define TIM_CHANNEL_2 ((uint32_t)0x0004) -#define TIM_CHANNEL_3 ((uint32_t)0x0008) -#define TIM_CHANNEL_4 ((uint32_t)0x000C) -#define TIM_CHANNEL_ALL ((uint32_t)0x0018) +#define TIM_CHANNEL_1 ((uint32_t)0x0000U) +#define TIM_CHANNEL_2 ((uint32_t)0x0004U) +#define TIM_CHANNEL_3 ((uint32_t)0x0008U) +#define TIM_CHANNEL_4 ((uint32_t)0x000CU) +#define TIM_CHANNEL_ALL ((uint32_t)0x0018U) /** * @} */ @@ -531,7 +531,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /** @defgroup TIM_Input_Capture_Prescaler Input capture prescaler * @{ */ -#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV1 ((uint32_t)0x0000U) /*!< Capture performed each time an edge is detected on the capture input */ #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ @@ -547,7 +547,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state * @{ */ #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) -#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) +#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000U) /** * @} */ @@ -592,7 +592,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /** * @} */ -#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FF) == 0x00000000) && ((__SOURCE__) != 0x00000000)) +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) @@ -608,7 +608,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /** * @} */ -#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0) == 0x00000000) && ((__SOURCE__) != 0x00000000)) +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) /** @defgroup TIM_Flag_definition Flag definition @@ -633,7 +633,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) -#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) +#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000U) #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) @@ -691,13 +691,13 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /* Check clock filter */ -#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) /** @defgroup TIM_ClearInput_Source Clear input source * @{ */ -#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) -#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) +#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U) +#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U) /** * @} */ @@ -735,13 +735,13 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /* Check IC filter */ -#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU) /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection * @{ */ -#define TIM_TRGO_RESET ((uint32_t)0x0000) +#define TIM_TRGO_RESET ((uint32_t)0x0000U) #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) @@ -766,11 +766,11 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /** @defgroup TIM_Slave_Mode Slave mode * @{ */ -#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) -#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004) -#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005) -#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006) -#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007) +#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000U) +#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004U) +#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005U) +#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006U) +#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007U) /** * @} */ @@ -784,8 +784,8 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state * @{ */ -#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) -#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) +#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080U) +#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000U) /** * @} */ @@ -795,15 +795,15 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /** @defgroup TIM_Trigger_Selection Trigger selection * @{ */ -#define TIM_TS_ITR0 ((uint32_t)0x0000) -#define TIM_TS_ITR1 ((uint32_t)0x0010) -#define TIM_TS_ITR2 ((uint32_t)0x0020) -#define TIM_TS_ITR3 ((uint32_t)0x0030) -#define TIM_TS_TI1F_ED ((uint32_t)0x0040) -#define TIM_TS_TI1FP1 ((uint32_t)0x0050) -#define TIM_TS_TI2FP2 ((uint32_t)0x0060) -#define TIM_TS_ETRF ((uint32_t)0x0070) -#define TIM_TS_NONE ((uint32_t)0xFFFF) +#define TIM_TS_ITR0 ((uint32_t)0x0000U) +#define TIM_TS_ITR1 ((uint32_t)0x0010U) +#define TIM_TS_ITR2 ((uint32_t)0x0020U) +#define TIM_TS_ITR3 ((uint32_t)0x0030U) +#define TIM_TS_TI1F_ED ((uint32_t)0x0040U) +#define TIM_TS_TI1FP1 ((uint32_t)0x0050U) +#define TIM_TS_TI2FP2 ((uint32_t)0x0060U) +#define TIM_TS_ETRF ((uint32_t)0x0070U) +#define TIM_TS_NONE ((uint32_t)0xFFFFU) /** * @} */ @@ -857,13 +857,13 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /* Check trigger filter */ -#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) /** @defgroup TIM_TI1_Selection TI1 selection * @{ */ -#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) +#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000U) #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) /** * @} @@ -875,24 +875,24 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /** @defgroup TIM_DMA_Base_address DMA base address * @{ */ -#define TIM_DMABASE_CR1 (0x00000000) -#define TIM_DMABASE_CR2 (0x00000001) -#define TIM_DMABASE_SMCR (0x00000002) -#define TIM_DMABASE_DIER (0x00000003) -#define TIM_DMABASE_SR (0x00000004) -#define TIM_DMABASE_EGR (0x00000005) -#define TIM_DMABASE_CCMR1 (0x00000006) -#define TIM_DMABASE_CCMR2 (0x00000007) -#define TIM_DMABASE_CCER (0x00000008) -#define TIM_DMABASE_CNT (0x00000009) -#define TIM_DMABASE_PSC (0x0000000A) -#define TIM_DMABASE_ARR (0x0000000B) -#define TIM_DMABASE_CCR1 (0x0000000D) -#define TIM_DMABASE_CCR2 (0x0000000E) -#define TIM_DMABASE_CCR3 (0x0000000F) -#define TIM_DMABASE_CCR4 (0x00000010) -#define TIM_DMABASE_DCR (0x00000012) -#define TIM_DMABASE_OR (0x00000013) +#define TIM_DMABASE_CR1 (0x00000000U) +#define TIM_DMABASE_CR2 (0x00000001U) +#define TIM_DMABASE_SMCR (0x00000002U) +#define TIM_DMABASE_DIER (0x00000003U) +#define TIM_DMABASE_SR (0x00000004U) +#define TIM_DMABASE_EGR (0x00000005U) +#define TIM_DMABASE_CCMR1 (0x00000006U) +#define TIM_DMABASE_CCMR2 (0x00000007U) +#define TIM_DMABASE_CCER (0x00000008U) +#define TIM_DMABASE_CNT (0x00000009U) +#define TIM_DMABASE_PSC (0x0000000AU) +#define TIM_DMABASE_ARR (0x0000000BU) +#define TIM_DMABASE_CCR1 (0x0000000DU) +#define TIM_DMABASE_CCR2 (0x0000000EU) +#define TIM_DMABASE_CCR3 (0x0000000FU) +#define TIM_DMABASE_CCR4 (0x00000010U) +#define TIM_DMABASE_DCR (0x00000012U) +#define TIM_DMABASE_OR (0x00000013U) /** * @} */ @@ -919,24 +919,24 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /** @defgroup TIM_DMA_Burst_Length DMA burst length * @{ */ -#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) -#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) -#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) -#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) -#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) -#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) -#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) -#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) -#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) -#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) -#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) -#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) -#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) -#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) -#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) -#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) -#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) -#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) +#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U) +#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U) +#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U) +#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U) +#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U) +#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U) +#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U) +#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U) +#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U) +#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U) +#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U) +#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U) +#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U) +#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U) +#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U) +#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U) +#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U) +#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U) /** * @} */ @@ -961,17 +961,17 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /* Check IC filter */ -#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) /** @defgroup DMA_Handle_index DMA handle index * @{ */ -#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ -#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ -#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ -#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ -#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ -#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x5) /*!< Index of the DMA handle used for Trigger DMA requests */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Trigger DMA requests */ /** * @} */ @@ -979,8 +979,8 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /** @defgroup Channel_CC_State Channel state * @{ */ -#define TIM_CCx_ENABLE ((uint32_t)0x0001) -#define TIM_CCx_DISABLE ((uint32_t)0x0000) +#define TIM_CCx_ENABLE ((uint32_t)0x0001U) +#define TIM_CCx_DISABLE ((uint32_t)0x0000U) /** * @} */ @@ -1018,7 +1018,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ #define __HAL_TIM_DISABLE(__HANDLE__) \ do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \ { \ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ } \ @@ -1039,7 +1039,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) @@ -1051,9 +1051,9 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\ - ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P))) + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P))) #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ @@ -1075,7 +1075,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state * @retval None */ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ -(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__)) +(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__)) /** * @brief Gets the TIM Capture Compare Register value on runtime @@ -1089,7 +1089,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state * @retval None */ #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ - (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2))) + (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U))) /** * @brief Sets the TIM Counter Register value on runtime. @@ -1188,7 +1188,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ - (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) /** diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim_ex.c index 7f34b250cf..bac0a17d13 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief TIM HAL module driver. * @brief This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim_ex.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim_ex.h index 78d3ad4527..ca1579be49 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention @@ -80,7 +80,7 @@ typedef struct { /** @defgroup TIMEx_Trigger_Selection Trigger selection * @{ */ -#define TIM_TRGO_RESET ((uint32_t)0x0000) +#define TIM_TRGO_RESET ((uint32_t)0x0000U) #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) @@ -108,7 +108,7 @@ typedef struct { #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) -#define TIM2_ETR_GPIO ((uint32_t)0x0) +#define TIM2_ETR_GPIO ((uint32_t)0x0U) #define TIM2_ETR_HSI48 TIM2_OR_ETR_RMP_2 #define TIM2_ETR_HSI16 (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0) #define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0) @@ -117,7 +117,7 @@ typedef struct { #elif defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx) -#define TIM2_ETR_GPIO ((uint32_t)0x0) +#define TIM2_ETR_GPIO ((uint32_t)0x0U) #define TIM2_ETR_HSI16 (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0) #define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0) #define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1) @@ -125,7 +125,7 @@ typedef struct { #else -#define TIM2_ETR_GPIO ((uint32_t)0x0) +#define TIM2_ETR_GPIO ((uint32_t)0x0U) #define TIM2_ETR_HSI48 TIM2_OR_ETR_RMP_2 #define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0) #define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1) @@ -135,15 +135,15 @@ typedef struct { -#define TIM2_TI4_GPIO ((uint32_t)0x0) +#define TIM2_TI4_GPIO ((uint32_t)0x0U) #define TIM2_TI4_COMP2 TIM2_OR_TI4_RMP_0 #define TIM2_TI4_COMP1 TIM2_OR_TI4_RMP_1 -#define TIM21_ETR_GPIO ((uint32_t)0x0) +#define TIM21_ETR_GPIO ((uint32_t)0x0U) #define TIM21_ETR_COMP2_OUT TIM21_OR_ETR_RMP_0 #define TIM21_ETR_COMP1_OUT TIM21_OR_ETR_RMP_1 #define TIM21_ETR_LSE TIM21_OR_ETR_RMP -#define TIM21_TI1_GPIO ((uint32_t)0x0) +#define TIM21_TI1_GPIO ((uint32_t)0x0U) #define TIM21_TI1_MCO TIM21_OR_TI1_RMP #define TIM21_TI1_RTC_WKUT_IT TIM21_OR_TI1_RMP_0 #define TIM21_TI1_HSE_RTC TIM21_OR_TI1_RMP_1 @@ -151,15 +151,15 @@ typedef struct { #define TIM21_TI1_LSE TIM21_OR_TI1_RMP_2 #define TIM21_TI1_LSI (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_0) #define TIM21_TI1_COMP1_OUT (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_1) -#define TIM21_TI2_GPIO ((uint32_t)0x0) +#define TIM21_TI2_GPIO ((uint32_t)0x0U) #define TIM21_TI2_COMP2_OUT TIM21_OR_TI2_RMP #if !defined(STM32L011xx) && !defined(STM32L021xx) -#define TIM22_ETR_LSE ((uint32_t)0x0) +#define TIM22_ETR_LSE ((uint32_t)0x0U) #define TIM22_ETR_COMP2_OUT TIM22_OR_ETR_RMP_0 #define TIM22_ETR_COMP1_OUT TIM22_OR_ETR_RMP_1 #define TIM22_ETR_GPIO TIM22_OR_ETR_RMP -#define TIM22_TI1_GPIO1 ((uint32_t)0x0) +#define TIM22_TI1_GPIO1 ((uint32_t)0x0U) #define TIM22_TI1_COMP2_OUT TIM22_OR_TI1_RMP_0 #define TIM22_TI1_COMP1_OUT TIM22_OR_TI1_RMP_1 #define TIM22_TI1_GPIO2 TIM22_OR_TI1_RMP @@ -168,13 +168,13 @@ typedef struct { #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) -#define TIM3_TI4_GPIO_DEF ((uint32_t)0x0) +#define TIM3_TI4_GPIO_DEF ((uint32_t)0x0U) #define TIM3_TI4_GPIOC9_AF2 TIM3_OR_TI4_RMP -#define TIM3_TI2_GPIO_DEF ((uint32_t)0x0) +#define TIM3_TI2_GPIO_DEF ((uint32_t)0x0U) #define TIM3_TI2_GPIOB5_AF4 TIM3_OR_TI2_RMP -#define TIM3_TI1_USB_SOF ((uint32_t)0x0) +#define TIM3_TI1_USB_SOF ((uint32_t)0x0U) #define TIM3_TI1_GPIO TIM3_OR_TI1_RMP -#define TIM3_ETR_GPIO ((uint32_t)0x0) +#define TIM3_ETR_GPIO ((uint32_t)0x0U) #define TIM3_ETR_HSI TIM3_OR_ETR_RMP_1 #endif /*defined (STM32L07Xxx) or defined (STM32L08Xxx) */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.c index 52a0b15f0b..daf265ddd3 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_tsc.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Touch Sensing Controller (TSC) peripheral: * + Initialization and DeInitialization @@ -203,7 +203,7 @@ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc) /* Set all functions */ htsc->Instance->CR |= (htsc->Init.CTPulseHighLength | htsc->Init.CTPulseLowLength | - (uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17) | + (uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17U) | htsc->Init.SpreadSpectrumPrescaler | htsc->Init.PulseGeneratorPrescaler | htsc->Init.MaxCountValue | @@ -786,14 +786,14 @@ __weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc) */ static uint32_t TSC_extract_groups(uint32_t iomask) { - uint32_t groups = 0; + uint32_t groups = 0U; uint32_t idx; - for (idx = 0; idx < TSC_NB_OF_GROUPS; idx++) + for (idx = 0U; idx < TSC_NB_OF_GROUPS; idx++) { - if ((iomask & ((uint32_t)0x0F << (idx * 4))) != RESET) + if ((iomask & ((uint32_t)0x0FU << (idx * 4U))) != RESET) { - groups |= ((uint32_t)1 << idx); + groups |= ((uint32_t)1U << idx); } } diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.h index 5d5b7932a3..5c7808b41f 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_tsc.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief This file contains all the functions prototypes for the TSC firmware * library. ****************************************************************************** @@ -66,10 +66,10 @@ */ typedef enum { - HAL_TSC_STATE_RESET = 0x00, /*!< TSC registers have their reset value */ - HAL_TSC_STATE_READY = 0x01, /*!< TSC registers are initialized or acquisition is completed with success */ - HAL_TSC_STATE_BUSY = 0x02, /*!< TSC initialization or acquisition is on-going */ - HAL_TSC_STATE_ERROR = 0x03 /*!< Acquisition is completed with max count error */ + HAL_TSC_STATE_RESET = 0x00U, /*!< TSC registers have their reset value */ + HAL_TSC_STATE_READY = 0x01U, /*!< TSC registers are initialized or acquisition is completed with success */ + HAL_TSC_STATE_BUSY = 0x02U, /*!< TSC initialization or acquisition is on-going */ + HAL_TSC_STATE_ERROR = 0x03U /*!< Acquisition is completed with max count error */ } HAL_TSC_StateTypeDef; /** @@ -77,8 +77,8 @@ typedef enum */ typedef enum { - TSC_GROUP_ONGOING = 0x00, /*!< Acquisition on group is on-going or not started */ - TSC_GROUP_COMPLETED = 0x01 /*!< Acquisition on group is completed with success (no max count error) */ + TSC_GROUP_ONGOING = 0x00U, /*!< Acquisition on group is on-going or not started */ + TSC_GROUP_COMPLETED = 0x01U /*!< Acquisition on group is completed with success (no max count error) */ } TSC_GroupStatusTypeDef; /** @@ -135,72 +135,72 @@ typedef struct */ -#define TSC_CTPH_1CYCLE ((uint32_t)((uint32_t) 0 << 28)) -#define TSC_CTPH_2CYCLES ((uint32_t)((uint32_t) 1 << 28)) -#define TSC_CTPH_3CYCLES ((uint32_t)((uint32_t) 2 << 28)) -#define TSC_CTPH_4CYCLES ((uint32_t)((uint32_t) 3 << 28)) -#define TSC_CTPH_5CYCLES ((uint32_t)((uint32_t) 4 << 28)) -#define TSC_CTPH_6CYCLES ((uint32_t)((uint32_t) 5 << 28)) -#define TSC_CTPH_7CYCLES ((uint32_t)((uint32_t) 6 << 28)) -#define TSC_CTPH_8CYCLES ((uint32_t)((uint32_t) 7 << 28)) -#define TSC_CTPH_9CYCLES ((uint32_t)((uint32_t) 8 << 28)) -#define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9 << 28)) -#define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10 << 28)) -#define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11 << 28)) -#define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12 << 28)) -#define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28)) -#define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28)) -#define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28)) +#define TSC_CTPH_1CYCLE ((uint32_t)((uint32_t) 0U << 28U)) +#define TSC_CTPH_2CYCLES ((uint32_t)((uint32_t) 1U << 28U)) +#define TSC_CTPH_3CYCLES ((uint32_t)((uint32_t) 2U << 28U)) +#define TSC_CTPH_4CYCLES ((uint32_t)((uint32_t) 3U << 28U)) +#define TSC_CTPH_5CYCLES ((uint32_t)((uint32_t) 4U << 28U)) +#define TSC_CTPH_6CYCLES ((uint32_t)((uint32_t) 5U << 28U)) +#define TSC_CTPH_7CYCLES ((uint32_t)((uint32_t) 6U << 28U)) +#define TSC_CTPH_8CYCLES ((uint32_t)((uint32_t) 7U << 28U)) +#define TSC_CTPH_9CYCLES ((uint32_t)((uint32_t) 8U << 28U)) +#define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9U << 28U)) +#define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10U << 28U)) +#define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11U << 28U)) +#define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12U << 28U)) +#define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13U << 28U)) +#define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14U << 28U)) +#define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15U << 28U)) -#define TSC_CTPL_1CYCLE ((uint32_t)((uint32_t) 0 << 24)) -#define TSC_CTPL_2CYCLES ((uint32_t)((uint32_t) 1 << 24)) -#define TSC_CTPL_3CYCLES ((uint32_t)((uint32_t) 2 << 24)) -#define TSC_CTPL_4CYCLES ((uint32_t)((uint32_t) 3 << 24)) -#define TSC_CTPL_5CYCLES ((uint32_t)((uint32_t) 4 << 24)) -#define TSC_CTPL_6CYCLES ((uint32_t)((uint32_t) 5 << 24)) -#define TSC_CTPL_7CYCLES ((uint32_t)((uint32_t) 6 << 24)) -#define TSC_CTPL_8CYCLES ((uint32_t)((uint32_t) 7 << 24)) -#define TSC_CTPL_9CYCLES ((uint32_t)((uint32_t) 8 << 24)) -#define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9 << 24)) -#define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10 << 24)) -#define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11 << 24)) -#define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12 << 24)) -#define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24)) -#define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24)) -#define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24)) +#define TSC_CTPL_1CYCLE ((uint32_t)((uint32_t) 0U << 24U)) +#define TSC_CTPL_2CYCLES ((uint32_t)((uint32_t) 1U << 24U)) +#define TSC_CTPL_3CYCLES ((uint32_t)((uint32_t) 2U << 24U)) +#define TSC_CTPL_4CYCLES ((uint32_t)((uint32_t) 3U << 24U)) +#define TSC_CTPL_5CYCLES ((uint32_t)((uint32_t) 4U << 24U)) +#define TSC_CTPL_6CYCLES ((uint32_t)((uint32_t) 5U << 24U)) +#define TSC_CTPL_7CYCLES ((uint32_t)((uint32_t) 6U << 24U)) +#define TSC_CTPL_8CYCLES ((uint32_t)((uint32_t) 7U << 24U)) +#define TSC_CTPL_9CYCLES ((uint32_t)((uint32_t) 8U << 24U)) +#define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9U << 24U)) +#define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10U << 24U)) +#define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11U << 24U)) +#define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12U << 24U)) +#define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13U << 24U)) +#define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14U << 24U)) +#define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15U << 24U)) -#define TSC_SS_PRESC_DIV1 ((uint32_t)0) +#define TSC_SS_PRESC_DIV1 ((uint32_t)0U) #define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC) -#define TSC_PG_PRESC_DIV1 ((uint32_t)(0 << 12)) -#define TSC_PG_PRESC_DIV2 ((uint32_t)(1 << 12)) -#define TSC_PG_PRESC_DIV4 ((uint32_t)(2 << 12)) -#define TSC_PG_PRESC_DIV8 ((uint32_t)(3 << 12)) -#define TSC_PG_PRESC_DIV16 ((uint32_t)(4 << 12)) -#define TSC_PG_PRESC_DIV32 ((uint32_t)(5 << 12)) -#define TSC_PG_PRESC_DIV64 ((uint32_t)(6 << 12)) -#define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12)) -#define TSC_MCV_255 ((uint32_t)(0 << 5)) -#define TSC_MCV_511 ((uint32_t)(1 << 5)) -#define TSC_MCV_1023 ((uint32_t)(2 << 5)) -#define TSC_MCV_2047 ((uint32_t)(3 << 5)) -#define TSC_MCV_4095 ((uint32_t)(4 << 5)) -#define TSC_MCV_8191 ((uint32_t)(5 << 5)) -#define TSC_MCV_16383 ((uint32_t)(6 << 5)) +#define TSC_PG_PRESC_DIV1 ((uint32_t)(0U << 12U)) +#define TSC_PG_PRESC_DIV2 ((uint32_t)(1U << 12U)) +#define TSC_PG_PRESC_DIV4 ((uint32_t)(2U << 12U)) +#define TSC_PG_PRESC_DIV8 ((uint32_t)(3U << 12U)) +#define TSC_PG_PRESC_DIV16 ((uint32_t)(4U << 12U)) +#define TSC_PG_PRESC_DIV32 ((uint32_t)(5U << 12U)) +#define TSC_PG_PRESC_DIV64 ((uint32_t)(6U << 12U)) +#define TSC_PG_PRESC_DIV128 ((uint32_t)(7U << 12U)) +#define TSC_MCV_255 ((uint32_t)(0U << 5U)) +#define TSC_MCV_511 ((uint32_t)(1U << 5U)) +#define TSC_MCV_1023 ((uint32_t)(2U << 5U)) +#define TSC_MCV_2047 ((uint32_t)(3U << 5U)) +#define TSC_MCV_4095 ((uint32_t)(4U << 5U)) +#define TSC_MCV_8191 ((uint32_t)(5U << 5U)) +#define TSC_MCV_16383 ((uint32_t)(6U << 5U)) -#define TSC_IODEF_OUT_PP_LOW ((uint32_t)0) +#define TSC_IODEF_OUT_PP_LOW ((uint32_t)0U) #define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF) -#define TSC_SYNC_POLARITY_FALLING ((uint32_t)0) +#define TSC_SYNC_POLARITY_FALLING ((uint32_t)0U) #define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL) -#define TSC_ACQ_MODE_NORMAL ((uint32_t)0) +#define TSC_ACQ_MODE_NORMAL ((uint32_t)0U) #define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM) -#define TSC_IOMODE_UNUSED ((uint32_t)0) -#define TSC_IOMODE_CHANNEL ((uint32_t)1) -#define TSC_IOMODE_SHIELD ((uint32_t)2) -#define TSC_IOMODE_SAMPLING ((uint32_t)3) +#define TSC_IOMODE_UNUSED ((uint32_t)0U) +#define TSC_IOMODE_CHANNEL ((uint32_t)1U) +#define TSC_IOMODE_SHIELD ((uint32_t)2U) +#define TSC_IOMODE_SAMPLING ((uint32_t)3U) /** @defgroup TSC_interrupts_definition TSC Interrupts Definition * @{ @@ -222,74 +222,74 @@ typedef struct #define TSC_NB_OF_GROUPS (8) -#define TSC_GROUP1 ((uint32_t)0x00000001) -#define TSC_GROUP2 ((uint32_t)0x00000002) -#define TSC_GROUP3 ((uint32_t)0x00000004) -#define TSC_GROUP4 ((uint32_t)0x00000008) -#define TSC_GROUP5 ((uint32_t)0x00000010) -#define TSC_GROUP6 ((uint32_t)0x00000020) -#define TSC_GROUP7 ((uint32_t)0x00000040) -#define TSC_GROUP8 ((uint32_t)0x00000080) -#define TSC_ALL_GROUPS ((uint32_t)0x000000FF) +#define TSC_GROUP1 ((uint32_t)0x00000001U) +#define TSC_GROUP2 ((uint32_t)0x00000002U) +#define TSC_GROUP3 ((uint32_t)0x00000004U) +#define TSC_GROUP4 ((uint32_t)0x00000008U) +#define TSC_GROUP5 ((uint32_t)0x00000010U) +#define TSC_GROUP6 ((uint32_t)0x00000020U) +#define TSC_GROUP7 ((uint32_t)0x00000040U) +#define TSC_GROUP8 ((uint32_t)0x00000080U) +#define TSC_ALL_GROUPS ((uint32_t)0x000000FFU) -#define TSC_GROUP1_IDX ((uint32_t)0) -#define TSC_GROUP2_IDX ((uint32_t)1) -#define TSC_GROUP3_IDX ((uint32_t)2) -#define TSC_GROUP4_IDX ((uint32_t)3) -#define TSC_GROUP5_IDX ((uint32_t)4) -#define TSC_GROUP6_IDX ((uint32_t)5) -#define TSC_GROUP7_IDX ((uint32_t)6) -#define TSC_GROUP8_IDX ((uint32_t)7) +#define TSC_GROUP1_IDX ((uint32_t)0U) +#define TSC_GROUP2_IDX ((uint32_t)1U) +#define TSC_GROUP3_IDX ((uint32_t)2U) +#define TSC_GROUP4_IDX ((uint32_t)3U) +#define TSC_GROUP5_IDX ((uint32_t)4U) +#define TSC_GROUP6_IDX ((uint32_t)5U) +#define TSC_GROUP7_IDX ((uint32_t)6U) +#define TSC_GROUP8_IDX ((uint32_t)7U) -#define TSC_GROUP1_IO1 ((uint32_t)0x00000001) -#define TSC_GROUP1_IO2 ((uint32_t)0x00000002) -#define TSC_GROUP1_IO3 ((uint32_t)0x00000004) -#define TSC_GROUP1_IO4 ((uint32_t)0x00000008) -#define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000F) +#define TSC_GROUP1_IO1 ((uint32_t)0x00000001U) +#define TSC_GROUP1_IO2 ((uint32_t)0x00000002U) +#define TSC_GROUP1_IO3 ((uint32_t)0x00000004U) +#define TSC_GROUP1_IO4 ((uint32_t)0x00000008U) +#define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000FU) -#define TSC_GROUP2_IO1 ((uint32_t)0x00000010) -#define TSC_GROUP2_IO2 ((uint32_t)0x00000020) -#define TSC_GROUP2_IO3 ((uint32_t)0x00000040) -#define TSC_GROUP2_IO4 ((uint32_t)0x00000080) -#define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0) +#define TSC_GROUP2_IO1 ((uint32_t)0x00000010U) +#define TSC_GROUP2_IO2 ((uint32_t)0x00000020U) +#define TSC_GROUP2_IO3 ((uint32_t)0x00000040U) +#define TSC_GROUP2_IO4 ((uint32_t)0x00000080U) +#define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0U) -#define TSC_GROUP3_IO1 ((uint32_t)0x00000100) -#define TSC_GROUP3_IO2 ((uint32_t)0x00000200) -#define TSC_GROUP3_IO3 ((uint32_t)0x00000400) -#define TSC_GROUP3_IO4 ((uint32_t)0x00000800) -#define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00) +#define TSC_GROUP3_IO1 ((uint32_t)0x00000100U) +#define TSC_GROUP3_IO2 ((uint32_t)0x00000200U) +#define TSC_GROUP3_IO3 ((uint32_t)0x00000400U) +#define TSC_GROUP3_IO4 ((uint32_t)0x00000800U) +#define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00U) -#define TSC_GROUP4_IO1 ((uint32_t)0x00001000) -#define TSC_GROUP4_IO2 ((uint32_t)0x00002000) -#define TSC_GROUP4_IO3 ((uint32_t)0x00004000) -#define TSC_GROUP4_IO4 ((uint32_t)0x00008000) -#define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000) +#define TSC_GROUP4_IO1 ((uint32_t)0x00001000U) +#define TSC_GROUP4_IO2 ((uint32_t)0x00002000U) +#define TSC_GROUP4_IO3 ((uint32_t)0x00004000U) +#define TSC_GROUP4_IO4 ((uint32_t)0x00008000U) +#define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000U) -#define TSC_GROUP5_IO1 ((uint32_t)0x00010000) -#define TSC_GROUP5_IO2 ((uint32_t)0x00020000) -#define TSC_GROUP5_IO3 ((uint32_t)0x00040000) -#define TSC_GROUP5_IO4 ((uint32_t)0x00080000) -#define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000) +#define TSC_GROUP5_IO1 ((uint32_t)0x00010000U) +#define TSC_GROUP5_IO2 ((uint32_t)0x00020000U) +#define TSC_GROUP5_IO3 ((uint32_t)0x00040000U) +#define TSC_GROUP5_IO4 ((uint32_t)0x00080000U) +#define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000U) -#define TSC_GROUP6_IO1 ((uint32_t)0x00100000) -#define TSC_GROUP6_IO2 ((uint32_t)0x00200000) -#define TSC_GROUP6_IO3 ((uint32_t)0x00400000) -#define TSC_GROUP6_IO4 ((uint32_t)0x00800000) -#define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000) +#define TSC_GROUP6_IO1 ((uint32_t)0x00100000U) +#define TSC_GROUP6_IO2 ((uint32_t)0x00200000U) +#define TSC_GROUP6_IO3 ((uint32_t)0x00400000U) +#define TSC_GROUP6_IO4 ((uint32_t)0x00800000U) +#define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000U) -#define TSC_GROUP7_IO1 ((uint32_t)0x01000000) -#define TSC_GROUP7_IO2 ((uint32_t)0x02000000) -#define TSC_GROUP7_IO3 ((uint32_t)0x04000000) -#define TSC_GROUP7_IO4 ((uint32_t)0x08000000) -#define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000) +#define TSC_GROUP7_IO1 ((uint32_t)0x01000000U) +#define TSC_GROUP7_IO2 ((uint32_t)0x02000000U) +#define TSC_GROUP7_IO3 ((uint32_t)0x04000000U) +#define TSC_GROUP7_IO4 ((uint32_t)0x08000000U) +#define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000U) -#define TSC_GROUP8_IO1 ((uint32_t)0x10000000) -#define TSC_GROUP8_IO2 ((uint32_t)0x20000000) -#define TSC_GROUP8_IO3 ((uint32_t)0x40000000) -#define TSC_GROUP8_IO4 ((uint32_t)0x80000000) -#define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000) +#define TSC_GROUP8_IO1 ((uint32_t)0x10000000U) +#define TSC_GROUP8_IO2 ((uint32_t)0x20000000U) +#define TSC_GROUP8_IO3 ((uint32_t)0x40000000U) +#define TSC_GROUP8_IO4 ((uint32_t)0x80000000U) +#define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000U) -#define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFF) +#define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFFU) /** * @} @@ -488,7 +488,7 @@ typedef struct * @retval SET or RESET */ #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ -((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) +((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) == (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) /** * @} @@ -536,7 +536,7 @@ typedef struct #define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE)) -#define IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128))) +#define IS_TSC_SSD(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < 128U))) #define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2)) #define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \ ((VAL) == TSC_PG_PRESC_DIV2) || \ @@ -563,7 +563,7 @@ typedef struct ((VAL) == TSC_IOMODE_SAMPLING)) #define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE)) -#define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS))) +#define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < TSC_NB_OF_GROUPS))) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart.c index 65107470f2..98470850f3 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_uart.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief UART HAL module driver. * * This file provides firmware functions to manage the following @@ -173,7 +173,7 @@ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#define UART_TIMEOUT_VALUE ((uint32_t) 22000) +#define UART_TIMEOUT_VALUE ((uint32_t) 22000U) #define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /* Private macro -------------------------------------------------------------*/ @@ -214,23 +214,6 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); (++) Stop Bit (++) Parity: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible UART frame formats are as listed in the following table: - +-----------------------------------------------------------------------+ - | M1 bit | M0 bit | PCE bit | USART frame | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 0 | | SB | 8 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 0 | | SB | 9 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 0 | | SB | 7 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | - +-----------------------------------------------------------------------+ (++) Hardware flow control (++) Receiver/transmitter modes (++) Over Sampling Method @@ -250,6 +233,28 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); are available in reference manual). @endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | USART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + * @{ */ @@ -278,7 +283,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) assert_param(IS_UART_INSTANCE(huart->Instance)); } - if(huart->State == HAL_UART_STATE_RESET) + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; @@ -287,7 +292,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) HAL_UART_MspInit(huart); } - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -309,7 +314,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* TEACK and/or REACK to check before moving huart->State to Ready */ + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -331,12 +336,14 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); - if(huart->State == HAL_UART_STATE_RESET) + if(huart->gState == HAL_UART_STATE_RESET) { /* Init the low level hardware : GPIO, CLOCK, CORTEX */ HAL_UART_MspInit(huart); } + huart->gState = HAL_UART_STATE_BUSY; + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -360,7 +367,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* TEACK and/or REACK to check before moving huart->State to Ready */ + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -399,12 +406,14 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe return HAL_ERROR; } - if(huart->State == HAL_UART_STATE_RESET) + if(huart->gState == HAL_UART_STATE_RESET) { /* Init the low level hardware : GPIO, CLOCK, CORTEX */ HAL_UART_MspInit(huart); } + huart->gState = HAL_UART_STATE_BUSY; + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -431,7 +440,7 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* TEACK and/or REACK to check before moving huart->State to Ready */ + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -464,13 +473,13 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /* Check the wake up method parameter */ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); - if(huart->State == HAL_UART_STATE_RESET) + if(huart->gState == HAL_UART_STATE_RESET) { /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -501,7 +510,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* TEACK and/or REACK to check before moving huart->State to Ready */ + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -521,20 +530,21 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - huart->Instance->CR1 = 0x0; - huart->Instance->CR2 = 0x0; - huart->Instance->CR3 = 0x0; + huart->Instance->CR1 = 0x0U; + huart->Instance->CR2 = 0x0U; + huart->Instance->CR3 = 0x0U; /* DeInit the low level hardware */ HAL_UART_MspDeInit(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->State = HAL_UART_STATE_RESET; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(huart); @@ -643,9 +653,11 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u { uint16_t* tmp; - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) + + /* Check that a Tx process is not already ongoing */ + if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -654,19 +666,12 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u __HAL_LOCK(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a non-blocking receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_TX; - } + huart->gState = HAL_UART_STATE_BUSY_TX; + huart->TxXferSize = Size; huart->TxXferCount = Size; - while(huart->TxXferCount > 0) + while(huart->TxXferCount > 0U) { huart->TxXferCount--; if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK) @@ -676,27 +681,20 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { tmp = (uint16_t*) pData; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - pData += 2; + huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + pData += 2U; } else { - huart->Instance->TDR = (*pData++ & (uint8_t)0xFF); + huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU); } } if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - /* Check if a non-blocking receive Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -722,9 +720,10 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui uint16_t* tmp; uint16_t uhMask; - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -733,15 +732,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui __HAL_LOCK(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a non-blocking transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_RX; - } + huart->RxState = HAL_UART_STATE_BUSY_RX; huart->RxXferSize = Size; huart->RxXferCount = Size; @@ -751,7 +742,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui uhMask = huart->Mask; /* as long as data have to be received */ - while(huart->RxXferCount > 0) + while(huart->RxXferCount > 0U) { huart->RxXferCount--; if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK) @@ -762,7 +753,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui { tmp = (uint16_t*) pData ; *tmp = (uint16_t)(huart->Instance->RDR & uhMask); - pData +=2; + pData +=2U; } else { @@ -770,15 +761,9 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui } } - /* Check if a non-blocking transmit Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -799,9 +784,10 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -814,15 +800,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData huart->TxXferCount = Size; huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_TX; - } + huart->gState = HAL_UART_STATE_BUSY_TX; /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); @@ -850,9 +828,10 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -868,15 +847,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, UART_MASK_COMPUTATION(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_RX; - } + huart->RxState = HAL_UART_STATE_BUSY_RX; /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); @@ -909,9 +880,10 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat { uint32_t *tmp; - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -924,15 +896,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat huart->TxXferCount = Size; huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_TX; - } + huart->gState = HAL_UART_STATE_BUSY_TX; /* Set the UART DMA transfert complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; @@ -977,9 +941,10 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData { uint32_t *tmp; - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -991,15 +956,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData huart->RxXferSize = Size; huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_RX; - } + huart->RxState = HAL_UART_STATE_BUSY_RX; /* Set the UART DMA transfert complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; @@ -1039,23 +996,16 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - if(huart->State == HAL_UART_STATE_BUSY_TX) + if(huart->gState == HAL_UART_STATE_BUSY_TX) { /* Disable the UART DMA Tx request */ huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); } - else if(huart->State == HAL_UART_STATE_BUSY_RX) + if(huart->RxState == HAL_UART_STATE_BUSY_RX) { /* Disable the UART DMA Rx request */ huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); } - else if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - /* Disable the UART DMA Tx request */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); - /* Disable the UART DMA Rx request */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); - } /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1072,12 +1022,12 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - if(huart->State == HAL_UART_STATE_BUSY_TX) + if(huart->gState == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ huart->Instance->CR3 |= USART_CR3_DMAT; } - else if(huart->State == HAL_UART_STATE_BUSY_RX) + else if(huart->RxState == HAL_UART_STATE_BUSY_RX) { /* Clear the Overrun flag before resumming the Rx transfer*/ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); @@ -1085,17 +1035,6 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) /* Enable the UART DMA Rx request */ huart->Instance->CR3 |= USART_CR3_DMAR; } - else if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - /* Clear the Overrun flag before resumming the Rx transfer*/ - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); - - /* Enable the UART DMA Rx request before the DMA Tx request */ - huart->Instance->CR3 |= USART_CR3_DMAR; - - /* Enable the UART DMA Tx request */ - huart->Instance->CR3 |= USART_CR3_DMAT; - } /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1131,7 +1070,8 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) HAL_DMA_Abort(huart->hdmarx); } - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; return HAL_OK; } @@ -1151,7 +1091,8 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->ErrorCode |= HAL_UART_ERROR_PE; /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; } /* UART frame error interrupt occured --------------------------------------*/ @@ -1161,7 +1102,8 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->ErrorCode |= HAL_UART_ERROR_FE; /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; } /* UART noise error interrupt occured --------------------------------------*/ @@ -1171,22 +1113,28 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->ErrorCode |= HAL_UART_ERROR_NE; /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; } - /* UART Over-Run interrupt occured -----------------------------------------*/ + /* UART Over-Run interrupt occurred -----------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) { __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); huart->ErrorCode |= HAL_UART_ERROR_ORE; /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; } - /* Call UART Error Call back function if need be --------------------------*/ + /* Call UART Error Call back function if need be --------------------------*/ if(huart->ErrorCode != HAL_UART_ERROR_NONE) { + /* Set the UART state ready to be able to start again the process */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + HAL_UART_ErrorCallback(huart); } @@ -1194,8 +1142,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) if((__HAL_UART_GET_IT(huart, UART_IT_WUF) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_WUF) != RESET)) { __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF); + /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + HAL_UARTEx_WakeupCallback(huart); } @@ -1215,7 +1166,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET)) { UART_EndTransmit_IT(huart); - } + } } /** @@ -1329,12 +1280,12 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Enable USART mute mode by setting the MME bit in the CR1 register */ huart->Instance->CR1 |= USART_CR1_MME; - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; return (UART_CheckIdleState(huart)); } @@ -1350,12 +1301,12 @@ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable USART mute mode by clearing the MME bit in the CR1 register */ huart->Instance->CR1 &= ~(USART_CR1_MME); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; return (UART_CheckIdleState(huart)); } @@ -1381,14 +1332,14 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Clear TE and RE bits */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_TE); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1404,14 +1355,14 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Clear TE and RE bits */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_RE); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1432,12 +1383,12 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Send break characters */ huart->Instance->RQR |= USART_RQR_SBKRQ; - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1452,7 +1403,11 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) */ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) { - return huart->State; + uint32_t temp1= 0x00U, temp2 = 0x00U; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); } /** @@ -1493,7 +1448,7 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* DMA Normal mode */ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { - huart->TxXferCount = 0; + huart->TxXferCount = 0U; /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the UART CR3 register */ @@ -1532,23 +1487,17 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode*/ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { - huart->RxXferCount = 0; + huart->RxXferCount = 0U; /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); - /* Check if a transmit Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + } HAL_UART_RxCpltCallback(huart); } @@ -1573,9 +1522,10 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) static void UART_DMAError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - huart->RxXferCount = 0; - huart->TxXferCount = 0; - huart->State= HAL_UART_STATE_READY; + huart->RxXferCount = 0U; + huart->TxXferCount = 0U; + huart->gState= HAL_UART_STATE_READY; + huart->RxState= HAL_UART_STATE_READY; huart->ErrorCode |= HAL_UART_ERROR_DMA; HAL_UART_ErrorCallback(huart); } @@ -1591,9 +1541,9 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { uint16_t* tmp; - if ((huart->State == HAL_UART_STATE_BUSY_TX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX)) + if (huart->gState == HAL_UART_STATE_BUSY_TX) { - if(huart->TxXferCount == 0) + if(huart->TxXferCount == 0U) { /* Disable the UART TXE Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); @@ -1609,12 +1559,12 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { tmp = (uint16_t*) huart->pTxBuffPtr; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - huart->pTxBuffPtr += 2; + huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + huart->pTxBuffPtr += 2U; } else { - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU); } huart->TxXferCount--; @@ -1638,16 +1588,8 @@ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); - - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } + + huart->gState = HAL_UART_STATE_READY; HAL_UART_TxCpltCallback(huart); @@ -1667,48 +1609,47 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) uint16_t* tmp; uint16_t uhMask = huart->Mask; - if((huart->State == HAL_UART_STATE_BUSY_RX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX)) + /* Check that a Rx process is ongoing */ + if(huart->RxState == HAL_UART_STATE_BUSY_RX) { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { tmp = (uint16_t*) huart->pRxBuffPtr ; *tmp = (uint16_t)(huart->Instance->RDR & uhMask); - huart->pRxBuffPtr +=2; + huart->pRxBuffPtr +=2U; } else { *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); } - if(--huart->RxXferCount == 0) + if(--huart->RxXferCount == 0U) { while(HAL_IS_BIT_SET(huart->Instance->ISR, UART_FLAG_RXNE)) { } __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - /* Check if a transmit Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - /* Disable the UART Parity Error Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + /* Disable the UART Parity Error Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; - huart->State = HAL_UART_STATE_READY; - } HAL_UART_RxCpltCallback(huart); + return HAL_OK; } return HAL_OK; } else { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + return HAL_BUSY; } } @@ -1720,10 +1661,10 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) */ void UART_SetConfig(UART_HandleTypeDef *huart) { - uint32_t tmpreg = 0x00000000; - uint32_t clocksource = 0x00000000; - uint16_t brrtemp = 0x0000; - uint16_t usartdiv = 0x0000; + uint32_t tmpreg = 0x00000000U; + uint32_t clocksource = 0x00000000U; + uint16_t brrtemp = 0x0000U; + uint16_t usartdiv = 0x0000U; /* Check the parameters */ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); @@ -1783,9 +1724,9 @@ void UART_SetConfig(UART_HandleTypeDef *huart) huart->Instance->BRR = (uint32_t)(__DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_HSI: - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0) + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) { - huart->Instance->BRR = (uint32_t)(__DIV_LPUART((HSI_VALUE >> 2), huart->Init.BaudRate)); + huart->Instance->BRR = (uint32_t)(__DIV_LPUART((HSI_VALUE >> 2U), huart->Init.BaudRate)); } else { @@ -1814,9 +1755,9 @@ void UART_SetConfig(UART_HandleTypeDef *huart) usartdiv = (uint32_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_HSI: - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0) + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) { - usartdiv = (uint32_t)(UART_DIV_SAMPLING8((HSI_VALUE >> 2), huart->Init.BaudRate)); + usartdiv = (uint32_t)(UART_DIV_SAMPLING8((HSI_VALUE >> 2U), huart->Init.BaudRate)); } else { @@ -1833,8 +1774,8 @@ void UART_SetConfig(UART_HandleTypeDef *huart) break; } - brrtemp = usartdiv & 0xFFF0; - brrtemp |= (uint16_t)((uint16_t)(usartdiv & (uint16_t)0x000F) >> (uint16_t)1); + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((uint16_t)(usartdiv & (uint16_t)0x000FU) >> (uint16_t)1U); huart->Instance->BRR = brrtemp; } else @@ -1848,9 +1789,9 @@ void UART_SetConfig(UART_HandleTypeDef *huart) huart->Instance->BRR = (uint32_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_HSI: - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0) + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) { - huart->Instance->BRR = (uint32_t)(UART_DIV_SAMPLING16((HSI_VALUE >> 2), huart->Init.BaudRate)); + huart->Instance->BRR = (uint32_t)(UART_DIV_SAMPLING16((HSI_VALUE >> 2U), huart->Init.BaudRate)); } else { @@ -1900,7 +1841,8 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Initialize the UART state*/ huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->State= HAL_UART_STATE_READY; + huart->gState= HAL_UART_STATE_READY; + huart->RxState= HAL_UART_STATE_READY; return HAL_OK; } @@ -1989,7 +1931,7 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { - uint32_t tickstart = 0x00; + uint32_t tickstart = 0x00U; tickstart = HAL_GetTick(); /* Wait until flag is set */ @@ -2000,7 +1942,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); @@ -2008,7 +1950,8 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - huart->State= HAL_UART_STATE_READY; + huart->gState= HAL_UART_STATE_READY; + huart->RxState= HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -2025,7 +1968,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); @@ -2033,7 +1976,8 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - huart->State= HAL_UART_STATE_READY; + huart->gState= HAL_UART_STATE_READY; + huart->RxState= HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart.h index d7e63ae79a..11d6261f58 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_uart.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of UART HAL module. ****************************************************************************** * @attention @@ -157,20 +157,67 @@ typedef struct /** @defgroup UART_State_Definition UART state definition * @{ */ + /** * @brief HAL UART State structures definition + * @note HAL UART State value is a combination of 2 different substates: gState and RxState. + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. */ typedef enum { - HAL_UART_STATE_RESET = 0x00, /*!< Peripheral Reset state */ - HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_UART_STATE_ERROR = 0x04 /*!< Error */ + HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized + Value is allowed for gState and RxState */ + HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ + HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state + Value is allowed for gState only */ + HAL_UART_STATE_ERROR = 0xE0U /*!< Error + Value is allowed for gState only */ }HAL_UART_StateTypeDef; + /** * @} */ @@ -181,12 +228,12 @@ typedef enum * @brief HAL UART Error Code definition */ -#define HAL_UART_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_UART_ERROR_PE ((uint32_t)0x01) /*!< Parity error */ -#define HAL_UART_ERROR_NE ((uint32_t)0x02) /*!< Noise error */ -#define HAL_UART_ERROR_FE ((uint32_t)0x04) /*!< frame error */ -#define HAL_UART_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */ -#define HAL_UART_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ +#define HAL_UART_ERROR_NONE ((uint32_t)0x00U) /*!< No error */ +#define HAL_UART_ERROR_PE ((uint32_t)0x01U) /*!< Parity error */ +#define HAL_UART_ERROR_NE ((uint32_t)0x02U) /*!< Noise error */ +#define HAL_UART_ERROR_FE ((uint32_t)0x04U) /*!< frame error */ +#define HAL_UART_ERROR_ORE ((uint32_t)0x08U) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA ((uint32_t)0x10U) /*!< DMA transfer error */ /** * @} @@ -199,11 +246,11 @@ typedef enum */ typedef enum { - UART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - UART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - UART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - UART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - UART_CLOCKSOURCE_LSE = 0x08 /*!< LSE clock source */ + UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + UART_CLOCKSOURCE_LSE = 0x08U /*!< LSE clock source */ }UART_ClockSourceTypeDef; /** * @} @@ -211,43 +258,49 @@ typedef enum /** @defgroup UART_handle_Definition Handle structure definition * @{ */ + /** * @brief UART handle Structure definition */ - typedef struct { - USART_TypeDef *Instance; /* UART registers base address */ + USART_TypeDef *Instance; /*!< UART registers base address */ - UART_InitTypeDef Init; /* UART communication parameters */ + UART_InitTypeDef Init; /*!< UART communication parameters */ - UART_AdvFeatureInitTypeDef AdvancedInit; /* UART Advanced Features initialization parameters */ + UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ - uint8_t *pTxBuffPtr; /* Pointer to UART Tx transfer Buffer */ + uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ - uint16_t TxXferSize; /* UART Tx Transfer size */ + uint16_t TxXferSize; /*!< UART Tx Transfer size */ - uint16_t TxXferCount; /* UART Tx Transfer Counter */ + uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ - uint8_t *pRxBuffPtr; /* Pointer to UART Rx transfer Buffer */ + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ - uint16_t RxXferSize; /* UART Rx Transfer size */ + uint16_t RxXferSize; /*!< UART Rx Transfer size */ - uint16_t RxXferCount; /* UART Rx Transfer Counter */ + uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ - uint16_t Mask; /* UART Rx RDR register mask */ + uint16_t Mask; /*!< UART Rx RDR register mask */ - DMA_HandleTypeDef *hdmatx; /* UART Tx DMA Handle parameters */ + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ - DMA_HandleTypeDef *hdmarx; /* UART Rx DMA Handle parameters */ + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ - HAL_LockTypeDef Lock; /* Locking object */ + HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_UART_StateTypeDef State; /* UART communication state */ + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ - __IO uint32_t ErrorCode; /* UART Error code */ + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ }UART_HandleTypeDef; + /** * @} */ @@ -263,7 +316,7 @@ typedef struct /** @defgroup UART_Stop_Bits UART stop bit definition * @{ */ -#define UART_STOPBITS_1 ((uint32_t)0x0000) /*!< USART frame with 1 stop bit */ +#define UART_STOPBITS_1 ((uint32_t)0x0000U) /*!< USART frame with 1 stop bit */ #define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */ #define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< USART frame with 2 stop bits */ #define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ @@ -280,7 +333,7 @@ typedef struct /** @defgroup UART_Parity UART parity definition * @{ */ -#define UART_PARITY_NONE ((uint32_t)0x0000) +#define UART_PARITY_NONE ((uint32_t)0x0000U) #define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) #define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) #define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ @@ -293,7 +346,7 @@ typedef struct /** @defgroup UART_Hardware_Flow_Control UART hardware flow control definition * @{ */ -#define UART_HWCONTROL_NONE ((uint32_t)0x0000) +#define UART_HWCONTROL_NONE ((uint32_t)0x0000U) #define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) #define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) #define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) @@ -312,7 +365,7 @@ typedef struct #define UART_MODE_RX ((uint32_t)USART_CR1_RE) #define UART_MODE_TX ((uint32_t)USART_CR1_TE) #define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) -#define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00)) +#define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00U) && ((MODE) != (uint32_t)0x00U)) /** * @} */ @@ -320,7 +373,7 @@ typedef struct /** @defgroup UART_State UART state enable and disable definition * @{ */ -#define UART_STATE_DISABLE ((uint32_t)0x0000) +#define UART_STATE_DISABLE ((uint32_t)0x0000U) #define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) #define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ ((STATE) == UART_STATE_ENABLE)) @@ -331,7 +384,7 @@ typedef struct /** @defgroup UART_Over_Sampling UART over sampling definition * @{ */ -#define UART_OVERSAMPLING_16 ((uint32_t)0x0000) +#define UART_OVERSAMPLING_16 ((uint32_t)0x0000U) #define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) #define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ ((SAMPLING) == UART_OVERSAMPLING_8)) @@ -343,7 +396,7 @@ typedef struct /** @defgroup UART_Receiver_TimeOut UART receiver timeOut definition * @{ */ -#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000) +#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000U) #define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) #define IS_UART_RECEIVER_TIMEOUT(TIMEOUT) (((TIMEOUT) == UART_RECEIVER_TIMEOUT_DISABLE) || \ ((TIMEOUT) == UART_RECEIVER_TIMEOUT_ENABLE)) @@ -354,7 +407,7 @@ typedef struct /** @defgroup UART_LIN UART LIN enable and disable definition * @{ */ -#define UART_LIN_DISABLE ((uint32_t)0x00000000) +#define UART_LIN_DISABLE ((uint32_t)0x00000000U) #define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) #define IS_UART_LIN(LIN) (((LIN) == UART_LIN_DISABLE) || \ ((LIN) == UART_LIN_ENABLE)) @@ -365,7 +418,7 @@ typedef struct /** @defgroup UART_LIN_Break_Detection UART LIN break detection definition * @{ */ -#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) +#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000U) #define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) #define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) @@ -378,7 +431,7 @@ typedef struct /** @defgroup UART_One_Bit UART one bit definition * @{ */ -#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) +#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U) #define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) #define IS_UART_ONE_BIT_SAMPLE(ONEBIT) (((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLE) || \ ((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLE)) @@ -389,7 +442,7 @@ typedef struct /** @defgroup UART_DMA_Tx UART DMA Tx definition * @{ */ -#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000) +#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000U) #define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) #define IS_UART_DMA_TX(DMATX) (((DMATX) == UART_DMA_TX_DISABLE) || \ ((DMATX) == UART_DMA_TX_ENABLE)) @@ -400,7 +453,7 @@ typedef struct /** @defgroup UART_DMA_Rx UART DMA Rx definition * @{ */ -#define UART_DMA_RX_DISABLE ((uint32_t)0x0000) +#define UART_DMA_RX_DISABLE ((uint32_t)0x0000U) #define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) #define IS_UART_DMA_RX(DMARX) (((DMARX) == UART_DMA_RX_DISABLE) || \ ((DMARX) == UART_DMA_RX_ENABLE)) @@ -411,7 +464,7 @@ typedef struct /** @defgroup UART_Half_Duplex_Selection UART half duplex selection definition * @{ */ -#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000) +#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000U) #define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) #define IS_UART_HALF_DUPLEX(HDSEL) (((HDSEL) == UART_HALF_DUPLEX_DISABLE) || \ ((HDSEL) == UART_HALF_DUPLEX_ENABLE)) @@ -460,15 +513,15 @@ typedef struct * - ZZZZZ : Flag position in the ISR register(5bits) * @{ */ -#define UART_IT_PE ((uint32_t)0x0028) -#define UART_IT_TXE ((uint32_t)0x0727) -#define UART_IT_TC ((uint32_t)0x0626) -#define UART_IT_RXNE ((uint32_t)0x0525) -#define UART_IT_IDLE ((uint32_t)0x0424) -#define UART_IT_LBD ((uint32_t)0x0846) -#define UART_IT_CTS ((uint32_t)0x096A) -#define UART_IT_CM ((uint32_t)0x112E) -#define UART_IT_WUF ((uint32_t)0x1476) +#define UART_IT_PE ((uint32_t)0x0028U) +#define UART_IT_TXE ((uint32_t)0x0727U) +#define UART_IT_TC ((uint32_t)0x0626U) +#define UART_IT_RXNE ((uint32_t)0x0525U) +#define UART_IT_IDLE ((uint32_t)0x0424U) +#define UART_IT_LBD ((uint32_t)0x0846U) +#define UART_IT_CTS ((uint32_t)0x096AU) +#define UART_IT_CM ((uint32_t)0x112EU) +#define UART_IT_WUF ((uint32_t)0x1476U) /** Elements values convention: 000000000XXYYYYYb * - YYYYY : Interrupt source position in the XX register (5bits) @@ -477,14 +530,14 @@ typedef struct * - 10: CR2 register * - 11: CR3 register */ -#define UART_IT_ERR ((uint32_t)0x0060) +#define UART_IT_ERR ((uint32_t)0x0060U) /** Elements values convention: 0000ZZZZ00000000b * - ZZZZ : Flag position in the ISR register(4bits) */ -#define UART_IT_ORE ((uint32_t)0x0300) -#define UART_IT_NE ((uint32_t)0x0200) -#define UART_IT_FE ((uint32_t)0x0100) +#define UART_IT_ORE ((uint32_t)0x0300U) +#define UART_IT_NE ((uint32_t)0x0200U) +#define UART_IT_FE ((uint32_t)0x0100U) /** * @} */ @@ -528,15 +581,15 @@ typedef struct /** @defgroup UART_Advanced_Features_Initialization_Type UART advanced features initialization type definition * @{ */ -#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) -#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) -#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) -#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) -#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) -#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) -#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) -#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040) -#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) +#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000U) +#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001U) +#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002U) +#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004U) +#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008U) +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010U) +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020U) +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040U) +#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080U) #define IS_UART_ADVFEATURE_INIT(INIT) ((INIT) <= (UART_ADVFEATURE_NO_INIT | \ UART_ADVFEATURE_TXINVERT_INIT | \ UART_ADVFEATURE_RXINVERT_INIT | \ @@ -553,7 +606,7 @@ typedef struct /** @defgroup UART_Tx_Inv UART advanced Tx inv activation definition * @{ */ -#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) #define IS_UART_ADVFEATURE_TXINV(TXINV) (((TXINV) == UART_ADVFEATURE_TXINV_DISABLE) || \ ((TXINV) == UART_ADVFEATURE_TXINV_ENABLE)) @@ -564,7 +617,7 @@ typedef struct /** @defgroup UART_Rx_Inv UART advanced Rx inv activation definition * @{ */ -#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) #define IS_UART_ADVFEATURE_RXINV(RXINV) (((RXINV) == UART_ADVFEATURE_RXINV_DISABLE) || \ ((RXINV) == UART_ADVFEATURE_RXINV_ENABLE)) @@ -575,7 +628,7 @@ typedef struct /** @defgroup UART_Data_Inv UART advanced data inv activation definition * @{ */ -#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) #define IS_UART_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == UART_ADVFEATURE_DATAINV_DISABLE) || \ ((DATAINV) == UART_ADVFEATURE_DATAINV_ENABLE)) @@ -586,7 +639,7 @@ typedef struct /** @defgroup UART_Rx_Tx_Swap UART advanced swap activation definition * @{ */ -#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) #define IS_UART_ADVFEATURE_SWAP(SWAP) (((SWAP) == UART_ADVFEATURE_SWAP_DISABLE) || \ ((SWAP) == UART_ADVFEATURE_SWAP_ENABLE)) @@ -597,7 +650,7 @@ typedef struct /** @defgroup UART_Overrun_Disable UART advanced overrun activation definition * @{ */ -#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) #define IS_UART_OVERRUN(OVERRUN) (((OVERRUN) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ ((OVERRUN) == UART_ADVFEATURE_OVERRUN_DISABLE)) @@ -608,7 +661,7 @@ typedef struct /** @defgroup UART_AutoBaudRate_Enable UART advanced auto baud rate activation definition * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) #define IS_UART_ADVFEATURE_AUTOBAUDRATE(AUTOBAUDRATE) (((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ ((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) @@ -619,7 +672,7 @@ typedef struct /** @defgroup UART_DMA_Disable_on_Rx_Error UART advanced DMA on Rx error activation definition * @{ */ -#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000U) #define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) #define IS_UART_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ ((DMA) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) @@ -630,7 +683,7 @@ typedef struct /** @defgroup UART_MSB_First UART advanced MSB first activation definition * @{ */ -#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) #define IS_UART_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ ((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_ENABLE)) @@ -641,7 +694,7 @@ typedef struct /** @defgroup UART_Stop_Mode_Enable UART advanced stop mode activation definition * @{ */ -#define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) #define IS_UART_ADVFEATURE_STOPMODE(STOPMODE) (((STOPMODE) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ ((STOPMODE) == UART_ADVFEATURE_STOPMODE_ENABLE)) @@ -652,7 +705,7 @@ typedef struct /** @defgroup UART_Mute_Mode UART advanced mute mode activation definition * @{ */ -#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) #define IS_UART_MUTE_MODE(MUTE) (((MUTE) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ ((MUTE) == UART_ADVFEATURE_MUTEMODE_ENABLE)) @@ -663,7 +716,7 @@ typedef struct /** @defgroup UART_CR2_ADDRESS_LSBPOS UART CR2 address lsb position definition * @{ */ -#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24) +#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24U) /** * @} */ @@ -671,7 +724,7 @@ typedef struct /** @defgroup UART_WakeUp_from_Stop_Selection UART wake up mode selection definition * @{ */ -#define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x0000) +#define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x0000U) #define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) #define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) #define IS_UART_WAKEUP_SELECTION(WAKE) (((WAKE) == UART_WAKEUP_ON_ADDRESS) || \ @@ -684,7 +737,7 @@ typedef struct /** @defgroup UART_DriverEnable_Polarity UART driver polarity level definition * @{ */ -#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000) +#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000U) #define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) #define IS_UART_DE_POLARITY(POLARITY) (((POLARITY) == UART_DE_POLARITY_HIGH) || \ ((POLARITY) == UART_DE_POLARITY_LOW)) @@ -695,7 +748,7 @@ typedef struct /** @defgroup UART_CR1_DEAT_ADDRESS_LSBPOS UART CR1 DEAT address lsb position definition * @{ */ -#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21) +#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21U) /** * @} */ @@ -703,7 +756,7 @@ typedef struct /** @defgroup UART_CR1_DEDT_ADDRESS_LSBPOS UART CR1 DEDT address lsb position definition * @{ */ -#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16) +#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16U) /** * @} */ @@ -711,7 +764,7 @@ typedef struct /** @defgroup UART_Interruption_Mask UART interruption mask definition * @{ */ -#define UART_IT_MASK ((uint32_t)0x001F) +#define UART_IT_MASK ((uint32_t)0x001FU) /** * @} */ @@ -840,9 +893,9 @@ typedef struct * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & UART_IT_MASK)))) +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Disables the specified UART interrupt. * @param __HANDLE__: specifies the UART Handle. @@ -861,9 +914,9 @@ typedef struct * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & UART_IT_MASK)))) +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Checks whether the specified UART interrupt has occurred or not. * @param __HANDLE__: specifies the UART Handle. @@ -884,7 +937,7 @@ typedef struct * @arg UART_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) +#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08U))) /** @brief Checks whether the specified UART interrupt source is enabled. * @param __HANDLE__: specifies the UART Handle. @@ -903,8 +956,8 @@ typedef struct * @arg UART_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK))) +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \ + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1U << (((uint16_t)(__IT__)) & UART_IT_MASK))) /** @brief Clears the specified UART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__: specifies the UART Handle. @@ -1062,21 +1115,21 @@ typedef struct * @param _BAUD_: Baud rate set by the user * @retval Division result */ -#define __DIV_LPUART(_PCLK_, _BAUD_) ((uint32_t)(((((uint64_t)_PCLK_)*256.0))/(((uint64_t)_BAUD_)))) +#define __DIV_LPUART(_PCLK_, _BAUD_) ((uint32_t)(((((uint64_t)_PCLK_)*256.0) + (((uint64_t)_BAUD_)/2U)) / (((uint64_t)_BAUD_)))) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode * @param _PCLK_: UART clock * @param _BAUD_: Baud rate set by the user * @retval Division result */ -#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*2)/((_BAUD_))) +#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) ((((_PCLK_)*2U) + ((_BAUD_)/2U)) / ((_BAUD_))) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode * @param _PCLK_: UART clock * @param _BAUD_: Baud rate set by the user * @retval Division result */ -#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_))/((_BAUD_))) +#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) ((((_PCLK_)) + ((_BAUD_)/2U)) / ((_BAUD_))) /** @brief Check whether or not UART instance is Low Power UART. * @param __HANDLE__: specifies the UART Handle. diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart_ex.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart_ex.c index 3f7ba739c2..a9a90da882 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_uart_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Extended UART HAL module driver. * * This file provides firmware functions to manage the following @@ -76,7 +76,7 @@ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#define UART_REACK_TIMEOUT ((uint32_t) 1000) +#define UART_REACK_TIMEOUT ((uint32_t) 1000U) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -128,7 +128,7 @@ static void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpType */ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) { - uint32_t temp = 0x0; + uint32_t temp = 0x0U; /* Check the UART handle allocation */ if(huart == NULL) @@ -145,13 +145,13 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, /* Check the Driver Enable deassertion time */ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); - if(huart->State == HAL_UART_STATE_RESET) + if(huart->gState == HAL_UART_STATE_RESET) { /* Init the low level hardware : GPIO, CLOCK, CORTEX */ HAL_UART_MspInit(huart); } - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -178,7 +178,7 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* TEACK and/or REACK to check before moving huart->State to Ready */ + /* TEACK and/or REACK to check before moving huart->gState and huart_RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -219,12 +219,12 @@ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Set the USART UESM bit */ huart->Instance->CR1 |= USART_CR1_UESM; - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -243,12 +243,12 @@ HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Set the USART UESM bit */ huart->Instance->CR3 |= USART_CR3_UCESM; - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -266,12 +266,12 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Clear USART UESM bit */ huart->Instance->CR1 &= ~(USART_CR1_UESM); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -289,12 +289,12 @@ HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Clear USART UESM bit */ huart->Instance->CR3 &= ~(USART_CR3_UCESM); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -323,7 +323,7 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -339,7 +339,7 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* Wait until REACK flag is set before moving huart->State to Ready */ + /* Wait until REACK flag is set before moving huart->gState to Ready */ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, UART_REACK_TIMEOUT) != HAL_OK) { return HAL_TIMEOUT; @@ -350,7 +350,7 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar /* Initialize the UART state*/ huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->State= HAL_UART_STATE_READY; + huart->gState= HAL_UART_STATE_READY; return HAL_OK; } @@ -379,7 +379,7 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua /* Check the address length parameter */ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -390,7 +390,7 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* TEACK and/or REACK to check before moving huart->State to Ready */ + /* TEACK and/or REACK to check before moving huart->gState and/or huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart_ex.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart_ex.h index 88b5fb3a1f..839caf54d6 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_uart_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of UART HAL Extension module. ****************************************************************************** * @attention @@ -97,7 +97,7 @@ typedef struct * @{ */ #define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) -#define UART_WORDLENGTH_8B ((uint32_t)0x0000) +#define UART_WORDLENGTH_8B ((uint32_t)0x0000U) #define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) #define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_7B) || \ ((LENGTH) == UART_WORDLENGTH_8B) || \ @@ -109,7 +109,7 @@ typedef struct /** @defgroup UARTEx_AutoBaud_Rate_Mode Auto baud rate mode definition * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000) +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000U) #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) @@ -124,7 +124,7 @@ typedef struct /** @defgroup UARTEx_WakeUp_Address_Length WakeUp address length definition * @{ */ -#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000) +#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000U) #define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) #define IS_UART_ADDRESSLENGTH_DETECT(ADDRESS) (((ADDRESS) == UART_ADDRESS_DETECT_4B) || \ ((ADDRESS) == UART_ADDRESS_DETECT_7B)) @@ -136,7 +136,7 @@ typedef struct /** @defgroup UARTEx_WakeUp_Methods Wakeup methods definition * @{ */ -#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000) +#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000U) #define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) #define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart.c index f12d6422e0..3fc35648d2 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_usart.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief USART HAL module driver. * * This file provides firmware functions to manage the following @@ -100,9 +100,9 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#define DUMMY_DATA ((uint16_t) 0xFFFF) -#define TEACK_REACK_TIMEOUT ((uint32_t) 1000) -#define HAL_USART_TXDMA_TIMEOUTVALUE ((uint32_t) 22000) +#define DUMMY_DATA ((uint16_t) 0xFFFFU) +#define TEACK_REACK_TIMEOUT ((uint32_t) 1000U) +#define HAL_USART_TXDMA_TIMEOUTVALUE ((uint32_t) 22000U) #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | \ @@ -150,8 +150,21 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); (++) Stop Bit (++) Parity: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible USART frame formats are as listed in the following table: + (++) USART polarity + (++) USART phase + (++) USART LastBit + (++) Receiver/transmitter modes + + [..] + The HAL_USART_Init() function follows the USART synchronous configuration + procedure (details for the procedure are available in reference manual (RM0329)). + +@endverbatim + + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible USART frame formats are as listed in the following table: + + Table 1. USART frame format. +-------------------------------------------------------------+ | M0 bit | PCE bit | USART frame | |---------------------|---------------------------------------| @@ -163,16 +176,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); |---------|-----------|---------------------------------------| | 1 | 1 | | SB | 8 bit data | PB | STB | | +-------------------------------------------------------------+ - (++) USART polarity - (++) USART phase - (++) USART LastBit - (++) Receiver/transmitter modes - [..] - The HAL_USART_Init() function follows the USART synchronous configuration - procedure (details for the procedure are available in reference manual (RM0329)). - -@endverbatim * @{ */ @@ -244,9 +248,9 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) husart->State = HAL_USART_STATE_BUSY; - husart->Instance->CR1 = 0x0; - husart->Instance->CR2 = 0x0; - husart->Instance->CR3 = 0x0; + husart->Instance->CR1 = 0x0U; + husart->Instance->CR2 = 0x0U; + husart->Instance->CR3 = 0x0U; /* DeInit the low level hardware */ HAL_USART_MspDeInit(husart); @@ -366,7 +370,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -381,7 +385,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa husart->TxXferCount = Size; /* Check the remaining data to be sent */ - while(husart->TxXferCount > 0) + while(husart->TxXferCount > 0U) { husart->TxXferCount--; if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) @@ -391,12 +395,12 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { tmp = (uint16_t*) pTxData; - husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - pTxData += 2; + husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + pTxData += 2U; } else { - husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF); + husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFFU); } } @@ -434,7 +438,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL) || (Size == 0)) + if((pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -452,7 +456,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat uhMask = husart->Mask; /* as long as data have to be received */ - while(husart->RxXferCount > 0) + while(husart->RxXferCount > 0U) { husart->RxXferCount--; @@ -464,7 +468,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat { return HAL_TIMEOUT; } - husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x0FF); + husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x0FFU); /* Wait for RXNE Flag */ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) @@ -476,7 +480,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat { tmp = (uint16_t*) pRxData ; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - pRxData +=2; + pRxData +=2U; } else { @@ -513,7 +517,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -533,7 +537,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t uhMask = husart->Mask; /* Check the remain data to be sent */ - while(husart->TxXferCount > 0) + while(husart->TxXferCount > 0U) { husart->TxXferCount--; husart->RxXferCount--; @@ -547,7 +551,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t { tmp = (uint16_t*) pTxData; husart->Instance->TDR = (*tmp & uhMask); - pTxData += 2; + pTxData += 2U; } else { @@ -564,7 +568,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t { tmp = (uint16_t*) pRxData ; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - pRxData +=2; + pRxData +=2U; } else { @@ -596,7 +600,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT { if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL ) || (Size == 0)) + if((pTxData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -643,7 +647,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx { if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL ) || (Size == 0)) + if((pRxData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -674,11 +678,11 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /* Send dummy byte in order to generate the clock for the Slave to send the next data */ if(husart->Init.WordLength == USART_WORDLENGTH_9B) { - husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x01FF); + husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x01FFU); } else { - husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FF); + husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FFU); } return HAL_OK; @@ -701,7 +705,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint { if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -757,7 +761,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL ) || (Size == 0)) + if((pTxData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -818,7 +822,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL ) || (Size == 0)) + if((pRxData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -891,7 +895,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1265,7 +1269,7 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) */ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { - uint32_t tickstart = 0x00; + uint32_t tickstart = 0x00U; tickstart = HAL_GetTick(); /* Wait until flag is set */ @@ -1276,7 +1280,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); @@ -1301,7 +1305,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); @@ -1334,7 +1338,7 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* DMA Normal mode */ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { - husart->TxXferCount = 0; + husart->TxXferCount = 0U; if(husart->State == HAL_USART_STATE_BUSY_TX) { @@ -1377,9 +1381,9 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { - husart->RxXferCount = 0; + husart->RxXferCount = 0U; if(husart->State == HAL_USART_STATE_BUSY_RX) { @@ -1438,8 +1442,8 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma) { USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - husart->RxXferCount = 0; - husart->TxXferCount = 0; + husart->RxXferCount = 0U; + husart->TxXferCount = 0U; husart->ErrorCode |= HAL_USART_ERROR_DMA; husart->State= HAL_USART_STATE_READY; @@ -1456,11 +1460,11 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) { - uint16_t* tmp = 0; + uint16_t* tmp = 0U; if(husart->State == HAL_USART_STATE_BUSY_TX) { - if(husart->TxXferCount == 0) + if(husart->TxXferCount == 0U) { /* Disable the USART Transmit Complete Interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); @@ -1475,12 +1479,12 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { tmp = (uint16_t*) husart->pTxBuffPtr; - husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - husart->pTxBuffPtr += 2; + husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + husart->pTxBuffPtr += 2U; } else { - husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF); + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFFU); } husart->TxXferCount--; @@ -1534,16 +1538,16 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) { tmp = (uint16_t*) husart->pRxBuffPtr; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - husart->pRxBuffPtr += 2; + husart->pRxBuffPtr += 2U; } else { *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); } /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ - husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FF); + husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FFU); - if(--husart->RxXferCount == 0) + if(--husart->RxXferCount == 0U) { /* Wait for RXNE Flag */ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, HAL_USART_TXDMA_TIMEOUTVALUE) != HAL_OK) @@ -1590,7 +1594,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) if(husart->State == HAL_USART_STATE_BUSY_TX_RX) { - if(husart->TxXferCount != 0x00) + if(husart->TxXferCount != 0x00U) { if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TC) != RESET) { @@ -1598,7 +1602,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) { tmp = (uint16_t*) husart->pTxBuffPtr; husart->Instance->TDR = (uint16_t)(*tmp & uhMask); - husart->pTxBuffPtr += 2; + husart->pTxBuffPtr += 2U; } else { @@ -1607,14 +1611,14 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) husart->TxXferCount--; /* Check the latest data transmitted */ - if(husart->TxXferCount == 0) + if(husart->TxXferCount == 0U) { __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); } } } - if(husart->RxXferCount != 0x00) + if(husart->RxXferCount != 0x00U) { if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET) { @@ -1622,7 +1626,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) { tmp = (uint16_t*) husart->pRxBuffPtr; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - husart->pRxBuffPtr += 2; + husart->pRxBuffPtr += 2U; } else { @@ -1633,7 +1637,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) } /* Check the latest data received */ - if(husart->RxXferCount == 0) + if(husart->RxXferCount == 0U) { __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); @@ -1668,11 +1672,11 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) */ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) { - uint32_t tmpreg = 0x0; - uint32_t clocksource = 0x0; + uint32_t tmpreg = 0x0U; + uint32_t clocksource = 0x0U; HAL_StatusTypeDef ret = HAL_OK; - uint16_t brrtemp = 0x0000; - uint16_t usartdiv = 0x0000; + uint16_t brrtemp = 0x0000U; + uint16_t usartdiv = 0x0000U; /* Check the parameters */ @@ -1716,19 +1720,19 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) switch (clocksource) { case USART_CLOCKSOURCE_PCLK1: - usartdiv = (uint16_t)((2*HAL_RCC_GetPCLK1Freq()) / husart->Init.BaudRate); + usartdiv = (uint16_t)(((2U*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate); break; case USART_CLOCKSOURCE_PCLK2: - usartdiv = (uint16_t)((2*HAL_RCC_GetPCLK2Freq()) / husart->Init.BaudRate); + usartdiv = (uint16_t)(((2U*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate); break; case USART_CLOCKSOURCE_HSI: - usartdiv = (uint16_t)((2*HSI_VALUE) / husart->Init.BaudRate); + usartdiv = (uint16_t)(((2U*HSI_VALUE) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate); break; case USART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint16_t)((2*HAL_RCC_GetSysClockFreq()) / husart->Init.BaudRate); + usartdiv = (uint16_t)(((2U*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate); break; case USART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)((2*LSE_VALUE) / husart->Init.BaudRate); + usartdiv = (uint16_t)(((2U*LSE_VALUE) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate); break; case USART_CLOCKSOURCE_UNDEFINED: default: @@ -1736,8 +1740,8 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) break; } - brrtemp = usartdiv & 0xFFF0; - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U); + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); husart->Instance->BRR = brrtemp; return ret; diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart.h index 9c61966e83..ffcad4402e 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_usart.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of USART HAL module. ****************************************************************************** * @attention @@ -119,14 +119,14 @@ typedef struct */ typedef enum { - HAL_USART_STATE_RESET = 0x00, /*!< Peripheral Reset state */ - HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */ - HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_USART_STATE_ERROR = 0x04 /*!< Error */ + HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral Reset state */ + HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */ + HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_USART_STATE_ERROR = 0x04U /*!< Error */ }HAL_USART_StateTypeDef; /** * @} @@ -138,12 +138,12 @@ typedef enum * @brief HAL USART Error Code definition */ -#define HAL_USART_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_USART_ERROR_PE ((uint32_t)0x01) /*!< Parity error */ -#define HAL_USART_ERROR_NE ((uint32_t)0x02) /*!< Noise error */ -#define HAL_USART_ERROR_FE ((uint32_t)0x04) /*!< frame error */ -#define HAL_USART_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */ -#define HAL_USART_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ +#define HAL_USART_ERROR_NONE ((uint32_t)0x00U) /*!< No error */ +#define HAL_USART_ERROR_PE ((uint32_t)0x01U) /*!< Parity error */ +#define HAL_USART_ERROR_NE ((uint32_t)0x02U) /*!< Noise error */ +#define HAL_USART_ERROR_FE ((uint32_t)0x04U) /*!< frame error */ +#define HAL_USART_ERROR_ORE ((uint32_t)0x08U) /*!< Overrun error */ +#define HAL_USART_ERROR_DMA ((uint32_t)0x10U) /*!< DMA transfer error */ /** * @} @@ -156,12 +156,12 @@ typedef enum */ typedef enum { - USART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - USART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - USART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - USART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - USART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - USART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */ + USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ }USART_ClockSourceTypeDef; /** * @} @@ -219,7 +219,7 @@ typedef struct /** @defgroup USART_Stop_Bits USART stop bit definition * @{ */ -#define USART_STOPBITS_1 ((uint32_t)0x0000) +#define USART_STOPBITS_1 ((uint32_t)0x0000U) #define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) #define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) #define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \ @@ -232,7 +232,7 @@ typedef struct /** @defgroup USART_Parity USART parity definition * @{ */ -#define USART_PARITY_NONE ((uint32_t)0x0000) +#define USART_PARITY_NONE ((uint32_t)0x0000U) #define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) #define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) #define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \ @@ -258,7 +258,7 @@ typedef struct /** @defgroup USART_Clock USART clock activation definition * @{ */ -#define USART_CLOCK_DISABLE ((uint32_t)0x0000) +#define USART_CLOCK_DISABLE ((uint32_t)0x0000U) #define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) #define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \ ((CLOCK) == USART_CLOCK_ENABLE)) @@ -269,7 +269,7 @@ typedef struct /** @defgroup USART_Clock_Polarity USART polarity level definition * @{ */ -#define USART_POLARITY_LOW ((uint32_t)0x0000) +#define USART_POLARITY_LOW ((uint32_t)0x0000U) #define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) #define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH)) /** @@ -279,7 +279,7 @@ typedef struct /** @defgroup USART_Clock_Phase USART clock phase definition * @{ */ -#define USART_PHASE_1EDGE ((uint32_t)0x0000) +#define USART_PHASE_1EDGE ((uint32_t)0x0000U) #define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) #define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE)) /** @@ -289,7 +289,7 @@ typedef struct /** @defgroup USART_Last_Bit USART last bit activation definition * @{ */ -#define USART_LASTBIT_DISABLE ((uint32_t)0x0000) +#define USART_LASTBIT_DISABLE ((uint32_t)0x0000U) #define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) #define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \ ((LASTBIT) == USART_LASTBIT_ENABLE)) @@ -332,16 +332,16 @@ typedef struct * @{ */ -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_PE ((uint16_t)0x0028U) +#define USART_IT_TXE ((uint16_t)0x0727U) +#define USART_IT_TC ((uint16_t)0x0626U) +#define USART_IT_RXNE ((uint16_t)0x0525U) +#define USART_IT_IDLE ((uint16_t)0x0424U) +#define USART_IT_ERR ((uint16_t)0x0060U) -#define USART_IT_ORE ((uint16_t)0x0300) -#define USART_IT_NE ((uint16_t)0x0200) -#define USART_IT_FE ((uint16_t)0x0100) +#define USART_IT_ORE ((uint16_t)0x0300U) +#define USART_IT_NE ((uint16_t)0x0200U) +#define USART_IT_FE ((uint16_t)0x0100U) /** * @} */ @@ -374,7 +374,7 @@ typedef struct /** @defgroup USART_Interruption_Mask USART interruption mask definition * @{ */ -#define USART_IT_MASK ((uint16_t)0x001F) +#define USART_IT_MASK ((uint16_t)0x001FU) /** * @} */ @@ -489,9 +489,9 @@ typedef struct * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)(((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & USART_IT_MASK)))) +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disables the specified USART interrupt. * @param __HANDLE__: specifies the USART Handle which can be USART1 or USART2. @@ -505,9 +505,9 @@ typedef struct * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & USART_IT_MASK)))) +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Checks whether the specified USART interrupt has occurred or not. * @param __HANDLE__: specifies the USART Handle which can be USART1 or USART2. @@ -523,7 +523,7 @@ typedef struct * @arg USART_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) +#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08U))) /** @brief Checks whether the specified USART interrupt source is enabled. * @param __HANDLE__: specifies the USART Handle which can be USART1 or USART2. @@ -539,8 +539,8 @@ typedef struct * @arg USART_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \ +#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \ + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1U << \ (((uint16_t)(__IT__)) & USART_IT_MASK))) @@ -604,7 +604,7 @@ typedef struct * divided by the smallest oversampling used on the USART (i.e. 8) * @retval Test result (TRUE or FALSE). */ -#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4000001) +#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4000001U) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart_ex.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart_ex.h index 291dd0ac80..424c613460 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_usart_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of USART HAL Extension module. ****************************************************************************** * @attention @@ -63,7 +63,7 @@ * @{ */ #define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) -#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) +#define USART_WORDLENGTH_8B ((uint32_t)0x00000000U) #define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) #define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_7B) || \ ((LENGTH) == USART_WORDLENGTH_8B) || \ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_wwdg.c index 4f349e4cd6..3a8a20b333 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_wwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_wwdg.c * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: @@ -196,9 +196,9 @@ HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg) HAL_WWDG_MspDeInit(hwwdg); /* Reset WWDG Control, configuration and status register */ - MODIFY_REG(hwwdg->Instance->CR, (WWDG_CR_T | WWDG_CR_WDGA),0x0000007F); - MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W | WWDG_CFR_EWI),0x0000007F); - MODIFY_REG(hwwdg->Instance->SR,WWDG_SR_EWIF,0x0); + MODIFY_REG(hwwdg->Instance->CR, (WWDG_CR_T | WWDG_CR_WDGA),0x0000007FU); + MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W | WWDG_CFR_EWI),0x0000007FU); + MODIFY_REG(hwwdg->Instance->SR,WWDG_SR_EWIF,0x0U); /* Change peripheral state and release lock*/ hwwdg->State = HAL_WWDG_STATE_RESET; diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_wwdg.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_wwdg.h index b703719d1f..34f1d10599 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_wwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_wwdg.h * @author MCD Application Team - * @version V1.5.0 - * @date 8-January-2016 + * @version V1.7.0 + * @date 31-May-2016 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention @@ -68,11 +68,11 @@ */ typedef enum { - HAL_WWDG_STATE_RESET = 0x00, /*!< WWDG not yet initialized or disabled */ - HAL_WWDG_STATE_READY = 0x01, /*!< WWDG initialized and ready for use */ - HAL_WWDG_STATE_BUSY = 0x02, /*!< WWDG internal process is ongoing */ - HAL_WWDG_STATE_TIMEOUT = 0x03, /*!< WWDG timeout state */ - HAL_WWDG_STATE_ERROR = 0x04 /*!< WWDG error state */ + HAL_WWDG_STATE_RESET = 0x00U, /*!< WWDG not yet initialized or disabled */ + HAL_WWDG_STATE_READY = 0x01U, /*!< WWDG initialized and ready for use */ + HAL_WWDG_STATE_BUSY = 0x02U, /*!< WWDG internal process is ongoing */ + HAL_WWDG_STATE_TIMEOUT = 0x03U, /*!< WWDG timeout state */ + HAL_WWDG_STATE_ERROR = 0x04U /*!< WWDG error state */ }HAL_WWDG_StateTypeDef; /** @@ -140,7 +140,7 @@ typedef struct /* --- CFR Register ---*/ /* Alias word address of EWI bit */ -#define WWDG_CFR_BASE (uint32_t)(WWDG_BASE + 0x04) +#define WWDG_CFR_BASE (uint32_t)(WWDG_BASE + 0x04U) /** * @} @@ -166,7 +166,7 @@ typedef struct /** @defgroup WWDG_Prescaler WWDG Prescaler * @{ */ -#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define WWDG_PRESCALER_1 ((uint32_t)0x00000000U) /*!< WWDG counter clock = (PCLK1/4096)/1 */ #define WWDG_PRESCALER_2 ((uint32_t)WWDG_CFR_WDGTB0) /*!< WWDG counter clock = (PCLK1/4096)/2 */ #define WWDG_PRESCALER_4 ((uint32_t)WWDG_CFR_WDGTB1) /*!< WWDG counter clock = (PCLK1/4096)/4 */ #define WWDG_PRESCALER_8 ((uint32_t)WWDG_CFR_WDGTB) /*!< WWDG counter clock = (PCLK1/4096)/8 */ @@ -181,10 +181,10 @@ typedef struct /* Check for window */ -#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F) +#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7FU) /* Check for counter */ -#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F)) +#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40U) && ((__COUNTER__) <= 0x7FU)) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L0/serial_api.c b/targets/TARGET_STM/TARGET_STM32L0/serial_api.c index 26d5bafee4..f947b4d645 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/serial_api.c +++ b/targets/TARGET_STM/TARGET_STM32L0/serial_api.c @@ -825,10 +825,10 @@ void serial_tx_abort_asynch(serial_t *obj) // reset states huart->TxXferCount = 0; // update handle state - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) { - huart->State = HAL_UART_STATE_BUSY_RX; + if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) { + huart->gState = HAL_UART_STATE_BUSY_RX; } else { - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; } } @@ -855,10 +855,10 @@ void serial_rx_abort_asynch(serial_t *obj) // reset states huart->RxXferCount = 0; // update handle state - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) { - huart->State = HAL_UART_STATE_BUSY_TX; + if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) { + huart->RxState = HAL_UART_STATE_BUSY_TX; } else { - huart->State = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; } }