ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #3009 from pradeep-gr/master 

TRNG enabled. TRNG APIs implemented. REV A/B/C/D flags removed. Warnings removed
pull/3158/head
Martin Kojtal 2016-10-28 10:13:50 +02:00 committed by GitHub
parent f33088b7e4 bb824c6f91
commit 6eac2b008a
26 changed files with 271 additions and 503 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
targets/TARGET_ONSEMI/TARGET_NCS36510/Pad.c
View File

@ -1,4 +1,3 @@
#ifdef REVD
/**
******************************************************************************
* @file pad.c
@ -83,20 +82,20 @@ void fPadInit()
PADREG->PADIO1.WORD = PAD_INPUT_PD_L1_PP; /* UART1 RXD */
PADREG->PADIO2.WORD = PAD_INPUT_PD_L1_PP; /* UART1 CTS */
PADREG->PADIO3.WORD = PAD_OUTPUT_PN_L1_OD; /* UART1 RTS */
PADREG->PADIO4.WORD = PAD_UNUSED_PD_L0_PP;
PADREG->PADIO5.WORD = PAD_UNUSED_PD_L0_PP;
PADREG->PADIO6.WORD = PAD_UNUSED_PD_L0_PP;
PADREG->PADIO7.WORD = PAD_UNUSED_PD_L0_PP;
PADREG->PADIO4.WORD = PAD_UNUSED_PD_L1_PP;
PADREG->PADIO5.WORD = PAD_UNUSED_PD_L1_PP;
PADREG->PADIO6.WORD = PAD_UNUSED_PD_L1_PP;
PADREG->PADIO7.WORD = PAD_UNUSED_PD_L1_PP;
PADREG->PADIO8.WORD = PAD_OUTPUT_PN_L1_OD; /* UART2 TXD */
PADREG->PADIO9.WORD = PAD_INPUT_PD_L1_PP; /* UART2 RXD */
PADREG->PADIO10.WORD = PAD_UNUSED_PD_L0_PP;
PADREG->PADIO10.WORD = PAD_UNUSED_PD_L1_PP;
PADREG->PADIO11.WORD = PAD_INPUT_PD_L1_PP; /* SWO */
PADREG->PADIO12.WORD = PAD_INPUT_PD_L1_PP; /* SWCLK */
PADREG->PADIO13.WORD = PAD_INPUT_PD_L1_PP; /* SWDIO */
PADREG->PADIO14.WORD = PAD_INPUT_PD_L1_PP;
PADREG->PADIO15.WORD = PAD_UNUSED_PD_L0_PP;
PADREG->PADIO16.WORD = PAD_UNUSED_PD_L0_PP;
PADREG->PADIO17.WORD = PAD_UNUSED_PD_L0_PP;
PADREG->PADIO15.WORD = PAD_UNUSED_PD_L1_PP;
PADREG->PADIO16.WORD = PAD_UNUSED_PD_L1_PP;
PADREG->PADIO17.WORD = PAD_UNUSED_PD_L1_PP;
/** - Disable the clock for PAD peripheral device */
CLOCK_DISABLE(CLOCK_PAD);
@ -142,5 +141,4 @@ boolean fPadIOCtrl(uint8_t PadNum, uint8_t OutputDriveStrength, uint8_t OutputDr
}
/* Invalid parameter/s */
return False;
}
#endif /* REVD */
}

60
targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/startup_NCS36510.s
View File

@ -157,153 +157,153 @@ Reset_Handler
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
; PUBWEAK HardFault_Handler
; SECTION .text:CODE:REORDER(1)
; SECTION .text:CODE:REORDER:NOROOT(1)
;HardFault_Handler
; B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
; PUBWEAK vPortSVCHandler
; SECTION .text:CODE:REORDER(1)
; SECTION .text:CODE:REORDER:NOROOT(1)
;vPortSVCHandler
; B vPortSVCHandler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
; PUBWEAK xPortPendSVHandler
; SECTION .text:CODE:REORDER(1)
; SECTION .text:CODE:REORDER:NOROOT(1)
;xPortPendSVHandler
; B xPortPendSVHandler
; PUBWEAK SysTick_Handler
; SECTION .text:CODE:REORDER(1)
; SECTION .text:CODE:REORDER:NOROOT(1)
;SysTick_Handler
; B SysTick_Handler
; PUBWEAK fIrqTim0Handler
; SECTION .text:CODE:REORDER(1)
; SECTION .text:CODE:REORDER:NOROOT(1)
;fIrqTim0Handler
; B fIrqTim0Handler
; PUBWEAK fIrqTim1Handler
; SECTION .text:CODE:REORDER(1)
; SECTION .text:CODE:REORDER:NOROOT(1)
;fIrqTim1Handler
; B fIrqTim1Handler
; PUBWEAK fIrqTim2Handler
; SECTION .text:CODE:REORDER(1)
; SECTION .text:CODE:REORDER:NOROOT(1)
;fIrqTim2Handler
; B fIrqTim2Handler
; PUBWEAK fIrqUart1Handler
; SECTION .text:CODE:REORDER(1)
; SECTION .text:CODE:REORDER:NOROOT(1)
;fIrqUart1Handler
; B fIrqUart1Handler
; PUBWEAK fIrqSpiHandler
; SECTION .text:CODE:REORDER(1)
; SECTION .text:CODE:REORDER:NOROOT(1)
;fIrqSpiHandler
; B fIrqSpiHandler
PUBWEAK fIrqI2CHandler
SECTION .text:CODE:REORDER(1)
SECTION .text:CODE:REORDER:NOROOT(1)
fIrqI2CHandler
B fIrqI2CHandler
; PUBWEAK fIrqGpioHandler
; SECTION .text:CODE:REORDER(1)
; SECTION .text:CODE:REORDER:NOROOT(1)
;fIrqGpioHandler
; B fIrqGpioHandler
PUBWEAK fIrqRtcHandler
SECTION .text:CODE:REORDER(1)
SECTION .text:CODE:REORDER:NOROOT(1)
fIrqRtcHandler
B fIrqRtcHandler
PUBWEAK fIrqFlashHandler
SECTION .text:CODE:REORDER(1)
SECTION .text:CODE:REORDER:NOROOT(1)
fIrqFlashHandler
B fIrqFlashHandler
PUBWEAK fIrqMacHwHandler
SECTION .text:CODE:REORDER(1)
SECTION .text:CODE:REORDER:NOROOT(1)
fIrqMacHwHandler
B fIrqMacHwHandler
PUBWEAK fIrqAesHandler
SECTION .text:CODE:REORDER(1)
SECTION .text:CODE:REORDER:NOROOT(1)
fIrqAesHandler
B fIrqAesHandler
PUBWEAK fIrqAdcHandler
SECTION .text:CODE:REORDER(1)
SECTION .text:CODE:REORDER:NOROOT(1)
fIrqAdcHandler
B fIrqAdcHandler
PUBWEAK fIrqClockCalHandler
SECTION .text:CODE:REORDER(1)
SECTION .text:CODE:REORDER:NOROOT(1)
fIrqClockCalHandler
B fIrqClockCalHandler
; PUBWEAK fIrqUart2Handler
; SECTION .text:CODE:REORDER(1)
; SECTION .text:CODE:REORDER:NOROOT(1)
;fIrqUart2Handler
; B fIrqUart2Handler
PUBWEAK fIrqDbgPwrUpHandler
SECTION .text:CODE:REORDER(1)
SECTION .text:CODE:REORDER:NOROOT(1)
fIrqDbgPwrUpHandler
B fIrqDbgPwrUpHandler
PUBWEAK fIrqDmaHandler
SECTION .text:CODE:REORDER(1)
SECTION .text:CODE:REORDER:NOROOT(1)
fIrqDmaHandler
B fIrqDmaHandler
PUBWEAK fIrqUviHandler
SECTION .text:CODE:REORDER(1)
SECTION .text:CODE:REORDER:NOROOT(1)
fIrqUviHandler
B fIrqUviHandler
PUBWEAK fIrqSpi2Handler
SECTION .text:CODE:REORDER(1)
SECTION .text:CODE:REORDER:NOROOT(1)
fIrqSpi2Handler
B fIrqSpi2Handler
PUBWEAK fIrqI2c2Handler
SECTION .text:CODE:REORDER(1)
SECTION .text:CODE:REORDER:NOROOT(1)
fIrqI2c2Handler
B fIrqI2c2Handler
PUBWEAK FIrqFVDDHCompHandler
SECTION .text:CODE:REORDER(1)
SECTION .text:CODE:REORDER:NOROOT(1)
FIrqFVDDHCompHandler
B FIrqFVDDHCompHandler
PUBWEAK DEF_IRQHandler
SECTION .text:CODE:REORDER(1)
SECTION .text:CODE:REORDER:NOROOT(1)
DEF_IRQHandler
B DEF_IRQHandler

2
targets/TARGET_ONSEMI/TARGET_NCS36510/device/system_NCS36510.c
View File

@ -23,7 +23,7 @@
******************************************************************************/
#include <NCS36510.h>
//#include "ncs36510Init.h" /* TODO */
#include "ncs36510Init.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/

14
targets/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h
View File

@ -47,19 +47,6 @@
**************************************************************************************************/
/** DMA control HW registers structure overlay */
#ifdef REVB
typedef struct {
__IO uint32_t CONTROL; /**< Write 1 to enable DMA, write 0 to disable */
__IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */
__IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */
__IO uint32_t SIZE; /**< Lenght of the entire transfer */
__IO uint32_t STATUS; /**< To be debined */
__IO uint32_t INT_ENABLE; /**< Enable interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
__IO uint32_t INT_CLEAR_ENABLE; /**< Clear Interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
__I uint32_t INT_STATUS; /**< Current interrupt status. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
} DmaReg_t, *DmaReg_pt;
#endif /* REVB */
#ifdef REVD
typedef struct {
union {
struct {
@ -104,5 +91,4 @@ typedef struct {
__I uint32_t WORD;
} INT_STATUS; /**< Interrupt status */
} DmaReg_t, *DmaReg_pt;
#endif /* REVD */
#endif /* DMA_MAP_H_ */

16
targets/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h
View File

@ -131,9 +131,7 @@ typedef struct {
__O uint32_t FS:1;
__O uint32_t FP:1;
__O uint32_t FMD:1;
#ifdef REVD
__I uint32_t PC:1;
#endif /* REVD */
} BITS;
__O uint32_t WORD;
} CLEAR_IRQ; /**< 0x40014030 */
@ -145,9 +143,7 @@ typedef struct {
__IO uint32_t FS:1;
__IO uint32_t FP:1;
__IO uint32_t FM:1;
#ifdef REVD
__I uint32_t PC:1;
#endif /* REVD */
} BITS;
__IO uint32_t WORD;
} MASK_IRQ; /**< 0x40014034 */
@ -159,9 +155,7 @@ typedef struct {
__I uint32_t FS:1;
__I uint32_t FP:1;
__I uint32_t FM:1;
#ifdef REVD
__I uint32_t PC:1;
#endif /* REVD */
} BITS;
__I uint32_t WORD;
} IRQ_STATUS; /**< 0x40014038 */
@ -202,9 +196,6 @@ typedef struct {
__IO uint32_t WORD;
} SLOT_OFFSET; /**< 0x40014064 */
__I uint32_t TIME_STAMP; /**< 0x40014068 */
#ifdef REVB
__O uint32_t PAD5; /**< 0x4001406C */
#endif /* REVB */
union {
struct {
__IO uint32_t CRD_SHORT_ADDRESS:16;
@ -214,17 +205,10 @@ typedef struct {
__IO uint32_t PAN_COORD_ADDR_S:1;
} BITS;
__IO uint32_t WORD;
#ifdef REVB
} CRD_SHORT_ADDR; /**< 0x40014070 */
__IO uint32_t CRD_LONG_ADDR_HI; /**< 0x40014074 */
__IO uint32_t CRD_LONG_ADDR_LO; /**< 0x40014078 */
#endif /* REVB */
#ifdef REVD
} CRD_SHORT_ADDR; /**< 0x4001406C */
__IO uint32_t CRD_LONG_ADDR_HI; /**< 0x40014070 */
__IO uint32_t CRD_LONG_ADDR_LO; /**< 0x40014074 */
__O uint32_t PAD5; /**< 0x40014078 */
#endif /* REVD */
__O uint32_t PAD9; /**< 0x4001407C */
__O uint32_t PAD10; /**< 0x40014080 */
__O uint32_t PAD11; /**< 0x40014084 */

42
targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_trng.h Normal file
View File

@ -0,0 +1,42 @@
/**
******************************************************************************
* @file ncs36510_trng.h
* @brief Header file for ncs36510_trng_api.c.
* @internal
* @author ON Semiconductor.
* $Rev: $
* $Date: $
******************************************************************************
* Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
* All rights reserved. This software and/or documentation is licensed by ON Semiconductor
* under limited terms and conditions. The terms and conditions pertaining to the software
* and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
* (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
* if applicable the software license agreement. Do not use this software and/or
* documentation unless you have carefully read and you agree to the limited terms and
* conditions. By using this software and/or documentation, you agree to the limited
* terms and conditions.
*
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* @endinternal
*
* @ingroup TRNG header
*
*/
#ifndef RANDOM_H_
#define RANDOM_H_
#define TRNG_SLOW_MODE 0
#define TRNG_FAST_MODE 1
#define TRNG_DISABLE 0
#define TRNG_ENABLE 1
#define TRNG_ON_READ_EVENT 1
#endif /* RANDOM_H_ */

113
targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_trng_api.c Normal file
View File

@ -0,0 +1,113 @@
/**
******************************************************************************
* @file trng_api.c
* @brief Implementation of TRNG functionality.
* @internal
* @author ON Semiconductor.
* $Rev: $
* $Date: $
******************************************************************************
* Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
* All rights reserved. This software and/or documentation is licensed by ON Semiconductor
* under limited terms and conditions. The terms and conditions pertaining to the software
* and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
* (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
* if applicable the software license agreement. Do not use this software and/or
* documentation unless you have carefully read and you agree to the limited terms and
* conditions. By using this software and/or documentation, you agree to the limited
* terms and conditions.
*
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* @endinternal
*
* @ingroup TRNG
*
*/
#if DEVICE_TRNG
/*************************************************************************************************
* *
* Header files *
* *
*************************************************************************************************/
#include "trng_api.h"
#include "memory_map.h"
#include "ncs36510_trng.h"
#include "clock.h"
#include "wait_api.h"
/*************************************************************************************************
* *
* Functions *
* *
*************************************************************************************************/
void trng_init(trng_t *obj)
{
/* Enable TRNG */
CLOCK_ENABLE(CLOCK_RAND);
/* Initialize TRNG */
RANDREG->CONTROL.WORD = False;
return;
}
void trng_free(trng_t *obj)
{
/* Stop TRNG */
RANDREG->CONTROL.WORD = False;
/* Disable TRNG */
CLOCK_DISABLE(CLOCK_RAND);
return;
}
int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
{
uint32_t MSLRandom = 0, Index, TempLen, *TempPtr = (uint32_t*)output;
RANDREG->CONTROL.BITS.METASTABLE_LATCH_EN = TRNG_ENABLE; /* ENable MSL TRNG */
RANDREG->CONTROL.BITS.MEATSTABLE_SPEED = TRNG_FAST_MODE; /* Meta-stable Latch TRNG Speed Control */
RANDREG->CONTROL.BITS.MODE = TRNG_ON_READ_EVENT; /* TRNG is only updated on a read event of the TRNG register */
wait_us(1); /* Wait till MSL generates random number after enable for the first time */
TempLen = length / 4;
for(Index = 0; Index < TempLen; Index++)
{
MSLRandom = RANDREG->METASTABLE_LATCH_VAL;
*TempPtr++ = MSLRandom ;
}
TempLen = length % 4;
Index *= 4;
if(TempLen-- > 0)
{
MSLRandom = RANDREG->METASTABLE_LATCH_VAL;
*(output + Index++) = (MSLRandom >> 0) & 0xFF;
if(TempLen-- > 0)
{
*(output + Index++) = (MSLRandom >> 8) & 0xFF;
if(TempLen-- > 0)
{
*(output + Index++) = (MSLRandom >> 16) & 0xFF;
}
}
}
RANDREG->CONTROL.BITS.METASTABLE_LATCH_EN = TRNG_DISABLE; /* Disable MSL */
*output_length = Index;
return 0; /* Success */
}
#endif /* DEVICE_TRNG */

6
targets/TARGET_ONSEMI/TARGET_NCS36510/objects.h
View File

@ -169,7 +169,7 @@ struct spi_s {
uint8_t rxWatermark; /* Receive FIFO Watermark: Defines level of TX Half Full Flag:
* - Value between 1 and 15
* * (unused option in current implementation / rxWatermark fixed to 1) */
spi_ipc7207_endian_t endian; /* Bits endianness:
spi_ipc7207_endian_t endian; /* Bits endianness:
* - LITTLE_ENDIAN = LSB first
* - BIG_ENDIAN = MSB first */
uint8_t samplingEdge; /* SDI sampling edge (relative to SDO sampling edge):
@ -193,6 +193,10 @@ struct i2c_s {
//queue_pt rxQueue; /**< The receive queue for the device instance. */
};
struct trng_s {
RandReg_pt membase; /**< The memory base for the device's registers. */
};
#ifdef __cplusplus
}
#endif

4
targets/TARGET_ONSEMI/TARGET_NCS36510/pad.h
View File

@ -1,4 +1,3 @@
#ifdef REVD
/**
******************************************************************************
* @file pad.h
@ -84,5 +83,4 @@ extern void fPadInit();
*/
extern boolean fPadIOCtrl(uint8_t, uint8_t, uint8_t, uint8_t);
#endif //_PAD_H_
#endif /* REVD */
#endif //_PAD_H_

4
targets/TARGET_ONSEMI/TARGET_NCS36510/pad_map.h
View File

@ -71,14 +71,12 @@
#define PAD_LOW_POWER (PAD_PULL_NONE | (PAD_DRIVE_L0<<2) | (PAD_OOUTCFG_OPENDRAIN<<5))
/** custom Power PAD configuration */
#ifdef REVD
#define PAD_OUTPUT_PN_L1_OD (PAD_PULL_NONE | (PAD_DRIVE_L1<<2) | (PAD_OOUTCFG_OPENDRAIN<<5))
#define PAD_INPUT_PD_L1_PP (PAD_PULL_DOWN | (PAD_DRIVE_L1<<2) | (PAD_OUTCFG_PUSHPULL<<5))
#define PAD_UNUSED_PD_L0_PP (PAD_PULL_DOWN | (PAD_DRIVE_L0<<2) | (PAD_OUTCFG_PUSHPULL<<5))
#define PAD_UNUSED_PD_L1_PP (PAD_PULL_DOWN | (PAD_DRIVE_L1<<2) | (PAD_OUTCFG_PUSHPULL<<5))
#define PAD_UART_TX (PAD_PULL_UP | (PAD_DRIVE_L1<<2) | (PAD_OUTCFG_PUSHPULL<<5))
#define PAD_UART_RX (PAD_PULL_UP | (PAD_DRIVE_L1<<2) | (PAD_OOUTCFG_OPENDRAIN<<5))
#endif /* REVD */
/**************************************************************************************************
* *

2
targets/TARGET_ONSEMI/TARGET_NCS36510/port_api.c
View File

@ -24,7 +24,9 @@
* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*/
#include "gpio.h"
#include "gpio_api.h"
#include "port_api.h"
#include "pinmap.h"
#if DEVICE_PORTIN || DEVICE_PORTOUT

32
targets/TARGET_ONSEMI/TARGET_NCS36510/pwm_map.h
View File

@ -44,37 +44,6 @@
#include "architecture.h"
/** Power management Control HW Structure Overlay */
#ifdef REVB
typedef struct {
__IO uint32_t DUTYCYCLE;
union {
struct {
__IO uint32_t ENABLED :1;/**< 1 = PWM enable , 0 = PWM disable */
__I uint32_t CURRENT :1;/**< current state of PWM enable signal */
__O uint32_t PAD1 :6; /**< Reserved. Writes have no effect; Read as 0x00. */
__O uint32_t RDPWMEN :1;/**< current state of pwmEnable configuration */
__O uint32_t RDPWMOP :1;/**< current state of PWM out signal */
__O uint32_t PAD2 :6; /**< Reserved. Writes have no effect; Read as 0x00. */
} BITS;
__I uint32_t WORD;
} PWMOUT;
__O uint32_t DISABLE;
union {
struct {
__IO uint32_t ENABLED :1;
__O uint32_t PAD1 :7; /**< Reserved. Writes have no effect */
__O uint32_t STATE :1; /**< current state of prescaler enable configuration. */
__O uint32_t PAD2 :7; /**< Reserved. Writes have no effect; Read as 0x00. */
} BITS;
__I uint32_t WORD;
} PRESCALE_EN;
__O uint32_t PRESCALE_DIS;
} PwmReg_t, *PwmReg_pt;
#endif /* REVB */
#ifdef REVD
typedef struct {
__IO uint32_t DUTYCYCLE;
union {
@ -96,5 +65,4 @@ typedef struct {
} PRESCALE_ENABLE;
__O uint32_t PRESCALE_DISABLE;
} PwmReg_t, *PwmReg_pt;
#endif /* REVD */
#endif /* PWM_MAP_H_ */

3
targets/TARGET_ONSEMI/TARGET_NCS36510/random_map.h
View File

@ -49,9 +49,6 @@
/** Random Number Generator Control HW Structure Overlay */
typedef struct {
__IO uint32_t WR_SEED_RD_RAND; /* Seed set & random read reg - 0x40011000 */
#ifdef REVB
__IO uint32_t MODE;
#endif /* REVB */
union {
struct {
__IO uint32_t MODE :1; /**<Mode Register, 0 – LSFR is updated on every rising edge of PCLK, 1 – LSFR is only updated on a read event of the LSFR register */

123
targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c
View File

@ -41,10 +41,6 @@
#include "rfAna.h"
#include "clock.h"
#ifdef REVA
#include "test.h"
#endif
/*************************************************************************************************
* *
* Global variables *
@ -78,7 +74,6 @@
*/
// RR: Making high side injection changes to RevD
#ifdef REVD
/** This rf LUT is built for high side injection, using low side injection
* would requiere to change this LUT. */
@ -107,93 +102,6 @@ const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
13,14,15,16,17,18,19,20,20,20
}; // +1dBm to +10 dBm
#endif /* REVD */
#ifdef REVC
/** This rf LUT is built for low side injection, using high side injection
* would requiere to change this LUT. */
const uint32_t rfLut[16][4] = {{0x47,0xFF15FC,0x4B,0x00A000},
{0x47,0xFFAC93,0x4B,0x014001},
{0x47,0x00432A,0x4B,0x01E001},
{0x47,0x00D9C1,0x4C,0xFE7FFF},
{0x47,0x017058,0x4C,0xFF1FFF},
{0x48,0xFE06EC,0x4C,0xFFC000},
{0x48,0xFE9D83,0x4C,0x006000},
{0x48,0xFF341A,0x4C,0x010001},
{0x48,0xFFCAB1,0x4C,0x01A001},
{0x48,0x006148,0x4D,0xFE3FFF},
{0x48,0x00F7DF,0x4D,0xFEDFFF},
{0x48,0x018E76,0x4D,0xFF8000},
{0x49,0xFE250A,0x4D,0x002000},
{0x49,0xFEBBA1,0x4D,0x00C001},
{0x49,0xFF5238,0x4D,0x016001},
{0x49,0xFFE8CF,0x4E,0xFDFFFE}
};
const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
0,0,0,0,0,0,1,1,2,2, // -19dBm to -10dBm (clamp low at -14dB)
3,3,4,6,7,9,10,12,13,15, // -9dBm to 0dBm
17,19,20,20,20,20,20,20,20,20
}; // +1dBm to +10 dBm (clamp high at +3dB)
#endif /* REVC */
#ifdef REVB
/** This rf LUT is built for low side injection, using high side injection
* would requiere to change this LUT. */
const uint32_t rfLut[16][4] = {{0x47,0xFF15FC,0x4B,0x00A000},
{0x47,0xFFAC93,0x4B,0x014001},
{0x47,0x00432A,0x4B,0x01E001},
{0x47,0x00D9C1,0x4C,0xFE7FFF},
{0x47,0x017058,0x4C,0xFF1FFF},
{0x48,0xFE06EC,0x4C,0xFFC000},
{0x48,0xFE9D83,0x4C,0x006000},
{0x48,0xFF341A,0x4C,0x010001},
{0x48,0xFFCAB1,0x4C,0x01A001},
{0x48,0x006148,0x4D,0xFE3FFF},
{0x48,0x00F7DF,0x4D,0xFEDFFF},
{0x48,0x018E76,0x4D,0xFF8000},
{0x49,0xFE250A,0x4D,0x002000},
{0x49,0xFEBBA1,0x4D,0x00C001},
{0x49,0xFF5238,0x4D,0x016001},
{0x49,0xFFE8CF,0x4E,0xFDFFFE}
};
const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
0,0,0,0,0,0,1,1,2,2, // -19dBm to -10dBm (clamp low at -14dB)
3,3,4,6,7,9,10,12,13,15, // -9dBm to 0dBm
17,19,20,20,20,20,20,20,20,20
}; // +1dBm to +10 dBm (clamp high at +3dB)
#endif
#ifdef REVA
const uint32_t rfLut[16][4] = {{0x57,0xFF5D2F,0x51,0x018001},
{0x57,0x0007DA,0x52,0xFE1FFF},
{0x57,0x00B285,0x52,0xFEBFFF},
{0x57,0x015D30,0x52,0xFF6000},
{0x58,0xFE07D8,0x52,0x000000},
{0x58,0xFEB283,0x52,0x00A000},
{0x58,0xFF5D2F,0x52,0x014001},
{0x58,0x0007DA,0x52,0x01E001},
{0x58,0x00B285,0x53,0xFE7FFF},
{0x58,0x015D30,0x53,0xFF1FFF},
{0x59,0xFE07D8,0x53,0xFFC000},
{0x59,0xFEB283,0x53,0x006000},
{0x59,0xFF5D2F,0x53,0x010001},
{0x59,0x0007DA,0x53,0x01A001},
{0x59,0x00B285,0x53,0xFE3FFF},
{0x59,0x015D30,0x53,0xFEDFFF}
};
const uint8_t txPowerLut[43] = {1,2,3, // -32dBm to -30dBm
4,5,5,5,5,5,5,5,5,5, // -29dBm to -20dBm (clamp at -28dB)
5,5,5,5,5,5,5,5,5,5, // -19dBm to -10dBm
5,5,5,5,5,5,5,5,5,5, // -9dBm to 0dBm
5,5,5,5,5,5,5,5,5,5
}; // +1dBm to +10 dBm
#endif
/*************************************************************************************************
* *
* Functions *
@ -205,13 +113,6 @@ void fRfAnaInit()
// Enable rfana clock
CLOCK_ENABLE(CLOCK_RFANA);
#ifdef REVA
// Force Pll lock (it shouldn't be needed for either silicon if the part is configured/trimmed properly)
fTestForcePllLock();
// Bypass Pll regulator
fTestBypassPllReg();
#endif
// Set PLL timing
RFANAREG->PLL_TIMING.BITS.PLL_RESET_TIME = 0x1E; // 30us
RFANAREG->PLL_TIMING.BITS.PLL_LOCK_TIME = 0x2F; // 47us
@ -239,29 +140,6 @@ boolean fRfAnaIoctl (uint32_t request, void *argument)
RFANAREG->RX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][0];
// Set tx/rx vco trims
#ifdef REVB
/** REVB is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
* from trims stored in flash A, it has the drawback that it is not workable when flash A is not accessible.*/
if (channel < 19) {
RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (TRIMREG->TX_VCO_LUT1.WORD) >> ((channel - 11) * 4);
RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (TRIMREG->RX_VCO_LUT1.WORD) >> ((channel - 11) * 4);
} else {
RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (TRIMREG->TX_VCO_LUT2.WORD) >> ((channel - 19) * 4);
RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (TRIMREG->RX_VCO_LUT2.WORD) >> ((channel - 19) * 4);
}
#endif /* REVB */
#ifdef REVC
/** REVC is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
* from trims stored in dedicated registers available in digital.*/
if (channel < 19) {
RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
} else {
RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
}
#endif /* REVC */
#ifdef REVD
/** REVD is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
* from trims stored in dedicated registers available in digital.*/
if (channel < 19) {
@ -271,7 +149,6 @@ boolean fRfAnaIoctl (uint32_t request, void *argument)
RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
}
#endif /* REVD */
break;
case SET_TX_POWER:
txPower = *(uint8_t*)argument;

10
targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna_map.h
View File

@ -105,21 +105,11 @@ typedef struct {
} PLL_TRIM;
__IO uint32_t PLL_VCO_TAP_LOCATION;
__IO uint32_t TX_CHAIN_TRIM;
#ifdef REVC
__IO uint32_t RX_VCO_TRIM_LUT2; /** 0x40019098 */
__IO uint32_t RX_VCO_TRIM_LUT1; /** 0x4001909C */
__IO uint32_t TX_VCO_TRIM_LUT2; /** 0x400190A0 */
__IO uint32_t TX_VCO_TRIM_LUT1; /** 0x400190A4 */
__IO uint32_t ADC_OFFSET_BUF; /** 0x400190A8 */
#endif
#ifdef REVD
__IO uint32_t RX_VCO_TRIM_LUT2; /** 0x40019098 */
__IO uint32_t RX_VCO_TRIM_LUT1; /** 0x4001909C */
__IO uint32_t TX_VCO_TRIM_LUT2; /** 0x400190A0 */
__IO uint32_t TX_VCO_TRIM_LUT1; /** 0x400190A4 */
__IO uint32_t ADC_OFFSET_BUF; /** 0x400190A8 */
#endif /* REVD */
} RfAnaTrimReg_t, *RfAnaTrimReg_pt;
#endif /* RFANA_MAP_H_ */

50
targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c
View File

@ -43,6 +43,7 @@
*/
#include "rtc.h"
#include "mbed_assert.h"
#include "lp_ticker_api.h"
static uint16_t SubSecond;
static uint64_t LastRtcTimeus;
@ -100,7 +101,7 @@ void fRtcFree(void)
void fRtcSetInterrupt(uint32_t timestamp)
{
SubSecond = False;
uint32_t Second = False;
uint32_t Second = False, EnableInterrupt = False;
uint8_t DividerAdjust = 1;
if(timestamp) {
@ -110,7 +111,7 @@ void fRtcSetInterrupt(uint32_t timestamp)
RTCREG->SECOND_ALARM = Second; /* Write to alarm register */
/* Enable second interrupt */
RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
EnableInterrupt = True << RTC_CONTROL_SEC_CNT_INT_BIT_POS;
}
timestamp = timestamp - Second * RTC_SEC_TO_US; /* Take out micro second for sub second alarm */
if(timestamp > False) {
@ -129,7 +130,6 @@ void fRtcSetInterrupt(uint32_t timestamp)
SubSecond = 0;
}
if(SubSecond > False) {
/* Second interrupt not enabled */
@ -137,12 +137,18 @@ void fRtcSetInterrupt(uint32_t timestamp)
RTCREG->SUB_SECOND_ALARM = SubSecond; /* Write to sub second alarm */
/* Enable sub second interrupt */
while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
EnableInterrupt |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
}
}
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
RTCREG->CONTROL.WORD |= EnableInterrupt;
/* Enable RTC interrupt */
NVIC_EnableIRQ(Rtc_IRQn);
/* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
while((RTCREG->STATUS.WORD & ((True << RTC_STATUS_SUB_SEC_ALARM_WRT_BIT_POS) |
(True << RTC_STATUS_SEC_ALARM_WRT_BIT_POS) |
(True << RTC_STATUS_CONTROL_WRT_BIT_POS))) == True);
}
return;
}
@ -150,17 +156,15 @@ void fRtcSetInterrupt(uint32_t timestamp)
/* See rtc.h for details */
void fRtcDisableInterrupt(void)
{
/* Disable subsec/sec interrupt */
RTCREG->CONTROL.WORD &= ~((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
/* Disable RTC interrupt */
NVIC_DisableIRQ(Rtc_IRQn);
}
/* See rtc.h for details */
void fRtcEnableInterrupt(void)
{
/* Disable subsec/sec interrupt */
RTCREG->CONTROL.WORD |= ((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
/* Enable RTC interrupt */
NVIC_EnableIRQ(Rtc_IRQn);
}
/* See rtc.h for details */
@ -170,7 +174,9 @@ void fRtcClearInterrupt(void)
/* Clear sec & sub_sec interrupts */
RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
(True << RTC_INT_CLR_SEC_BIT_POS));
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
while((RTCREG->STATUS.WORD & ((True << RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS) |
(True << RTC_STATUS_SEC_INT_CLR_WRT_BIT_POS))) == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
}
/* See rtc.h for details */
@ -191,9 +197,9 @@ uint64_t fRtcRead(void)
*/
do {
Second = RTCREG->SECOND_COUNTER; /* Get SEC_COUNTER reg value */
SubSecond = (RTCREG->SUB_SECOND_COUNTER - 1) & 0x7FFF; /* Get SUB_SEC_COUNTER reg value */
} while (Second != RTCREG->SECOND_COUNTER); /* Repeat if the second has changed */
Second = RTCREG->SECOND_COUNTER; /* Get SEC_COUNTER reg value */
SubSecond = (RTCREG->SUB_SECOND_COUNTER - 1) & SUB_SEC_MASK; /* Get SUB_SEC_COUNTER reg value */
} while (Second != RTCREG->SECOND_COUNTER); /* Repeat if the second has changed */
//note: casting to float removed to avoid reduction in resolution
uint64_t RtcTimeus = ((uint64_t)SubSecond * RTC_SEC_TO_US / RTC_CLOCK_HZ) + ((uint64_t)Second * RTC_SEC_TO_US);
@ -208,8 +214,8 @@ uint64_t fRtcRead(void)
/* See rtc.h for details */
void fRtcWrite(uint64_t RtcTimeus)
{
uint32_t Second = 0;
uint16_t SubSecond = 0;
uint32_t Second = False;
uint16_t SubSecond = False;
/* Stop RTC */
RTCREG->CONTROL.WORD &= ~((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
(True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
@ -270,7 +276,11 @@ void fRtcHandler(void)
NVIC_EnableIRQ(Rtc_IRQn);
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
/* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
while((RTCREG->STATUS.WORD & ((True << RTC_STATUS_SUB_SEC_ALARM_WRT_BIT_POS) |
(True << RTC_STATUS_CONTROL_WRT_BIT_POS) |
(True << RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS) |
(True << RTC_STATUS_SEC_INT_CLR_WRT_BIT_POS))) == True);
lp_ticker_irq_handler();
}

6
targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.h
View File

@ -52,9 +52,15 @@
#define RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS 2
#define RTC_CONTROL_SEC_CNT_INT_BIT_POS 3
#define RTC_STATUS_SUB_SEC_ALARM_WRT_BIT_POS 6
#define RTC_STATUS_SEC_ALARM_WRT_BIT_POS 7
#define RTC_STATUS_CONTROL_WRT_BIT_POS 8
#define RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS 9
#define RTC_STATUS_SEC_INT_CLR_WRT_BIT_POS 10
#define SUB_SEC_MASK 0x7FFF
/* FUnction pointer for call back */
typedef void (* fRtcCallBack)(void);

2
targets/TARGET_ONSEMI/TARGET_NCS36510/rtc_api.c
View File

@ -39,8 +39,6 @@
#include "rtc.h"
#include "cmsis_nvic.h"
static IRQn_Type Irq;
/* See rtc_apc.h for description */
void rtc_init(void)

67
targets/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h
View File

@ -45,72 +45,6 @@
/** Real Time Clock Control HW Structure Overlay */
typedef struct {
#ifdef REVB
/*REVD REPLACE COMPLETE MAP WITH DATA FROM DIG DESIGN SPEC */
__IO uint32_t SECOND;/**<SECOND Counter */
__IO uint32_t MINUTE;/**<DAY Counter */
__IO uint32_t HOUR;/**< HOUR Counter */
__IO uint32_t DAY;/**< DAY Counter */
__IO uint32_t MONTH;/**< MONTH Counter */
__IO uint32_t YEAR;/**< YEAR Counter */
union {
struct {
__IO uint32_t PAD1 :1;/**<Reserved; Writes have no effect. Read as 0 */
__IO uint32_t TEST_MINUTE :1;/**<0 = normal operation , 1 = Test Mode */
__IO uint32_t TEST_HOUR :1;/**<0 = normal operation , 1 = Test Mode */
__IO uint32_t TEST_DAY :1;/**<0 = normal operation , 1 = Test Mode */
__IO uint32_t TEST_MONTH :1;/**<0 = normal operation , 1 = Test Mode */
__IO uint32_t TEST_YEAR :1;/**<0 = normal operation , 1 = Test Mode */
__IO uint32_t PAD2 :1;/**<Reserved; Writes have no effect. Read as 0 */
__IO uint32_t RESET :1;/**< 0 = counters are incrementing , 1 = counters are in reset */
} BITS;
__IO uint32_t WORD;
} CONTROL;
__IO uint32_t DIVISOR;/**<Clock Divisor value */
__IO uint32_t ALARM_SECOND;/**<SECOND Alarm's BCD value */
__IO uint32_t ALARM_MINUTE;/**<MINUTE Alarm's BCD value */
__IO uint32_t ALARM_HOUR;/**<HOUR Alarm's BCD value*/
__IO uint32_t ALARM_DAY;/**<DAY Alarm's BCD value */
__IO uint32_t ALARM_MONTH;/**<MONTH Alarm's BCD value */
__IO uint32_t ALARM_YEAR;/**<YEAR Alarm's BCD value */
union {
struct {
__IO uint32_t SECOND :1;/**<SECOND Alarm interrupt : 0 = disabled, 1 = enabled */
__IO uint32_t MINUTE :1;/**<MINUTE Alarm interrupt : 0 = disabled, 1 = enabled */
__IO uint32_t HOUR :1;/**<HOUR Alarm interrupt : 0 = disabled, 1 = enabled */
__IO uint32_t DAY :1;/**<DAY Alarm interrupt : 0 = disabled, 1 = enabled */
__IO uint32_t MONTH :1;/**<MONTH Alarm interrupt : 0 = disabled, 1 = enabled */
__IO uint32_t YEAR :1;/**<YEAR Alarm interrupt : 0 = disabled, 1 = enabled */
__IO uint32_t PAD :2 ;/**<Writes have no effect; Read as 2’b00 */
} BITS;
__IO uint32_t WORD;
} INT_EN_CONTROL;
union {
struct {
__I uint32_t SECOND :1;/**<SECOND Alarm interrupt : 0= inactive , 1 = active */
__I uint32_t MINUTE :1;/**<MINUTE Alarm interrupt : 0= inactive , 1 = active */
__I uint32_t HOUR :1;/**<HOUR Alarm interrupt : 0= inactive , 1 = active */
__I uint32_t DAY :1;/**<DAY Alarm interrupt : 0= inactive , 1 = active */
__I uint32_t MONTH :1;/**<MONTH Alarm interrupt : 0= inactive , 1 = active */
__I uint32_t YEAR :1;/**<YEAR Alarm interrupt : 0= inactive , 1 = active */
__I uint32_t PAD :2; /**<Read as 00 */
} BITS;
__I uint32_t WORD;
} INT_STATUS;
union {
struct {
__O uint32_t SECOND :1;/**<Write 1 to clear the SECOND Alarm interrupt.*/
__O uint32_t MINUTE :1;/**<Write 1 to clear the MINUTE Alarm interrupt*/
__O uint32_t HOUR :1;/**<Write 1 to clear the HOUR Alarm interrupt*/
__O uint32_t DAY :1;/**< Write 1 to clear the DAY Alarm interrupt*/
__O uint32_t MONTH :1;/**<Write 1 to clear the MONTH Alarm interrupt */
__O uint32_t YEAR :1;/**< Write 1 to clear the YEAR Alarm interrupt*/
__O uint32_t PAD :2 ;/**< Writes have no effect. */
} BITS;
__O uint32_t WORD;
} INT_CLEAR;
#endif /* REVB */
#ifdef REVD
__IO uint32_t SUB_SECOND_COUNTER; /**<SUB SECOND Counter */ /* 0x4000F000 */
__IO uint32_t SECOND_COUNTER; /**<SECOND Counter */ /* 0x4000F004 */
__IO uint32_t SUB_SECOND_ALARM; /**< SUB SECOND alarm */ /* 0x4000F008 */
@ -148,7 +82,6 @@ typedef struct {
} BITS;
__O uint32_t WORD;
} INT_CLEAR; /* 0x4000F018 */
#endif /* REVD */
} RtcReg_t, *RtcReg_pt;
#endif /* RTC_MAP_H_ */

6
targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c
View File

@ -44,7 +44,7 @@
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
void sleep(void)
void fncs36510_sleep(void)
{
/** Unset SLEEPDEEP (SCR) and COMA to select sleep mode */
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
@ -55,7 +55,7 @@ void sleep(void)
__WFI();
}
void deepsleep(void)
void fncs36510_deepsleep(void)
{
/** Set SLEEPDEEP (SCR) and unset COMA to select deep sleep mode */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
@ -72,7 +72,7 @@ void deepsleep(void)
PMUREG->CONTROL.BITS.INT32M = 1;
}
void coma(void)
void fncs36510_coma(void)
{
/** Set SLEEPDEEP (SCR) and set COMA to select coma mode */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;

10
targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.h
View File

@ -42,10 +42,10 @@
#include "crossbar.h"
#include "clock.h"
#define SLEEP_TYPE_NONE 0
#define SLEEP_TYPE_NONE 0
#define SLEEP_TYPE_SLEEP 1
#define SLEEP_TYPE_DEEPSLEEP 2
#define SLEEP_TYPE_COMA 3
#define SLEEP_TYPE_COMA 3
#define SLEEP_TYPE_DEFAULT SLEEP_TYPE_DEEPSLEEP
@ -54,6 +54,10 @@
#define SLEEP_DURATION_DEEPSLEEP_MAX 500 /* msec */
#define SLEEP_DURATION_COMA_MAX 1000000000 /* TODO 1000 sec */
void coma(void);
void fncs36510_sleep(void);
void fncs36510_deepsleep(void);
void fncs36510_coma(void);
#endif // SLEEP_H_

48
targets/TARGET_ONSEMI/TARGET_NCS36510/sleep_api.c
View File

@ -37,54 +37,14 @@
#include "sleep_api.h"
#include "cmsis_nvic.h"
void mbed_enter_sleep(sleep_t *obj)
void sleep()
{
#ifdef SLEEP_TYPE_DEFAULT
if(SLEEP_TYPE_DEFAULT == SLEEP_TYPE_SLEEP) {
/* Sleep mode */
sleep();
} else if(SLEEP_TYPE_DEFAULT == SLEEP_TYPE_DEEPSLEEP) {
/* Deep Sleep mode */
deepsleep();
} else {
/* Coma mode */
coma();
}
#else
if(obj->SleepType == SLEEP_TYPE_NONE) {
/* Select low power mode based on sleep duration */
if(obj->timeToSleep <= SLEEP_DURATION_SLEEP_MAX) {
/* Sleep mode */
sleep();
} else if(obj->timeToSleep <= SLEEP_DURATION_DEEPSLEEP_MAX) {
/* Deep sleep */
deepsleep();
} else {
/* Coma */
coma();
}
} else if(obj->SleepType == SLEEP_TYPE_SLEEP) {
/* Sleep mode */
sleep();
} else if(obj->SleepType == SLEEP_TYPE_DEEPSLEEP) {
/* Deep Sleep mode */
deepsleep();
} else {
/* Coma mode */
coma();
}
#endif
fncs36510_sleep();
}
void mbed_exit_sleep(sleep_t *obj)
void deepsleep()
{
(void)obj;
fncs36510_deepsleep();
}
#endif /* DEVICE_SLEEP */

18
targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c
View File

@ -99,28 +99,28 @@ uint8_t spi_get_module(spi_t *obj)
int spi_slave_receive(spi_t *obj)
{
if(obj->membase->STATUS.BITS.RX_EMPTY != True){ /* if receive status is not empty */
return True; /* Byte available to read */
}
return False; /* Byte not available to read */
if(obj->membase->STATUS.BITS.RX_EMPTY != True){ /* if receive status is not empty */
return True; /* Byte available to read */
}
return False; /* Byte not available to read */
}
int spi_slave_read(spi_t *obj)
{
int byte;
while (obj->membase->STATUS.BITS.RX_EMPTY == True); /* Wait till Receive status is empty */
int byte;
while (obj->membase->STATUS.BITS.RX_EMPTY == True); /* Wait till Receive status is empty */
byte = obj->membase->RX_DATA;
return byte;
}
void spi_slave_write(spi_t *obj, int value)
{
while((obj->membase->STATUS.BITS.TX_FULL == True) && (obj->membase->STATUS.BITS.RX_FULL == True)); /* Wait till Tx/Rx status is full */
while((obj->membase->STATUS.BITS.TX_FULL == True) && (obj->membase->STATUS.BITS.RX_FULL == True)); /* Wait till Tx/Rx status is full */
obj->membase->TX_DATA = value;
}
#if DEVICE_SPI_ASYNCH /* TODO Not implemented yet */
#if DEVICE_SPI_ASYNCH /* TODO Not yet implemented */
void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t handler, uint32_t event, DMAUsage hint)
{

17
targets/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h
View File

@ -50,20 +50,15 @@
**************************************************************************************************/
/** trim register map */
typedef struct { /**< REV B REV D */
__I uint32_t PAD0; /**< 0x1FA0 0x1FA0 */
typedef struct {
__I uint32_t PAD0; /**< 0x1FA0 */
__I uint32_t MAC_ADDR_LOW; /**< 0x1FA4 */
__I uint32_t MAC_ADDR_HIGH; /**< 0x1FA8 */
#ifdef REVB
__I uint32_t TX_POWER; /**< 0x1FAC */
#endif
__I uint32_t TRIM_32K_EXT; /**< 0x1FB0 0x1FAC */
__I uint32_t TRIM_32M_EXT; /**< 0x1FB4 0x1FB0 */
#ifdef REVD
__I uint32_t FVVDH_COMP_TH; /**< 0x1FB4 */
#endif
__I uint32_t TRIM_32K_EXT; /**< 0x1FAC */
__I uint32_t TRIM_32M_EXT; /**< 0x1FB0 */
__I uint32_t FVVDH_COMP_TH; /**< 0x1FB4 */
union {
struct { /* Common to REV B & REV D */
struct {
__I uint32_t CHANNEL11:4;
__I uint32_t CHANNEL12:4;
__I uint32_t CHANNEL13:4;

95
targets/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h
View File

@ -42,100 +42,6 @@
#include "architecture.h"
#ifdef REVB
/** Watch Dog Timer Control HW Structure Overlay */
typedef struct {
__IO uint32_t LOAD; /**< Watchdog load value */
__I uint32_t VALUE; /**< Watchdog current value */
union {
struct {
__IO uint32_t INT_EN :1; /**< interrupt event : 0 = disable counter and interrupt , 1 = enable counter and interrupt */
__IO uint32_t RESET_EN :1; /**< Watchdog reset output : 0 = disable 1 = enable */
__IO uint32_t PAD :30; /**< Reserved, read undefined, must read as zeros. */
} BITS;
__IO uint32_t WORD;
} CONTROL;
__IO uint32_t INT_CLEAR; /**< Watchdog interrupt clear */
__I uint32_t RAW_INT_STAT; /**< Raw interrupt status from the counter */
__I uint32_t MASKED_INT_STAT; /**< Enabled interrupt status from the counter */
union {
struct {
__IO uint32_t WRITE_EN :1; /**< write access to all other registers : 0 = enabled(default) , 1 = disabled */
__IO uint32_t REG_WRITE_EN :31; /**< Enable write access to all other registers by writing 0x1ACCE551. Disable it by writing any other value.*/
} BITS;
__IO uint32_t WORD;
} LOCK;
__I uint32_t TEST_CTRL; /**< Integration Test Mode : 0 = disable , 1 = Enable */
union {
struct {
__IO uint32_t VAL_INT :1; /**< Value output on WDOGINT when in Integration Test Mode */
__IO uint32_t VAL_RES :1; /**< Value output on WDOGRES when in Integration Test Mode */
__IO uint32_t PAD:30; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} TEST_OUT;
union {
struct {
__IO uint32_t PART_0 :8; /**< These bits read back as 0x05 */
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PID_REG0;
union {
struct {
__IO uint32_t PART_1 :4; /**< These bits read back as 0x08 */
__IO uint32_t DESIGNER_0 :4; /**< These bits read back as 0x01 */
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PID_REG1;
union {
struct {
__IO uint32_t DESIGNER_1 :4; /**< These bits read back as 0x4 */
__IO uint32_t REVISION :4; /**< These bits read back as 0x0*/
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PID_REG2;
union {
struct {
__IO uint32_t CONFIG :8; /**< These bits read back as 0x00 */
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PID_REG3;
union {
struct {
__IO uint32_t ID0 :8; /**< These bits read back as 0x0D */
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PCELL_ID0;
union {
struct {
__IO uint32_t ID :8; /**< These bits read back as 0xF0*/
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PCELL_ID1;
union {
struct {
__IO uint32_t ID :8; /**< These bits read back as 0x05*/
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PCELL_ID2;
union {
struct {
__IO uint32_t ID :8; /**< These bits read back as 0xB1*/
__IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
} BITS;
__IO uint32_t WORD;
} PCELL_ID3;
} WdtReg_t, *WdtReg_pt;
#endif /* REVB */
#ifdef REVD
typedef struct {
__IO uint32_t LOAD; /**< 0x4000A000 Contains the value from which the counter is decremented. When this register is written to the count is immediately restarted from the new value. The minimum valid value is 1. */
__I uint32_t CURRENT_VALUE; /**< 0x4000A004 Gives the current value of the decrementing counter */
@ -157,5 +63,4 @@ typedef struct {
__IO uint32_t WORD;
} STATUS; /* 0x4000A014 */
} WdtReg_t, *WdtReg_pt;
#endif /* REVD */
#endif /* WDT_MAP_H_ */

4
targets/targets.json
View File

@ -2328,9 +2328,9 @@
"core": "Cortex-M3",
"extra_labels": ["ONSEMI"],
"post_binary_hook": {"function": "NCS36510TargetCode.ncs36510_addfib"},
"macros": ["REVD", "CM3", "CPU_NCS36510", "TARGET_NCS36510", "LOAD_ADDRESS=0x3000"],
"macros": ["CM3", "CPU_NCS36510", "TARGET_NCS36510", "LOAD_ADDRESS=0x3000"],
"supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
"device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "LOWPOWERTIMER"],
"device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "LOWPOWERTIMER", "TRNG"],
"device_name": "NCS36510",
"release_versions": ["2", "5"]
},