From 20c3e383494f57d5d486395fbf9c804b0ca02d01 Mon Sep 17 00:00:00 2001 From: Rajkumar Kanagaraj Date: Mon, 16 Mar 2020 10:13:44 -0700 Subject: [PATCH] Remove the deprecated ethernet APIs --- hal/ethernet_api.h | 105 -- .../TARGET_IOTSS/ethernet_api.c | 164 --- .../TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c | 164 --- .../TARGET_NXP/TARGET_LPC176X/ethernet_api.c | 948 ------------------ .../TARGET_NXP/TARGET_LPC43XX/ethernet_api.c | 528 ---------- .../TARGET_RZ_A1XX/ethernet_api.c | 825 --------------- 6 files changed, 2734 deletions(-) delete mode 100644 hal/ethernet_api.h delete mode 100644 targets/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c delete mode 100644 targets/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC176X/ethernet_api.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC43XX/ethernet_api.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/ethernet_api.c diff --git a/hal/ethernet_api.h b/hal/ethernet_api.h deleted file mode 100644 index 46e89ea5f0..0000000000 --- a/hal/ethernet_api.h +++ /dev/null @@ -1,105 +0,0 @@ - -/** \addtogroup hal */ -/** @{*/ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_ETHERNET_API_H -#define MBED_ETHERNET_API_H - -#include "device.h" -#include "platform/mbed_toolchain.h" - -#if DEVICE_ETHERNET - -#ifdef __cplusplus -extern "C" { -#endif - -// Connection constants -MBED_DEPRECATED( - "Ethernet drivers are provided by a class derived from `EMAC` attached to" - " either lwIP or Nanostack." -) -int ethernet_init(void); -MBED_DEPRECATED( - "Ethernet drivers are provided by a class derived from `EMAC` attached to" - " either lwIP or Nanostack." -) -void ethernet_free(void); - -// write size bytes from data to ethernet buffer -// return num bytes written -// or -1 if size is too big -MBED_DEPRECATED( - "Ethernet drivers are provided by a class derived from `EMAC` attached to" - " either lwIP or Nanostack." -) -int ethernet_write(const char *data, int size); - -// send ethernet write buffer, returning the packet size sent -MBED_DEPRECATED( - "Ethernet drivers are provided by a class derived from `EMAC` attached to" - " either lwIP or Nanostack." -) -int ethernet_send(void); - -// receive from ethernet buffer, returning packet size, or 0 if no packet -MBED_DEPRECATED( - "Ethernet drivers are provided by a class derived from `EMAC` attached to" - " either lwIP or Nanostack." -) -int ethernet_receive(void); - -// read size bytes in to data, return actual num bytes read (0..size) -// if data == NULL, throw the bytes away -MBED_DEPRECATED( - "Ethernet drivers are provided by a class derived from `EMAC` attached to" - " either lwIP or Nanostack." -) -int ethernet_read(char *data, int size); - -// get the ethernet address -MBED_DEPRECATED( - "Ethernet drivers are provided by a class derived from `EMAC` attached to" - " either lwIP or Nanostack." -) -void ethernet_address(char *mac); - -// see if the link is up -MBED_DEPRECATED( - "Ethernet drivers are provided by a class derived from `EMAC` attached to" - " either lwIP or Nanostack." -) -int ethernet_link(void); - -// force link settings -MBED_DEPRECATED( - "Ethernet drivers are provided by a class derived from `EMAC` attached to" - " either lwIP or Nanostack." -) -void ethernet_set_link(int speed, int duplex); - -#ifdef __cplusplus -} -#endif - -#endif - -#endif - - -/** @}*/ diff --git a/targets/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c b/targets/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c deleted file mode 100644 index 78469a645f..0000000000 --- a/targets/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c +++ /dev/null @@ -1,164 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "ethernet_api.h" -#include "mps2_ethernet_api.h" -#include "cmsis.h" -#include "mbed_interface.h" -#include "mbed_toolchain.h" -#include "mbed_error.h" -#include "ETH_MPS2.h" -#include "mbed_wait_api.h" - -#define TX_PKT_SIZE 256 -#define RX_PKT_SIZE 300 - -// Types -#undef FALSE -#undef TRUE -#define FALSE 0 -#define TRUE 1 - -/*---------------------------------------------------------------------------- - Ethernet Device initialize - *----------------------------------------------------------------------------*/ -int ethernet_init() -{ - int error; - error = 0; - - if(smsc9220_check_id()) { - error = TRUE; - } - - if(smsc9220_soft_reset()) { - error = TRUE; - } - - smsc9220_set_txfifo(5); - - // Sets automatic flow control thresholds, and backpressure - // threshold to defaults specified. - SMSC9220->AFC_CFG = 0x006E3740; - - if(smsc9220_wait_eeprom()) { - error = TRUE; - } - - // Configure GPIOs as LED outputs. - SMSC9220->GPIO_CFG = 0x70070000; - - smsc9220_init_irqs(); - - /* Configure MAC addresses here if needed. */ - - if(smsc9220_check_phy()) { - error = TRUE; - } - - if(smsc9220_reset_phy()) { - error = TRUE; - return error; - } - - wait_ms(100); - // Checking whether phy reset completed successfully. - { - unsigned short phyreset; - phyreset = 0; - smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &phyreset); - if(phyreset & (1 << 15)) { - error = TRUE; - return error; - } - } - - /* Advertise capabilities */ - smsc9220_advertise_cap(); - - - /* Begin to establish link */ - smsc9220_establish_link(); // bit [12] of BCONTROL seems self-clearing. - // Although it's not so in the manual. - - /* Interrupt threshold */ - SMSC9220->FIFO_INT = 0xFF000000; - - smsc9220_enable_mac_xmit(); - - smsc9220_enable_xmit(); - - SMSC9220->RX_CFG = 0; - - smsc9220_enable_mac_recv(); - - // Rx status FIFO level irq threshold - SMSC9220->FIFO_INT &= ~(0xFF); // Clear 2 bottom nibbles - - // This sleep is compulsory otherwise txmit/receive will fail. - wait_ms(2000); - return error; - -} - -/*---------------------------------------------------------------------------- - Ethernet Device Uninitialize - *----------------------------------------------------------------------------*/ -void ethernet_free() { -} - -int ethernet_write(const char *data, int size) -{ - return 0; -} - -int ethernet_send() -{ - return 0; -} - -int ethernet_receive() -{ - return 0; -} - -// Read from an recevied ethernet packet. -// After receive returnd a number bigger than 0 it is -// possible to read bytes from this packet. -// Read will write up to size bytes into data. -// It is possible to use read multible times. -// Each time read will start reading after the last read byte before. - -int ethernet_read(char *data, int dlen) -{ - return 0; -} - -void ethernet_address(char *mac) { - mbed_mac_address(mac); -} - -int ethernet_link(void) -{ - return 0; -} - -void ethernet_set_link(int speed, int duplex) -{ - smsc9220_establish_link(); -} - diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c b/targets/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c deleted file mode 100644 index 78469a645f..0000000000 --- a/targets/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c +++ /dev/null @@ -1,164 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "ethernet_api.h" -#include "mps2_ethernet_api.h" -#include "cmsis.h" -#include "mbed_interface.h" -#include "mbed_toolchain.h" -#include "mbed_error.h" -#include "ETH_MPS2.h" -#include "mbed_wait_api.h" - -#define TX_PKT_SIZE 256 -#define RX_PKT_SIZE 300 - -// Types -#undef FALSE -#undef TRUE -#define FALSE 0 -#define TRUE 1 - -/*---------------------------------------------------------------------------- - Ethernet Device initialize - *----------------------------------------------------------------------------*/ -int ethernet_init() -{ - int error; - error = 0; - - if(smsc9220_check_id()) { - error = TRUE; - } - - if(smsc9220_soft_reset()) { - error = TRUE; - } - - smsc9220_set_txfifo(5); - - // Sets automatic flow control thresholds, and backpressure - // threshold to defaults specified. - SMSC9220->AFC_CFG = 0x006E3740; - - if(smsc9220_wait_eeprom()) { - error = TRUE; - } - - // Configure GPIOs as LED outputs. - SMSC9220->GPIO_CFG = 0x70070000; - - smsc9220_init_irqs(); - - /* Configure MAC addresses here if needed. */ - - if(smsc9220_check_phy()) { - error = TRUE; - } - - if(smsc9220_reset_phy()) { - error = TRUE; - return error; - } - - wait_ms(100); - // Checking whether phy reset completed successfully. - { - unsigned short phyreset; - phyreset = 0; - smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &phyreset); - if(phyreset & (1 << 15)) { - error = TRUE; - return error; - } - } - - /* Advertise capabilities */ - smsc9220_advertise_cap(); - - - /* Begin to establish link */ - smsc9220_establish_link(); // bit [12] of BCONTROL seems self-clearing. - // Although it's not so in the manual. - - /* Interrupt threshold */ - SMSC9220->FIFO_INT = 0xFF000000; - - smsc9220_enable_mac_xmit(); - - smsc9220_enable_xmit(); - - SMSC9220->RX_CFG = 0; - - smsc9220_enable_mac_recv(); - - // Rx status FIFO level irq threshold - SMSC9220->FIFO_INT &= ~(0xFF); // Clear 2 bottom nibbles - - // This sleep is compulsory otherwise txmit/receive will fail. - wait_ms(2000); - return error; - -} - -/*---------------------------------------------------------------------------- - Ethernet Device Uninitialize - *----------------------------------------------------------------------------*/ -void ethernet_free() { -} - -int ethernet_write(const char *data, int size) -{ - return 0; -} - -int ethernet_send() -{ - return 0; -} - -int ethernet_receive() -{ - return 0; -} - -// Read from an recevied ethernet packet. -// After receive returnd a number bigger than 0 it is -// possible to read bytes from this packet. -// Read will write up to size bytes into data. -// It is possible to use read multible times. -// Each time read will start reading after the last read byte before. - -int ethernet_read(char *data, int dlen) -{ - return 0; -} - -void ethernet_address(char *mac) { - mbed_mac_address(mac); -} - -int ethernet_link(void) -{ - return 0; -} - -void ethernet_set_link(int speed, int duplex) -{ - smsc9220_establish_link(); -} - diff --git a/targets/TARGET_NXP/TARGET_LPC176X/ethernet_api.c b/targets/TARGET_NXP/TARGET_LPC176X/ethernet_api.c deleted file mode 100644 index 0b4b7a8312..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC176X/ethernet_api.c +++ /dev/null @@ -1,948 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "ethernet_api.h" - -#include -#include "cmsis.h" -#include "mbed_interface.h" -#include "mbed_toolchain.h" -#include "mbed_error.h" - -#define NEW_LOGIC 0 -#define NEW_ETH_BUFFER 0 - -#if NEW_ETH_BUFFER - -#define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets) -#define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets) - -#define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size -#define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length) - -#else - -// Memfree calculation: -// (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) + -// (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556 -/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ -#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ -#define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */ -//#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ - -//#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ -#define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */ -#define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */ - -const int ethernet_MTU_SIZE = 0x300; - -#endif - -#define ETHERNET_ADDR_SIZE 6 - -struct RX_DESC_TypeDef { /* RX Descriptor struct */ - unsigned int Packet; - unsigned int Ctrl; -} PACKED; -typedef struct RX_DESC_TypeDef RX_DESC_TypeDef; - -struct RX_STAT_TypeDef { /* RX Status struct */ - unsigned int Info; - unsigned int HashCRC; -} PACKED; -typedef struct RX_STAT_TypeDef RX_STAT_TypeDef; - -struct TX_DESC_TypeDef { /* TX Descriptor struct */ - unsigned int Packet; - unsigned int Ctrl; -} PACKED; -typedef struct TX_DESC_TypeDef TX_DESC_TypeDef; - -struct TX_STAT_TypeDef { /* TX Status struct */ - unsigned int Info; -} PACKED; -typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; - -/* MAC Configuration Register 1 */ -#define MAC1_REC_EN 0x00000001 /* Receive Enable */ -#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ -#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ -#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ -#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ -#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ -#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ -#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ -#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ -#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ -#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ - -/* MAC Configuration Register 2 */ -#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ -#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ -#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ -#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ -#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ -#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ -#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ -#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ -#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ -#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ -#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ -#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ -#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ - -/* Back-to-Back Inter-Packet-Gap Register */ -#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ -#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ - -/* Non Back-to-Back Inter-Packet-Gap Register */ -#define IPGR_DEF 0x00000012 /* Recommended value */ - -/* Collision Window/Retry Register */ -#define CLRT_DEF 0x0000370F /* Default value */ - -/* PHY Support Register */ -#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ -//#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ -#define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */ - -/* Test Register */ -#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ -#define TEST_TST_PAUSE 0x00000002 /* Test Pause */ -#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ - -/* MII Management Configuration Register */ -#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ -#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ -#define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */ -#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ - -/* MII Management Command Register */ -#define MCMD_READ 0x00000001 /* MII Read */ -#define MCMD_SCAN 0x00000002 /* MII Scan continuously */ - -#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ -#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ - -/* MII Management Address Register */ -#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ -#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ - -/* MII Management Indicators Register */ -#define MIND_BUSY 0x00000001 /* MII is Busy */ -#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ -#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ -#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ - -/* Command Register */ -#define CR_RX_EN 0x00000001 /* Enable Receive */ -#define CR_TX_EN 0x00000002 /* Enable Transmit */ -#define CR_REG_RES 0x00000008 /* Reset Host Registers */ -#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ -#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ -#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ -#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ -#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ -#define CR_RMII 0x00000200 /* Reduced MII Interface */ -#define CR_FULL_DUP 0x00000400 /* Full Duplex */ - -/* Status Register */ -#define SR_RX_EN 0x00000001 /* Enable Receive */ -#define SR_TX_EN 0x00000002 /* Enable Transmit */ - -/* Transmit Status Vector 0 Register */ -#define TSV0_CRC_ERR 0x00000001 /* CRC error */ -#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ -#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ -#define TSV0_DONE 0x00000008 /* Tramsmission Completed */ -#define TSV0_MCAST 0x00000010 /* Multicast Destination */ -#define TSV0_BCAST 0x00000020 /* Broadcast Destination */ -#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ -#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ -#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ -#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ -#define TSV0_GIANT 0x00000400 /* Giant Frame */ -#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ -#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ -#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ -#define TSV0_PAUSE 0x20000000 /* Pause Frame */ -#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ -#define TSV0_VLAN 0x80000000 /* VLAN Frame */ - -/* Transmit Status Vector 1 Register */ -#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ -#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ - -/* Receive Status Vector Register */ -#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ -#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ -#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ -#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ -#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ -#define RSV_CRC_ERR 0x00100000 /* CRC Error */ -#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ -#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ -#define RSV_REC_OK 0x00800000 /* Frame Received OK */ -#define RSV_MCAST 0x01000000 /* Multicast Frame */ -#define RSV_BCAST 0x02000000 /* Broadcast Frame */ -#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ -#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ -#define RSV_PAUSE 0x10000000 /* Pause Frame */ -#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ -#define RSV_VLAN 0x40000000 /* VLAN Frame */ - -/* Flow Control Counter Register */ -#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ -#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ - -/* Flow Control Status Register */ -#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ - -/* Receive Filter Control Register */ -#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ -#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ -#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ -#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ -#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ -#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ -#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ -#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ - -/* Receive Filter WoL Status/Clear Registers */ -#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ -#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ -#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ -#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ -#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ -#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ -#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ -#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ - -/* Interrupt Status/Enable/Clear/Set Registers */ -#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ -#define INT_RX_ERR 0x00000002 /* Receive Error */ -#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ -#define INT_RX_DONE 0x00000008 /* Receive Done */ -#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ -#define INT_TX_ERR 0x00000020 /* Transmit Error */ -#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ -#define INT_TX_DONE 0x00000080 /* Transmit Done */ -#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ -#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ - -/* Power Down Register */ -#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ - -/* RX Descriptor Control Word */ -#define RCTRL_SIZE 0x000007FF /* Buffer size mask */ -#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ - -/* RX Status Hash CRC Word */ -#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ -#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ - -/* RX Status Information Word */ -#define RINFO_SIZE 0x000007FF /* Data size in bytes */ -#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ -#define RINFO_VLAN 0x00080000 /* VLAN Frame */ -#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ -#define RINFO_MCAST 0x00200000 /* Multicast Frame */ -#define RINFO_BCAST 0x00400000 /* Broadcast Frame */ -#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ -#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ -#define RINFO_LEN_ERR 0x02000000 /* Length Error */ -#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ -#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ -#define RINFO_OVERRUN 0x10000000 /* Receive overrun */ -#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ -#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ -#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ - -//#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) -#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \ - RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) - - -/* TX Descriptor Control Word */ -#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ -#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ -#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ -#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ -#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ -#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ -#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ - -/* TX Status Information Word */ -#define TINFO_COL_CNT 0x01E00000 /* Collision Count */ -#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ -#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ -#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ -#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ -#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ -#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ -#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ - -/* ENET Device Revision ID */ -#define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ - -/* DP83848C PHY Registers */ -#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ -#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ -#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ -#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ -#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ -#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ -#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ -#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ - -/* PHY Extended Registers */ -#define PHY_REG_STS 0x10 /* Status Register */ -#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ -#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ -#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ -#define PHY_REG_RECR 0x15 /* Receive Error Counter */ -#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ -#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ -#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ -#define PHY_REG_PHYCR 0x19 /* PHY Control Register */ -#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ -#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ -#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ - -#define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */ - -#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ -#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ -#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ -#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ -#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ - -#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ -#define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */ - -#define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */ - -#define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */ -#define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */ -#define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */ - -#define PHY_BMCR_RESET 0x8000 /* PHY Reset */ - -#define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */ - -#define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */ -#define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */ - - -static int phy_read(unsigned int PhyReg); -static int phy_write(unsigned int PhyReg, unsigned short Data); - -static void txdscr_init(void); -static void rxdscr_init(void); - -#if defined (__ICCARM__) -# define AHBSRAM1 -#elif defined(TOOLCHAIN_GCC_CR) -# define AHBSRAM1 __attribute__((section(".data.$RamPeriph32"))) -#else -# define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned)) -#endif - -AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE]; -AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE]; -AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG]; -AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG]; -AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG]; -AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG]; - - -#if NEW_LOGIC -static int rx_consume_offset = -1; -static int tx_produce_offset = -1; -#else -static int send_doff = 0; -static int send_idx = -1; -static int send_size = 0; - -static int receive_soff = 0; -static int receive_idx = -1; -#endif - -static uint32_t phy_id = 0; - -static inline int rinc(int idx, int mod) { - ++idx; - idx %= mod; - return idx; -} - -//extern unsigned int SystemFrequency; -static inline unsigned int clockselect() { - if(SystemCoreClock < 10000000) { - return 1; - } else if(SystemCoreClock < 15000000) { - return 2; - } else if(SystemCoreClock < 20000000) { - return 3; - } else if(SystemCoreClock < 25000000) { - return 4; - } else if(SystemCoreClock < 35000000) { - return 5; - } else if(SystemCoreClock < 50000000) { - return 6; - } else if(SystemCoreClock < 70000000) { - return 7; - } else if(SystemCoreClock < 80000000) { - return 8; - } else if(SystemCoreClock < 90000000) { - return 9; - } else if(SystemCoreClock < 100000000) { - return 10; - } else if(SystemCoreClock < 120000000) { - return 11; - } else if(SystemCoreClock < 130000000) { - return 12; - } else if(SystemCoreClock < 140000000) { - return 13; - } else if(SystemCoreClock < 150000000) { - return 15; - } else if(SystemCoreClock < 160000000) { - return 16; - } else { - return 0; - } -} - -#ifndef min -#define min(x, y) (((x)<(y))?(x):(y)) -#endif - -/*---------------------------------------------------------------------------- - Ethernet Device initialize - *----------------------------------------------------------------------------*/ -int ethernet_init() { - int regv, tout; - char mac[ETHERNET_ADDR_SIZE]; - unsigned int clock = clockselect(); - - LPC_SC->PCONP |= 0x40000000; /* Power Up the EMAC controller. */ - - LPC_PINCON->PINSEL2 = 0x50150105; /* Enable P1 Ethernet Pins. */ - LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005; - - /* Reset all EMAC internal modules. */ - LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | - MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES; - LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM; - - for(tout = 100; tout; tout--) __NOP(); /* A short delay after reset. */ - - LPC_EMAC->MAC1 = MAC1_PASS_ALL; /* Initialize MAC control registers. */ - LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; - LPC_EMAC->MAXF = ETH_MAX_FLEN; - LPC_EMAC->CLRT = CLRT_DEF; - LPC_EMAC->IPGR = IPGR_DEF; - - LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; /* Enable Reduced MII interface. */ - - LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; /* Set clock */ - LPC_EMAC->MCFG |= MCFG_RES_MII; /* and reset */ - - for(tout = 100; tout; tout--) __NOP(); /* A short delay */ - - LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; - LPC_EMAC->MCMD = 0; - - LPC_EMAC->SUPP = SUPP_RES_RMII; /* Reset Reduced MII Logic. */ - - for (tout = 100; tout; tout--) __NOP(); /* A short delay */ - - LPC_EMAC->SUPP = 0; - - phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */ - for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */ - regv = phy_read(PHY_REG_BMCR); - if(regv < 0 || tout == 0) { - return -1; /* Error */ - } - if(!(regv & PHY_BMCR_RESET)) { - break; /* Reset complete. */ - } - } - - phy_id = (phy_read(PHY_REG_IDR1) << 16); - phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0); - - if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) { - error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id); - } - - ethernet_set_link(-1, 0); - - /* Set the Ethernet MAC Address registers */ - ethernet_address(mac); - LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4]; - LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2]; - LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0]; - - txdscr_init(); /* initialize DMA TX Descriptor */ - rxdscr_init(); /* initialize DMA RX Descriptor */ - - LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN; - /* Receive Broadcast, Perfect Match Packets */ - - LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Enable EMAC interrupts. */ - LPC_EMAC->IntClear = 0xFFFF; /* Reset all interrupts */ - - - LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); /* Enable receive and transmit mode of MAC Ethernet core */ - LPC_EMAC->MAC1 |= MAC1_REC_EN; - -#if NEW_LOGIC - rx_consume_offset = -1; - tx_produce_offset = -1; -#else - send_doff = 0; - send_idx = -1; - send_size = 0; - - receive_soff = 0; - receive_idx = -1; -#endif - - return 0; -} - -/*---------------------------------------------------------------------------- - Ethernet Device Uninitialize - *----------------------------------------------------------------------------*/ -void ethernet_free() { - LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE); - LPC_EMAC->IntClear = 0xFFFF; - - LPC_SC->PCONP &= ~0x40000000; /* Power down the EMAC controller. */ - - LPC_PINCON->PINSEL2 &= ~0x50150105; /* Disable P1 ethernet pins. */ - LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000000; -} - -// if(TxProduceIndex == TxConsumeIndex) buffer array is empty -// if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill -// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment -// TxConsumeIndex - The buffer that will/is beign sent by hardware - -int ethernet_write(const char *data, int slen) { - -#if NEW_LOGIC - - if(tx_produce_offset < 0) { // mark as active if not already - tx_produce_offset = 0; - } - - int index = LPC_EMAC->TxProduceIndex; - - int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum - int requested = slen; - int ncopy = min(remaining, requested); - - void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset); - void *psrc = (void *)(data); - - if(ncopy > 0 ){ - if(data != NULL) { - memcpy(pdst, psrc, ncopy); - } else { - memset(pdst, 0, ncopy); - } - } - - tx_produce_offset += ncopy; - - return ncopy; - -#else - void *pdst, *psrc; - const int dlen = ETH_FRAG_SIZE; - int copy = 0; - int soff = 0; - - if(send_idx == -1) { - send_idx = LPC_EMAC->TxProduceIndex; - } - - if(slen + send_doff > ethernet_MTU_SIZE) { - return -1; - } - - do { - copy = min(slen - soff, dlen - send_doff); - pdst = (void *)(txdesc[send_idx].Packet + send_doff); - psrc = (void *)(data + soff); - if(send_doff + copy > ETH_FRAG_SIZE) { - txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT); - send_idx = rinc(send_idx, NUM_TX_FRAG); - send_doff = 0; - } - - if(data != NULL) { - memcpy(pdst, psrc, copy); - } else { - memset(pdst, 0, copy); - } - - soff += copy; - send_doff += copy; - send_size += copy; - } while(soff != slen); - - return soff; -#endif -} - -int ethernet_send() { - -#if NEW_LOGIC - if(tx_produce_offset < 0) { // no buffer active - return -1; - } - - // ensure there is a link - if(!ethernet_link()) { - return -2; - } - - // we have been writing in to a buffer, so finalise it - int size = tx_produce_offset; - int index = LPC_EMAC->TxProduceIndex; - txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST); - - // Increment ProduceIndex to allow it to be sent - // We can only do this if the next slot is free - int next = rinc(index, NUM_TX_FRAG); - while(next == LPC_EMAC->TxConsumeIndex) { - for(int i=0; i<1000; i++) { __NOP(); } - } - - LPC_EMAC->TxProduceIndex = next; - tx_produce_offset = -1; - return size; - -#else - int s = send_size; - txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST); - send_idx = rinc(send_idx, NUM_TX_FRAG); - LPC_EMAC->TxProduceIndex = send_idx; - send_doff = 0; - send_idx = -1; - send_size = 0; - return s; -#endif -} - -// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read -// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd -// -// if(RxConsumeIndex == RxProduceIndex) buffer array is empty -// if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full - -// Recevies an arrived ethernet packet. -// Receiving an ethernet packet will drop the last received ethernet packet -// and make a new ethernet packet ready to read. -// Returns size of packet, else 0 if nothing to receive - -// We read from RxConsumeIndex from position rx_consume_offset -// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading -// rx_consume_offset = -1 // no frame -// rx_consume_offset = 0 // start of frame -// Assumption: A fragment should alway be a whole frame - -int ethernet_receive() { -#if NEW_LOGIC - - // if we are currently reading a valid RxConsume buffer, increment to the next one - if(rx_consume_offset >= 0) { - LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG); - } - - // if the buffer is empty, mark it as no valid buffer - if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) { - rx_consume_offset = -1; - return 0; - } - - uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info; - rx_consume_offset = 0; - - // check if it is not marked as last or for errors - if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) { - return -1; - } - - int size = (info & RINFO_SIZE) + 1; - return size - 4; // don't include checksum bytes - -#else - if(receive_idx == -1) { - receive_idx = LPC_EMAC->RxConsumeIndex; - } else { - while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && ((uint32_t)receive_idx != LPC_EMAC->RxProduceIndex)) { - receive_idx = rinc(receive_idx, NUM_RX_FRAG); - } - unsigned int info = rxstat[receive_idx].Info; - int slen = (info & RINFO_SIZE) + 1; - - if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) { - /* Invalid frame, ignore it and free buffer. */ - receive_idx = rinc(receive_idx, NUM_RX_FRAG); - } - receive_idx = rinc(receive_idx, NUM_RX_FRAG); - receive_soff = 0; - - LPC_EMAC->RxConsumeIndex = receive_idx; - } - - if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex) { - receive_idx = -1; - return 0; - } - - return (rxstat[receive_idx].Info & RINFO_SIZE) - 3; -#endif -} - -// Read from an recevied ethernet packet. -// After receive returnd a number bigger than 0 it is -// possible to read bytes from this packet. -// Read will write up to size bytes into data. -// It is possible to use read multible times. -// Each time read will start reading after the last read byte before. - -int ethernet_read(char *data, int dlen) { -#if NEW_LOGIC - // Check we have a valid buffer to read - if(rx_consume_offset < 0) { - return 0; - } - - // Assume 1 fragment block - uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info; - int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum - - int remaining = size - rx_consume_offset; - int requested = dlen; - int ncopy = min(remaining, requested); - - void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset); - void *pdst = (void *)(data); - - if(data != NULL && ncopy > 0) { - memcpy(pdst, psrc, ncopy); - } - - rx_consume_offset += ncopy; - - return ncopy; -#else - int slen; - int copy = 0; - unsigned int more; - unsigned int info; - void *pdst, *psrc; - int doff = 0; - - if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) { - return 0; - } - - do { - info = rxstat[receive_idx].Info; - more = !(info & RINFO_LAST_FLAG); - slen = (info & RINFO_SIZE) + 1; - - if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) { - /* Invalid frame, ignore it and free buffer. */ - receive_idx = rinc(receive_idx, NUM_RX_FRAG); - } else { - - copy = min(slen - receive_soff, dlen - doff); - psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff); - pdst = (void *)(data + doff); - - if(data != NULL) { - /* check if Buffer available */ - memcpy(pdst, psrc, copy); - } - - receive_soff += copy; - doff += copy; - - if((more && (receive_soff == slen))) { - receive_idx = rinc(receive_idx, NUM_RX_FRAG); - receive_soff = 0; - } - } - } while(more && !(doff == dlen) && !receive_soff); - - return doff; -#endif -} - -int ethernet_link(void) { - - if (phy_id == DP83848C_ID) { - return (phy_read(PHY_REG_STS) & PHY_STS_LINK); - } - else { // LAN8720_ID - return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK); - } -} - -static int phy_write(unsigned int PhyReg, unsigned short Data) { - unsigned int timeOut; - - LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; - LPC_EMAC->MWTD = Data; - - for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) { /* Wait until operation completed */ - if((LPC_EMAC->MIND & MIND_BUSY) == 0) { - return 0; - } - } - - return -1; -} - - -static int phy_read(unsigned int PhyReg) { - unsigned int timeOut; - - LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; - LPC_EMAC->MCMD = MCMD_READ; - - for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) { /* Wait until operation completed */ - if((LPC_EMAC->MIND & MIND_BUSY) == 0) { - LPC_EMAC->MCMD = 0; - return LPC_EMAC->MRDD; /* Return a 16-bit value. */ - } - } - - return -1; -} - - -static void txdscr_init() { - int i; - - for(i = 0; i < NUM_TX_FRAG; i++) { - txdesc[i].Packet = (uint32_t)&txbuf[i]; - txdesc[i].Ctrl = 0; - txstat[i].Info = 0; - } - - LPC_EMAC->TxDescriptor = (uint32_t)txdesc; /* Set EMAC Transmit Descriptor Registers. */ - LPC_EMAC->TxStatus = (uint32_t)txstat; - LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1; - - LPC_EMAC->TxProduceIndex = 0; /* Tx Descriptors Point to 0 */ -} - - -static void rxdscr_init() { - int i; - - for(i = 0; i < NUM_RX_FRAG; i++) { - rxdesc[i].Packet = (uint32_t)&rxbuf[i]; - rxdesc[i].Ctrl = RCTRL_INT | (ETH_FRAG_SIZE-1); - rxstat[i].Info = 0; - rxstat[i].HashCRC = 0; - } - - LPC_EMAC->RxDescriptor = (uint32_t)rxdesc; /* Set EMAC Receive Descriptor Registers. */ - LPC_EMAC->RxStatus = (uint32_t)rxstat; - LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1; - - LPC_EMAC->RxConsumeIndex = 0; /* Rx Descriptors Point to 0 */ -} - -void ethernet_address(char *mac) { - mbed_mac_address(mac); -} - -void ethernet_set_link(int speed, int duplex) { - unsigned short phy_data; - int tout; - - if((speed < 0) || (speed > 1)) { - - phy_data = PHY_AUTO_NEG; - - } else { - - phy_data = (((unsigned short) speed << 13) | - ((unsigned short) duplex << 8)); - } - - phy_write(PHY_REG_BMCR, phy_data); - - for(tout = 100; tout; tout--) { __NOP(); } /* A short delay */ - - switch(phy_id) { - case DP83848C_ID: - - phy_data = phy_read(PHY_REG_STS); - - if(phy_data & PHY_STS_DUPLEX) { - LPC_EMAC->MAC2 |= MAC2_FULL_DUP; - LPC_EMAC->Command |= CR_FULL_DUP; - LPC_EMAC->IPGT = IPGT_FULL_DUP; - } else { - LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP; - LPC_EMAC->Command &= ~CR_FULL_DUP; - LPC_EMAC->IPGT = IPGT_HALF_DUP; - } - - if(phy_data & PHY_STS_SPEED) { - LPC_EMAC->SUPP &= ~SUPP_SPEED; - } else { - LPC_EMAC->SUPP |= SUPP_SPEED; - } - - - break; - case LAN8720_ID: - - phy_data = phy_read(PHY_REG_SCSR); - - if (phy_data & PHY_SCSR_DUPLEX) { - LPC_EMAC->MAC2 |= MAC2_FULL_DUP; - LPC_EMAC->Command |= CR_FULL_DUP; - LPC_EMAC->IPGT = IPGT_FULL_DUP; - } else { - LPC_EMAC->Command &= ~CR_FULL_DUP; - LPC_EMAC->IPGT = IPGT_HALF_DUP; - } - - if(phy_data & PHY_SCSR_100MBIT) { - LPC_EMAC->SUPP |= SUPP_SPEED; - } else { - LPC_EMAC->SUPP &= ~SUPP_SPEED; - } - - - break; - } - - -} diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/ethernet_api.c b/targets/TARGET_NXP/TARGET_LPC43XX/ethernet_api.c deleted file mode 100644 index b947155941..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC43XX/ethernet_api.c +++ /dev/null @@ -1,528 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Contribution by Nitin Bhaskar(nitin.bhaskar.27.09@gmail.com) - */ -#include "ethernet_api.h" - -#include -#include "cmsis.h" -#include "mbed_interface.h" -#include "mbed_toolchain.h" -#include "mbed_error.h" -#include "pinmap.h" - -#define NEW_LOGIC 0 -#define NEW_ETH_BUFFER 0 - -#if NEW_ETH_BUFFER - -#define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets) -#define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets) - -#define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size -#define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length) - -#else - -// Memfree calculation: -// (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) + -// (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556 -/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ -#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ -#define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */ -//#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ - -//#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ -#define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */ -#define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */ - -const int ethernet_MTU_SIZE = 0x300; - -#endif - -#define ETHERNET_ADDR_SIZE 6 - -/* Descriptors Fields bits */ -#define TRDES_OWN_BIT (1U<<31) /* Own bit in RDES0 & TDES0 */ -#define RX_END_RING (1<<15) /* Receive End of Ring bit in RDES1 */ -#define RX_NXTDESC_FLAG (1<<14) /* Second Address Chained bit in RDES1 */ -#define TX_LAST_SEGM (1<<29) /* Last Segment bit in TDES0 */ -#define TX_FIRST_SEGM (1<<28) /* First Segment bit in TDES0 */ -#define TX_END_RING (1<<21) /* Transmit End of Ring bit in TDES0 */ -#define TX_NXTDESC_FLAG (1<<20) /* Second Address Chained bit in TDES0 */ - -PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */ - unsigned int Status; - unsigned int Ctrl; - unsigned int BufAddr1; - unsigned int NextDescAddr; -}; -typedef struct RX_DESC_TypeDef RX_DESC_TypeDef; - -PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */ - unsigned int Status; - unsigned int Ctrl; - unsigned int BufAddr1; - unsigned int NextDescAddr; -}; -typedef struct TX_DESC_TypeDef TX_DESC_TypeDef; - -/* ETHMODE RMII SELECT */ -#define RMII_SELECT 0x04 -/* define to tell PHY about write operation */ -#define MII_WRITE (1 << 1) -/* define to tell PHY about read operation */ -#define MII_READ (0 << 1) -/* define to enable duplex mode */ -#define MAC_DUPLEX_MODE (1 << 11) - -/* MAC_FRAME_FILTER register bit defines */ -#define MAC_FRAME_FILTER_PR (1 << 0) /* Promiscuous Mode */ -#define MAC_FRAME_FILTER_RA (1UL << 31) /* Receive all */ - -/* MAC_CONFIG register bit defines */ -#define MAC_CONFIG_RE (1 << 2) /* Receiver enable */ -#define MAC_CONFIG_TE (1 << 3) /* Transmitter Enable */ - -/* DMA_OP_MODE register bit defines */ -#define DMA_OP_MODE_SSR (1 << 1) /* Start/stop receive */ -#define DMA_OP_MODE_SST (1 << 13) /* Start/Stop Transmission Command */ - -/* DMA_INT_EN register bit defines */ -#define DMA_INT_EN_TIE (1 << 0) /* Transmit interrupt enable */ -#define DMA_INT_EN_TSE (1 << 1) /* Transmit stopped enable */ -#define DMA_INT_EN_TUE (1 << 2) /* Transmit buffer unavailable enable */ -#define DMA_INT_EN_TJE (1 << 3) /* Transmit jabber timeout enable */ -#define DMA_INT_EN_OVE (1 << 4) /* Overflow interrupt enable */ -#define DMA_INT_EN_UNE (1 << 5) /* Underflow interrupt enable */ -#define DMA_INT_EN_RIE (1 << 6) /* Receive interrupt enable */ -#define DMA_INT_EN_RUE (1 << 7) /* Receive buffer unavailable enable */ -#define DMA_INT_EN_RSE (1 << 8) /* Received stopped enable */ -#define DMA_INT_EN_RWE (1 << 9) /* Receive watchdog timeout enable */ -#define DMA_INT_EN_ETE (1 << 10) /* Early transmit interrupt enable */ -#define DMA_INT_EN_FBE (1 << 13) /* Fatal bus error enable */ -#define DMA_INT_EN_ERE (1 << 14) /* Early receive interrupt enable */ -#define DMA_INT_EN_AIE (1 << 15) /* Abnormal interrupt summary enable */ -#define DMA_INT_EN_NIE (1 << 16) /* Normal interrupt summary enable */ - - - -/* PHY Support Register */ -#define SUPP_SPEED 0x00004000 /* Reduced MII Logic Current Speed */ -//#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ -#define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */ - -/* MII Management Command Register */ -#define MCMD_READ 0x00000001 /* MII Read */ -#define MCMD_SCAN 0x00000002 /* MII Scan continuously */ - -#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ -#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ - -/* MII Management Address Register */ -#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ -#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ - -/* MII Management Indicators Register */ -#define MIND_BUSY 0x00000001 /* MII is Busy */ -#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ -#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ -#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ - -/* DP83848C PHY Registers */ -#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ -#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ -#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ -#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ -#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ -#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ -#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ -#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ - -/* PHY Extended Registers */ -#define PHY_REG_STS 0x10 /* Status Register */ -#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ -#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ -#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ -#define PHY_REG_RECR 0x15 /* Receive Error Counter */ -#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ -#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ -#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ -#define PHY_REG_PHYCR 0x19 /* PHY Control Register */ -#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ -#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ -#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ - -#define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */ - -#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ -#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ -#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ -#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ -#define PHY_AUTO_NEG 0x1000 /* Select Auto Negotiation */ - -#define DP83848C_DEF_ADR 0x01 /* Default PHY device address */ -#define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */ - -#define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */ - -#define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */ -#define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */ -#define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */ - -#define PHY_BMCR_RESET 0x8000 /* PHY Reset */ - -#define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */ - -#define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */ -#define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */ - -static int phy_read(unsigned int PhyReg); -static int phy_write(unsigned int PhyReg, unsigned short Data); - -static void txdscr_init(void); -static void rxdscr_init(void); - -#if defined (__ICCARM__) -# define AHBSRAM1 -#elif defined(TOOLCHAIN_GCC_CR) -# define AHBSRAM1 __attribute__((section(".data.$RamPeriph32"))) -#else -# define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned)) -#endif - -AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE]; -AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE]; -AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG]; -AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG]; - -#ifndef min -#define min(x, y) (((x)<(y))?(x):(y)) -#endif - -static uint32_t phy_id = 0; -static uint32_t TxDescIndex = 0; -static uint32_t RxDescIndex = 0; -static uint32_t RxOffset = 0; - -/*---------------------------------------------------------------------------- - Ethernet Device initialize - *----------------------------------------------------------------------------*/ -int ethernet_init() -{ - int regv, tout; - char mac[ETHERNET_ADDR_SIZE]; - - pin_function(PC_0, (SCU_MODE_INACT | FUNC3)); /* Enable ENET RX CLK */ - pin_function(P1_19, (SCU_MODE_INACT | FUNC0)); /* Enable ENET TX CLK */ - - /* Ethernet pinmuxing */ - pin_function(P2_0, SCU_PINIO_FAST | FUNC7); /* ENET_MDC */ - pin_function(P1_17, SCU_PINIO_FAST | FUNC3); /* ENET_MDIO */ - pin_function(P1_18, SCU_PINIO_FAST | FUNC3); /* ENET_TXD0 */ - pin_function(P1_20, SCU_PINIO_FAST | FUNC3); /* ENET_TXD1 */ - pin_function(P1_19, SCU_PINIO_FAST | FUNC0); /* ENET_REF */ - pin_function(P0_1, SCU_PINIO_FAST | FUNC6); /* ENET_TX_EN */ - pin_function(P1_15, SCU_PINIO_FAST | FUNC3); /* ENET_RXD0 */ - pin_function(P0_0, SCU_PINIO_FAST | FUNC2); /* ENET_RXD1 */ - pin_function(P1_16, SCU_PINIO_FAST | FUNC3); /* ENET_CRS */ - pin_function(PC_9, SCU_PINIO_FAST | FUNC3); /* ENET_RX_ER */ - pin_function(P1_16, SCU_PINIO_FAST | FUNC7); /* ENET_RXDV */ - - LPC_CREG->CREG6 |= RMII_SELECT; - - /* perform RGU soft reset */ - LPC_RGU->RESET_CTRL0 = 1 << 22; - LPC_RGU->RESET_CTRL0 = 0; - - /* Wait until reset is performed */ - while(1) { - if (LPC_RGU->RESET_ACTIVE_STATUS0 & (1 << 22)) - break; - } - - /* Reset MAC DMA Controller */ - LPC_ETHERNET->DMA_BUS_MODE |= 0x01; - while(LPC_ETHERNET->DMA_BUS_MODE & 0x01); - - phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */ - - for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */ - regv = phy_read(PHY_REG_BMCR); - if(regv < 0 || tout == 0) { - return -1; /* Error */ - } - if(!(regv & PHY_BMCR_RESET)) { - break; /* Reset complete. */ - } - } - - phy_id = (phy_read(PHY_REG_IDR1) << 16); - phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0); - - if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) { - error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id); - } - - ethernet_set_link(-1, 0); - - /* Set the Ethernet MAC Address registers */ - ethernet_address(mac); - LPC_ETHERNET->MAC_ADDR0_HIGH = (mac[5] << 8) | mac[4]; - LPC_ETHERNET->MAC_ADDR0_LOW = (mac[3] << 24) | (mac[2] << 16) | (mac[1] << 8) | mac[0]; - - txdscr_init(); /* initialize DMA TX Descriptor */ - rxdscr_init(); /* initialize DMA RX Descriptor */ - - /* Configure Filter */ - LPC_ETHERNET->MAC_FRAME_FILTER = MAC_FRAME_FILTER_PR | MAC_FRAME_FILTER_RA; - - /* Enable Receiver and Transmitter */ - LPC_ETHERNET->MAC_CONFIG |= (MAC_CONFIG_RE | MAC_CONFIG_TE); - - //LPC_ETHERNET->DMA_INT_EN = DMA_INT_EN_NIE | DMA_INT_EN_RIE | DMA_INT_EN_TJE; /* Enable EMAC interrupts. */ - - /* Start Transmission & Receive processes */ - LPC_ETHERNET->DMA_OP_MODE |= (DMA_OP_MODE_SST | DMA_OP_MODE_SSR); - - return 0; -} - -/*---------------------------------------------------------------------------- - Ethernet Device Uninitialize - *----------------------------------------------------------------------------*/ -void ethernet_free() -{ -} - -/*---------------------------------------------------------------------------- - Ethernet write - *----------------------------------------------------------------------------*/ -int ethernet_write(const char *data, int slen) -{ - if (slen > ETH_FRAG_SIZE) - return -1; - - txdesc[TxDescIndex].Ctrl = slen; - memcpy((void *)txdesc[TxDescIndex].BufAddr1, data, slen); - return slen; -} - -/*---------------------------------------------------------------------------- - Ethernet Send - *----------------------------------------------------------------------------*/ -int ethernet_send() -{ - int s = txdesc[TxDescIndex].Ctrl; - txdesc[TxDescIndex].Status |= TRDES_OWN_BIT; - LPC_ETHERNET->DMA_TRANS_POLL_DEMAND = 1; // Wake Up the DMA if it's in Suspended Mode - TxDescIndex++; - if (TxDescIndex == NUM_TX_FRAG) - TxDescIndex = 0; - - return s; -} - -/*---------------------------------------------------------------------------- - Ethernet receive - *----------------------------------------------------------------------------*/ -int ethernet_receive() -{ - int i, slen = 0; - for (i = RxDescIndex;; i++) { - if (rxdesc[i].Status & TRDES_OWN_BIT) - return (slen - RxOffset); - else - slen += (rxdesc[i].Status >> 16) & 0x03FFF; - } - return 0; -} - - -/*---------------------------------------------------------------------------- - Ethernet read - *----------------------------------------------------------------------------*/ -int ethernet_read(char *data, int dlen) -{ - int copylen; - uint32_t *pSrc = (uint32_t *)rxdesc[RxDescIndex].BufAddr1; - copylen = (rxdesc[RxDescIndex].Status >> 16) & 0x03FFF; - if (rxdesc[RxDescIndex].Status & TRDES_OWN_BIT || (dlen + RxOffset) > copylen) - return -1; - - if ((dlen + RxOffset) == copylen) { - memcpy(&pSrc[RxOffset], data, copylen); - rxdesc[RxDescIndex].Status = TRDES_OWN_BIT; - RxDescIndex++; - RxOffset = 0; - if (RxDescIndex == NUM_RX_FRAG) - RxDescIndex = 0; - } else if ((dlen + RxOffset) < copylen) { - copylen = dlen; - memcpy(&pSrc[RxOffset], data, copylen); - RxOffset += dlen; - } - return copylen; -} - -int ethernet_link(void) -{ - - if (phy_id == DP83848C_ID) { - return (phy_read(PHY_REG_STS) & PHY_STS_LINK); - } else { // LAN8720_ID - return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK); - } -} - -static int phy_write(unsigned int PhyReg, unsigned short Data) -{ - unsigned int timeOut; - - while(LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY); - LPC_ETHERNET->MAC_MII_ADDR = (DP83848C_DEF_ADR<<11) | (PhyReg<<6) | MII_WRITE; - LPC_ETHERNET->MAC_MII_DATA = Data; - LPC_ETHERNET->MAC_MII_ADDR |= MIND_BUSY; // Start PHY Write Cycle - - /* Wait utill operation completed */ - for (timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) { - if ((LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY) == 0) { - break; - } - } - - return -1; -} - -static int phy_read(unsigned int PhyReg) -{ - unsigned int timeOut; - - while(LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY); - LPC_ETHERNET->MAC_MII_ADDR = (DP83848C_DEF_ADR<<11) | (PhyReg<<6) | MII_READ; - LPC_ETHERNET->MAC_MII_ADDR |= MIND_BUSY; - - for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) { /* Wait until operation completed */ - if((LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY) == 0) { - return LPC_ETHERNET->MAC_MII_DATA; /* Return a 16-bit value. */ - } - } - - return -1; -} - -static void txdscr_init() -{ - int i; - - for(i = 0; i < NUM_TX_FRAG; i++) { - txdesc[i].Status = TX_LAST_SEGM | TX_FIRST_SEGM;; - txdesc[i].Ctrl = 0; - txdesc[i].BufAddr1 = (uint32_t)&txbuf[i]; - if (i == (NUM_TX_FRAG - 1)) { - txdesc[i].Status |= TX_END_RING; - } - } - - LPC_ETHERNET->DMA_TRANS_DES_ADDR = (uint32_t)txdesc; /* Set EMAC Transmit Descriptor Registers. */ -} - - -static void rxdscr_init() -{ - int i; - - for(i = 0; i < NUM_RX_FRAG; i++) { - rxdesc[i].Status = TRDES_OWN_BIT; - rxdesc[i].Ctrl = ETH_FRAG_SIZE; - rxdesc[i].BufAddr1 = (uint32_t)&rxbuf[i]; - if (i == (NUM_RX_FRAG - 1)) { - rxdesc[i].Ctrl |= RX_END_RING; - } - } - - LPC_ETHERNET->DMA_REC_DES_ADDR = (uint32_t)rxdesc; /* Set EMAC Receive Descriptor Registers. */ -} - -void ethernet_address(char *mac) -{ - mbed_mac_address(mac); -} - -void ethernet_set_link(int speed, int duplex) -{ - volatile unsigned short phy_data; - int tout; - - if((speed < 0) || (speed > 1)) { - - phy_data = PHY_AUTO_NEG; - - } else { - - phy_data = (((unsigned short) speed << 13) | - ((unsigned short) duplex << 8)); - } - - phy_write(PHY_REG_BMCR, phy_data); - - for(tout = 100; tout; tout--) { - __NOP(); /* A short delay */ - } - - switch(phy_id) { - case DP83848C_ID: - - phy_data = phy_read(PHY_REG_STS); - - if(phy_data & PHY_STS_DUPLEX) { - /* Full duplex is enabled. */ - LPC_ETHERNET->MAC_CONFIG |= MAC_DUPLEX_MODE; - } else { - LPC_ETHERNET->MAC_CONFIG &= ~MAC_DUPLEX_MODE; - } - - if(phy_data & PHY_STS_SPEED) { - LPC_ETHERNET->MAC_CONFIG &= ~SUPP_SPEED; - } else { - LPC_ETHERNET->MAC_CONFIG |= SUPP_SPEED; - } - break; - - case LAN8720_ID: - - for(tout = 100; tout; tout--) { - phy_data = phy_read(PHY_REG_BMSR); - if (phy_data & PHY_STS_DUPLEX) - break; - } - - if (phy_data & PHY_STS_DUPLEX) { - /* Full duplex is enabled. */ - LPC_ETHERNET->MAC_CONFIG |= MAC_DUPLEX_MODE; - } else { - LPC_ETHERNET->MAC_CONFIG &= ~MAC_DUPLEX_MODE; - } - - if(phy_data & PHY_STS_SPEED) { - LPC_ETHERNET->MAC_CONFIG &= ~SUPP_SPEED; - } else { - LPC_ETHERNET->MAC_CONFIG |= SUPP_SPEED; - } - break; - } -} - diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/ethernet_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/ethernet_api.c deleted file mode 100644 index 168f9c8694..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/ethernet_api.c +++ /dev/null @@ -1,825 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "ethernet_api.h" -#include "cmsis.h" -#include "mbed_interface.h" -#include "mbed_toolchain.h" -#include "mbed_error.h" -#include "iodefine.h" -#include "ethernetext_api.h" - -#if DEVICE_ETHERNET - -/* Descriptor info */ -#define NUM_OF_TX_DESCRIPTOR (16) -#define NUM_OF_RX_DESCRIPTOR (16) -#define SIZE_OF_BUFFER (1600) /* Must be an integral multiple of 32 */ -#define MAX_SEND_SIZE (1514) -/* Ethernet Descriptor Value Define */ -#define TD0_TFP_TOP_BOTTOM (0x30000000) -#define TD0_TACT (0x80000000) -#define TD0_TDLE (0x40000000) -#define RD0_RACT (0x80000000) -#define RD0_RDLE (0x40000000) -#define RD0_RFE (0x08000000) -#define RD0_RCSE (0x04000000) -#define RD0_RFS (0x03FF0000) -#define RD0_RCS (0x0000FFFF) -#define RD0_RFS_RFOF (0x02000000) -#define RD0_RFS_RUAF (0x00400000) -#define RD0_RFS_RRF (0x00100000) -#define RD0_RFS_RTLF (0x00080000) -#define RD0_RFS_RTSF (0x00040000) -#define RD0_RFS_PRE (0x00020000) -#define RD0_RFS_CERF (0x00010000) -#define RD0_RFS_ERROR (RD0_RFS_RFOF | RD0_RFS_RUAF | RD0_RFS_RRF | RD0_RFS_RTLF | \ - RD0_RFS_RTSF | RD0_RFS_PRE | RD0_RFS_CERF) -#define RD1_RDL_MSK (0x0000FFFF) -/* PHY Register */ -#define BASIC_MODE_CONTROL_REG (0) -#define BASIC_MODE_STATUS_REG (1) -#define PHY_IDENTIFIER1_REG (2) -#define PHY_IDENTIFIER2_REG (3) -#define PHY_SP_CTL_STS_REG (31) -/* MII management interface access */ -#define PHY_ADDR (0) /* Confirm the pin connection of the PHY-LSI */ -#define PHY_ST (1) -#define PHY_WRITE (1) -#define PHY_READ (2) -#define MDC_WAIT (6) /* 400ns/4 */ -#define BASIC_STS_MSK_LINK (0x0004) /* Link Status */ -#define BASIC_STS_MSK_AUTO_CMP (0x0020) /* Auto-Negotiate Complete */ -#define M_PHY_ID (0xFFFFFFF0) -#define PHY_ID_LAN8710A (0x0007C0F0) -/* ETHERPIR0 */ -#define PIR0_MDI (0x00000008) -#define PIR0_MDO (0x00000004) -#define PIR0_MMD (0x00000002) -#define PIR0_MDC (0x00000001) -#define PIR0_MDC_HIGH (0x00000001) -#define PIR0_MDC_LOW (0x00000000) -/* ETHEREDRRR0 */ -#define EDRRR0_RR (0x00000001) -/* ETHEREDTRR0 */ -#define EDTRR0_TR (0x00000003) -/* software wait */ -#define LOOP_100us (6700) /* Loop counter for software wait 6666=100us/((1/400MHz)*6cyc) */ - -#define EDMAC_EESIPR_INI_RECV (0x0205001F) /* 0x02000000 : Detect reception suspended */ - /* 0x00040000 : Detect frame reception */ - /* 0x00010000 : Receive FIFO overflow */ - /* 0x00000010 : Residual bit frame reception */ - /* 0x00000008 : Long frame reception */ - /* 0x00000004 : Short frame reception */ - /* 0x00000002 : PHY-LSI reception error */ - /* 0x00000001 : Receive frame CRC error */ -#define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */ - -void ethernet_address(char *); -void ethernet_set_link(int, int); - - -/* Send descriptor */ -typedef struct tag_edmac_send_desc { - uint32_t td0; - uint32_t td1; - uint8_t *td2; - uint32_t padding4; -} edmac_send_desc_t; - -/* Receive descriptor */ -typedef struct tag_edmac_recv_desc { - uint32_t rd0; - uint32_t rd1; - uint8_t *rd2; - uint32_t padding4; -} edmac_recv_desc_t; - -/* memory */ -/* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */ -/* Transmit/receive buffers (must be allocated in 16-byte boundaries) */ -#if defined(__ICCARM__) -#pragma data_alignment=16 -static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) + - (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) + - (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) + - (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] //16 bytes aligned! - @ ".mirrorram"; -#else -static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) + - (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) + - (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) + - (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] - __attribute((section("NC_BSS"),aligned(16))); //16 bytes aligned! -#endif -static int32_t rx_read_offset; /* read offset */ -static int32_t tx_wite_offset; /* write offset */ -static uint32_t send_top_index; -static uint32_t recv_top_index; -static int32_t Interrupt_priority; -static edmac_send_desc_t *p_eth_desc_dsend = NULL; -static edmac_recv_desc_t *p_eth_desc_drecv = NULL; -static edmac_recv_desc_t *p_recv_end_desc = NULL; -static ethernetext_cb_fnc *p_recv_cb_fnc = NULL; -static char mac_addr[6] = {0x00, 0x02, 0xF7, 0xF0, 0x00, 0x00}; /* MAC Address */ -static uint32_t phy_id = 0; -static uint32_t start_stop = 1; /* 0:stop 1:start */ -static uint32_t tsu_ten_tmp = 0; - -volatile struct st_ether_from_tsu_adrh0* ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ - -/* function */ -static void lan_reg_reset(void); -static void lan_desc_create(void); -static void lan_reg_set(int32_t link); -static uint16_t phy_reg_read(uint16_t reg_addr); -static void phy_reg_write(uint16_t reg_addr, uint16_t data); -static void mii_preamble(void); -static void mii_cmd(uint16_t reg_addr, uint32_t option); -static void mii_reg_read(uint16_t *data); -static void mii_reg_write(uint16_t data); -static void mii_z(void); -static void mii_write_1(void); -static void mii_write_0(void); -static void set_ether_pir(uint32_t set_data); -static void wait_100us(int32_t wait_cnt); - - -int ethernetext_init(ethernet_cfg_t *p_ethcfg) { - int32_t i; - uint16_t val; - - CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */ - -#if defined(TARGET_RZ_A1H) - /* P4_2(PHY Reset) */ - GPIOP4 &= ~0x0004; /* Outputs low level */ - GPIOPMC4 &= ~0x0004; /* Port mode */ - GPIOPM4 &= ~0x0004; /* Output mode */ - - /* GPIO P1 P1_14(ET_COL) */ - GPIOPMC1 |= 0x4000; - GPIOPFCAE1 &= ~0x4000; - GPIOPFCE1 |= 0x4000; - GPIOPFC1 |= 0x4000; - - /* P3_0(ET_TXCLK), P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */ - GPIOPMC3 |= 0x0079; - GPIOPFCAE3 &= ~0x0079; - GPIOPFCE3 &= ~0x0079; - GPIOPFC3 |= 0x0079; - GPIOPIPC3 |= 0x0079; - - /* P5_9(ET_MDC) */ - GPIOPMC5 |= 0x0200; - GPIOPFCAE5 &= ~0x0200; - GPIOPFCE5 &= ~0x0200; - GPIOPFC5 |= 0x0200; - GPIOPIPC5 |= 0x0200; - - /* P10_1(ET_TXER), P10_2(ET_TXEN), P10_3(ET_CRS), P10_4(ET_TXD0), P10_5(ET_TXD1) */ - /* P10_6(ET_TXD2), P10_7(ET_TXD3), P10_8(ET_RXD0), P10_9(ET_RXD1), P10_10(ET_RXD2), P10_11(ET_RXD3) */ - GPIOPMC10 |= 0x0FFE; - GPIOPFCAE10 &= ~0x0FFE; - GPIOPFCE10 |= 0x0FFE; - GPIOPFC10 |= 0x0FFE; - GPIOPIPC10 |= 0x0FFE; - - /* Resets the E-MAC,E-DMAC */ - lan_reg_reset(); - - /* PHY Reset */ - GPIOP4 &= ~0x0004; /* P4_2 Outputs low level */ - wait_100us(250); /* 25msec */ - GPIOP4 |= 0x0004; /* P4_2 Outputs high level */ - wait_100us(100); /* 10msec */ -#elif defined(TARGET_VK_RZ_A1H) - /* -->4F<-- P1_14(ET_COL) */ - GPIOPMC1 |= 0x4000; - GPIOPFCAE1 &= ~0x4000; - GPIOPFCE1 |= 0x4000; - GPIOPFC1 |= 0x4000; - GPIOPIPC1 |= 0x4000; - - /* -->2F<-- P2_0(ET_TXCLK), P2_1(ET_TXER), P2_2(ET_TXEN), P2_3(ET_CRS), P2_4(ET_TXD0), - P2_5(ET_TXD1), P2_6(ET_TXD2), P2_7(ET_TXD3), P2_8(ET_RXD0), P2_9(ET_RXD1), P2_10(ET_RXD2) P2_11(ET_RXD3) */ - GPIOPMC2 |= 0x0FFF; - GPIOPFCAE2 &= ~0x0FFF; - GPIOPFCE2 &= ~0x0FFF; - GPIOPFC2 |= 0x0FFF; - GPIOPIPC2 |= 0x0FFF; - - /* -->3F<-- P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */ - GPIOPMC3 |= 0x0078; - GPIOPFCAE3 &= ~0x0078; - GPIOPFCE3 &= ~0x0078; - GPIOPFC3 |= 0x0078; - GPIOPIPC3 |= 0x0078; - - /* -->3F<-- P7_0(ET_MDC) */ - GPIOPMC7 |= 0x0001; - GPIOPFCAE7 &= ~0x0001; - GPIOPFCE7 |= 0x0001; - GPIOPFC7 &= ~0x0001; - GPIOPIPC7 |= 0x0001; - - /* Resets the E-MAC,E-DMAC */ - lan_reg_reset(); -#else -#error "There is no initialization processing." -#endif - - /* Resets the PHY-LSI */ - phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000); - for (i = 10000; i > 0; i--) { - val = phy_reg_read(BASIC_MODE_CONTROL_REG); - if (((uint32_t)val & 0x8000uL) == 0) { - break; /* Reset complete */ - } - } - - phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16) - | (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG); - - Interrupt_priority = p_ethcfg->int_priority; - p_recv_cb_fnc = p_ethcfg->recv_cb; - start_stop = 1; - - if (p_ethcfg->ether_mac != NULL) { - (void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr)); - } else { - ethernet_address(mac_addr); /* Get MAC Address */ - } - - return 0; -} - -void ethernetext_start_stop(int32_t mode) { - if (mode == 1) { - /* start */ - ETHEREDTRR0 |= EDTRR0_TR; - ETHEREDRRR0 |= EDRRR0_RR; - start_stop = 1; - } else { - /* stop */ - ETHEREDTRR0 &= ~EDTRR0_TR; - ETHEREDRRR0 &= ~EDRRR0_RR; - start_stop = 0; - } -} - -int ethernetext_chk_link_mode(void) { - int32_t link; - uint16_t data; - - if ((phy_id & M_PHY_ID) == PHY_ID_LAN8710A) { - data = phy_reg_read(PHY_SP_CTL_STS_REG); - switch (((uint32_t)data >> 2) & 0x00000007) { - case 0x0001: - link = HALF_10M; - break; - case 0x0005: - link = FULL_10M; - break; - case 0x0002: - link = HALF_TX; - break; - case 0x0006: - link = FULL_TX; - break; - default: - link = NEGO_FAIL; - break; - } - } else { - link = NEGO_FAIL; - } - - return link; -} - -void ethernetext_set_link_mode(int32_t link) { - lan_reg_reset(); /* Resets the E-MAC,E-DMAC */ - lan_desc_create(); /* Initialize of buffer memory */ - lan_reg_set(link); /* E-DMAC, E-MAC initialization */ -} - -void ethernetext_add_multicast_group(const uint8_t *addr) { - uint32_t cnt; - uint32_t tmp_data_h; - uint32_t tmp_data_l; - - if (tsu_ten_tmp == 0xFFFFFFFF) { - ethernetext_set_all_multicast(1); - } else { - tmp_data_h = ((uint32_t)addr[0] << 24) | ((uint32_t)addr[1] << 16) | ((uint32_t)addr[2] << 8) | ((uint32_t)addr[3]); - tmp_data_l = ((uint32_t)addr[4] << 8) | ((uint32_t)addr[5]); - - for (cnt = 0; cnt < 32; cnt++) { - if ((tsu_ten_tmp & (0x80000000 >> cnt)) == 0) { - while ((ETHERTSU_ADSBSY & 0x00000001) != 0) { - ; - } - ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRH0 = tmp_data_h; - while ((ETHERTSU_ADSBSY & 0x00000001) != 0) { - ; - } - ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRL0 = tmp_data_l; - if ((ETHERECMR0 & 0x00002000) != 0) { - ETHERTSU_TEN |= (0x80000000 >> cnt); - } - tsu_ten_tmp |= (0x80000000 >> cnt); - break; - } - } - } -} - -void ethernetext_remove_multicast_group(const uint8_t *addr) { - uint32_t cnt; - uint32_t tmp_data_h; - uint32_t tmp_data_l; - - tmp_data_h = ((uint32_t)addr[0] << 24) | ((uint32_t)addr[1] << 16) | ((uint32_t)addr[2] << 8) | ((uint32_t)addr[3]); - tmp_data_l = ((uint32_t)addr[4] << 8) | ((uint32_t)addr[5]); - - for (cnt = 0; cnt< 32; cnt++) { - if ((ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRH0 == tmp_data_h) && - (ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRL0 == tmp_data_l)) { - while ((ETHERTSU_ADSBSY & 0x00000001) != 0) { - ; - } - ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRH0 = 0; - while ((ETHERTSU_ADSBSY & 0x00000001) != 0) { - ; - } - ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRL0 = 0; - - ETHERTSU_TEN &= ~(0x80000000 >> cnt); - tsu_ten_tmp &= ~(0x80000000 >> cnt); - break; - } - } -} - -void ethernetext_set_all_multicast(int all) { - if (all != 0) { - ETHERECMR0 &= ~(0x00002000); - ETHERTSU_TEN = 0x00000000; - } else { - ETHERECMR0 |= 0x00002000; - ETHERTSU_TEN = tsu_ten_tmp; - } -} - - -int ethernet_init() { - ethernet_cfg_t ethcfg; - - ethcfg.int_priority = 5; - ethcfg.recv_cb = NULL; - ethcfg.ether_mac = NULL; - ethernetext_init(ðcfg); - ethernet_set_link(-1, 0); /* Auto-Negotiation */ - - return 0; -} - -void ethernet_free() { - ETHERARSTR |= 0x00000001; /* ETHER software reset */ - CPGSTBCR7 |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */ -} - -int ethernet_write(const char *data, int slen) { - edmac_send_desc_t *p_send_desc; - int32_t copy_size; - - if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0) - || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) { - copy_size = 0; - } else { - p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */ - if ((p_send_desc->td0 & TD0_TACT) != 0) { - copy_size = 0; - } else { - copy_size = MAX_SEND_SIZE - tx_wite_offset; - if (copy_size > slen) { - copy_size = slen; - } - (void)memcpy(&p_send_desc->td2[tx_wite_offset], data, copy_size); - tx_wite_offset += copy_size; - } - } - - return copy_size; -} - -int ethernet_send() { - edmac_send_desc_t *p_send_desc; - int32_t ret; - - if ((p_eth_desc_dsend == NULL) || (tx_wite_offset <= 0)) { - ret = 0; - } else { - /* Transfer 1 frame */ - p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */ - - /* Sets the frame length */ - p_send_desc->td1 = ((uint32_t)tx_wite_offset << 16); - tx_wite_offset = 0; - - /* Sets the transmit descriptor to transmit again */ - p_send_desc->td0 &= (TD0_TACT | TD0_TDLE | TD0_TFP_TOP_BOTTOM); - p_send_desc->td0 |= TD0_TACT; - if ((start_stop == 1) && ((ETHEREDTRR0 & EDTRR0_TR) != EDTRR0_TR)) { - ETHEREDTRR0 |= EDTRR0_TR; - } - - /* Update the current descriptor */ - send_top_index++; - if (send_top_index >= NUM_OF_TX_DESCRIPTOR) { - send_top_index = 0; - } - ret = 1; - } - - return ret; -} - -int ethernet_receive() { - edmac_recv_desc_t *p_recv_desc; - int32_t receive_size = 0; - - if (p_eth_desc_drecv != NULL) { - if (p_recv_end_desc != NULL) { - /* Sets the receive descriptor to receive again */ - p_recv_end_desc->rd0 &= (RD0_RACT | RD0_RDLE); - p_recv_end_desc->rd0 |= RD0_RACT; - if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) { - ETHEREDRRR0 |= EDRRR0_RR; - } - p_recv_end_desc = NULL; - } - - p_recv_desc = &p_eth_desc_drecv[recv_top_index]; /* Current descriptor */ - if ((p_recv_desc->rd0 & RD0_RACT) == 0) { - /* Receives 1 frame */ - if (((p_recv_desc->rd0 & RD0_RFE) != 0) && ((p_recv_desc->rd0 & RD0_RFS_ERROR) != 0)) { - /* Receive frame error */ - /* Sets the receive descriptor to receive again */ - p_recv_desc->rd0 &= (RD0_RACT | RD0_RDLE); - p_recv_desc->rd0 |= RD0_RACT; - if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) { - ETHEREDRRR0 |= EDRRR0_RR; - } - } else { - /* Copies the received frame */ - rx_read_offset = 0; - p_recv_end_desc = p_recv_desc; - receive_size = (p_recv_desc->rd1 & RD1_RDL_MSK); /* number of bytes received */ - } - - /* Update the current descriptor */ - recv_top_index++; - if (recv_top_index >= NUM_OF_TX_DESCRIPTOR) { - recv_top_index = 0; - } - } - } - - return receive_size; -} - -int ethernet_read(char *data, int dlen) { - edmac_recv_desc_t *p_recv_desc = p_recv_end_desc; /* Read top descriptor */ - int32_t copy_size; - - if ((data == NULL) || (dlen < 0) || (p_recv_desc == NULL)) { - copy_size = 0; - } else { - copy_size = (p_recv_desc->rd1 & RD1_RDL_MSK) - rx_read_offset; - if (copy_size > dlen) { - copy_size = dlen; - } - (void)memcpy(data, &p_recv_desc->rd2[rx_read_offset], (size_t)copy_size); - rx_read_offset += copy_size; - } - - return copy_size; -} - -void ethernet_address(char *mac) { - if (mac != NULL) { - mbed_mac_address(mac); /* Get MAC Address */ - } -} - -int ethernet_link(void) { - int32_t ret; - uint16_t data; - - data = phy_reg_read(BASIC_MODE_STATUS_REG); - if (((uint32_t)data & BASIC_STS_MSK_LINK) != 0) { - ret = 1; - } else { - ret = 0; - } - - return ret; -} - -void ethernet_set_link(int speed, int duplex) { - uint16_t data; - int32_t i; - int32_t link; - - if ((speed < 0) || (speed > 1)) { - data = 0x1000; /* Auto-Negotiation Enable */ - phy_reg_write(BASIC_MODE_CONTROL_REG, data); - for (i = 0; i < 1000; i++) { - data = phy_reg_read(BASIC_MODE_STATUS_REG); - if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) { - break; - } - wait_100us(10); - } - } else { - data = (uint16_t)(((uint32_t)speed << 13) | ((uint32_t)duplex << 8)); - phy_reg_write(BASIC_MODE_CONTROL_REG, data); - wait_100us(1); - } - - link = ethernetext_chk_link_mode(); - ethernetext_set_link_mode(link); -} - -void INT_Ether(void) { - uint32_t stat_edmac; - uint32_t stat_etherc; - - /* Clear the interrupt request flag */ - stat_edmac = (ETHEREESR0 & ETHEREESIPR0); /* Targets are restricted to allowed interrupts */ - ETHEREESR0 = stat_edmac; - /* Reception-related */ - if (stat_edmac & EDMAC_EESIPR_INI_RECV) { - if (p_recv_cb_fnc != NULL) { - p_recv_cb_fnc(); - } - } - /* E-MAC-related */ - if (stat_edmac & EDMAC_EESIPR_INI_EtherC) { - /* Clear the interrupt request flag */ - stat_etherc = (ETHERECSR0 & ETHERECSIPR0); /* Targets are restricted to allowed interrupts */ - ETHERECSR0 = stat_etherc; - } -} - -static void lan_reg_reset(void) { - volatile int32_t j = 400; /* Wait for B dia 256 cycles ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */ - - ETHERARSTR |= 0x00000001; /* ETHER software reset */ - while (j--) { - /* Do Nothing */ - } - - ETHEREDSR0 |= 0x00000003; /* E-DMAC software reset */ - ETHEREDMR0 |= 0x00000003; /* Set SWRR and SWRT simultaneously */ - - /* Check clear software reset */ - while ((ETHEREDMR0 & 0x00000003) != 0) { - /* Do Nothing */ - } -} - -static void lan_desc_create(void) { - int32_t i; - uint8_t *p_memory_top; - - (void)memset((void *)ethernet_nc_memory, 0, sizeof(ethernet_nc_memory)); - p_memory_top = ethernet_nc_memory; - - /* Descriptor area configuration */ - p_eth_desc_dsend = (edmac_send_desc_t *)p_memory_top; - p_memory_top += (sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR); - p_eth_desc_drecv = (edmac_recv_desc_t *)p_memory_top; - p_memory_top += (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR); - - /* Transmit descriptor */ - for (i = 0; i < NUM_OF_TX_DESCRIPTOR; i++) { - p_eth_desc_dsend[i].td2 = p_memory_top; /* TD2 TBA */ - p_memory_top += SIZE_OF_BUFFER; - p_eth_desc_dsend[i].td1 = 0; /* TD1 TDL */ - p_eth_desc_dsend[i].td0 = TD0_TFP_TOP_BOTTOM; /* TD0:1frame/1buf1buf, transmission disabled */ - } - p_eth_desc_dsend[i - 1].td0 |= TD0_TDLE; /* Set the last descriptor */ - - /* Receive descriptor */ - for (i = 0; i < NUM_OF_RX_DESCRIPTOR; i++) { - p_eth_desc_drecv[i].rd2 = p_memory_top; /* RD2 RBA */ - p_memory_top += SIZE_OF_BUFFER; - p_eth_desc_drecv[i].rd1 = ((uint32_t)SIZE_OF_BUFFER << 16); /* RD1 RBL */ - p_eth_desc_drecv[i].rd0 = RD0_RACT; /* RD0:reception enabled */ - } - p_eth_desc_drecv[i - 1].rd0 |= RD0_RDLE; /* Set the last descriptor */ - - /* Initialize descriptor management information */ - send_top_index = 0; - recv_top_index = 0; - rx_read_offset = 0; - tx_wite_offset = 0; - p_recv_end_desc = NULL; -} - -static void lan_reg_set(int32_t link) { - /* MAC address setting */ - ETHERMAHR0 = ((uint8_t)mac_addr[0] << 24) - | ((uint8_t)mac_addr[1] << 16) - | ((uint8_t)mac_addr[2] << 8) - | (uint8_t)mac_addr[3]; - ETHERMALR0 = ((uint8_t)mac_addr[4] << 8) - | (uint8_t)mac_addr[5]; - - /* E-DMAC */ - ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0]; - ETHERRDLAR0 = (uint32_t)&p_eth_desc_drecv[0]; - ETHERTDFAR0 = (uint32_t)&p_eth_desc_dsend[0]; - ETHERRDFAR0 = (uint32_t)&p_eth_desc_drecv[0]; - ETHERTDFXR0 = (uint32_t)&p_eth_desc_dsend[NUM_OF_TX_DESCRIPTOR - 1]; - ETHERRDFXR0 = (uint32_t)&p_eth_desc_drecv[NUM_OF_RX_DESCRIPTOR - 1]; - ETHERTDFFR0 |= 0x00000001; /* TDLF Transmit Descriptor Queue Last Flag : Last descriptor (1) */ - ETHERRDFFR0 |= 0x00000001; /* RDLF Receive Descriptor Queue Last Flag : Last descriptor (1) */ - ETHEREDMR0 |= 0x00000040; /* Little endian */ - ETHERTRSCER0 &= ~0x0003009F; /* All clear */ - ETHERTFTR0 &= ~0x000007FF; /* TFT[10:0] Transmit FIFO Threshold : Store and forward modes (H'000) */ - ETHERFDR0 |= 0x00000707; /* Transmit FIFO Size:2048 bytes, Receive FIFO Size:2048 bytes */ - ETHERRMCR0 |= 0x00000001; /* RNC Receive Enable Control : Continuous reception enabled (1) */ - ETHERFCFTR0 &= ~0x001F00FF; - ETHERFCFTR0 |= 0x00070007; - ETHERRPADIR0 &= ~0x001FFFFF; /* Padding Size:No padding insertion, Padding Slot:Inserts at first byte */ - - /* E-MAC */ - ETHERECMR0 &= ~0x04BF2063; /* All clear */ - ETHERRFLR0 &= ~0x0003FFFF; /* RFL[17:0] Receive Frame Length : 1518 bytes (H'00000) */ - ETHERAPR0 &= ~0x0000FFFF; /* AP[15:0] Automatic PAUSE : Flow control is disabled (H'0000) */ - ETHERMPR0 &= ~0x0000FFFF; /* MP[15:0] Manual PAUSE : Flow control is disabled (H'0000) */ - ETHERTPAUSER0 &= ~0x0000FFFF; /* Upper Limit for Automatic PAUSE Frame : Retransmit count is unlimited */ - ETHERCSMR &= ~0xC000003F; /* The result of checksum is not written back to the receive descriptor */ - if ((link == FULL_TX) || (link == FULL_10M) || (link == NEGO_FAIL)) { - ETHERECMR0 |= 0x00000002; /* Set to full-duplex mode */ - } else { - ETHERECMR0 &= ~0x00000002; /* Set to half-duplex mode */ - } - ETHERECMR0 |= 0x00002000; /* MCT = 1 */ - - /* Interrupt-related */ - if (p_recv_cb_fnc != NULL) { - ETHEREESR0 |= 0xFF7F009F; /* Clear all status (by writing 1) */ - ETHEREESIPR0 |= 0x00040000; /* FR Frame Reception (1) */ - ETHERECSR0 |= 0x00000011; /* Clear all status (clear by writing 1) */ - ETHERECSIPR0 &= ~0x00000011; /* PFROIP Disable, ICDIP Disable */ - InterruptHandlerRegister(ETHERI_IRQn, INT_Ether); /* Ethernet interrupt handler registration */ - GIC_SetPriority(ETHERI_IRQn, Interrupt_priority); /* Ethernet interrupt priority */ - GIC_SetConfiguration(ETHERI_IRQn, 1); - GIC_EnableIRQ(ETHERI_IRQn); /* Enables the E-DMAC interrupt */ - } - - ETHERECMR0 |= 0x00000060; /* RE Enable, TE Enable */ - - /* Enable transmission/reception */ - if ((start_stop == 1) && ((ETHEREDRRR0 & 0x00000001) == 0)) { - ETHEREDRRR0 |= 0x00000001; /* RR */ - } -} - -static uint16_t phy_reg_read(uint16_t reg_addr) { - uint16_t data; - - mii_preamble(); - mii_cmd(reg_addr, PHY_READ); - mii_z(); - mii_reg_read(&data); - mii_z(); - - return data; -} - -static void phy_reg_write(uint16_t reg_addr, uint16_t data) { - mii_preamble(); - mii_cmd(reg_addr, PHY_WRITE); - mii_write_1(); - mii_write_0(); - mii_reg_write(data); - mii_z(); -} - -static void mii_preamble(void) { - int32_t i = 32; - - for (i = 32; i > 0; i--) { - /* 1 is output via the MII (Media Independent Interface) block. */ - mii_write_1(); - } -} - -static void mii_cmd(uint16_t reg_addr, uint32_t option) { - int32_t i; - uint16_t data = 0; - - data |= (PHY_ST << 14); /* ST code */ - data |= (option << 12); /* OP code */ - data |= (PHY_ADDR << 7); /* PHY Address */ - data |= (uint16_t)(reg_addr << 2); /* Reg Address */ - for (i = 14; i > 0; i--) { - if ((data & 0x8000) == 0) { - mii_write_0(); - } else { - mii_write_1(); - } - data <<= 1; - } -} - -static void mii_reg_read(uint16_t *data) { - int32_t i; - uint16_t reg_data = 0; - - /* Data are read in one bit at a time */ - for (i = 16; i > 0; i--) { - set_ether_pir(PIR0_MDC_LOW); - set_ether_pir(PIR0_MDC_HIGH); - reg_data <<= 1; - reg_data |= (uint16_t)((ETHERPIR0 & PIR0_MDI) >> 3); /* MDI read */ - set_ether_pir(PIR0_MDC_HIGH); - set_ether_pir(PIR0_MDC_LOW); - } - *data = reg_data; -} - -static void mii_reg_write(uint16_t data) { - int32_t i; - - /* Data are written one bit at a time */ - for (i = 16; i > 0; i--) { - if ((data & 0x8000) == 0) { - mii_write_0(); - } else { - mii_write_1(); - } - data <<= 1; - } -} - -static void mii_z(void) { - set_ether_pir(PIR0_MDC_LOW); - set_ether_pir(PIR0_MDC_HIGH); - set_ether_pir(PIR0_MDC_HIGH); - set_ether_pir(PIR0_MDC_LOW); -} - -static void mii_write_1(void) { - set_ether_pir(PIR0_MDO | PIR0_MMD); - set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC); - set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC); - set_ether_pir(PIR0_MDO | PIR0_MMD); -} - -static void mii_write_0(void) { - set_ether_pir(PIR0_MMD); - set_ether_pir(PIR0_MMD | PIR0_MDC); - set_ether_pir(PIR0_MMD | PIR0_MDC); - set_ether_pir(PIR0_MMD); -} - -static void set_ether_pir(uint32_t set_data) { - int32_t i; - - for (i = MDC_WAIT; i > 0; i--) { - ETHERPIR0 = set_data; - } -} - -static void wait_100us(int32_t wait_cnt) { - volatile int32_t j = LOOP_100us * wait_cnt; - - while (--j) { - /* Do Nothing */ - } -} -#endif /* DEVICE_ETHERNET */