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Merge pull request #5140 from ARMmbed/release-candidate 

Release candidate for mbed-os-5.6.0-rc2
pull/5394/head mbed-os-5.6.0-rc2
Jimmy Brisson 2017-09-19 16:51:54 -05:00 committed by GitHub
parent 411b7fd63f de0e99cf11
commit 6e087488e1
37 changed files with 526 additions and 86 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
features/FEATURE_LWIP/TESTS/mbedmicro-net/tcp_hello_world/main.cpp
View File

@ -33,7 +33,7 @@ using namespace utest::v1;
namespace {
// Test connection information
const char *HTTP_SERVER_NAME = "developer.mbed.org";
const char *HTTP_SERVER_NAME = "os.mbed.com";
const char *HTTP_SERVER_FILE_PATH = "/media/uploads/mbed_official/hello.txt";
const int HTTP_SERVER_PORT = 80;
#if defined(TARGET_VK_RZ_A1H)

5
features/FEATURE_LWIP/lwip-interface/mbed_lib.json
View File

@ -84,5 +84,10 @@
"help": "Thread stack size for PPP",
"value": 768
}
},
"target_overrides": {
"REALTEK_RTL8195AM": {
"tcpip-thread-stacksize": 1600
}
}
}

4
features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp
View File

@ -141,7 +141,7 @@ static void CMT_URC(ATCmdParser *at)
static bool set_atd(ATCmdParser *at)
{
bool success = at->send("ATD*99***" CTX"#") && at->recv("CONNECT");
bool success = at->send("ATD*99***" CTX "#") && at->recv("CONNECT");
return success;
}
@ -469,7 +469,7 @@ retry_without_dual_stack:
#endif
success = _at->send("AT"
"+FCLASS=0;" // set to connection (ATD) to data mode
"+CGDCONT=" CTX",\"%s\",\"%s%s\"",
"+CGDCONT=" CTX ",\"%s\",\"%s%s\"",
pdp_type, auth, _apn
)
&& _at->recv("OK");

8
rtos/TARGET_CORTEX/mbed_rtx_idle.cpp
View File

@ -195,6 +195,14 @@ static void default_idle_hook(void)
core_util_critical_section_exit();
}
#elif defined(FEATURE_UVISOR)
static void default_idle_hook(void)
{
/* uVisor can't sleep. See <https://github.com/ARMmbed/uvisor/issues/420>
* for details. */
}
#else
static void default_idle_hook(void)

298
rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_ARM/irq_armv8mbl.S Normal file
View File

@ -0,0 +1,298 @@
;/*
; * Copyright (c) 2016-2017 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; *
; * -----------------------------------------------------------------------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: ARMv8M Baseline Exception handlers
; *
; * -----------------------------------------------------------------------------
; */
I_T_RUN_OFS EQU 28 ; osInfo.thread.run offset
TCB_SM_OFS EQU 48 ; TCB.stack_mem offset
TCB_SP_OFS EQU 56 ; TCB.SP offset
TCB_SF_OFS EQU 34 ; TCB.stack_frame offset
TCB_TZM_OFS EQU 64 ; TCB.tz_memory offset
PRESERVE8
THUMB
AREA |.constdata|, DATA, READONLY
EXPORT irqRtxLib
irqRtxLib DCB 0 ; Non weak library reference
AREA |.text|, CODE, READONLY
SVC_Handler PROC
EXPORT SVC_Handler
IMPORT osRtxUserSVC
IMPORT osRtxInfo
#ifdef __DOMAIN_NS
IMPORT TZ_LoadContext_S
IMPORT TZ_StoreContext_S
#endif
MRS R0,PSP ; Get PSP
LDR R1,[R0,#24] ; Load saved PC from stack
SUBS R1,R1,#2 ; Point to SVC instruction
LDRB R1,[R1] ; Load SVC number
CMP R1,#0
BNE SVC_User ; Branch if not SVC 0
PUSH {R0,LR} ; Save PSP and EXC_RETURN
LDM R0,{R0-R3} ; Load function parameters from stack
BLX R7 ; Call service function
POP {R2,R3} ; Restore PSP and EXC_RETURN
STMIA R2!,{R0-R1} ; Store function return values
MOV LR,R3 ; Set EXC_RETURN
SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
LDMIA R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
BEQ SVC_Exit ; Branch when threads are the same
CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted
SVC_ContextSave
#ifdef __DOMAIN_NS
LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CBZ R0,SVC_ContextSave1 ; Branch if there is no secure context
PUSH {R1,R2,R3,R7} ; Save registers
MOV R7,LR ; Get EXC_RETURN
BL TZ_StoreContext_S ; Store secure context
MOV LR,R7 ; Set EXC_RETURN
POP {R1,R2,R3,R7} ; Restore registers
#endif
SVC_ContextSave1
MRS R0,PSP ; Get PSP
SUBS R0,R0,#32 ; Adjust PSP
STR R0,[R1,#TCB_SP_OFS] ; Store SP
STMIA R0!,{R4-R7} ; Save R4..R7
MOV R4,R8
MOV R5,R9
MOV R6,R10
MOV R7,R11
STMIA R0!,{R4-R7} ; Save R8..R11
SVC_ContextSave2
MOV R0,LR ; Get EXC_RETURN
ADDS R1,R1,#TCB_SF_OFS ; Adjust address
STRB R0,[R1] ; Store stack frame information
SVC_ContextSwitch
SUBS R3,R3,#8 ; Adjust address
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
SVC_ContextRestore
#ifdef __DOMAIN_NS
LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CBZ R0,SVC_ContextRestore1 ; Branch if there is no secure context
PUSH {R2,R3} ; Save registers
BL TZ_LoadContext_S ; Load secure context
POP {R2,R3} ; Restore registers
#endif
SVC_ContextRestore1
MOV R1,R2
ADDS R1,R1,#TCB_SF_OFS ; Adjust address
LDRB R0,[R1] ; Load stack frame information
MOVS R1,#0xFF
MVNS R1,R1 ; R1=0xFFFFFF00
ORRS R0,R1
MOV LR,R0 ; Set EXC_RETURN
#ifdef __DOMAIN_NS
LSLS R0,R0,#25 ; Check domain of interrupted thread
BPL SVC_ContextRestore2 ; Branch if non-secure
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
MSR PSP,R0 ; Set PSP
BX LR ; Exit from handler
#else
LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base
MSR PSPLIM,R0 ; Set PSPLIM
#endif
SVC_ContextRestore2
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
ADDS R0,R0,#16 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R8..R11
MOV R8,R4
MOV R9,R5
MOV R10,R6
MOV R11,R7
MSR PSP,R0 ; Set PSP
SUBS R0,R0,#32 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R4..R7
SVC_Exit
BX LR ; Exit from handler
SVC_User
PUSH {R4,LR} ; Save registers
LDR R2,=osRtxUserSVC ; Load address of SVC table
LDR R3,[R2] ; Load SVC maximum number
CMP R1,R3 ; Check SVC number range
BHI SVC_Done ; Branch if out of range
LSLS R1,R1,#2
LDR R4,[R2,R1] ; Load address of SVC function
LDM R0,{R0-R3} ; Load function parameters from stack
BLX R4 ; Call service function
MRS R4,PSP ; Get PSP
STR R0,[R4] ; Store function return value
SVC_Done
POP {R4,PC} ; Return from handler
ALIGN
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler
IMPORT osRtxPendSV_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
B Sys_Context
ALIGN
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler
IMPORT osRtxTick_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
B Sys_Context
ALIGN
ENDP
Sys_Context PROC
EXPORT Sys_Context
IMPORT osRtxInfo
#ifdef __DOMAIN_NS
IMPORT TZ_LoadContext_S
IMPORT TZ_StoreContext_S
#endif
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
LDM R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
BEQ Sys_ContextExit ; Branch when threads are the same
Sys_ContextSave
#ifdef __DOMAIN_NS
LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CBZ R0,Sys_ContextSave1 ; Branch if there is no secure context
PUSH {R1,R2,R3,R7} ; Save registers
MOV R7,LR ; Get EXC_RETURN
BL TZ_StoreContext_S ; Store secure context
MOV LR,R7 ; Set EXC_RETURN
POP {R1,R2,R3,R7} ; Restore registers
LSLS R7,R7,#25 ; Check domain of interrupted thread
BMI Sys_ContextSave1 ; Branch if secure
MRS R0,PSP ; Get PSP
STR R0,[R1,#TCB_SP_OFS] ; Store SP
B Sys_ContextSave2
#endif
Sys_ContextSave1
MRS R0,PSP ; Get PSP
SUBS R0,R0,#32 ; Adjust address
STR R0,[R1,#TCB_SP_OFS] ; Store SP
STMIA R0!,{R4-R7} ; Save R4..R7
MOV R4,R8
MOV R5,R9
MOV R6,R10
MOV R7,R11
STMIA R0!,{R4-R7} ; Save R8..R11
Sys_ContextSave2
MOV R0,LR ; Get EXC_RETURN
ADDS R1,R1,#TCB_SF_OFS ; Adjust address
STRB R0,[R1] ; Store stack frame information
Sys_ContextSwitch
SUBS R3,R3,#8 ; Adjust address
STR R2,[R3] ; osRtxInfo.run: curr = next
Sys_ContextRestore
#ifdef __DOMAIN_NS
LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CBZ R0,Sys_ContextRestore1 ; Branch if there is no secure context
PUSH {R2,R3} ; Save registers
BL TZ_LoadContext_S ; Load secure context
POP {R2,R3} ; Restore registers
#endif
Sys_ContextRestore1
MOV R1,R2
ADDS R1,R1,#TCB_SF_OFS ; Adjust offset
LDRB R0,[R1] ; Load stack frame information
MOVS R1,#0xFF
MVNS R1,R1 ; R1=0xFFFFFF00
ORRS R0,R1
MOV LR,R0 ; Set EXC_RETURN
#ifdef __DOMAIN_NS
LSLS R0,R0,#25 ; Check domain of interrupted thread
BPL Sys_ContextRestore2 ; Branch if non-secure
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
MSR PSP,R0 ; Set PSP
BX LR ; Exit from handler
#else
LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base
MSR PSPLIM,R0 ; Set PSPLIM
#endif
Sys_ContextRestore2
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
ADDS R0,R0,#16 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R8..R11
MOV R8,R4
MOV R9,R5
MOV R10,R6
MOV R11,R7
MSR PSP,R0 ; Set PSP
SUBS R0,R0,#32 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R4..R7
Sys_ContextExit
BX LR ; Exit from handler
ALIGN
ENDP
END

2
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct
View File

@ -19,7 +19,7 @@ LR_IROM1 0x1B000 0x0025000 {
.ANY (+RO)
}
RW_IRAM0 0x20002ef8 UNINIT 0x000000c0 { ;no init section
*(noinit)
*(*noinit)
}
RW_IRAM1 0x20002FB8 0x00005048 {
.ANY (+RW +ZI)

2
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct
View File

@ -19,7 +19,7 @@ LR_IROM1 0x18000 0x0028000 {
.ANY (+RO)
}
RW_IRAM0 0x20002000 UNINIT 0x000000c0 { ;no init section
*(noinit)
*(*noinit)
}
RW_IRAM1 0x200020C0 0x00001F40 {
.ANY (+RW +ZI)

2
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct
View File

@ -19,7 +19,7 @@ LR_IROM1 0x0001B000 0x0025000 {
.ANY (+RO)
}
RW_IRAM0 0x20002ef8 UNINIT 0x000000c0 { ;no init section
*(noinit)
*(*noinit)
}
RW_IRAM1 0x20002FB8 0x00001048 {
.ANY (+RW +ZI)

2
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/nRF52832.sct
View File

@ -19,7 +19,7 @@ LR_IROM1 0x1C000 0x0064000 {
.ANY (+RO)
}
RW_IRAM0 0x20002EF8 UNINIT 0x000000D8 { ;no init section
*(noinit)
*(*noinit)
}
RW_IRAM1 0x20002FD0 0x0000D030 {
.ANY (+RW +ZI)

2
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52832.sct
View File

@ -5,7 +5,7 @@ LR_IROM1 0x21000 0x00DF000 {
.ANY (+RO)
}
RW_IRAM0 0x20003288 UNINIT 0x000000F8 { ;no init section
*(noinit)
*(*noinit)
}
RW_IRAM1 0x20003380 0x0003cc80 {
.ANY (+RW +ZI)

4
targets/TARGET_NORDIC/TARGET_NRF5/reloc_vector_table.c
View File

@ -42,8 +42,8 @@
#include "nrf_sdm.h"
#include "section_vars.h"
#if defined(__CC_ARM)
__attribute__ ((section("noinit"),zero_init))
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
__attribute__ ((section(".bss.noinit"),zero_init))
uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS];
#elif defined(__GNUC__)
__attribute__ ((section(".noinit")))

2
targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp
View File

@ -28,7 +28,7 @@
#include "osdep_service.h"
typedef struct _wifi_scan_hdl {
void *scan_sema;
_sema scan_sema;
nsapi_size_t ap_num;
nsapi_size_t scan_num;
WiFiAccessPoint *ap_details;

BIN
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_wlan_mbed_arm.ar
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Binary file not shown.

31
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a_startup.S Normal file
View File

@ -0,0 +1,31 @@
;
; Copyright (c) 2017 Realtek Semiconductor Corp.
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
PRESERVE8
THUMB
AREA |i.PLAT_Start|, CODE, READONLY
PLAT_Start PROC
EXPORT PLAT_Start
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
IMPORT PLAT_Init
LDR SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
LDR R0, =PLAT_Init
BX R0
ENDP
ALIGN
END

BIN
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_wlan_mbed_gcc.a
View File

Binary file not shown.

32
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a_startup.S Normal file
View File

@ -0,0 +1,32 @@
/*
* Copyright (c) 2017 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
.syntax unified
.thumb
.global __StackTop
.global PLAT_Init
/* entry point of application image */
.section .text.PLAT_Start
.weak PLAT_Start
.type PLAT_Start, %function
PLAT_Start:
ldr sp, =__StackTop
ldr r0, =PLAT_Init
bx r0
.size PLAT_Start, .-PLAT_Start
.end

BIN
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_wlan_mbed_iar.a
View File

Binary file not shown.

31
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a_startup.S Normal file
View File

@ -0,0 +1,31 @@
;
; Copyright (c) 2017 Realtek Semiconductor Corp.
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
MODULE ?cstartup
SECTION .text:CODE:NOROOT:REORDER(2)
EXTERN CSTACK$$Limit
EXTERN PLAT_Init
; Default image 2 entry
THUMB
PUBWEAK PLAT_Start
PLAT_Start
LDR SP, =CSTACK$$Limit
LDR R0, =PLAT_Init
BX R0
END

6
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_compiler.h
View File

@ -29,6 +29,12 @@
#define __romcall
#define __longcall
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#ifndef __longcall
#define __longcall
#endif
#elif defined(__CC_ARM)
#ifndef __longcall

24
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c
View File

@ -29,7 +29,6 @@
#if defined(__CC_ARM) || \
(defined (__ARMCC_VERSION) && __ARMCC_VERSION >= 6010050)
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
extern uint8_t Image$$RW_IRAM2$$ZI$$Base[];
extern uint8_t Image$$RW_IRAM2$$ZI$$Limit[];
extern uint8_t Image$$TCM_OVERLAY$$ZI$$Base[];
@ -42,13 +41,11 @@ extern uint8_t Image$$RW_DRAM2$$ZI$$Limit[];
#define __bss_dtcm_end__ Image$$TCM_OVERLAY$$ZI$$Limit
#define __bss_dram_start__ Image$$RW_DRAM2$$ZI$$Base
#define __bss_dram_end__ Image$$RW_DRAM2$$ZI$$Limit
#define __stackp Image$$ARM_LIB_STACK$$ZI$$Limit
#elif defined (__ICCARM__)
#pragma section=".ram.bss"
extern uint32_t CSTACK$$Limit;
uint8_t *__bss_start__;
uint8_t *__bss_end__;
@ -57,12 +54,9 @@ void __iar_data_init_app(void)
__bss_start__ = (uint8_t *)__section_begin(".ram.bss");
__bss_end__ = (uint8_t *)__section_end(".ram.bss");
}
#define __stackp CSTACK$$Limit
#else
extern uint32_t __StackTop;
extern uint32_t __StackLimit;
extern uint8_t __bss_sram_start__[];
extern uint8_t __bss_sram_end__[];
extern uint8_t __bss_dtcm_start__[];
@ -70,7 +64,6 @@ extern uint8_t __bss_dtcm_end__[];
extern uint8_t __bss_dram_start__[];
extern uint8_t __bss_dram_end__[];
#define __stackp __StackTop
#endif
extern VECTOR_Func NewVectorTable[];
@ -175,16 +168,19 @@ void TRAP_HardFaultHandler_Patch(void)
extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n);
// Image2 Entry Function
void PLAT_Start(void)
void PLAT_Init(void)
{
uint32_t val;
#if defined (__ICCARM__)
__iar_data_init_app();
// Overwrite vector table
NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler;
#if defined ( __ICCARM__ )
NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch;
#endif
// Clear RAM BSS
#if defined (__ICCARM__)
__iar_data_init_app();
__rtl_memset_v1_00((void *)__bss_start__, 0, __bss_end__ - __bss_start__);
#else
__rtl_memset_v1_00((void *)__bss_sram_start__, 0, __bss_sram_end__ - __bss_sram_start__);
@ -192,14 +188,6 @@ void PLAT_Start(void)
__rtl_memset_v1_00((void *)__bss_dram_start__, 0, __bss_dram_end__ - __bss_dram_start__);
#endif
// Set MSP
__set_MSP((uint32_t)&__stackp - 0x100);
// Overwrite vector table
NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler;
#if defined ( __ICCARM__ )
NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch;
#endif
extern HAL_TIMER_OP_EXT HalTimerOpExt;
__rtl_memset_v1_00((void *)&HalTimerOpExt, 0, sizeof(HalTimerOpExt));
__rtl_memset_v1_00((void *)&HalTimerOp, 0, sizeof(HalTimerOp));

5
targets/TARGET_Realtek/TARGET_AMEBA/rtw_emac.cpp
View File

@ -218,10 +218,7 @@ emac_interface_t *wlan_emac_init_interface()
if (_emac == NULL) {
_emac = (emac_interface_t*) malloc(sizeof(emac_interface_t));
if (_emac == NULL) {//new emac_interface_t fail
printf("emac initialization failed\r\n");
return NULL;
}
MBED_ASSERT(_emac);
_emac->hw = NULL;
memcpy((void*)&_emac->ops, &wlan_emac_interface, sizeof(wlan_emac_interface));
}

2
targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/rtx2/rtx2_service.c
View File

@ -548,7 +548,7 @@ _func_exit_;
static u32 _rtx2_get_current_time(void)
{
return osKernelGetTickCount();
return osKernelGetSysTimerCount();
}
static u32 _rtx2_systime_to_ms(u32 systime)

17
targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/common/bsp/basic_types.h
View File

@ -206,6 +206,23 @@ typedef __kernel_ssize_t SSIZE_T;
#define _LONG_CALL_ROM_ _LONG_CALL_
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define SECTION(_name) __attribute__ ((__section__(_name)))
#define ALIGNMTO(_bound) __attribute__ ((aligned (_bound)))
#define _PACKED_ __attribute__ ((packed))
#ifdef CONFIG_RELEASE_BUILD_LIBRARIES
#define _LONG_CALL_
#define _LONG_CALL_ROM_
#ifdef E_CUT_ROM_DOMAIN
#undef _LONG_CALL_ROM_
#define _LONG_CALL_ROM_
#endif
#else
#define _LONG_CALL_
#define _LONG_CALL_ROM_ _LONG_CALL_
#endif
#define _WEAK __attribute__ ((weak))
#else
#define SECTION(_name) __attribute__ ((__section__(_name)))
#define ALIGNMTO(_bound) __attribute__ ((aligned (_bound)))

56
targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c
View File

@ -23,24 +23,33 @@
#define SYS_TIM_ID 1 // the G-Timer ID for System
#define APP_TIM_ID 6 // the G-Timer ID for Application
#define TICK_TO_US(x) (uint64_t)(((x)/2) * 61 + ((x)%2) * TIMER_TICK_US)
static int us_ticker_inited = 0;
static TIMER_ADAPTER TimerAdapter;
extern HAL_TIMER_OP HalTimerOp;
extern HAL_TIMER_OP_EXT HalTimerOpExt;
VOID _us_ticker_irq_handler(IN VOID *Data)
VOID _us_ticker_irq_handler(void *Data)
{
us_ticker_irq_handler();
HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId);
}
void us_ticker_init(void)
{
if (us_ticker_inited) return;
if (us_ticker_inited){
return;
}
us_ticker_inited = 1;
HalTimerOp.HalTimerDis(SYS_TIM_ID);
HalTimerOpExt.HalTimerReLoad(SYS_TIM_ID, 0xFFFFFFFFUL);
HalTimerOp.HalTimerEn(SYS_TIM_ID);
// Initial a G-Timer
TimerAdapter.IrqDis = 0; // Enable Irq @ initial
TimerAdapter.IrqHandle.IrqFun = (IRQ_FUN) _us_ticker_irq_handler;
@ -52,50 +61,45 @@ void us_ticker_init(void)
TimerAdapter.TimerLoadValueUs = 0xFFFFFFFF;
TimerAdapter.TimerMode = USER_DEFINED;
HalTimerOp.HalTimerInit((VOID*) &TimerAdapter);
HalTimerOp.HalTimerInit((void *) &TimerAdapter);
DBG_TIMER_INFO("%s: Timer_Id=%d\n", __FUNCTION__, APP_TIM_ID);
}
uint32_t us_ticker_read()
uint32_t us_ticker_read(void)
{
uint32_t tick_cnt;
uint32_t ticks_125ms;
uint32_t ticks_remain;
uint64_t us_tick;
uint64_t tick_us;
if (!us_ticker_inited) {
us_ticker_init();
}
tick_cnt = HalTimerOp.HalTimerReadCount(SYS_TIM_ID);
tick_cnt = 0xffffffff - tick_cnt; // it's a down counter
ticks_125ms = tick_cnt/(GTIMER_CLK_HZ/8); //use 125ms as a intermediate unit;
ticks_remain = tick_cnt - (ticks_125ms*(GTIMER_CLK_HZ/8)); //calculate the remainder
us_tick = ticks_125ms * 125000; //change unit to us, 125ms is 125000 us
us_tick += (ticks_remain * 1000000)/GTIMER_CLK_HZ; //also use us as unit
tick_us = TICK_TO_US(0xFFFFFFFFUL - tick_cnt);
return ((uint32_t)us_tick); //return ticker value in micro-seconds (us)
return ((uint32_t)tick_us); //return ticker value in micro-seconds (us)
}
void us_ticker_set_interrupt(timestamp_t timestamp)
{
uint32_t cur_time_us;
uint32_t time_dif;
uint32_t time_cur;
uint32_t time_cnt;
HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId);
cur_time_us = us_ticker_read();
if ((uint32_t)timestamp > cur_time_us) {
time_dif = (uint32_t)timestamp - cur_time_us;
time_cur = us_ticker_read();
if (timestamp > time_cur + TIMER_TICK_US) {
time_cnt = timestamp - time_cur;
} else {
HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, 0xffffffff);
HalTimerOpExt.HalTimerIrqEn((u32)TimerAdapter.TimerId);
HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId);
NVIC_SetPendingIRQ(TIMER2_7_IRQ);
us_ticker_fire_interrupt();
return;
}
TimerAdapter.TimerLoadValueUs = time_dif;
HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, time_dif / TIMER_TICK_US);
HalTimerOpExt.HalTimerIrqEn((u32)TimerAdapter.TimerId);
TimerAdapter.TimerLoadValueUs = time_cnt / TIMER_TICK_US;
HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, TimerAdapter.TimerLoadValueUs);
HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId);
}
void us_ticker_fire_interrupt(void)

1
tools/export/__init__.py
View File

@ -310,6 +310,7 @@ def export_project(src_paths, export_path, target, ide, libraries_paths=None,
extra_verbose=extra_verbose, config=config, build_profile=build_profile,
app_config=app_config)
# The first path will give the name to the library
toolchain.RESPONSE_FILES = False
if name is None:
name = basename(normpath(abspath(src_paths[0])))

2
tools/export/makefile/__init__.py
View File

@ -225,7 +225,7 @@ class Arm(Makefile):
def generate(self):
if self.resources.linker_script:
new_script = self.toolchain.make_real_scatter(
new_script = self.toolchain.correct_scatter_shebang(
self.resources.linker_script)
if new_script is not self.resources.linker_script:
self.resources.linker_script = new_script

5
tools/export/uvision/__init__.py
View File

@ -167,8 +167,9 @@ class Uvision(Exporter):
"""Format toolchain flags for Uvision"""
flags = copy.deepcopy(self.flags)
# to be preprocessed with armcc
asm_flag_string = '--cpreproc --cpreproc_opts=-D__ASSERT_MSG,' + \
",".join(flags['asm_flags'])
asm_flag_string = (
'--cpreproc --cpreproc_opts=-D__ASSERT_MSG,' +
",".join(filter(lambda f: f.startswith("-D"), flags['asm_flags'])))
flags['asm_flags'] = asm_flag_string
# All non-asm flags are in one template field
c_flags = list(set(flags['c_flags'] + flags['cxx_flags'] +flags['common_flags']))

2
tools/export/uvision/uvision.tmpl
View File

@ -394,7 +394,7 @@
<MiscControls>{{asm_flags}}</MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
<IncludePath>{{include_paths}}</IncludePath>
</VariousControls>
</Aads>
<LDads>

2
tools/hooks.py
View File

@ -65,7 +65,7 @@ class Hook(object):
_HOOKS.clear()
self._cmdline_hooks = {}
self.toolchain = toolchain
target.init_hooks(self, toolchain.__class__.__name__)
target.init_hooks(self, toolchain)
# Hook various functions directly
@staticmethod

2
tools/memap.py
View File

@ -269,7 +269,7 @@ class MemapParser(object):
else:
RE_OBJECT_ARMCC = r'(.+\.l)\((.+\.o)\)'
RE_OBJECT_ARMCC = r'(.+\.(l|ar))\((.+\.o)\)'
test_re_obj_name = re.match(RE_OBJECT_ARMCC, line)
if test_re_obj_name:

2
tools/profiles/debug.json
View File

@ -19,7 +19,7 @@
"common": ["-c", "--target=arm-arm-none-eabi", "-mthumb", "-g", "-O0",
"-Wno-armcc-pragma-push-pop", "-Wno-armcc-pragma-anon-unions",
"-DMULADDC_CANNOT_USE_R7", "-fdata-sections",
"-fno-exceptions"],
"-fno-exceptions", "-MMD"],
"asm": [],
"c": ["-D__ASSERT_MSG", "-std=gnu99"],
"cxx": ["-fno-rtti", "-std=gnu++98"],

2
tools/profiles/develop.json
View File

@ -18,7 +18,7 @@
"common": ["-c", "--target=arm-arm-none-eabi", "-mthumb", "-Os",
"-Wno-armcc-pragma-push-pop", "-Wno-armcc-pragma-anon-unions",
"-DMULADDC_CANNOT_USE_R7", "-fdata-sections",
"-fno-exceptions"],
"-fno-exceptions", "-MMD"],
"asm": [],
"c": ["-D__ASSERT_MSG", "-std=gnu99"],
"cxx": ["-fno-rtti", "-std=gnu++98"],

2
tools/profiles/release.json
View File

@ -18,7 +18,7 @@
"common": ["-c", "--target=arm-arm-none-eabi", "-mthumb", "-Oz",
"-Wno-armcc-pragma-push-pop", "-Wno-armcc-pragma-anon-unions",
"-DMULADDC_CANNOT_USE_R7", "-fdata-sections",
"-fno-exceptions"],
"-fno-exceptions", "-MMD"],
"asm": [],
"c": ["-D__ASSERT_MSG", "-std=gnu99"],
"cxx": ["-fno-rtti", "-std=gnu++98"],

16
tools/targets/__init__.py
View File

@ -22,6 +22,7 @@ import shutil
import inspect
import sys
from copy import copy
from inspect import getmro
from collections import namedtuple, Mapping
from tools.targets.LPC import patch
from tools.paths import TOOLS_BOOTLOADERS
@ -310,10 +311,14 @@ class Target(namedtuple("Target", "name json_data resolution_order resolution_or
labels.append("UVISOR_UNSUPPORTED")
return labels
def init_hooks(self, hook, toolchain_name):
def init_hooks(self, hook, toolchain):
"""Initialize the post-build hooks for a toolchain. For now, this
function only allows "post binary" hooks (hooks that are executed
after the binary image is extracted from the executable file)
Positional Arguments:
hook - the hook object to add post-binary-hooks to
toolchain - the toolchain object for inspection
"""
# If there's no hook, simply return
@ -329,7 +334,7 @@ class Target(namedtuple("Target", "name json_data resolution_order resolution_or
("Invalid format for hook '%s' in target '%s'"
% (hook_data["function"], self.name)) +
" (must be 'class_name.function_name')")
class_name, function_name = temp[0], temp[1]
class_name, function_name = temp
# "class_name" must refer to a class in this file, so check if the
# class exists
mdata = self.get_module_data()
@ -349,10 +354,11 @@ class Target(namedtuple("Target", "name json_data resolution_order resolution_or
("required by '%s' " % hook_data["function"]) +
("in target '%s' " % self.name) +
("not found in class '%s'" % class_name))
# Check if the hook specification also has target restrictions
toolchain_restrictions = hook_data.get("toolchains", [])
# Check if the hook specification also has toolchain restrictions
toolchain_restrictions = set(hook_data.get("toolchains", []))
toolchain_labels = set(c.__name__ for c in getmro(toolchain.__class__))
if toolchain_restrictions and \
(toolchain_name not in toolchain_restrictions):
not toolchain_labels.intersection(toolchain_restrictions):
return
# Finally, hook the requested function
hook.hook_add_binary("post", getattr(cls, function_name))

13
tools/test/build_api/build_api_test.py
View File

@ -20,10 +20,13 @@ from collections import namedtuple
from mock import patch, MagicMock
from tools.build_api import prepare_toolchain, build_project, build_library,\
scan_resources
from tools.toolchains import TOOLCHAINS
"""
Tests for build_api.py
"""
make_mock_target = namedtuple(
"Target", "init_hooks name features core supported_toolchains")
class BuildApiTests(unittest.TestCase):
"""
@ -82,9 +85,8 @@ class BuildApiTests(unittest.TestCase):
:return:
"""
app_config = "app_config"
mock_target = namedtuple("Target",
"init_hooks name features core")(lambda _, __ : None,
"Junk", [], "Cortex-M3")
mock_target = make_mock_target(lambda _, __ : None,
"Junk", [], "Cortex-M3", TOOLCHAINS)
mock_config_init.return_value = namedtuple(
"Config", "target has_regions name")(mock_target, False, None)
@ -102,9 +104,8 @@ class BuildApiTests(unittest.TestCase):
:param mock_config_init: mock of Config __init__
:return:
"""
mock_target = namedtuple("Target",
"init_hooks name features core")(lambda _, __ : None,
"Junk", [], "Cortex-M3")
mock_target = make_mock_target(lambda _, __ : None,
"Junk", [], "Cortex-M3", TOOLCHAINS)
mock_config_init.return_value = namedtuple(
"Config", "target has_regions name")(mock_target, False, None)

5
tools/toolchains/__init__.py
View File

@ -26,7 +26,6 @@ from os.path import join, splitext, exists, relpath, dirname, basename, split, a
from itertools import chain
from inspect import getmro
from copy import deepcopy
from tools.config import Config
from abc import ABCMeta, abstractmethod
from distutils.spawn import find_executable
@ -1257,7 +1256,7 @@ class mbedToolchain:
else:
prev_data = None
# Get the current configuration data
crt_data = Config.config_to_header(self.config_data) if self.config_data else None
crt_data = self.config.config_to_header(self.config_data) if self.config_data else None
# "changed" indicates if a configuration change was detected
changed = False
if prev_data is not None: # a previous mbed_config.h exists
@ -1553,7 +1552,7 @@ class mbedToolchain:
# Return the list of macros geenrated by the build system
def get_config_macros(self):
return Config.config_to_macros(self.config_data) if self.config_data else []
return self.config.config_to_macros(self.config_data) if self.config_data else []
@property
def report(self):

21
tools/toolchains/arm.py
View File

@ -49,6 +49,9 @@ class ARM(mbedToolchain):
extra_verbose=extra_verbose,
build_profile=build_profile)
if "ARM" not in target.supported_toolchains:
raise NotSupportedException("ARM compiler support is required for ARM build")
if target.core == "Cortex-M0+":
cpu = "Cortex-M0"
elif target.core == "Cortex-M4F":
@ -276,8 +279,8 @@ class ARMC6(ARM_STD):
def __init__(self, target, *args, **kwargs):
mbedToolchain.__init__(self, target, *args, **kwargs)
if "ARM" not in target.supported_toolchains:
raise NotSupportedException("ARM compiler support is required for ARMC6 support")
if not set(("ARM", "ARMC6")).intersection(set(target.supported_toolchains)):
raise NotSupportedException("ARM/ARMC6 compiler support is required for ARMC6 build")
if target.core.lower().endswith("fd"):
self.flags['common'].append("-mcpu=%s" % target.core.lower()[:-2])
@ -285,6 +288,9 @@ class ARMC6(ARM_STD):
elif target.core.lower().endswith("f"):
self.flags['common'].append("-mcpu=%s" % target.core.lower()[:-1])
self.flags['ld'].append("--cpu=%s" % target.core.lower()[:-1])
elif target.core.lower().endswith("ns"):
self.flags['common'].append("-mcpu=%s" % target.core.lower()[:-3])
self.flags['ld'].append("--cpu=%s" % target.core.lower()[:-3])
else:
self.flags['common'].append("-mcpu=%s" % target.core.lower())
self.flags['ld'].append("--cpu=%s" % target.core.lower())
@ -298,12 +304,21 @@ class ARMC6(ARM_STD):
elif target.core == "Cortex-M7FD":
self.flags['common'].append("-mfpu=fpv5-d16")
self.flags['common'].append("-mfloat-abi=softfp")
elif target.core.startswith("Cortex-M23"):
self.flags['common'].append("-march=armv8-m.base")
elif target.core.startswith("Cortex-M33"):
self.flags['common'].append("-march=armv8-m.main")
if target.core == "Cortex-M23" or target.core == "Cortex-M33":
self.flags['common'].append("-mcmse")
asm_cpu = {
"Cortex-M0+": "Cortex-M0",
"Cortex-M4F": "Cortex-M4.fp",
"Cortex-M7F": "Cortex-M7.fp.sp",
"Cortex-M7FD": "Cortex-M7.fp.dp"}.get(target.core, target.core)
"Cortex-M7FD": "Cortex-M7.fp.dp",
"Cortex-M23-NS": "Cortex-M23",
"Cortex-M33-NS": "Cortex-M33" }.get(target.core, target.core)
self.flags['asm'].append("--cpu=%s" % asm_cpu)