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[M2351] Support configurable for partitioning flash/SRAM

pull/7302/head
ccli8 2018-06-08 17:49:19 +08:00
parent 778aa1e766
commit 6bf8e191af
11 changed files with 273 additions and 250 deletions
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101
targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/M2351.sct
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@ -1,25 +1,66 @@
#! armcc -E #! armcc -E
#include "partition_M2351_sub.h" /* Default flash/SRAM partition
*
* Default flash partition:
* Secure: 256KiB
* Non-secure: 256KiB
*
* Default SRAM partition:
* Secure: 32KiB
* Non-secure: 64KiB
*/
#if defined(__DOMAIN_NS) && __DOMAIN_NS
/* Check relevant macros have been defined */ #ifndef MBED_APP_START
#if (! defined(NU_TZ_SECURE_FLASH_SIZE)) #define MBED_APP_START 0x10040000
#error("NU_TZ_SECURE_FLASH_SIZE not defined")
#endif #endif
#if (! defined(NU_TZ_SECURE_SRAM_SIZE))
#error("NU_TZ_SECURE_SRAM_SIZE not defined") #ifndef MBED_APP_SIZE
#define MBED_APP_SIZE 0x40000
#endif #endif
#if (! defined(NU_TZ_NSC_REGION_SIZE))
#error("NU_TZ_NSC_REGION_SIZE not defined") #ifndef MBED_RAM_START
#define MBED_RAM_START 0x30008000
#endif
#ifndef MBED_RAM_SIZE
#define MBED_RAM_SIZE 0x10000
#endif
#else
#ifndef MBED_APP_START
#define MBED_APP_START 0x0
#endif
#ifndef MBED_APP_SIZE
#define MBED_APP_SIZE 0x40000
#endif
#ifndef MBED_RAM_START
#define MBED_RAM_START 0x20000000
#endif
#ifndef MBED_RAM_SIZE
#define MBED_RAM_SIZE 0x8000
#endif
#endif #endif
/* Requirements for NSC location /* Requirements for NSC location
* *
* 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. * 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
* 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range. * 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
* 3. Greentea NVSTORE uses last 2 sectors or 4KB x 2 for its test. Avoid this range. * 3. Greentea NVSTORE uses last 2 sectors or 4KiB x 2 for its test. Avoid this range.
* 4. NSC region size defaults to 4KiB if not defined.
*/ */
#define NU_TZ_NSC_REGION_BASE (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_REGION_SIZE) #ifndef NU_TZ_NSC_START
#define NU_TZ_NSC_START (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE)
#endif
#ifndef NU_TZ_NSC_SIZE
#define NU_TZ_NSC_SIZE 0x1000
#endif
/* Initial/ISR stack size */ /* Initial/ISR stack size */
#if (! defined(NU_INITIAL_STACK_SIZE)) #if (! defined(NU_INITIAL_STACK_SIZE))
@ -32,14 +73,6 @@
#if defined(__DOMAIN_NS) && __DOMAIN_NS #if defined(__DOMAIN_NS) && __DOMAIN_NS
#if (! defined(MBED_APP_START))
#define MBED_APP_START (0x10000000 + NU_TZ_SECURE_FLASH_SIZE)
#endif
#if (! defined(MBED_APP_SIZE))
#define MBED_APP_SIZE (0x80000 - NU_TZ_SECURE_FLASH_SIZE)
#endif
LR_IROM1 MBED_APP_START LR_IROM1 MBED_APP_START
{ {
/* load address = execution address */ /* load address = execution address */
@ -50,7 +83,7 @@ LR_IROM1 MBED_APP_START
.ANY (+RO) .ANY (+RO)
} }
ARM_LIB_STACK 0x30000000 + NU_TZ_SECURE_SRAM_SIZE EMPTY NU_INITIAL_STACK_SIZE ARM_LIB_STACK MBED_RAM_START EMPTY NU_INITIAL_STACK_SIZE
{ {
} }
@ -68,24 +101,16 @@ LR_IROM1 MBED_APP_START
.ANY (+RW +ZI) .ANY (+RW +ZI)
} }
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x30018000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
{ {
} }
} }
ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE)) ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x30018000) ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= MBED_RAM_START + MBED_RAM_SIZE)
#else #else
#if (! defined(MBED_APP_START))
#define MBED_APP_START 0
#endif
#if (! defined(MBED_APP_SIZE))
#define MBED_APP_SIZE NU_TZ_SECURE_FLASH_SIZE
#endif
LR_IROM1 MBED_APP_START LR_IROM1 MBED_APP_START
{ {
/* load address = execution address */ /* load address = execution address */
@ -114,23 +139,27 @@ LR_IROM1 MBED_APP_START
.ANY (+RW +ZI) .ANY (+RW +ZI)
} }
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + NU_TZ_SECURE_SRAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
{ {
} }
} }
LR_IROM2 NU_TZ_NSC_REGION_BASE LR_IROM_NSC NU_TZ_NSC_START NU_TZ_NSC_SIZE
{ {
NSC_ROM +0 NU_TZ_NSC_REGION_SIZE ER_IROM_NSC +0
{ {
*(Veneer$$CMSE) *(Veneer$$CMSE)
} }
ER_IROM_NSC_PAD +0 FILL 0xFFFFFFFF (NU_TZ_NSC_START + NU_TZ_NSC_SIZE - ImageLimit(ER_IROM_NSC))
{
}
} }
ScatterAssert(LoadLimit(LR_IROM1) <= NU_TZ_NSC_REGION_BASE) ScatterAssert(LoadLimit(LR_IROM1) <= NU_TZ_NSC_START)
ScatterAssert(LoadLimit(LR_IROM2) <= (NU_TZ_NSC_REGION_BASE + NU_TZ_NSC_REGION_SIZE)) ScatterAssert(LoadLimit(LR_IROM_NSC) <= (NU_TZ_NSC_START + NU_TZ_NSC_SIZE))
/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000 */ /* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000 */
ScatterAssert(LoadBase(LR_IROM2) >= 0x4000) ScatterAssert(LoadBase(LR_IROM_NSC) >= 0x4000)
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (0x20000000 + NU_TZ_SECURE_SRAM_SIZE)) ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_START + MBED_RAM_SIZE))
#endif #endif

23
targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/partition_M2351_sub.h
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@ -1,23 +0,0 @@
/**************************************************************************//**
* @file partition_M2351_sub.c
* @version V3.00
* @brief SAU configuration for secure/nonsecure region settings.
*
* @note
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#ifndef PARTITION_M2351_SUB
#define PARTITION_M2351_SUB
/* Secure flash size: 256 KB */
#define NU_TZ_SECURE_FLASH_SIZE 0x40000
/* Secure SRAM size: 32 KB */
#define NU_TZ_SECURE_SRAM_SIZE 0x8000
/* NSC region size: 4 KB */
#define NU_TZ_NSC_REGION_SIZE 0x1000
#endif /* PARTITION_M2351_SUB */

101
targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/M2351.sct
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@ -1,25 +1,66 @@
#! armcc -E #! armcc -E
#include "partition_M2351_sub.h" /* Default flash/SRAM partition
*
* Default flash partition:
* Secure: 256KiB
* Non-secure: 256KiB
*
* Default SRAM partition:
* Secure: 32KiB
* Non-secure: 64KiB
*/
#if defined(__DOMAIN_NS) && __DOMAIN_NS
/* Check relevant macros have been defined */ #ifndef MBED_APP_START
#if (! defined(NU_TZ_SECURE_FLASH_SIZE)) #define MBED_APP_START 0x10040000
#error("NU_TZ_SECURE_FLASH_SIZE not defined")
#endif #endif
#if (! defined(NU_TZ_SECURE_SRAM_SIZE))
#error("NU_TZ_SECURE_SRAM_SIZE not defined") #ifndef MBED_APP_SIZE
#define MBED_APP_SIZE 0x40000
#endif #endif
#if (! defined(NU_TZ_NSC_REGION_SIZE))
#error("NU_TZ_NSC_REGION_SIZE not defined") #ifndef MBED_RAM_START
#define MBED_RAM_START 0x30008000
#endif
#ifndef MBED_RAM_SIZE
#define MBED_RAM_SIZE 0x10000
#endif
#else
#ifndef MBED_APP_START
#define MBED_APP_START 0x0
#endif
#ifndef MBED_APP_SIZE
#define MBED_APP_SIZE 0x40000
#endif
#ifndef MBED_RAM_START
#define MBED_RAM_START 0x20000000
#endif
#ifndef MBED_RAM_SIZE
#define MBED_RAM_SIZE 0x8000
#endif
#endif #endif
/* Requirements for NSC location /* Requirements for NSC location
* *
* 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. * 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
* 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range. * 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
* 3. Greentea NVSTORE uses last 2 sectors or 4KB x 2 for its test. Avoid this range. * 3. Greentea NVSTORE uses last 2 sectors or 4KiB x 2 for its test. Avoid this range.
* 4. NSC region size defaults to 4KiB if not defined.
*/ */
#define NU_TZ_NSC_REGION_BASE (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_REGION_SIZE) #ifndef NU_TZ_NSC_START
#define NU_TZ_NSC_START (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE)
#endif
#ifndef NU_TZ_NSC_SIZE
#define NU_TZ_NSC_SIZE 0x1000
#endif
/* Initial/ISR stack size */ /* Initial/ISR stack size */
#if (! defined(NU_INITIAL_STACK_SIZE)) #if (! defined(NU_INITIAL_STACK_SIZE))
@ -32,14 +73,6 @@
#if defined(__DOMAIN_NS) && __DOMAIN_NS #if defined(__DOMAIN_NS) && __DOMAIN_NS
#if (! defined(MBED_APP_START))
#define MBED_APP_START (0x10000000 + NU_TZ_SECURE_FLASH_SIZE)
#endif
#if (! defined(MBED_APP_SIZE))
#define MBED_APP_SIZE (0x80000 - NU_TZ_SECURE_FLASH_SIZE)
#endif
LR_IROM1 MBED_APP_START LR_IROM1 MBED_APP_START
{ {
/* load address = execution address */ /* load address = execution address */
@ -50,7 +83,7 @@ LR_IROM1 MBED_APP_START
.ANY (+RO) .ANY (+RO)
} }
ARM_LIB_STACK 0x30000000 + NU_TZ_SECURE_SRAM_SIZE EMPTY NU_INITIAL_STACK_SIZE ARM_LIB_STACK MBED_RAM_START EMPTY NU_INITIAL_STACK_SIZE
{ {
} }
@ -68,24 +101,16 @@ LR_IROM1 MBED_APP_START
.ANY (+RW +ZI) .ANY (+RW +ZI)
} }
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x30018000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
{ {
} }
} }
ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE)) ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x30018000) ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= MBED_RAM_START + MBED_RAM_SIZE)
#else #else
#if (! defined(MBED_APP_START))
#define MBED_APP_START 0
#endif
#if (! defined(MBED_APP_SIZE))
#define MBED_APP_SIZE NU_TZ_SECURE_FLASH_SIZE
#endif
LR_IROM1 MBED_APP_START LR_IROM1 MBED_APP_START
{ {
/* load address = execution address */ /* load address = execution address */
@ -114,23 +139,27 @@ LR_IROM1 MBED_APP_START
.ANY (+RW +ZI) .ANY (+RW +ZI)
} }
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + NU_TZ_SECURE_SRAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
{ {
} }
} }
LR_IROM2 NU_TZ_NSC_REGION_BASE LR_IROM_NSC NU_TZ_NSC_START NU_TZ_NSC_SIZE
{ {
NSC_ROM +0 NU_TZ_NSC_REGION_SIZE ER_IROM_NSC +0
{ {
*(Veneer$$CMSE) *(Veneer$$CMSE)
} }
ER_IROM_NSC_PAD +0 FILL 0xFFFFFFFF (NU_TZ_NSC_START + NU_TZ_NSC_SIZE - ImageLimit(ER_IROM_NSC))
{
}
} }
ScatterAssert(LoadLimit(LR_IROM1) <= NU_TZ_NSC_REGION_BASE) ScatterAssert(LoadLimit(LR_IROM1) <= NU_TZ_NSC_START)
ScatterAssert(LoadLimit(LR_IROM2) <= (NU_TZ_NSC_REGION_BASE + NU_TZ_NSC_REGION_SIZE)) ScatterAssert(LoadLimit(LR_IROM_NSC) <= (NU_TZ_NSC_START + NU_TZ_NSC_SIZE))
/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000 */ /* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000 */
ScatterAssert(LoadBase(LR_IROM2) >= 0x4000) ScatterAssert(LoadBase(LR_IROM_NSC) >= 0x4000)
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (0x20000000 + NU_TZ_SECURE_SRAM_SIZE)) ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_START + MBED_RAM_SIZE))
#endif #endif

23
targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/partition_M2351_sub.h
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@ -1,23 +0,0 @@
/**************************************************************************//**
* @file partition_M2351_sub.c
* @version V3.00
* @brief SAU configuration for secure/nonsecure region settings.
*
* @note
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#ifndef PARTITION_M2351_SUB
#define PARTITION_M2351_SUB
/* Secure flash size: 256 KB */
#define NU_TZ_SECURE_FLASH_SIZE 0x40000
/* Secure SRAM size: 32 KB */
#define NU_TZ_SECURE_SRAM_SIZE 0x8000
/* NSC region size: 4 KB */
#define NU_TZ_NSC_REGION_SIZE 0x1000
#endif /* PARTITION_M2351_SUB */

99
targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/M2351.ld
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@ -2,66 +2,92 @@
* Nuvoton M2351 GCC linker script file * Nuvoton M2351 GCC linker script file
*/ */
/* Default flash/SRAM partition
*
* Default flash partition:
* Secure: 256KiB
* Non-secure: 256KiB
*
* Default SRAM partition:
* Secure: 32KiB
* Non-secure: 64KiB
*/
#if defined(__DOMAIN_NS) && __DOMAIN_NS
#ifndef MBED_APP_START
#define MBED_APP_START 0x10040000
#endif
#ifndef MBED_APP_SIZE
#define MBED_APP_SIZE 0x40000
#endif
#ifndef MBED_RAM_START
#define MBED_RAM_START 0x30008000
#endif
#ifndef MBED_RAM_SIZE
#define MBED_RAM_SIZE 0x10000
#endif
#else
#ifndef MBED_APP_START
#define MBED_APP_START 0x0
#endif
#ifndef MBED_APP_SIZE
#define MBED_APP_SIZE 0x40000
#endif
#ifndef MBED_RAM_START
#define MBED_RAM_START 0x20000000
#endif
#ifndef MBED_RAM_SIZE
#define MBED_RAM_SIZE 0x8000
#endif
#endif
#if defined(__DOMAIN_NS) && __DOMAIN_NS #if defined(__DOMAIN_NS) && __DOMAIN_NS
StackSize = 0x800; StackSize = 0x800;
#else #else
StackSize = 0x800; StackSize = 0x800;
#endif #endif
#include "partition_M2351_sub.h"
/* Check relevant macros have been defined */
#if (! defined(NU_TZ_SECURE_FLASH_SIZE))
#error("NU_TZ_SECURE_FLASH_SIZE not defined")
#endif
#if (! defined(NU_TZ_SECURE_SRAM_SIZE))
#error("NU_TZ_SECURE_SRAM_SIZE not defined")
#endif
#if (! defined(NU_TZ_NSC_REGION_SIZE))
#error("NU_TZ_NSC_REGION_SIZE not defined")
#endif
/* Requirements for NSC location /* Requirements for NSC location
* *
* 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. * 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
* 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range. * 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
* 3. Greentea NVSTORE uses last 2 sectors or 4KB x 2 for its test. Avoid this range. * 3. Greentea NVSTORE uses last 2 sectors or 4KiB x 2 for its test. Avoid this range.
* 4. NSC region size defaults to 4KiB if not defined.
*/ */
#define NU_TZ_NSC_REGION_BASE (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_REGION_SIZE) #ifndef NU_TZ_NSC_START
#define NU_TZ_NSC_START (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE)
#endif
#ifndef NU_TZ_NSC_SIZE
#define NU_TZ_NSC_SIZE 0x1000
#endif
#if defined(__DOMAIN_NS) && __DOMAIN_NS #if defined(__DOMAIN_NS) && __DOMAIN_NS
#if (! defined(MBED_APP_START))
#define MBED_APP_START (0x10000000 + NU_TZ_SECURE_FLASH_SIZE)
#endif
#if (! defined(MBED_APP_SIZE))
#define MBED_APP_SIZE (0x80000 - NU_TZ_SECURE_FLASH_SIZE)
#endif
MEMORY MEMORY
{ {
VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400 VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400 FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400
RAM_INTERN (rwx) : ORIGIN = 0x30000000 + NU_TZ_SECURE_SRAM_SIZE, LENGTH = 0x00018000 - NU_TZ_SECURE_SRAM_SIZE RAM_INTERN (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
} }
#else #else
#if (! defined(MBED_APP_START))
#define MBED_APP_START 0
#endif
#if (! defined(MBED_APP_SIZE))
#define MBED_APP_SIZE NU_TZ_SECURE_FLASH_SIZE
#endif
MEMORY MEMORY
{ {
VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400 VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = NU_TZ_NSC_REGION_BASE - MBED_APP_START - 0x400 FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = NU_TZ_NSC_START - MBED_APP_START - 0x400
NSC_FLASH (rx) : ORIGIN = NU_TZ_NSC_REGION_BASE, LENGTH = NU_TZ_NSC_REGION_SIZE NSC_FLASH (rx) : ORIGIN = NU_TZ_NSC_START, LENGTH = NU_TZ_NSC_SIZE
RAM_INTERN (rwx) : ORIGIN = 0x20000000, LENGTH = NU_TZ_SECURE_SRAM_SIZE RAM_INTERN (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
} }
#endif #endif
@ -175,6 +201,9 @@ SECTIONS
__sgstubs_end = .; __sgstubs_end = .;
} > NSC_FLASH } > NSC_FLASH
__nu_tz_nsc_start = NU_TZ_NSC_START;
__nu_tz_nsc_size = NU_TZ_NSC_SIZE;
/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. */ /* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. */
ASSERT(__sgstubs_start >= 0x4000, "By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.") ASSERT(__sgstubs_start >= 0x4000, "By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.")
#endif #endif

23
targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/partition_M2351_sub.h
View File

@ -1,23 +0,0 @@
/**************************************************************************//**
* @file partition_M2351_sub.c
* @version V3.00
* @brief SAU configuration for secure/nonsecure region settings.
*
* @note
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#ifndef PARTITION_M2351_SUB
#define PARTITION_M2351_SUB
/* Secure flash size: 256 KB */
#define NU_TZ_SECURE_FLASH_SIZE 0x40000
/* Secure SRAM size: 32 KB */
#define NU_TZ_SECURE_SRAM_SIZE 0x8000
/* NSC region size: 4 KB */
#define NU_TZ_NSC_REGION_SIZE 0x1000
#endif /* PARTITION_M2351_SUB */

39
targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_IAR/M2351.icf
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@ -1,5 +1,3 @@
include partition_M2351_sub
/*###ICF### Section handled by ICF editor, don't touch! ****/ /*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/ /*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
@ -7,11 +5,11 @@ include partition_M2351_sub
if (isdefinedsymbol(__DOMAIN_NS)) { if (isdefinedsymbol(__DOMAIN_NS)) {
if (! isdefinedsymbol(MBED_APP_START)) { if (! isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = 0x10000000 + NU_TZ_SECURE_FLASH_SIZE; define symbol MBED_APP_START = 0x10040000;
} }
if (! isdefinedsymbol(MBED_APP_SIZE)) { if (! isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = 0x80000 - NU_TZ_SECURE_FLASH_SIZE; define symbol MBED_APP_SIZE = 0x40000;
} }
@ -20,8 +18,8 @@ if (isdefinedsymbol(__DOMAIN_NS)) {
/*-Memory Regions-*/ /*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol __ICFEDIT_region_IRAM_start__ = 0x30000000 + NU_TZ_SECURE_SRAM_SIZE; define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM_end__ = 0x30018000 - 1; define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_START + MBED_RAM_SIZE - 1;
/*-Sizes-*/ /*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800; define symbol __ICFEDIT_size_cstack__ = 0x800;
@ -30,35 +28,38 @@ if (isdefinedsymbol(__DOMAIN_NS)) {
} else { } else {
if (! isdefinedsymbol(MBED_APP_START)) { if (! isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = 0; define symbol MBED_APP_START = 0x0;
} }
if (! isdefinedsymbol(MBED_APP_SIZE)) { if (! isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = NU_TZ_SECURE_FLASH_SIZE; define symbol MBED_APP_SIZE = 0x40000;
} }
/* Requirements for NSC location /* Requirements for NSC location
* *
* 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. * 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
* 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range. * 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
* 3. Greentea NVSTORE uses last 2 sectors or 4KB x 2 for its test. Avoid this range. * 3. Greentea NVSTORE uses last 2 sectors or 4KiB x 2 for its test. Avoid this range.
* 4. NSC region size defaults to 4KiB if not defined.
*/ */
define exported symbol NU_TZ_NSC_REGION_BASE = MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_REGION_SIZE; if (! isdefinedsymbol(NU_TZ_NSC_START)) {
define symbol NU_TZ_NSC_START = MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE;
}
define exported symbol __NU_TZ_NSC_start__ = NU_TZ_NSC_START;
if (! isdefinedsymbol(NU_TZ_NSC_SIZE)) {
define symbol NU_TZ_NSC_SIZE = 0x1000;
}
define exported symbol __NU_TZ_NSC_size__ = NU_TZ_NSC_SIZE;
/*-Specials-*/ /*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
/*-Memory Regions-*/ /*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol __ICFEDIT_region_NSCROM_start__ = NU_TZ_NSC_REGION_BASE; define symbol __ICFEDIT_region_NSCROM_start__ = NU_TZ_NSC_START;
define symbol __ICFEDIT_region_NSCROM_end__ = NU_TZ_NSC_REGION_BASE + NU_TZ_NSC_REGION_SIZE - 1; define symbol __ICFEDIT_region_NSCROM_end__ = NU_TZ_NSC_START + NU_TZ_NSC_SIZE - 1;
define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000; define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM_end__ = 0x20000000 + NU_TZ_SECURE_SRAM_SIZE - 1; define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_START + MBED_RAM_SIZE - 1;
export symbol __NU_TZ_SECURE_FLASH_SIZE__ = NU_TZ_SECURE_FLASH_SIZE;
export symbol __NU_TZ_SECURE_SRAM_SIZE__ = NU_TZ_SECURE_SRAM_SIZE;
export symbol __NU_TZ_NSC_REGION_BASE__ = NU_TZ_NSC_REGION_BASE;
export symbol __NU_TZ_NSC_REGION_SIZE__ = NU_TZ_NSC_REGION_SIZE;
/*-Sizes-*/ /*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800; define symbol __ICFEDIT_size_cstack__ = 0x800;

11
targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_IAR/partition_M2351_sub
View File

@ -1,11 +0,0 @@
/* Secure flash size: 256 KB */
define exported symbol NU_TZ_SECURE_FLASH_SIZE = 0x40000
/* Secure SRAM size: 32 KB */
define exported symbol NU_TZ_SECURE_SRAM_SIZE = 0x8000
/* NSC region size: 4 KB */
define exported symbol NU_TZ_NSC_REGION_SIZE = 0x1000

48
targets/TARGET_NUVOTON/TARGET_M2351/device/partition_M2351.h
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@ -11,33 +11,41 @@
#ifndef PARTITION_M2351 #ifndef PARTITION_M2351
#define PARTITION_M2351 #define PARTITION_M2351
#ifndef MBED_ROM_SIZE
#define NU_TZ_SECURE_FLASH_SIZE 0x40000
#else
#define NU_TZ_SECURE_FLASH_SIZE MBED_ROM_SIZE
#endif
#ifndef APPLICATION_RAM_SIZE
#define NU_TZ_SECURE_SRAM_SIZE 0x8000
#else
#define NU_TZ_SECURE_SRAM_SIZE APPLICATION_RAM_SIZE
#endif
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) #if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#include "partition_M2351_sub.h" extern int Load$$LR$$LR_IROM_NSC$$Base;
extern int Load$$LR$$LR_IROM_NSC$$Length;
extern int Image$$NSC_ROM$$Base; #define NU_TZ_NSC_REGION_START ((uint32_t) &Load$$LR$$LR_IROM_NSC$$Base)
#define NU_TZ_NSC_REGION_SIZE ((uint32_t) &Load$$LR$$LR_IROM_NSC$$Length)
#define NU_TZ_NSC_REGION_BASE ((uint32_t) &Image$$NSC_ROM$$Base)
#elif defined(__ICCARM__) #elif defined(__ICCARM__)
extern int __NU_TZ_SECURE_FLASH_SIZE__; extern int __NU_TZ_NSC_start__;
extern int __NU_TZ_SECURE_SRAM_SIZE__; extern int __NU_TZ_NSC_size__;
extern int __NU_TZ_NSC_REGION_BASE__;
extern int __NU_TZ_NSC_REGION_SIZE__;
#define NU_TZ_SECURE_FLASH_SIZE ((uint32_t) &__NU_TZ_SECURE_FLASH_SIZE__) #define NU_TZ_NSC_REGION_START ((uint32_t) &__NU_TZ_NSC_start__)
#define NU_TZ_SECURE_SRAM_SIZE ((uint32_t) &__NU_TZ_SECURE_SRAM_SIZE__) #define NU_TZ_NSC_REGION_SIZE ((uint32_t) &__NU_TZ_NSC_size__)
#define NU_TZ_NSC_REGION_BASE ((uint32_t) &__NU_TZ_NSC_REGION_BASE__)
#define NU_TZ_NSC_REGION_SIZE ((uint32_t) &__NU_TZ_NSC_REGION_SIZE__)
#elif defined(__GNUC__) #elif defined(__GNUC__)
#include "partition_M2351_sub.h" extern int __nu_tz_nsc_start;
extern int __nu_tz_nsc_size;
extern int __sgstubs_start; #define NU_TZ_NSC_REGION_START ((uint32_t) &__nu_tz_nsc_start)
#define NU_TZ_NSC_REGION_SIZE ((uint32_t) &__nu_tz_nsc_size)
#define NU_TZ_NSC_REGION_BASE ((uint32_t) &__sgstubs_start)
#endif #endif
@ -48,8 +56,8 @@ extern int __sgstubs_start;
#if (! defined(NU_TZ_SECURE_SRAM_SIZE)) #if (! defined(NU_TZ_SECURE_SRAM_SIZE))
#error("NU_TZ_SECURE_SRAM_SIZE not defined") #error("NU_TZ_SECURE_SRAM_SIZE not defined")
#endif #endif
#if (! defined(NU_TZ_NSC_REGION_BASE)) #if (! defined(NU_TZ_NSC_REGION_START))
#error("NU_TZ_NSC_REGION_BASE not defined") #error("NU_TZ_NSC_REGION_START not defined")
#endif #endif
#if (! defined(NU_TZ_NSC_REGION_SIZE)) #if (! defined(NU_TZ_NSC_REGION_SIZE))
#error("NU_TZ_NSC_REGION_SIZE not defined") #error("NU_TZ_NSC_REGION_SIZE not defined")
@ -431,11 +439,11 @@ __STATIC_INLINE void SCU_Setup(void)
/* /*
// <o>Start Address <0-0xFFFFFFE0> // <o>Start Address <0-0xFFFFFFE0>
*/ */
#define SAU_INIT_START3 NU_TZ_NSC_REGION_BASE #define SAU_INIT_START3 NU_TZ_NSC_REGION_START
/* /*
// <o>End Address <0x1F-0xFFFFFFFF> // <o>End Address <0x1F-0xFFFFFFFF>
*/ */
#define SAU_INIT_END3 (NU_TZ_NSC_REGION_BASE + NU_TZ_NSC_REGION_SIZE - 1) #define SAU_INIT_END3 (NU_TZ_NSC_REGION_START + NU_TZ_NSC_REGION_SIZE - 1)
/* /*
// <o>Region is // <o>Region is
// <0=>Non-Secure // <0=>Non-Secure

31
targets/TARGET_NUVOTON/TARGET_M2351/flash_api.c
View File

@ -25,6 +25,17 @@
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#ifndef MBED_ROM_START
#define MBED_ROM_START 0x0
#endif
#ifndef MBED_ROM_SIZE
#define MBED_ROM_SIZE 0x40000
#endif
#define NU_SECURE_FLASH_START MBED_ROM_START
#define NU_SECURE_FLASH_SIZE MBED_ROM_SIZE
// This is a flash algo binary blob. It is PIC (position independent code) that should be stored in RAM // This is a flash algo binary blob. It is PIC (position independent code) that should be stored in RAM
// NOTE: On ARMv7-M/ARMv8-M, instruction fetches are always little-endian. // NOTE: On ARMv7-M/ARMv8-M, instruction fetches are always little-endian.
static uint32_t FLASH_ALGO[] = { static uint32_t FLASH_ALGO[] = {
@ -85,7 +96,7 @@ static const flash_algo_t flash_algo_config = {
/* Secure flash */ /* Secure flash */
static const sector_info_t sectors_info[] = { static const sector_info_t sectors_info[] = {
{0x0, 0x800}, // (start, sector size) {NU_SECURE_FLASH_START, 0x800}, // (start, sector size)
}; };
/* Secure flash */ /* Secure flash */
@ -93,19 +104,15 @@ static const flash_target_config_t flash_target_config = {
.page_size = 4, // 4 bytes .page_size = 4, // 4 bytes
// Here page_size is program unit, which is different // Here page_size is program unit, which is different
// than FMC definition. // than FMC definition.
.flash_start = 0x0, .flash_start = NU_SECURE_FLASH_START,
#if defined(FMC_SECURE_ROM_SIZE) .flash_size = NU_SECURE_FLASH_SIZE,
.flash_size = FMC_SECURE_ROM_SIZE,
#else
.flash_size = 0x80000, // 512 KB
#endif
.sectors = sectors_info, .sectors = sectors_info,
.sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t) .sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t)
}; };
/* Non-secure flash */ /* Non-secure flash */
static const sector_info_t sectors_info_ns[] = { static const sector_info_t sectors_info_ns[] = {
{(NS_OFFSET + FMC_SECURE_ROM_SIZE), 0x800}, // (start, sector size) {(NS_OFFSET + NU_SECURE_FLASH_SIZE), 0x800}, // (start, sector size)
}; };
/* Non-secure flash */ /* Non-secure flash */
@ -113,12 +120,8 @@ static const flash_target_config_t flash_target_config_ns = {
.page_size = 4, // 4 bytes .page_size = 4, // 4 bytes
// Here page_size is program unit, which is different // Here page_size is program unit, which is different
// than FMC definition. // than FMC definition.
.flash_start = NS_OFFSET + FMC_SECURE_ROM_SIZE, .flash_start = NS_OFFSET + NU_SECURE_FLASH_SIZE,
#if defined(FMC_SECURE_ROM_SIZE) .flash_size = 0x80000 - NU_SECURE_FLASH_SIZE,
.flash_size = 0x80000 - FMC_SECURE_ROM_SIZE,
#else
.flash_size = 0,
#endif
.sectors = sectors_info_ns, .sectors = sectors_info_ns,
.sector_info_count = sizeof(sectors_info_ns) / sizeof(sector_info_t) .sector_info_count = sizeof(sectors_info_ns) / sizeof(sector_info_t)
}; };

4
targets/targets.json
View File

@ -4245,6 +4245,10 @@
"value": "GPIO_DBCTL_DBCLKSEL_16" "value": "GPIO_DBCTL_DBCLKSEL_16"
} }
}, },
"mbed_rom_start": "0x10040000",
"mbed_rom_size": "0x40000",
"mbed_ram_start": "0x30008000",
"mbed_ram_size": "0x10000",
"inherits": ["Target"], "inherits": ["Target"],
"device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "FLASH"], "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "FLASH"],
"detect_code": ["1305"], "detect_code": ["1305"],