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Merge pull request #3434 from OpenNuvoton/nuvoton 

[NUC472/M453] Fix stuck in lp_ticker_init and other updates
pull/3316/merge
Sam Grove 2016-12-15 10:38:35 -06:00 committed by GitHub
parent 19acef97ee 0053b70d1e
commit 6b64dbc5fe
22 changed files with 140 additions and 477 deletions
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15
features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_eth.c
View File

@ -33,6 +33,7 @@
#define ETH_DISABLE_TX() do{EMAC->CTL &= ~EMAC_CTL_TXON;}while(0)
#define ETH_DISABLE_RX() do{EMAC->CTL &= ~EMAC_CTL_RXON;}while(0)
/*
#ifdef __ICCARM__
#pragma data_alignment=4
@ -99,7 +100,7 @@ static int reset_phy(void)
}
if(delay == 0) {
printf("Reset phy failed\n");
LWIP_DEBUGF(LWIP_DBG_LEVEL_SEVERE|LWIP_DBG_ON,("Reset phy failed\n"));
return(-1);
}
@ -120,23 +121,23 @@ static int reset_phy(void)
}
if(delay == 0) {
printf("AN failed. Set to 100 FULL\n");
LWIP_DEBUGF(LWIP_DBG_LEVEL_SEVERE|LWIP_DBG_ON , ("AN failed. Set to 100 FULL\n"));
EMAC->CTL |= (EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
return(-1);
} else {
reg = mdio_read(CONFIG_PHY_ADDR, MII_LPA);
if(reg & ADVERTISE_100FULL) {
printf("100 full\n");
LWIP_DEBUGF(LWIP_DBG_LEVEL_ALL|LWIP_DBG_ON, ("100 full\n"));
EMAC->CTL |= (EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
} else if(reg & ADVERTISE_100HALF) {
printf("100 half\n");
LWIP_DEBUGF(LWIP_DBG_LEVEL_ALL|LWIP_DBG_ON, ("100 half\n"));
EMAC->CTL = (EMAC->CTL & ~EMAC_CTL_FUDUP_Msk) | EMAC_CTL_OPMODE_Msk;
} else if(reg & ADVERTISE_10FULL) {
printf("10 full\n");
LWIP_DEBUGF(LWIP_DBG_LEVEL_ALL|LWIP_DBG_ON, ("10 full\n"));
EMAC->CTL = (EMAC->CTL & ~EMAC_CTL_OPMODE_Msk) | EMAC_CTL_FUDUP_Msk;
} else {
printf("10 half\n");
LWIP_DEBUGF(LWIP_DBG_LEVEL_ALL|LWIP_DBG_ON, ("10 half\n"));
EMAC->CTL &= ~(EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
}
}
@ -267,7 +268,7 @@ void EMAC_RX_IRQHandler(void)
EMAC->INTSTS = m_status;
if (m_status & EMAC_INTSTS_RXBEIF_Msk) {
// Shouldn't goes here, unless descriptor corrupted
printf("RX descriptor corrupted \r\n");
LWIP_DEBUGF(LWIP_DBG_LEVEL_SERIOUS|LWIP_DBG_ON, ("RX descriptor corrupted \r\n"));
//return;
}
ack_emac_rx_isr();

11
features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_netif.c
View File

@ -42,7 +42,7 @@
* search-and-replace for the word "ethernetif" to replace it with
* something that better describes your network interface.
*/
#include "lwip/opt.h"
#include "lwip/def.h"
@ -494,16 +494,15 @@ static void __phy_task(void *data) {
// Compare with previous state
if( !(ETH_link_ok()) && (netif->flags & NETIF_FLAG_LINK_UP) ) {
//tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_down, (void*) netif, 1);
/* tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_down, (void*) netif, 1); */
netif_set_link_down(netif);
printf("Link Down\r\n");
LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING|LWIP_DBG_ON, ("Link Down\r\n"));
}else if ( ETH_link_ok() && !(netif->flags & NETIF_FLAG_LINK_UP) ) {
//tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_up, (void*) netif, 1);
/* tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_up, (void*) netif, 1); */
netif_set_link_up(netif);
printf("Link Up\r\n");
LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING|LWIP_DBG_ON, ("Link Up\r\n"));
}
// printf("-");
osDelay(200);
}
}

3
targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_can.c
View File

@ -196,8 +196,9 @@ void CAN_WaitMsg(CAN_T *tCAN)
}
if(tCAN->STATUS & CAN_STATUS_RXOK_Msk)
{
DEBUG_PRINTF("Rx OK\n");
}
if(tCAN->STATUS & CAN_STATUS_LEC_Msk)
{
DEBUG_PRINTF("Error\n");

12
targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_pwm.c
View File

@ -55,7 +55,11 @@ uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u
{
//clock source is from PCLK
SystemCoreClockUpdate();
u32PWMClockSrc = SystemCoreClock;
if(pwm == PWM0)
u32PWMClockSrc = CLK_GetPCLK0Freq();
else//(pwm == PWM1)
u32PWMClockSrc = CLK_GetPCLK1Freq();
}
u32PWMClockSrc /= 1000;
@ -142,7 +146,11 @@ uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
{
//clock source is from PCLK
SystemCoreClockUpdate();
u32PWMClockSrc = SystemCoreClock;
if(pwm == PWM0)
u32PWMClockSrc = CLK_GetPCLK0Freq();
else//(pwm == PWM1)
u32PWMClockSrc = CLK_GetPCLK1Freq();
}
for(u16Prescale = 1; u16Prescale < 0xFFF; u16Prescale++)//prescale could be 0~0xFFF

7
targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c
View File

@ -95,11 +95,14 @@ void lp_ticker_init(void)
TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
// Schedule wakeup to match semantics of lp_ticker_get_compare_match()
lp_ticker_set_interrupt(wakeup_tick);
// NOTE: TIMER_Start() first and then lp_ticker_set_interrupt(); otherwise, we may get stuck in lp_ticker_read() because
// timer is not running.
// Start timer
TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
// Schedule wakeup to match semantics of lp_ticker_get_compare_match()
lp_ticker_set_interrupt(wakeup_tick);
}
timestamp_t lp_ticker_read()

14
targets/TARGET_NUVOTON/TARGET_M451/serial_api.c
View File

@ -300,8 +300,8 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
MBED_ASSERT(uart_rts == obj->serial.uart);
// Enable the pin for RTS function
pinmap_pinout(rxflow, PinMap_UART_RTS);
// nRTS pin output is high level active
uart_base->MODEM = (uart_base->MODEM & ~UART_MODEM_RTSACTLV_Msk);
// nRTS pin output is low level active
uart_base->MODEM |= UART_MODEM_RTSACTLV_Msk;
uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES;
// Enable RTS
uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk;
@ -313,8 +313,8 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
MBED_ASSERT(uart_cts == obj->serial.uart);
// Enable the pin for CTS function
pinmap_pinout(txflow, PinMap_UART_CTS);
// nCTS pin input is high level active
uart_base->MODEMSTS = (uart_base->MODEMSTS & ~UART_MODEMSTS_CTSACTLV_Msk);
// nCTS pin input is low level active
uart_base->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
// Enable CTS
uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk;
}
@ -479,9 +479,6 @@ static void uart_irq(serial_t *obj)
#if DEVICE_SERIAL_ASYNCH
int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
{
// NOTE: tx_width is deprecated. Assume its value is databits ceiled to the nearest number among 8, 16, and 32.
tx_width = (obj->serial.databits <= 8) ? 8 : (obj->serial.databits <= 16) ? 16 : 32;
MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32);
obj->serial.dma_usage_tx = hint;
@ -536,9 +533,6 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
{
// NOTE: rx_width is deprecated. Assume its value is databits ceiled to the nearest number among 8, 16, and 32.
rx_width = (obj->serial.databits <= 8) ? 8 : (obj->serial.databits <= 16) ? 16 : 32;
MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32);
obj->serial.dma_usage_rx = hint;

12
targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.c
View File

@ -66,11 +66,13 @@ void mbedtls_sha1_clone(mbedtls_sha1_context *dst,
{
unsigned char output[20];
crypto_sha_getinternstate(output, sizeof (output));
dst->sw_ctx.state[0] = nu_get32_be(output);
dst->sw_ctx.state[1] = nu_get32_be(output + 4);
dst->sw_ctx.state[2] = nu_get32_be(output + 8);
dst->sw_ctx.state[3] = nu_get32_be(output + 12);
dst->sw_ctx.state[4] = nu_get32_be(output + 16);
unsigned char *output_pos = output;
unsigned char *output_end = output + (sizeof (output) / sizeof (output[0]));
uint32_t *state_pos = (uint32_t *) &(dst->sw_ctx.state[0]);
while (output_pos != output_end) {
*state_pos ++ = nu_get32_be(output_pos);
output_pos += 4;
}
}
memcpy(dst->sw_ctx.buffer, src->hw_ctx.buffer, src->hw_ctx.buffer_left);
if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) {

1
targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.h
View File

@ -25,7 +25,6 @@
#if defined(MBEDTLS_SHA1_C)
#if defined(MBEDTLS_SHA1_ALT)
#include "sha1.h"
#include "sha_alt_hw.h"
#include "sha1_alt_sw.h"

8
targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.c
View File

@ -36,6 +36,14 @@
#include "mbedtls/sha1.h"
#include <string.h>
#if defined(MBEDTLS_SELF_TEST)
#if defined(MBEDTLS_PLATFORM_C)
#include "mbedtls/platform.h"
#else
#include <stdio.h>
#define mbedtls_printf printf
#endif /* MBEDTLS_PLATFORM_C */
#endif /* MBEDTLS_SELF_TEST */
/* Implementation that should never be optimized out by the compiler */
static void mbedtls_zeroize( void *v, size_t n ) {

15
targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.c
View File

@ -66,14 +66,13 @@ void mbedtls_sha256_clone(mbedtls_sha256_context *dst,
{
unsigned char output[32];
crypto_sha_getinternstate(output, sizeof (output));
dst->sw_ctx.state[0] = nu_get32_be(output);
dst->sw_ctx.state[1] = nu_get32_be(output + 4);
dst->sw_ctx.state[2] = nu_get32_be(output + 8);
dst->sw_ctx.state[3] = nu_get32_be(output + 12);
dst->sw_ctx.state[4] = nu_get32_be(output + 16);
dst->sw_ctx.state[5] = nu_get32_be(output + 20);
dst->sw_ctx.state[6] = nu_get32_be(output + 24);
dst->sw_ctx.state[7] = nu_get32_be(output + 28);
unsigned char *output_pos = output;
unsigned char *output_end = output + (sizeof (output) / sizeof (output[0]));
uint32_t *state_pos = (uint32_t *) &(dst->sw_ctx.state[0]);
while (output_pos != output_end) {
*state_pos ++ = nu_get32_be(output_pos);
output_pos += 4;
}
}
memcpy(dst->sw_ctx.buffer, src->hw_ctx.buffer, src->hw_ctx.buffer_left);
dst->sw_ctx.is224 = src->hw_ctx.is224;

5
targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.h
View File

@ -22,10 +22,9 @@
#include MBEDTLS_CONFIG_FILE
#endif
#if defined(MBEDTLS_SHA1_C)
#if defined(MBEDTLS_SHA256_C)
#if defined(MBEDTLS_SHA256_ALT)
#include "sha256.h"
#include "sha_alt_hw.h"
#include "sha256_alt_sw.h"
@ -103,6 +102,6 @@ void mbedtls_sha256_process( mbedtls_sha256_context *ctx, const unsigned char da
#endif
#endif /* MBEDTLS_SHA256_ALT */
#endif /* MBEDTLS_SHA1_C */
#endif /* MBEDTLS_SHA256_C */
#endif /* sha256_alt.h */

13
targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.c
View File

@ -36,6 +36,17 @@
#include "mbedtls/sha256.h"
#include <string.h>
#if defined(MBEDTLS_SELF_TEST)
#if defined(MBEDTLS_PLATFORM_C)
#include "mbedtls/platform.h"
#else
#include <stdio.h>
#include <stdlib.h>
#define mbedtls_printf printf
#define mbedtls_calloc calloc
#define mbedtls_free free
#endif /* MBEDTLS_PLATFORM_C */
#endif /* MBEDTLS_SELF_TEST */
/* Implementation that should never be optimized out by the compiler */
static void mbedtls_zeroize( void *v, size_t n ) {
@ -303,6 +314,6 @@ void mbedtls_sha256_sw_finish( mbedtls_sha256_sw_context *ctx, unsigned char out
PUT_UINT32_BE( ctx->state[7], output, 28 );
}
#endif /* MBEDTLS_SHA1_ALT */
#endif /* MBEDTLS_SHA256_ALT */
#endif /* MBEDTLS_SHA256_C */

2
targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h
View File

@ -32574,7 +32574,7 @@ typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile
#include "nuc472_acmp.h"
#include "nuc472_adc.h"
#include "nuc472_eadc.h"
#include "nuc472_cap.h"
/* Disable Capture: #include "nuc472_cap.h" */
#include "nuc472_crypto.h"
#include "nuc472_pdma.h"
#include "nuc472_ebi.h"

4
targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_can.c
View File

@ -99,9 +99,9 @@ void CAN_WaitMsg(CAN_T *tCAN)
DEBUG_PRINTF("New Data IN\n");
break;
}
if(tCAN->STATUS & CAN_STATUS_RXOK_Msk)
if(tCAN->STATUS & CAN_STATUS_RXOK_Msk) {
DEBUG_PRINTF("Rx OK\n");
}
if(tCAN->STATUS & CAN_STATUS_LEC_Msk) {
DEBUG_PRINTF("Error\n");
}

370
targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_cap.c
View File

@ -1,370 +0,0 @@
/**************************************************************************//**
* @file cap.c
* @version V0.10
* $Revision: 17 $
* $Date: 14/10/06 3:41p $
* @brief NUC472/NUC442 CAP driver source file
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NUC472_442.h"
/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
@{
*/
/** @addtogroup NUC472_442_CAP_Driver CAP Driver
@{
*/
/** @addtogroup NUC472_442_CAP_EXPORTED_FUNCTIONS CAP Exported Functions
@{
*/
/**
* @brief Open engine clock and sensor clock
*
* @param[in] u32InFormat The bits corresponding VSP, HSP, PCLK, INFMT, SNRTYPE, OUTFMT, PDORD and PNFMT configurations.
* - VSP should be ether \ref CAP_PAR_VSP_LOW or \ref CAP_PAR_VSP_HIGH
* - HSP should be ether \ref CAP_PAR_HSP_LOW or \ref CAP_PAR_HSP_HIGH
* - PCLK should be ether \ref CAP_PAR_PCLKP_LOW or \ref CAP_PAR_PCLKP_HIGH
* - INFMT should be ether \ref CAP_PAR_INFMT_YUV422 or \ref CAP_PAR_INFMT_RGB565
* - SNRTYPE should be ether \ref CAP_PAR_SENTYPE_CCIR601 or \ref CAP_PAR_SENTYPE_CCIR656
* - OUTFMT should be one of the following setting
* - \ref CAP_PAR_OUTFMT_YUV422
* - \ref CAP_PAR_OUTFMT_ONLY_Y
* - \ref CAP_PAR_OUTFMT_RGB555
* - \ref CAP_PAR_OUTFMT_RGB565
* - PDORD should be one of the following setting
* - \ref CAP_PAR_INDATORD_YUYV
* - \ref CAP_PAR_INDATORD_YVYU
* - \ref CAP_PAR_INDATORD_UYVY
* - \ref CAP_PAR_INDATORD_VYUY
* - \ref CAP_PAR_INDATORD_RGGB
* - \ref CAP_PAR_INDATORD_BGGR
* - \ref CAP_PAR_INDATORD_GBRG
* - \ref CAP_PAR_INDATORD_GRBG
* - PNFMT should be one of the following setting
* - \ref CAP_PAR_PLNFMT_YUV422
* - \ref CAP_PAR_PLNFMT_YUV420
*
* @param[in] u32OutFormet Capture output format, should be one of following setting
* - \ref CAP_CTL_PKTEN
* - \ref CAP_CTL_PLNEN
*
* @return None
*
* @details Initialize the Image Capture Interface. Register a call back for driver internal using
*/
void CAP_Open(uint32_t u32InFormat, uint32_t u32OutFormet)
{
ICAP->PAR = (ICAP->PAR & ~0x000007BF) | u32InFormat;
ICAP->CTL = (ICAP->CTL & ~0x00000060) | u32OutFormet;
}
/**
* @brief Set Cropping Window Starting Address and Size
*
* @param[in] u32VStart: Cropping Window Vertical Starting Address. It should be 0 ~ 0x7FF.
*
* @param[in] u32HStart: Cropping Window Horizontal Starting Address. It should be 0 ~ 0x7FF.
*
* @param[in] u32Height: Cropping Window Height . It should be 0 ~ 0x7FF.
*
* @param[in] u32Width: Cropping Window Width. It should be 0 ~ 0x7FF.
*
* @return None
*
* @details Set Cropping Window Starting Address Register
*/
void CAP_SetCroppingWindow(uint32_t u32VStart,uint32_t u32HStart, uint32_t u32Height, uint32_t u32Width)
{
ICAP->CWSP = (ICAP->CWSP & ~(CAP_CWSP_CWSADDRV_Msk | CAP_CWSP_CWSADDRH_Msk))
| (((u32VStart << 16) | u32HStart));
ICAP->CWS = (ICAP->CWS & ~(CAP_CWS_CWH_Msk | CAP_CWS_CWW_Msk))
| ((u32Height << 16)| u32Width);
}
/**
* @brief Set System Memory Packet Base Address0 Register
*
* @param[in] u32Address : set PKTBA0 register, It should be 0x0 ~ 0xFFFFFFFF
*
* @return None
*
* @details Set System Memory Packet Base Address Register
*/
void CAP_SetPacketBuf(uint32_t u32Address )
{
ICAP->PKTBA0 = u32Address;
ICAP->CTL |= CAP_CTL_UPDATE_Msk;
}
/**
* @brief Set System Memory Planar Y, U and V Base Address Registers.
*
* @param[in] u32YAddr : set YBA register, It should be 0x0 ~ 0xFFFFFFFF
*
* @param[in] u32UAddr : set UBA register, It should be 0x0 ~ 0xFFFFFFFF
*
* @param[in] u32VAddr : set VBA register, It should be 0x0 ~ 0xFFFFFFFF
*
* @return None
*
* @details Set System Memory Planar Y,U and V Base Address Registers
*/
void CAP_SetPlanarBuf(uint32_t u32YAddr, uint32_t u32UAddr, uint32_t u32VAddr)
{
ICAP->YBA = u32YAddr;
ICAP->UBA = u32UAddr;
ICAP->VBA = u32VAddr;
ICAP->CTL |= CAP_CTL_UPDATE_Msk;
}
/**
* @brief Close Image Capture Interface
*
* @return None
*/
void CAP_Close(void)
{
ICAP->CTL &= ~CAP_CTL_CAPEN;
}
/**
* @brief Set CAP Interrupt
*
* @param[in] u32IntMask Interrupt settings. It could be
* - \ref CAP_INT_VIEN_Msk
* - \ref CAP_INT_MEIEN_Msk
* - \ref CAP_INT_ADDRMIEN_Msk
* - \ref CAP_INT_MDIEN_Msk
* @return None
*
* @details Set Video Frame End Interrupt Enable,
* System Memory Error Interrupt Enable,
* Address Match Interrupt Enable,
* Motion Detection Output Finish Interrupt Enable.
*/
void CAP_EnableInt(uint32_t u32IntMask)
{
ICAP->INT = (ICAP->INT & ~(CAP_INT_VIEN_Msk | CAP_INT_MEIEN_Msk | CAP_INT_ADDRMIEN_Msk | CAP_INT_MDIEN_Msk ) )
| u32IntMask;
}
/**
* @brief Disable CAP Interrupt
*
* @param[in] u32IntMask Interrupt settings. It could be
* - \ref CAP_INT_VINTF_Msk
* - \ref CAP_INT_MEINTF_Msk
* - \ref CAP_INT_ADDRMINTF_Msk
* - \ref CAP_INT_MDINTF_Msk
* @return None
*
* @details Disable Video Frame End Interrupt ,
* System Memory Error Interrupt ,
* Address Match Interrupt and
* Motion Detection Output Finish Interrupt .
*/
void CAP_DisableInt(uint32_t u32IntMask)
{
ICAP->INT = (ICAP->INT & ~(u32IntMask) ) ;
}
/**
* @brief Start Image Capture Interface
*
* @return None
*/
void CAP_Start(void)
{
ICAP->CTL |= CAP_CTL_CAPEN;
}
/**
* @brief Stop Image Capture Interface
*
* @param[in] u32FrameComplete :
* TRUE: Capture module automatically disable the CAP module after a frame had been captured
* FALSE: Stop Capture module now
* @return None
*
* @details if u32FrameComplete is set to TRUE then get a new frame and disable CAP module
*/
void CAP_Stop(uint32_t u32FrameComplete)
{
if(u32FrameComplete==TRUE)
ICAP->CTL &= ~CAP_CTL_CAPEN;
else {
ICAP->CTL |= CAP_CTL_SHUTTER_Msk;
while(CAP_IS_STOPPED());
}
}
/**
* @brief Set Packet Scaling Vertical and Horizontal Factor Register
*
* @param[in] u32VNumerator: Packet Scaling Vertical Factor N. It should be 0 ~ FFFF.
*
* @param[in] u32VDenominator: Packet Scaling Vertical Factor M. It should be 0 ~ FFFF.
*
* @param[in] u32HNumerator: Packet Scaling Vertical Factor N. It should be 0 ~ FFFF.
*
* @param[in] u32HDenominator: Packet Scaling Vertical Factor M. It should be 0 ~ FFFF.
*
* @return None
*
*/
void CAP_SetPacketScaling(uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator)
{
uint32_t u32NumeratorL, u32NumeratorH;
uint32_t u32DenominatorL, u32DenominatorH;
u32NumeratorL = u32VNumerator&0xFF;
u32NumeratorH=u32VNumerator>>8;
u32DenominatorL = u32VDenominator&0xFF;
u32DenominatorH = u32VDenominator>>8;
ICAP->PKTSL = (ICAP->PKTSL & ~(CAP_PKTSL_PKTSVNL_Msk | CAP_PKTSL_PKTSVML_Msk))
| ((u32NumeratorL << 24)| (u32DenominatorL << 16));
ICAP->PKTSM = (ICAP->PKTSM & ~(CAP_PKTSM_PKTSVNH_Msk | CAP_PKTSM_PKTSVMH_Msk))
| ((u32NumeratorH << 24) | (u32DenominatorH << 16));
u32NumeratorL = u32HNumerator&0xFF;
u32NumeratorH=u32HNumerator>>8;
u32DenominatorL = u32HDenominator&0xFF;
u32DenominatorH = u32HDenominator>>8;
ICAP->PKTSL = (ICAP->PKTSL & ~(CAP_PKTSL_PKTSHNL_Msk | CAP_PKTSL_PKTSHML_Msk))
| ((u32NumeratorL << 8)| u32DenominatorL);
ICAP->PKTSM = (ICAP->PKTSM & ~(CAP_PKTSM_PKTSHNH_Msk | CAP_PKTSM_PKTSHMH_Msk))
| ((u32NumeratorH << 8) | u32DenominatorH);
}
/**
* @brief Set Planar Scaling Vertical and Horizontal Factor Register
*
* @param[in] u32VNumerator: Planar Scaling Vertical Factor N. It should be 0 ~ FFFF.
*
* @param[in] u32VDenominator: Planar Scaling Vertical Factor M. It should be 0 ~ FFFF.
*
* @param[in] u32HNumerator: Planar Scaling Vertical Factor N. It should be 0 ~ FFFF.
*
* @param[in] u32HDenominator: Planar Scaling Vertical Factor M. It should be 0 ~ FFFF.
*
* @return None
*
*/
void CAP_SetPlanarScaling(uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator)
{
uint32_t u32NumeratorL, u32NumeratorH;
uint32_t u32DenominatorL, u32DenominatorH;
u32NumeratorL = u32VNumerator&0xFF;
u32NumeratorH = u32VNumerator>>8;
u32DenominatorL = u32VDenominator&0xFF;
u32DenominatorH = u32VDenominator>>8;
ICAP->PLNSL = (ICAP->PLNSL & ~(CAP_PLNSL_PLNSVNL_Msk | CAP_PLNSL_PLNSVML_Msk))
| ((u32NumeratorL << 24)| (u32DenominatorL << 16));
ICAP->PLNSM = (ICAP->PLNSM & ~(CAP_PLNSM_PLNSVNH_Msk | CAP_PLNSM_PLNSVMH_Msk))
| ((u32NumeratorH << 24)| (u32DenominatorH << 16));
u32NumeratorL = u32HNumerator&0xFF;
u32NumeratorH = u32HNumerator>>8;
u32DenominatorL = u32HDenominator&0xFF;
u32DenominatorH = u32HDenominator>>8;
ICAP->PLNSL = (ICAP->PLNSL & ~(CAP_PLNSL_PLNSHNL_Msk | CAP_PLNSL_PLNSHML_Msk))
| ((u32NumeratorL << 8)| u32DenominatorL);
ICAP->PLNSM = (ICAP->PLNSM & ~(CAP_PLNSM_PLNSHNH_Msk | CAP_PLNSM_PLNSHMH_Msk))
| ((u32NumeratorH << 8)| u32DenominatorH);
}
/**
* @brief Set Packet Frame Output Pixel Stride Width.
*
* @param[in] u32Stride : set PKTSTRIDE register, It should be 0x0 ~ 0x3FFF
*
* @return None
*
* @details Set Packet Frame Output Pixel Stride Width
*/
void CAP_SetPacketStride(uint32_t u32Stride )
{
ICAP->STRIDE = (ICAP->STRIDE & ~CAP_STRIDE_PKTSTRIDE_Msk) | u32Stride;
}
/**
* @brief Set Planar Frame Output Pixel Stride Width.
*
* @param[in] u32Stride : set PLNSTRIDE register, It should be 0x0 ~ 0x3FFF
*
* @return None
*
* @details Set Planar Frame Output Pixel Stride Width
*/
void CAP_SetPlanarStride(uint32_t u32Stride )
{
ICAP->STRIDE = (ICAP->STRIDE & ~CAP_STRIDE_PLNSTRIDE_Msk) | u32Stride<<CAP_STRIDE_PLNSTRIDE_Pos;
}
/**
* @brief Enable Motion Detection Function
*
* @param[in] u32Freq: Motion Detection Detect Frequency. It should be 0x0 ~ 0x3.
*
* @param[in] u32BlockSize: Motion Detection Block Size
* FALSE : 16x16
* TRUE : 8x8
*
* @param[in] u32Format: Motion Detection Save Mode
* FALSE : 1 bit DIFF + 7 Y Differential
* TRUE : 1 bit DIFF only
*
* @param[in] u32Threshold: Motion Detection Detect Threshold. It should be 0x0 ~ 0x1F.
*
* @param[in] u32YDetAddr : Motion Detection Detect Temp Y Output Address
*
* @param[in] u32DetAddr: Motion Detection Detect Address
*
* @return None
*
* @details Set Planar Frame Output Pixel Stride Width
*/
void CAP_EnableMotionDet(uint32_t u32Freq, uint32_t u32BlockSize, uint32_t u32Format, uint32_t u32Threshold, uint32_t u32YDetAddr, uint32_t u32DetAddr)
{
ICAP->MD = (ICAP->MD & ~(CAP_MD_MDSM_Msk | CAP_MD_MDBS_Msk | CAP_MD_MDEN_Msk)) |
((CAP_MD_MDEN_Msk | (u32BlockSize?CAP_MD_MDBS_Msk:0)) |
(u32Format?CAP_MD_MDSM_Msk:0));
ICAP->MD = (ICAP->MD & ~CAP_MD_MDDF_Msk) | (u32Freq<<CAP_MD_MDDF_Pos);
ICAP->MD = (ICAP->MD & ~CAP_MD_MDTHR_Msk) | (u32Threshold<<CAP_MD_MDTHR_Pos);
ICAP->MDYADDR = u32YDetAddr;
ICAP->MDADDR = u32DetAddr;
}
/**
* @brief Enable Motion Detection Function
*
* @return None
*
* @details Set Planar Frame Output Pixel Stride Width
*/
void CAP_DisableMotionDet(void)
{
ICAP->MD &= ~CAP_MD_MDEN_Msk;
}
/*@}*/ /* end of group NUC472_442_CAP_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group NUC472_442_CAP_Driver */
/*@}*/ /* end of group NUC472_442_Device_Driver */
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

50
targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_emac.c
View File

@ -204,7 +204,7 @@ static void EMAC_PhyInit(void)
break;
}
if(!EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID) { // Cable not connected
if(~EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) && PHY_STATUS_LINK_VALID) { // Cable not connected
printf("Unplug\n..");
EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
@ -485,10 +485,10 @@ uint32_t EMAC_RecvPkt(uint8_t *pu8Data, uint32_t *pu32Size)
u32Count = 1;
} else {
// Save Error status if necessary
if (status & EMAC_RXFD_RP);
if (status & EMAC_RXFD_ALIE);
if (status & EMAC_RXFD_PTLE);
if (status & EMAC_RXFD_CRCE);
if (status & EMAC_RXFD_RP) {;}
if (status & EMAC_RXFD_ALIE) {;}
if (status & EMAC_RXFD_PTLE) {;}
if (status & EMAC_RXFD_CRCE) {;}
}
}
}
@ -545,10 +545,10 @@ uint32_t EMAC_RecvPktTS(uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec,
u32Count = 1;
} else {
// Save Error status if necessary
if (status & EMAC_RXFD_RP);
if (status & EMAC_RXFD_ALIE);
if (status & EMAC_RXFD_PTLE);
if (status & EMAC_RXFD_CRCE);
if (status & EMAC_RXFD_RP) {;}
if (status & EMAC_RXFD_ALIE) {;}
if (status & EMAC_RXFD_PTLE) {;}
if (status & EMAC_RXFD_CRCE) {;}
}
}
}
@ -664,14 +664,14 @@ uint32_t EMAC_SendPktDone(void)
u32Count++;
} else {
// Do nothing here on error.
if (status & EMAC_TXFD_TXABT);
if (status & EMAC_TXFD_DEF);
if (status & EMAC_TXFD_PAU);
if (status & EMAC_TXFD_EXDEF);
if (status & EMAC_TXFD_NCS);
if (status & EMAC_TXFD_SQE);
if (status & EMAC_TXFD_LC);
if (status & EMAC_TXFD_TXHA);
if (status & EMAC_TXFD_TXABT) {;}
if (status & EMAC_TXFD_DEF) {;}
if (status & EMAC_TXFD_PAU) {;}
if (status & EMAC_TXFD_EXDEF) {;}
if (status & EMAC_TXFD_NCS) {;}
if (status & EMAC_TXFD_SQE) {;}
if (status & EMAC_TXFD_LC) {;}
if (status & EMAC_TXFD_TXHA) {;}
}
// restore descriptor link list and data pointer they will be overwrite if time stamp enabled
@ -727,14 +727,14 @@ uint32_t EMAC_SendPktDoneTS(uint32_t *pu32Sec, uint32_t *pu32Nsec)
*pu32Nsec = EMAC_Subsec2Nsec(desc->u32Data); // Sub nano second store in DATA field
} else {
// Do nothing here on error.
if (status & EMAC_TXFD_TXABT);
if (status & EMAC_TXFD_DEF);
if (status & EMAC_TXFD_PAU);
if (status & EMAC_TXFD_EXDEF);
if (status & EMAC_TXFD_NCS);
if (status & EMAC_TXFD_SQE);
if (status & EMAC_TXFD_LC);
if (status & EMAC_TXFD_TXHA);
if (status & EMAC_TXFD_TXABT) {;}
if (status & EMAC_TXFD_DEF) {;}
if (status & EMAC_TXFD_PAU) {;}
if (status & EMAC_TXFD_EXDEF) {;}
if (status & EMAC_TXFD_NCS) {;}
if (status & EMAC_TXFD_SQE) {;}
if (status & EMAC_TXFD_LC) {;}
if (status & EMAC_TXFD_TXHA) {;}
}
// restore descriptor link list and data pointer they will be overwrite if time stamp enabled

24
targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.c
View File

@ -70,7 +70,7 @@ uint32_t PWM_ConfigOutputChannel2 (PWM_T *pwm,
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 1)
u32PWM_CLock = __LXT;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 2)
u32PWM_CLock = SystemCoreClock;
u32PWM_CLock = CLK_GetPCLKFreq();
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 3)
u32PWM_CLock = __HIRC;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 4)
@ -81,7 +81,7 @@ uint32_t PWM_ConfigOutputChannel2 (PWM_T *pwm,
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
u32PWM_CLock = __LXT;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
u32PWM_CLock = SystemCoreClock;
u32PWM_CLock = CLK_GetPCLKFreq();
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
u32PWM_CLock = __HIRC;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
@ -92,7 +92,7 @@ uint32_t PWM_ConfigOutputChannel2 (PWM_T *pwm,
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
u32PWM_CLock = __LXT;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
u32PWM_CLock = SystemCoreClock;
u32PWM_CLock = CLK_GetPCLKFreq();
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
u32PWM_CLock = __HIRC;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
@ -105,7 +105,7 @@ uint32_t PWM_ConfigOutputChannel2 (PWM_T *pwm,
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
u32PWM_CLock = __LXT;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
u32PWM_CLock = SystemCoreClock;
u32PWM_CLock = CLK_GetPCLKFreq();
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
u32PWM_CLock = __HIRC;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
@ -116,7 +116,7 @@ uint32_t PWM_ConfigOutputChannel2 (PWM_T *pwm,
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
u32PWM_CLock = __LXT;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
u32PWM_CLock = SystemCoreClock;
u32PWM_CLock = CLK_GetPCLKFreq();
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
u32PWM_CLock = __HIRC;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
@ -127,7 +127,7 @@ uint32_t PWM_ConfigOutputChannel2 (PWM_T *pwm,
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
u32PWM_CLock = __LXT;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
u32PWM_CLock = SystemCoreClock;
u32PWM_CLock = CLK_GetPCLKFreq();
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
u32PWM_CLock = __HIRC;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
@ -218,7 +218,7 @@ uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 1)
u32PWM_CLock = __LXT;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 2)
u32PWM_CLock = SystemCoreClock;
u32PWM_CLock = CLK_GetPCLKFreq();
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 3)
u32PWM_CLock = __HIRC;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 4)
@ -229,7 +229,7 @@ uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
u32PWM_CLock = __LXT;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
u32PWM_CLock = SystemCoreClock;
u32PWM_CLock = CLK_GetPCLKFreq();
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
u32PWM_CLock = __HIRC;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
@ -240,7 +240,7 @@ uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
u32PWM_CLock = __LXT;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
u32PWM_CLock = SystemCoreClock;
u32PWM_CLock = CLK_GetPCLKFreq();
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
u32PWM_CLock = __HIRC;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
@ -253,7 +253,7 @@ uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
u32PWM_CLock = __LXT;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
u32PWM_CLock = SystemCoreClock;
u32PWM_CLock = CLK_GetPCLKFreq();
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
u32PWM_CLock = __HIRC;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
@ -264,7 +264,7 @@ uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
u32PWM_CLock = __LXT;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
u32PWM_CLock = SystemCoreClock;
u32PWM_CLock = CLK_GetPCLKFreq();
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
u32PWM_CLock = __HIRC;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
@ -275,7 +275,7 @@ uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
u32PWM_CLock = __LXT;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
u32PWM_CLock = SystemCoreClock;
u32PWM_CLock = CLK_GetPCLKFreq();
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
u32PWM_CLock = __HIRC;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH45SEL_Pos))

20
targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_uart.c
View File

@ -1,8 +1,8 @@
/**************************************************************************//**
* @file uart.c
* @version V1.00
* $Revision: 13 $
* $Date: 14/10/03 1:55p $
* $Revision: 14 $
* $Date: 15/11/26 10:47a $
* @brief NUC472/NUC442 UART driver source file
*
* @note
@ -118,7 +118,7 @@ void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag )
void UART_EnableFlowCtrl(UART_T* uart )
{
uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
uart->MODEM &= UART_MODEM_RTS_Msk;
uart->MODEM &= ~UART_MODEM_RTS_Msk;
uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk;
}
@ -161,7 +161,7 @@ void UART_Open(UART_T* uart, uint32_t u32baudrate)
uint32_t u32Clk;
uint32_t u32Baud_Div;
u32ClkTbl[1] = CLK_GetPLLClockFreq();;
u32ClkTbl[1] = CLK_GetPLLClockFreq();
u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UARTSEL_Msk) >> CLK_CLKSEL1_UARTSEL_Pos;
@ -272,7 +272,17 @@ void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC)
*/
void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction)
{
uart->BAUD = UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER(12000000, 57600);
uint8_t u8UartClkSrcSel;
uint32_t u32ClkTbl[4] = {__HXT, 0, __HIRC, __HIRC};
uint32_t u32Clk;
u32ClkTbl[1] = CLK_GetPLLClockFreq();
u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UARTSEL_Msk) >> CLK_CLKSEL1_UARTSEL_Pos;
u32Clk = (u32ClkTbl[u8UartClkSrcSel]) / (((CLK->CLKDIV0 & CLK_CLKDIV0_UARTDIV_Msk) >> CLK_CLKDIV0_UARTDIV_Pos) + 1);
uart->BAUD = UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER(u32Clk, u32Buadrate);
uart->IRDA &= ~UART_IRDA_TXINV_Msk;
uart->IRDA |= UART_IRDA_RXINV_Msk;

6
targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_uart.h
View File

@ -1,8 +1,8 @@
/**************************************************************************//**
* @file uart.h
* @version V1.00
* $Revision: 19 $
* $Date: 14/10/07 9:28a $
* $Revision: 20 $
* $Date: 15/11/30 1:35p $
* @brief NUC472/NUC442 UART driver header file
*
* @note
@ -310,7 +310,7 @@ extern "C"
* - \ref UART_INTSTS_LINIF_Msk : LIN Bus Flag.
* - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag
* - \ref UART_INTSTS_RXTOIF_Msk : Rx time-out interrupt Flag
* - \ref UART_INTSTS_MODENIF_Msk : Modem interrupt Flag
* - \ref UART_INTSTS_MODEMIF_Msk : Modem interrupt Flag
* - \ref UART_INTSTS_RLSIF_Msk : Rx Line status interrupt Flag
* - \ref UART_INTSTS_THREIF_Msk : Tx empty interrupt Flag
* - \ref UART_INTSTS_RDAIF_Msk : Rx ready interrupt Flag

7
targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c
View File

@ -94,11 +94,14 @@ void lp_ticker_init(void)
TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
// Schedule wakeup to match semantics of lp_ticker_get_compare_match()
lp_ticker_set_interrupt(wakeup_tick);
// NOTE: TIMER_Start() first and then lp_ticker_set_interrupt(); otherwise, we may get stuck in lp_ticker_read() because
// timer is not running.
// Start timer
TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
// Schedule wakeup to match semantics of lp_ticker_get_compare_match()
lp_ticker_set_interrupt(wakeup_tick);
}
timestamp_t lp_ticker_read()

16
targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c
View File

@ -330,8 +330,10 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
MBED_ASSERT(uart_rts == obj->serial.uart);
// Enable the pin for RTS function
pinmap_pinout(rxflow, PinMap_UART_RTS);
// nRTS pin output is high level active
uart_base->MODEM = (uart_base->MODEM & ~UART_MODEM_RTSACTLV_Msk) | UART_MODEM_RTSACTLV_Msk;
// nRTS pin output is low level active
uart_base->MODEM |= UART_MODEM_RTSACTLV_Msk;
uart_base->MODEM &= ~UART_MODEM_RTS_Msk;
uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES;
// Enable RTS
uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk;
@ -343,8 +345,8 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
MBED_ASSERT(uart_cts == obj->serial.uart);
// Enable the pin for CTS function
pinmap_pinout(txflow, PinMap_UART_CTS);
// nCTS pin input is high level active
uart_base->MODEMSTS = (uart_base->MODEMSTS & ~UART_MODEMSTS_CTSACTLV_Msk) | UART_MODEMSTS_CTSACTLV_Msk;
// nCTS pin input is low level active
uart_base->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
// Enable CTS
uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk;
}
@ -519,9 +521,6 @@ static void uart_irq(serial_t *obj)
#if DEVICE_SERIAL_ASYNCH
int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
{
// NOTE: tx_width is deprecated. Assume its value is databits ceiled to the nearest number among 8, 16, and 32.
tx_width = (obj->serial.databits <= 8) ? 8 : (obj->serial.databits <= 16) ? 16 : 32;
MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32);
obj->serial.dma_usage_tx = hint;
@ -574,9 +573,6 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
{
// NOTE: rx_width is deprecated. Assume its value is databits ceiled to the nearest number among 8, 16, and 32.
rx_width = (obj->serial.databits <= 8) ? 8 : (obj->serial.databits <= 16) ? 16 : 32;
MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32);
obj->serial.dma_usage_rx = hint;

2
targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c
View File

@ -86,7 +86,7 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l
memcpy(output, &tmpBuff, length);
*output_length = length;
} else {
for (int i = 0; i < (length/32); i++) {
for (size_t i = 0; i < (length/32); i++) {
trng_get(output);
*output_length += 32;
output += 32;