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Merge pull request #7925 from maciejbocianski/qspi_hal_test_refactoring 

Qspi hal test refactoring/update
pull/7970/head^2
Martin Kojtal 2018-09-21 09:40:10 +02:00 committed by GitHub
parent 8f7c0ae18d cffd581308
commit 6a34251b07
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
10 changed files with 524 additions and 337 deletions
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192
TESTS/mbed_hal/qspi/flash_configs/MX25R6435F_config.h
View File

@ -1,192 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2018-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_QSPI_FLASH_MX25R6435F_H
#define MBED_QSPI_FLASH_MX25R6435F_H
#define QSPI_FLASH_CHIP_STRING "macronix MX25R6435F"
// Command for reading status register
#define QSPI_CMD_RDSR 0x05
// Command for reading configuration register
#define QSPI_CMD_RDCR0 0x15
// Command for writing status/configuration register
#define QSPI_CMD_WRSR 0x01
// Command for reading security register
#define QSPI_CMD_RDSCUR 0x2B
// Command for setting Reset Enable
#define QSPI_CMD_RSTEN 0x66
// Command for setting Reset
#define QSPI_CMD_RST 0x99
// Command for setting write enable
#define QSPI_CMD_WREN 0x06
// Command for setting write disable
#define QSPI_CMD_WRDI 0x04
// WRSR operations max time [us] (datasheet max time + 15%)
#define QSPI_WRSR_MAX_TIME 34500 // 30ms
// general wait max time [us]
#define QSPI_WAIT_MAX_TIME 100000 // 100ms
// Commands for writing (page programming)
#define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
#define QSPI_CMD_WRITE_4IO 0x38 // 1-4-4 mode
// write operations max time [us] (datasheet max time + 15%)
#define QSPI_PAGE_PROG_MAX_TIME 11500 // 10ms
#define QSPI_PAGE_SIZE 256 // 256B
// Commands for reading
#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
#define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
#define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode
#define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode
#define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode
#define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode
#define QSPI_READ_1IO_DUMMY_CYCLE 0
#define QSPI_READ_FAST_DUMMY_CYCLE 8
#define QSPI_READ_2IO_DUMMY_CYCLE 4
#define QSPI_READ_1I2O_DUMMY_CYCLE 8
#define QSPI_READ_4IO_DUMMY_CYCLE 6
#define QSPI_READ_1I4O_DUMMY_CYCLE 8
// Commands for erasing
#define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
#define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB
#define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
#define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
// erase operations max time [us] (datasheet max time + 15%)
#define QSPI_ERASE_SECTOR_MAX_TIME 276000 // 240 ms
#define QSPI_ERASE_BLOCK_32_MAX_TIME 3450000 // 3s
#define QSPI_ERASE_BLOCK_64_MAX_TIME 4025000 // 3.5s
// max frequency for basic rw operation
#define QSPI_COMMON_MAX_FREQUENCY 32000000
#define QSPI_STATUS_REG_SIZE 1
#define QSPI_CONFIG_REG_0_SIZE 2
#define QSPI_SECURITY_REG_SIZE 1
#define QSPI_MAX_REG_SIZE 2
// status register
#define STATUS_BIT_WIP (1 << 0) // write in progress bit
#define STATUS_BIT_WEL (1 << 1) // write enable latch
#define STATUS_BIT_BP0 (1 << 2) //
#define STATUS_BIT_BP1 (1 << 3) //
#define STATUS_BIT_BP2 (1 << 4) //
#define STATUS_BIT_BP3 (1 << 5) //
#define STATUS_BIT_QE (1 << 6) // Quad Enable
#define STATUS_BIT_SRWD (1 << 7) // status register write protect
// configuration register 0
// bit 0, 1, 2, 4, 5, 7 reserved
#define CONFIG0_BIT_TB (1 << 3) // Top/Bottom area protect
#define CONFIG0_BIT_DC (1 << 6) // Dummy Cycle
// configuration register 1
// bit 0, 2, 3, 4, 5, 6, 7 reserved
#define CONFIG1_BIT_LH (1 << 1) // 0 = Ultra Low power mode, 1 = High performance mode
// single quad enable flag for both dual and quad mode
#define QUAD_ENABLE() \
\
uint8_t reg_data[QSPI_STATUS_REG_SIZE]; \
\
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
reg_data[0] = STATUS_BIT_QE; \
qspi.cmd.build(QSPI_CMD_WRSR); \
\
if (qspi_command_transfer(&qspi.handle, qspi.cmd.get(), \
reg_data, QSPI_STATUS_REG_SIZE, NULL, 0) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
memset(reg_data, 0, QSPI_STATUS_REG_SIZE); \
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & STATUS_BIT_QE) != 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define QUAD_DISABLE() \
\
uint8_t reg_data[QSPI_STATUS_REG_SIZE]; \
\
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
reg_data[0] = 0; \
qspi.cmd.build(QSPI_CMD_WRSR); \
\
if (qspi_command_transfer(&qspi.handle, qspi.cmd.get(), \
reg_data, QSPI_STATUS_REG_SIZE, NULL, 0) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
reg_data[0] = 0; \
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & STATUS_BIT_QE) == 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define FAST_MODE_ENABLE() \
\
qspi_status_t ret; \
const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
uint8_t reg_data[reg_size]; \
\
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[2] |= CONFIG1_BIT_LH; \
qspi.cmd.build(QSPI_CMD_WRSR); \
\
return qspi_command_transfer(&qspi.handle, qspi.cmd.get(), \
reg_data, reg_size, NULL, 0)
#endif // MBED_QSPI_FLASH_MX25R6435F_H

112
TESTS/mbed_hal/qspi/flash_configs/MX25R3235F_config.h → TESTS/mbed_hal/qspi/flash_configs/MX25RXX35F_config.h
View File

@ -13,11 +13,11 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_QSPI_FLASH_MX25R3235F_H
#define MBED_QSPI_FLASH_MX25R3235F_H
#ifndef MBED_QSPI_FLASH_MX25RXX35F_H
#define MBED_QSPI_FLASH_MX25RXX35F_H
#define QSPI_FLASH_CHIP_STRING "macronix MX25R3235F"
#define QSPI_FLASH_CHIP_STRING "macronix MX25RXX35F"
// Command for reading status register
#define QSPI_CMD_RDSR 0x05
@ -52,6 +52,8 @@
#define QSPI_PAGE_PROG_MAX_TIME 11500 // 10ms
#define QSPI_PAGE_SIZE 256 // 256B
#define QSPI_SECTOR_SIZE 4096 // 4kB
#define QSPI_SECTOR_COUNT 32 // adjusted to MX25R1035F smallest one from MX25RXX35F family
// Commands for reading
#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
@ -79,7 +81,7 @@
#define QSPI_ERASE_BLOCK_32_MAX_TIME 3450000 // 3s
#define QSPI_ERASE_BLOCK_64_MAX_TIME 4025000 // 3.5s
// max frequency for basic rw operation
// max frequency for basic rw operation (for fast mode)
#define QSPI_COMMON_MAX_FREQUENCY 32000000
#define QSPI_STATUS_REG_SIZE 1
@ -107,21 +109,28 @@
#define CONFIG1_BIT_LH (1 << 1) // 0 = Ultra Low power mode, 1 = High performance mode
// single quad enable flag for both dual and quad mode
#define QUAD_ENABLE() \
#define EXTENDED_SPI_ENABLE() \
\
uint8_t reg_data[QSPI_STATUS_REG_SIZE]; \
const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
uint8_t reg_data[reg_size] = { 0 }; \
\
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
reg_data[0] = STATUS_BIT_QE; \
qspi.cmd.build(QSPI_CMD_WRSR); \
\
if (qspi_command_transfer(&qspi.handle, qspi.cmd.get(), \
reg_data, QSPI_STATUS_REG_SIZE, NULL, 0) != QSPI_STATUS_OK) { \
if (write_register(QSPI_CMD_WRSR, reg_data, \
reg_size, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
@ -137,20 +146,28 @@
#define QUAD_DISABLE() \
#define EXTENDED_SPI_DISABLE() \
\
uint8_t reg_data[QSPI_STATUS_REG_SIZE]; \
const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
uint8_t reg_data[reg_size] = { 0 }; \
\
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
reg_data[0] = 0; \
qspi.cmd.build(QSPI_CMD_WRSR); \
reg_data[0] &= ~(STATUS_BIT_QE); \
\
if (qspi_command_transfer(&qspi.handle, qspi.cmd.get(), \
reg_data, QSPI_STATUS_REG_SIZE, NULL, 0) != QSPI_STATUS_OK) { \
if (write_register(QSPI_CMD_WRSR, reg_data, \
reg_size, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
@ -168,7 +185,6 @@
#define FAST_MODE_ENABLE() \
\
qspi_status_t ret; \
const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
uint8_t reg_data[reg_size]; \
\
@ -181,12 +197,58 @@
return QSPI_STATUS_ERROR; \
} \
\
reg_data[2] |= CONFIG1_BIT_LH; \
qspi.cmd.build(QSPI_CMD_WRSR); \
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return qspi_command_transfer(&qspi.handle, qspi.cmd.get(), \
reg_data, reg_size, NULL, 0)
reg_data[2] |= CONFIG1_BIT_LH; \
if (write_register(QSPI_CMD_WRSR, reg_data, \
reg_size, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
if (read_register(CONFIG_REG0, reg_data, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[1] & CONFIG1_BIT_LH) != 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define FAST_MODE_DISABLE() \
\
const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
uint8_t reg_data[reg_size]; \
\
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[2] &= ~(CONFIG1_BIT_LH); \
if (write_register(QSPI_CMD_WRSR, reg_data, \
reg_size, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
if (read_register(CONFIG_REG0, reg_data, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[1] & CONFIG1_BIT_LH) == 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#endif // MBED_QSPI_FLASH_MX25R3235F_H
#endif // MBED_QSPI_FLASH_MX25RXX35F_H

130
TESTS/mbed_hal/qspi/flash_configs/N25Q128A_config.h
View File

@ -58,18 +58,24 @@
#define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
#define QSPI_CMD_WRITE_2IO 0xD2 // 1-2-2 mode
#define QSPI_CMD_WRITE_4IO 0x12 // 1-4-4 mode
#define QSPI_CMD_WRITE_DPI 0xD2 // 2-2-2 mode
#define QSPI_CMD_WRITE_QPI 0x12 // 4-4-4 mode
// write operations max time [us] (datasheet max time + 15%)
#define QSPI_PAGE_PROG_MAX_TIME 5750 // 5ms
#define QSPI_PAGE_SIZE 256 // 256B
#define QSPI_SECTOR_SIZE 4096 // 4kB
#define QSPI_SECTOR_COUNT 4096
// Commands for reading
#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
#define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
#define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode
#define QSPI_CMD_READ_DPI 0xBB // 2-2-2 mode
#define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode
#define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode
#define QSPI_CMD_READ_QPI 0xEB // 4-4-4 mode
#define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode
@ -88,7 +94,7 @@
#define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
// erase operations max time [us] (datasheet max time + 15%)
#define QSPI_ERASE_SECTOR_MAX_TIME 276000 // 240 ms
#define QSPI_ERASE_SECTOR_MAX_TIME 920000 // 0.8s
#define QSPI_ERASE_BLOCK_32_MAX_TIME 3000000 // 3s
#define QSPI_ERASE_BLOCK_64_MAX_TIME 3500000 // 3.5s
@ -155,28 +161,122 @@
#define DUAL_ENABLE() \
/* TODO: add implementation */ \
return QSPI_STATUS_OK
\
uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
\
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[0] = reg_data[0] & ~(CONFIG2_BIT_DE); \
if (write_register(QSPI_CMD_WRCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
qspi.cmd.configure(MODE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8); \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & (CONFIG2_BIT_DE)) == 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define DUAL_DISABLE() \
/* TODO: add implementation */ \
return QSPI_STATUS_OK
\
uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
\
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[0] = reg_data[0] | (CONFIG2_BIT_DE); \
if (write_register(QSPI_CMD_WRCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & CONFIG2_BIT_DE) != 1 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define QUAD_ENABLE() \
/* TODO: add implementation */ \
return QSPI_STATUS_OK
\
uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
\
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[0] = reg_data[0] & ~(CONFIG2_BIT_QE); \
if (write_register(QSPI_CMD_WRCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
qspi.cmd.configure(MODE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8); \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & (CONFIG2_BIT_QE)) == 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define QUAD_DISABLE() \
/* TODO: add implementation */ \
return QSPI_STATUS_OK
#define FAST_MODE_ENABLE() \
/* TODO: add implementation */ \
return QSPI_STATUS_OK
\
uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
\
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[0] = reg_data[0] | (CONFIG2_BIT_QE); \
if (write_register(QSPI_CMD_WRCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & CONFIG2_BIT_QE) != 1 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#endif // MBED_QSPI_FLASH_N25Q128A_H

6
TESTS/mbed_hal/qspi/flash_configs/NORDIC/NRF52840_DK/flash_config.h
View File

@ -16,7 +16,7 @@
#ifndef MBED_QSPI_FLASH_CONFIG_H
#define MBED_QSPI_FLASH_CONFIG_H
#include "../../MX25R6435F_config.h"
#include "../../MX25RXX35F_config.h"
// NRF doesn't uses read/write opcodes, instead it uses commands id's.
// Before sending it to H/W opcodes are mapped to id's in Mbed hal qspi implementation
@ -29,5 +29,9 @@
#undef QSPI_CMD_READ_1IO
#define QSPI_CMD_READ_1IO QSPI_CMD_READ_1IO_FAST
#ifdef QSPI_SECTOR_COUNT
#undef QSPI_SECTOR_COUNT
#define QSPI_SECTOR_COUNT 2048 // for MX25R6435F
#endif
#endif // MBED_QSPI_FLASH_CONFIG_H

2
TESTS/mbed_hal/qspi/flash_configs/STM/DISCO_L475VG_IOT01A/flash_config.h
View File

@ -16,7 +16,7 @@
#ifndef MBED_QSPI_FLASH_CONFIG_H
#define MBED_QSPI_FLASH_CONFIG_H
#include "../../MX25R6435F_config.h"
#include "../../MX25RXX35F_config.h"
#endif // MBED_QSPI_FLASH_CONFIG_H

6
TESTS/mbed_hal/qspi/flash_configs/SiliconLabs/EFM32GG11_STK3701/flash_config.h
View File

@ -16,7 +16,11 @@
#ifndef MBED_QSPI_FLASH_CONFIG_H
#define MBED_QSPI_FLASH_CONFIG_H
#include "../../MX25R3235F_config.h"
#include "../../MX25RXX35F_config.h"
#ifdef QSPI_SECTOR_COUNT
#undef QSPI_SECTOR_COUNT
#define QSPI_SECTOR_COUNT 1024 // for MX25R3235F
#endif
#endif // MBED_QSPI_FLASH_CONFIG_H

266
TESTS/mbed_hal/qspi/main.cpp
View File

@ -52,7 +52,7 @@ uint8_t rx_buf[DATA_SIZE_1024];
#define TEST_FLASH_ADDRESS 0x0
#define TEST_REPEAT_SINGLE 1
#define TEST_REPEAT_MULTIPLE 16
#define TEST_REPEAT_MULTIPLE 4
// write block of data in single write operation
#define WRITE_SINGLE 1
@ -74,6 +74,13 @@ uint8_t rx_buf[DATA_SIZE_1024];
#define QCSN static_cast<PinName>(QSPI_FLASH1_CSN)
static uint32_t gen_flash_address()
{
srand(ticker_read(get_us_ticker_data()));
uint32_t address = (((uint32_t)rand()) % QSPI_SECTOR_COUNT) * QSPI_SECTOR_SIZE;
return address;
}
static void log_data(const char *str, uint8_t *data, uint32_t size)
{
utest_printf("%s: ", str);
@ -100,7 +107,6 @@ static void _qspi_write_read_test(Qspi &qspi, qspi_bus_width_t write_inst_width,
size_t buf_len = data_size;
for (uint32_t tc = 0; tc < test_count; tc++) {
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
srand(ticker_read(get_us_ticker_data()));
for (uint32_t i = 0; i < data_size; i++) {
@ -125,6 +131,11 @@ static void _qspi_write_read_test(Qspi &qspi, qspi_bus_width_t write_inst_width,
WAIT_FOR(WAIT_MAX_TIME, qspi);
}
// switching to extended-SPI/DPI/QPI mode here for write operation
// for DPI/QPI qspi.cmd is automatically switched to 2_2_2/4_4_4 mode
ret = mode_enable(qspi, write_inst_width, write_addr_width, write_data_width);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
const uint32_t write_size = data_size / write_count;
for (uint32_t wc = 0, write_start = flash_addr; wc < write_count; wc++, write_start += write_size) {
ret = write_enable(qspi);
@ -140,18 +151,32 @@ static void _qspi_write_read_test(Qspi &qspi, qspi_bus_width_t write_inst_width,
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
TEST_ASSERT_EQUAL(write_size, buf_len);
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
if(is_extended_mode(write_inst_width, write_addr_width, write_data_width)) {
// on some flash chips in extended-SPI mode, control commands works only in 1-1-1 mode
// so switching back to 1-1-1 mode
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
}
WAIT_FOR(PAGE_PROG_MAX_TIME, qspi);
timer.stop();
write_time = timer.read_us();
}
// switching back to single channel SPI
ret = mode_disable(qspi, write_inst_width, write_addr_width, write_data_width);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
if (read_frequency != QSPI_NONE) {
qspi_frequency(&qspi.handle, read_frequency);
WAIT_FOR(WAIT_MAX_TIME, qspi);
}
// switching to extended-SPI/DPI/QPI mode here for read operation
// for DPI/QPI qspi.cmd is automatically switched to 2_2_2/4_4_4 mode
ret = mode_enable(qspi, read_inst_width, read_addr_width, read_data_width);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
memset(rx_buf, 0, sizeof(rx_buf));
const uint32_t read_size = data_size / read_count;
qspi.cmd.configure(read_inst_width, read_addr_width, read_data_width, read_alt_width, read_addr_size, read_alt_size, read_dummy_cycles);
@ -168,6 +193,17 @@ static void _qspi_write_read_test(Qspi &qspi, qspi_bus_width_t write_inst_width,
timer.stop();
read_time = timer.read_us();
}
qspi.cmd.set_dummy_cycles(0);
if(is_extended_mode(read_inst_width, read_addr_width, read_data_width)) {
// on some flash chips in extended-SPI mode, control commands works only in 1-1-1 mode
// so switching back to 1-1-1 mode
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
}
// switching back to single channel SPI
ret = mode_disable(qspi, read_inst_width, read_addr_width, read_data_width);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
for (uint32_t i = 0; i < data_size; i++) {
if (tx_buf[i] != rx_buf[i]) {
@ -217,43 +253,29 @@ void qspi_write_read_test(void)
{
qspi_status_t ret;
Qspi qspi;
uint32_t addr = flash_addr;
if (addr == 0) {
// if no specified address selected, use random one to extend flash life
addr = gen_flash_address();
}
qspi_init(&qspi.handle, QPIN_0, QPIN_1, QPIN_2, QPIN_3, QSCK, QCSN, QSPI_COMMON_MAX_FREQUENCY, 0);
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
flash_init(qspi);
if (is_dual_cmd(write_inst_width, write_addr_width, write_data_width) ||
is_dual_cmd(read_inst_width, read_addr_width, read_data_width)) {
ret = dual_enable(qspi);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
WAIT_FOR(WRSR_MAX_TIME, qspi);
}
if (is_quad_cmd(write_inst_width, write_addr_width, write_data_width) ||
is_quad_cmd(read_inst_width, read_addr_width, read_data_width)) {
ret = quad_enable(qspi);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
WAIT_FOR(WRSR_MAX_TIME, qspi);
}
ret = write_enable(qspi);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
WAIT_FOR(WRSR_MAX_TIME, qspi);
// switch memory to high performance mode (if available)
ret = fast_mode_enable(qspi);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
WAIT_FOR(WRSR_MAX_TIME, qspi);
#ifdef QSPI_TEST_LOG_FLASH_STATUS
//utest_printf("Status register:\r\n");
log_register(STATUS_REG, QSPI_STATUS_REG_SIZE, qspi, "Status register");
//utest_printf("Config register 0:\r\n");
log_register(CONFIG_REG0, QSPI_CONFIG_REG_0_SIZE, qspi, "Config register 0");
#ifdef CONFIG_REG1
//utest_printf("Config register 1:\r\n");
log_register(CONFIG_REG1, QSPI_CONFIG_REG_1_SIZE, qspi, "Config register 1");
#endif
#ifdef CONFIG_REG2
//utest_printf("Config register 2:\r\n");
log_register(CONFIG_REG2, QSPI_CONFIG_REG_2_SIZE, qspi, "Config register 2");
#endif
#endif
@ -262,23 +284,10 @@ void qspi_write_read_test(void)
write_addr_size, write_alt_size, write_frequency, write_count, read_inst_width,
read_addr_width, read_data_width, read_alt_width, read_cmd, read_dummy_cycles,
read_addr_size, read_alt_size, read_frequency, read_count, test_count,
data_size, flash_addr);
data_size, addr);
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
if (is_dual_cmd(write_inst_width, write_addr_width, write_data_width) ||
is_dual_cmd(read_inst_width, read_addr_width, read_data_width)) {
ret = dual_disable(qspi);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
WAIT_FOR(WRSR_MAX_TIME, qspi);
}
if (is_quad_cmd(write_inst_width, write_addr_width, write_data_width) ||
is_quad_cmd(read_inst_width, read_addr_width, read_data_width)) {
ret = quad_disable(qspi);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
WAIT_FOR(WRSR_MAX_TIME, qspi);
}
ret = fast_mode_disable(qspi);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
qspi_free(&qspi.handle);
}
@ -315,16 +324,12 @@ void qspi_init_free_test(void)
flash_init(qspi);
#ifdef QSPI_TEST_LOG_FLASH_STATUS
//utest_printf("Status register:\r\n");
log_register(STATUS_REG, QSPI_STATUS_REG_SIZE, qspi, "Status register");
//utest_printf("Config register 0:\r\n");
log_register(CONFIG_REG0, QSPI_CONFIG_REG_0_SIZE, qspi, "Config register 0");
#ifdef CONFIG_REG1
//utest_printf("Config register 1:\r\n");
log_register(CONFIG_REG1, QSPI_CONFIG_REG_1_SIZE, qspi, "Config register 1");
#endif
#ifdef CONFIG_REG2
//utest_printf("Config register 2:\r\n");
log_register(CONFIG_REG2, QSPI_CONFIG_REG_2_SIZE, qspi, "Config register 2");
#endif
#endif
@ -338,37 +343,33 @@ void qspi_frequency_test(void)
{
Qspi qspi;
qspi_status_t ret;
int freq = QSPI_COMMON_MAX_FREQUENCY;
ret = qspi_init(&qspi.handle, QPIN_0, QPIN_1, QPIN_2, QPIN_3, QSCK, QCSN, QSPI_COMMON_MAX_FREQUENCY, 0);
ret = qspi_init(&qspi.handle, QPIN_0, QPIN_1, QPIN_2, QPIN_3, QSCK, QCSN, freq, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
// check if the memory is working properly
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
flash_init(qspi);
_qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS);
_qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, freq, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, freq, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS);
ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY / 2);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
freq /= 2;
// check if the memory is working properly
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
flash_init(qspi);
_qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS);
_qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, freq, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, freq, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS);
ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY / 4);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
freq /= 2;
// check if the memory is working properly
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
flash_init(qspi);
_qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS);
_qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, freq, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, freq, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS);
ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY / 8);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
freq /= 2;
// check if the memory is working properly
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
flash_init(qspi);
_qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS);
_qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, freq, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, freq, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS);
qspi_free(&qspi.handle);
}
@ -387,69 +388,184 @@ Case cases[] = {
// read/x1 write/x1 - read/write block of data in single write/read operation
// read/x4 write/x4 - read/write block of data in adjacent locations in multiple write/read operations
// repeat/xN - test repeat count (new data pattern each time)
// 1-1-1 - single channel SPI
// 1-1-2 - Dual data (extended SPI)
// 1-2-2 - Dual I/O (extended SPI)
// 1-1-4 - Quad data (extended SPI)
// 1-4-4 - Quad I/O (extended SPI)
// 2-2-2 - DPI (multi-channel SPI)
// 4-4-4 - QPI (multi-channel SPI)
Case("qspi write(1-1-1)/x1 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x4 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-1-1)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-1-1)/x1 repeat/x16 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-1-1)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x4 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-1-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-1-2)/x1 repeat/x16 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-1-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x4 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-2-2)/x1 repeat/x16 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_2_2_2
Case("qspi write(1-1-1)/x1 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x4 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(2-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(2-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
Case("qspi write(1-1-1)/x1 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x4 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-1-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-1-4)/x1 repeat/x16 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-1-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x4 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-4-4)/x1 repeat/x16 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef QSPI_CMD_WRITE_2IO
Case("qspi write(1-1-1)/x1 read(1-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_4_4_4
Case("qspi write(1-1-1)/x1 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x4 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(4-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(4-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#ifdef WRITE_1_2_2
Case("qspi write(1-2-2)/x1 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x4 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-1-1)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-1-1)/x1 repeat/x16 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-1-1)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x4 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-1-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-1-2)/x1 repeat/x16 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-1-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x4 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-2-2)/x1 repeat/x16 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_2_2_2
Case("qspi write(1-2-2)/x1 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x4 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(2-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(2-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
Case("qspi write(1-2-2)/x1 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x4 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-1-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-1-4)/x1 repeat/x16 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-1-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x4 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-4-4)/x1 repeat/x16 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_4_4_4
Case("qspi write(1-2-2)/x1 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x4 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(4-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(4-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#ifdef QSPI_CMD_WRITE_4IO
#endif
#ifdef WRITE_2_2_2
Case("qspi write(2-2-2)/x1 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x4 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-1-1)/x4 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-1-1)/x1 repeat/x4 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x4 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-1-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-1-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x4 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_2_2_2
Case("qspi write(2-2-2)/x1 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x4 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(2-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(2-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
Case("qspi write(2-2-2)/x1 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x4 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-1-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-1-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x4 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_4_4_4
Case("qspi write(2-2-2)/x1 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x4 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(4-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(4-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#endif
#ifdef WRITE_1_4_4
Case("qspi write(1-4-4)/x1 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x4 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-1-1)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-1-1)/x1 repeat/x16 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-1-1)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x4 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-1-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-1-2)/x1 repeat/x16 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-1-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x4 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-2-2)/x1 repeat/x16 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_2_2_2
Case("qspi write(1-4-4)/x1 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x4 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(2-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(2-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
Case("qspi write(1-4-4)/x1 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x4 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-1-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-1-4)/x1 repeat/x16 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-1-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x4 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-4-4)/x1 repeat/x16 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_4_4_4
Case("qspi write(1-4-4)/x1 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x4 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(4-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(4-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#endif
#ifdef WRITE_4_4_4
Case("qspi write(4-4-4)/x1 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x4 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-1-1)/x4 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-1-1)/x1 repeat/x4 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x4 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-1-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-1-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x4 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_2_2_2
Case("qspi write(4-4-4)/x1 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x4 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(2-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(2-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
Case("qspi write(4-4-4)/x1 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x4 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-1-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-1-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x4 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_4_4_4
Case("qspi write(4-4-4)/x1 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x4 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_MULTIPLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(4-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(4-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#endif
};

101
TESTS/mbed_hal/qspi/qspi_test_utils.cpp
View File

@ -26,6 +26,12 @@
#include "flash_configs/flash_configs.h"
#include "mbed.h"
static qspi_status_t extended_enable(Qspi &qspi);
static qspi_status_t extended_disable(Qspi &qspi);
static qspi_status_t dual_enable(Qspi &qspi);
static qspi_status_t dual_disable(Qspi &qspi);
static qspi_status_t quad_enable(Qspi &qspi);
static qspi_status_t quad_disable(Qspi &qspi);
void QspiCommand::configure(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width,
qspi_bus_width_t data_width, qspi_bus_width_t alt_width,
@ -44,6 +50,11 @@ void QspiCommand::configure(qspi_bus_width_t inst_width, qspi_bus_width_t addr_w
_cmd.dummy_count = dummy_cycles;
}
void QspiCommand::set_dummy_cycles(int dummy_cycles)
{
_cmd.dummy_count = dummy_cycles;
}
void QspiCommand::build(int instruction, int address, int alt)
{
_cmd.instruction.disabled = (instruction == QSPI_NONE);
@ -188,46 +199,116 @@ qspi_status_t erase(uint32_t erase_cmd, uint32_t flash_addr, Qspi &qspi)
return qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, NULL, 0);
}
qspi_status_t dual_enable(Qspi &qspi)
qspi_status_t mode_enable(Qspi &qspi, qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width)
{
if(is_extended_mode(inst_width, addr_width, data_width)) {
return extended_enable(qspi);
} else if(is_dual_mode(inst_width, addr_width, data_width)) {
return dual_enable(qspi);
} else if(is_quad_mode(inst_width, addr_width, data_width)) {
return quad_enable(qspi);
} else {
return QSPI_STATUS_OK;
}
}
qspi_status_t mode_disable(Qspi &qspi, qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width)
{
if(is_extended_mode(inst_width, addr_width, data_width)) {
return extended_disable(qspi);
} else if(is_dual_mode(inst_width, addr_width, data_width)) {
return dual_disable(qspi);
} else if(is_quad_mode(inst_width, addr_width, data_width)) {
return quad_disable(qspi);
} else {
return QSPI_STATUS_OK;
}
}
static qspi_status_t extended_enable(Qspi &qspi)
{
#ifdef EXTENDED_SPI_ENABLE
EXTENDED_SPI_ENABLE();
#else
return QSPI_STATUS_OK;
#endif
}
static qspi_status_t extended_disable(Qspi &qspi)
{
#ifdef EXTENDED_SPI_DISABLE
EXTENDED_SPI_DISABLE();
#else
return QSPI_STATUS_OK;
#endif
}
static qspi_status_t dual_enable(Qspi &qspi)
{
#ifdef DUAL_ENABLE
DUAL_ENABLE();
#else
QUAD_ENABLE();
return QSPI_STATUS_OK;
#endif
}
qspi_status_t dual_disable(Qspi &qspi)
static qspi_status_t dual_disable(Qspi &qspi)
{
#ifdef DUAL_DISABLE
DUAL_DISABLE();
#else
QUAD_DISABLE();
return QSPI_STATUS_OK;
#endif
}
qspi_status_t quad_enable(Qspi &qspi)
static qspi_status_t quad_enable(Qspi &qspi)
{
#ifdef QUAD_ENABLE
QUAD_ENABLE();
#else
return QSPI_STATUS_OK;
#endif
}
qspi_status_t quad_disable(Qspi &qspi)
static qspi_status_t quad_disable(Qspi &qspi)
{
#ifdef QUAD_DISABLE
QUAD_DISABLE();
#else
return QSPI_STATUS_OK;
#endif
}
qspi_status_t fast_mode_enable(Qspi &qspi)
{
#ifdef FAST_MODE_ENABLE
FAST_MODE_ENABLE();
#else
return QSPI_STATUS_OK;
#endif
}
bool is_dual_cmd(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width)
qspi_status_t fast_mode_disable(Qspi &qspi)
{
return (inst_width == QSPI_CFG_BUS_DUAL) || (addr_width == QSPI_CFG_BUS_DUAL) || (data_width == QSPI_CFG_BUS_DUAL);
#ifdef FAST_MODE_DISABLE
FAST_MODE_DISABLE();
#else
return QSPI_STATUS_OK;
#endif
}
bool is_quad_cmd(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width)
bool is_extended_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width)
{
return (inst_width == QSPI_CFG_BUS_QUAD) || (addr_width == QSPI_CFG_BUS_QUAD) || (data_width == QSPI_CFG_BUS_QUAD);
return (inst_width == QSPI_CFG_BUS_SINGLE) && ((addr_width != QSPI_CFG_BUS_SINGLE) || (data_width != QSPI_CFG_BUS_SINGLE));
}
bool is_dual_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width)
{
return (inst_width == QSPI_CFG_BUS_DUAL) && (addr_width == QSPI_CFG_BUS_DUAL) && (data_width == QSPI_CFG_BUS_DUAL);
}
bool is_quad_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width)
{
return (inst_width == QSPI_CFG_BUS_QUAD) && (addr_width == QSPI_CFG_BUS_QUAD) && (data_width == QSPI_CFG_BUS_QUAD);
}

36
TESTS/mbed_hal/qspi/qspi_test_utils.h
View File

@ -34,6 +34,8 @@ public:
qspi_bus_width_t alt_width, qspi_address_size_t addr_size, qspi_alt_size_t alt_size,
int dummy_cycles = 0);
void set_dummy_cycles(int dummy_cycles);
void build(int instruction, int address = QSPI_NONE, int alt = QSPI_NONE);
qspi_command_t *get();
@ -51,8 +53,10 @@ struct Qspi {
#define MODE_1_1_1 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE
#define MODE_1_1_2 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL
#define MODE_1_2_2 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL
#define MODE_1_1_4 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_SINGLE
#define MODE_2_2_2 QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL
#define MODE_1_1_4 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD
#define MODE_1_4_4 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD
#define MODE_4_4_4 QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD
#define WRITE_1_1_1 MODE_1_1_1, QSPI_CMD_WRITE_1IO
#ifdef QSPI_CMD_WRITE_2IO
@ -61,6 +65,12 @@ struct Qspi {
#ifdef QSPI_CMD_WRITE_4IO
#define WRITE_1_4_4 MODE_1_4_4, QSPI_CMD_WRITE_4IO
#endif
#ifdef QSPI_CMD_WRITE_DPI
#define WRITE_2_2_2 MODE_2_2_2, QSPI_CMD_WRITE_DPI
#endif
#ifdef QSPI_CMD_WRITE_QPI
#define WRITE_4_4_4 MODE_4_4_4, QSPI_CMD_WRITE_QPI
#endif
#define READ_1_1_1 MODE_1_1_1, QSPI_CMD_READ_1IO, QSPI_READ_1IO_DUMMY_CYCLE
@ -68,7 +78,12 @@ struct Qspi {
#define READ_1_2_2 MODE_1_2_2, QSPI_CMD_READ_2IO, QSPI_READ_2IO_DUMMY_CYCLE
#define READ_1_1_4 MODE_1_1_4, QSPI_CMD_READ_1I4O, QSPI_READ_1I4O_DUMMY_CYCLE
#define READ_1_4_4 MODE_1_4_4, QSPI_CMD_READ_4IO, QSPI_READ_4IO_DUMMY_CYCLE
#ifdef QSPI_CMD_READ_DPI
#define READ_2_2_2 MODE_2_2_2, QSPI_CMD_READ_DPI, QSPI_READ_2IO_DUMMY_CYCLE
#endif
#ifdef QSPI_CMD_READ_QPI
#define READ_4_4_4 MODE_4_4_4, QSPI_CMD_READ_QPI, QSPI_READ_4IO_DUMMY_CYCLE
#endif
#define ADDR_SIZE_8 QSPI_CFG_ADDR_SIZE_8
#define ADDR_SIZE_16 QSPI_CFG_ADDR_SIZE_16
@ -120,26 +135,21 @@ QspiStatus flash_wait_for(uint32_t time_us, Qspi &qspi);
void flash_init(Qspi &qspi);
qspi_status_t write_enable(Qspi &qspi);
qspi_status_t write_disable(Qspi &qspi);
void log_register(uint32_t cmd, uint32_t reg_size, Qspi &qspi, const char *str = NULL);
qspi_status_t dual_enable(Qspi &qspi);
qspi_status_t dual_disable(Qspi &qspi);
qspi_status_t quad_enable(Qspi &qspi);
qspi_status_t quad_disable(Qspi &qspi);
qspi_status_t mode_enable(Qspi &qspi, qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
qspi_status_t mode_disable(Qspi &qspi, qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
qspi_status_t fast_mode_enable(Qspi &qspi);
qspi_status_t fast_mode_disable(Qspi &qspi);
qspi_status_t erase(uint32_t erase_cmd, uint32_t flash_addr, Qspi &qspi);
bool is_dual_cmd(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
bool is_quad_cmd(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
bool is_extended_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
bool is_dual_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
bool is_quad_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
#define WAIT_FOR(timeout, q) TEST_ASSERT_EQUAL_MESSAGE(sOK, flash_wait_for(timeout, q), "flash_wait_for failed!!!")

10
targets/TARGET_NORDIC/TARGET_NRF5x/qspi_api.c
View File

@ -281,7 +281,7 @@ qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command,
ret_code_t ret_code;
uint8_t data[8];
uint32_t data_size = tx_size + rx_size;
nrf_qspi_cinstr_conf_t qspi_cinstr_config;
qspi_cinstr_config.opcode = command->instruction.value;
qspi_cinstr_config.io2_level = true;
@ -298,8 +298,10 @@ qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command,
} else {
return QSPI_STATUS_INVALID_PARAMETER;
}
for (uint32_t i = 0; i < (uint32_t)qspi_cinstr_config.length - 1; ++i) {
data[i] = ((uint8_t *)&command->address.value)[i];
uint32_t address_size = (uint32_t)qspi_cinstr_config.length - 1;
uint8_t *address_bytes = (uint8_t *)&command->address.value;
for (uint32_t i = 0; i < address_size; ++i) {
data[i] = address_bytes[address_size - 1 - i];
}
} else if (data_size < 9) {
qspi_cinstr_config.length = (nrf_qspi_cinstr_len_t)(NRF_QSPI_CINSTR_LEN_1B + data_size);
@ -321,7 +323,7 @@ qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command,
// Data is sending as a normal SPI transmission so there is one buffer to send and receive data.
((uint8_t *)rx_data)[i] = data[i];
}
return QSPI_STATUS_OK;
}