mirror of https://github.com/ARMmbed/mbed-os.git
Add NUC472 support for USBH
ccli8
parent
f5fb485dcd
commit
69f4a200c0
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@ -72,7 +72,10 @@ enum ENDPOINT_TYPE {
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#define OR_CONTROL_CLE 0x00000010
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#define OR_CONTROL_BLE 0x00000020
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#define OR_CONTROL_HCFS 0x000000C0
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#define OR_CONTROL_HC_RSET 0x00000000
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#define OR_CONTROL_HC_RES 0x00000040
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#define OR_CONTROL_HC_OPER 0x00000080
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#define OR_CONTROL_HC_SUSP 0x000000C0
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// ----------------- HcCommandStatus Register -----------------
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#define OR_CMD_STATUS_HCR 0x00000001
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#define OR_CMD_STATUS_CLF 0x00000002
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@ -0,0 +1,361 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2015-2016 Nuvoton
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#if defined(TARGET_NUC472)
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#include "mbed.h"
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#include "USBHALHost.h"
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#include "dbg.h"
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#include "pinmap.h"
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#define HCCA_SIZE sizeof(HCCA)
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#define ED_SIZE sizeof(HCED)
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#define TD_SIZE sizeof(HCTD)
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#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
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static volatile MBED_ALIGN(256) uint8_t usb_buf[TOTAL_SIZE]; // 256 bytes aligned!
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USBHALHost * USBHALHost::instHost;
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USBHALHost::USBHALHost()
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{
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instHost = this;
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memInit();
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memset((void*)usb_hcca, 0, HCCA_SIZE);
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for (int i = 0; i < MAX_ENDPOINT; i++) {
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edBufAlloc[i] = false;
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}
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for (int i = 0; i < MAX_TD; i++) {
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tdBufAlloc[i] = false;
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}
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}
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void USBHALHost::init()
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{
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// Unlock protected registers
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SYS_UnlockReg();
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// NOTE: Configure as OTG device first; otherwise, program will trap in wait loop CLK_STATUS_PLL2STB_Msk below.
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SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk | SYS_USBPHY_USBROLE_ON_THE_GO;
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// NOTE: Enable OTG here; otherwise, program will trap in wait loop CLK_STATUS_PLL2STB_Msk below.
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CLK_EnableModuleClock(OTG_MODULE);
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OTG->PHYCTL = (OTG->PHYCTL | OTG_PHYCTL_OTGPHYEN_Msk) & ~OTG_PHYCTL_IDDETEN_Msk;
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//OTG->CTL |= OTG_CTL_OTGEN_Msk | OTG_CTL_BUSREQ_Msk;
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// PB.0: USB0 external VBUS regulator status
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// USB_OC
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// PB.1: USB0 external VBUS regulator enable
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// NCT3520U low active (USB_PWR_EN)
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pin_function(PB_0, SYS_GPB_MFPL_PB0MFP_USB0_OTG5V_ST);
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pin_function(PB_1, SYS_GPB_MFPL_PB1MFP_USB0_OTG5V_EN);
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// PB.2: USB1 differential signal D-
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// PB.3: USB1 differential signal D+
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//pin_function(PB_2, SYS_GPB_MFPL_PB2MFP_USB1_D_N);
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//pin_function(PB_3, SYS_GPB_MFPL_PB3MFP_USB1_D_P);
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// Set PB.4 output high to enable USB power
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//gpio_t gpio;
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//gpio_init_out_ex(&gpio, PB_4, 1);
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// NOTE:
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// 1. Set USBH clock source to PLL2; otherwise, program will trap in wait loop CLK_STATUS_PLL2STB_Msk below.
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// 2. Don't set CLK_PLL2CTL_PLL2CKEN_Msk. USBH will work abnormally with it enabled.
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CLK->CLKSEL0 &= ~CLK_CLKSEL0_USBHSEL_Msk;
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// Enable PLL2, 480 MHz / 2 / (1+4) => 48 MHz output
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CLK->PLL2CTL = /*CLK_PLL2CTL_PLL2CKEN_Msk | */ (4 << CLK_PLL2CTL_PLL2DIV_Pos);
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// Wait PLL2 stable ...
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while (!(CLK->STATUS & CLK_STATUS_PLL2STB_Msk));
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// Select USB Host clock source from PLL2, clock divied by 1
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CLK_SetModuleClock(USBH_MODULE, CLK_CLKSEL0_USBHSEL_PLL2, CLK_CLKDIV0_USB(1));
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// Enable USB Host clock
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CLK_EnableModuleClock(USBH_MODULE);
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// Lock protected registers
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SYS_LockReg();
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// Overcurrent flag is high active
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USBH->HcMiscControl &= ~USBH_HcMiscControl_OCAL_Msk;
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// Disable HC interrupts
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USBH->HcInterruptDisable = OR_INTR_ENABLE_MIE;
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// Needed by some controllers
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USBH->HcControl = 0;
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// Software reset
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USBH->HcCommandStatus = OR_CMD_STATUS_HCR;
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while (USBH->HcCommandStatus & OR_CMD_STATUS_HCR);
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// Put HC in reset state
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USBH->HcControl = (USBH->HcControl & ~OR_CONTROL_HCFS) | OR_CONTROL_HC_RSET;
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// HCD must wait 10ms for HC reset complete
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wait_ms(100);
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USBH->HcControlHeadED = 0; // Initialize Control ED list head to 0
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USBH->HcBulkHeadED = 0; // Initialize Bulk ED list head to 0
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USBH->HcHCCA = (uint32_t) usb_hcca;
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USBH->HcFmInterval = DEFAULT_FMINTERVAL; // Frame interval = 12000 - 1
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// MPS = 10,104
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USBH->HcPeriodicStart = FI * 90 / 100; // 90% of frame interval
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USBH->HcLSThreshold = 0x628; // Low speed threshold
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// Put HC in operational state
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USBH->HcControl = (USBH->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
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// FIXME: Ports are power switched. All ports are powered at the same time. Doesn't match BSP sample.
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USBH->HcRhDescriptorA = USBH->HcRhDescriptorA & ~USBH_HcRhDescriptorA_NPS_Msk & ~USBH_HcRhDescriptorA_PSM_Msk;
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// Issue SetGlobalPower command
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USBH->HcRhStatus = USBH_HcRhStatus_LPSC_Msk;
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// Power On To Power Good Time, in 2 ms units
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wait_ms(((USBH->HcRhDescriptorA & USBH_HcRhDescriptorA_POTPGT_Msk) >> USBH_HcRhDescriptorA_POTPGT_Pos) * 2);
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// Clear Interrrupt Status
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USBH->HcInterruptStatus |= USBH->HcInterruptStatus;
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// Enable interrupts we care about
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USBH->HcInterruptEnable = OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC;
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// Unlock protected registers
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SYS_UnlockReg();
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// NOTE: Configure as USB host after USBH init above; otherwise system will crash.
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SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) | SYS_USBPHY_USBROLE_STD_USBH;
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// Lock protected registers
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SYS_LockReg();
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NVIC_SetVector(USBH_IRQn, (uint32_t)(_usbisr));
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NVIC_EnableIRQ(USBH_IRQn);
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// Check for any connected devices
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if (USBH->HcRhPortStatus[0] & OR_RH_PORT_CCS) {
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// Device connected
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wait_ms(150);
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deviceConnected(0, 1, USBH->HcRhPortStatus[0] & OR_RH_PORT_LSDA);
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}
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}
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uint32_t USBHALHost::controlHeadED()
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{
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return USBH->HcControlHeadED;
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}
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uint32_t USBHALHost::bulkHeadED()
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{
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return USBH->HcBulkHeadED;
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}
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uint32_t USBHALHost::interruptHeadED()
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{
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// FIXME: Only support one INT ED?
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return usb_hcca->IntTable[0];
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}
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void USBHALHost::updateBulkHeadED(uint32_t addr)
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{
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USBH->HcBulkHeadED = addr;
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}
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void USBHALHost::updateControlHeadED(uint32_t addr)
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{
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USBH->HcControlHeadED = addr;
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}
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void USBHALHost::updateInterruptHeadED(uint32_t addr)
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{
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// FIXME: Only support one INT ED?
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usb_hcca->IntTable[0] = addr;
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}
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void USBHALHost::enableList(ENDPOINT_TYPE type)
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{
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switch(type) {
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case CONTROL_ENDPOINT:
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USBH->HcCommandStatus = OR_CMD_STATUS_CLF;
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USBH->HcControl |= OR_CONTROL_CLE;
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break;
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case ISOCHRONOUS_ENDPOINT:
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// FIXME
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break;
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case BULK_ENDPOINT:
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USBH->HcCommandStatus = OR_CMD_STATUS_BLF;
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USBH->HcControl |= OR_CONTROL_BLE;
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break;
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case INTERRUPT_ENDPOINT:
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USBH->HcControl |= OR_CONTROL_PLE;
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break;
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}
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}
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bool USBHALHost::disableList(ENDPOINT_TYPE type)
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{
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switch(type) {
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case CONTROL_ENDPOINT:
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if(USBH->HcControl & OR_CONTROL_CLE) {
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USBH->HcControl &= ~OR_CONTROL_CLE;
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return true;
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}
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return false;
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case ISOCHRONOUS_ENDPOINT:
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// FIXME
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return false;
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case BULK_ENDPOINT:
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if(USBH->HcControl & OR_CONTROL_BLE){
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USBH->HcControl &= ~OR_CONTROL_BLE;
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return true;
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}
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return false;
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case INTERRUPT_ENDPOINT:
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if(USBH->HcControl & OR_CONTROL_PLE) {
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USBH->HcControl &= ~OR_CONTROL_PLE;
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return true;
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}
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return false;
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}
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return false;
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}
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void USBHALHost::memInit()
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{
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usb_hcca = (volatile HCCA *)usb_buf;
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usb_edBuf = usb_buf + HCCA_SIZE;
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usb_tdBuf = usb_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE);
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}
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volatile uint8_t * USBHALHost::getED()
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{
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for (int i = 0; i < MAX_ENDPOINT; i++) {
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if ( !edBufAlloc[i] ) {
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edBufAlloc[i] = true;
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return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
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}
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}
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perror("Could not allocate ED\r\n");
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return NULL; //Could not alloc ED
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}
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volatile uint8_t * USBHALHost::getTD()
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{
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int i;
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for (i = 0; i < MAX_TD; i++) {
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if ( !tdBufAlloc[i] ) {
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tdBufAlloc[i] = true;
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return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
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}
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}
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perror("Could not allocate TD\r\n");
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return NULL; //Could not alloc TD
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}
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void USBHALHost::freeED(volatile uint8_t * ed)
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{
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int i;
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i = (ed - usb_edBuf) / ED_SIZE;
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edBufAlloc[i] = false;
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}
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void USBHALHost::freeTD(volatile uint8_t * td)
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{
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int i;
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i = (td - usb_tdBuf) / TD_SIZE;
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tdBufAlloc[i] = false;
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}
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void USBHALHost::resetRootHub()
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{
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// Reset port1
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USBH->HcRhPortStatus[0] = OR_RH_PORT_PRS;
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while (USBH->HcRhPortStatus[0] & OR_RH_PORT_PRS);
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USBH->HcRhPortStatus[0] = OR_RH_PORT_PRSC;
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}
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void USBHALHost::_usbisr(void)
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{
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if (instHost) {
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instHost->UsbIrqhandler();
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}
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}
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void USBHALHost::UsbIrqhandler()
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{
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uint32_t ints = USBH->HcInterruptStatus;
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// Root hub status change interrupt
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if (ints & OR_INTR_STATUS_RHSC) {
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uint32_t ints_roothub = USBH->HcRhStatus;
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uint32_t ints_port1 = USBH->HcRhPortStatus[0];
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if (ints_port1 & OR_RH_PORT_CSC) {
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if (ints_roothub & OR_RH_STATUS_DRWE) {
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// When DRWE is on, Connect Status Change means a remote wakeup event.
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} else {
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if (ints_port1 & OR_RH_PORT_CCS) {
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// Root device connected
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// wait 150ms to avoid bounce
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wait_ms(150);
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//Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
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deviceConnected(0, 1, ints_port1 & OR_RH_PORT_LSDA);
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} else {
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// Root device disconnected
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if (!(ints & OR_INTR_STATUS_WDH)) {
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usb_hcca->DoneHead = 0;
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}
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// wait 200ms to avoid bounce
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wait_ms(200);
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deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
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if (ints & OR_INTR_STATUS_WDH) {
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usb_hcca->DoneHead = 0;
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USBH->HcInterruptStatus = OR_INTR_STATUS_WDH;
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}
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}
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}
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USBH->HcRhPortStatus[0] = OR_RH_PORT_CSC;
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}
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// Reset completed
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if (ints_port1 & OR_RH_PORT_PRSC) {
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USBH->HcRhPortStatus[0] = OR_RH_PORT_PRSC;
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}
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USBH->HcInterruptStatus = OR_INTR_STATUS_RHSC;
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}
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// Writeback Done Head interrupt
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if (ints & OR_INTR_STATUS_WDH) {
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transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
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USBH->HcInterruptStatus = OR_INTR_STATUS_WDH;
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}
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}
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#endif
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@ -92,8 +92,8 @@ extern "C"
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#define CLK_CLKSEL0_PCLKSEL_HCLK (0x00UL<<CLK_CLKSEL0_PCLKSEL_Pos) /*!< Setting clock source as HCLK \hideinitializer */
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#define CLK_CLKSEL0_PCLKSEL_HCLK_DIV2 (0x01UL<<CLK_CLKSEL0_PCLKSEL_Pos) /*!< Setting clock source as HCLK/2 \hideinitializer */
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#define CLK_CLKSEL0_USBHSEL_PLL (0x00UL<<CLK_CLKSEL0_USBH_Pos) /*!< Setting clock source as PLL \hideinitializer */
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#define CLK_CLKSEL0_USBHSEL_PLL2 (0x01UL<<CLK_CLKSEL0_USBH_Pos) /*!< Setting clock source as PLL2 \hideinitializer */
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#define CLK_CLKSEL0_USBHSEL_PLL2 (0x00UL<<CLK_CLKSEL0_USBHSEL_Pos) /*!< Setting clock source as PLL2 \hideinitializer */
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#define CLK_CLKSEL0_USBHSEL_PLL (0x01UL<<CLK_CLKSEL0_USBHSEL_Pos) /*!< Setting clock source as PLL \hideinitializer */
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#define CLK_CLKSEL0_EMACSEL_PLL (0x01UL<<10) /*!< Setting clock source as PLL \hideinitializer */
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