mirror of https://github.com/ARMmbed/mbed-os.git
NUC472 support EMAC bus reset as while bus error
cyliangtw
parent
16dacb73c0
commit
68e9f4a8ed
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@ -16,30 +16,38 @@
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*
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* Description: NUC472 MAC driver source file
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*/
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#include <stdbool.h>
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#include "nuc472_eth.h"
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#include "mbed_toolchain.h"
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//#define NU_TRACE
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#include "numaker_eth_hal.h"
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#define ETH_TRIGGER_RX() do{EMAC->RXST = 0;}while(0)
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#define ETH_TRIGGER_TX() do{EMAC->TXST = 0;}while(0)
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#define ETH_ENABLE_TX() do{EMAC->CTL |= EMAC_CTL_TXON;}while(0)
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#define ETH_ENABLE_RX() do{EMAC->CTL |= EMAC_CTL_RXON;}while(0)
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#define ETH_ENABLE_RX() do{EMAC->CTL |= EMAC_CTL_RXON_Msk;}while(0)
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#define ETH_DISABLE_TX() do{EMAC->CTL &= ~EMAC_CTL_TXON;}while(0)
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#define ETH_DISABLE_RX() do{EMAC->CTL &= ~EMAC_CTL_RXON;}while(0)
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#define ETH_DISABLE_RX() do{EMAC->CTL &= ~EMAC_CTL_RXON_Msk;}while(0)
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#define EMAC_ENABLE_INT(emac, u32eIntSel) ((emac)->INTEN |= (u32eIntSel))
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#define EMAC_DISABLE_INT(emac, u32eIntSel) ((emac)->INTEN &= ~ (u32eIntSel))
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MBED_ALIGN(4) struct eth_descriptor rx_desc[RX_DESCRIPTOR_NUM];
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MBED_ALIGN(4) struct eth_descriptor tx_desc[TX_DESCRIPTOR_NUM];
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struct eth_descriptor volatile *cur_tx_desc_ptr, *cur_rx_desc_ptr, *fin_tx_desc_ptr;
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__attribute__ ((section("EMAC_RAM")))
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MBED_ALIGN(4) uint8_t rx_buf[RX_DESCRIPTOR_NUM][PACKET_BUFFER_SIZE];
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__attribute__ ((section("EMAC_RAM")))
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MBED_ALIGN(4) uint8_t tx_buf[TX_DESCRIPTOR_NUM][PACKET_BUFFER_SIZE];
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eth_callback_t nu_eth_txrx_cb = NULL;
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void *nu_userData = NULL;
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extern void ack_emac_rx_isr(void);
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static bool isPhyReset = false;
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static uint16_t phyLPAval = 0;
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// PTP source clock is 84MHz (Real chip using PLL). Each tick is 11.90ns
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// Assume we want to set each tick to 100ns.
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@ -113,6 +121,7 @@ static int reset_phy(void)
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return(-1);
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} else {
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reg = mdio_read(CONFIG_PHY_ADDR, MII_LPA);
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phyLPAval = reg;
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if(reg & ADVERTISE_100FULL) {
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NU_DEBUGF(("100 full\n"));
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@ -164,7 +173,7 @@ static void init_rx_desc(void)
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rx_desc[i].status1 = OWNERSHIP_EMAC;
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rx_desc[i].buf = &rx_buf[i][0];
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rx_desc[i].status2 = 0;
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rx_desc[i].next = &rx_desc[(i + 1) % TX_DESCRIPTOR_NUM];
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rx_desc[i].next = &rx_desc[(i + 1) % (RX_DESCRIPTOR_NUM)];
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}
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EMAC->RXDSA = (unsigned int)&rx_desc[0];
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return;
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@ -188,10 +197,14 @@ void numaker_set_mac_addr(uint8_t *addr)
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static void __eth_clk_pin_init()
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{
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/* Unlock protected registers */
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SYS_UnlockReg();
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/* Enable IP clock */
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CLK_EnableModuleClock(EMAC_MODULE);
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// Configure MDC clock rate to HCLK / (127 + 1) = 656 kHz if system is running at 84 MHz
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CLK_SetModuleClock(EMAC_MODULE, 0, CLK_CLKDIV3_EMAC(127));
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/* Update System Core Clock */
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SystemCoreClockUpdate();
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/*---------------------------------------------------------------------------------------------------------*/
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/* Init I/O Multi-function */
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/*---------------------------------------------------------------------------------------------------------*/
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@ -216,6 +229,8 @@ static void __eth_clk_pin_init()
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SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB14MFP_Msk | SYS_GPB_MFPH_PB15MFP_Msk);
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SYS->GPB_MFPH |= SYS_GPB_MFPH_PB14MFP_EMAC_MII_MDC | SYS_GPB_MFPH_PB15MFP_EMAC_MII_MDIO;
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/* Lock protected registers */
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SYS_LockReg();
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}
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void numaker_eth_init(uint8_t *mac_addr)
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@ -225,15 +240,13 @@ void numaker_eth_init(uint8_t *mac_addr)
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// Reset MAC
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EMAC->CTL = EMAC_CTL_RST_Msk;
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while(EMAC->CTL & EMAC_CTL_RST_Msk) {}
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init_tx_desc();
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init_rx_desc();
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numaker_set_mac_addr(mac_addr); // need to reconfigure hardware address 'cos we just RESET emc...
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/* Limit the max receive frame length to 1514 + 4 */
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EMAC->MRFL = NU_ETH_MAX_FLEN;
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reset_phy();
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EMAC->CTL |= EMAC_CTL_STRIPCRC_Msk | EMAC_CTL_RXON_Msk | EMAC_CTL_TXON_Msk | EMAC_CTL_RMIIEN_Msk | EMAC_CTL_RMIIRXCTL_Msk;
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EMAC->INTEN |= EMAC_INTEN_RXIEN_Msk |
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@ -244,7 +257,36 @@ void numaker_eth_init(uint8_t *mac_addr)
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EMAC_INTEN_TXABTIEN_Msk |
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EMAC_INTEN_TXCPIEN_Msk |
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EMAC_INTEN_TXBEIEN_Msk;
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EMAC->RXST = 0; // trigger Rx
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/* Limit the max receive frame length to 1514 + 4 */
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EMAC->MRFL = NU_ETH_MAX_FLEN;
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/* Set RX FIFO threshold as 8 words */
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if (isPhyReset != true)
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{
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if (!reset_phy())
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{
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isPhyReset = true;
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}
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} else {
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if (phyLPAval & ADVERTISE_100FULL) {
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NU_DEBUGF(("100 full\n"));
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EMAC->CTL |= (EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
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} else if (phyLPAval & ADVERTISE_100HALF) {
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NU_DEBUGF(("100 half\n"));
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EMAC->CTL = (EMAC->CTL & ~EMAC_CTL_FUDUP_Msk) | EMAC_CTL_OPMODE_Msk;
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} else if (phyLPAval & ADVERTISE_10FULL) {
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NU_DEBUGF(("10 full\n"));
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EMAC->CTL = (EMAC->CTL & ~EMAC_CTL_OPMODE_Msk) | EMAC_CTL_FUDUP_Msk;
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} else {
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NU_DEBUGF(("10 half\n"));
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EMAC->CTL &= ~(EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
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}
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}
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EMAC_ENABLE_RX();
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EMAC_ENABLE_TX();
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}
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@ -259,20 +301,22 @@ unsigned int m_status;
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void EMAC_RX_IRQHandler(void)
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{
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// NU_DEBUGF(("%s ... nu_eth_txrx_cb=0x%x\r\n", __FUNCTION__, nu_eth_txrx_cb));
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m_status = EMAC->INTSTS & 0xFFFF;
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EMAC->INTSTS = m_status;
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if (m_status & EMAC_INTSTS_RXBEIF_Msk) {
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// Shouldn't goes here, unless descriptor corrupted
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NU_DEBUGF(("RX descriptor corrupted \r\n"));
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//return;
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mbed_error_printf("### RX Bus error [0x%x]\r\n", m_status);
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if (nu_eth_txrx_cb != NULL) nu_eth_txrx_cb('B', nu_userData);
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return;
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}
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EMAC_DISABLE_INT(EMAC, (EMAC_INTEN_RDUIEN_Msk | EMAC_INTEN_RXGDIEN_Msk));
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if (nu_eth_txrx_cb != NULL) nu_eth_txrx_cb('R', nu_userData);
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}
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void numaker_eth_trigger_rx(void)
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{
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EMAC_ENABLE_INT(EMAC, (EMAC_INTEN_RDUIEN_Msk | EMAC_INTEN_RXGDIEN_Msk));
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ETH_TRIGGER_RX();
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}
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@ -291,6 +335,12 @@ int numaker_eth_get_rx_buf(uint16_t *len, uint8_t **buf)
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if (status & RXFD_RXGD) {
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*buf = cur_rx_desc_ptr->buf;
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*len = status & 0xFFFF;
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// length of payload should be <= 1514
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if ( *len > (NU_ETH_MAX_FLEN - 4) ) {
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NU_DEBUGF(("%s... unexpected long packet length=%d, buf=0x%x\r\n", __FUNCTION__, *len, *buf));
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*len = 0; // Skip this unexpected long packet
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}
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if (*len == (NU_ETH_MAX_FLEN - 4)) NU_DEBUGF(("%s... length=%d, buf=0x%x\r\n", __FUNCTION__, *len, *buf));
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}
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return 0;
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}
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@ -309,6 +359,8 @@ void EMAC_TX_IRQHandler(void)
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EMAC->INTSTS = status;
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if(status & EMAC_INTSTS_TXBEIF_Msk) {
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// Shouldn't goes here, unless descriptor corrupted
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mbed_error_printf("### TX Bus error [0x%x]\r\n", status);
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if (nu_eth_txrx_cb != NULL) nu_eth_txrx_cb('B', nu_userData);
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return;
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}
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