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Merge pull request #3843 from bcostm/fix_stm32l4_apb2_80MHz 

STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz)
pull/3294/merge
Martin Kojtal 2017-03-09 15:44:08 +00:00 committed by GitHub
parent c3e7b5434c ae6899b448
commit 68dc25331a
2 changed files with 2 additions and 2 deletions
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2
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_stm32l4xx.c
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@ -569,7 +569,7 @@ uint8_t SetSysClock_PLL_MSI(void)
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; /* 40 MHz */
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
{
return 0; // FAIL

2
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_stm32l4xx.c
View File

@ -569,7 +569,7 @@ uint8_t SetSysClock_PLL_MSI(void)
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; /* 40 MHz */
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
{
return 0; // FAIL