diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/LPC82x.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/LPC82x.h
new file mode 100644
index 0000000000..fee91c063a
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/LPC82x.h
@@ -0,0 +1,1308 @@
+
+/****************************************************************************************************//**
+ * @file LPC82x.h
+ *
+ * @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for
+ * LPC82x from .
+ *
+ * @version V0.4
+ * @date 17. June 2014
+ *
+ * @note Generated with SVDConv V2.80
+ * from CMSIS SVD File 'LPC82x.svd' Version 0.4,
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup (null)
+ * @{
+ */
+
+/** @addtogroup LPC82x
+ * @{
+ */
+
+#ifndef LPC82X_H
+#define LPC82X_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum {
+/* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+/* ---------------------- LPC82x Specific Interrupt Numbers --------------------- */
+ SPI0_IRQn = 0, /*!< 0 SPI0 */
+ SPI1_IRQn = 1, /*!< 1 SPI1 */
+ UART0_IRQn = 3, /*!< 3 UART0 */
+ UART1_IRQn = 4, /*!< 4 UART1 */
+ UART2_IRQn = 5, /*!< 5 UART2 */
+ I2C1_IRQn = 7, /*!< 7 I2C1 */
+ I2C0_IRQn = 8, /*!< 8 I2C0 */
+ SCT_IRQn = 9, /*!< 9 SCT */
+ MRT_IRQn = 10, /*!< 10 MRT */
+ CMP_IRQn = 11, /*!< 11 CMP */
+ WDT_IRQn = 12, /*!< 12 WDT */
+ BOD_IRQn = 13, /*!< 13 BOD */
+ FLASH_IRQn = 14, /*!< 14 FLASH */
+ WKT_IRQn = 15, /*!< 15 WKT */
+ ADC_SEQA_IRQn = 16, /*!< 16 ADC_SEQA */
+ ADC_SEQB_IRQn = 17, /*!< 17 ADC_SEQB */
+ ADC_THCMP_IRQn = 18, /*!< 18 ADC_THCMP */
+ ADC_OVR_IRQn = 19, /*!< 19 ADC_OVR */
+ DMA_IRQn = 20, /*!< 20 DMA */
+ I2C2_IRQn = 21, /*!< 21 I2C2 */
+ I2C3_IRQn = 22, /*!< 22 I2C3 */
+ PIN_INT0_IRQn = 24, /*!< 24 PIN_INT0 */
+ PIN_INT1_IRQn = 25, /*!< 25 PIN_INT1 */
+ PIN_INT2_IRQn = 26, /*!< 26 PIN_INT2 */
+ PIN_INT3_IRQn = 27, /*!< 27 PIN_INT3 */
+ PIN_INT4_IRQn = 28, /*!< 28 PIN_INT4 */
+ PIN_INT5_IRQn = 29, /*!< 29 PIN_INT5 */
+ PIN_INT6_IRQn = 30, /*!< 30 PIN_INT6 */
+ PIN_INT7_IRQn = 31 /*!< 31 PIN_INT7 */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */
+#define __CM0PLUS_REV 0x0001 /*!< Cortex-M0PLUS Core Revision */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm0plus.h" /*!< Cortex-M0PLUS processor and core peripherals */
+#include "system_LPC82x.h" /*!< LPC82x System */
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+/* ------------------- Start of section using anonymous unions ------------------ */
+#if defined(__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning 586
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+/* ================================================================================ */
+/* ================ WWDT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Windowed Watchdog Timer (WWDT) (WWDT)
+ */
+
+typedef struct { /*!< (@ 0x40000000) WWDT Structure */
+ __IO uint32_t MOD; /*!< (@ 0x40000000) Watchdog mode register. This register contains
+ the basic mode and status of the Watchdog Timer. */
+ __IO uint32_t TC; /*!< (@ 0x40000004) Watchdog timer constant register. This 24-bit
+ register determines the time-out value. */
+ __O uint32_t FEED; /*!< (@ 0x40000008) Watchdog feed sequence register. Writing 0xAA
+ followed by 0x55 to this register reloads the Watchdog timer
+ with the value contained in WDTC. */
+ __I uint32_t TV; /*!< (@ 0x4000000C) Watchdog timer value register. This 24-bit register
+ reads out the current value of the Watchdog timer. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t WARNINT; /*!< (@ 0x40000014) Watchdog Warning Interrupt compare value. */
+ __IO uint32_t WINDOW; /*!< (@ 0x40000018) Watchdog Window compare value. */
+} LPC_WWDT_Type;
+
+
+/* ================================================================================ */
+/* ================ MRT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Multi-Rate Timer (MRT) (MRT)
+ */
+
+typedef struct { /*!< (@ 0x40004000) MRT Structure */
+ __IO uint32_t INTVAL0; /*!< (@ 0x40004000) MRT0 Time interval value register. This value
+ is loaded into the TIMER0 register. */
+ __I uint32_t TIMER0; /*!< (@ 0x40004004) MRT0 Timer register. This register reads the
+ value of the down-counter. */
+ __IO uint32_t CTRL0; /*!< (@ 0x40004008) MRT0 Control register. This register controls
+ the MRT0 modes. */
+ __IO uint32_t STAT0; /*!< (@ 0x4000400C) MRT0 Status register. */
+ __IO uint32_t INTVAL1; /*!< (@ 0x40004010) MRT0 Time interval value register. This value
+ is loaded into the TIMER0 register. */
+ __I uint32_t TIMER1; /*!< (@ 0x40004014) MRT0 Timer register. This register reads the
+ value of the down-counter. */
+ __IO uint32_t CTRL1; /*!< (@ 0x40004018) MRT0 Control register. This register controls
+ the MRT0 modes. */
+ __IO uint32_t STAT1; /*!< (@ 0x4000401C) MRT0 Status register. */
+ __IO uint32_t INTVAL2; /*!< (@ 0x40004020) MRT0 Time interval value register. This value
+ is loaded into the TIMER0 register. */
+ __I uint32_t TIMER2; /*!< (@ 0x40004024) MRT0 Timer register. This register reads the
+ value of the down-counter. */
+ __IO uint32_t CTRL2; /*!< (@ 0x40004028) MRT0 Control register. This register controls
+ the MRT0 modes. */
+ __IO uint32_t STAT2; /*!< (@ 0x4000402C) MRT0 Status register. */
+ __IO uint32_t INTVAL3; /*!< (@ 0x40004030) MRT0 Time interval value register. This value
+ is loaded into the TIMER0 register. */
+ __I uint32_t TIMER3; /*!< (@ 0x40004034) MRT0 Timer register. This register reads the
+ value of the down-counter. */
+ __IO uint32_t CTRL3; /*!< (@ 0x40004038) MRT0 Control register. This register controls
+ the MRT0 modes. */
+ __IO uint32_t STAT3; /*!< (@ 0x4000403C) MRT0 Status register. */
+ __I uint32_t RESERVED0[45];
+ __I uint32_t IDLE_CH; /*!< (@ 0x400040F4) Idle channel register. This register returns
+ the number of the first idle channel. */
+ __IO uint32_t IRQ_FLAG; /*!< (@ 0x400040F8) Global interrupt flag register */
+} LPC_MRT_Type;
+
+
+/* ================================================================================ */
+/* ================ WKT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Self wake-up timer (WKT) (WKT)
+ */
+
+typedef struct { /*!< (@ 0x40008000) WKT Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40008000) Self wake-up timer control register. */
+ __I uint32_t RESERVED0[2];
+ __IO uint32_t COUNT; /*!< (@ 0x4000800C) Counter register. */
+} LPC_WKT_Type;
+
+
+/* ================================================================================ */
+/* ================ SWM ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Switch matrix (SWM) (SWM)
+ */
+
+typedef struct { /*!< (@ 0x4000C000) SWM Structure */
+ union {
+ __IO uint32_t PINASSIGN[12];
+ struct {
+ __IO uint32_t PINASSIGN0; /*!< (@ 0x4000C000) Pin assign register 0. Assign movable functions
+ U0_TXD, U0_RXD, U0_RTS, U0_CTS. */
+ __IO uint32_t PINASSIGN1; /*!< (@ 0x4000C004) Pin assign register 1. Assign movable functions
+ U0_SCLK, U1_TXD, U1_RXD, U1_RTS. */
+ __IO uint32_t PINASSIGN2; /*!< (@ 0x4000C008) Pin assign register 2. Assign movable functions
+ U1_CTS, U1_SCLK, U2_TXD, U2_RXD. */
+ __IO uint32_t PINASSIGN3; /*!< (@ 0x4000C00C) Pin assign register 3. Assign movable function
+ U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK. */
+ __IO uint32_t PINASSIGN4; /*!< (@ 0x4000C010) Pin assign register 4. Assign movable functions
+ SPI0_MOSI, SPI0_MISO, SPI0_SSEL0, SPI0_SSEL1. */
+ __IO uint32_t PINASSIGN5; /*!< (@ 0x4000C014) Pin assign register 5. Assign movable functions
+ SPI0_SSEL2, SPI0_SSEL3, SPI1_SCK, SPI1_MOSI */
+ __IO uint32_t PINASSIGN6; /*!< (@ 0x4000C018) Pin assign register 6. Assign movable functions
+ SPI1_MISO, SPI1_SSEL0, SPI1_SSEL1, SCT0_IN0. */
+ __IO uint32_t PINASSIGN7; /*!< (@ 0x4000C01C) Pin assign register 7. Assign movable functions
+ SCT_IN1, SCT_IN2, SCT_IN3, SCT_OUT0. */
+ __IO uint32_t PINASSIGN8; /*!< (@ 0x4000C020) Pin assign register 8. Assign movable functions
+ SCT_OUT1, SCT_OUT2, SCT_OUT3, SCT_OUT4. */
+ __IO uint32_t PINASSIGN9; /*!< (@ 0x4000C024) Pin assign register 9. Assign movable functions
+ SCT_OUT5, I2C1_SDA, I2C1_SCL, I2C2_SDA. */
+ __IO uint32_t PINASSIGN10; /*!< (@ 0x4000C028) Pin assign register 10. Assign movable functions
+ I2C2_SCL, I2C3_SDA, I2C3_SCL, ADC_PINTRIG0. */
+ __IO uint32_t PINASSIGN11; /*!< (@ 0x4000C02C) Pin assign register 11. Assign movable functions
+ ADC_PINTRIG1, ACMP_O, CLKOUT, GPIO_INT_BMAT */
+ };
+ };
+ __I uint32_t RESERVED0[100];
+ __IO uint32_t PINENABLE0; /*!< (@ 0x4000C1C0) Pin enable register 0. Enables fixed-pin functions
+ ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN,
+ VDDCMP. */
+} LPC_SWM_Type;
+
+
+/* ================================================================================ */
+/* ================ ADC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief 12-bit Analog-to-Digital Converter (ADC) (ADC)
+ */
+
+typedef struct { /*!< (@ 0x4001C000) ADC Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x4001C000) A/D Control Register. Contains the clock divide
+ value, enable bits for each sequence and the A/D power-down
+ bit. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t SEQA_CTRL; /*!< (@ 0x4001C008) A/D Conversion Sequence-A control Register: Controls
+ triggering and channel selection for conversion sequence-A.
+ Also specifies interrupt mode for sequence-A. */
+ __IO uint32_t SEQB_CTRL; /*!< (@ 0x4001C00C) A/D Conversion Sequence-B Control Register: Controls
+ triggering and channel selection for conversion sequence-B.
+ Also specifies interrupt mode for sequence-B. */
+ __IO uint32_t SEQA_GDAT; /*!< (@ 0x4001C010) A/D Sequence-A Global Data Register. This register
+ contains the result of the most recent A/D conversion performed
+ under sequence-A */
+ __IO uint32_t SEQB_GDAT; /*!< (@ 0x4001C014) A/D Sequence-B Global Data Register. This register
+ contains the result of the most recent A/D conversion performed
+ under sequence-B */
+ __I uint32_t RESERVED1[2];
+ __I uint32_t DAT0; /*!< (@ 0x4001C020) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT1; /*!< (@ 0x4001C024) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT2; /*!< (@ 0x4001C028) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT3; /*!< (@ 0x4001C02C) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT4; /*!< (@ 0x4001C030) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT5; /*!< (@ 0x4001C034) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT6; /*!< (@ 0x4001C038) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT7; /*!< (@ 0x4001C03C) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT8; /*!< (@ 0x4001C040) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT9; /*!< (@ 0x4001C044) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT10; /*!< (@ 0x4001C048) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT11; /*!< (@ 0x4001C04C) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __IO uint32_t THR0_LOW; /*!< (@ 0x4001C050) A/D Low Compare Threshold Register 0 : Contains
+ the lower threshold level for automatic threshold comparison
+ for any channels linked to threshold pair 0. */
+ __IO uint32_t THR1_LOW; /*!< (@ 0x4001C054) A/D Low Compare Threshold Register 1: Contains
+ the lower threshold level for automatic threshold comparison
+ for any channels linked to threshold pair 1. */
+ __IO uint32_t THR0_HIGH; /*!< (@ 0x4001C058) A/D High Compare Threshold Register 0: Contains
+ the upper threshold level for automatic threshold comparison
+ for any channels linked to threshold pair 0. */
+ __IO uint32_t THR1_HIGH; /*!< (@ 0x4001C05C) A/D High Compare Threshold Register 1: Contains
+ the upper threshold level for automatic threshold comparison
+ for any channels linked to threshold pair 1. */
+ __IO uint32_t CHAN_THRSEL; /*!< (@ 0x4001C060) A/D Channel-Threshold Select Register. Specifies
+ which set of threshold compare registers are to be used for
+ each channel */
+ __IO uint32_t INTEN; /*!< (@ 0x4001C064) A/D Interrupt Enable Register. This register
+ contains enable bits that enable the sequence-A, sequence-B,
+ threshold compare and data overrun interrupts to be generated. */
+ __IO uint32_t FLAGS; /*!< (@ 0x4001C068) A/D Flags Register. Contains the four interrupt
+ request flags and the individual component overrun and threshold-compare
+ flags. (The overrun bits replicate information stored in the
+ result registers). */
+ __IO uint32_t TRM; /*!< (@ 0x4001C06C) ADC trim register. */
+} LPC_ADC_Type;
+
+
+/* ================================================================================ */
+/* ================ PMU ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Power Management Unit (PMU) (PMU)
+ */
+
+typedef struct { /*!< (@ 0x40020000) PMU Structure */
+ __IO uint32_t PCON; /*!< (@ 0x40020000) Power control register */
+ __IO uint32_t GPREG0; /*!< (@ 0x40020004) General purpose register 0 */
+ __IO uint32_t GPREG1; /*!< (@ 0x40020008) General purpose register 0 */
+ __IO uint32_t GPREG2; /*!< (@ 0x4002000C) General purpose register 0 */
+ __IO uint32_t GPREG3; /*!< (@ 0x40020010) General purpose register 0 */
+ __IO uint32_t DPDCTRL; /*!< (@ 0x40020014) Deep power-down control register. Also includes
+ bits for general purpose storage. */
+} LPC_PMU_Type;
+
+
+/* ================================================================================ */
+/* ================ CMP ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Analog comparator (CMP)
+ */
+
+typedef struct { /*!< (@ 0x40024000) CMP Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
+ __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
+} LPC_CMP_Type;
+
+
+/* ================================================================================ */
+/* ================ DMATRIGMUX ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief DMA trigger mux (DMATRIGMUX)
+ */
+
+typedef struct { /*!< (@ 0x40028000) DMATRIGMUX Structure */
+ __IO uint32_t DMA_ITRIG_INMUX0; /*!< (@ 0x40028000) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX1; /*!< (@ 0x40028004) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX2; /*!< (@ 0x40028008) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX3; /*!< (@ 0x4002800C) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX4; /*!< (@ 0x40028010) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX5; /*!< (@ 0x40028014) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX6; /*!< (@ 0x40028018) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX7; /*!< (@ 0x4002801C) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX8; /*!< (@ 0x40028020) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX9; /*!< (@ 0x40028024) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX10; /*!< (@ 0x40028028) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX11; /*!< (@ 0x4002802C) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX12; /*!< (@ 0x40028030) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX13; /*!< (@ 0x40028034) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX14; /*!< (@ 0x40028038) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX15; /*!< (@ 0x4002803C) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX16; /*!< (@ 0x40028040) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX17; /*!< (@ 0x40028044) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+} LPC_DMATRIGMUX_Type;
+
+
+/* ================================================================================ */
+/* ================ INPUTMUX ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Input multiplexing (INPUTMUX)
+ */
+
+typedef struct { /*!< (@ 0x4002C000) INPUTMUX Structure */
+ __IO uint32_t DMA_INMUX_INMUX0; /*!< (@ 0x4002C000) Input mux register for DMA trigger input 20.
+ Selects from 18 DMA trigger outputs. */
+ __IO uint32_t DMA_INMUX_INMUX1; /*!< (@ 0x4002C004) Input mux register for DMA trigger input 20.
+ Selects from 18 DMA trigger outputs. */
+ __I uint32_t RESERVED0[6];
+ __IO uint32_t SCT0_INMUX0; /*!< (@ 0x4002C020) Input mux register for SCT input 0 */
+ __IO uint32_t SCT0_INMUX1; /*!< (@ 0x4002C024) Input mux register for SCT input 0 */
+ __IO uint32_t SCT0_INMUX2; /*!< (@ 0x4002C028) Input mux register for SCT input 0 */
+ __IO uint32_t SCT0_INMUX3; /*!< (@ 0x4002C02C) Input mux register for SCT input 0 */
+} LPC_INPUTMUX_Type;
+
+
+/* ================================================================================ */
+/* ================ FLASHCTRL ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Flash controller (FLASHCTRL)
+ */
+
+typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */
+ __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */
+ __I uint32_t RESERVED2;
+ __I uint32_t FMSW0; /*!< (@ 0x4004002C) Signature Word */
+} LPC_FLASHCTRL_Type;
+
+
+/* ================================================================================ */
+/* ================ IOCON ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief I/O configuration (IOCON) (IOCON)
+ */
+
+typedef struct { /*!< (@ 0x40044000) IOCON Structure */
+ __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
+ __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
+ __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
+ __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5/RESET */
+ __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
+ __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3/SWCLK */
+ __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2/SWDIO */
+ __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11. This is the
+ pin configuration for the true open-drain pin. */
+ __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10. This is the
+ pin configuration for the true open-drain pin. */
+ __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
+ __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
+ __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_17 */
+ __I uint32_t RESERVED0;
+ __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9/XTALOUT */
+ __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8/XTALIN */
+ __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
+ __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6/VDDCMP */
+ __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0/ACMP_I0 */
+ __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
+ __I uint32_t RESERVED1;
+ __IO uint32_t PIO0_28; /*!< (@ 0x40044050) I/O configuration for pin PIO0_28 */
+ __IO uint32_t PIO0_27; /*!< (@ 0x40044054) I/O configuration for pin PIO0_27 */
+ __IO uint32_t PIO0_26; /*!< (@ 0x40044058) I/O configuration for pin PIO0_26 */
+ __IO uint32_t PIO0_25; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_25 */
+ __IO uint32_t PIO0_24; /*!< (@ 0x40044060) I/O configuration for pin PIO0_24 */
+ __IO uint32_t PIO0_23; /*!< (@ 0x40044064) I/O configuration for pin PIO0_23/ADC_3 */
+ __IO uint32_t PIO0_22; /*!< (@ 0x40044068) I/O configuration for pin PIO0_22/ADC_4 */
+ __IO uint32_t PIO0_21; /*!< (@ 0x4004406C) I/O configuration for pin PIO0_21/ACMP_I4/ADC_5 */
+ __IO uint32_t PIO0_20; /*!< (@ 0x40044070) I/O configuration for pin PIO0_20/ADC_6 */
+ __IO uint32_t PIO0_19; /*!< (@ 0x40044074) I/O configuration for pin PIO0_19/ADC_7 */
+ __IO uint32_t PIO0_18; /*!< (@ 0x40044078) I/O configuration for pin PIO0_18/ADC_8 */
+} LPC_IOCON_Type;
+
+
+/* ================================================================================ */
+/* ================ SYSCON ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief System configuration (SYSCON) (SYSCON)
+ */
+
+typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
+ __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
+ __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
+ __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
+ __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
+ __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
+ __IO uint32_t IRCCTRL; /*!< (@ 0x40048028) IRC control */
+ __I uint32_t RESERVED1;
+ __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
+ __I uint32_t RESERVED2[3];
+ __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
+ __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */
+ __I uint32_t RESERVED3[10];
+ __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
+ __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */
+ __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
+ __I uint32_t RESERVED4;
+ __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
+ __I uint32_t RESERVED5[4];
+ __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048094) USART clock divider */
+ __I uint32_t RESERVED6[18];
+ __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
+ __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */
+ __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
+ __I uint32_t RESERVED7;
+ __IO uint32_t UARTFRGDIV; /*!< (@ 0x400480F0) USART1 to USART4 common fractional generator
+ divider value */
+ __IO uint32_t UARTFRGMULT; /*!< (@ 0x400480F4) USART1 to USART4 common fractional generator
+ multiplier value */
+ __I uint32_t RESERVED8;
+ __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */
+ __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
+ __I uint32_t RESERVED9[12];
+ __IO uint32_t IOCONCLKDIV6; /*!< (@ 0x40048134) Peripheral clock 6 to the IOCON block for programmable
+ glitch filter */
+ __I uint32_t RESERVED10[6];
+ __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
+ __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
+ __I uint32_t RESERVED11[6];
+ __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt
+ latency and determinism. */
+ __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
+ union {
+ __IO uint32_t PINTSEL[8];
+ struct {
+ __IO uint32_t PINTSEL0; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL1; /*!< (@ 0x4004817C) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL2; /*!< (@ 0x40048180) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL3; /*!< (@ 0x40048184) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL4; /*!< (@ 0x40048188) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL5; /*!< (@ 0x4004818C) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL6; /*!< (@ 0x40048190) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL7; /*!< (@ 0x40048194) GPIO Pin Interrupt Select register 0 */
+ };
+ };
+ __I uint32_t RESERVED12[27];
+ __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 pin wake-up enable register */
+ __I uint32_t RESERVED13[3];
+ __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register */
+ __I uint32_t RESERVED14[6];
+ __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
+ __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
+ __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
+ __I uint32_t RESERVED15[111];
+ __I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
+} LPC_SYSCON_Type;
+
+
+/* ================================================================================ */
+/* ================ I2C0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief I2C0-bus interface (I2C0)
+ */
+
+typedef struct { /*!< (@ 0x40050000) I2C0 Structure */
+ __IO uint32_t CFG; /*!< (@ 0x40050000) Configuration for shared functions. */
+ __IO uint32_t STAT; /*!< (@ 0x40050004) Status register for Master, Slave, and Monitor
+ functions. */
+ __IO uint32_t INTENSET; /*!< (@ 0x40050008) Interrupt Enable Set and read register. */
+ __O uint32_t INTENCLR; /*!< (@ 0x4005000C) Interrupt Enable Clear register. */
+ __IO uint32_t TIMEOUT; /*!< (@ 0x40050010) Time-out value register. */
+ __IO uint32_t CLKDIV; /*!< (@ 0x40050014) Clock pre-divider for the entire I2C block. This
+ determines what time increments are used for the MSTTIME and
+ SLVTIME registers. */
+ __I uint32_t INTSTAT; /*!< (@ 0x40050018) Interrupt Status register for Master, Slave,
+ and Monitor functions. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t MSTCTL; /*!< (@ 0x40050020) Master control register. */
+ __IO uint32_t MSTTIME; /*!< (@ 0x40050024) Master timing configuration. */
+ __IO uint32_t MSTDAT; /*!< (@ 0x40050028) Combined Master receiver and transmitter data
+ register. */
+ __I uint32_t RESERVED1[5];
+ __IO uint32_t SLVCTL; /*!< (@ 0x40050040) Slave control register. */
+ __IO uint32_t SLVDAT; /*!< (@ 0x40050044) Combined Slave receiver and transmitter data
+ register. */
+ union {
+ __IO uint32_t SLVADR[4];
+ struct {
+ __IO uint32_t SLVADR0; /*!< (@ 0x40050048) Slave address 0. */
+ __IO uint32_t SLVADR1; /*!< (@ 0x4005004C) Slave address 0. */
+ __IO uint32_t SLVADR2; /*!< (@ 0x40050050) Slave address 0. */
+ __IO uint32_t SLVADR3; /*!< (@ 0x40050054) Slave address 0. */
+ };
+ };
+ __IO uint32_t SLVQUAL0; /*!< (@ 0x40050058) Slave Qualification for address 0. */
+ __I uint32_t RESERVED2[9];
+ __I uint32_t MONRXDAT; /*!< (@ 0x40050080) Monitor receiver data register. */
+} LPC_I2C0_Type;
+
+
+/* ================================================================================ */
+/* ================ SPI0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief SPI0 (SPI0)
+ */
+
+typedef struct { /*!< (@ 0x40058000) SPI0 Structure */
+ __IO uint32_t CFG; /*!< (@ 0x40058000) SPI Configuration register */
+ __IO uint32_t DLY; /*!< (@ 0x40058004) SPI Delay register */
+ __IO uint32_t STAT; /*!< (@ 0x40058008) SPI Status. Some status flags can be cleared
+ by writing a 1 to that bit position */
+ __IO uint32_t INTENSET; /*!< (@ 0x4005800C) SPI Interrupt Enable read and Set. A complete
+ value may be read from this register. Writing a 1 to any implemented
+ bit position causes that bit to be set. */
+ __O uint32_t INTENCLR; /*!< (@ 0x40058010) SPI Interrupt Enable Clear. Writing a 1 to any
+ implemented bit position causes the corresponding bit in INTENSET
+ to be cleared. */
+ __I uint32_t RXDAT; /*!< (@ 0x40058014) SPI Receive Data */
+ __IO uint32_t TXDATCTL; /*!< (@ 0x40058018) SPI Transmit Data with Control */
+ __IO uint32_t TXDAT; /*!< (@ 0x4005801C) SPI Transmit Data */
+ __IO uint32_t TXCTL; /*!< (@ 0x40058020) SPI Transmit Control */
+ __IO uint32_t DIV; /*!< (@ 0x40058024) SPI clock Divider */
+ __I uint32_t INTSTAT; /*!< (@ 0x40058028) SPI Interrupt Status */
+} LPC_SPI0_Type;
+
+
+/* ================================================================================ */
+/* ================ USART0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief USART0 (USART0)
+ */
+
+typedef struct { /*!< (@ 0x40064000) USART0 Structure */
+ __IO uint32_t CFG; /*!< (@ 0x40064000) USART Configuration register. Basic USART configuration
+ settings that typically are not changed during operation. */
+ __IO uint32_t CTL; /*!< (@ 0x40064004) USART Control register. USART control settings
+ that are more likely to change during operation. */
+ __IO uint32_t STAT; /*!< (@ 0x40064008) USART Status register. The complete status value
+ can be read here. Writing ones clears some bits in the register.
+ Some bits can be cleared by writing a 1 to them. */
+ __IO uint32_t INTENSET; /*!< (@ 0x4006400C) Interrupt Enable read and Set register. Contains
+ an individual interrupt enable bit for each potential USART
+ interrupt. A complete value may be read from this register.
+ Writing a 1 to any implemented bit position causes that bit
+ to be set. */
+ __O uint32_t INTENCLR; /*!< (@ 0x40064010) Interrupt Enable Clear register. Allows clearing
+ any combination of bits in the INTENSET register. Writing a
+ 1 to any implemented bit position causes the corresponding bit
+ to be cleared. */
+ __I uint32_t RXDAT; /*!< (@ 0x40064014) Receiver Data register. Contains the last character
+ received. */
+ __I uint32_t RXDATSTAT; /*!< (@ 0x40064018) Receiver Data with Status register. Combines
+ the last character received with the current USART receive status.
+ Allows DMA or software to recover incoming data and status together. */
+ __IO uint32_t TXDAT; /*!< (@ 0x4006401C) Transmit Data register. Data to be transmitted
+ is written here. */
+ __IO uint32_t BRG; /*!< (@ 0x40064020) Baud Rate Generator register. 16-bit integer
+ baud rate divisor value. */
+ __I uint32_t INTSTAT; /*!< (@ 0x40064024) Interrupt status register. Reflects interrupts
+ that are currently enabled. */
+ __IO uint32_t OSR; /*!< (@ 0x40064028) Oversample selection register for asynchronous
+ communication. */
+ __IO uint32_t ADDR; /*!< (@ 0x4006402C) Address register for automatic address matching. */
+} LPC_USART0_Type;
+
+
+/* ================================================================================ */
+/* ================ CRC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Cyclic Redundancy Check (CRC) engine (CRC)
+ */
+
+typedef struct { /*!< (@ 0x50000000) CRC Structure */
+ __IO uint32_t MODE; /*!< (@ 0x50000000) CRC mode register */
+ __IO uint32_t SEED; /*!< (@ 0x50000004) CRC seed register */
+
+ union {
+ __O uint32_t WR_DATA; /*!< (@ 0x50000008) CRC data register */
+ __I uint32_t SUM; /*!< (@ 0x50000008) CRC checksum register */
+ };
+} LPC_CRC_Type;
+
+
+/* ================================================================================ */
+/* ================ SCT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief State Configurable Timer (SCT) (SCT)
+ */
+
+typedef struct { /*!< (@ 0x50004000) SCT Structure */
+ __IO uint32_t CONFIG; /*!< (@ 0x50004000) SCT configuration register */
+ __IO uint32_t CTRL; /*!< (@ 0x50004004) SCT control register */
+ __IO uint32_t LIMIT; /*!< (@ 0x50004008) SCT limit register */
+ __IO uint32_t HALT; /*!< (@ 0x5000400C) SCT halt condition register */
+ __IO uint32_t STOP; /*!< (@ 0x50004010) SCT stop condition register */
+ __IO uint32_t START; /*!< (@ 0x50004014) SCT start condition register */
+ __I uint32_t RESERVED0[10];
+ __IO uint32_t COUNT; /*!< (@ 0x50004040) SCT counter register */
+ __IO uint32_t STATE; /*!< (@ 0x50004044) SCT state register */
+ __I uint32_t INPUT; /*!< (@ 0x50004048) SCT input register */
+ __IO uint32_t REGMODE; /*!< (@ 0x5000404C) SCT match/capture registers mode register */
+ __IO uint32_t OUTPUT; /*!< (@ 0x50004050) SCT output register */
+ __IO uint32_t OUTPUTDIRCTRL; /*!< (@ 0x50004054) SCT output counter direction control register */
+ __IO uint32_t RES; /*!< (@ 0x50004058) SCT conflict resolution register */
+ __IO uint32_t DMAREQ0; /*!< (@ 0x5000405C) SCT DMA request 0 register */
+ __IO uint32_t DMAREQ1; /*!< (@ 0x50004060) SCT DMA request 1 register */
+ __I uint32_t RESERVED1[35];
+ __IO uint32_t EVEN; /*!< (@ 0x500040F0) SCT event enable register */
+ __IO uint32_t EVFLAG; /*!< (@ 0x500040F4) SCT event flag register */
+ __IO uint32_t CONEN; /*!< (@ 0x500040F8) SCT conflict enable register */
+ __IO uint32_t CONFLAG; /*!< (@ 0x500040FC) SCT conflict flag register */
+
+union {
+ union {
+ __IO uint32_t CAP0; /*!< (@ 0x50004100) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ __IO uint32_t MATCH0; /*!< (@ 0x50004100) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAP1; /*!< (@ 0x50004104) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ __IO uint32_t MATCH1; /*!< (@ 0x50004104) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAP2; /*!< (@ 0x50004108) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ __IO uint32_t MATCH2; /*!< (@ 0x50004108) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCH3; /*!< (@ 0x5000410C) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ __IO uint32_t CAP3; /*!< (@ 0x5000410C) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ };
+
+ union {
+ __IO uint32_t CAP4; /*!< (@ 0x50004110) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ __IO uint32_t MATCH4; /*!< (@ 0x50004110) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCH5; /*!< (@ 0x50004114) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ __IO uint32_t CAP5; /*!< (@ 0x50004114) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ };
+
+ union {
+ __IO uint32_t CAP6; /*!< (@ 0x50004118) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ __IO uint32_t MATCH6; /*!< (@ 0x50004118) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAP7; /*!< (@ 0x5000411C) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ __IO uint32_t MATCH7; /*!< (@ 0x5000411C) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ };
+ __IO uint32_t CAP[8];
+ __IO uint32_t MATCH[8];
+};
+ __I uint32_t RESERVED2[56];
+
+ union {
+ struct {
+ union {
+ __IO uint32_t CAPCTRL0; /*!< (@ 0x50004200) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL0; /*!< (@ 0x50004200) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL1; /*!< (@ 0x50004204) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL1; /*!< (@ 0x50004204) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL2; /*!< (@ 0x50004208) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL2; /*!< (@ 0x50004208) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCHREL3; /*!< (@ 0x5000420C) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ __IO uint32_t CAPCTRL3; /*!< (@ 0x5000420C) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL4; /*!< (@ 0x50004210) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL4; /*!< (@ 0x50004210) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL5; /*!< (@ 0x50004214) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL5; /*!< (@ 0x50004214) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL6; /*!< (@ 0x50004218) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL6; /*!< (@ 0x50004218) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL7; /*!< (@ 0x5000421C) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL7; /*!< (@ 0x5000421C) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+ };
+ __IO uint32_t MATCHREL[8];
+ };
+ __I uint32_t RESERVED3[56];
+
+ union {
+ struct {
+ __IO uint32_t EV0_STATE; /*!< (@ 0x50004300) SCT event state register 0 */
+ __IO uint32_t EV0_CTRL; /*!< (@ 0x50004304) SCT event control register 0 */
+ __IO uint32_t EV1_STATE; /*!< (@ 0x50004308) SCT event state register 0 */
+ __IO uint32_t EV1_CTRL; /*!< (@ 0x5000430C) SCT event control register 0 */
+ __IO uint32_t EV2_STATE; /*!< (@ 0x50004310) SCT event state register 0 */
+ __IO uint32_t EV2_CTRL; /*!< (@ 0x50004314) SCT event control register 0 */
+ __IO uint32_t EV3_STATE; /*!< (@ 0x50004318) SCT event state register 0 */
+ __IO uint32_t EV3_CTRL; /*!< (@ 0x5000431C) SCT event control register 0 */
+ __IO uint32_t EV4_STATE; /*!< (@ 0x50004320) SCT event state register 0 */
+ __IO uint32_t EV4_CTRL; /*!< (@ 0x50004324) SCT event control register 0 */
+ __IO uint32_t EV5_STATE; /*!< (@ 0x50004328) SCT event state register 0 */
+ __IO uint32_t EV5_CTRL; /*!< (@ 0x5000432C) SCT event control register 0 */
+ __IO uint32_t EV6_STATE; /*!< (@ 0x50004330) SCT event state register 0 */
+ __IO uint32_t EV6_CTRL; /*!< (@ 0x50004334) SCT event control register 0 */
+ __IO uint32_t EV7_STATE; /*!< (@ 0x50004338) SCT event state register 0 */
+ __IO uint32_t EV7_CTRL; /*!< (@ 0x5000433C) SCT event control register 0 */
+ };
+ __IO struct {
+ uint32_t STATE;
+ uint32_t CTRL;
+ } EVENT[8];
+ };
+
+ __I uint32_t RESERVED4[112];
+
+ union {
+ struct {
+ __IO uint32_t OUT0_SET; /*!< (@ 0x50004500) SCT output 0 set register */
+ __IO uint32_t OUT0_CLR; /*!< (@ 0x50004504) SCT output 0 clear register */
+ __IO uint32_t OUT1_SET; /*!< (@ 0x50004508) SCT output 0 set register */
+ __IO uint32_t OUT1_CLR; /*!< (@ 0x5000450C) SCT output 0 clear register */
+ __IO uint32_t OUT2_SET; /*!< (@ 0x50004510) SCT output 0 set register */
+ __IO uint32_t OUT2_CLR; /*!< (@ 0x50004514) SCT output 0 clear register */
+ __IO uint32_t OUT3_SET; /*!< (@ 0x50004518) SCT output 0 set register */
+ __IO uint32_t OUT3_CLR; /*!< (@ 0x5000451C) SCT output 0 clear register */
+ __IO uint32_t OUT4_SET; /*!< (@ 0x50004520) SCT output 0 set register */
+ __IO uint32_t OUT4_CLR; /*!< (@ 0x50004524) SCT output 0 clear register */
+ __IO uint32_t OUT5_SET; /*!< (@ 0x50004528) SCT output 0 set register */
+ __IO uint32_t OUT5_CLR; /*!< (@ 0x5000452C) SCT output 0 clear register */
+ };
+ __IO struct {
+ uint32_t SET;
+ uint32_t CLR;
+ } OUT[6];
+};
+
+} LPC_SCT_Type;
+
+
+/* ================================================================================ */
+/* ================ DMA ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief DMA controller (DMA)
+ */
+
+typedef struct { /*!< (@ 0x50008000) DMA Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x50008000) DMA control. */
+ __I uint32_t INTSTAT; /*!< (@ 0x50008004) Interrupt status. */
+ __IO uint32_t SRAMBASE; /*!< (@ 0x50008008) SRAM address of the channel configuration table. */
+ __I uint32_t RESERVED0[5];
+ __IO uint32_t ENABLESET0; /*!< (@ 0x50008020) Channel Enable read and Set for all DMA channels. */
+ __I uint32_t RESERVED1;
+ __O uint32_t ENABLECLR0; /*!< (@ 0x50008028) Channel Enable Clear for all DMA channels. */
+ __I uint32_t RESERVED2;
+ __I uint32_t ACTIVE0; /*!< (@ 0x50008030) Channel Active status for all DMA channels. */
+ __I uint32_t RESERVED3;
+ __I uint32_t BUSY0; /*!< (@ 0x50008038) Channel Busy status for all DMA channels. */
+ __I uint32_t RESERVED4;
+ __IO uint32_t ERRINT0; /*!< (@ 0x50008040) Error Interrupt status for all DMA channels. */
+ __I uint32_t RESERVED5;
+ __IO uint32_t INTENSET0; /*!< (@ 0x50008048) Interrupt Enable read and Set for all DMA channels. */
+ __I uint32_t RESERVED6;
+ __O uint32_t INTENCLR0; /*!< (@ 0x50008050) Interrupt Enable Clear for all DMA channels. */
+ __I uint32_t RESERVED7;
+ __IO uint32_t INTA0; /*!< (@ 0x50008058) Interrupt A status for all DMA channels. */
+ __I uint32_t RESERVED8;
+ __IO uint32_t INTB0; /*!< (@ 0x50008060) Interrupt B status for all DMA channels. */
+ __I uint32_t RESERVED9;
+ __O uint32_t SETVALID0; /*!< (@ 0x50008068) Set ValidPending control bits for all DMA channels. */
+ __I uint32_t RESERVED10;
+ __O uint32_t SETTRIG0; /*!< (@ 0x50008070) Set Trigger control bits for all DMA channels. */
+ __I uint32_t RESERVED11;
+ __O uint32_t ABORT0; /*!< (@ 0x50008078) Channel Abort control for all DMA channels. */
+ __I uint32_t RESERVED12[225];
+ __IO uint32_t CFG0; /*!< (@ 0x50008400) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT0; /*!< (@ 0x50008404) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG0; /*!< (@ 0x50008408) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED13;
+ __IO uint32_t CFG1; /*!< (@ 0x50008410) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT1; /*!< (@ 0x50008414) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG1; /*!< (@ 0x50008418) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED14;
+ __IO uint32_t CFG2; /*!< (@ 0x50008420) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT2; /*!< (@ 0x50008424) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG2; /*!< (@ 0x50008428) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED15;
+ __IO uint32_t CFG3; /*!< (@ 0x50008430) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT3; /*!< (@ 0x50008434) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG3; /*!< (@ 0x50008438) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED16;
+ __IO uint32_t CFG4; /*!< (@ 0x50008440) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT4; /*!< (@ 0x50008444) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG4; /*!< (@ 0x50008448) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED17;
+ __IO uint32_t CFG5; /*!< (@ 0x50008450) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT5; /*!< (@ 0x50008454) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG5; /*!< (@ 0x50008458) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED18;
+ __IO uint32_t CFG6; /*!< (@ 0x50008460) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT6; /*!< (@ 0x50008464) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG6; /*!< (@ 0x50008468) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED19;
+ __IO uint32_t CFG7; /*!< (@ 0x50008470) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT7; /*!< (@ 0x50008474) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG7; /*!< (@ 0x50008478) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED20;
+ __IO uint32_t CFG8; /*!< (@ 0x50008480) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT8; /*!< (@ 0x50008484) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG8; /*!< (@ 0x50008488) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED21;
+ __IO uint32_t CFG9; /*!< (@ 0x50008490) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT9; /*!< (@ 0x50008494) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG9; /*!< (@ 0x50008498) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED22;
+ __IO uint32_t CFG10; /*!< (@ 0x500084A0) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT10; /*!< (@ 0x500084A4) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG10; /*!< (@ 0x500084A8) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED23;
+ __IO uint32_t CFG11; /*!< (@ 0x500084B0) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT11; /*!< (@ 0x500084B4) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG11; /*!< (@ 0x500084B8) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED24;
+ __IO uint32_t CFG12; /*!< (@ 0x500084C0) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT12; /*!< (@ 0x500084C4) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG12; /*!< (@ 0x500084C8) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED25;
+ __IO uint32_t CFG13; /*!< (@ 0x500084D0) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT13; /*!< (@ 0x500084D4) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG13; /*!< (@ 0x500084D8) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED26;
+ __IO uint32_t CFG14; /*!< (@ 0x500084E0) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT14; /*!< (@ 0x500084E4) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG14; /*!< (@ 0x500084E8) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED27;
+ __IO uint32_t CFG15; /*!< (@ 0x500084F0) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT15; /*!< (@ 0x500084F4) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG15; /*!< (@ 0x500084F8) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED28;
+ __IO uint32_t CFG16; /*!< (@ 0x50008500) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT16; /*!< (@ 0x50008504) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG16; /*!< (@ 0x50008508) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED29;
+ __IO uint32_t CFG17; /*!< (@ 0x50008510) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT17; /*!< (@ 0x50008514) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG17; /*!< (@ 0x50008518) Transfer configuration register for DMA channel
+ 0. */
+} LPC_DMA_Type;
+
+
+/* ================================================================================ */
+/* ================ GPIO_PORT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief General Purpose I/O port (GPIO) (GPIO_PORT)
+ */
+
+typedef struct { /*!< (@ 0xA0000000) GPIO_PORT Structure */
+ __IO uint8_t B0; /*!< (@ 0xA0000000) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B1; /*!< (@ 0xA0000001) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B2; /*!< (@ 0xA0000002) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B3; /*!< (@ 0xA0000003) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B4; /*!< (@ 0xA0000004) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B5; /*!< (@ 0xA0000005) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B6; /*!< (@ 0xA0000006) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B7; /*!< (@ 0xA0000007) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B8; /*!< (@ 0xA0000008) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B9; /*!< (@ 0xA0000009) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B10; /*!< (@ 0xA000000A) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B11; /*!< (@ 0xA000000B) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B12; /*!< (@ 0xA000000C) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B13; /*!< (@ 0xA000000D) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B14; /*!< (@ 0xA000000E) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B15; /*!< (@ 0xA000000F) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B16; /*!< (@ 0xA0000010) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B17; /*!< (@ 0xA0000011) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B18; /*!< (@ 0xA0000012) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B19; /*!< (@ 0xA0000013) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B20; /*!< (@ 0xA0000014) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B21; /*!< (@ 0xA0000015) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B22; /*!< (@ 0xA0000016) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B23; /*!< (@ 0xA0000017) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B24; /*!< (@ 0xA0000018) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B25; /*!< (@ 0xA0000019) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B26; /*!< (@ 0xA000001A) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B27; /*!< (@ 0xA000001B) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B28; /*!< (@ 0xA000001C) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __I uint8_t RESERVED0[4067];
+ __IO uint32_t W0; /*!< (@ 0xA0001000) Word pin registers port 0 */
+ __IO uint32_t W1; /*!< (@ 0xA0001004) Word pin registers port 0 */
+ __IO uint32_t W2; /*!< (@ 0xA0001008) Word pin registers port 0 */
+ __IO uint32_t W3; /*!< (@ 0xA000100C) Word pin registers port 0 */
+ __IO uint32_t W4; /*!< (@ 0xA0001010) Word pin registers port 0 */
+ __IO uint32_t W5; /*!< (@ 0xA0001014) Word pin registers port 0 */
+ __IO uint32_t W6; /*!< (@ 0xA0001018) Word pin registers port 0 */
+ __IO uint32_t W7; /*!< (@ 0xA000101C) Word pin registers port 0 */
+ __IO uint32_t W8; /*!< (@ 0xA0001020) Word pin registers port 0 */
+ __IO uint32_t W9; /*!< (@ 0xA0001024) Word pin registers port 0 */
+ __IO uint32_t W10; /*!< (@ 0xA0001028) Word pin registers port 0 */
+ __IO uint32_t W11; /*!< (@ 0xA000102C) Word pin registers port 0 */
+ __IO uint32_t W12; /*!< (@ 0xA0001030) Word pin registers port 0 */
+ __IO uint32_t W13; /*!< (@ 0xA0001034) Word pin registers port 0 */
+ __IO uint32_t W14; /*!< (@ 0xA0001038) Word pin registers port 0 */
+ __IO uint32_t W15; /*!< (@ 0xA000103C) Word pin registers port 0 */
+ __IO uint32_t W16; /*!< (@ 0xA0001040) Word pin registers port 0 */
+ __IO uint32_t W17; /*!< (@ 0xA0001044) Word pin registers port 0 */
+ __IO uint32_t W18; /*!< (@ 0xA0001048) Word pin registers port 0 */
+ __IO uint32_t W19; /*!< (@ 0xA000104C) Word pin registers port 0 */
+ __IO uint32_t W20; /*!< (@ 0xA0001050) Word pin registers port 0 */
+ __IO uint32_t W21; /*!< (@ 0xA0001054) Word pin registers port 0 */
+ __IO uint32_t W22; /*!< (@ 0xA0001058) Word pin registers port 0 */
+ __IO uint32_t W23; /*!< (@ 0xA000105C) Word pin registers port 0 */
+ __IO uint32_t W24; /*!< (@ 0xA0001060) Word pin registers port 0 */
+ __IO uint32_t W25; /*!< (@ 0xA0001064) Word pin registers port 0 */
+ __IO uint32_t W26; /*!< (@ 0xA0001068) Word pin registers port 0 */
+ __IO uint32_t W27; /*!< (@ 0xA000106C) Word pin registers port 0 */
+ __IO uint32_t W28; /*!< (@ 0xA0001070) Word pin registers port 0 */
+ __I uint32_t RESERVED1[995];
+ __IO uint32_t DIR0; /*!< (@ 0xA0002000) Direction registers port 0 */
+ __I uint32_t RESERVED2[31];
+ __IO uint32_t MASK0; /*!< (@ 0xA0002080) Mask register port 0 */
+ __I uint32_t RESERVED3[31];
+ __IO uint32_t PIN0; /*!< (@ 0xA0002100) Port pin register port 0 */
+ __I uint32_t RESERVED4[31];
+ __IO uint32_t MPIN0; /*!< (@ 0xA0002180) Masked port register port 0 */
+ __I uint32_t RESERVED5[31];
+ __IO uint32_t SET0; /*!< (@ 0xA0002200) Write: Set register for port 0 Read: output bits
+ for port 0 */
+ __I uint32_t RESERVED6[31];
+ __O uint32_t CLR0; /*!< (@ 0xA0002280) Clear port 0 */
+ __I uint32_t RESERVED7[31];
+ __O uint32_t NOT0; /*!< (@ 0xA0002300) Toggle port 0 */
+ __I uint32_t RESERVED8[31];
+ __O uint32_t DIRSET0; /*!< (@ 0xA0002380) Set pin direction bits for port 0. */
+ __I uint32_t RESERVED9[31];
+ __O uint32_t DIRCLR0; /*!< (@ 0xA0002400) Clear pin direction bits for port 0. */
+ __I uint32_t RESERVED10[31];
+ __O uint32_t DIRNOT0; /*!< (@ 0xA0002480) Toggle pin direction bits for port 0. */
+} LPC_GPIO_PORT_Type;
+
+
+/* ================================================================================ */
+/* ================ PIN_INT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Pin interrupt and pattern match engine (PIN_INT)
+ */
+
+typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
+ __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
+ __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin interrupt level or rising edge interrupt
+ enable register */
+ __O uint32_t SIENR; /*!< (@ 0xA0004008) Pin interrupt level (rising edge) interrupt set
+ register */
+ __O uint32_t CIENR; /*!< (@ 0xA000400C) Pin interrupt level or rising edge interrupt
+ clear register */
+ __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin interrupt active level or falling edge interrupt
+ enable register */
+ __O uint32_t SIENF; /*!< (@ 0xA0004014) Pin interrupt active level or falling edge interrupt
+ set register */
+ __O uint32_t CIENF; /*!< (@ 0xA0004018) Pin interrupt active level (falling edge) interrupt
+ clear register */
+ __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin interrupt rising edge register */
+ __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin interrupt falling edge register */
+ __IO uint32_t IST; /*!< (@ 0xA0004024) Pin interrupt status register */
+ __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
+ __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source
+ register */
+ __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration
+ register */
+} LPC_PIN_INT_Type;
+
+
+/* -------------------- End of section using anonymous unions ------------------- */
+#if defined(__CC_ARM)
+ #pragma pop
+#elif defined(__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning restore
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================ Peripheral memory map ================ */
+/* ================================================================================ */
+
+#define LPC_WWDT_BASE 0x40000000UL
+#define LPC_MRT_BASE 0x40004000UL
+#define LPC_WKT_BASE 0x40008000UL
+#define LPC_SWM_BASE 0x4000C000UL
+#define LPC_ADC_BASE 0x4001C000UL
+#define LPC_PMU_BASE 0x40020000UL
+#define LPC_CMP_BASE 0x40024000UL
+#define LPC_DMATRIGMUX_BASE 0x40028000UL
+#define LPC_INPUTMUX_BASE 0x4002C000UL
+#define LPC_FLASHCTRL_BASE 0x40040000UL
+#define LPC_IOCON_BASE 0x40044000UL
+#define LPC_SYSCON_BASE 0x40048000UL
+#define LPC_I2C0_BASE 0x40050000UL
+#define LPC_I2C1_BASE 0x40054000UL
+#define LPC_SPI0_BASE 0x40058000UL
+#define LPC_SPI1_BASE 0x4005C000UL
+#define LPC_USART0_BASE 0x40064000UL
+#define LPC_USART1_BASE 0x40068000UL
+#define LPC_USART2_BASE 0x4006C000UL
+#define LPC_I2C2_BASE 0x40070000UL
+#define LPC_I2C3_BASE 0x40074000UL
+#define LPC_CRC_BASE 0x50000000UL
+#define LPC_SCT_BASE 0x50004000UL
+#define LPC_DMA_BASE 0x50008000UL
+#define LPC_GPIO_PORT_BASE 0xA0000000UL
+#define LPC_PIN_INT_BASE 0xA0004000UL
+
+
+/* ================================================================================ */
+/* ================ Peripheral declaration ================ */
+/* ================================================================================ */
+
+#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
+#define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
+#define LPC_WKT ((LPC_WKT_Type *) LPC_WKT_BASE)
+#define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
+#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
+#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
+#define LPC_CMP ((LPC_CMP_Type *) LPC_CMP_BASE)
+#define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE)
+#define LPC_INPUTMUX ((LPC_INPUTMUX_Type *) LPC_INPUTMUX_BASE)
+#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
+#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
+#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
+#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
+#define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE)
+#define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
+#define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
+#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
+#define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
+#define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
+#define LPC_I2C2 ((LPC_I2C0_Type *) LPC_I2C2_BASE)
+#define LPC_I2C3 ((LPC_I2C0_Type *) LPC_I2C3_BASE)
+#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
+#define LPC_SCT ((LPC_SCT_Type *) LPC_SCT_BASE)
+#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
+#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
+#define LPC_PIN_INT ((LPC_PIN_INT_Type *) LPC_PIN_INT_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group LPC82x */
+/** @} */ /* End of group (null) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC82x_H */
+
diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/LPC824.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/LPC824.sct
new file mode 100644
index 0000000000..310aa82197
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/LPC824.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x10000000+0xC0 0x2000-0xC0 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s
new file mode 100644
index 0000000000..a90d8d290e
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s
@@ -0,0 +1,218 @@
+;/*****************************************************************************
+; * @file: startup_LPC8xx.s
+; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
+; * for the NXP LPC8xx Device Series
+; * @version: V1.0
+; * @date: 16. Aug. 2012
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+__initial_sp EQU 0x10002000
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD SPI0_IRQHandler ; SPI0 controller
+ DCD SPI1_IRQHandler ; SPI1 controller
+ DCD 0 ; Reserved
+ DCD UART0_IRQHandler ; UART0
+ DCD UART1_IRQHandler ; UART1
+ DCD UART2_IRQHandler ; UART2
+ DCD 0 ; Reserved
+ DCD I2C1_IRQHandler ; I2C1 controller
+ DCD I2C0_IRQHandler ; I2C0 controller
+ DCD SCT_IRQHandler ; Smart Counter Timer
+ DCD MRT_IRQHandler ; Multi-Rate Timer
+ DCD CMP_IRQHandler ; Comparator
+ DCD WDT_IRQHandler ; PIO1 (0:11)
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD Flash_IRQHandler ; Flash interrupt
+ DCD WKT_IRQHandler ; Wakeup timer
+ DCD ADC_SEQA_IRQHandler ; ADC sequence A completion
+ DCD ADC_SEQB_IRQHandler ; ADC sequence B completion
+ DCD ADC_THCMP_IRQHandler ; ADC threshold compare
+ DCD ADC_OVR_IRQHandler ; ADC overrun
+ DCD DMA__RQHandler ; DMA interrupt
+ DCD I2C2_IRQHandler ; I2C2 controller
+ DCD I2C3_IRQHandler ; I2C3 controller
+ DCD 0 ; Reserved
+ DCD PININT0_IRQHandler ; PIO INT0
+ DCD PININT1_IRQHandler ; PIO INT1
+ DCD PININT2_IRQHandler ; PIO INT2
+ DCD PININT3_IRQHandler ; PIO INT3
+ DCD PININT4_IRQHandler ; PIO INT4
+ DCD PININT5_IRQHandler ; PIO INT5
+ DCD PININT6_IRQHandler ; PIO INT6
+ DCD PININT7_IRQHandler ; PIO INT7
+
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT NMI_Handler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT SCT_IRQHandler [WEAK]
+ EXPORT MRT_IRQHandler [WEAK]
+ EXPORT CMP_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT Flash_IRQHandler [WEAK]
+ EXPORT WKT_IRQHandler [WEAK]
+ EXPORT ADC_SEQA_IRQHandler [WEAK]
+ EXPORT ADC_SEQB_IRQHandler [WEAK]
+ EXPORT ADC_THCMP_IRQHandler [WEAK]
+ EXPORT ADC_OVR_IRQHandler [WEAK]
+ EXPORT DMA__RQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT I2C3_IRQHandler [WEAK]
+ EXPORT PININT0_IRQHandler [WEAK]
+ EXPORT PININT1_IRQHandler [WEAK]
+ EXPORT PININT2_IRQHandler [WEAK]
+ EXPORT PININT3_IRQHandler [WEAK]
+ EXPORT PININT4_IRQHandler [WEAK]
+ EXPORT PININT5_IRQHandler [WEAK]
+ EXPORT PININT6_IRQHandler [WEAK]
+ EXPORT PININT7_IRQHandler [WEAK]
+
+NMI_Handler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+I2C1_IRQHandler
+I2C0_IRQHandler
+SCT_IRQHandler
+MRT_IRQHandler
+CMP_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+Flash_IRQHandler
+WKT_IRQHandler
+ADC_SEQA_IRQHandler
+ADC_SEQB_IRQHandler
+ADC_THCMP_IRQHandler
+ADC_OVR_IRQHandler
+DMA__RQHandler
+I2C2_IRQHandler
+I2C3_IRQHandler
+PININT0_IRQHandler
+PININT1_IRQHandler
+PININT2_IRQHandler
+PININT3_IRQHandler
+PININT4_IRQHandler
+PININT5_IRQHandler
+PININT6_IRQHandler
+PININT7_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/system_LPC8xx.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/system_LPC8xx.c
new file mode 100644
index 0000000000..4050de7144
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/system_LPC8xx.c
@@ -0,0 +1,389 @@
+/******************************************************************************
+ * @file: system_LPC8xx.c
+ * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
+ * for the NXP LPC8xx Device Series
+ * @version: V1.0
+ * @date: 16. Aug. 2012
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#include
+#include "LPC82x.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------*/
+//
+// Clock Configuration
+#define CLOCK_SETUP 1
+// System Oscillator Control Register (SYSOSCCTRL)
+// BYPASS: System Oscillator Bypass Enable
+// If enabled then PLL input (sys_osc_clk) is fed
+// directly from XTALIN and XTALOUT pins.
+// FREQRANGE: System Oscillator Frequency Range
+// Determines frequency range for Low-power oscillator.
+// <0=> 1 - 20 MHz
+// <1=> 15 - 25 MHz
+//
+#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+//
+// Watchdog Oscillator Control Register (WDTOSCCTRL)
+// DIVSEL: Select Divider for Fclkana
+// wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
+// <0-31>
+// FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
+// <0=> Undefined
+// <1=> 0.6 MHz
+// <2=> 1.05 MHz
+// <3=> 1.4 MHz
+// <4=> 1.75 MHz
+// <5=> 2.1 MHz
+// <6=> 2.4 MHz
+// <7=> 2.7 MHz
+// <8=> 3.0 MHz
+// <9=> 3.25 MHz
+// <10=> 3.5 MHz
+// <11=> 3.75 MHz
+// <12=> 4.0 MHz
+// <13=> 4.2 MHz
+// <14=> 4.4 MHz
+// <15=> 4.6 MHz
+#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
+//
+// System PLL Control Register (SYSPLLCTRL)
+// F_clkout = M * F_clkin = F_CCO / (2 * P)
+// F_clkin must be in the range of 10 MHz to 25 MHz
+// F_CCO must be in the range of 156 MHz to 320 MHz
+// MSEL: Feedback Divider Selection
+// M = MSEL + 1
+// <0-31>
+// PSEL: Post Divider Selection
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+//
+#define SYSPLLCTRL_Val 0x00000024 // Reset: 0x000
+//
+// System PLL Clock Source Select Register (SYSPLLCLKSEL)
+// SEL: System PLL Clock Source
+// <0=> IRC
+// <1=> Crystal Oscillator
+// <2=> Reserved
+// <3=> CLKIN. External clock input.
+//
+#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000
+//
+// Main Clock Source Select Register (MAINCLKSEL)
+// SEL: Clock Source for Main Clock
+// <0=> IRC Oscillator
+// <1=> PLL input
+// <2=> Watchdog Oscillator
+// <3=> PLL output
+//
+#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
+// System AHB Clock Divider Register (SYSAHBCLKDIV)
+// DIV: System AHB Clock Divider
+// Divides main clock to provide system clock to core, memories, and peripherals.
+// 0 = is disabled
+// <0-255>
+//
+#define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001
+//
+
+//#define CLOCK_SETUP 0 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal:
+
+/*
+#if (CLOCK_SETUP == 0)
+ #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+ #define WDTOSCCTRL_Val 0x00000024 // Reset: 0x000
+ #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000
+ #define SYSPLLCLKSEL_Val 0x00000003 // Reset: 0x000
+ #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000
+ #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
+#elif (CLOCK_SETUP == 2)
+// #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+ #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
+ #define SYSPLLCTRL_Val 0x00000040 // Reset: 0x000
+ #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
+ #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
+ #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
+#endif
+*/
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
+ #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
+ #error "WDTOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
+ #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
+ #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
+ #error "MAINCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+ #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL (12000000UL) /* Oscillator frequency */
+#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
+#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
+#define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */
+
+
+#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
+#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
+
+#if (CLOCK_SETUP) /* Clock Setup */
+ #if (__FREQSEL == 0)
+ #define __WDT_OSC_CLK ( 0) /* undefined */
+ #elif (__FREQSEL == 1)
+ #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
+ #elif (__FREQSEL == 2)
+ #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
+ #elif (__FREQSEL == 3)
+ #define __WDT_OSC_CLK (1100000 / __DIVSEL)
+ #elif (__FREQSEL == 4)
+ #define __WDT_OSC_CLK (1400000 / __DIVSEL)
+ #elif (__FREQSEL == 5)
+ #define __WDT_OSC_CLK (1600000 / __DIVSEL)
+ #elif (__FREQSEL == 6)
+ #define __WDT_OSC_CLK (1800000 / __DIVSEL)
+ #elif (__FREQSEL == 7)
+ #define __WDT_OSC_CLK (2000000 / __DIVSEL)
+ #elif (__FREQSEL == 8)
+ #define __WDT_OSC_CLK (2200000 / __DIVSEL)
+ #elif (__FREQSEL == 9)
+ #define __WDT_OSC_CLK (2400000 / __DIVSEL)
+ #elif (__FREQSEL == 10)
+ #define __WDT_OSC_CLK (2600000 / __DIVSEL)
+ #elif (__FREQSEL == 11)
+ #define __WDT_OSC_CLK (2700000 / __DIVSEL)
+ #elif (__FREQSEL == 12)
+ #define __WDT_OSC_CLK (2900000 / __DIVSEL)
+ #elif (__FREQSEL == 13)
+ #define __WDT_OSC_CLK (3100000 / __DIVSEL)
+ #elif (__FREQSEL == 14)
+ #define __WDT_OSC_CLK (3200000 / __DIVSEL)
+ #else
+ #define __WDT_OSC_CLK (3400000 / __DIVSEL)
+ #endif
+
+ /* sys_pllclkin calculation */
+ #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
+ #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ #define __SYS_PLLCLKIN (__CLKIN_CLK)
+ #else
+ #define __SYS_PLLCLKIN (0)
+ #endif
+
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+
+ /* main clock calculation */
+ #if ((MAINCLKSEL_Val & 0x03) == 0)
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)
+ #elif ((MAINCLKSEL_Val & 0x03) == 1)
+ #define __MAIN_CLOCK (__SYS_PLLCLKIN)
+ #elif ((MAINCLKSEL_Val & 0x03) == 2)
+ #if (__FREQSEL == 0)
+ #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
+ #else
+ #define __MAIN_CLOCK (__WDT_OSC_CLK)
+ #endif
+ #elif ((MAINCLKSEL_Val & 0x03) == 3)
+ #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
+ #else
+ #define __MAIN_CLOCK (0)
+ #endif
+
+ #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
+
+#else
+ #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
+#endif // CLOCK_SETUP
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
+uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ uint32_t wdt_osc = 0;
+
+ /* Determine clock frequency according to clock register values */
+ switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
+ case 0: wdt_osc = 0; break;
+ case 1: wdt_osc = 500000; break;
+ case 2: wdt_osc = 800000; break;
+ case 3: wdt_osc = 1100000; break;
+ case 4: wdt_osc = 1400000; break;
+ case 5: wdt_osc = 1600000; break;
+ case 6: wdt_osc = 1800000; break;
+ case 7: wdt_osc = 2000000; break;
+ case 8: wdt_osc = 2200000; break;
+ case 9: wdt_osc = 2400000; break;
+ case 10: wdt_osc = 2600000; break;
+ case 11: wdt_osc = 2700000; break;
+ case 12: wdt_osc = 2900000; break;
+ case 13: wdt_osc = 3100000; break;
+ case 14: wdt_osc = 3200000; break;
+ case 15: wdt_osc = 3400000; break;
+ }
+ wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
+
+ switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* Input Clock to System PLL */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK;
+ break;
+ case 2: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ case 3: /* CLKIN pin */
+ SystemCoreClock = __CLKIN_CLK;
+ break;
+ }
+ break;
+ case 2: /* WDT Oscillator */
+ SystemCoreClock = wdt_osc;
+ break;
+ case 3: /* System PLL Clock Out */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 2: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ case 3: /* CLKIN pin */
+ SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ }
+ break;
+ }
+
+ SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void) {
+ volatile uint32_t i;
+
+ /* System clock to the IOCON & the SWM need to be enabled or
+ most of the I/O related peripherals won't work. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
+
+#if (CLOCK_SETUP) /* Clock Setup */
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
+ LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
+ LPC_SWM->PINENABLE0 &= ~(0x3 << 6); /* XTALIN and XTALOUT */
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */
+ for (i = 0; i < 200; i++) __NOP();
+ LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
+#endif
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
+ LPC_SWM->PINENABLE0 &= ~(0x1 << 9); /* CLKIN */
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up System PLL */
+ LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->SYSPLLCLKUEN = 0;
+ LPC_SYSCON->SYSPLLCLKUEN = 1; /* Update Clock Source */
+ while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
+
+#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */
+ while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+#endif
+
+#if (((MAINCLKSEL_Val & 0x03) == 2) )
+ LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
+ LPC_SYSCON->MAINCLKUEN = 0;
+ LPC_SYSCON->MAINCLKUEN = 1; /* Update MCLK Clock Source */
+ while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
+#endif
+}
diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 0000000000..2f1024ace8
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+#include
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis.h
new file mode 100644
index 0000000000..dc68e39335
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC8xx specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "LPC82x.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.c
new file mode 100644
index 0000000000..6b8912505b
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.c
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.h
new file mode 100644
index 0000000000..6acdca9efd
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.h
@@ -0,0 +1,26 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/system_LPC82x.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/system_LPC82x.h
new file mode 100644
index 0000000000..a80f832909
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/system_LPC82x.h
@@ -0,0 +1,63 @@
+/******************************************************************************
+ * @file: system_LPC8xx.h
+ * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File
+ * for the NXP LPC8xx Device Series
+ * @version: V1.0
+ * @date: 16. Aug. 2012
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC8xx_H
+#define __SYSTEM_LPC8xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+extern uint32_t MainClock; /*!< Main Clock Frequency */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC8xx_H */
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/PortNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/PortNames.h
new file mode 100644
index 0000000000..bbd5b31103
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/PortNames.h
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ Port0 = 0,
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PeripheralNames.h
new file mode 100644
index 0000000000..2d39ea9959
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PeripheralNames.h
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Default peripherals
+
+// SPI: MOSI, MISO, CLK, SEL
+#define MBED_SPI0 P0_26, P0_25, P0_24, P0_15
+
+#define MBED_UART0 P0_7, P0_18
+#define MBED_UARTUSB USBTX, USBRX
+
+#define MBED_I2C0 P0_10, P0_11
+
+typedef enum {
+ ADC_0 = 0,
+ ADC_1,
+ ADC_2,
+ ADC_3,
+ ADC_4,
+ ADC_5,
+ ADC_6,
+ ADC_7,
+ ADC_8,
+ ADC_9,
+ ADC_10,
+ ADC_11,
+} ADCName;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PinNames.h
new file mode 100644
index 0000000000..4aa2995ffe
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PinNames.h
@@ -0,0 +1,135 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PIN_SHIFT 8
+
+typedef enum {
+// LPC824 Pin Names (PIN[11:8] + IOCON offset[7:0])
+
+ P0_0 = ( 0 << PIN_SHIFT) | 0x44,
+ P0_1 = ( 1 << PIN_SHIFT) | 0x2C,
+ P0_2 = ( 2 << PIN_SHIFT) | 0x18,
+ P0_3 = ( 3 << PIN_SHIFT) | 0x14,
+ P0_4 = ( 4 << PIN_SHIFT) | 0x10,
+ P0_5 = ( 5 << PIN_SHIFT) | 0x0C,
+ P0_6 = ( 6 << PIN_SHIFT) | 0x40,
+ P0_7 = ( 7 << PIN_SHIFT) | 0x3C,
+ P0_8 = ( 8 << PIN_SHIFT) | 0x38,
+ P0_9 = ( 9 << PIN_SHIFT) | 0x34,
+ P0_10 = (10 << PIN_SHIFT) | 0x20,
+ P0_11 = (11 << PIN_SHIFT) | 0x1C,
+ P0_12 = (12 << PIN_SHIFT) | 0x08,
+ P0_13 = (13 << PIN_SHIFT) | 0x04,
+ P0_14 = (14 << PIN_SHIFT) | 0x48,
+ P0_15 = (15 << PIN_SHIFT) | 0x28,
+ P0_16 = (16 << PIN_SHIFT) | 0x24,
+ P0_17 = (17 << PIN_SHIFT) | 0x00,
+ P0_18 = (18 << PIN_SHIFT) | 0x78,
+ P0_19 = (19 << PIN_SHIFT) | 0x74,
+ P0_20 = (20 << PIN_SHIFT) | 0x70,
+ P0_21 = (21 << PIN_SHIFT) | 0x6C,
+ P0_22 = (22 << PIN_SHIFT) | 0x68,
+ P0_23 = (23 << PIN_SHIFT) | 0x64,
+ P0_24 = (24 << PIN_SHIFT) | 0x60,
+ P0_25 = (25 << PIN_SHIFT) | 0x5C,
+ P0_26 = (26 << PIN_SHIFT) | 0x58,
+ P0_27 = (27 << PIN_SHIFT) | 0x54,
+ P0_28 = (28 << PIN_SHIFT) | 0x50,
+
+ D0 = P0_0,
+ D1 = P0_4,
+ D2 = P0_19,
+ D3 = P0_12, // LED_RED
+ D4 = P0_18,
+ D5 = P0_28,
+ D6 = P0_16, // LED_GREEN
+ D7 = P0_17,
+ D8 = P0_13,
+ D9 = P0_27, // LED_BLUE
+ D10 = P0_15,
+ D11 = P0_26,
+ D12 = P0_25,
+ D13 = P0_24,
+ D14 = P0_11,
+ D15 = P0_10,
+
+ A0 = P0_6,
+ A1 = P0_14,
+ A2 = P0_23,
+ A3 = P0_22,
+ A4 = P0_21,
+ A5 = P0_20,
+
+ // LPC824-MAX board
+ LED_RED = P0_12,
+ LED_GREEN = P0_16,
+ LED_BLUE = P0_27,
+
+ // mbed original LED naming
+ LED1 = LED_RED,
+ LED2 = LED_GREEN,
+ LED3 = LED_BLUE,
+ LED4 = LED_BLUE,
+
+ // Serial to USB pins
+ USBTX = P0_7,
+ USBRX = P0_18,
+
+ // I2C pins
+ SDA = P0_10,
+ SCL = P0_11,
+ I2C_SDA = P0_10,
+ I2C_SCL = P0_11,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+} PinName;
+
+typedef enum {
+ PullUp = 2,
+ PullDown = 1,
+ PullNone = 0,
+ Repeater = 3,
+ OpenDrain = 4,
+ PullDefault = PullDown
+} PinMode;
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+
+typedef struct {
+ unsigned char n;
+ unsigned char offset;
+} SWM_Map;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device.h
new file mode 100644
index 0000000000..be5981dc85
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device.h
@@ -0,0 +1,58 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN 0
+#define DEVICE_PORTOUT 0
+#define DEVICE_PORTINOUT 0
+
+#define DEVICE_INTERRUPTIN 1
+
+#define DEVICE_ANALOGIN 1
+#define DEVICE_ANALOGOUT 0
+
+#define DEVICE_SERIAL 1
+#define DEVICE_SERIAL_FC 0
+
+#define DEVICE_I2C 1
+#define DEVICE_I2CSLAVE 0
+
+#define DEVICE_SPI 1
+#define DEVICE_SPISLAVE 1
+
+#define DEVICE_CAN 0
+
+#define DEVICE_RTC 0
+
+#define DEVICE_ETHERNET 0
+
+#define DEVICE_PWMOUT 1
+
+#define DEVICE_SEMIHOST 0
+#define DEVICE_LOCALFILESYSTEM 0
+
+#define DEVICE_SLEEP 1
+
+#define DEVICE_DEBUG_AWARENESS 0
+
+#define DEVICE_STDIO_MESSAGES 0
+
+#define DEVICE_ERROR_RED 1
+
+#include "objects.h"
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/analogin_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/analogin_api.c
new file mode 100644
index 0000000000..786be8ba06
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/analogin_api.c
@@ -0,0 +1,131 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralNames.h"
+
+#if DEVICE_ANALOGIN
+
+#define ANALOGIN_MEDIAN_FILTER 1
+
+#define ADC_RANGE 0xFFF
+
+static const PinMap PinMap_ADC[] = {
+ {P0_7 , ADC_0, 0},
+ {P0_6 , ADC_1, 0},
+ {P0_14, ADC_2, 0},
+ {P0_23, ADC_3, 0},
+ {P0_22, ADC_4, 0},
+ {P0_21, ADC_5, 0},
+ {P0_20, ADC_6, 0},
+ {P0_19, ADC_7, 0},
+ {P0_18, ADC_8, 0},
+ {P0_17, ADC_9, 0},
+ {P0_13, ADC_10,0},
+ {P0_4 , ADC_11,0},
+};
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+ obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+ MBED_ASSERT(obj->adc != (ADCName)NC);
+
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1UL << 6);
+ // pin enable
+ LPC_SWM->PINENABLE0 &= ~(1UL << (13 + obj->adc));
+ // configure GPIO as input
+ LPC_GPIO_PORT->DIR0 &= ~(1UL << (pin >> PIN_SHIFT));
+
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 4);
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 24);
+
+ __IO LPC_ADC_Type *adc_reg = LPC_ADC;
+
+ // determine the system clock divider for a 500kHz ADC clock during calibration
+ uint32_t clkdiv = (SystemCoreClock / 500000) - 1;
+
+ // perform a self-calibration
+ adc_reg->CTRL = (1UL << 30) | (clkdiv & 0xFF);
+ while ((adc_reg->CTRL & (1UL << 30)) != 0);
+}
+
+static inline uint32_t adc_read(analogin_t *obj)
+{
+ uint32_t channels;
+ __IO LPC_ADC_Type *adc_reg = LPC_ADC;
+
+ channels = (obj->adc & 0x1F);
+
+ // select channel
+ adc_reg->SEQA_CTRL &= ~(0xFFF);
+ adc_reg->SEQA_CTRL |= (1UL << channels);
+
+ // start conversion and sequence enable
+ adc_reg->SEQA_CTRL |= ((1UL << 26) | (1UL << 31));
+
+ // Repeatedly get the sample data until DONE bit
+ volatile uint32_t data;
+ do {
+ data = adc_reg->SEQA_GDAT;
+ } while ((data & (1UL << 31)) == 0);
+
+ // Stop conversion
+ adc_reg->SEQA_CTRL &= ~(1UL << 31);
+
+ return ((data >> 4) & ADC_RANGE);
+}
+
+static inline void order(uint32_t *a, uint32_t *b)
+{
+ if (*a > *b) {
+ uint32_t t = *a;
+ *a = *b;
+ *b = t;
+ }
+}
+
+static inline uint32_t adc_read_u32(analogin_t *obj)
+{
+ uint32_t value;
+#if ANALOGIN_MEDIAN_FILTER
+ uint32_t v1 = adc_read(obj);
+ uint32_t v2 = adc_read(obj);
+ uint32_t v3 = adc_read(obj);
+ order(&v1, &v2);
+ order(&v2, &v3);
+ order(&v1, &v2);
+ value = v2;
+#else
+ value = adc_read(obj);
+#endif
+ return value;
+}
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+ uint32_t value = adc_read_u32(obj);
+ return (value << 4) | ((value >> 8) & 0x000F); // 12 bit
+}
+
+float analogin_read(analogin_t *obj)
+{
+ uint32_t value = adc_read_u32(obj);
+ return (float)value * (1.0f / (float)ADC_RANGE);
+}
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_api.c
new file mode 100644
index 0000000000..8eb2a2b2f4
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_api.c
@@ -0,0 +1,72 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "gpio_api.h"
+#include "pinmap.h"
+
+static int gpio_enabled = 0;
+
+static void gpio_enable(void)
+{
+ gpio_enabled = 1;
+
+ /* Enable AHB clock to the GPIO domain. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 6);
+
+ /* Peripheral reset control to GPIO and GPIO INT, a "1" bring it out of reset. */
+ LPC_SYSCON->PRESETCTRL &= ~(1 << 10);
+ LPC_SYSCON->PRESETCTRL |= (1 << 10);
+}
+
+uint32_t gpio_set(PinName pin)
+{
+ if (!gpio_enabled)
+ gpio_enable();
+
+ return (1 << ((int)pin >> PIN_SHIFT));
+}
+
+void gpio_init(gpio_t *obj, PinName pin)
+{
+ obj->pin = pin;
+ if (pin == (PinName)NC)
+ return;
+
+ obj->mask = gpio_set(pin);
+
+ obj->reg_set = &LPC_GPIO_PORT->SET0;
+ obj->reg_clr = &LPC_GPIO_PORT->CLR0;
+ obj->reg_in = &LPC_GPIO_PORT->PIN0;
+ obj->reg_dir = &LPC_GPIO_PORT->DIR0;
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+ pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ switch (direction) {
+ case PIN_INPUT :
+ *obj->reg_dir &= ~obj->mask;
+ break;
+ case PIN_OUTPUT:
+ *obj->reg_dir |= obj->mask;
+ break;
+ }
+}
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_irq_api.c
new file mode 100644
index 0000000000..a8f7ab4cd8
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_irq_api.c
@@ -0,0 +1,145 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include
+
+#include "cmsis.h"
+#include "gpio_irq_api.h"
+#include "mbed_error.h"
+
+#if DEVICE_INTERRUPTIN
+
+#define CHANNEL_NUM 8
+#define LPC_GPIO_X LPC_PIN_INT
+#define PININT_IRQ PIN_INT0_IRQn
+
+static uint32_t channel_ids[CHANNEL_NUM] = {0};
+static gpio_irq_handler irq_handler;
+
+static inline void handle_interrupt_in(uint32_t channel)
+{
+ uint32_t ch_bit = (1 << channel);
+ // Return immediately if:
+ // * The interrupt was already served
+ // * There is no user handler
+ // * It is a level interrupt, not an edge interrupt
+ if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
+ (channel_ids[channel] == 0 ) ||
+ (LPC_GPIO_X->ISEL & ch_bit ) ) return;
+
+ if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
+ irq_handler(channel_ids[channel], IRQ_RISE);
+ LPC_GPIO_X->RISE = ch_bit;
+ }
+ if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
+ irq_handler(channel_ids[channel], IRQ_FALL);
+ }
+ LPC_GPIO_X->IST = ch_bit;
+}
+
+void gpio_irq0(void) {handle_interrupt_in(0);}
+void gpio_irq1(void) {handle_interrupt_in(1);}
+void gpio_irq2(void) {handle_interrupt_in(2);}
+void gpio_irq3(void) {handle_interrupt_in(3);}
+void gpio_irq4(void) {handle_interrupt_in(4);}
+void gpio_irq5(void) {handle_interrupt_in(5);}
+void gpio_irq6(void) {handle_interrupt_in(6);}
+void gpio_irq7(void) {handle_interrupt_in(7);}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
+ if (pin == NC) return -1;
+
+ irq_handler = handler;
+
+ int found_free_channel = 0;
+ int i = 0;
+ for (i=0; ich = i;
+ found_free_channel = 1;
+ break;
+ }
+ }
+ if (!found_free_channel) return -1;
+
+ /* Enable AHB clock to the GPIO domain. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
+
+ LPC_SYSCON->PINTSEL[obj->ch] = (pin >> PIN_SHIFT);
+
+ // Interrupt Wake-Up Enable
+ LPC_SYSCON->STARTERP0 |= 1 << obj->ch;
+
+ void (*channels_irq)(void) = NULL;
+ switch (obj->ch) {
+ case 0: channels_irq = &gpio_irq0; break;
+ case 1: channels_irq = &gpio_irq1; break;
+ case 2: channels_irq = &gpio_irq2; break;
+ case 3: channels_irq = &gpio_irq3; break;
+ case 4: channels_irq = &gpio_irq4; break;
+ case 5: channels_irq = &gpio_irq5; break;
+ case 6: channels_irq = &gpio_irq6; break;
+ case 7: channels_irq = &gpio_irq7; break;
+ }
+ NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
+ NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+
+ return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj)
+{
+ channel_ids[obj->ch] = 0;
+ LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+ unsigned int ch_bit = (1 << obj->ch);
+
+ // Clear interrupt
+ if (!(LPC_GPIO_X->ISEL & ch_bit))
+ LPC_GPIO_X->IST = ch_bit;
+
+ // Edge trigger
+ LPC_GPIO_X->ISEL &= ~ch_bit;
+ if (event == IRQ_RISE) {
+ if (enable) {
+ LPC_GPIO_X->IENR |= ch_bit;
+ } else {
+ LPC_GPIO_X->IENR &= ~ch_bit;
+ }
+ } else {
+ if (enable) {
+ LPC_GPIO_X->IENF |= ch_bit;
+ } else {
+ LPC_GPIO_X->IENF &= ~ch_bit;
+ }
+ }
+}
+
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+ NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+}
+
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+ NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+}
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_object.h
new file mode 100644
index 0000000000..75d9291620
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_object.h
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_set;
+ __IO uint32_t *reg_clr;
+ __I uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ if (value)
+ *obj->reg_set = obj->mask;
+ else
+ *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/i2c_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/i2c_api.c
new file mode 100644
index 0000000000..f6cecf01c6
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/i2c_api.c
@@ -0,0 +1,358 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include
+#include
+
+#include "i2c_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+
+#include "rom_i2c_8xx.h"
+
+#if DEVICE_I2C
+
+typedef struct ROM_API {
+ const uint32_t unused[5];
+ const I2CD_API_T *pI2CD; /*!< I2C driver routines functions table */
+} LPC_ROM_API_T;
+
+
+/* Pointer to ROM API function address */
+#define LPC_ROM_API_BASE_LOC 0x1FFF1FF8UL
+#define LPC_ROM_API (*(LPC_ROM_API_T * *) LPC_ROM_API_BASE_LOC)
+
+/* Pointer to @ref I2CD_API_T functions in ROM */
+#define LPC_I2CD_API ((LPC_ROM_API)->pI2CD)
+
+static const SWM_Map SWM_I2C_SDA[] = {
+ { 9, 8},
+ { 9, 24},
+ {10, 8},
+};
+
+static const SWM_Map SWM_I2C_SCL[] = {
+ { 9, 16},
+ {10, 0},
+ {10, 16},
+};
+
+
+static int i2c_used = 0;
+static uint8_t repeated_start = 0;
+static uint32_t *i2c_buffer;
+
+#define I2C_DAT(x) (x->i2c->MSTDAT)
+#define I2C_STAT(x) ((x->i2c->STAT >> 1) & (0x07))
+
+static inline int i2c_status(i2c_t *obj)
+{
+ return I2C_STAT(obj);
+}
+
+// Wait until the Serial Interrupt (SI) is set
+static int i2c_wait_SI(i2c_t *obj)
+{
+ volatile int timeout = 0;
+ while (!(obj->i2c->STAT & (1 << 0))) {
+ timeout++;
+ if (timeout > 100000) return -1;
+ }
+ return 0;
+}
+
+static inline void i2c_interface_enable(i2c_t *obj)
+{
+ obj->i2c->CFG |= 1;
+}
+
+static inline void i2c_power_enable(int ch)
+{
+ switch(ch) {
+ case 0:
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 5);
+ LPC_SYSCON->PRESETCTRL &= ~(1 << 6);
+ LPC_SYSCON->PRESETCTRL |= (1 << 6);
+ break;
+ case 1:
+ case 2:
+ case 3:
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (20 + ch));
+ LPC_SYSCON->PRESETCTRL &= ~(1 << (13 + ch));
+ LPC_SYSCON->PRESETCTRL |= (1 << (13 + ch));
+ break;
+ default:
+ break;
+ }
+}
+
+
+static int get_available_i2c(void) {
+ int i;
+ for (i=0; i<3; i++) {
+ if ((i2c_used & (1 << i)) == 0)
+ return i+1;
+ }
+ return -1;
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
+ const SWM_Map *swm;
+ uint32_t regVal;
+ int i2c_ch = 0;
+
+ if (sda == I2C_SDA && scl == I2C_SCL) {
+ LPC_SWM->PINENABLE0 &= ~(0x3 << 11);
+ }
+ else {
+ i2c_ch = get_available_i2c();
+ if (i2c_ch == -1)
+ return;
+
+ swm = &SWM_I2C_SDA[i2c_ch - 1];
+ regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+ LPC_SWM->PINASSIGN[swm->n] = regVal | ((sda >> PIN_SHIFT) << swm->offset);
+
+ swm = &SWM_I2C_SCL[i2c_ch - 1];
+ regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+ LPC_SWM->PINASSIGN[swm->n] = regVal | ((scl >> PIN_SHIFT) << swm->offset);
+ }
+
+ switch(i2c_ch) {
+ case 0:
+ obj->i2c = (LPC_I2C0_Type *)LPC_I2C0;
+ break;
+ case 1:
+ obj->i2c = (LPC_I2C0_Type *)LPC_I2C1;
+ break;
+ case 2:
+ obj->i2c = (LPC_I2C0_Type *)LPC_I2C2;
+ break;
+ case 3:
+ obj->i2c = (LPC_I2C0_Type *)LPC_I2C3;
+ break;
+ default:
+ break;
+ }
+
+ // enable power
+ i2c_power_enable(i2c_ch);
+ i2c_interface_enable(obj);
+
+ uint32_t size_in_bytes = LPC_I2CD_API->i2c_get_mem_size();
+ i2c_buffer = malloc(size_in_bytes);
+ obj->handler = LPC_I2CD_API->i2c_setup((uint32_t)(obj->i2c), i2c_buffer);
+ LPC_I2CD_API->i2c_set_bitrate(obj->handler, SystemCoreClock, 100000);
+ LPC_I2CD_API->i2c_set_timeout(obj->handler, 100000);
+}
+
+inline int i2c_start(i2c_t *obj)
+{
+ int status = 0;
+ if (repeated_start) {
+ obj->i2c->MSTCTL = (1 << 1) | (1 << 0);
+ repeated_start = 0;
+ } else {
+ obj->i2c->MSTCTL = (1 << 1);
+ }
+ return status;
+}
+
+inline int i2c_stop(i2c_t *obj)
+{
+ volatile int timeout = 0;
+
+ obj->i2c->MSTCTL = (1 << 2) | (1 << 0);
+ while ((obj->i2c->STAT & ((1 << 0) | (7 << 1))) != ((1 << 0) | (0 << 1))) {
+ timeout ++;
+ if (timeout > 100000) return 1;
+ }
+
+ return 0;
+}
+
+static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr)
+{
+ // write the data
+ I2C_DAT(obj) = value;
+
+ if (!addr)
+ obj->i2c->MSTCTL = (1 << 0);
+
+ // wait and return status
+ i2c_wait_SI(obj);
+ return i2c_status(obj);
+}
+
+static inline int i2c_do_read(i2c_t *obj, int last)
+{
+ // wait for it to arrive
+ i2c_wait_SI(obj);
+ if (!last)
+ obj->i2c->MSTCTL = (1 << 0);
+
+ // return the data
+ return (I2C_DAT(obj) & 0xFF);
+}
+
+void i2c_frequency(i2c_t *obj, int hz)
+{
+ LPC_I2CD_API->i2c_set_bitrate(obj->handler, SystemCoreClock, 100000);
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+ ErrorCode_t err;
+ I2C_PARAM_T i2c_param;
+ I2C_RESULT_T i2c_result;
+
+ uint8_t *buf = malloc(length + 1);
+ buf[0] = (uint8_t)((address | 0x01) & 0xFF);
+ i2c_param.buffer_ptr_rec = buf;
+ i2c_param.num_bytes_rec = length + 1;
+ i2c_param.stop_flag = stop;
+ err = LPC_I2CD_API->i2c_master_receive_poll(obj->handler, &i2c_param, &i2c_result);
+ memcpy(data, buf + 1, i2c_result.n_bytes_recd);
+ free(buf);
+ if (err == 0)
+ return i2c_result.n_bytes_recd;
+ else
+ return -1;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
+ ErrorCode_t err;
+ I2C_PARAM_T i2c_param;
+ I2C_RESULT_T i2c_result;
+
+ uint8_t *buf = malloc(length + 1);
+ buf[0] = (uint8_t)(address & 0xFE);
+ memcpy(buf + 1, data, length);
+ i2c_param.buffer_ptr_send = buf;
+ i2c_param.num_bytes_send = length + 1;
+ i2c_param.stop_flag = stop;
+ err = LPC_I2CD_API->i2c_master_transmit_poll(obj->handler, &i2c_param, &i2c_result);
+ free(buf);
+ if (err == 0)
+ return i2c_result.n_bytes_sent;
+ else
+ return -1;
+}
+
+void i2c_reset(i2c_t *obj)
+{
+ i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last)
+{
+ return (i2c_do_read(obj, last) & 0xFF);
+}
+
+int i2c_byte_write(i2c_t *obj, int data)
+{
+ int ack;
+ int status = i2c_do_write(obj, (data & 0xFF), 0);
+
+ switch(status) {
+ case 2:
+ ack = 1;
+ break;
+ default:
+ ack = 0;
+ break;
+ }
+
+ return ack;
+}
+
+#if DEVICE_I2CSLAVE
+
+ void i2c_slave_mode(i2c_t *obj, int enable_slave)
+{
+ obj->handler = LPC_I2CD_API->i2c_setup((uint32_t)(obj->i2c), i2c_buffer);
+ if (enable_slave != 0) {
+ obj->i2c->CFG &= ~(1 << 0);
+ obj->i2c->CFG |= (1 << 1);
+ }
+ else {
+ obj->i2c->CFG |= (1 << 0);
+ obj->i2c->CFG &= ~(1 << 1);
+ }
+
+}
+
+int i2c_slave_receive(i2c_t *obj)
+{
+ CHIP_I2C_MODE_T mode;
+ int ret;
+
+ mode = LPC_I2CD_API->i2c_get_status(obj->handler);
+ switch(mode) {
+ case SLAVE_SEND:
+ ret = 1;
+ break;
+ case SLAVE_RECEIVE:
+ ret = 3;
+ break;
+ case MASTER_SEND:
+ case MASTER_RECEIVE:
+ default:
+ ret = 0;
+ break;
+ }
+ return ret;
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length)
+{
+ ErrorCode_t err;
+ I2C_PARAM_T i2c_param;
+ I2C_RESULT_T i2c_result;
+
+ i2c_param.buffer_ptr_send = (uint8_t *)data;
+ i2c_param.num_bytes_send = length;
+ err = LPC_I2CD_API->i2c_slave_transmit_poll(obj->handler, &i2c_param, &i2c_result);
+ if (err == 0)
+ return i2c_result.n_bytes_sent;
+ else
+ return -1;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length)
+{
+ ErrorCode_t err;
+ I2C_PARAM_T i2c_param;
+ I2C_RESULT_T i2c_result;
+
+ i2c_param.buffer_ptr_rec = (uint8_t *)data;
+ i2c_param.num_bytes_rec = length;
+ err = LPC_I2CD_API->i2c_slave_receive_poll(obj->handler, &i2c_param, &i2c_result);
+ if (err == 0)
+ return i2c_result.n_bytes_recd;
+ else
+ return -1;
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
+{
+ LPC_I2CD_API->i2c_set_slave_addr(obj->handler, address, 0);
+}
+
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/objects.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/objects.h
new file mode 100644
index 0000000000..2454b4dc10
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/objects.h
@@ -0,0 +1,62 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ uint32_t ch;
+};
+
+struct serial_s {
+ LPC_USART0_Type *uart;
+ unsigned char index;
+};
+
+struct i2c_s {
+ LPC_I2C0_Type *i2c;
+ void *handler;
+};
+
+struct spi_s {
+ LPC_SPI0_Type *spi;
+ unsigned char spi_n;
+};
+
+struct analogin_s {
+ ADCName adc;
+};
+
+struct pwmout_s {
+ LPC_SCT_Type* pwm;
+ uint32_t pwm_ch;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pinmap.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pinmap.c
new file mode 100644
index 0000000000..41b2144d8e
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pinmap.c
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+
+void pin_function(PinName pin, int function)
+{
+ // do nothing
+ return;
+}
+
+void pin_mode(PinName pin, PinMode mode)
+{
+ MBED_ASSERT(pin != (PinName)NC);
+
+ if ((pin == P0_10) || (pin == P0_11)) {
+ // True open-drain pins can be configured for different I2C-bus speeds
+ return;
+ }
+
+ __IO uint32_t *reg = (uint32_t *)(LPC_IOCON_BASE + (pin & 0xFF));
+
+ if (mode == OpenDrain) {
+ *reg |= (1 << 10);
+ } else {
+ uint32_t tmp = *reg;
+ tmp &= ~(0x3 << 3);
+ tmp |= (mode & 0x3) << 3;
+ *reg = tmp;
+ }
+}
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c
new file mode 100644
index 0000000000..dcfd96656c
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c
@@ -0,0 +1,173 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "pwmout_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+#if DEVICE_PWMOUT
+
+// bit flags for used SCTs
+static unsigned char sct_used = 0;
+
+static int get_available_sct()
+{
+ int i;
+ for (i = 0; i < 4; i++) {
+ if ((sct_used & (1 << i)) == 0)
+ return i;
+ }
+ return -1;
+}
+
+void pwmout_init(pwmout_t* obj, PinName pin)
+{
+ MBED_ASSERT(pin != (uint32_t)NC);
+
+ int sct_n = get_available_sct();
+ if (sct_n == -1) {
+ error("No available SCT");
+ }
+
+ sct_used |= (1 << sct_n);
+
+ obj->pwm = (LPC_SCT_Type*)LPC_SCT;
+ obj->pwm_ch = sct_n;
+
+ LPC_SCT_Type* pwm = obj->pwm;
+
+ // Enable the SCT clock
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8);
+
+ // Clear peripheral reset the SCT:
+ LPC_SYSCON->PRESETCTRL |= (1 << 8);
+
+ switch(sct_n) {
+ case 0:
+ // SCT_OUT0
+ LPC_SWM->PINASSIGN[7] &= ~0xFF000000;
+ LPC_SWM->PINASSIGN[7] |= ((pin >> PIN_SHIFT) << 24);
+ break;
+ case 1:
+ // SCT_OUT1
+ LPC_SWM->PINASSIGN[8] &= ~0x000000FF;
+ LPC_SWM->PINASSIGN[8] |= (pin >> PIN_SHIFT);
+ break;
+ case 2:
+ // SCT2_OUT2
+ LPC_SWM->PINASSIGN[8] &= ~0x0000FF00;
+ LPC_SWM->PINASSIGN[8] |= ((pin >> PIN_SHIFT) << 8);
+ break;
+ case 3:
+ // SCT3_OUT3
+ LPC_SWM->PINASSIGN[8] &= ~0x00FF0000;
+ LPC_SWM->PINASSIGN[8] |= ((pin >> PIN_SHIFT) << 16);
+ break;
+ default:
+ break;
+ }
+
+ // Two 16-bit counters, autolimit
+ pwm->CONFIG &= ~(0x1);
+ pwm->CONFIG |= (1 << 17);
+
+ // halt and clear the counter
+ pwm->CTRL |= (1 << 2) | (1 << 3);
+
+ // System Clock -> us_ticker (1)MHz
+ pwm->CTRL &= ~(0x7F << 5);
+ pwm->CTRL |= (((SystemCoreClock/1000000 - 1) & 0x7F) << 5);
+
+ pwm->OUT[sct_n].SET = (1 << ((sct_n * 2) + 0));
+ pwm->OUT[sct_n].CLR = (1 << ((sct_n * 2) + 1));
+
+ pwm->EVENT[(sct_n * 2) + 0].CTRL = (1 << 12) | ((sct_n * 2) + 0); // match event
+ pwm->EVENT[(sct_n * 2) + 0].STATE = 0xFFFFFFFF;
+ pwm->EVENT[(sct_n * 2) + 1].CTRL = (1 << 12) | ((sct_n * 2) + 1);
+ pwm->EVENT[(sct_n * 2) + 1].STATE = 0xFFFFFFFF;
+
+ // unhalt the counter:
+ // - clearing bit 2 of the CTRL register
+ pwm->CTRL &= ~(1 << 2);
+
+ // default to 20ms: standard for servos, and fine for e.g. brightness control
+ pwmout_period_ms(obj, 20);
+ pwmout_write (obj, 0);
+}
+
+void pwmout_free(pwmout_t* obj)
+{
+ // Disable the SCT clock
+ LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8);
+ sct_used &= ~(1 << obj->pwm_ch);
+}
+
+void pwmout_write(pwmout_t* obj, float value)
+{
+ if (value < 0.0f) {
+ value = 0.0;
+ } else if (value > 1.0f) {
+ value = 1.0;
+ }
+ uint32_t t_on = (uint32_t)((float)(obj->pwm->MATCHREL[obj->pwm_ch * 2]) * value);
+ obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = t_on;
+}
+
+float pwmout_read(pwmout_t* obj)
+{
+ uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0];
+ uint32_t t_on = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1];
+ float v = (float)t_on/(float)t_off;
+ return (v > 1.0f) ? (1.0f) : (v);
+}
+
+void pwmout_period(pwmout_t* obj, float seconds)
+{
+ pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms)
+{
+ pwmout_period_us(obj, ms * 1000);
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t* obj, int us)
+{
+ uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0];
+ uint32_t t_on = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1];
+ float v = (float)t_on/(float)t_off;
+ obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0] = (uint64_t)us;
+ obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = (uint64_t)((float)us * (float)v);
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds)
+{
+ pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
+{
+ pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us)
+{
+ obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = (uint64_t)us;
+}
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/rom_i2c_8xx.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/rom_i2c_8xx.h
new file mode 100644
index 0000000000..8969a6dd56
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/rom_i2c_8xx.h
@@ -0,0 +1,127 @@
+/*
+ * @brief LPC8xx I2C ROM API declarations and functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products. This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __ROM_I2C_8XX_H_
+#define __ROM_I2C_8XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CHIP_I2CROM_8XX CHIP: LPC8xx I2C ROM API declarations and functions
+ * @ingroup CHIP_8XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief LPC8xx I2C ROM driver handle structure
+ */
+typedef void *I2C_HANDLE_T;
+
+typedef uint32_t ErrorCode_t;
+
+/**
+ * @brief LPC8xx I2C ROM driver callback function
+ */
+typedef void (*I2C_CALLBK_T)(uint32_t err_code, uint32_t n);
+
+/**
+ * LPC8xx I2C ROM driver parameter structure
+ */
+typedef struct I2C_PARAM {
+ uint32_t num_bytes_send; /*!< No. of bytes to send */
+ uint32_t num_bytes_rec; /*!< No. of bytes to receive */
+ uint8_t *buffer_ptr_send; /*!< Pointer to send buffer */
+ uint8_t *buffer_ptr_rec; /*!< Pointer to receive buffer */
+ I2C_CALLBK_T func_pt; /*!< Callback function */
+ uint8_t stop_flag; /*!< Stop flag */
+ uint8_t dummy[3];
+} I2C_PARAM_T;
+
+/**
+ * LPC8xx I2C ROM driver result structure
+ */
+typedef struct I2C_RESULT {
+ uint32_t n_bytes_sent; /*!< No. of bytes sent */
+ uint32_t n_bytes_recd; /*!< No. of bytes received */
+} I2C_RESULT_T;
+
+/**
+ * LPC8xx I2C ROM driver modes enum
+ */
+typedef enum CHIP_I2C_MODE {
+ IDLE, /*!< IDLE state */
+ MASTER_SEND, /*!< Master send state */
+ MASTER_RECEIVE, /*!< Master Receive state */
+ SLAVE_SEND, /*!< Slave send state */
+ SLAVE_RECEIVE /*!< Slave receive state */
+} CHIP_I2C_MODE_T;
+
+/**
+ * LPC8xx I2C ROM driver APIs structure
+ */
+typedef struct I2CD_API {
+ /*!< Interrupt Support Routine */
+ void (*i2c_isr_handler)(I2C_HANDLE_T *handle);
+
+ /*!< MASTER functions */
+ ErrorCode_t (*i2c_master_transmit_poll)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result);
+ ErrorCode_t (*i2c_master_receive_poll)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result);
+ ErrorCode_t (*i2c_master_tx_rx_poll)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result);
+ ErrorCode_t (*i2c_master_transmit_intr)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result);
+ ErrorCode_t (*i2c_master_receive_intr)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result);
+ ErrorCode_t (*i2c_master_tx_rx_intr)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result);
+
+ /*!< SLAVE functions */
+ ErrorCode_t (*i2c_slave_receive_poll)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result);
+ ErrorCode_t (*i2c_slave_transmit_poll)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result);
+ ErrorCode_t (*i2c_slave_receive_intr)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result);
+ ErrorCode_t (*i2c_slave_transmit_intr)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result);
+ ErrorCode_t (*i2c_set_slave_addr)(I2C_HANDLE_T *handle, uint32_t slave_addr_0_3, uint32_t slave_mask_0_3);
+
+ /*!< OTHER support functions */
+ uint32_t (*i2c_get_mem_size)(void);
+ I2C_HANDLE_T * (*i2c_setup)( uint32_t i2c_base_addr, uint32_t * start_of_ram);
+ ErrorCode_t (*i2c_set_bitrate)(I2C_HANDLE_T *handle, uint32_t p_clk_in_hz, uint32_t bitrate_in_bps);
+ uint32_t (*i2c_get_firmware_version)(void);
+ CHIP_I2C_MODE_T (*i2c_get_status)(I2C_HANDLE_T *handle);
+ ErrorCode_t (*i2c_set_timeout)(I2C_HANDLE_T *handle, uint32_t timeout);
+} I2CD_API_T;
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ROM_I2C_8XX_H_ */
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/serial_api.c
new file mode 100644
index 0000000000..93386fb8aa
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/serial_api.c
@@ -0,0 +1,333 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// math.h required for floating point operations for baud rate calculation
+#include "mbed_assert.h"
+#include
+#include
+
+#include "serial_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+#if DEVICE_SERIAL
+
+/******************************************************************************
+ * INITIALIZATION
+ ******************************************************************************/
+#define UART_NUM 3
+
+static const SWM_Map SWM_UART_TX[] = {
+ {0, 0},
+ {1, 8},
+ {2, 16},
+};
+
+static const SWM_Map SWM_UART_RX[] = {
+ {0, 8},
+ {1, 16},
+ {2, 24},
+};
+
+static const SWM_Map SWM_UART_RTS[] = {
+ {0, 16},
+ {1, 24},
+ {3, 0},
+};
+
+static const SWM_Map SWM_UART_CTS[] = {
+ {0, 24},
+ {2, 0},
+ {3, 8}
+};
+
+// bit flags for used UARTs
+static unsigned char uart_used = 0;
+
+static int get_available_uart(void)
+{
+ int i;
+ for (i=0; iindex = uart_n;
+ obj->uart = (LPC_USART0_Type *)(LPC_USART0_BASE + (0x4000 * uart_n));
+ uart_used |= (1 << uart_n);
+
+ const SWM_Map *swm;
+ uint32_t regVal;
+
+ swm = &SWM_UART_TX[uart_n];
+ regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+ LPC_SWM->PINASSIGN[swm->n] = regVal | ((tx >> PIN_SHIFT) << swm->offset);
+
+ swm = &SWM_UART_RX[uart_n];
+ regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+ LPC_SWM->PINASSIGN[swm->n] = regVal | ((rx >> PIN_SHIFT) << swm->offset);
+
+ /* uart clock divided by 1 */
+ LPC_SYSCON->UARTCLKDIV = 1;
+
+ /* disable uart interrupts */
+ NVIC_DisableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
+
+ /* Enable UART clock */
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (14 + uart_n));
+
+ /* Peripheral reset control to UART, a "1" bring it out of reset. */
+ LPC_SYSCON->PRESETCTRL &= ~(0x1 << (3 + uart_n));
+ LPC_SYSCON->PRESETCTRL |= (0x1 << (3 + uart_n));
+
+ UARTSysClk = MainClock / LPC_SYSCON->UARTCLKDIV;
+
+ // set default baud rate and format
+ serial_baud (obj, 9600);
+ serial_format(obj, 8, ParityNone, 1);
+
+ /* Clear all status bits. */
+ obj->uart->STAT = CTS_DELTA | DELTA_RXBRK;
+
+ /* enable uart interrupts */
+ NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
+
+ /* Enable UART */
+ obj->uart->CFG |= UART_EN;
+
+ is_stdio_uart = ((tx == USBTX) && (rx == USBRX));
+
+ if (is_stdio_uart) {
+ stdio_uart_inited = 1;
+ memcpy(&stdio_uart, obj, sizeof(serial_t));
+ }
+}
+
+void serial_free(serial_t *obj)
+{
+ uart_used &= ~(1 << obj->index);
+ serial_irq_ids[obj->index] = 0;
+}
+
+void serial_baud(serial_t *obj, int baudrate)
+{
+ /* Integer divider:
+ BRG = UARTSysClk/(Baudrate * 16) - 1
+
+ Frational divider:
+ FRG = ((UARTSysClk / (Baudrate * 16 * (BRG + 1))) - 1)
+
+ where
+ FRG = (LPC_SYSCON->UARTFRDADD + 1) / (LPC_SYSCON->UARTFRDSUB + 1)
+
+ (1) The easiest way is set SUB value to 256, -1 encoded, thus SUB
+ register is 0xFF.
+ (2) In ADD register value, depending on the value of UartSysClk,
+ baudrate, BRG register value, and SUB register value, be careful
+ about the order of multiplier and divider and make sure any
+ multiplier doesn't exceed 32-bit boundary and any divider doesn't get
+ down below one(integer 0).
+ (3) ADD should be always less than SUB.
+ */
+ obj->uart->BRG = UARTSysClk / 16 / baudrate - 1;
+
+ LPC_SYSCON->UARTFRGDIV = 0xFF;
+ LPC_SYSCON->UARTFRGMULT = ( ((UARTSysClk / 16) * (LPC_SYSCON->UARTFRGDIV + 1)) /
+ (baudrate * (obj->uart->BRG + 1))
+ ) - (LPC_SYSCON->UARTFRGDIV + 1);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
+ // 0: 1 stop bits, 1: 2 stop bits
+ MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
+ MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits
+ MBED_ASSERT((parity == ParityNone) || (parity == ParityEven) || (parity == ParityOdd));
+ stop_bits -= 1;
+ data_bits -= 7;
+
+ int paritysel;
+ switch (parity) {
+ case ParityNone: paritysel = 0; break;
+ case ParityEven: paritysel = 2; break;
+ case ParityOdd : paritysel = 3; break;
+ default:
+ break;
+ }
+
+ obj->uart->CFG = (data_bits << 2)
+ | (paritysel << 4)
+ | (stop_bits << 6);
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+static inline void uart_irq(uint32_t iir, uint32_t index)
+{
+ SerialIrq irq_type;
+ switch (iir) {
+ case 1: irq_type = TxIrq; break;
+ case 2: irq_type = RxIrq; break;
+ default: return;
+ }
+
+ if (serial_irq_ids[index] != 0)
+ irq_handler(serial_irq_ids[index], irq_type);
+}
+
+void uart0_irq() {uart_irq((LPC_USART0->STAT & (1 << 2)) ? 2 : 1, 0);}
+void uart1_irq() {uart_irq((LPC_USART1->STAT & (1 << 2)) ? 2 : 1, 1);}
+void uart2_irq() {uart_irq((LPC_USART2->STAT & (1 << 2)) ? 2 : 1, 2);}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+ irq_handler = handler;
+ serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+ switch ((int)obj->uart) {
+ case LPC_USART0_BASE: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
+ case LPC_USART1_BASE: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
+ case LPC_USART2_BASE: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
+ }
+
+ if (enable) {
+ obj->uart->INTENSET = (1 << ((irq == RxIrq) ? 0 : 2));
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+ } else { // disable
+ int all_disabled = 0;
+ SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
+ obj->uart->INTENSET &= ~(1 << ((irq == RxIrq) ? 0 : 2));
+ all_disabled = (obj->uart->INTENSET & (1 << ((other_irq == RxIrq) ? 0 : 2))) == 0;
+ if (all_disabled)
+ NVIC_DisableIRQ(irq_n);
+ }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj)
+{
+ while (!serial_readable(obj));
+ return obj->uart->RXDAT;
+}
+
+void serial_putc(serial_t *obj, int c)
+{
+ while (!serial_writable(obj));
+ obj->uart->TXDAT = c;
+}
+
+int serial_readable(serial_t *obj)
+{
+ return obj->uart->STAT & RXRDY;
+}
+
+int serial_writable(serial_t *obj)
+{
+ return obj->uart->STAT & TXRDY;
+}
+
+void serial_clear(serial_t *obj)
+{
+ // [TODO]
+}
+
+void serial_pinout_tx(PinName tx)
+{
+
+}
+
+void serial_break_set(serial_t *obj)
+{
+ obj->uart->CTL |= TXBRKEN;
+}
+
+void serial_break_clear(serial_t *obj)
+{
+ obj->uart->CTL &= ~TXBRKEN;
+}
+
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
+{
+ const SWM_Map *swm_rts, *swm_cts;
+ uint32_t regVal_rts, regVal_cts;
+
+ swm_rts = &SWM_UART_RTS[obj->index];
+ swm_cts = &SWM_UART_CTS[obj->index];
+ regVal_rts = LPC_SWM->PINASSIGN[swm_rts->n] & ~(0xFF << swm_rts->offset);
+ regVal_cts = LPC_SWM->PINASSIGN[swm_cts->n] & ~(0xFF << swm_cts->offset);
+
+ if (FlowControlNone == type) {
+ LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset);
+ LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset);
+ obj->uart->CFG &= ~CTSEN;
+ return;
+ }
+ if ((FlowControlRTS == type || FlowControlRTSCTS == type) && (rxflow != NC)) {
+ LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | ((rxflow >> PIN_SHIFT) << swm_rts->offset);
+ if (FlowControlRTS == type) {
+ LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset);
+ obj->uart->CFG &= ~CTSEN;
+ }
+ }
+ if ((FlowControlCTS == type || FlowControlRTSCTS == type) && (txflow != NC)) {
+ LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | ((txflow >> PIN_SHIFT) << swm_cts->offset);
+ obj->uart->CFG |= CTSEN;
+ if (FlowControlCTS == type) {
+ LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset);
+ }
+ }
+}
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/sleep.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/sleep.c
new file mode 100644
index 0000000000..64115a2055
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/sleep.c
@@ -0,0 +1,62 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "sleep_api.h"
+#include "cmsis.h"
+
+
+//#define DEEPSLEEP
+#define POWERDOWN
+
+void sleep(void)
+{
+ //Normal sleep mode for PCON:
+ LPC_PMU->PCON &= ~0x03;
+
+ //Normal sleep mode for ARM core:
+ SCB->SCR = 0;
+
+ //And go to sleep
+ __WFI();
+}
+
+// Deepsleep/powerdown modes assume the device is configured to use its internal RC oscillator directly
+
+void deepsleep(void)
+{
+ //Deep sleep in PCON
+ LPC_PMU->PCON &= ~0x03;
+
+#if defined(DEEPSLEEP)
+ LPC_PMU->PCON |= 0x01;
+#elif defined(POWERDOWN)
+ LPC_PMU->PCON |= 0x02;
+#endif
+
+ //If brownout detection and WDT are enabled, keep them enabled during sleep
+ LPC_SYSCON->PDSLEEPCFG = LPC_SYSCON->PDRUNCFG;
+
+ //After wakeup same stuff as currently enabled:
+ LPC_SYSCON->PDAWAKECFG = LPC_SYSCON->PDRUNCFG;
+
+ //All interrupts may wake up:
+ LPC_SYSCON->STARTERP0 = 0xFF;
+ LPC_SYSCON->STARTERP1 = 0xFFFF;
+
+ //Deep sleep for ARM core:
+ SCB->SCR = 1<<2;
+
+ __WFI();
+}
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/spi_api.c
new file mode 100644
index 0000000000..5e416c4c34
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/spi_api.c
@@ -0,0 +1,214 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+
+#include "spi_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+#if DEVICE_SPI
+
+static const SWM_Map SWM_SPI_SSEL[] = {
+ {4, 16},
+ {5, 16},
+};
+
+static const SWM_Map SWM_SPI_SCLK[] = {
+ {3, 24},
+ {4, 24},
+};
+
+static const SWM_Map SWM_SPI_MOSI[] = {
+ {4, 0},
+ {5, 0},
+};
+
+static const SWM_Map SWM_SPI_MISO[] = {
+ {4, 8},
+ {5, 16},
+};
+
+// bit flags for used SPIs
+static unsigned char spi_used = 0;
+
+static int get_available_spi(void)
+{
+ int i;
+ for (i=0; i<2; i++) {
+ if ((spi_used & (1 << i)) == 0)
+ return i;
+ }
+ return -1;
+}
+
+static inline int ssp_disable(spi_t *obj);
+static inline int ssp_enable(spi_t *obj);
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
+ int spi_n = get_available_spi();
+ if (spi_n == -1) {
+ error("No available SPI");
+ }
+ obj->spi_n = spi_n;
+ spi_used |= (1 << spi_n);
+
+ obj->spi = (spi_n) ? (LPC_SPI0_Type *)(LPC_SPI1_BASE) : (LPC_SPI0_Type *)(LPC_SPI0_BASE);
+
+ const SWM_Map *swm;
+ uint32_t regVal;
+
+ if (sclk != (PinName)NC) {
+ swm = &SWM_SPI_SCLK[obj->spi_n];
+ regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+ LPC_SWM->PINASSIGN[swm->n] = regVal | ((sclk >> PIN_SHIFT) << swm->offset);
+ }
+
+ if (mosi != (PinName)NC) {
+ swm = &SWM_SPI_MOSI[obj->spi_n];
+ regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+ LPC_SWM->PINASSIGN[swm->n] = regVal | ((mosi >> PIN_SHIFT) << swm->offset);
+ }
+
+ if (miso != (PinName)NC) {
+ swm = &SWM_SPI_MISO[obj->spi_n];
+ regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+ LPC_SWM->PINASSIGN[swm->n] = regVal | ((miso >> PIN_SHIFT) << swm->offset);
+ }
+
+ if (ssel != (PinName)NC) {
+ swm = &SWM_SPI_SSEL[obj->spi_n];
+ regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+ LPC_SWM->PINASSIGN[swm->n] = regVal | ((ssel >> PIN_SHIFT) << swm->offset);
+ }
+
+ // clear interrupts
+ obj->spi->INTENCLR = 0x3f;
+
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (11 + obj->spi_n));
+ LPC_SYSCON->PRESETCTRL &= ~(1 << obj->spi_n);
+ LPC_SYSCON->PRESETCTRL |= (1 << obj->spi_n);
+
+ // set default format and frequency
+ if (ssel == NC) {
+ spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
+ } else {
+ spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
+ }
+ spi_frequency(obj, 1000000);
+
+ // enable the ssp channel
+ ssp_enable(obj);
+}
+
+void spi_free(spi_t *obj)
+{
+}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+ MBED_ASSERT(((bits >= 1) && (bits <= 16)) && ((mode >= 0) && (mode <= 3)));
+ ssp_disable(obj);
+
+ obj->spi->CFG &= ~((0x3 << 4) | (1 << 2));
+ obj->spi->CFG |= ((mode & 0x3) << 4) | ((slave ? 0 : 1) << 2);
+
+ obj->spi->TXDATCTL &= ~( 0xF << 24);
+ obj->spi->TXDATCTL |= (((bits & 0xF) - 1) << 24);
+
+ ssp_enable(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz)
+{
+ ssp_disable(obj);
+
+ // rise DIV value if it cannot be divided
+ obj->spi->DIV = (SystemCoreClock + (hz - 1))/hz - 1;
+ obj->spi->DLY = 0;
+
+ ssp_enable(obj);
+}
+
+static inline int ssp_disable(spi_t *obj)
+{
+ return obj->spi->CFG &= ~(1 << 0);
+}
+
+static inline int ssp_enable(spi_t *obj)
+{
+ return obj->spi->CFG |= (1 << 0);
+}
+
+static inline int ssp_readable(spi_t *obj)
+{
+ return obj->spi->STAT & (1 << 0);
+}
+
+static inline int ssp_writeable(spi_t *obj)
+{
+ return obj->spi->STAT & (1 << 1);
+}
+
+static inline void ssp_write(spi_t *obj, int value)
+{
+ while (!ssp_writeable(obj));
+ // end of transfer
+ obj->spi->TXDATCTL |= (1 << 20);
+ obj->spi->TXDAT = value;
+}
+
+static inline int ssp_read(spi_t *obj)
+{
+ while (!ssp_readable(obj));
+ return obj->spi->RXDAT;
+}
+
+static inline int ssp_busy(spi_t *obj)
+{
+ // checking RXOV(Receiver Overrun interrupt flag)
+ return obj->spi->STAT & (1 << 2);
+}
+
+int spi_master_write(spi_t *obj, int value)
+{
+ ssp_write(obj, value);
+ return ssp_read(obj);
+}
+
+int spi_slave_receive(spi_t *obj)
+{
+ return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
+}
+
+int spi_slave_read(spi_t *obj)
+{
+ return obj->spi->RXDAT;
+}
+
+void spi_slave_write(spi_t *obj, int value)
+{
+ while (ssp_writeable(obj) == 0);
+ obj->spi->TXDAT = value;
+}
+
+int spi_busy(spi_t *obj)
+{
+ return ssp_busy(obj);
+}
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/us_ticker.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/us_ticker.c
new file mode 100644
index 0000000000..94b2318ca3
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/us_ticker.c
@@ -0,0 +1,89 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+
+static int us_ticker_inited = 0;
+static int ticker_expired = 0;
+
+#define US_TICKER_TIMER_IRQn MRT_IRQn
+#define MRT_CLOCK_MHZ 30
+
+void us_ticker_init(void)
+{
+ if (us_ticker_inited)
+ return;
+
+ us_ticker_inited = 1;
+
+ // Enable the MRT clock
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10);
+
+ // Clear peripheral reset the MRT
+ LPC_SYSCON->PRESETCTRL |= (1 << 7);
+
+ // Force load interval value
+ LPC_MRT->INTVAL0 = 0xFFFFFFFFUL;
+ // Enable ch0 interrupt
+ LPC_MRT->CTRL0 = 1;
+
+ // Force load interval value
+ LPC_MRT->INTVAL1 = 0x80000000UL;
+ // Disable ch1 interrupt
+ LPC_MRT->CTRL1 = 0;
+
+ // Set MRT interrupt vector
+ NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
+ NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
+}
+
+uint32_t us_ticker_read()
+{
+ if (!us_ticker_inited)
+ us_ticker_init();
+
+ // Generate ticker value
+ // MRT source clock is SystemCoreClock (30MHz) and 31-bit down count timer
+ // Calculate expected value using number of expired times
+ return (0x7FFFFFFFUL - LPC_MRT->TIMER0)/MRT_CLOCK_MHZ + (ticker_expired * (0x80000000UL/MRT_CLOCK_MHZ));
+}
+
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+ // Force load interval value
+ LPC_MRT->INTVAL1 = (((timestamp - us_ticker_read()) * MRT_CLOCK_MHZ) | 0x80000000UL);
+
+ // Enable interrupt
+ LPC_MRT->CTRL1 |= 1;
+}
+
+void us_ticker_disable_interrupt()
+{
+ LPC_MRT->CTRL1 &= ~1;
+}
+
+void us_ticker_clear_interrupt()
+{
+ if (LPC_MRT->STAT1 & 1)
+ LPC_MRT->STAT1 = 1;
+
+ if (LPC_MRT->STAT0 & 1) {
+ LPC_MRT->STAT0 = 1;
+ ticker_expired++;
+ }
+}
diff --git a/libraries/rtos/rtx/RTX_CM_lib.h b/libraries/rtos/rtx/RTX_CM_lib.h
index 2a694e26ab..e4e17dc941 100755
--- a/libraries/rtos/rtx/RTX_CM_lib.h
+++ b/libraries/rtos/rtx/RTX_CM_lib.h
@@ -214,6 +214,9 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL}
#elif defined(TARGET_LPC812)
#define INITIAL_SP (0x10001000UL)
+#elif defined(TARGET_LPC824)
+#define INITIAL_SP (0x10002000UL)
+
#elif defined(TARGET_KL25Z)
#define INITIAL_SP (0x20003000UL)
diff --git a/libraries/rtos/rtx/RTX_Conf_CM.c b/libraries/rtos/rtx/RTX_Conf_CM.c
index 35e4c114cf..00c60b204b 100755
--- a/libraries/rtos/rtx/RTX_Conf_CM.c
+++ b/libraries/rtos/rtx/RTX_Conf_CM.c
@@ -54,7 +54,7 @@
# define OS_TASKCNT 14
# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \
|| defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \
- || defined(TARGET_STM32F103RB)
+ || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824)
# define OS_TASKCNT 6
# else
# error "no target defined"
@@ -68,7 +68,7 @@
# define OS_SCHEDULERSTKSIZE 256
# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \
|| defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \
- || defined(TARGET_STM32F103RB)
+ || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824)
# define OS_SCHEDULERSTKSIZE 128
# else
# error "no target defined"
@@ -123,6 +123,9 @@
# elif defined(TARGET_LPC812)
# define OS_CLOCK 36000000
+# elif defined(TARGET_LPC824)
+# define OS_CLOCK 30000000
+
# elif defined(TARGET_STM32F100RB)
# define OS_CLOCK 24000000
diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py
index 997d710c5f..43ad9029b3 100755
--- a/workspace_tools/build_release.py
+++ b/workspace_tools/build_release.py
@@ -33,6 +33,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = (
('ARCH_PRO', ('ARM', 'GCC_ARM', 'GCC_CR', 'GCC_CS', 'IAR')),
('LPC2368', ('ARM',)),
('LPC812', ('uARM',)),
+ ('LPC824', ('uARM',)),
('LPC1347', ('ARM',)),
('LPC4088', ('ARM', 'GCC_ARM', 'GCC_CR')),
('LPC1114', ('uARM','GCC_ARM')),
diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py
index 563a68f6fd..8b6b337aee 100644
--- a/workspace_tools/targets.py
+++ b/workspace_tools/targets.py
@@ -198,6 +198,17 @@ class LPC810(LPCTarget):
self.is_disk_virtual = True
+class LPC824(LPCTarget):
+ def __init__(self):
+ LPCTarget.__init__(self)
+ self.core = "Cortex-M0+"
+ self.extra_labels = ['NXP', 'LPC82X']
+ self.supported_toolchains = ["uARM"]
+ self.default_toolchain = "uARM"
+ self.supported_form_factors = ["ARDUINO"]
+ self.is_disk_virtual = True
+
+
class LPC4088(LPCTarget):
def __init__(self):
LPCTarget.__init__(self)
@@ -695,6 +706,7 @@ TARGETS = [
K22F(),
LPC812(),
LPC810(),
+ LPC824(),
LPC4088(),
LPC4330_M4(),
LPC4337(),