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Merge branch 'master' of https://github.com/mbedmicro/mbed

pull/969/head
mazgch 2015-03-03 16:10:25 +01:00
parent 1c90460566 9d2fd3e097
commit 67ad872b47
411 changed files with 87996 additions and 12253 deletions
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5
.travis.yml
View File

@ -1,5 +1,8 @@
---
install: "sudo $TRAVIS_BUILD_DIR/travis/install_dependencies.sh > /dev/null"
python:
- "2.7"
script: "python workspace_tools/build_travis.py"
install:
- "sudo $TRAVIS_BUILD_DIR/travis/install_dependencies.sh > /dev/null"
- sudo pip install colorama
- sudo pip install prettytable

1
README.md
View File

@ -33,6 +33,7 @@ NXP:
* LPC810 (Cortex-M0+)
* [LPC812](http://developer.mbed.org/platforms/NXP-LPC800-MAX/) (Cortex-M0+)
* [EA LPC4088](http://developer.mbed.org/platforms/EA-LPC4088/) (Cortex-M4F)
* [EA LPC4088 DM](http://developer.mbed.org/platforms/EA-LPC4088-Display-Module/) (Cortex-M4F)
* LPC4330 (Cortex-M4F + Cortex-M0)
* [LPC1347](http://developer.mbed.org/platforms/DipCortex-M3/) (Cortex-M3)
* [LPC1114](http://developer.mbed.org/platforms/LPC1114FN28/) (Cortex-M0)

2
libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_function_userdef.c
View File

@ -52,7 +52,7 @@ Typedef definitions
/*******************************************************************************
Macro definitions
*******************************************************************************/
#define DUMMY_ACCESS (*(volatile unsigned long *)(OSTM0CNT))
#define DUMMY_ACCESS OSTM0CNT
/* #define CACHE_WRITEBACK */

2
libraries/USBDevice/USBDevice/USBEndpoints.h
View File

@ -37,7 +37,7 @@ typedef enum {
} EP_STATUS;
/* Include configuration for specific target */
#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088)
#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
#include "USBEndpoints_LPC17_LPC23.h"
#elif defined(TARGET_LPC11UXX) || defined(TARGET_LPC1347) || defined (TARGET_LPC11U6X) || defined (TARGET_LPC1549)
#include "USBEndpoints_LPC11U.h"

2
libraries/USBDevice/USBDevice/USBHAL_LPC40.cpp
View File

@ -16,7 +16,7 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#if defined(TARGET_LPC4088)
#if defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
#include "USBHAL.h"

6
libraries/USBDevice/USBDevice/USBHAL_RZ_A1H.cpp
View File

@ -515,10 +515,10 @@ extern "C" {
if (RZA_IO_RegRead_16(
&g_usb0_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) {
/* read */
__nop();
__NOP();
} else {
/* write */
__nop();
__NOP();
}
}
}
@ -629,7 +629,7 @@ extern "C" {
if (RZA_IO_RegRead_16(
&g_usb0_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) {
/* read */
__nop();
__NOP();
} else {
/* write */
EPx_read_status = DEVDRV_USBF_PIPE_WAIT;

2
libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_userdef.c
View File

@ -56,7 +56,7 @@ Typedef definitions
/*******************************************************************************
Macro definitions
*******************************************************************************/
#define DUMMY_ACCESS (*(volatile unsigned long *)(OSTM0CNT))
#define DUMMY_ACCESS OSTM0CNT
/* #define CACHE_WRITEBACK */

4
libraries/USBHost/USBHost/USBHALHost_RZ_A1.cpp
View File

@ -237,6 +237,7 @@ void USBHALHost::_usbisr(void) {
void USBHALHost::UsbIrqhandler() {
uint32_t int_status = ohciwrapp_reg_r(OHCI_REG_INTERRUPTSTATUS) & ohciwrapp_reg_r(OHCI_REG_INTERRUPTENABLE);
uint32_t data;
if (int_status != 0) { //Is there something to actually process?
// Root hub status change interrupt
@ -254,7 +255,8 @@ void USBHALHost::UsbIrqhandler() {
wait_ms(150);
//Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
deviceConnected(0, 1, ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA);
data = ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA;
deviceConnected(0, 1, data);
}
//Root device disconnected

2
libraries/mbed/api/mbed.h
View File

@ -16,7 +16,7 @@
#ifndef MBED_H
#define MBED_H
#define MBED_LIBRARY_VERSION 92
#define MBED_LIBRARY_VERSION 94
#include "platform.h"

46
libraries/mbed/common/exit.c
View File

@ -1,46 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "semihost_api.h"
#include "mbed_interface.h"
#if DEVICE_STDIO_MESSAGES
#include <stdio.h>
#endif
#ifdef TOOLCHAIN_GCC_CW
// TODO: Ideally, we would like to define directly "_ExitProcess"
void mbed_exit(int return_code) {
#elif defined TOOLCHAIN_GCC_ARM
void _exit(int return_code) {
#else
void exit(int return_code) {
#endif
#if DEVICE_STDIO_MESSAGES
fflush(stdout);
fflush(stderr);
#endif
#if DEVICE_SEMIHOST
if (mbed_interface_connected()) {
semihost_exit();
}
#endif
if (return_code) {
mbed_die();
}
while (1);
}

53
libraries/mbed/common/retarget.cpp
View File

@ -1,5 +1,5 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@ -19,6 +19,11 @@
#include "FilePath.h"
#include "serial_api.h"
#include "toolchain.h"
#include "semihost_api.h"
#include "mbed_interface.h"
#if DEVICE_STDIO_MESSAGES
#include <stdio.h>
#endif
#include <errno.h>
#if defined(__ARMCC_VERSION)
@ -454,6 +459,10 @@ extern "C" void __iar_argc_argv() {
// Linker defined symbol used by _sbrk to indicate where heap should start.
extern "C" int __end__;
#if defined(TARGET_CORTEX_A)
extern "C" uint32_t __HeapLimit;
#endif
// Turn off the errno macro and use actual global variable instead.
#undef errno
extern "C" int errno;
@ -469,6 +478,8 @@ extern "C" caddr_t _sbrk(int incr) {
#if defined(TARGET_ARM7)
if (new_heap >= stack_ptr) {
#elif defined(TARGET_CORTEX_A)
if (new_heap >= (unsigned char*)&__HeapLimit) { /* __HeapLimit is end of heap section */
#else
if (new_heap >= (unsigned char*)__get_MSP()) {
#endif
@ -482,6 +493,38 @@ extern "C" caddr_t _sbrk(int incr) {
#endif
#ifdef TOOLCHAIN_GCC_CW
// TODO: Ideally, we would like to define directly "_ExitProcess"
extern "C" void mbed_exit(int return_code) {
#elif defined TOOLCHAIN_GCC_ARM
extern "C" void _exit(int return_code) {
#else
namespace std {
extern "C" void exit(int return_code) {
#endif
#if DEVICE_STDIO_MESSAGES
fflush(stdout);
fflush(stderr);
#endif
#if DEVICE_SEMIHOST
if (mbed_interface_connected()) {
semihost_exit();
}
#endif
if (return_code) {
mbed_die();
}
while (1);
}
#if !defined(TOOLCHAIN_GCC_ARM) && !defined(TOOLCHAIN_GCC_CW)
} //namespace std
#endif
namespace mbed {
void mbed_set_unbuffered_stream(FILE *_file) {
@ -524,11 +567,3 @@ char* mbed_gets(char*s, int size, FILE *_file){
}
} // namespace mbed

14
libraries/mbed/common/us_ticker_api.c
View File

@ -116,3 +116,17 @@ void us_ticker_remove_event(ticker_event_t *obj) {
__enable_irq();
}
int us_ticker_get_next_timestamp(timestamp_t *timestamp) {
int ret = 0;
/* if head is NULL, there are no pending events */
__disable_irq();
if (head != NULL) {
*timestamp = head->timestamp;
ret = 1;
}
__enable_irq();
return ret;
}

2
libraries/mbed/hal/i2c_api.h
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@ -46,6 +46,8 @@ void i2c_slave_mode (i2c_t *obj, int enable_slave);
int i2c_slave_receive(i2c_t *obj);
int i2c_slave_read (i2c_t *obj, char *data, int length);
int i2c_slave_write (i2c_t *obj, const char *data, int length);
int i2c_slave_byte_read(i2c_t *obj, int last);
int i2c_slave_byte_write(i2c_t *obj, int data);
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
#endif

1
libraries/mbed/hal/us_ticker_api.h
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@ -43,6 +43,7 @@ void us_ticker_irq_handler(void);
void us_ticker_insert_event(ticker_event_t *obj, timestamp_t timestamp, uint32_t id);
void us_ticker_remove_event(ticker_event_t *obj);
int us_ticker_get_next_timestamp(timestamp_t *timestamp);
#ifdef __cplusplus
}

5
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf
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@ -11,8 +11,9 @@ define symbol __ICFEDIT_region_NVIC_end__ = 0x1fffe0f7;
define symbol __ICFEDIT_region_RAM_start__ = 0x1fffe0f8;
define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x800;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0x600;
define symbol __ICFEDIT_size_heap__ = 0xC00;
/**** End of ICF editor section. ###ICF###*/
define symbol __region_RAM2_start__ = 0x20000000;

9
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf
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@ -7,12 +7,13 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0007ffff;
define symbol __ICFEDIT_region_NVIC_start__ = 0x1fff0000;
define symbol __ICFEDIT_region_NVIC_end__ = 0x1fff0197;
define symbol __ICFEDIT_region_RAM_start__ = 0x1fff0198;
define symbol __ICFEDIT_region_NVIC_end__ = 0x1fff03ff;
define symbol __ICFEDIT_region_RAM_start__ = 0x1fff0400;
define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x2000;
define symbol __ICFEDIT_size_heap__ = 0x4000;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0x4000;
define symbol __ICFEDIT_size_heap__ = 0x8000;
/**** End of ICF editor section. ###ICF###*/
define symbol __region_RAM2_start__ = 0x20000000;

2
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c
View File

@ -30,7 +30,7 @@
*/
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000) // Vectors positioned at start of RAM
#define NVIC_RAM_VECTOR_ADDRESS (0x1FFF0000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {

2
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h
View File

@ -32,7 +32,7 @@
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 46) // CORE + MCU Peripherals
#define NVIC_NUM_VECTORS (16 + 86) // CORE + MCU Peripherals
#define NVIC_USER_IRQ_OFFSET 16
#include "cmsis.h"

3
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_IAR/MKL05Z4.icf
View File

@ -11,8 +11,9 @@ define symbol __ICFEDIT_region_NVIC_end__ = 0x1ffffcbf;
define symbol __ICFEDIT_region_RAM_start__ = 0x1ffffcc0;
define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
/*-Sizes-*/
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0x200;
define symbol __ICFEDIT_size_heap__ = 0x200;
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define symbol __region_RAM2_start__ = 0x20000000;

5
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_IAR/MKL25Z4.icf
View File

@ -11,8 +11,9 @@ define symbol __ICFEDIT_region_NVIC_end__ = 0x1ffff0bf;
define symbol __ICFEDIT_region_RAM_start__ = 0x1ffff0c0;
define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0xA00;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__ = 0x1000;
/**** End of ICF editor section. ###ICF###*/
define symbol __region_RAM2_start__ = 0x20000000;

5
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/MKL46Z4.icf
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@ -11,8 +11,9 @@ define symbol __ICFEDIT_region_NVIC_end__ = 0x1fffe0bf;
define symbol __ICFEDIT_region_RAM_start__ = 0x1fffe0c0;
define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__ = 0x1000;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x2000;
/**** End of ICF editor section. ###ICF###*/
define symbol __region_RAM2_start__ = 0x20000000;

5
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_IAR/MK64F.icf
View File

@ -11,8 +11,9 @@ define symbol __ICFEDIT_region_NVIC_end__ = 0x1fff0197;
define symbol __ICFEDIT_region_RAM_start__ = 0x1fff0198;
define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x2000;
define symbol __ICFEDIT_size_heap__ = 0x4000;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0x8000;
define symbol __ICFEDIT_size_heap__ = 0x10000;
/**** End of ICF editor section. ###ICF###*/
define symbol __region_RAM2_start__ = 0x20000000;

155
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_IAR/startup_MK64F12.s
View File

@ -138,160 +138,7 @@ __vector_table
DCD ENET_Transmit_IRQHandler ; Ethernet MAC Transmit Interrupt
DCD ENET_Receive_IRQHandler ; Ethernet MAC Receive Interrupt
DCD ENET_Error_IRQHandler ; Ethernet MAC Error and miscelaneous Interrupt
DCD Default_Handler ; 102
DCD Default_Handler ; 103
DCD Default_Handler ; 104
DCD Default_Handler ; 105
DCD Default_Handler ; 106
DCD Default_Handler ; 107
DCD Default_Handler ; 108
DCD Default_Handler ; 109
DCD Default_Handler ; 110
DCD Default_Handler ; 111
DCD Default_Handler ; 112
DCD Default_Handler ; 113
DCD Default_Handler ; 114
DCD Default_Handler ; 115
DCD Default_Handler ; 116
DCD Default_Handler ; 117
DCD Default_Handler ; 118
DCD Default_Handler ; 119
DCD Default_Handler ; 120
DCD Default_Handler ; 121
DCD Default_Handler ; 122
DCD Default_Handler ; 123
DCD Default_Handler ; 124
DCD Default_Handler ; 125
DCD Default_Handler ; 126
DCD Default_Handler ; 127
DCD Default_Handler ; 128
DCD Default_Handler ; 129
DCD Default_Handler ; 130
DCD Default_Handler ; 131
DCD Default_Handler ; 132
DCD Default_Handler ; 133
DCD Default_Handler ; 134
DCD Default_Handler ; 135
DCD Default_Handler ; 136
DCD Default_Handler ; 137
DCD Default_Handler ; 138
DCD Default_Handler ; 139
DCD Default_Handler ; 140
DCD Default_Handler ; 141
DCD Default_Handler ; 142
DCD Default_Handler ; 143
DCD Default_Handler ; 144
DCD Default_Handler ; 145
DCD Default_Handler ; 146
DCD Default_Handler ; 147
DCD Default_Handler ; 148
DCD Default_Handler ; 149
DCD Default_Handler ; 150
DCD Default_Handler ; 151
DCD Default_Handler ; 152
DCD Default_Handler ; 153
DCD Default_Handler ; 154
DCD Default_Handler ; 155
DCD Default_Handler ; 156
DCD Default_Handler ; 157
DCD Default_Handler ; 158
DCD Default_Handler ; 159
DCD Default_Handler ; 160
DCD Default_Handler ; 161
DCD Default_Handler ; 162
DCD Default_Handler ; 163
DCD Default_Handler ; 164
DCD Default_Handler ; 165
DCD Default_Handler ; 166
DCD Default_Handler ; 167
DCD Default_Handler ; 168
DCD Default_Handler ; 169
DCD Default_Handler ; 170
DCD Default_Handler ; 171
DCD Default_Handler ; 172
DCD Default_Handler ; 173
DCD Default_Handler ; 174
DCD Default_Handler ; 175
DCD Default_Handler ; 176
DCD Default_Handler ; 177
DCD Default_Handler ; 178
DCD Default_Handler ; 179
DCD Default_Handler ; 180
DCD Default_Handler ; 181
DCD Default_Handler ; 182
DCD Default_Handler ; 183
DCD Default_Handler ; 184
DCD Default_Handler ; 185
DCD Default_Handler ; 186
DCD Default_Handler ; 187
DCD Default_Handler ; 188
DCD Default_Handler ; 189
DCD Default_Handler ; 190
DCD Default_Handler ; 191
DCD Default_Handler ; 192
DCD Default_Handler ; 193
DCD Default_Handler ; 194
DCD Default_Handler ; 195
DCD Default_Handler ; 196
DCD Default_Handler ; 197
DCD Default_Handler ; 198
DCD Default_Handler ; 199
DCD Default_Handler ; 200
DCD Default_Handler ; 201
DCD Default_Handler ; 202
DCD Default_Handler ; 203
DCD Default_Handler ; 204
DCD Default_Handler ; 205
DCD Default_Handler ; 206
DCD Default_Handler ; 207
DCD Default_Handler ; 208
DCD Default_Handler ; 209
DCD Default_Handler ; 210
DCD Default_Handler ; 211
DCD Default_Handler ; 212
DCD Default_Handler ; 213
DCD Default_Handler ; 214
DCD Default_Handler ; 215
DCD Default_Handler ; 216
DCD Default_Handler ; 217
DCD Default_Handler ; 218
DCD Default_Handler ; 219
DCD Default_Handler ; 220
DCD Default_Handler ; 221
DCD Default_Handler ; 222
DCD Default_Handler ; 223
DCD Default_Handler ; 224
DCD Default_Handler ; 225
DCD Default_Handler ; 226
DCD Default_Handler ; 227
DCD Default_Handler ; 228
DCD Default_Handler ; 229
DCD Default_Handler ; 230
DCD Default_Handler ; 231
DCD Default_Handler ; 232
DCD Default_Handler ; 233
DCD Default_Handler ; 234
DCD Default_Handler ; 235
DCD Default_Handler ; 236
DCD Default_Handler ; 237
DCD Default_Handler ; 238
DCD Default_Handler ; 239
DCD Default_Handler ; 240
DCD Default_Handler ; 241
DCD Default_Handler ; 242
DCD Default_Handler ; 243
DCD Default_Handler ; 244
DCD Default_Handler ; 245
DCD Default_Handler ; 246
DCD Default_Handler ; 247
DCD Default_Handler ; 248
DCD Default_Handler ; 249
DCD Default_Handler ; 250
DCD Default_Handler ; 251
DCD Default_Handler ; 252
DCD Default_Handler ; 253
DCD Default_Handler ; 254
DCD Default_Handler ; 255
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;Flash Configuration
;;16-byte flash configuration field that stores default protection settings (loaded on reset)

2
libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct
View File

@ -5,7 +5,7 @@
; *(InRoot$$Sections)
; .ANY (+RO)
; }
; RW_IRAM1 0x20000000 0x00004000 {
; RW_IRAM1 0x20000000 0x00008000 {
; .ANY (+RW +ZI)
; }
;}

43
libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf Normal file
View File

@ -0,0 +1,43 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00016000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x000160c0;
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20002000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x900;
/**** End of ICF editor section. ###ICF###*/
define symbol __code_start_soft_device__ = 0x0;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
keep { section .intvec };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK,
block HEAP };
/*This is used for mbed applications build inside the Embedded workbench
Applications build with the python scritps use a hex merge so need to merge it
inside the linker. The linker can only use binary files so the hex merge is not possible
through the linker. That is why a binary is used instead of a hex image for the embedded project.
*/
if(isdefinedsymbol(SOFT_DEVICE_BIN))
{
place at address mem:__code_start_soft_device__ { section .noinit_softdevice };
}

237
libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.s Normal file
View File

@ -0,0 +1,237 @@
;; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
;; The information contained herein is confidential property of Nordic
;; Semiconductor ASA.Terms and conditions of usage are described in detail
;; in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
;; Licensees are granted free, non-transferable use of the information. NO
;; WARRANTY of ANY KIND is provided. This heading must NOT be removed from
;; the file.
;; Description message
MODULE ?cstartup
;; Stack size default : 1024
;; Heap size default : 2048
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD 0
DCD 0
DCD 0
;__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD 0
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK
DCD RADIO_IRQHandler ;RADIO
DCD UART0_IRQHandler ;UART0
DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0
DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1
DCD 0 ;Reserved
DCD GPIOTE_IRQHandler ;GPIOTE
DCD ADC_IRQHandler ;ADC
DCD TIMER0_IRQHandler ;TIMER0
DCD TIMER1_IRQHandler ;TIMER1
DCD TIMER2_IRQHandler ;TIMER2
DCD RTC0_IRQHandler ;RTC0
DCD TEMP_IRQHandler ;TEMP
DCD RNG_IRQHandler ;RNG
DCD ECB_IRQHandler ;ECB
DCD CCM_AAR_IRQHandler ;CCM_AAR
DCD WDT_IRQHandler ;WDT
DCD RTC1_IRQHandler ;RTC1
DCD QDEC_IRQHandler ;QDEC
DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP
DCD SWI0_IRQHandler ;SWI0
DCD SWI1_IRQHandler ;SWI1
DCD SWI2_IRQHandler ;SWI2
DCD SWI3_IRQHandler ;SWI3
DCD SWI4_IRQHandler ;SWI4
DCD SWI5_IRQHandler ;SWI5
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask
; Default handlers.
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =NRF_POWER_RAMON_ADDRESS
LDR R2, [R0]
MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
ORRS R2, R2, R1
STR R2, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
; Dummy exception handlers
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B .
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B .
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B .
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B .
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B .
; Dummy interrupt handlers
PUBWEAK POWER_CLOCK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
POWER_CLOCK_IRQHandler
B .
PUBWEAK RADIO_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RADIO_IRQHandler
B .
PUBWEAK UART0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART0_IRQHandler
B .
PUBWEAK SPI0_TWI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI0_TWI0_IRQHandler
B .
PUBWEAK SPI1_TWI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_TWI1_IRQHandler
B .
PUBWEAK GPIOTE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOTE_IRQHandler
B .
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC_IRQHandler
B .
PUBWEAK TIMER0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER0_IRQHandler
B .
PUBWEAK TIMER1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER1_IRQHandler
B .
PUBWEAK TIMER2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER2_IRQHandler
B .
PUBWEAK RTC0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC0_IRQHandler
B .
PUBWEAK TEMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TEMP_IRQHandler
B .
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RNG_IRQHandler
B .
PUBWEAK ECB_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ECB_IRQHandler
B .
PUBWEAK CCM_AAR_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CCM_AAR_IRQHandler
B .
PUBWEAK WDT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WDT_IRQHandler
B .
PUBWEAK RTC1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC1_IRQHandler
B .
PUBWEAK QDEC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
QDEC_IRQHandler
B .
PUBWEAK LPCOMP_COMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
LPCOMP_COMP_IRQHandler
B .
PUBWEAK SWI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SWI0_IRQHandler
B .
PUBWEAK SWI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SWI1_IRQHandler
B .
PUBWEAK SWI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SWI2_IRQHandler
B .
PUBWEAK SWI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SWI3_IRQHandler
B .
PUBWEAK SWI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SWI4_IRQHandler
B .
PUBWEAK SWI5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SWI5_IRQHandler
B .
END

44
libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf Normal file
View File

@ -0,0 +1,44 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00016000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x000160c0;
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20002000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
/*-Sizes-*/
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0xc00;
define symbol __ICFEDIT_size_heap__ = 0x1800;
/**** End of ICF editor section. ###ICF###*/
define symbol __code_start_soft_device__ = 0x0;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
keep { section .intvec };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK,
block HEAP };
/*This is used for mbed applications build inside the Embedded workbench
Applications build with the python scritps use a hex merge so need to merge it
inside the linker. The linker can only use binary files so the hex merge is not possible
through the linker. That is why a binary is used instead of a hex image for the embedded project.
*/
if(isdefinedsymbol(SOFT_DEVICE_BIN))
{
place at address mem:__code_start_soft_device__ { section .noinit_softdevice };
}

237
libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.s Normal file
View File

@ -0,0 +1,237 @@
;; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
;; The information contained herein is confidential property of Nordic
;; Semiconductor ASA.Terms and conditions of usage are described in detail
;; in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
;; Licensees are granted free, non-transferable use of the information. NO
;; WARRANTY of ANY KIND is provided. This heading must NOT be removed from
;; the file.
;; Description message
MODULE ?cstartup
;; Stack size default : 1024
;; Heap size default : 2048
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD 0
DCD 0
DCD 0
;__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD 0
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK
DCD RADIO_IRQHandler ;RADIO
DCD UART0_IRQHandler ;UART0
DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0
DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1
DCD 0 ;Reserved
DCD GPIOTE_IRQHandler ;GPIOTE
DCD ADC_IRQHandler ;ADC
DCD TIMER0_IRQHandler ;TIMER0
DCD TIMER1_IRQHandler ;TIMER1
DCD TIMER2_IRQHandler ;TIMER2
DCD RTC0_IRQHandler ;RTC0
DCD TEMP_IRQHandler ;TEMP
DCD RNG_IRQHandler ;RNG
DCD ECB_IRQHandler ;ECB
DCD CCM_AAR_IRQHandler ;CCM_AAR
DCD WDT_IRQHandler ;WDT
DCD RTC1_IRQHandler ;RTC1
DCD QDEC_IRQHandler ;QDEC
DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP
DCD SWI0_IRQHandler ;SWI0
DCD SWI1_IRQHandler ;SWI1
DCD SWI2_IRQHandler ;SWI2
DCD SWI3_IRQHandler ;SWI3
DCD SWI4_IRQHandler ;SWI4
DCD SWI5_IRQHandler ;SWI5
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask
; Default handlers.
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =NRF_POWER_RAMON_ADDRESS
LDR R2, [R0]
MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
ORRS R2, R2, R1
STR R2, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
; Dummy exception handlers
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B .
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B .
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B .
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B .
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B .
; Dummy interrupt handlers
PUBWEAK POWER_CLOCK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
POWER_CLOCK_IRQHandler
B .
PUBWEAK RADIO_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RADIO_IRQHandler
B .
PUBWEAK UART0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART0_IRQHandler
B .
PUBWEAK SPI0_TWI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI0_TWI0_IRQHandler
B .
PUBWEAK SPI1_TWI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_TWI1_IRQHandler
B .
PUBWEAK GPIOTE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOTE_IRQHandler
B .
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC_IRQHandler
B .
PUBWEAK TIMER0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER0_IRQHandler
B .
PUBWEAK TIMER1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER1_IRQHandler
B .
PUBWEAK TIMER2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER2_IRQHandler
B .
PUBWEAK RTC0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC0_IRQHandler
B .
PUBWEAK TEMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TEMP_IRQHandler
B .
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RNG_IRQHandler
B .
PUBWEAK ECB_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ECB_IRQHandler
B .
PUBWEAK CCM_AAR_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CCM_AAR_IRQHandler
B .
PUBWEAK WDT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WDT_IRQHandler
B .
PUBWEAK RTC1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC1_IRQHandler
B .
PUBWEAK QDEC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
QDEC_IRQHandler
B .
PUBWEAK LPCOMP_COMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
LPCOMP_COMP_IRQHandler
B .
PUBWEAK SWI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SWI0_IRQHandler
B .
PUBWEAK SWI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SWI1_IRQHandler
B .
PUBWEAK SWI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SWI2_IRQHandler
B .
PUBWEAK SWI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SWI3_IRQHandler
B .
PUBWEAK SWI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SWI4_IRQHandler
B .
PUBWEAK SWI5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SWI5_IRQHandler
B .
END

BIN
libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/s110_nrf51822_7.1.0_softdevice.bin Normal file
View File

Binary file not shown.

5
libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c
View File

@ -1,6 +1,6 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor.
* Copyright (c) 2015 Nordic Semiconductor.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@ -21,7 +21,6 @@
#include "nrf51822.h"
#include "system_nrf51822.h"
#define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */
static bool is_manual_peripheral_setup_needed(void);
@ -67,7 +66,7 @@ void SystemInit(void)
// Start the external 32khz crystal oscillator.
#ifdef TARGET_HRM1017
#if defined(TARGET_DELTA_DFCM_NNN40) || defined(TARGET_HRM1017)
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_RC << CLOCK_LFCLKSRC_SRC_Pos);
#else
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos);

13
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/LPC11U68.sct Normal file
View File

@ -0,0 +1,13 @@
LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(16+47 vect * 4 bytes) = 0x100
; 32kB (0x8000) - 0x100 = 0x7F00
RW_IRAM1 (0x10000000+0x100) (0x8000-0x100) {
.ANY (+RW +ZI)
}
}

244
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/startup_LPC11U6x.s Normal file
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@ -0,0 +1,244 @@
;/**************************************************************************//**
; * @file startup_LPC11U6x.s
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
; * NXP LPC11U6x Device Series
; * @version V1.00
; * @date 22. October 2013
; *
; * @note
; * Copyright (C) 2013 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
AREA STACK, NOINIT, READWRITE, ALIGN=3
EXPORT __initial_sp
__initial_sp EQU 0x10008000 ; Top of RAM from LPC1U68
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PIN_INT0_IRQHandler ; 16+ 0 GPIO pin interrupt 0
DCD PIN_INT1_IRQHandler ; 16+ 1 GPIO pin interrupt 1
DCD PIN_INT2_IRQHandler ; 16+ 2 GPIO pin interrupt 2
DCD PIN_INT3_IRQHandler ; 16+ 3 GPIO pin interrupt 3
DCD PIN_INT4_IRQHandler ; 16+ 4 GPIO pin interrupt 4
DCD PIN_INT5_IRQHandler ; 16+ 5 GPIO pin interrupt 5
DCD PIN_INT6_IRQHandler ; 16+ 6 GPIO pin interrupt 6
DCD PIN_INT7_IRQHandler ; 16+ 7 GPIO pin interrupt 7
DCD GINT0_IRQHandler ; 16+ 8 GPIO GROUP0 interrupt
DCD GINT1_IRQHandler ; 16+ 9 GPIO GROUP1 interrupt
DCD I2C1_IRQHandler ; 16+10 I2C1 interrupt
DCD USART1_4_IRQHandler ; 16+11 Combined USART1 and USART4 interrupts
DCD USART2_3_IRQHandler ; 16+12 Combined USART2 and USART3 interrupts
DCD SCT0_1_IRQHandler ; 16+13 Combined SCT0 and SCT1 interrupts
DCD SSP1_IRQHandler ; 16+14 SSP1 interrupt
DCD I2C0_IRQHandler ; 16+15 I2C0 interrupt
DCD CT16B0_IRQHandler ; 16+16 CT16B0 interrupt
DCD CT16B1_IRQHandler ; 16+17 CT16B1 interrupt
DCD CT32B0_IRQHandler ; 16+18 CT32B0 interrupt
DCD CT32B1_IRQHandler ; 16+19 CT32B1 interrupt
DCD SSP0_IRQHandler ; 16+20 SSP0 interrupt
DCD USART0_IRQHandler ; 16+21 USART0 interrupt
DCD USB_IRQHandler ; 16+22 USB interrupt
DCD USB_FIQ_IRQHandler ; 16+23 USB_FIQ interrupt
DCD ADC_A_IRQHandler ; 16+24 Combined ADC_A end-of-sequence A and threshold crossing interrupts
DCD RTC_IRQHandler ; 16+25 RTC interrupt
DCD BOD_WDT_IRQHandler ; 16+26 Combined BOD and WWDT interrupt
DCD FLASH_IRQHandler ; 16+27 Combined flash and EEPROM controller interrupts
DCD DMA_IRQHandler ; 16+28 DMA interrupt
DCD ADC_B_IRQHandler ; 16+29 Combined ADC_A end-of-sequence A and threshold crossing interrupts
DCD USBWAKEUP_IRQHandler ; 16+30 USB_WAKEUP interrupt
DCD 0 ; 16+31 Reserved
; <h> Code Read Protection
; <o> Code Read Protection <0xFFFFFFFF=>CRP Disabled
; <0x12345678=>CRP Level 1
; <0x87654321=>CRP Level 2
; <0x43218765=>CRP Level 3 (ARE YOU SURE?)
; <0x4E697370=>NO ISP (ARE YOU SURE?)
; </h>
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Reserved_IRQHandler PROC
EXPORT Reserved_IRQHandler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PIN_INT0_IRQHandler [WEAK]
EXPORT PIN_INT1_IRQHandler [WEAK]
EXPORT PIN_INT2_IRQHandler [WEAK]
EXPORT PIN_INT3_IRQHandler [WEAK]
EXPORT PIN_INT4_IRQHandler [WEAK]
EXPORT PIN_INT5_IRQHandler [WEAK]
EXPORT PIN_INT6_IRQHandler [WEAK]
EXPORT PIN_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT USART1_4_IRQHandler [WEAK]
EXPORT USART2_3_IRQHandler [WEAK]
EXPORT SCT0_1_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT CT16B0_IRQHandler [WEAK]
EXPORT CT16B1_IRQHandler [WEAK]
EXPORT CT32B0_IRQHandler [WEAK]
EXPORT CT32B1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT USB_FIQ_IRQHandler [WEAK]
EXPORT ADC_A_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT BOD_WDT_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT ADC_B_IRQHandler [WEAK]
EXPORT USBWAKEUP_IRQHandler [WEAK]
PIN_INT0_IRQHandler
PIN_INT1_IRQHandler
PIN_INT2_IRQHandler
PIN_INT3_IRQHandler
PIN_INT4_IRQHandler
PIN_INT5_IRQHandler
PIN_INT6_IRQHandler
PIN_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
I2C1_IRQHandler
USART1_4_IRQHandler
USART2_3_IRQHandler
SCT0_1_IRQHandler
SSP1_IRQHandler
I2C0_IRQHandler
CT16B0_IRQHandler
CT16B1_IRQHandler
CT32B0_IRQHandler
CT32B1_IRQHandler
SSP0_IRQHandler
USART0_IRQHandler
USB_IRQHandler
USB_FIQ_IRQHandler
ADC_A_IRQHandler
RTC_IRQHandler
BOD_WDT_IRQHandler
FLASH_IRQHandler
DMA_IRQHandler
ADC_B_IRQHandler
USBWAKEUP_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
END

31
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/sys.cpp Normal file
View File

@ -0,0 +1,31 @@
/* mbed Microcontroller Library - stackheap
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* Setup a fixed single stack/heap memory model,
* between the top of the RW/ZI region and the stackpointer
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$RW_IRAM1$$ZI$$Limit[];
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

5
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_IAR/TARGET_LPC11U68/LPC11U68.icf
View File

@ -11,8 +11,9 @@ define symbol __ICFEDIT_region_NVIC_end__ = 0x100000FF;
define symbol __ICFEDIT_region_RAM_start__ = 0x10000100;
define symbol __ICFEDIT_region_RAM_end__ = 0x10007FDF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x800;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x2000;
/**** End of ICF editor section. ###ICF###*/
define symbol __CRP_start__ = 0x000002FC;

17
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct Normal file
View File

@ -0,0 +1,17 @@
LR_IROM1 0x00000000 0xC000 { ; load region size_region (48k)
ER_IROM1 0x00000000 0xC000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
; 8KB - 0xC0 = 0x1F40
RW_IRAM1 0x100000C0 0x1F40 {
.ANY (+RW +ZI)
}
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
.ANY (USBRAM)
}
}

325
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.s Normal file
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@ -0,0 +1,325 @@
;/*****************************************************************************
; * @file: startup_LPC11xx.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File
; * for the NXP LPC11xx Device Series
; * @version: V1.0
; * @date: 25. Nov. 2008
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2008 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; *****************************************************************************/
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
EXPORT __initial_sp
Stack_Mem SPACE Stack_Size
__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
EXPORT __heap_base
EXPORT __heap_limit
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; for LPC11Uxx (With USB)
DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
DCD FLEX_INT1_IRQHandler
DCD FLEX_INT2_IRQHandler
DCD FLEX_INT3_IRQHandler
DCD FLEX_INT4_IRQHandler
DCD FLEX_INT5_IRQHandler
DCD FLEX_INT6_IRQHandler
DCD FLEX_INT7_IRQHandler
DCD GINT0_IRQHandler
DCD GINT1_IRQHandler ; PIO0 (0:7)
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler
DCD Reserved_IRQHandler
DCD Reserved_IRQHandler
DCD SSP1_IRQHandler ; SSP1
DCD I2C_IRQHandler ; I2C
DCD TIMER16_0_IRQHandler ; 16-bit Timer0
DCD TIMER16_1_IRQHandler ; 16-bit Timer1
DCD TIMER32_0_IRQHandler ; 32-bit Timer0
DCD TIMER32_1_IRQHandler ; 32-bit Timer1
DCD SSP0_IRQHandler ; SSP0
DCD UART_IRQHandler ; UART
DCD USB_IRQHandler ; USB IRQ
DCD USB_FIQHandler ; USB FIQ
DCD ADC_IRQHandler ; A/D Converter
DCD WDT_IRQHandler ; Watchdog timer
DCD BOD_IRQHandler ; Brown Out Detect
DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler ; Reserved
DCD USBWakeup_IRQHandler ; USB wake up
DCD Reserved_IRQHandler ; Reserved
;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
; for particular peripheral.
;NMI_Handler PROC
; EXPORT NMI_Handler [WEAK]
; B .
; ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Reserved_IRQHandler PROC
EXPORT Reserved_IRQHandler [WEAK]
B .
ENDP
Default_Handler PROC
; for LPC11Uxx (With USB)
EXPORT NMI_Handler [WEAK]
EXPORT FLEX_INT0_IRQHandler [WEAK]
EXPORT FLEX_INT1_IRQHandler [WEAK]
EXPORT FLEX_INT2_IRQHandler [WEAK]
EXPORT FLEX_INT3_IRQHandler [WEAK]
EXPORT FLEX_INT4_IRQHandler [WEAK]
EXPORT FLEX_INT5_IRQHandler [WEAK]
EXPORT FLEX_INT6_IRQHandler [WEAK]
EXPORT FLEX_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT TIMER16_0_IRQHandler [WEAK]
EXPORT TIMER16_1_IRQHandler [WEAK]
EXPORT TIMER32_0_IRQHandler [WEAK]
EXPORT TIMER32_1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT UART_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT USB_FIQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT USBWakeup_IRQHandler [WEAK]
NMI_Handler
FLEX_INT0_IRQHandler
FLEX_INT1_IRQHandler
FLEX_INT2_IRQHandler
FLEX_INT3_IRQHandler
FLEX_INT4_IRQHandler
FLEX_INT5_IRQHandler
FLEX_INT6_IRQHandler
FLEX_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
SSP1_IRQHandler
I2C_IRQHandler
TIMER16_0_IRQHandler
TIMER16_1_IRQHandler
TIMER32_0_IRQHandler
TIMER32_1_IRQHandler
SSP0_IRQHandler
UART_IRQHandler
USB_IRQHandler
USB_FIQHandler
ADC_IRQHandler
WDT_IRQHandler
BOD_IRQHandler
FMC_IRQHandler
USBWakeup_IRQHandler
B .
ENDP
ALIGN
END

17
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/LPC11U34.sct Normal file
View File

@ -0,0 +1,17 @@
LR_IROM1 0x00000000 0xC000 { ; load region size_region (48k)
ER_IROM1 0x00000000 0xC000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
; 8KB - 0xC0 = 0x1F40
RW_IRAM1 0x100000C0 0x1F40 {
.ANY (+RW +ZI)
}
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
.ANY (USBRAM)
}
}

325
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/startup_LPC11xx.s Normal file
View File

@ -0,0 +1,325 @@
;/*****************************************************************************
; * @file: startup_LPC11xx.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File
; * for the NXP LPC11xx Device Series
; * @version: V1.0
; * @date: 25. Nov. 2008
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2008 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; *****************************************************************************/
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
EXPORT __initial_sp
Stack_Mem SPACE Stack_Size
__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
EXPORT __heap_base
EXPORT __heap_limit
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; for LPC11Uxx (With USB)
DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
DCD FLEX_INT1_IRQHandler
DCD FLEX_INT2_IRQHandler
DCD FLEX_INT3_IRQHandler
DCD FLEX_INT4_IRQHandler
DCD FLEX_INT5_IRQHandler
DCD FLEX_INT6_IRQHandler
DCD FLEX_INT7_IRQHandler
DCD GINT0_IRQHandler
DCD GINT1_IRQHandler ; PIO0 (0:7)
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler
DCD Reserved_IRQHandler
DCD Reserved_IRQHandler
DCD SSP1_IRQHandler ; SSP1
DCD I2C_IRQHandler ; I2C
DCD TIMER16_0_IRQHandler ; 16-bit Timer0
DCD TIMER16_1_IRQHandler ; 16-bit Timer1
DCD TIMER32_0_IRQHandler ; 32-bit Timer0
DCD TIMER32_1_IRQHandler ; 32-bit Timer1
DCD SSP0_IRQHandler ; SSP0
DCD UART_IRQHandler ; UART
DCD USB_IRQHandler ; USB IRQ
DCD USB_FIQHandler ; USB FIQ
DCD ADC_IRQHandler ; A/D Converter
DCD WDT_IRQHandler ; Watchdog timer
DCD BOD_IRQHandler ; Brown Out Detect
DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler ; Reserved
DCD USBWakeup_IRQHandler ; USB wake up
DCD Reserved_IRQHandler ; Reserved
;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
; for particular peripheral.
;NMI_Handler PROC
; EXPORT NMI_Handler [WEAK]
; B .
; ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Reserved_IRQHandler PROC
EXPORT Reserved_IRQHandler [WEAK]
B .
ENDP
Default_Handler PROC
; for LPC11Uxx (With USB)
EXPORT NMI_Handler [WEAK]
EXPORT FLEX_INT0_IRQHandler [WEAK]
EXPORT FLEX_INT1_IRQHandler [WEAK]
EXPORT FLEX_INT2_IRQHandler [WEAK]
EXPORT FLEX_INT3_IRQHandler [WEAK]
EXPORT FLEX_INT4_IRQHandler [WEAK]
EXPORT FLEX_INT5_IRQHandler [WEAK]
EXPORT FLEX_INT6_IRQHandler [WEAK]
EXPORT FLEX_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT TIMER16_0_IRQHandler [WEAK]
EXPORT TIMER16_1_IRQHandler [WEAK]
EXPORT TIMER32_0_IRQHandler [WEAK]
EXPORT TIMER32_1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT UART_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT USB_FIQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT USBWakeup_IRQHandler [WEAK]
NMI_Handler
FLEX_INT0_IRQHandler
FLEX_INT1_IRQHandler
FLEX_INT2_IRQHandler
FLEX_INT3_IRQHandler
FLEX_INT4_IRQHandler
FLEX_INT5_IRQHandler
FLEX_INT6_IRQHandler
FLEX_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
SSP1_IRQHandler
I2C_IRQHandler
TIMER16_0_IRQHandler
TIMER16_1_IRQHandler
TIMER32_0_IRQHandler
TIMER32_1_IRQHandler
SSP0_IRQHandler
UART_IRQHandler
USB_IRQHandler
USB_FIQHandler
ADC_IRQHandler
WDT_IRQHandler
BOD_IRQHandler
FMC_IRQHandler
USBWakeup_IRQHandler
B .
ENDP
ALIGN
END

17
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct Normal file
View File

@ -0,0 +1,17 @@
LR_IROM1 0x00000000 0xC000 { ; load region size_region (48k)
ER_IROM1 0x00000000 0xC000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
; 8KB - 0xC0 = 0x1F40
RW_IRAM1 0x100000C0 0x1F40 {
.ANY (+RW +ZI)
}
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
.ANY (USBRAM)
}
}

308
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.s Normal file
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@ -0,0 +1,308 @@
;/*****************************************************************************
; * @file: startup_LPC11xx.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File
; * for the NXP LPC11xx Device Series
; * @version: V1.0
; * @date: 25. Nov. 2008
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2008 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; *****************************************************************************/
__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; for LPC11Uxx (With USB)
DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
DCD FLEX_INT1_IRQHandler
DCD FLEX_INT2_IRQHandler
DCD FLEX_INT3_IRQHandler
DCD FLEX_INT4_IRQHandler
DCD FLEX_INT5_IRQHandler
DCD FLEX_INT6_IRQHandler
DCD FLEX_INT7_IRQHandler
DCD GINT0_IRQHandler
DCD GINT1_IRQHandler ; PIO0 (0:7)
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler
DCD Reserved_IRQHandler
DCD Reserved_IRQHandler
DCD SSP1_IRQHandler ; SSP1
DCD I2C_IRQHandler ; I2C
DCD TIMER16_0_IRQHandler ; 16-bit Timer0
DCD TIMER16_1_IRQHandler ; 16-bit Timer1
DCD TIMER32_0_IRQHandler ; 32-bit Timer0
DCD TIMER32_1_IRQHandler ; 32-bit Timer1
DCD SSP0_IRQHandler ; SSP0
DCD UART_IRQHandler ; UART
DCD USB_IRQHandler ; USB IRQ
DCD USB_FIQHandler ; USB FIQ
DCD ADC_IRQHandler ; A/D Converter
DCD WDT_IRQHandler ; Watchdog timer
DCD BOD_IRQHandler ; Brown Out Detect
DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler ; Reserved
DCD USBWakeup_IRQHandler ; USB wake up
DCD Reserved_IRQHandler ; Reserved
;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
; for particular peripheral.
;NMI_Handler PROC
; EXPORT NMI_Handler [WEAK]
; B .
; ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Reserved_IRQHandler PROC
EXPORT Reserved_IRQHandler [WEAK]
B .
ENDP
Default_Handler PROC
; for LPC11Uxx (With USB)
EXPORT NMI_Handler [WEAK]
EXPORT FLEX_INT0_IRQHandler [WEAK]
EXPORT FLEX_INT1_IRQHandler [WEAK]
EXPORT FLEX_INT2_IRQHandler [WEAK]
EXPORT FLEX_INT3_IRQHandler [WEAK]
EXPORT FLEX_INT4_IRQHandler [WEAK]
EXPORT FLEX_INT5_IRQHandler [WEAK]
EXPORT FLEX_INT6_IRQHandler [WEAK]
EXPORT FLEX_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT TIMER16_0_IRQHandler [WEAK]
EXPORT TIMER16_1_IRQHandler [WEAK]
EXPORT TIMER32_0_IRQHandler [WEAK]
EXPORT TIMER32_1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT UART_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT USB_FIQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT USBWakeup_IRQHandler [WEAK]
NMI_Handler
FLEX_INT0_IRQHandler
FLEX_INT1_IRQHandler
FLEX_INT2_IRQHandler
FLEX_INT3_IRQHandler
FLEX_INT4_IRQHandler
FLEX_INT5_IRQHandler
FLEX_INT6_IRQHandler
FLEX_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
SSP1_IRQHandler
I2C_IRQHandler
TIMER16_0_IRQHandler
TIMER16_1_IRQHandler
TIMER32_0_IRQHandler
TIMER32_1_IRQHandler
SSP0_IRQHandler
UART_IRQHandler
USB_IRQHandler
USB_FIQHandler
ADC_IRQHandler
WDT_IRQHandler
BOD_IRQHandler
FMC_IRQHandler
USBWakeup_IRQHandler
B .
ENDP
ALIGN
END

17
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/LPC11U34.sct Normal file
View File

@ -0,0 +1,17 @@
LR_IROM1 0x00000000 0xC000 { ; load region size_region (48k)
ER_IROM1 0x00000000 0xC000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
; 8KB - 0xC0 = 0x1F40
RW_IRAM1 0x100000C0 0x1F40 {
.ANY (+RW +ZI)
}
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
.ANY (USBRAM)
}
}

308
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/startup_LPC11xx.s Normal file
View File

@ -0,0 +1,308 @@
;/*****************************************************************************
; * @file: startup_LPC11xx.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File
; * for the NXP LPC11xx Device Series
; * @version: V1.0
; * @date: 25. Nov. 2008
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2008 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; *****************************************************************************/
__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; for LPC11Uxx (With USB)
DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
DCD FLEX_INT1_IRQHandler
DCD FLEX_INT2_IRQHandler
DCD FLEX_INT3_IRQHandler
DCD FLEX_INT4_IRQHandler
DCD FLEX_INT5_IRQHandler
DCD FLEX_INT6_IRQHandler
DCD FLEX_INT7_IRQHandler
DCD GINT0_IRQHandler
DCD GINT1_IRQHandler ; PIO0 (0:7)
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler
DCD Reserved_IRQHandler
DCD Reserved_IRQHandler
DCD SSP1_IRQHandler ; SSP1
DCD I2C_IRQHandler ; I2C
DCD TIMER16_0_IRQHandler ; 16-bit Timer0
DCD TIMER16_1_IRQHandler ; 16-bit Timer1
DCD TIMER32_0_IRQHandler ; 32-bit Timer0
DCD TIMER32_1_IRQHandler ; 32-bit Timer1
DCD SSP0_IRQHandler ; SSP0
DCD UART_IRQHandler ; UART
DCD USB_IRQHandler ; USB IRQ
DCD USB_FIQHandler ; USB FIQ
DCD ADC_IRQHandler ; A/D Converter
DCD WDT_IRQHandler ; Watchdog timer
DCD BOD_IRQHandler ; Brown Out Detect
DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler ; Reserved
DCD USBWakeup_IRQHandler ; USB wake up
DCD Reserved_IRQHandler ; Reserved
;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
; for particular peripheral.
;NMI_Handler PROC
; EXPORT NMI_Handler [WEAK]
; B .
; ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Reserved_IRQHandler PROC
EXPORT Reserved_IRQHandler [WEAK]
B .
ENDP
Default_Handler PROC
; for LPC11Uxx (With USB)
EXPORT NMI_Handler [WEAK]
EXPORT FLEX_INT0_IRQHandler [WEAK]
EXPORT FLEX_INT1_IRQHandler [WEAK]
EXPORT FLEX_INT2_IRQHandler [WEAK]
EXPORT FLEX_INT3_IRQHandler [WEAK]
EXPORT FLEX_INT4_IRQHandler [WEAK]
EXPORT FLEX_INT5_IRQHandler [WEAK]
EXPORT FLEX_INT6_IRQHandler [WEAK]
EXPORT FLEX_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT TIMER16_0_IRQHandler [WEAK]
EXPORT TIMER16_1_IRQHandler [WEAK]
EXPORT TIMER32_0_IRQHandler [WEAK]
EXPORT TIMER32_1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT UART_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT USB_FIQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT USBWakeup_IRQHandler [WEAK]
NMI_Handler
FLEX_INT0_IRQHandler
FLEX_INT1_IRQHandler
FLEX_INT2_IRQHandler
FLEX_INT3_IRQHandler
FLEX_INT4_IRQHandler
FLEX_INT5_IRQHandler
FLEX_INT6_IRQHandler
FLEX_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
SSP1_IRQHandler
I2C_IRQHandler
TIMER16_0_IRQHandler
TIMER16_1_IRQHandler
TIMER32_0_IRQHandler
TIMER32_1_IRQHandler
SSP0_IRQHandler
UART_IRQHandler
USB_IRQHandler
USB_FIQHandler
ADC_IRQHandler
WDT_IRQHandler
BOD_IRQHandler
FMC_IRQHandler
USBWakeup_IRQHandler
B .
ENDP
ALIGN
END

151
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.ld Normal file
View File

@ -0,0 +1,151 @@
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 48K
RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
*(.text.Reset_Handler)
/* Only vectors and code running at reset are safe to be in first 512
bytes since RAM can be mapped into this area for RAM based interrupt
vectors. */
. = 0x00000200;
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
{
*(.stack)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

151
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U34_421/LPC11U34.ld Normal file
View File

@ -0,0 +1,151 @@
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 48K
RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
*(.text.Reset_Handler)
/* Only vectors and code running at reset are safe to be in first 512
bytes since RAM can be mapped into this area for RAM based interrupt
vectors. */
. = 0x00000200;
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
{
*(.stack)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

6
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s
View File

@ -118,8 +118,8 @@ __isr_vector:
.long TIMER32_1_IRQHandler /* 35 19 CT32B1 32 bit timer 1 */
.long SSP0_IRQHandler /* 36 20 SSP */
.long UART_IRQHandler /* 37 21 UART */
.long Default_Handler /* 38 22 */
.long Default_Handler /* 39 23 */
.long USB_IRQHandler /* 38 22 USB IRQ */
.long USB_FIQHandler /* 39 23 USB FIQ */
.long ADC_IRQHandler /* 40 24 ADC end of conversion */
.long WDT_IRQHandler /* 41 25 Watchdog interrupt (WDINT) */
.long BOD_IRQHandler /* 42 26 BOD Brown-out detect */
@ -203,6 +203,8 @@ Reset_Handler:
def_irq_default_handler TIMER32_1_IRQHandler
def_irq_default_handler SSP0_IRQHandler
def_irq_default_handler UART_IRQHandler
def_irq_default_handler USB_IRQHandler
def_irq_default_handler USB_FIQHandler
def_irq_default_handler ADC_IRQHandler
def_irq_default_handler WDT_IRQHandler
def_irq_default_handler BOD_IRQHandler

2
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_IAR/LPC1347.icf
View File

@ -11,7 +11,7 @@ define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF;
define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0;
define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x800;
/**** End of ICF editor section. ###ICF###*/

5
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_IAR/LPC15xx.icf
View File

@ -11,8 +11,9 @@ define symbol __ICFEDIT_region_NVIC_end__ = 0x020000FF;
define symbol __ICFEDIT_region_RAM_start__ = 0x02000100;
define symbol __ICFEDIT_region_RAM_end__ = 0x02008FDF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x2000;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0x1200;
define symbol __ICFEDIT_size_heap__ = 0x2400;
/**** End of ICF editor section. ###ICF###*/
define symbol __CRP_start__ = 0x000002FC;

5
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_IAR/LPC17xx.icf
View File

@ -12,8 +12,9 @@ define symbol __ICFEDIT_region_RAM_start__ = 0x100000C8;
define symbol __ICFEDIT_region_RAM_end__ = 0x10007FDF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__ = 0x1000;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x2000;
/**** End of ICF editor section. ###ICF###*/
define symbol __CRP_start__ = 0x000002FC;

5
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_IAR/LPC4088.icf
View File

@ -11,8 +11,9 @@ define symbol __ICFEDIT_region_NVIC_end__ = 0x100000E7;
define symbol __ICFEDIT_region_RAM_start__ = 0x100000E8;
define symbol __ICFEDIT_region_RAM_end__ = 0x1000FFDF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__ = 0x1000;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0x2000;
define symbol __ICFEDIT_size_heap__ = 0x4000;
/**** End of ICF editor section. ###ICF###*/
define symbol __CRP_start__ = 0x000002FC;

5
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_IAR/LPC43xx.icf
View File

@ -20,8 +20,9 @@ define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_
define region AHB_RAM_region = mem:[from _AHB_RAM_start__ to _AHB_RAM_end__];
/* Stack and Heap */
define symbol __size_cstack__ = 0x800;
define symbol __size_heap__ = 0x800;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __size_cstack__ = 0x4000;
define symbol __size_heap__ = 0x8000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };

51
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h
View File

@ -368,23 +368,46 @@ typedef struct { /*!< (@ 0x40028000) WKT Structure
} LPC_WKT_TypeDef;
/*@}*/ /* end of group LPC8xx_WKT */
/*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/
typedef struct {
__IO uint32_t INTVAL;
__IO uint32_t TIMER;
__IO uint32_t CTRL;
__IO uint32_t STAT;
} MRT_Channel_cfg_Type;
typedef struct {
MRT_Channel_cfg_Type Channel[4];
uint32_t Reserved0[1];
__IO uint32_t IDLE_CH;
__IO uint32_t IRQ_FLAG;
//New, Copied from lpc824
/**
* @brief Multi-Rate Timer (MRT) (MRT)
*/
typedef struct { /*!< (@ 0x40004000) MRT Structure */
__IO uint32_t INTVAL0; /*!< (@ 0x40004000) MRT0 Time interval value register. This value
is loaded into the TIMER0 register. */
__I uint32_t TIMER0; /*!< (@ 0x40004004) MRT0 Timer register. This register reads the
value of the down-counter. */
__IO uint32_t CTRL0; /*!< (@ 0x40004008) MRT0 Control register. This register controls
the MRT0 modes. */
__IO uint32_t STAT0; /*!< (@ 0x4000400C) MRT0 Status register. */
__IO uint32_t INTVAL1; /*!< (@ 0x40004010) MRT0 Time interval value register. This value
is loaded into the TIMER0 register. */
__I uint32_t TIMER1; /*!< (@ 0x40004014) MRT0 Timer register. This register reads the
value of the down-counter. */
__IO uint32_t CTRL1; /*!< (@ 0x40004018) MRT0 Control register. This register controls
the MRT0 modes. */
__IO uint32_t STAT1; /*!< (@ 0x4000401C) MRT0 Status register. */
__IO uint32_t INTVAL2; /*!< (@ 0x40004020) MRT0 Time interval value register. This value
is loaded into the TIMER0 register. */
__I uint32_t TIMER2; /*!< (@ 0x40004024) MRT0 Timer register. This register reads the
value of the down-counter. */
__IO uint32_t CTRL2; /*!< (@ 0x40004028) MRT0 Control register. This register controls
the MRT0 modes. */
__IO uint32_t STAT2; /*!< (@ 0x4000402C) MRT0 Status register. */
__IO uint32_t INTVAL3; /*!< (@ 0x40004030) MRT0 Time interval value register. This value
is loaded into the TIMER0 register. */
__I uint32_t TIMER3; /*!< (@ 0x40004034) MRT0 Timer register. This register reads the
value of the down-counter. */
__IO uint32_t CTRL3; /*!< (@ 0x40004038) MRT0 Control register. This register controls
the MRT0 modes. */
__IO uint32_t STAT3; /*!< (@ 0x4000403C) MRT0 Status register. */
__I uint32_t RESERVED0[45];
__I uint32_t IDLE_CH; /*!< (@ 0x400040F4) Idle channel register. This register returns
the number of the first idle channel. */
__IO uint32_t IRQ_FLAG; /*!< (@ 0x400040F8) Global interrupt flag register */
} LPC_MRT_TypeDef;
/*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/
/** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter
@{

2
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_IAR/LPC810.icf
View File

@ -12,7 +12,7 @@ define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0;
define symbol __ICFEDIT_region_RAM_end__ = 0x100003FF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x100;
define symbol __ICFEDIT_size_heap__ = 0x100;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define symbol __CRP_start__ = 0x000002FC;

41
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/system_LPC8xx.c
View File

@ -100,14 +100,18 @@
// </h>
// </e>
*/
// 1 == IRC 12Mhz 2 == System Oscillator 12Mhz Xtal:
#define CLOCK_SETUP 1
//use PLL for IRC
#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
#define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000
#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
#define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000 MSEL=1 => M=2; PSEL=2 => 2P=8; PLLCLKOUT = (12x2) = 24MHz
//#define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz
#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 Select IRC
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 DIV=1 => SYSTEMCORECLK = 24 / 1 = 24MHz
//#define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
@ -235,9 +239,10 @@
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
//Replaced SystemCoreClock with MainClock
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
@ -268,46 +273,46 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK;
MainClock = __IRC_OSC_CLK;
break;
case 1: /* Input Clock to System PLL */
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK;
MainClock = __IRC_OSC_CLK;
break;
case 1: /* System oscillator */
SystemCoreClock = __SYS_OSC_CLK;
MainClock = __SYS_OSC_CLK;
break;
case 2: /* Reserved */
SystemCoreClock = 0;
MainClock = 0;
break;
case 3: /* CLKIN pin */
SystemCoreClock = __CLKIN_CLK;
MainClock = __CLKIN_CLK;
break;
}
break;
case 2: /* WDT Oscillator */
SystemCoreClock = wdt_osc;
MainClock = wdt_osc;
break;
case 3: /* System PLL Clock Out */
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
MainClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
break;
case 1: /* System oscillator */
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
MainClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
break;
case 2: /* Reserved */
SystemCoreClock = 0;
MainClock = 0;
break;
case 3: /* CLKIN pin */
SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
MainClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
break;
}
break;
}
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
SystemCoreClock = MainClock / LPC_SYSCON->SYSAHBCLKDIV;
}

4
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_IAR/LPC812.icf
View File

@ -11,8 +11,8 @@ define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF;
define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0;
define symbol __ICFEDIT_region_RAM_end__ = 0x10000FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x200;
define symbol __ICFEDIT_size_heap__ = 0x400;
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x800;
/**** End of ICF editor section. ###ICF###*/
define symbol __CRP_start__ = 0x000002FC;

2
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c
View File

@ -86,7 +86,7 @@
// <2=> Reserved
// <3=> CLKIN. External clock input.
// </h>
#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000
#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
//
// <h> Main Clock Source Select Register (MAINCLKSEL)
// <o.0..1> SEL: Clock Source for Main Clock

96
libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/RZA1H.ld
View File

@ -1,13 +1,14 @@
/* Linker script for mbed LPC1768 */
/* Linker script for mbed RZ_A1H */
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x20000000, LENGTH = 512K
RAM (rwx) : ORIGIN = 0x20080000, LENGTH = (1M)
USB_RAM(rwx) : ORIGIN = 0x20180000, LENGTH = 16K
ETH_RAM(rwx) : ORIGIN = 0x20280000, LENGTH = 16K
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x02000000
BOOT_LOADER (rx) : ORIGIN = 0x18000000, LENGTH = 0x00004000
SFLASH (rx) : ORIGIN = 0x18004000, LENGTH = 0x07FFC000
L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000
RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x00700000
RAM_NC (rwx) : ORIGIN = 0x20900000, LENGTH = 0x00100000
}
/* Linker script to place sections and symbol values. Should be used together
@ -40,9 +41,21 @@ ENTRY(Reset_Handler)
SECTIONS
{
.boot :
{
KEEP(*(.boot_loader))
} > BOOT_LOADER
.text :
{
Image$$VECTORS$$Base = .;
* (RESET)
Image$$VECTORS$$Limit = .;
. += 0x00000400;
KEEP(*(.isr_vector))
*(SVC_TABLE)
*(.text*)
KEEP(*(.init))
@ -62,31 +75,66 @@ SECTIONS
*(SORT(.dtors.*))
*(.dtors)
Image$$RO_DATA$$Base = .;
*(.rodata*)
Image$$RO_DATA$$Limit = .;
KEEP(*(.eh_frame*))
} > FLASH
} > SFLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
} > SFLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
} > SFLASH
__exidx_end = .;
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
LONG (__etext2)
LONG (__nc_data_start)
LONG (__nc_data_end - __nc_data_start)
__copy_table_end__ = .;
} > SFLASH
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
LONG (__nc_bss_start)
LONG (__nc_bss_end - __nc_bss_start)
__zero_table_end__ = .;
} > SFLASH
__etext = .;
.ttb :
{
Image$$TTB$$ZI$$Base = .;
. += 0x00004000;
Image$$TTB$$ZI$$Limit = .;
} > L_TTB
.data : AT (__etext)
{
Image$$RW_DATA$$Base = .;
__data_start__ = .;
Image$$RW_RAM1$$Base = .;
*(vtable)
*(.data*)
Image$$RW_DATA$$Limit = .;
. = ALIGN(4);
/* preinit data */
@ -116,13 +164,14 @@ SECTIONS
} > RAM
.bss :
.bss ALIGN(0x400):
{
Image$$ZI_DATA$$Base = .;
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
Image$$RW_RAM1$$ZI$$Limit = . ;
Image$$ZI_DATA$$Limit = .;
} > RAM
@ -142,6 +191,29 @@ SECTIONS
*(.stack)
} > RAM
__etext2 = __etext + SIZEOF(.data);
.nc_data : AT (__etext2)
{
Image$$RW_DATA_NC$$Base = .;
__nc_data_start = .;
*(NC_DATA)
. = ALIGN(4);
__nc_data_end = .;
Image$$RW_DATA_NC$$Limit = .;
} > RAM_NC
.nc_bss (NOLOAD) :
{
Image$$ZI_DATA_NC$$Base = .;
__nc_bss_start = .;
*(NC_BSS)
. = ALIGN(4);
__nc_bss_end = .;
Image$$ZI_DATA_NC$$Limit = .;
} > RAM_NC
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);

125
libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/irqfiq_handler.s
View File

@ -1,125 +0,0 @@
@/*******************************************************************************
@* DISCLAIMER
@* This software is supplied by Renesas Electronics Corporation and is only
@* intended for use with Renesas products. No other uses are authorized. This
@* software is owned by Renesas Electronics Corporation and is protected under
@* all applicable laws, including copyright laws.
@* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
@* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
@* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
@* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
@* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
@* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
@* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
@* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
@* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
@* Renesas reserves the right, without notice, to make changes to this software
@* and to discontinue the availability of this software. By using this software,
@* you agree to the additional terms and conditions found by accessing the
@* following link:
@* http://www.renesas.com/disclaimer
@* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
@*******************************************************************************/
@/*******************************************************************************
@* File Name : irqfiq_handler.s
@* $Rev: 823 $
@* $Date:: 2014-04-21 16:45:10 +0900#$
@* Description : IRQ, FIQ handler
@*******************************************************************************/
@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
.EQU SYS_MODE, 0x1f
@ INTC ICCIAR register address
.EQU INTC_ICCIAR_ADDR, 0xE820200C
@ INTC ICCEOIR register address
.EQU INTC_ICCEOIR_ADDR, 0xE8202010
@ INTC ICDABR0 register address
.EQU INTC_ICDABR0_ADDR, 0xE8201300
@ INTC ICDIPR0 register address
.EQU INTC_ICDIPR0_ADDR, 0xE8201400
@ INTC ICCHPIR register address
.EQU INTC_ICCHPIR_ADDR, 0xE8202018
@==================================================================
@ Entry point for the FIQ handler
@==================================================================
@ PRESERVE8
@ .section IRQ_FIQ_HANDLER, #execinstr
.text
.arm
@ IMPORT FiqHandler_Interrupt
@ IMPORT INTC_Handler_Interrupt
.global irq_handler
.global fiq_handler
@******************************************************************************
@ Function Name : fiq_handler
@ Description : This function is the assembler function executed when the FIQ
@ : interrupt is generated.
@******************************************************************************
fiq_handler:
B FiqHandler_Interrupt
@******************************************************************************
@ Function Name : irq_handler
@ Description : This function is the assembler function executed when the IRQ
@ : interrupt is generated. After saving the stack pointer and
@ : the stack for general registers and obtaining the INTC interrupt
@ : source ID, calls the IntcIrqHandler_interrupt function written
@ : in C language to execute the processing for the INTC interrupt
@ : handler corresponding to the interrupt source ID.
@ : After the INTC interrupt handler processing, restores
@ : the stack pointer and the general registers from the stack and
@ : returns from the IRQ interrupt processing.
@******************************************************************************
irq_handler:
SUB lr, lr, #4
SRSDB sp!, #SYS_MODE @;; Store LR_irq and SPSR_irq in system mode stack
CPS #SYS_MODE @;; Switch to system mode
PUSH {r0-r3, r12} @;; Store other AAPCS registers
LDR r1, =INTC_ICCHPIR_ADDR
LDR r3, [r1]
LDR r2, =INTC_ICCIAR_ADDR
LDR r0, [r2] @;; Read ICCIAR
LDR r2, =0x000003FF
AND r3, r0, r2
CMP r3, r2
BEQ end_of_handler
CMP r3, #0
BNE int_active
LDR r2, =INTC_ICDABR0_ADDR
LDR r3, [r2]
AND r3, r3, #0x00000001
CMP r3, #0
BNE int_active
LDR r2, =INTC_ICDIPR0_ADDR
LDR r3, [r2]
STR r3, [r2]
B end_of_handler
int_active:
PUSH {r0}
MOV r1, sp @;;
AND r1, r1, #4 @;; Make alignment for stack
SUB sp, sp, r1 @;;
PUSH {r1, lr}
BL INTC_Handler_Interrupt @;; First argument(r0) = ICCIAR read value
POP {r1, lr}
ADD sp, sp, r1
POP {r0}
LDR r2, =INTC_ICCEOIR_ADDR
STR r0, [r2] @;; Write ICCEOIR
end_of_handler:
POP {r0-r3, r12} @;; Restore registers
RFEIA sp! @;; Return from system mode stack using RFE
Literals3:
.LTORG
.END

623
libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s
View File

@ -16,67 +16,90 @@
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*/
.syntax unified
.extern _start
@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
.equ USR_MODE, 0x10
.equ FIQ_MODE, 0x11
.equ IRQ_MODE, 0x12
.equ SVC_MODE, 0x13
.equ ABT_MODE, 0x17
.equ UND_MODE, 0x1b
.equ SYS_MODE, 0x1f
.equ Thum_bit, 0x20 @ CPSR/SPSR Thumb bit
.equ USR_MODE , 0x10
.equ FIQ_MODE , 0x11
.equ IRQ_MODE , 0x12
.equ SVC_MODE , 0x13
.equ ABT_MODE , 0x17
.equ UND_MODE , 0x1b
.equ SYS_MODE , 0x1f
.equ Thum_bit , 0x20 @ CPSR/SPSR Thumb bit
/* Memory Model
The HEAP starts at the end of the DATA section and grows upward.
The STACK starts at the end of the RAM and grows downward.
The HEAP and stack STACK are only checked at compile time:
(DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
This is just a check for the bare minimum for the Heap+Stack area before
aborting compilation, it is not the run time limit:
Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
*/
.equ GICI_BASE , 0xe8202000
.equ ICCIAR_OFFSET , 0x0000000C
.equ ICCEOIR_OFFSET , 0x00000010
.equ ICCHPIR_OFFSET , 0x00000018
.equ GICD_BASE , 0xe8201000
.equ ICDISER0_OFFSET , 0x00000100
.equ ICDICER0_OFFSET , 0x00000180
.equ ICDISPR0_OFFSET , 0x00000200
.equ ICDABR0_OFFSET , 0x00000300
.equ ICDIPR0_OFFSET , 0x00000400
.equ Mode_USR , 0x10
.equ Mode_FIQ , 0x11
.equ Mode_IRQ , 0x12
.equ Mode_SVC , 0x13
.equ Mode_ABT , 0x17
.equ Mode_UND , 0x1B
.equ Mode_SYS , 0x1F
.equ I_Bit , 0x80 @ when I bit is set, IRQ is disabled
.equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled
.equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state
.equ GIC_ERRATA_CHECK_1, 0x000003FE
.equ GIC_ERRATA_CHECK_2, 0x000003FF
.equ Sect_Normal , 0x00005c06 @ outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
.equ Sect_Normal_Cod , 0x0000dc06 @ outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
.equ Sect_Normal_RO , 0x0000dc16 @ as Sect_Normal_Cod, but not executable
.equ Sect_Normal_RW , 0x00005c16 @ as Sect_Normal_Cod, but writeable and not executable
.equ Sect_SO , 0x00000c12 @ strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
.equ Sect_Device_RO , 0x00008c12 @ device, non-shareable, non-executable, ro, domain 0, base addr 0
.equ Sect_Device_RW , 0x00000c12 @ as Sect_Device_RO, but writeable
.equ Sect_Fault , 0x00000000 @ this translation will fault (the bottom 2 bits are important, the rest are ignored)
.equ RAM_BASE , 0x80000000
.equ VRAM_BASE , 0x18000000
.equ SRAM_BASE , 0x2e000000
.equ ETHERNET , 0x1a000000
.equ CS3_PERIPHERAL_BASE, 0x1c000000
@ Stack Configuration
.EQU UND_Stack_Size , 0x00000100
.EQU SVC_Stack_Size , 0x00008000
.EQU ABT_Stack_Size , 0x00000100
.EQU FIQ_Stack_Size , 0x00000100
.EQU IRQ_Stack_Size , 0x00008000
.EQU USR_Stack_Size , 0x00004000
.EQU ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0xc00
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.space ISR_Stack_Size
__initial_sp:
.space USR_Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
__AStackLimit:
.space Stack_Size
.size __AStackLimit, . - __AStackLimit
__AStackTop:
.size __AStackTop, . - __AStackTop
__BStackLimit:
.space Stack_Size
.size __BStackLimit, . - __StackLimit
__BStackTop:
.size __BStackTop, . - __BStackTop
__CStackLimit:
.space Stack_Size
.size __CStackLimit, . - __CStackLimit
__CStackTop:
.size __CStackTop, . - __CStackTop
@ Heap Configuration
.EQU Heap_Size , 0x00080000
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x800
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
@ -84,164 +107,426 @@ __HeapBase:
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.long 0xe59ff018 // 0x00
.long 0xe59ff018 // 0x04
.long 0xe59ff018 // 0x08
.long 0xe59ff018 // 0x0c
.long 0xe59ff018 // 0x10
.long 0xe59ff018 // 0x14
.long 0xe59ff018 // 0x18
.long 0xe59ff018 // 0x1c
.long 0xe59ff018 // 0x00
.long 0xe59ff018 // 0x04
.long 0xe59ff018 // 0x08
.long 0xe59ff018 // 0x0c
.long 0xe59ff018 // 0x10
.long 0xe59ff018 // 0x14
.long 0xe59ff018 // 0x18
.long 0xe59ff018 // 0x1c
.long Reset_Handler /* 0x20 */
.long undefinedInstruction /* 0x24 */
.long softwareInterrupt /* 0x28 */
.long prefetchAboart /* 0x2c */
.long dataAbort /* 0x30 */
.long 0 /* Reserved */
.long irq_handler /* IRQ */
.long fiq_handler /* FIQ */
.long Reset_Handler /* 0x20 */
.long Undef_Handler /* 0x24 */
.long SVC_Handler /* 0x28 */
.long PAbt_Handler /* 0x2c */
.long DAbt_Handler /* 0x30 */
.long 0 /* Reserved */
.long IRQ_Handler /* IRQ */
.long FIQ_Handler /* FIQ */
.size __isr_vector, . - __isr_vector
.text
// .thumb
// .thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* _etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
@ Put any cores other than 0 to sleep
mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
ands r0, r0, #3
mrc p15, 0, r0, c1, c0, 0 @;; Read CP15 System Control register (SCTLR)
bic r0, r0, #(0x1 << 12) @;; Clear I bit 12 to disable I Cache
bic r0, r0, #(0x1 << 2) @;; Clear C bit 2 to disable D Cache
bic r0, r0, #0x1 @;; Clear M bit 0 to disable MMU
mcr p15, 0, r0, c1, c0, 0 @;; Write value back to CP15 System Control register
@;; SVC Mode(Default)
LDR sp, =__AStackTop
goToSleep:
wfine
bne goToSleep
CPS #IRQ_MODE @;; IRQ Mode
LDR sp, =__BStackTop
@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
@ Enables Full Access i.e. in both privileged and non privileged modes
mrc p15, 0, r0, c1, c0, 2 @ Read Coprocessor Access Control Register (CPACR)
orr r0, r0, #(0xF << 20) @ Enable access to CP 10 & 11
mcr p15, 0, r0, c1, c0, 2 @ Write Coprocessor Access Control Register (CPACR)
isb
CPS #FIQ_MODE @;; FIQ Mode
LDR sp, =__CStackTop
@ Switch on the VFP and NEON hardware
mov r0, #0x40000000
vmsr fpexc, r0 @ Write FPEXC register, EN bit set
@CPS #ABT_MODE @;; ABT Mode
@LDR sp, =__StackTop
mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register
bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache
bic r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache
bic r0, r0, #0x1 @ Clear M bit 0 to disable MMU
bic r0, r0, #(0x1 << 11) @ Clear Z bit 11 to disable branch prediction
bic r0, r0, #(0x1 << 13) @ Clear V bit 13 to disable hivecs
mcr p15, 0, r0, c1, c0, 0 @ Write value back to CP15 System Control register
isb
CPS #SYS_MODE @;; SYS Mode
@ Set Vector Base Address Register (VBAR) to point to this application's vector table
ldr r0, =__isr_vector
mcr p15, 0, r0, c12, c0, 0
@ Setup Stack for each exceptional mode
/* ldr r0, =__StackTop */
ldr r0, =__initial_sp
@; System mode Stack pointer is set up ARM_LIB_STACK in the __main()->__entry()
LDR sp, =__StackTop
@ Enter Undefined Instruction Mode and set its Stack Pointer
msr cpsr_c, #(Mode_UND | I_Bit | F_Bit)
mov sp, r0
sub r0, r0, #UND_Stack_Size
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
@ Enter Abort Mode and set its Stack Pointer
msr cpsr_c, #(Mode_ABT | I_Bit | F_Bit)
mov sp, r0
sub r0, r0, #ABT_Stack_Size
.Lflash_to_ram_loop:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .Lflash_to_ram_loop
@ Enter FIQ Mode and set its Stack Pointer
msr cpsr_c, #(Mode_FIQ | I_Bit | F_Bit)
mov sp, r0
sub r0, r0, #FIQ_Stack_Size
ldr r0, =set_low_vector
blx r0
ldr r0, =enable_VFP
blx r0
@ Enter IRQ Mode and set its Stack Pointer
msr cpsr_c, #(Mode_IRQ | I_Bit | F_Bit)
mov sp, r0
sub r0, r0, #IRQ_Stack_Size
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
@ Enter Supervisor Mode and set its Stack Pointer
msr cpsr_c, #(Mode_SVC | I_Bit | F_Bit)
mov sp, r0
set_low_vector:
mrc p15, 0, r0, c1, c0, 0
mov r1, #0xffffdfff
and r0, r1
mcr p15, 0, r0, c1, c0, 0
@ Enter System Mode to complete initialization and enter kernel
msr cpsr_c, #(Mode_SYS | I_Bit | F_Bit)
mov sp, r0
mrc p15, 0, r0, c12, c0, 0 // vector set
mov r0, #0x20000000
mcr p15, 0, r0, c12, c0, 0 // vector set
bx lr
isb
ldr r0, =RZ_A1_SetSramWriteEnable
blx r0
.extern create_translation_table
bl create_translation_table
@ USR/SYS stack pointer will be set during kernel init
ldr r0, =SystemInit
blx r0
ldr r0, =InitMemorySubsystem
blx r0
@ fp_init
mov r0, #0x3000000
vmsr fpscr, r0
@ data sections copy
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
@ bss sections clear
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
ldr r0, =_start
bx r0
ldr r0, sf_boot @ dummy to keep boot loader area
loop_here:
b loop_here
sf_boot:
.word boot_loader
.equ VFPEnable, 0x40000000
enable_VFP:
;;
mrc p15, 0, r0, c1, c0, 2 ;
orr r0, r0, #(3 << 20) ;
orr r0, r0, #(3 << 22) ;
bic r0, r0, #(3 << 30) ;
mcr p15, 0, r0, c1, c0, 2 ;
isb ;
;;
mov r0, #VFPEnable
vmsr fpexc, r0
bx lr
;;
.pool
.size Reset_Handler, . - Reset_Handler
.text
Undef_Handler:
.global Undef_Handler
.func Undef_Handler
.extern CUndefHandler
SRSDB SP!, #Mode_UND
PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */
MRS R0, SPSR
TST R0, #T_Bit /* Check mode */
MOVEQ R1, #4 /* R1 = 4 ARM mode */
MOVNE R1, #2 /* R1 = 2 Thumb mode */
SUB R0, LR, R1
LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */
BEQ undef_cont
/* Thumb instruction */
/* Determine if it is a 32-bit Thumb instruction */
LDRH R0, [R0]
MOV R2, #0x1c
CMP R2, R0, LSR #11
BHS undef_cont /* 16-bit Thumb instruction */
/* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */
LDRH R2, [LR]
ORR R0, R2, R0, LSL #16
undef_cont:
MOV R2, LR /* Set LR to third argument */
/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
MOV R3, SP /* Ensure stack is 8-byte aligned */
AND R12, R3, #4
SUB SP, SP, R12 /* Adjust stack */
PUSH {R12, LR} /* Store stack adjustment and dummy LR */
/* R0 Offending instruction */
/* R1 =2 (Thumb) or =4 (ARM) */
BL CUndefHandler
POP {R12, LR} /* Get stack adjustment & discard dummy LR */
ADD SP, SP, R12 /* Unadjust stack */
LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */
SUB LR, LR, R0
LDR R0, [SP, #28] /* Restore stacked SPSR */
MSR SPSR_cxsf, R0
POP {R0-R4, R12} /* Restore stacked APCS registers */
ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */
MOVS PC, LR
.endfunc
PAbt_Handler:
.global PAbt_Handler
.func PAbt_Handler
.extern CPAbtHandler
SUB LR, LR, #4 /* Pre-adjust LR */
SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
MRC p15, 0, R0, c5, c0, 1 /* IFSR */
MRC p15, 0, R1, c6, c0, 2 /* IFAR */
MOV R2, LR /* Set LR to third argument */
/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
MOV R3, SP /* Ensure stack is 8-byte aligned */
AND R12, R3, #4
SUB SP, SP, R12 /* Adjust stack */
PUSH {R12, LR} /* Store stack adjustment and dummy LR */
BL CPAbtHandler
POP {R12, LR} /* Get stack adjustment & discard dummy LR */
ADD SP, SP, R12 /* Unadjust stack */
POP {R0-R4, R12} /* Restore stack APCS registers */
RFEFD SP! /* Return from exception */
.endfunc
DAbt_Handler:
.global DAbt_Handler
.func DAbt_Handler
.extern CDAbtHandler
SUB LR, LR, #8 /* Pre-adjust LR */
SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
CLREX /* State of exclusive monitors unknown after taken data abort */
MRC p15, 0, R0, c5, c0, 0 /* DFSR */
MRC p15, 0, R1, c6, c0, 0 /* DFAR */
MOV R2, LR /* Set LR to third argument */
/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
MOV R3, SP /* Ensure stack is 8-byte aligned */
AND R12, R3, #4
SUB SP, SP, R12 /* Adjust stack */
PUSH {R12, LR} /* Store stack adjustment and dummy LR */
BL CDAbtHandler
POP {R12, LR} /* Get stack adjustment & discard dummy LR */
ADD SP, SP, R12 /* Unadjust stack */
POP {R0-R4, R12} /* Restore stacked APCS registers */
RFEFD SP! /* Return from exception */
.endfunc
FIQ_Handler:
.global FIQ_Handler
.func FIQ_Handler
/* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
* so if a real FIQ Handler is implemented, this will be needed before returning:
*/
/* LDR R1, =GICI_BASE
LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
*/
B .
.endfunc
.extern SVC_Handler /* refer RTX function */
IRQ_Handler:
.global IRQ_Handler
.func IRQ_Handler
.extern IRQCount
.extern IRQTable
.extern IRQNestLevel
/* prologue */
SUB LR, LR, #4 /* Pre-adjust LR */
SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */
CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */
PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */
/* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */
MOV R3, SP /* Ensure stack is 8-byte aligned */
AND R1, R3, #4
SUB SP, SP, R1 /* Adjust stack */
PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */
LDR R0, =IRQNestLevel /* Get address of nesting counter */
LDR R1, [R0]
ADD R1, R1, #1 /* Increment nesting counter */
STR R1, [R0]
/* identify and acknowledge interrupt */
LDR R1, =GICI_BASE
LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */
LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */
DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */
/* Workaround GIC 390 errata 733075
* If the ID is not 0, then service the interrupt as normal.
* If the ID is 0 and active, then service interrupt ID 0 as normal.
* If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
* with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced.
*/
LDR R2, =GICD_BASE
LDR R3, =GIC_ERRATA_CHECK_1
CMP R0, R3
BEQ unlock_cpu
LDR R3, =GIC_ERRATA_CHECK_2
CMP R0, R3
BEQ unlock_cpu
CMP R0, #0
BNE int_active /* If the ID is not 0, then service the interrupt */
LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */
TST R3, #1
BNE int_active /* If active, then service the interrupt */
unlock_cpu:
LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */
STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */
DSB /* Ensure the write completes before continuing */
B ret_irq /* Do not service the spurious interrupt */
/* End workaround */
int_active:
LDR R2, =IRQCount /* Read number of IRQs */
LDR R2, [R2]
CMP R0, R2 /* Clean up and return if no handler */
BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */
LDR R2, =IRQTable /* Get address of handler */
LDR R2, [R2, R0, LSL #2]
CMP R2, #0 /* Clean up and return if handler address is 0 */
BEQ ret_irq
PUSH {R0,R1}
CPSIE i /* Now safe to re-enable interrupts */
BLX R2 /* Call handler. R0 will be IRQ number */
CPSID i /* Disable interrupts again */
/* write EOIR (GIC CPU Interface register) */
POP {R0,R1}
DSB /* Ensure that interrupt source is cleared before we write the EOIR */
ret_irq:
/* epilogue */
STR R0, [R1, #ICCEOIR_OFFSET]
LDR R0, =IRQNestLevel /* Get address of nesting counter */
LDR R1, [R0]
SUB R1, R1, #1 /* Decrement nesting counter */
STR R1, [R0]
POP {R1, LR} /* Get stack adjustment and restore LR_SVC */
ADD SP, SP, R1 /* Unadjust stack */
POP {R0-R3,R12} /* Restore stacked APCS registers */
RFEFD SP! /* Return from exception */
.endfunc
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler undefinedInstruction /* 0x24 */
def_default_handler softwareInterrupt /* 0x28 */
def_default_handler prefetchAboart /* 0x2c */
def_default_handler dataAbort /* 0x30 */
def_default_handler Default_Handler /* --- */
.global __disable_irq
.global __enable_irq
.global __disable_fiq
.global __enable_fiq
__disable_irq:
mrs r0,apsr @ formerly cpsr
and r0,r0,#0x80
cpsid i
bx lr
__enable_irq:
cpsie i
bx lr
def_default_handler SVC_Handler
__disable_fiq:
cpsid f
bx lr
/* User Initial Stack & Heap */
__enable_fiq:
cpsie f
bx lr
.ifdef __MICROLIB
.global __initial_sp
.global __heap_base
.global __heap_limit
.else
.extern __use_two_region_memory
.global __user_initial_stackheap
__user_initial_stackheap:
LDR R0, = __HeapBase
LDR R1, =(__StackLimit + USR_Stack_Size)
LDR R2, = (__HeapBase + Heap_Size)
LDR R3, = __StackLimit
BX LR
.endif
.end
.END

9
libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mbed_sf_boot.c
View File

@ -26,8 +26,14 @@
* $Date:: $
* @brief RZ_A1 serial flash boot loader
******************************************************************************/
#if defined (__CC_ARM)
#pragma arm section rodata = "BOOT_LOADER"
const char boot_loader[] __attribute__((used)) =
#else
const char boot_loader[] __attribute__ ((section(".boot_loader"), used)) =
#endif
{
0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,
0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,
@ -814,6 +820,7 @@ const char boot_loader[] __attribute__((used)) =
0x00,0x02,0x00,0x18,0x00,0x00,0x02,0x20,0x04,0x00,0x9F,0xE5,0x10,0x0F,0x0C,0xEE,
0x1E,0xFF,0x2F,0xE1,0x00,0x00,0x00,0x18,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
};
#if defined (__CC_ARM)
#pragma arm section
#endif

28
libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c
View File

@ -72,16 +72,31 @@ extern uint32_t Image$$RO_DATA$$Base;
extern uint32_t Image$$RW_DATA$$Base;
extern uint32_t Image$$ZI_DATA$$Base;
extern uint32_t Image$$TTB$$ZI$$Base;
#if defined( __CC_ARM )
#else
extern uint32_t Image$$RW_DATA_NC$$Base;
extern uint32_t Image$$ZI_DATA_NC$$Base;
#endif
extern uint32_t Image$$VECTORS$$Limit;
extern uint32_t Image$$RO_DATA$$Limit;
extern uint32_t Image$$RW_DATA$$Limit;
extern uint32_t Image$$ZI_DATA$$Limit;
#if defined( __CC_ARM )
#else
extern uint32_t Image$$RW_DATA_NC$$Limit;
extern uint32_t Image$$ZI_DATA_NC$$Limit;
#endif
#define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
#define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
#define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
#define ZI_DATA_SIZE (((uint32_t)&Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA$$Base >> 20) + 1)
#define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
#define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
#define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
#define ZI_DATA_SIZE (((uint32_t)&Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA$$Base >> 20) + 1)
#if defined( __CC_ARM )
#else
#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1)
#endif
static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0
@ -147,7 +162,12 @@ void create_translation_table(void)
__TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
__TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
__TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW);
#if defined( __CC_ARM )
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE, 10, Sect_Normal_NC);
#else
__TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
__TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
#endif
/* Set location of level 1 page table
; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)

90
libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c
View File

@ -41,12 +41,18 @@
#include "RZ_A1_Init.h"
#if defined(__ARMCC_VERSION)
extern void $Super$$main(void);
__asm void FPUEnable(void);
#else
void FPUEnable(void);
#endif
uint32_t IRQNestLevel;
#if defined(__ARMCC_VERSION)
/**
* Initialize the cache.
*
@ -92,6 +98,45 @@ void InitMemorySubsystem(void) {
}
#pragma pop
#elif defined(__GNUC__)
void InitMemorySubsystem(void) {
/* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
* enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
* You are not required to invalidate the main TLB, even though it is recommended for safety
* reasons. This ensures compatibility with future revisions of the processor. */
unsigned int l2_id;
/* Invalidate undefined data */
__ca9u_inv_tlb_all();
__v7_inv_icache_all();
__v7_inv_dcache_all();
__v7_inv_btac();
/* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
* invalidate in order to flush the valid data to the next level cache.
*/
__enable_mmu();
/* After MMU is enabled and data has been invalidated, enable caches and BTAC */
__enable_caches();
__enable_btac();
/* If present, you may also need to Invalidate and Enable L2 cache here */
l2_id = PL310_GetID();
if (l2_id)
{
PL310_InvAllByWay();
PL310_Enable();
}
}
#else
#endif
IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
uint32_t IRQCount = sizeof IRQTable / 4;
@ -237,8 +282,8 @@ void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
//this will be 2 when we have performed some maintenance and want to retry the instruction in thumb (state == 2)
//this will be 4 when we have performed some maintenance and want to retry the instruction in arm (state == 4)
uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
const int THUMB = 2;
const int ARM = 4;
const unsigned int THUMB = 2;
const unsigned int ARM = 4;
//Lazy VFP/NEON initialisation and switching
if ((state == ARM && ((opcode & 0x0C000000)) >> 26 == 0x03) ||
(state == THUMB && ((opcode & 0xEC000000)) >> 26 == 0x3B)) {
@ -252,6 +297,7 @@ uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
while(1);
}
#if defined(__ARMCC_VERSION)
#pragma push
#pragma arm
//Critical section, called from undef handler, so systick is disabled
@ -296,3 +342,43 @@ __asm void FPUEnable(void) {
BX LR
}
#pragma pop
#elif defined(__GNUC__)
void FPUEnable(void)
{
__asm__ __volatile__ (
".align 2 \n\t"
".arm \n\t"
"mrc p15,0,r1,c1,c0,2 \n\t"
"orr r1,r1,#0x00f00000 \n\t"
"mcr p15,0,r1,c1,c0,2 \n\t"
"vmrs r1,fpexc \n\t"
"orr r1,r1,#0x40000000 \n\t"
"vmsr fpexc,r1 \n\t"
"mov r2,#0 \n\t"
"vmov d0, r2,r2 \n\t"
"vmov d1, r2,r2 \n\t"
"vmov d2, r2,r2 \n\t"
"vmov d3, r2,r2 \n\t"
"vmov d4, r2,r2 \n\t"
"vmov d5, r2,r2 \n\t"
"vmov d6, r2,r2 \n\t"
"vmov d7, r2,r2 \n\t"
"vmov d8, r2,r2 \n\t"
"vmov d9, r2,r2 \n\t"
"vmov d10,r2,r2 \n\t"
"vmov d11,r2,r2 \n\t"
"vmov d12,r2,r2 \n\t"
"vmov d13,r2,r2 \n\t"
"vmov d14,r2,r2 \n\t"
"vmov d15,r2,r2 \n\t"
"vmrs r2,fpscr \n\t"
"ldr r3,=0x00086060 \n\t"
"and r2,r2,r3 \n\t"
"vmsr fpscr,r2 \n\t"
"bx lr \n\t"
);
}
#else
#endif

5
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/TOOLCHAIN_IAR/stm32f10x.icf
View File

@ -11,8 +11,9 @@ define symbol __ICFEDIT_region_NVIC_end__ = 0x200000EB;
define symbol __ICFEDIT_region_RAM_start__ = 0x200000EC;
define symbol __ICFEDIT_region_RAM_end__ = 0x20004FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x1700;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0xA00;
define symbol __ICFEDIT_size_heap__ = 0x1400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;

3
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f030x8.icf
View File

@ -15,7 +15,8 @@ define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
/* Stack and Heap */
define symbol __size_cstack__ = 0x800;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __size_cstack__ = 0x400;
define symbol __size_heap__ = 0x800;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };

3
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_IAR/stm32f070xb.icf
View File

@ -15,8 +15,9 @@ define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
/* Stack and Heap */
/*Heap 1/4 of ram and stack 1/8*/
define symbol __size_cstack__ = 0x800;
define symbol __size_heap__ = 0x800;
define symbol __size_heap__ = 0x1000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_IAR/stm32f072xb.icf
View File

@ -16,7 +16,7 @@ define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]
/* Stack and Heap */
define symbol __size_cstack__ = 0x800;
define symbol __size_heap__ = 0x800;
define symbol __size_heap__ = 0x1000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };

1
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_IAR/stm32f091xc.icf
View File

@ -15,6 +15,7 @@ define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
/* Stack and Heap */
/*Heap 1/4 of ram and stack 1/8*/
define symbol __size_cstack__ = 0x1000;
define symbol __size_heap__ = 0x2000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };

5
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_IAR/stm32f302x8.icf
View File

@ -15,8 +15,9 @@ define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
/* Stack and Heap */
define symbol __size_cstack__ = 0x1000;
define symbol __size_heap__ = 0x1700;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __size_cstack__ = 0x800;
define symbol __size_heap__ = 0x1000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };

3
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_IAR/stm32f303xe.icf
View File

@ -19,8 +19,9 @@ define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_
define region CCMRAM_region = mem:[from __region_CCMRAM_start__ to __region_CCMRAM_end__];
/* Stack and Heap */
/*Heap 1/4 of ram and stack 1/8*/
define symbol __size_cstack__ = 0x2000;
define symbol __size_heap__ = 0x2000;
define symbol __size_heap__ = 0x4000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };

5
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/TOOLCHAIN_IAR/stm32f334x8.icf
View File

@ -18,8 +18,9 @@ define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]
define region CCMRAM_region = mem:[from __region_CCMRAM_start__ to __region_CCMRAM_end__];
/* Stack and Heap */
define symbol __size_cstack__ = 0x800;
define symbol __size_heap__ = 0x1000;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __size_cstack__ = 0x600;
define symbol __size_heap__ = 0xC00;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };

5
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/TOOLCHAIN_IAR/stm32f429xx_flash.icf
View File

@ -13,8 +13,9 @@ define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x5FFF;
define symbol __ICFEDIT_size_heap__ = 0x5FFF;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0x6000;
define symbol __ICFEDIT_size_heap__ = 0xC000;
/**** End of ICF editor section. ###ICF###*/

5
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf
View File

@ -15,8 +15,9 @@ define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
/* Stack and Heap */
define symbol __size_cstack__ = 0x400;
define symbol __size_heap__ = 0x400;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __size_cstack__ = 0x4000;
define symbol __size_heap__ = 0x8000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };

5
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_IAR/stm32f405xx.icf
View File

@ -14,8 +14,9 @@ define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x2000;
define symbol __ICFEDIT_size_heap__ = 0x2000;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0x4000;
define symbol __ICFEDIT_size_heap__ = 0x8000;
/**** End of ICF editor section. ###ICF###*/

5
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf
View File

@ -15,8 +15,9 @@ define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
/* Stack and Heap */
define symbol __size_cstack__ = 0x400;
define symbol __size_heap__ = 0x400;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __size_cstack__ = 0x4000;
define symbol __size_heap__ = 0x8000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };

5
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/TOOLCHAIN_IAR/stm32f401xe.icf
View File

@ -11,8 +11,9 @@ define symbol __NVIC_end__ = 0x20000197; /* to be aligned on 8 bytes
define symbol __ICFEDIT_region_RAM_start__ = 0x20000198;
define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x2000;
define symbol __ICFEDIT_size_heap__ = 0x2000;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0x3000;
define symbol __ICFEDIT_size_heap__ = 0x6000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;

3
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf
View File

@ -15,8 +15,9 @@ define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
/* Stack and Heap */
/*Heap 1/4 of ram and stack 1/8*/
define symbol __size_cstack__ = 0x4000;
define symbol __size_heap__ = 0x4000;
define symbol __size_heap__ = 0x8000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };

5
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_IAR/stm32f439xx_flash.icf
View File

@ -11,8 +11,9 @@ define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0x6000;
define symbol __ICFEDIT_size_heap__ = 0xC000;
/**** End of ICF editor section. ###ICF###*/

5
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/TOOLCHAIN_IAR/STM32F407.icf
View File

@ -11,8 +11,9 @@ define symbol __NVIC_end__ = 0x20000187; /* Aligned on 8 bytes */
define symbol __ICFEDIT_region_RAM_start__ = 0x20000188;
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x2000;
define symbol __ICFEDIT_size_heap__ = 0x2000;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0x4000;
define symbol __ICFEDIT_size_heap__ = 0x8000;
/**** End of ICF editor section. ###ICF###*/
define symbol __region_RAM1_start__ = 0x10000000;

5
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_IAR/stm32l152xe.icf
View File

@ -15,8 +15,9 @@ define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
/* Stack and Heap */
define symbol __size_cstack__ = 0x1000;
define symbol __size_heap__ = 0x1000;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __size_cstack__ = 0x2800;
define symbol __size_heap__ = 0x5000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };

94
libraries/mbed/targets/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.s Normal file
View File

@ -0,0 +1,94 @@
/* Copyright (c) 2009 - 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Functions
*---------------------------------------------------------------------------*/
.text
.global __v7_all_cache
/*
* __STATIC_ASM void __v7_all_cache(uint32_t op) {
*/
__v7_all_cache:
.arm
PUSH {R4-R11}
MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
ANDS R3, R6, #0x07000000 // Extract coherency level
MOV R3, R3, LSR #23 // Total cache levels << 1
BEQ Finished // If 0, no need to clean
MOV R10, #0 // R10 holds current cache level << 1
Loop1: ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
AND R1, R1, #7 // Isolate those lower 3 bits
CMP R1, #2
BLT Skip // No cache or only instruction cache at this level
MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
ISB // ISB to sync the change to the CacheSizeID reg
MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
AND R2, R1, #7 // Extract the line length field
ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
LDR R4, =0x3FF
ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
CLZ R5, R4 // R5 is the bit position of the way size increment
LDR R7, =0x7FFF
ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Loop2: MOV R9, R4 // R9 working copy of the max way size (right aligned)
Loop3: ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
ORR R11, R11, R7, LSL R2 // Factor in the Set number
CMP R0, #0
BNE Dccsw
MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
B cont
Dccsw: CMP R0, #1
BNE Dccisw
MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
B cont
Dccisw: MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
cont: SUBS R9, R9, #1 // Decrement the Way number
BGE Loop3
SUBS R7, R7, #1 // Decrement the Set number
BGE Loop2
Skip: ADD R10, R10, #2 // increment the cache number
CMP R3, R10
BGT Loop1
Finished:
DSB
POP {R4-R11}
BX lr
.END
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

571
libraries/mbed/targets/cmsis/core_caFunc.h
View File

@ -578,7 +578,576 @@ __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
//#error GNU Compiler support not implemented for Cortex-A
/* GNU gcc specific functions */
#define MODE_USR 0x10
#define MODE_FIQ 0x11
#define MODE_IRQ 0x12
#define MODE_SVC 0x13
#define MODE_MON 0x16
#define MODE_ABT 0x17
#define MODE_HYP 0x1A
#define MODE_UND 0x1B
#define MODE_SYS 0x1F
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
{
uint32_t result;
__ASM volatile ("mrs %0, cpsr" : "=r" (result));
__ASM volatile ("cpsid i");
return(result & 0x80);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
#if 1
uint32_t result;
__ASM volatile ("mrs %0, apsr" : "=r" (result) );
return (result);
#else
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
#endif
}
/** \brief Get CPSR Register
This function returns the content of the CPSR Register.
\return CPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
{
#if 1
register uint32_t __regCPSR;
__ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
#else
register uint32_t __regCPSR __ASM("cpsr");
#endif
return(__regCPSR);
}
#if 0
/** \brief Set Stack Pointer
This function assigns the given value to the current stack pointer.
\param [in] topOfStack Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
{
register uint32_t __regSP __ASM("sp");
__regSP = topOfStack;
}
#endif
/** \brief Get link register
This function returns the value of the link register
\return Value of link register
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
{
register uint32_t __reglr __ASM("lr");
return(__reglr);
}
#if 0
/** \brief Set link register
This function sets the value of the link register
\param [in] lr LR value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
{
register uint32_t __reglr __ASM("lr");
__reglr = lr;
}
#endif
/** \brief Set Process Stack Pointer
This function assigns the given value to the USR/SYS Stack Pointer (PSP).
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
extern void __set_PSP(uint32_t topOfProcStack);
/** \brief Set User Mode
This function changes the processor state to User Mode
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
extern void __set_CPS_USR(void);
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
#if 1
uint32_t result;
__ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
return (result);
#else
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#endif
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
#if 1
__ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
#else
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
#endif
}
/** \brief Get FPEXC
This function returns the current value of the Floating Point Exception Control register.
\return Floating Point Exception Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
{
#if (__FPU_PRESENT == 1)
#if 1
uint32_t result;
__ASM volatile ("vmrs %0, fpexc" : "=r" (result));
return (result);
#else
register uint32_t __regfpexc __ASM("fpexc");
return(__regfpexc);
#endif
#else
return(0);
#endif
}
/** \brief Set FPEXC
This function assigns the given value to the Floating Point Exception Control register.
\param [in] fpscr Floating Point Exception Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
{
#if (__FPU_PRESENT == 1)
#if 1
__ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
#else
register uint32_t __regfpexc __ASM("fpexc");
__regfpexc = (fpexc);
#endif
#endif
}
/** \brief Get CPACR
This function returns the current value of the Coprocessor Access Control register.
\return Coprocessor Access Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
{
#if 1
register uint32_t __regCPACR;
__ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
#else
register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
#endif
return __regCPACR;
}
/** \brief Set CPACR
This function assigns the given value to the Coprocessor Access Control register.
\param [in] cpacr Coporcessor Acccess Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
{
#if 1
__ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
#else
register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
__regCPACR = cpacr;
#endif
__ISB();
}
/** \brief Get CBAR
This function returns the value of the Configuration Base Address register.
\return Configuration Base Address register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
#if 1
register uint32_t __regCBAR;
__ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
#else
register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
#endif
return(__regCBAR);
}
/** \brief Get TTBR0
This function returns the value of the Configuration Base Address register.
\return Translation Table Base Register 0 value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
#if 1
register uint32_t __regTTBR0;
__ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
#else
register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
#endif
return(__regTTBR0);
}
/** \brief Set TTBR0
This function assigns the given value to the Coprocessor Access Control register.
\param [in] ttbr0 Translation Table Base Register 0 value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
#if 1
__ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
#else
register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
__regTTBR0 = ttbr0;
#endif
__ISB();
}
/** \brief Get DACR
This function returns the value of the Domain Access Control Register.
\return Domain Access Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
#if 1
register uint32_t __regDACR;
__ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
#else
register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
#endif
return(__regDACR);
}
/** \brief Set DACR
This function assigns the given value to the Coprocessor Access Control register.
\param [in] dacr Domain Access Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
#if 1
__ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
#else
register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
__regDACR = dacr;
#endif
__ISB();
}
/******************************** Cache and BTAC enable ****************************************************/
/** \brief Set SCTLR
This function assigns the given value to the System Control Register.
\param [in] sctlr System Control Register, value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
{
#if 1
__ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
#else
register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
__regSCTLR = sctlr;
#endif
}
/** \brief Get SCTLR
This function returns the value of the System Control Register.
\return System Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
#if 1
register uint32_t __regSCTLR;
__ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
#else
register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
#endif
return(__regSCTLR);
}
/** \brief Enable Caches
Enable Caches
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
// Set I bit 12 to enable I Cache
// Set C bit 2 to enable D Cache
__set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
}
/** \brief Disable Caches
Disable Caches
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
// Clear I bit 12 to disable I Cache
// Clear C bit 2 to disable D Cache
__set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
__ISB();
}
/** \brief Enable BTAC
Enable BTAC
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
// Set Z bit 11 to enable branch prediction
__set_SCTLR( __get_SCTLR() | (1 << 11));
__ISB();
}
/** \brief Disable BTAC
Disable BTAC
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
// Clear Z bit 11 to disable branch prediction
__set_SCTLR( __get_SCTLR() & ~(1 << 11));
}
/** \brief Enable MMU
Enable MMU
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
// Set M bit 0 to enable the MMU
// Set AFE bit to enable simplified access permissions model
// Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
__set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
__ISB();
}
/** \brief Enable MMU
Enable MMU
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
// Clear M bit 0 to disable the MMU
__set_SCTLR( __get_SCTLR() & ~1);
__ISB();
}
/******************************** TLB maintenance operations ************************************************/
/** \brief Invalidate the whole tlb
TLBIALL. Invalidate the whole tlb
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
#if 1
__ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
#else
register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
__TLBIALL = 0;
#endif
__DSB();
__ISB();
}
/******************************** BTB maintenance operations ************************************************/
/** \brief Invalidate entire branch predictor array
BPIALL. Branch Predictor Invalidate All.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
#if 1
__ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
#else
register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
__BPIALL = 0;
#endif
__DSB(); //ensure completion of the invalidation
__ISB(); //ensure instruction fetch path sees new state
}
/******************************** L1 cache operations ******************************************************/
/** \brief Invalidate the whole I$
ICIALLU. Instruction Cache Invalidate All to PoU
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
#if 1
__ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
#else
register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
__ICIALLU = 0;
#endif
__DSB(); //ensure completion of the invalidation
__ISB(); //ensure instruction fetch path sees new I cache state
}
/** \brief Clean D$ by MVA
DCCMVAC. Data cache clean by MVA to PoC
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
#if 1
__ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
#else
register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
__DCCMVAC = (uint32_t)va;
#endif
__DMB(); //ensure the ordering of data cache maintenance operations and their effects
}
/** \brief Invalidate D$ by MVA
DCIMVAC. Data cache invalidate by MVA to PoC
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
#if 1
__ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
#else
register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
__DCIMVAC = (uint32_t)va;
#endif
__DMB(); //ensure the ordering of data cache maintenance operations and their effects
}
/** \brief Clean and Invalidate D$ by MVA
DCCIMVAC. Data cache clean and invalidate by MVA to PoC
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
#if 1
__ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
#else
register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
__DCCIMVAC = (uint32_t)va;
#endif
__DMB(); //ensure the ordering of data cache maintenance operations and their effects
}
/** \brief
* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
*/
/** \brief __v7_all_cache - helper function
*/
extern void __v7_all_cache(uint32_t op);
/** \brief Invalidate the whole D$
DCISW. Invalidate by Set/Way
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
__v7_all_cache(0);
}
/** \brief Clean the whole D$
DCCSW. Clean by Set/Way
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
__v7_all_cache(1);
}
/** \brief Clean and invalidate the whole D$
DCCISW. Clean and Invalidate by Set/Way
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
__v7_all_cache(2);
}
#include "core_ca_mmu.h"
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/

4
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/PinNames.h
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@ -234,8 +234,8 @@ typedef enum {
A1 = PTB3,
A2 = PTB10,
A3 = PTB11,
A4 = PTC10,
A5 = PTC11,
A4 = PTC11,
A5 = PTC10,
DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */

125
libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h Normal file
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@ -0,0 +1,125 @@
/* mbed Microcontroller Library
* Copyright (c) 2015 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 3
typedef enum {
NC = (int)0xFFFFFFFF,
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p4 = 4,
p5 = 5,
p6 = 6,
p7 = 7,
p8 = NC,
p9 = NC,
p10 = NC,
p11 = NC,
p12 = NC,
p13 = 13,
p14 = NC,
p15 = NC,
p16 = 16,
p17 = 17,
p18 = NC,
p19 = 19,
p20 = 20,
p21 = 21,
p22 = 22,
p23 = 23,
p24 = 24,
p25 = 25,
p26 = 26,
p27 = 27,
p28 = NC,
p29 = 29,
p30 = 30,
p31 = 31,
LED1 = p7,
LED2 = p13,
BUTTON0 = p16,
BUTTON1 = p17,
RX_PIN_NUMBER = p23,
TX_PIN_NUMBER = p25,
// mBed interface Pins
USBTX = TX_PIN_NUMBER,
USBRX = RX_PIN_NUMBER,
SPI_PSELMOSI0 = p24,
SPI_PSELMISO0 = p29,
SPI_PSELSS0 = p6,
SPI_PSELSCK0 = p21,
SPIS_PSELMOSI = p24,
SPIS_PSELMISO = p29,
SPIS_PSELSS = p6,
SPIS_PSELSCK = p21,
I2C_SDA0 = p22,
I2C_SCL0 = p20,
A0 = p0,
A1 = p1,
A2 = p2,
A3 = p3,
A4 = p4,
A5 = p5,
SWIO = p19,
VERF0 = p0,
// Not connected
CTS_PIN_NUMBER = NC,
RTS_PIN_NUMBER = NC,
SPI_PSELMOSI1 = NC,
SPI_PSELMISO1 = NC,
SPI_PSELSS1 = NC,
SPI_PSELSCK1 = NC,
LED3 = NC,
LED4 = NC
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

57
libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h Normal file
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@ -0,0 +1,57 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_PORTIN 1
#define DEVICE_PORTOUT 1
#define DEVICE_PORTINOUT 1
#define DEVICE_INTERRUPTIN 1
#define DEVICE_ANALOGIN 1
#define DEVICE_ANALOGOUT 0
#define DEVICE_SERIAL 1
#define DEVICE_I2C 1
#define DEVICE_I2CSLAVE 0
#define DEVICE_SPI 1
#define DEVICE_SPISLAVE 1
#define DEVICE_CAN 0
#define DEVICE_RTC 0
#define DEVICE_ETHERNET 0
#define DEVICE_PWMOUT 1
#define DEVICE_SEMIHOST 0
#define DEVICE_LOCALFILESYSTEM 0
#define DEVICE_SLEEP 1
#define DEVICE_DEBUG_AWARENESS 1
#define DEVICE_STDIO_MESSAGES 0
#define DEVICE_ERROR_PATTERN 1
#include "objects.h"
#endif

37
libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c Normal file
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@ -0,0 +1,37 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "cmsis.h"
void mbed_sdk_init()
{
// Default SWIO setting, pull SWIO(p19) to low for turning antenna switch to BLE radiated path
NRF_GPIO->PIN_CNF[19] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN19_Clear << GPIO_OUTCLR_PIN19_Pos);
// Config External Crystal to 32MHz
NRF_CLOCK->XTALFREQ = 0x00;
NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
NRF_CLOCK->TASKS_HFCLKSTART = 1;
while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0)
{// Do nothing.
}
}

0
libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_BLE_SMURFS/PinNames.h → libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_SEEED_TINY_BLE/PinNames.h
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0
libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_BLE_SMURFS/device.h → libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_SEEED_TINY_BLE/device.h
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0
libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/i2c_api.c Executable file → Normal file
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71
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralNames.h Normal file
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@ -0,0 +1,71 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)LPC_USART_BASE
} UARTName;
typedef enum {
I2C_0 = (int)LPC_I2C_BASE
} I2CName;
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2,
ADC0_3,
ADC0_4,
ADC0_5,
ADC0_6,
ADC0_7
} ADCName;
typedef enum {
SPI_0 = (int)LPC_SSP0_BASE,
SPI_1 = (int)LPC_SSP1_BASE
} SPIName;
typedef enum {
PWM_1 = 0,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7,
PWM_8,
PWM_9,
PWM_10,
PWM_11
} PWMName;
#define STDIO_UART_TX UART_TX
#define STDIO_UART_RX UART_RX
#define STDIO_UART UART_0
#ifdef __cplusplus
}
#endif
#endif

117
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralPins.c Normal file
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@ -0,0 +1,117 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************ADC***************/
const PinMap PinMap_ADC[] = {
{P0_11, ADC0_0, 0x02},
{P0_12, ADC0_1, 0x02},
{P0_13, ADC0_2, 0x02},
{P0_14, ADC0_3, 0x02},
{P0_15, ADC0_4, 0x02},
{P0_16, ADC0_5, 0x01},
{P0_22, ADC0_6, 0x01},
{P0_23, ADC0_7, 0x01},
{NC , NC , 0 }
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{P0_5, I2C_0, 1},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{P0_4, I2C_0, 1},
{NC , NC, 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{P0_19, UART_0, 1},
{P1_13, UART_0, 3},
{P1_27, UART_0, 2},
{ NC , NC , 0}
};
const PinMap PinMap_UART_RX[] = {
{P0_18, UART_0, 1},
{P1_14, UART_0, 3},
{P1_26, UART_0, 2},
{NC , NC , 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
{P0_6 , SPI_0, 0x02},
{P0_10, SPI_0, 0x02},
{P1_29, SPI_0, 0x01},
{P1_15, SPI_1, 0x03},
{P1_20, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{P0_9 , SPI_0, 0x01},
{P0_21, SPI_1, 0x02},
{P1_22, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{P0_8 , SPI_0, 0x01},
{P0_22, SPI_1, 0x03},
{P1_21, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{P0_2 , SPI_0, 0x01},
{P1_19, SPI_1, 0x02},
{P1_23, SPI_1, 0x02},
{NC , NC , 0}
};
/************PWM***************/
/* To have a PWM where we can change both the period and the duty cycle,
* we need an entire timer. With the following conventions:
* * MR3 is used for the PWM period
* * MR0, MR1, MR2 are used for the duty cycle
*/
const PinMap PinMap_PWM[] = {
/* CT16B0 */
{P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */
{P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */
{P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */
/* CT16B1 */
{P0_21, PWM_4, 1}, /* MR0 */
{P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */
/* CT32B0 */
{P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */
{P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */
{P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */
/* CT32B1 */
{P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */
{P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */
{P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */
{NC, NC, 0}
};

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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
// LPC11U Pin Names
P0_0 = 0,
P0_1 = 1,
P0_2 = 2,
P0_3 = 3,
P0_4 = 4,
P0_5 = 5,
P0_6 = 6,
P0_7 = 7,
P0_8 = 8,
P0_9 = 9,
P0_10 = 10,
P0_11 = 11,
P0_12 = 12,
P0_13 = 13,
P0_14 = 14,
P0_15 = 15,
P0_16 = 16,
P0_17 = 17,
P0_18 = 18,
P0_19 = 19,
P0_20 = 20,
P0_21 = 21,
P0_22 = 22,
P0_23 = 23,
P0_24 = 24,
P0_25 = 25,
P0_26 = 26,
P0_27 = 27,
P1_0 = 32,
P1_1 = 33,
P1_2 = 34,
P1_3 = 35,
P1_4 = 36,
P1_5 = 37,
P1_6 = 38,
P1_7 = 39,
P1_8 = 40,
P1_9 = 41,
P1_10 = 42,
P1_11 = 43,
P1_12 = 44,
P1_13 = 45,
P1_14 = 46,
P1_15 = 47,
P1_16 = 48,
P1_17 = 49,
P1_18 = 50,
P1_19 = 51,
P1_20 = 52,
P1_21 = 53,
P1_22 = 54,
P1_23 = 55,
P1_24 = 56,
P1_25 = 57,
P1_26 = 58,
P1_27 = 59,
P1_28 = 60,
P1_29 = 61,
P1_31 = 63,
// MicroNFCBoard pin names
M_RST = P0_0,
M_BOOT = P0_1,
M_RXD = P0_18,
M_TXD = P0_19,
M_SCL = P0_4,
M_SDA = P0_5,
M_D0 = P0_20,
M_A0 = P0_16,
M_A1 = P0_15,
M_A2 = P0_14,
M_A3 = P0_13,
M_SCK = P0_10,
M_MOSI = P0_9,
M_MISO = P0_8,
M_NCS = P0_2,
M_IRQ = P0_7,
// MicroNFCBoard pin numbers
p4 = M_RST,
p5 = M_BOOT,
p6 = M_RXD,
p7 = M_TXD,
p8 = M_SCL,
p9 = M_SDA,
p10 = M_D0,
p11 = M_IRQ,
p12 = M_NCS,
p13 = M_MISO,
p14 = M_MOSI,
p15 = M_SCK,
p16 = M_A3,
p17 = M_A2,
p18 = M_A1,
p19 = M_A0,
// Other Pin Names
LED1 = P0_11,
LED2 = P0_12,
// Alias to have correct blue lights of death pattern
LED3 = LED2,
LED4 = LED1,
UART_TX = M_TXD,
UART_RX = M_RXD,
// Not connected
NC = (int)0xFFFFFFFF,
// Standard but not supported pins
USBTX = NC,
USBRX = NC,
} PinName;
typedef enum {
CHANNEL0 = FLEX_INT0_IRQn,
CHANNEL1 = FLEX_INT1_IRQn,
CHANNEL2 = FLEX_INT2_IRQn,
CHANNEL3 = FLEX_INT3_IRQn,
CHANNEL4 = FLEX_INT4_IRQn,
CHANNEL5 = FLEX_INT5_IRQn,
CHANNEL6 = FLEX_INT6_IRQn,
CHANNEL7 = FLEX_INT7_IRQn
} Channel;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4,
PullDefault = PullDown
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/device.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_PORTIN 1
#define DEVICE_PORTOUT 1
#define DEVICE_PORTINOUT 1
#define DEVICE_INTERRUPTIN 1
#define DEVICE_ANALOGIN 1
#define DEVICE_ANALOGOUT 0
#define DEVICE_SERIAL 1
#define DEVICE_I2C 1
#define DEVICE_I2CSLAVE 1
#define DEVICE_SPI 1
#define DEVICE_SPISLAVE 1
#define DEVICE_CAN 0
#define DEVICE_RTC 0
#define DEVICE_ETHERNET 0
#define DEVICE_PWMOUT 1
#define DEVICE_SEMIHOST 0
#define DEVICE_LOCALFILESYSTEM 0
#define DEVICE_ID_LENGTH 32
#define DEVICE_MAC_OFFSET 20
#define DEVICE_SLEEP 1
#define DEVICE_DEBUG_AWARENESS 0
#define DEVICE_STDIO_MESSAGES 0
#define DEVICE_ERROR_PATTERN 1
#include "objects.h"
#endif

71
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PeripheralNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)LPC_USART_BASE
} UARTName;
typedef enum {
I2C_0 = (int)LPC_I2C_BASE
} I2CName;
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2,
ADC0_3,
ADC0_4,
ADC0_5,
ADC0_6,
ADC0_7
} ADCName;
typedef enum {
SPI_0 = (int)LPC_SSP0_BASE,
SPI_1 = (int)LPC_SSP1_BASE
} SPIName;
typedef enum {
PWM_1 = 0,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7,
PWM_8,
PWM_9,
PWM_10,
PWM_11
} PWMName;
#define STDIO_UART_TX UART_TX
#define STDIO_UART_RX UART_RX
#define STDIO_UART UART_0
#ifdef __cplusplus
}
#endif
#endif

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PeripheralPins.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************ADC***************/
const PinMap PinMap_ADC[] = {
{P0_11, ADC0_0, 0x02},
{P0_12, ADC0_1, 0x02},
{P0_13, ADC0_2, 0x02},
{P0_14, ADC0_3, 0x02},
{P0_15, ADC0_4, 0x02},
{P0_16, ADC0_5, 0x01},
{P0_22, ADC0_6, 0x01},
{P0_23, ADC0_7, 0x01},
{NC , NC , 0 }
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{P0_5, I2C_0, 1},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{P0_4, I2C_0, 1},
{NC , NC, 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{P0_19, UART_0, 1},
{P1_13, UART_0, 3},
{P1_27, UART_0, 2},
{ NC , NC , 0}
};
const PinMap PinMap_UART_RX[] = {
{P0_18, UART_0, 1},
{P1_14, UART_0, 3},
{P1_26, UART_0, 2},
{NC , NC , 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
{P0_6 , SPI_0, 0x02},
{P0_10, SPI_0, 0x02},
{P1_29, SPI_0, 0x01},
{P1_15, SPI_1, 0x03},
{P1_20, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{P0_9 , SPI_0, 0x01},
{P0_21, SPI_1, 0x02},
{P1_22, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{P0_8 , SPI_0, 0x01},
{P0_22, SPI_1, 0x03},
{P1_21, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{P0_2 , SPI_0, 0x01},
{P1_19, SPI_1, 0x02},
{P1_23, SPI_1, 0x02},
{NC , NC , 0}
};
/************PWM***************/
/* To have a PWM where we can change both the period and the duty cycle,
* we need an entire timer. With the following conventions:
* * MR3 is used for the PWM period
* * MR0, MR1, MR2 are used for the duty cycle
*/
const PinMap PinMap_PWM[] = {
/* CT16B0 */
{P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */
{P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */
{P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */
/* CT16B1 */
{P0_21, PWM_4, 1}, /* MR0 */
{P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */
/* CT32B0 */
{P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */
{P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */
{P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */
/* CT32B1 */
{P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */
{P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */
{P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */
{NC, NC, 0}
};

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PinNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
// LPC11U Pin Names
P0_0 = 0,
P0_1 = 1,
P0_2 = 2,
P0_3 = 3,
P0_4 = 4,
P0_5 = 5,
P0_6 = 6,
P0_7 = 7,
P0_8 = 8,
P0_9 = 9,
P0_10 = 10,
P0_11 = 11,
P0_12 = 12,
P0_13 = 13,
P0_14 = 14,
P0_15 = 15,
P0_16 = 16,
P0_17 = 17,
P0_18 = 18,
P0_19 = 19,
P0_20 = 20,
P0_21 = 21,
P0_22 = 22,
P0_23 = 23,
P0_24 = 24,
P0_25 = 25,
P0_26 = 26,
P0_27 = 27,
P1_0 = 32,
P1_1 = 33,
P1_2 = 34,
P1_3 = 35,
P1_4 = 36,
P1_5 = 37,
P1_6 = 38,
P1_7 = 39,
P1_8 = 40,
P1_9 = 41,
P1_10 = 42,
P1_11 = 43,
P1_12 = 44,
P1_13 = 45,
P1_14 = 46,
P1_15 = 47,
P1_16 = 48,
P1_17 = 49,
P1_18 = 50,
P1_19 = 51,
P1_20 = 52,
P1_21 = 53,
P1_22 = 54,
P1_23 = 55,
P1_24 = 56,
P1_25 = 57,
P1_26 = 58,
P1_27 = 59,
P1_28 = 60,
P1_29 = 61,
P1_31 = 63,
// Other mbed Pin Names
LED1 = P0_7,
LED2 = P0_7,
LED3 = P0_7,
LED4 = P0_7,
UART_TX = P0_19,
UART_RX = P0_18,
// Not connected
NC = (int)0xFFFFFFFF,
// Standard but not supported pins
USBTX = NC,
USBRX = NC,
} PinName;
typedef enum {
CHANNEL0 = FLEX_INT0_IRQn,
CHANNEL1 = FLEX_INT1_IRQn,
CHANNEL2 = FLEX_INT2_IRQn,
CHANNEL3 = FLEX_INT3_IRQn,
CHANNEL4 = FLEX_INT4_IRQn,
CHANNEL5 = FLEX_INT5_IRQn,
CHANNEL6 = FLEX_INT6_IRQn,
CHANNEL7 = FLEX_INT7_IRQn
} Channel;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4,
PullDefault = PullDown
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/device.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_PORTIN 1
#define DEVICE_PORTOUT 1
#define DEVICE_PORTINOUT 1
#define DEVICE_INTERRUPTIN 1
#define DEVICE_ANALOGIN 1
#define DEVICE_ANALOGOUT 0
#define DEVICE_SERIAL 1
#define DEVICE_I2C 1
#define DEVICE_I2CSLAVE 1
#define DEVICE_SPI 1
#define DEVICE_SPISLAVE 1
#define DEVICE_CAN 0
#define DEVICE_RTC 0
#define DEVICE_ETHERNET 0
#define DEVICE_PWMOUT 1
#define DEVICE_SEMIHOST 0
#define DEVICE_LOCALFILESYSTEM 0
#define DEVICE_ID_LENGTH 32
#define DEVICE_MAC_OFFSET 20
#define DEVICE_SLEEP 1
#define DEVICE_DEBUG_AWARENESS 0
#define DEVICE_STDIO_MESSAGES 0
#define DEVICE_ERROR_PATTERN 1
#include "objects.h"
#endif

0
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/PeripheralNames.h → libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/PeripheralNames.h
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0
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/PinNames.h → libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/PinNames.h
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0
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/analogin_api.c → libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/analogin_api.c
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0
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/can_api.c → libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/can_api.c
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0
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/ethernet_api.c → libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c
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