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FastModels: add FVP_MPS2_M0 target support 

add cmsis drivers and toolchain scripts for FVP_MPS2_M0
pull/6862/head
Qinghao Shi 2018-05-14 11:33:57 +01:00
parent ce2c21a1f4
commit 67abec3998
14 changed files with 2812 additions and 0 deletions
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722
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/CMSDK_CM0.h Normal file
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/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2018 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* @file CMSDK_CM0.h
* @brief CMSIS Core Peripheral Access Layer Header File for
* CMSDK_CM0 Device
*
*******************************************************************************/
#ifndef CMSDK_CM0_H
#define CMSDK_CM0_H
#ifdef __cplusplus
extern "C" {
#endif
/* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn
{
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */
UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */
UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */
PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */
TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
SPI_IRQn = 11, /*!< SPI Interrupt */
UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */
ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */
I2S_IRQn = 14, /*!< I2S Interrupt */
TSC_IRQn = 15, /*!< Touch Screen Interrupt */
PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */
PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */
UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */
UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */
UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */
UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */
ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */
SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */
PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */
PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */
PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */
PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */
PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */
PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */
PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */
PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */
} IRQn_Type;
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* -------- Configuration of the Cortex-M0 Processor and Core Peripherals ------- */
#define __CM0_REV 0x0000 /* Core revision r0p0 */
#define __MPU_PRESENT 0 /* MPU present or not */
#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
#include <core_cm0.h> /* Processor and core peripherals */
#include "system_CMSDK_CM0.h" /* System Header */
/* ================================================================================ */
/* ================ Device Specific Peripheral Section ================ */
/* ================================================================================ */
/* ------------------- Start of section using anonymous unions ------------------ */
#if defined ( __CC_ARM )
#pragma push
#pragma anon_unions
#elif defined(__ICCARM__)
#pragma language=extended
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning 586
#else
#warning Not supported compiler type
#endif
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
__IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
union {
__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
};
__IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
} CMSDK_UART_TypeDef;
/* CMSDK_UART DATA Register Definitions */
#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */
#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */
#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */
#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */
#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
/*----------------------------- Timer (TIMER) -------------------------------*/
typedef struct
{
__IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
__IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
__IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
union {
__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
};
} CMSDK_TIMER_TypeDef;
/* CMSDK_TIMER CTRL Register Definitions */
#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */
#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */
#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */
#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
/*------------- Timer (TIM) --------------------------------------------------*/
typedef struct
{
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
__O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
__I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
__I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
__IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
uint32_t RESERVED0;
__IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
__I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
__IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
__O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
__I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
__I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
__IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
uint32_t RESERVED1[945];
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
} CMSDK_DUALTIMER_BOTH_TypeDef;
#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
typedef struct
{
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
__O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
__I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
__I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
__IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
} CMSDK_DUALTIMER_SINGLE_TypeDef;
#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
/*-------------------- General Purpose Input Output (GPIO) -------------------*/
typedef struct
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
uint32_t RESERVED0[2];
__IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
__IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
__IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
__IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
__IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
__IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
__IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
__IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
__IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
__IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
union {
__I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
__O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
};
uint32_t RESERVED1[241];
__IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
__IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
} CMSDK_GPIO_TypeDef;
#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */
#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
/*------------- System Control (SYSCON) --------------------------------------*/
typedef struct
{
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
__IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
__IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
} CMSDK_SYSCON_TypeDef;
#define CMSDK_SYSCON_REMAP_Pos 0
#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
/*------------- PL230 uDMA (PL230) --------------------------------------*/
typedef struct
{
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
__I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
__I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
__O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
__IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
__O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
__IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
__O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
__IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
__O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
__IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
__O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
__IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
__O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
uint32_t RESERVED0[3];
__IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
} CMSDK_PL230_TypeDef;
#define PL230_DMA_CHNL_BITS 0
#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
/*------------------- Watchdog ----------------------------------------------*/
typedef struct
{
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
__O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
__I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
__I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
uint32_t RESERVED0[762];
__IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
uint32_t RESERVED1[191];
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
}CMSDK_WATCHDOG_TypeDef;
#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
/* -------------------- End of section using anonymous unions ------------------- */
#if defined ( __CC_ARM )
#pragma pop
#elif defined(__ICCARM__)
/* leave anonymous unions enabled */
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning restore
#else
#warning Not supported compiler type
#endif
/* ================================================================================ */
/* ================ Peripheral memory map ================ */
/* ================================================================================ */
/* Peripheral and SRAM base address */
#define CMSDK_FLASH_BASE (0x00000000UL)
#define CMSDK_SRAM_BASE (0x20000000UL)
#define CMSDK_PERIPH_BASE (0x40000000UL)
#define CMSDK_RAM_BASE (0x20000000UL)
#define CMSDK_APB_BASE (0x40000000UL)
#define CMSDK_AHB_BASE (0x40010000UL)
/* APB peripherals */
#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL)
#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
#define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL)
#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
/* AHB peripherals */
#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
/* ================================================================================ */
/* ================ Peripheral declaration ================ */
/* ================================================================================ */
#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE )
#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
#ifdef __cplusplus
}
#endif
#endif /* CMSDK_M0_H */

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/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2018 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* File: smm_mps2.h
* Release: Version 1.1
*******************************************************************************/
#ifndef __SMM_MPS2_H
#define __SMM_MPS2_H
#include "peripherallink.h" /* device specific header file */
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************/
/* FPGA System Register declaration */
/******************************************************************************/
typedef struct
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved
// [1:0] : LEDs
uint32_t RESERVED1[1];
__IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons
// [31:2] : Reserved
// [1:0] : Buttons
uint32_t RESERVED2[1];
__IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter
__IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
__IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
// Increments when 32-bit prescale counter reach zero
uint32_t RESERVED3[1];
__IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler
// Bit[31:0] : reload value for prescale counter
__IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
// current value of the pre-scaler counter
// The Cycle Up Counter increment when the prescale down counter reach 0
// The pre-scaler counter is reloaded with PRESCALE after reaching 0.
uint32_t RESERVED4[9];
__IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
// [31:10] : Reserved
// [9] : SHIELD_1_SPI_nCS
// [8] : SHIELD_0_SPI_nCS
// [7] : ADC_SPI_nCS
// [6] : CLCD_BL_CTRL
// [5] : CLCD_RD
// [4] : CLCD_RS
// [3] : CLCD_RESET
// [2] : RESERVED
// [1] : SPI_nSS
// [0] : CLCD_CS
} MPS2_FPGAIO_TypeDef;
// MISC register bit definitions
#define CLCD_CS_Pos 0
#define CLCD_CS_Msk (1UL<<CLCD_CS_Pos)
#define SPI_nSS_Pos 1
#define SPI_nSS_Msk (1UL<<SPI_nSS_Pos)
#define CLCD_RESET_Pos 3
#define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos)
#define CLCD_RS_Pos 4
#define CLCD_RS_Msk (1UL<<CLCD_RS_Pos)
#define CLCD_RD_Pos 5
#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
#define CLCD_BL_Pos 6
#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
#define ADC_nCS_Pos 7
#define ADC_nCS_Msk (1UL<<ADC_nCS_Pos)
#define SHIELD_0_nCS_Pos 8
#define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos)
#define SHIELD_1_nCS_Pos 9
#define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos)
/******************************************************************************/
/* SCC Register declaration */
/******************************************************************************/
typedef struct //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved
// [0] 1 : REMAP BlockRam to ZBT
__IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs
// [31:8] : Reserved
// [7:0] : MCC LEDs
uint32_t RESERVED0[1];
__I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
// [31:8] : Reserved
// [7:0] : These bits indicate state of the MCC switches
__I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision
// [31:4] : Reserved
// [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
uint32_t RESERVED1[35];
__IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register
// [31:0] : Data
__IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register
// [31:0] : Data
__IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register
// [31] : Start (generates interrupt on write to this bit)
// [30] : R/W access
// [29:26] : Reserved
// [25:20] : Function value
// [19:12] : Reserved
// [11:0] : Device (value of 0/1/2 for supported clocks)
__IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information
// [31:2] : Reserved
// [1] : Error
// [0] : Complete
__IO uint32_t RESERVED2[20];
__IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register
// [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
// [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
// [15:1] : Reserved
// [0] : This bit indicates if all enabled DLLs are locked
uint32_t RESERVED3[957];
__I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register
// [31:24] : FPGA build number
// [23:20] : V2M-MPS2 target board revision (A = 0, B = 1)
// [19:11] : Reserved
// [10] : if “1” SCC_SW register has been implemented
// [9] : if “1” SCC_LED register has been implemented
// [8] : if “1” DLL lock register has been implemented
// [7:0] : number of SCC configuration register
__I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image
// [31:24] : Implementer ID: 0x41 = ARM
// [23:20] : Application note IP variant number
// [19:16] : IP Architecture: 0x4 =AHB
// [15:4] : Primary part number: 386 = AN386
// [3:0] : Application note IP revision number
} MPS2_SCC_TypeDef;
/******************************************************************************/
/* SSP Peripheral declaration */
/******************************************************************************/
typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
// [31:16] : Reserved
// [15:8] : Serial clock rate
// [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
// [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
// [5:4] : Frame format
// [3:0] : Data Size Select
__IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
// [31:4] : Reserved
// [3] : Slave-mode output disable
// [2] : Master or slave mode select
// [1] : Synchronous serial port enable
// [0] : Loop back mode
__IO uint32_t DR; // Offset: 0x008 (R/W) Data register
// [31:16] : Reserved
// [15:0] : Transmit/Receive FIFO
__I uint32_t SR; // Offset: 0x00C (R/ ) Status register
// [31:5] : Reserved
// [4] : PrimeCell SSP busy flag
// [3] : Receive FIFO full
// [2] : Receive FIFO not empty
// [1] : Transmit FIFO not full
// [0] : Transmit FIFO empty
__IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
// [31:8] : Reserved
// [8:0] : Clock prescale divisor
__IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
// [31:4] : Reserved
// [3] : Transmit FIFO interrupt mask
// [2] : Receive FIFO interrupt mask
// [1] : Receive timeout interrupt mask
// [0] : Receive overrun interrupt mask
__I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
// [31:4] : Reserved
// [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
// [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
// [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
// [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
__I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
// [31:4] : Reserved
// [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
// [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
// [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
// [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
__O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
// [31:2] : Reserved
// [1] : Clears the SSPRTINTR interrupt
// [0] : Clears the SSPRORINTR interrupt
__IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
// [31:2] : Reserved
// [1] : Transmit DMA Enable
// [0] : Receive DMA Enable
} MPS2_SSP_TypeDef;
// SSP_CR0 Control register 0
#define SSP_CR0_DSS_Pos 0 // Data Size Select
#define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos)
#define SSP_CR0_FRF_Pos 4 // Frame Format Select
#define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos)
#define SSP_CR0_SPO_Pos 6 // SSPCLKOUT polarity
#define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos)
#define SSP_CR0_SPH_Pos 7 // SSPCLKOUT phase
#define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos)
#define SSP_CR0_SCR_Pos 8 // Serial Clock Rate (divide)
#define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos)
#define SSP_CR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
#define SSP_CR0_FRF_MOT 0x0000 // Frame format, Motorola
#define SSP_CR0_DSS_8 0x0007 // Data packet size, 8bits
#define SSP_CR0_DSS_16 0x000F // Data packet size, 16bits
// SSP_CR1 Control register 1
#define SSP_CR1_LBM_Pos 0 // Loop Back Mode
#define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos)
#define SSP_CR1_SSE_Pos 1 // Serial port enable
#define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos)
#define SSP_CR1_MS_Pos 2 // Master or Slave mode
#define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos)
#define SSP_CR1_SOD_Pos 3 // Slave Output mode Disable
#define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos)
// SSP_SR Status register
#define SSP_SR_TFE_Pos 0 // Transmit FIFO empty
#define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos)
#define SSP_SR_TNF_Pos 1 // Transmit FIFO not full
#define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos)
#define SSP_SR_RNE_Pos 2 // Receive FIFO not empty
#define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos)
#define SSP_SR_RFF_Pos 3 // Receive FIFO full
#define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos)
#define SSP_SR_BSY_Pos 4 // Busy
#define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos)
// SSP_CPSR Clock prescale register
#define SSP_CPSR_CPD_Pos 0 // Clock prescale divisor
#define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos)
#define SSP_CPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
// SSPIMSC Interrupt mask set and clear register
#define SSP_IMSC_RORIM_Pos 0 // Receive overrun not Masked
#define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos)
#define SSP_IMSC_RTIM_Pos 1 // Receive timeout not Masked
#define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos)
#define SSP_IMSC_RXIM_Pos 2 // Receive FIFO not Masked
#define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos)
#define SSP_IMSC_TXIM_Pos 3 // Transmit FIFO not Masked
#define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos)
// SSPRIS Raw interrupt status register
#define SSP_RIS_RORRIS_Pos 0 // Raw Overrun interrupt flag
#define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos)
#define SSP_RIS_RTRIS_Pos 1 // Raw Timemout interrupt flag
#define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos)
#define SSP_RIS_RXRIS_Pos 2 // Raw Receive interrupt flag
#define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos)
#define SSP_RIS_TXRIS_Pos 3 // Raw Transmit interrupt flag
#define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos)
// SSPMIS Masked interrupt status register
#define SSP_MIS_RORMIS_Pos 0 // Masked Overrun interrupt flag
#define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos)
#define SSP_MIS_RTMIS_Pos 1 // Masked Timemout interrupt flag
#define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos)
#define SSP_MIS_RXMIS_Pos 2 // Masked Receive interrupt flag
#define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos)
#define SSP_MIS_TXMIS_Pos 3 // Masked Transmit interrupt flag
#define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos)
// SSPICR Interrupt clear register
#define SSP_ICR_RORIC_Pos 0 // Clears Overrun interrupt flag
#define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos)
#define SSP_ICR_RTIC_Pos 1 // Clears Timemout interrupt flag
#define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos)
// SSPDMACR DMA control register
#define SSP_DMACR_RXDMAE_Pos 0 // Enable Receive FIFO DMA
#define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos)
#define SSP_DMACR_TXDMAE_Pos 1 // Enable Transmit FIFO DMA
#define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos)
/******************************************************************************/
/* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/
typedef struct
{
union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
};
__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
} MPS2_I2C_TypeDef;
#define SDA 1 << 1
#define SCL 1 << 0
/******************************************************************************/
/* Audio I2S Peripheral declaration */
/******************************************************************************/
typedef struct
{
/*!< Offset: 0x000 CONTROL Register (R/W) */
__IO uint32_t CONTROL; // <h> CONTROL </h>
// <o.0> TX Enable
// <0=> TX disabled
// <1=> TX enabled
// <o.1> TX IRQ Enable
// <0=> TX IRQ disabled
// <1=> TX IRQ enabled
// <o.2> RX Enable
// <0=> RX disabled
// <1=> RX enabled
// <o.3> RX IRQ Enable
// <0=> RX IRQ disabled
// <1=> RX IRQ enabled
// <o.10..8> TX Buffer Water Level
// <0=> / IRQ triggers when any space available
// <1=> / IRQ triggers when more than 1 space available
// <2=> / IRQ triggers when more than 2 space available
// <3=> / IRQ triggers when more than 3 space available
// <4=> Undefined!
// <5=> Undefined!
// <6=> Undefined!
// <7=> Undefined!
// <o.14..12> RX Buffer Water Level
// <0=> Undefined!
// <1=> / IRQ triggers when less than 1 space available
// <2=> / IRQ triggers when less than 2 space available
// <3=> / IRQ triggers when less than 3 space available
// <4=> / IRQ triggers when less than 4 space available
// <5=> Undefined!
// <6=> Undefined!
// <7=> Undefined!
// <o.16> FIFO reset
// <0=> Normal operation
// <1=> FIFO reset
// <o.17> Audio Codec reset
// <0=> Normal operation
// <1=> Assert audio Codec reset
/*!< Offset: 0x004 STATUS Register (R/ ) */
__I uint32_t STATUS; // <h> STATUS </h>
// <o.0> TX Buffer alert
// <0=> TX buffer don't need service yet
// <1=> TX buffer need service
// <o.1> RX Buffer alert
// <0=> RX buffer don't need service yet
// <1=> RX buffer need service
// <o.2> TX Buffer Empty
// <0=> TX buffer have data
// <1=> TX buffer empty
// <o.3> TX Buffer Full
// <0=> TX buffer not full
// <1=> TX buffer full
// <o.4> RX Buffer Empty
// <0=> RX buffer have data
// <1=> RX buffer empty
// <o.5> RX Buffer Full
// <0=> RX buffer not full
// <1=> RX buffer full
union {
/*!< Offset: 0x008 Error Status Register (R/ ) */
__I uint32_t ERROR; // <h> ERROR </h>
// <o.0> TX error
// <0=> Okay
// <1=> TX overrun/underrun
// <o.1> RX error
// <0=> Okay
// <1=> RX overrun/underrun
/*!< Offset: 0x008 Error Clear Register ( /W) */
__O uint32_t ERRORCLR; // <h> ERRORCLR </h>
// <o.0> TX error
// <0=> Okay
// <1=> Clear TX error
// <o.1> RX error
// <0=> Okay
// <1=> Clear RX error
};
/*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
// <o.9..0> TX error (default 0x80)
/*!< Offset: 0x010 Transmit Buffer ( /W) */
__O uint32_t TXBUF; // <h> Transmit buffer </h>
// <o.15..0> Right channel
// <o.31..16> Left channel
/*!< Offset: 0x014 Receive Buffer (R/ ) */
__I uint32_t RXBUF; // <h> Receive buffer </h>
// <o.15..0> Right channel
// <o.31..16> Left channel
uint32_t RESERVED1[186];
__IO uint32_t ITCR; // <h> Integration Test Control Register </h>
// <o.0> ITEN
// <0=> Normal operation
// <1=> Integration Test mode enable
__O uint32_t ITIP1; // <h> Integration Test Input Register 1</h>
// <o.0> SDIN
__O uint32_t ITOP1; // <h> Integration Test Output Register 1</h>
// <o.0> SDOUT
// <o.1> SCLK
// <o.2> LRCK
// <o.3> IRQOUT
} MPS2_I2S_TypeDef;
#define I2S_CONTROL_TXEN_Pos 0
#define I2S_CONTROL_TXEN_Msk (1UL<<I2S_CONTROL_TXEN_Pos)
#define I2S_CONTROL_TXIRQEN_Pos 1
#define I2S_CONTROL_TXIRQEN_Msk (1UL<<I2S_CONTROL_TXIRQEN_Pos)
#define I2S_CONTROL_RXEN_Pos 2
#define I2S_CONTROL_RXEN_Msk (1UL<<I2S_CONTROL_RXEN_Pos)
#define I2S_CONTROL_RXIRQEN_Pos 3
#define I2S_CONTROL_RXIRQEN_Msk (1UL<<I2S_CONTROL_RXIRQEN_Pos)
#define I2S_CONTROL_TXWLVL_Pos 8
#define I2S_CONTROL_TXWLVL_Msk (7UL<<I2S_CONTROL_TXWLVL_Pos)
#define I2S_CONTROL_RXWLVL_Pos 12
#define I2S_CONTROL_RXWLVL_Msk (7UL<<I2S_CONTROL_RXWLVL_Pos)
/* FIFO reset*/
#define I2S_CONTROL_FIFORST_Pos 16
#define I2S_CONTROL_FIFORST_Msk (1UL<<I2S_CONTROL_FIFORST_Pos)
/* Codec reset*/
#define I2S_CONTROL_CODECRST_Pos 17
#define I2S_CONTROL_CODECRST_Msk (1UL<<I2S_CONTROL_CODECRST_Pos)
#define I2S_STATUS_TXIRQ_Pos 0
#define I2S_STATUS_TXIRQ_Msk (1UL<<I2S_STATUS_TXIRQ_Pos)
#define I2S_STATUS_RXIRQ_Pos 1
#define I2S_STATUS_RXIRQ_Msk (1UL<<I2S_STATUS_RXIRQ_Pos)
#define I2S_STATUS_TXEmpty_Pos 2
#define I2S_STATUS_TXEmpty_Msk (1UL<<I2S_STATUS_TXEmpty_Pos)
#define I2S_STATUS_TXFull_Pos 3
#define I2S_STATUS_TXFull_Msk (1UL<<I2S_STATUS_TXFull_Pos)
#define I2S_STATUS_RXEmpty_Pos 4
#define I2S_STATUS_RXEmpty_Msk (1UL<<I2S_STATUS_RXEmpty_Pos)
#define I2S_STATUS_RXFull_Pos 5
#define I2S_STATUS_RXFull_Msk (1UL<<I2S_STATUS_RXFull_Pos)
#define I2S_ERROR_TXERR_Pos 0
#define I2S_ERROR_TXERR_Msk (1UL<<I2S_ERROR_TXERR_Pos)
#define I2S_ERROR_RXERR_Pos 1
#define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos)
/******************************************************************************/
/* SMSC9220 Register Definitions */
/******************************************************************************/
typedef struct // SMSC LAN9220
{
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
uint32_t RESERVED1[0x7];
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
uint32_t RESERVED2[0x7];
__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
__IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
uint32_t RESERVED3; // Reserved for future use (offset 0x60)
__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
uint32_t RESERVED4; // Reserved for future use (offset 0x94)
__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
} SMSC9220_TypeDef;
// SMSC9220 MAC Registers Indices
#define SMSC9220_MAC_CR 0x1
#define SMSC9220_MAC_ADDRH 0x2
#define SMSC9220_MAC_ADDRL 0x3
#define SMSC9220_MAC_HASHH 0x4
#define SMSC9220_MAC_HASHL 0x5
#define SMSC9220_MAC_MII_ACC 0x6
#define SMSC9220_MAC_MII_DATA 0x7
#define SMSC9220_MAC_FLOW 0x8
#define SMSC9220_MAC_VLAN1 0x9
#define SMSC9220_MAC_VLAN2 0xA
#define SMSC9220_MAC_WUFF 0xB
#define SMSC9220_MAC_WUCSR 0xC
// SMSC9220 PHY Registers Indices
#define SMSC9220_PHY_BCONTROL 0x0
#define SMSC9220_PHY_BSTATUS 0x1
#define SMSC9220_PHY_ID1 0x2
#define SMSC9220_PHY_ID2 0x3
#define SMSC9220_PHY_ANEG_ADV 0x4
#define SMSC9220_PHY_ANEG_LPA 0x5
#define SMSC9220_PHY_ANEG_EXP 0x6
#define SMSC9220_PHY_MCONTROL 0x17
#define SMSC9220_PHY_MSTATUS 0x18
#define SMSC9220_PHY_CSINDICATE 0x27
#define SMSC9220_PHY_INTSRC 0x29
#define SMSC9220_PHY_INTMASK 0x30
#define SMSC9220_PHY_CS 0x31
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
#define MPS2_SSP1_BASE (0x40020000ul) /* User SSP Base Address */
#define MPS2_SSP0_BASE (0x40021000ul) /* CLCD SSP Base Address */
#define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
#define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
#define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
#define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */
#define MPS2_SSP3_BASE (0x40026000ul) /* Shield 0 SSP Base Address */
#define MPS2_SSP4_BASE (0x40027000ul) /* Shield 1 SSP Base Address */
#define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
#define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Shield 0 I2C Base Address */
#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Shield 1 I2C Base Address */
#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
#ifdef CORTEX_M7
#define SMSC9220_BASE (0xA0000000ul) /* Ethernet SMSC9220 Base Address */
#else
#define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
#endif
#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE )
#define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE )
#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
/******************************************************************************/
/* General Function Definitions */
/******************************************************************************/
/******************************************************************************/
/* General MACRO Definitions */
/******************************************************************************/
#endif /* __SMM_MPS2_H */

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;* MPS2 CMSIS Library
;*
;* Copyright (c) 2006-2018 ARM Limited
;* All rights reserved.
;*
;* Redistribution and use in source and binary forms, with or without
;* modification, are permitted provided that the following conditions are met:
;*
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;*
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;*
;* 3. Neither the name of the copyright holder nor the names of its contributors
;* may be used to endorse or promote products derived from this software without
;* specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;* POSSIBILITY OF SUCH DAMAGE.
;*
; *************************************************************
; *** Scatter-Loading Description File ***
; *************************************************************
LR_IROM1 0x00000000 0x00400000 { ; load region size_region
ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (0x20000000+0x100) (0x400000-0x100) { ; RW data
.ANY (+RW +ZI)
}
}

270
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; MPS2 CMSIS Library
;
; Copyright (c) 2006-2018 ARM Limited
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
; specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;******************************************************************************
; @file startup_CMSDK_CM0.s
; @brief CMSIS Core Device Startup File for
; CMSDK_CM0 Device
;
;******************************************************************************
;
;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00001000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UARTRX0_Handler ; UART 0 RX Handler
DCD UARTTX0_Handler ; UART 0 TX Handler
DCD UARTRX1_Handler ; UART 1 RX Handler
DCD UARTTX1_Handler ; UART 1 TX Handler
DCD UARTRX2_Handler ; UART 2 RX Handler
DCD UARTTX2_Handler ; UART 2 TX Handler
DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler
DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler
DCD TIMER0_Handler ; TIMER 0 handler
DCD TIMER1_Handler ; TIMER 1 handler
DCD DUALTIMER_HANDLER ; Dual timer handler
DCD SPI_Handler ; SPI exceptions Handler
DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler
DCD ETHERNET_Handler ; Ethernet Overflow Handler
DCD I2S_Handler ; I2S Handler
DCD TSC_Handler ; Touch Screen handler
DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler
DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler
DCD UARTRX3_Handler ; UART 3 RX Handler
DCD UARTTX3_Handler ; UART 3 TX Handler
DCD UARTRX4_Handler ; UART 4 RX Handler
DCD UARTTX4_Handler ; UART 4 TX Handler
DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UARTRX0_Handler [WEAK]
EXPORT UARTTX0_Handler [WEAK]
EXPORT UARTRX1_Handler [WEAK]
EXPORT UARTTX1_Handler [WEAK]
EXPORT UARTRX2_Handler [WEAK]
EXPORT UARTTX2_Handler [WEAK]
EXPORT PORT0_COMB_Handler [WEAK]
EXPORT PORT1_COMB_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_HANDLER [WEAK]
EXPORT SPI_Handler [WEAK]
EXPORT UARTOVF_Handler [WEAK]
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TSC_Handler [WEAK]
EXPORT PORT2_COMB_Handler [WEAK]
EXPORT PORT3_COMB_Handler [WEAK]
EXPORT UARTRX3_Handler [WEAK]
EXPORT UARTTX3_Handler [WEAK]
EXPORT UARTRX4_Handler [WEAK]
EXPORT UARTTX4_Handler [WEAK]
EXPORT ADCSPI_Handler [WEAK]
EXPORT SHIELDSPI_Handler [WEAK]
EXPORT PORT0_0_Handler [WEAK]
EXPORT PORT0_1_Handler [WEAK]
EXPORT PORT0_2_Handler [WEAK]
EXPORT PORT0_3_Handler [WEAK]
EXPORT PORT0_4_Handler [WEAK]
EXPORT PORT0_5_Handler [WEAK]
EXPORT PORT0_6_Handler [WEAK]
EXPORT PORT0_7_Handler [WEAK]
UARTRX0_Handler
UARTTX0_Handler
UARTRX1_Handler
UARTTX1_Handler
UARTRX2_Handler
UARTTX2_Handler
PORT0_COMB_Handler
PORT1_COMB_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_HANDLER
SPI_Handler
UARTOVF_Handler
ETHERNET_Handler
I2S_Handler
TSC_Handler
PORT2_COMB_Handler
PORT3_COMB_Handler
UARTRX3_Handler
UARTTX3_Handler
UARTRX4_Handler
UARTTX4_Handler
ADCSPI_Handler
SHIELDSPI_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

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/*
* MPS2 CMSIS Library
*/
/*
* Copyright (c) 2009-2018 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.00 gcc_arm.ld
*/
/* Linker script for mbed FVP Cortex-M0 on MPS2 */
/* Linker script to configure memory regions. */
/* The length of the VECTORS region is a bit larger than
* is necessary based on the number of exception handlers.
*/
MEMORY
{
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
HEAP_SIZE = 0x4000;
STACK_SIZE = 0x1000;
/* Size of the vector table in SRAM */
M_VECTOR_RAM_SIZE = 0x140;
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
. = ALIGN(4);
} > VECTORS
.text :
{
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
.interrupts_ram :
{
. = ALIGN(4);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
. += M_VECTOR_RAM_SIZE;
. = ALIGN(4);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > RAM
.data :
{
PROVIDE(__etext = LOADADDR(.data));
. = ALIGN(4);
__data_start__ = .;
*(vtable)
*(.data)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM AT > FLASH
.uninitialized (NOLOAD):
{
. = ALIGN(32);
__uninitialized_start = .;
*(.uninitialized)
KEEP(*(.keep.uninitialized))
. = ALIGN(32);
__uninitialized_end = .;
} > RAM
.bss :
{
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > RAM
bss_size = __bss_end__ - __bss_start__;
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
} /* End of sections */

205
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/*
* MPS2 CMSIS Library
*/
/*
* Copyright (c) 2009-2018 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.00 startup_ARMCM3.S
*/
.syntax unified
.arch armv6-m
.section .vector_table,"a",%progbits
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts */
.long UARTRX0_Handler /* UART 0 RX Handler */
.long UARTTX0_Handler /* UART 0 TX Handler */
.long UARTRX1_Handler /* UART 1 RX Handler */
.long UARTTX1_Handler /* UART 1 TX Handler */
.long UARTRX2_Handler /* UART 2 RX Handler */
.long UARTTX2_Handler /* UART 2 TX Handler */
.long PORT0_COMB_Handler /* GPIO Port 0 Combined Handler */
.long PORT1_COMB_Handler /* GPIO Port 1 Combined Handler */
.long TIMER0_Handler /* TIMER 0 handler */
.long TIMER1_Handler /* TIMER 1 handler */
.long DUALTIMER_HANDLER /* Dual timer handler */
.long SPI_Handler /* SPI exceptions Handler */
.long UARTOVF_Handler /* UART 0,1,2 Overflow Handler */
.long ETHERNET_Handler /* Ethernet Overflow Handler */
.long I2S_Handler /* I2S Handler */
.long TSC_Handler /* Touch Screen handler */
.long PORT2_COMB_Handler /* GPIO Port 2 Combined Handler */
.long PORT3_COMB_Handler /* GPIO Port 3 Combined Handler */
.long UARTRX3_Handler /* UART 3 RX Handler */
.long UARTTX3_Handler /* UART 3 TX Handler */
.long UARTRX4_Handler /* UART 4 RX Handler */
.long UARTTX4_Handler /* UART 4 TX Handler */
.long ADCSPI_Handler /* SHIELD ADC SPI exceptions Handler */
.long SHIELDSPI_Handler /* SHIELD SPI exceptions Handler */
.long PORT0_0_Handler /* GPIO Port 0 pin 0 Handler */
.long PORT0_1_Handler /* GPIO Port 0 pin 1 Handler */
.long PORT0_2_Handler /* GPIO Port 0 pin 2 Handler */
.long PORT0_3_Handler /* GPIO Port 0 pin 3 Handler */
.long PORT0_4_Handler /* GPIO Port 0 pin 4 Handler */
.long PORT0_5_Handler /* GPIO Port 0 pin 5 Handler */
.long PORT0_6_Handler /* GPIO Port 0 pin 6 Handler */
.long PORT0_7_Handler /* GPIO Port 0 pin 7 Handler */
.size __isr_vector, . - __isr_vector
.section .text.Reset_Handler
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =SystemInit
blx r0
/*
* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* _etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .Lflash_to_ram_loop_end
movs r4, 0
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
/* Initialize .bss */
init_bss:
ldr r1, =__bss_start__
ldr r2, =__bss_end__
ldr r3, =bss_size
movs r0, 0
subs r2, r1
ble .L_zero_done
.L_zero:
subs r2, #4
str r0, [r1, r2]
bgt .L_zero
.L_zero_done:
system_startup:
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/*
* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers
*/
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
/* External interrupts */
def_irq_default_handler UARTRX0_Handler /* 0: UART 0 RX Handler */
def_irq_default_handler UARTTX0_Handler /* 1: UART 0 TX Handler */
def_irq_default_handler UARTRX1_Handler /* 2: UART 1 RX Handler */
def_irq_default_handler UARTTX1_Handler /* 3: UART 1 TX Handler */
def_irq_default_handler UARTRX2_Handler /* 4: UART 2 RX Handler */
def_irq_default_handler UARTTX2_Handler /* 5: UART 2 TX Handler */
def_irq_default_handler PORT0_COMB_Handler /* 6: GPIO Port 0 Combined Handler */
def_irq_default_handler PORT1_COMB_Handler /* 7: GPIO Port 1 Combined Handler */
def_irq_default_handler TIMER0_Handler /* 8: TIMER 0 handler */
def_irq_default_handler TIMER1_Handler /* 9: TIMER 1 handler */
def_irq_default_handler DUALTIMER_HANDLER /* 10: Dual timer handler */
def_irq_default_handler SPI_Handler /* 11: SPI exceptions Handler */
def_irq_default_handler UARTOVF_Handler /* 12: UART 0,1,2 Overflow Handler */
def_irq_default_handler ETHERNET_Handler /* 13: Ethernet Overflow Handler */
def_irq_default_handler I2S_Handler /* 14: I2S Handler */
def_irq_default_handler TSC_Handler /* 15: Touch Screen handler */
def_irq_default_handler PORT2_COMB_Handler /* 16: GPIO Port 2 Combined Handler */
def_irq_default_handler PORT3_COMB_Handler /* 17: GPIO Port 3 Combined Handler */
def_irq_default_handler UARTRX3_Handler /* 18: UART 3 RX Handler */
def_irq_default_handler UARTTX3_Handler /* 19: UART 3 TX Handler */
def_irq_default_handler UARTRX4_Handler /* 20: UART 4 RX Handler */
def_irq_default_handler UARTTX4_Handler /* 21: UART 4 TX Handler */
def_irq_default_handler ADCSPI_Handler /* 22: SHIELD ADC SPI exceptions Handler */
def_irq_default_handler SHIELDSPI_Handler /* 23: SHIELD SPI exceptions Handler */
def_irq_default_handler PORT0_0_Handler /* 24: GPIO Port 0 pin 0 Handler */
def_irq_default_handler PORT0_1_Handler /* 25: GPIO Port 0 pin 1 Handler */
def_irq_default_handler PORT0_2_Handler /* 26: GPIO Port 0 pin 2 Handler */
def_irq_default_handler PORT0_3_Handler /* 27: GPIO Port 0 pin 3 Handler */
def_irq_default_handler PORT0_4_Handler /* 28: GPIO Port 0 pin 4 Handler */
def_irq_default_handler PORT0_5_Handler /* 29: GPIO Port 0 pin 5 Handler */
def_irq_default_handler PORT0_6_Handler /* 30: GPIO Port 0 pin 6 Handler */
def_irq_default_handler PORT0_7_Handler /* 31: GPIO Port 0 pin 7 Handler */
.end

56
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_IAR/MPS2.icf Normal file
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/*
* MPS2 CMSIS Library
*/
/*
* Copyright (c) 2009-2018 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License) you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* The RAM region doesn't start at the beginning of the RAM address
* space to create space for the vector table copied over to the RAM by mbed.
* The space left is a bit bigger than is necessary based on the number of
* interrupt handlers.
*/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000140;
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
/*-Sizes-*/
/* Heap and Stack size */
define symbol __ICFEDIT_size_heap__ = 0x4000;
define symbol __ICFEDIT_size_cstack__ = 0x1000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
initialize by copy { readwrite };
do not initialize { section .noinit };
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

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targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_IAR/startup_MPS2.S Normal file
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;/*
; * MPS2 CMSIS Library
; */
;/*
; * Copyright (c) 2009-2018 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
; * This file is derivative of CMSIS V5.00 startup_Device.s
; */
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD 0
DCD 0
DCD 0
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD 0
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD UARTRX0_Handler ; 0: UART 0 RX Handler
DCD UARTTX0_Handler ; 1: UART 0 TX Handler
DCD UARTRX1_Handler ; 2: UART 1 RX Handler
DCD UARTTX1_Handler ; 3: UART 1 TX Handler
DCD UARTRX2_Handler ; 4: UART 2 RX Handler
DCD UARTTX2_Handler ; 5: UART 2 TX Handler
DCD PORT0_COMB_Handler ; 6: GPIO Port 0 Combined Handler
DCD PORT1_COMB_Handler ; 7: GPIO Port 1 Combined Handler
DCD TIMER0_Handler ; 8: TIMER 0 handler
DCD TIMER1_Handler ; 9: TIMER 1 handler
DCD DUALTIMER_HANDLER ; 10: Dual timer handler
DCD SPI_Handler ; 11: SPI exceptions Handler
DCD UARTOVF_Handler ; 12: UART 0,1,2 Overflow Handler
DCD ETHERNET_Handler ; 13: Ethernet Overflow Handler
DCD I2S_Handler ; 14: I2S Handler
DCD TSC_Handler ; 15: Touch Screen handler
DCD PORT2_COMB_Handler ; 16: GPIO Port 2 Combined Handler
DCD PORT3_COMB_Handler ; 17: GPIO Port 3 Combined Handler
DCD UARTRX3_Handler ; 18: UART 3 RX Handler
DCD UARTTX3_Handler ; 19: UART 3 TX Handler
DCD UARTRX4_Handler ; 20: UART 4 RX Handler
DCD UARTTX4_Handler ; 21: UART 4 TX Handler
DCD ADCSPI_Handler ; 22: SHIELD ADC SPI exceptions Handler
DCD SHIELDSPI_Handler ; 23: SHIELD SPI exceptions Handler
DCD PORT0_0_Handler ; 24: GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; 25: GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; 26: GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; 27: GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; 28: GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; 29: GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; 30: GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; 31: GPIO Port 0 pin 7 Handler
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK UARTRX0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX0_Handler
B UARTRX0_Handler
PUBWEAK UARTTX0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX0_Handler
B UARTTX0_Handler
PUBWEAK UARTRX1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX1_Handler
B UARTRX1_Handler
PUBWEAK UARTTX1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX1_Handler
B UARTTX1_Handler
PUBWEAK UARTRX2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX2_Handler
B UARTRX2_Handler
PUBWEAK UARTTX2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX2_Handler
B UARTTX2_Handler
PUBWEAK PORT0_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_COMB_Handler
B PORT0_COMB_Handler
PUBWEAK PORT1_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT1_COMB_Handler
B PORT1_COMB_Handler
PUBWEAK TIMER0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER0_Handler
B TIMER0_Handler
PUBWEAK TIMER1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER1_Handler
B TIMER1_Handler
PUBWEAK DUALTIMER_HANDLER
SECTION .text:CODE:REORDER:NOROOT(1)
DUALTIMER_HANDLER
B DUALTIMER_HANDLER
PUBWEAK SPI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI_Handler
B SPI_Handler
PUBWEAK UARTOVF_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTOVF_Handler
B UARTOVF_Handler
PUBWEAK ETHERNET_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
ETHERNET_Handler
B ETHERNET_Handler
PUBWEAK I2S_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
I2S_Handler
B I2S_Handler
PUBWEAK TSC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TSC_Handler
B TSC_Handler
PUBWEAK PORT2_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT2_COMB_Handler
B PORT2_COMB_Handler
PUBWEAK PORT3_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT3_COMB_Handler
B PORT3_COMB_Handler
PUBWEAK UARTRX3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX3_Handler
B UARTRX3_Handler
PUBWEAK UARTTX3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX3_Handler
B UARTTX3_Handler
PUBWEAK UARTRX4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX4_Handler
B UARTRX4_Handler
PUBWEAK UARTTX4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX4_Handler
B UARTTX4_Handler
PUBWEAK ADCSPI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
ADCSPI_Handler
B ADCSPI_Handler
PUBWEAK SHIELDSPI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SHIELDSPI_Handler
B SHIELDSPI_Handler
PUBWEAK PORT0_0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_0_Handler
B PORT0_0_Handler
PUBWEAK PORT0_1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_1_Handler
B PORT0_1_Handler
PUBWEAK PORT0_2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_2_Handler
B PORT0_2_Handler
PUBWEAK PORT0_3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_3_Handler
B PORT0_3_Handler
PUBWEAK PORT0_4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_4_Handler
B PORT0_4_Handler
PUBWEAK PORT0_5_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_5_Handler
B PORT0_5_Handler
PUBWEAK PORT0_6_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_6_Handler
B PORT0_6_Handler
PUBWEAK PORT0_7_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_7_Handler
B PORT0_7_Handler
END

42
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis.h Normal file
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/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2018 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* A generic CMSIS include header, pulling in MPS2 specifics
*******************************************************************************/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "CMSDK_CM0.h"
#include "SMM_MPS2.h"
#include "cmsis_nvic.h"
#endif

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targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis_nvic.c Normal file
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/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2018 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************/
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
// int i;
// Space for dynamic vectors, initialised to allocate in R/W
static volatile uint32_t* vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
// Set the vector
vectors[IRQn + 16] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
// We can always read vectors at 0x0, as the addresses are remapped
uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
// Return the vector
return vectors[IRQn + 16];
}

54
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/cmsis_nvic.h Normal file
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/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2018 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#include "cmsis.h"
#define NVIC_NUM_VECTORS (16 + 48)
#define NVIC_USER_IRQ_OFFSET 16
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/peripherallink.h Normal file
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/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2018 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* Name: Device.h
* Purpose: Include the correct device header file
*******************************************************************************/
#ifndef __DEVICE_H
#define __DEVICE_H
#if defined CMSDK_CM0
#include "CMSDK_CM0.h" /* device specific header file */
#elif defined CMSDK_CM0plus
#include "CMSDK_CM0plus.h" /* device specific header file */
#elif defined CMSDK_CM3
#include "CMSDK_CM3.h" /* device specific header file */
#elif defined CMSDK_CM4
#include "CMSDK_CM4.h" /* device specific header file */
#elif defined CMSDK_CM7
#include "CMSDK_CM7.h" /* device specific header file */
#else
#warning "no appropriate header file found!"
#endif
#endif /* __DEVICE_H */

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/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2018 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* @file system_CMSDK_CM0.c
* @brief CMSIS Device System Source File for
* CMSDK_M0 Device
*
*******************************************************************************/
#include "CMSDK_CM0.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __XTAL (50000000UL) /* Oscillator frequency */
#define __SYSTEM_CLOCK (__XTAL / 2)
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = __SYSTEM_CLOCK;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
SystemCoreClock = __SYSTEM_CLOCK;
}

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targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/system_CMSDK_CM0.h Normal file
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/* MPS2 CMSIS Library
*
* Copyright (c) 2006-2018 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************
* @file system_CMSDK_CM0.h
* @brief CMSIS Device Peripheral Access Layer Header File for
* CMSDK_CM0 Device
*
******************************************************************************/
#ifndef SYSTEM_CMSDK_CM0_H
#define SYSTEM_CMSDK_CM0_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_CMSDK_CM0_H */