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DISCO_F429ZI: align system_stm32f4xx.c file with other products

pull/1414/head
adustm 2015-11-09 10:28:55 +01:00
parent 5eccd220ea
commit 675a12c2d5
1 changed files with 16 additions and 11 deletions
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27
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.c
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f4xx.c * @file system_stm32f4xx.c
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.4.0
* @date 19-June-2014 * @date 14-August-2015
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
* *
* This file provides two functions and one global variable to be called from * This file provides two functions and one global variable to be called from
@ -38,7 +38,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -106,9 +106,9 @@
*/ */
/************************* Miscellaneous Configuration ************************/ /************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* #define DATA_IN_ExtSRAM */ /* #define DATA_IN_ExtSRAM */
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
@ -169,7 +169,7 @@ const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8,
static void SystemInit_ExtMemCtl(void); static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
void SystemClock_Config(void); void SetSysClock(void);
/** /**
* @} * @}
*/ */
@ -227,7 +227,7 @@ void SystemInit(void)
/* Configure the System clock source, PLL Multiplier and Divider factors, /* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings */ AHB/APBx prescalers and Flash settings */
SystemClock_Config(); SetSysClock();
SystemCoreClockUpdate(); SystemCoreClockUpdate();
/* Reset the timer to avoid issues after the RAM initialization */ /* Reset the timer to avoid issues after the RAM initialization */
@ -416,7 +416,7 @@ void SystemInit_ExtMemCtl(void)
RCC->AHB3ENR |= 0x00000001; RCC->AHB3ENR |= 0x00000001;
/* Configure and enable SDRAM bank1 */ /* Configure and enable SDRAM bank1 */
FMC_Bank5_6->SDCR[0] = 0x000019E0; FMC_Bank5_6->SDCR[0] = 0x000019E4;
FMC_Bank5_6->SDTR[0] = 0x01115351; FMC_Bank5_6->SDTR[0] = 0x01115351;
/* SDRAM initialization sequence */ /* SDRAM initialization sequence */
@ -549,7 +549,7 @@ void SystemInit_ExtMemCtl(void)
* generated code by STM32CubeMX 4.4.0 for board 32F429Discovery * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery
* and SYSCLK=168MHZ * and SYSCLK=168MHZ
*/ */
void SystemClock_Config(void) void SetSysClock(void)
{ {
RCC_OscInitTypeDef RCC_OscInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct;
@ -577,6 +577,9 @@ void SystemClock_Config(void)
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
// HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
} }
#elif USE_SYSCLOCK_180 != 0 #elif USE_SYSCLOCK_180 != 0
@ -584,7 +587,7 @@ void SystemClock_Config(void)
* generated code by STM32CubeMX 4.4.0 for board 32F429Discovery * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery
* and SYSCLK=180MHZ * and SYSCLK=180MHZ
*/ */
void SystemClock_Config(void) void SetSysClock(void)
{ {
RCC_OscInitTypeDef RCC_OscInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct;
@ -614,6 +617,8 @@ void SystemClock_Config(void)
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
// HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
} }
#endif #endif