diff --git a/cmsis/TARGET_CORTEX_A/TOOLCHAIN_IAR/cmain.S b/cmsis/TARGET_CORTEX_A/TOOLCHAIN_IAR/cmain.S new file mode 100644 index 0000000000..0da55009b3 --- /dev/null +++ b/cmsis/TARGET_CORTEX_A/TOOLCHAIN_IAR/cmain.S @@ -0,0 +1,101 @@ +/************************************************** + * + * Part two of the system initialization code, contains C-level + * initialization, thumb-2 only variant. + * + * $Revision: 59783 $ + * + **************************************************/ +/* Copyright 2008-2017, IAR Systems AB. + This source code is the property of IAR Systems. The source code may only + be used together with the IAR Embedded Workbench. Redistribution and use + in source and binary forms, with or without modification, is permitted + provided that the following conditions are met: + - Redistributions of source code, in whole or in part, must retain the + above copyright notice, this list of conditions and the disclaimer below. + - IAR Systems name may not be used to endorse or promote products + derived from this software without specific prior written permission. + + THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +*/ + +; -------------------------------------------------- +; Module ?cmain, C-level initialization. +; + + + SECTION SHT$$PREINIT_ARRAY:CONST:NOROOT(2) + SECTION SHT$$INIT_ARRAY:CONST:NOROOT(2) + + SECTION .text:CODE:NOROOT(2) + + PUBLIC __cmain + ;; Keep ?main for legacy reasons, it is accessed in countless instances of cstartup.s around the world... + PUBLIC ?main + EXTWEAK __iar_data_init3 + EXTWEAK __iar_argc_argv + EXTERN __low_level_init + EXTERN __call_ctors + EXTERN main + EXTERN exit + EXTERN __iar_dynamic_initialization + EXTERN mbed_sdk_init + EXTERN mbed_main + EXTERN SystemInit + + THUMB +__cmain: +?main: + +; Initialize segments. +; __segment_init and __low_level_init are assumed to use the same +; instruction set and to be reachable by BL from the ICODE segment +; (it is safest to link them in segment ICODE). + + FUNCALL __cmain, __low_level_init + bl __low_level_init + cmp r0,#0 + beq ?l1 + FUNCALL __cmain, __iar_data_init3 + bl __iar_data_init3 + MOVS r0,#0 ; No parameters + FUNCALL __cmain, mbed_sdk_init + BL mbed_sdk_init + MOVS r0,#0 ; No parameters + FUNCALL __cmain, __iar_dynamic_initialization + BL __iar_dynamic_initialization ; C++ dynamic initialization + +?l1: + REQUIRE ?l3 + + SECTION .text:CODE:NOROOT(2) + + PUBLIC _main + PUBLIC _call_main + THUMB + +__iar_init$$done: ; Copy initialization is done + +?l3: +_call_main: + MOVS r0,#0 ; No parameters + FUNCALL __cmain, __iar_argc_argv + BL __iar_argc_argv ; Maybe setup command line + + MOVS r0,#0 ; No parameters + FUNCALL __cmain, mbed_main + BL mbed_main + + FUNCALL __cmain, main + BL main +_main: + FUNCALL __cmain, exit + BL exit + + END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_IAR/weak_handler.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_IAR/weak_handler.S new file mode 100644 index 0000000000..782ce2a2bf --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_IAR/weak_handler.S @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Cortex-A Exception handlers + * + * ----------------------------------------------------------------------------- + */ + + NAME irq_weak.S + +MODE_SVC EQU 0x13 + + PRESERVE8 + + SECTION .text:CODE:NOROOT(2) + + PUBWEAK Undef_Handler +Undef_Handler + B . + + PUBWEAK SVC_Handler +SVC_Handler + B . + + PUBWEAK PAbt_Handler +PAbt_Handler + B . + + PUBWEAK DAbt_Handler +DAbt_Handler + B . + + PUBWEAK IRQ_Handler +IRQ_Handler + IMPORT IRQ_GetActiveIRQ + IMPORT IRQ_GetHandler + IMPORT IRQ_EndOfInterrupt + + SUB LR, LR, #4 ; Pre-adjust LR + SRSFD SP!, #MODE_SVC ; Save LR_irq and SPSR_irq on to the SVC stack + CPS #MODE_SVC ; Change to SVC mode + PUSH {R0-R3, R12, LR} ; Save APCS corruptible registers + + MOV R3, SP ; Move SP into R3 + AND R3, R3, #4 ; Get stack adjustment to ensure 8-byte alignment + SUB SP, SP, R3 ; Adjust stack + PUSH {R3, R4} ; Store stack adjustment(R3) and user data(R4) + + BLX IRQ_GetActiveIRQ ; Retrieve interrupt ID into R0 + MOV R4, R0 ; Move interrupt ID to R4 + + BLX IRQ_GetHandler ; Retrieve interrupt handler address for current ID + CMP R0, #0 ; Check if handler address is 0 + BEQ IRQ_End ; If 0, end interrupt and return + + CPSIE i ; Re-enable interrupts + BLX R0 ; Call IRQ handler + CPSID i ; Disable interrupts + +IRQ_End + MOV R0, R4 ; Move interrupt ID to R0 + BLX IRQ_EndOfInterrupt ; Signal end of interrupt + + POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4) + ADD SP, SP, R3 ; Unadjust stack + + POP {R0-R3, R12, LR} ; Restore stacked APCS registers + RFEFD SP! ; Return from IRQ handler + + END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/weak_handler.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/weak_handler.S new file mode 100644 index 0000000000..782ce2a2bf --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/weak_handler.S @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Cortex-A Exception handlers + * + * ----------------------------------------------------------------------------- + */ + + NAME irq_weak.S + +MODE_SVC EQU 0x13 + + PRESERVE8 + + SECTION .text:CODE:NOROOT(2) + + PUBWEAK Undef_Handler +Undef_Handler + B . + + PUBWEAK SVC_Handler +SVC_Handler + B . + + PUBWEAK PAbt_Handler +PAbt_Handler + B . + + PUBWEAK DAbt_Handler +DAbt_Handler + B . + + PUBWEAK IRQ_Handler +IRQ_Handler + IMPORT IRQ_GetActiveIRQ + IMPORT IRQ_GetHandler + IMPORT IRQ_EndOfInterrupt + + SUB LR, LR, #4 ; Pre-adjust LR + SRSFD SP!, #MODE_SVC ; Save LR_irq and SPSR_irq on to the SVC stack + CPS #MODE_SVC ; Change to SVC mode + PUSH {R0-R3, R12, LR} ; Save APCS corruptible registers + + MOV R3, SP ; Move SP into R3 + AND R3, R3, #4 ; Get stack adjustment to ensure 8-byte alignment + SUB SP, SP, R3 ; Adjust stack + PUSH {R3, R4} ; Store stack adjustment(R3) and user data(R4) + + BLX IRQ_GetActiveIRQ ; Retrieve interrupt ID into R0 + MOV R4, R0 ; Move interrupt ID to R4 + + BLX IRQ_GetHandler ; Retrieve interrupt handler address for current ID + CMP R0, #0 ; Check if handler address is 0 + BEQ IRQ_End ; If 0, end interrupt and return + + CPSIE i ; Re-enable interrupts + BLX R0 ; Call IRQ handler + CPSID i ; Disable interrupts + +IRQ_End + MOV R0, R4 ; Move interrupt ID to R0 + BLX IRQ_EndOfInterrupt ; Signal end of interrupt + + POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4) + ADD SP, SP, R3 ; Unadjust stack + + POP {R0-R3, R12, LR} ; Restore stacked APCS registers + RFEFD SP! ; Return from IRQ handler + + END