From 653b0e9499d6916c06d2bf50e5b61fa03302f13c Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Wed, 19 Jul 2017 15:04:53 +0200 Subject: [PATCH] STM32 I2C : correct async issue --- .../TARGET_STM32F1/device/stm32f1xx_hal_i2c.c | 12 +++++-- .../TARGET_STM32F2/device/stm32f2xx_hal_i2c.c | 33 +++++++++++++++-- .../TARGET_STM32F4/device/stm32f4xx_hal_i2c.c | 32 +++++++++++++++-- .../TARGET_STM32L1/device/stm32l1xx_hal_i2c.c | 36 ++++++++++++++++--- 4 files changed, 100 insertions(+), 13 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.c index 194b3cbca0..f9cf9e3771 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.c @@ -1462,7 +1462,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Generate Start */ hi2c->Instance->CR1 |= I2C_CR1_START; } - else + else if(Prev_State == I2C_STATE_MASTER_BUSY_RX) // MBED { /* Generate ReStart */ hi2c->Instance->CR1 |= I2C_CR1_START; @@ -1564,7 +1564,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, /* Generate Start */ hi2c->Instance->CR1 |= I2C_CR1_START; } - else + else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) // MBED { /* Enable Acknowledge */ hi2c->Instance->CR1 |= I2C_CR1_ACK; @@ -4008,7 +4008,7 @@ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) /* Enable Pos */ hi2c->Instance->CR1 |= I2C_CR1_POS; - + /* Disable BUF interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); } @@ -4078,6 +4078,12 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) { /* Disable Acknowledge */ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)) + { + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } } else { diff --git a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_i2c.c index 314df550a3..879d808f78 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_i2c.c @@ -1414,8 +1414,17 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Generate Start */ if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE)) { - /* Generate Start or ReStart */ + /* Generate Start condition if first transfer */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Generate Start */ hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(Prev_State == I2C_STATE_MASTER_BUSY_RX) // MBED + { + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } } /* Process Unlocked */ @@ -1504,11 +1513,23 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE)) { + /* Generate Start condition if first transfer */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME)) + { /* Enable Acknowledge */ hi2c->Instance->CR1 |= I2C_CR1_ACK; - - /* Generate Start or ReStart */ + + /* Generate Start */ hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } } /* Process Unlocked */ @@ -3996,6 +4017,12 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) { /* Disable Acknowledge */ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)) + { + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } } else { diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.c index 2f0809dbe2..9e43671897 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.c @@ -1413,8 +1413,17 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Generate Start */ if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE)) { - /* Generate Start or ReStart */ + /* Generate Start condition if first transfer */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Generate Start */ hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(Prev_State == I2C_STATE_MASTER_BUSY_RX) // MBED + { + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } } /* Process Unlocked */ @@ -1503,10 +1512,23 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE)) { + /* Generate Start condition if first transfer */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME)) + { /* Enable Acknowledge */ hi2c->Instance->CR1 |= I2C_CR1_ACK; - /* Generate Start or ReStart */ + + /* Generate Start */ hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } } /* Process Unlocked */ @@ -3993,6 +4015,12 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) { /* Disable Acknowledge */ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)) + { + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } } else { diff --git a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2c.c index 94ae610577..40830723e8 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2c.c @@ -1337,7 +1337,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Enable Acknowledge */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - + /* Generate Start */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); @@ -1428,8 +1428,17 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Generate Start */ if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) || (hi2c->PreviousState == I2C_STATE_NONE)) { - /* Generate Start or ReStart */ + /* Generate Start condition if first transfer */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Generate Start */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + { + /* Generate ReStart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } } /* Process Unlocked */ @@ -1518,10 +1527,23 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE)) { + /* Generate Start condition if first transfer */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME)) + { /* Enable Acknowledge */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - /* Generate Start or ReStart */ + + /* Generate Start */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate ReStart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } } /* Process Unlocked */ @@ -3866,11 +3888,15 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) { /* Disable Acknowledge */ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)) + { + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } } else { - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; - /* Generate Stop */ hi2c->Instance->CR1 |= I2C_CR1_STOP; }