mirror of https://github.com/ARMmbed/mbed-os.git
Enable IAR and GCC_ARM compiler for CM3DS MPS2
1. Add startup code and linker script for IAR and GCC_ARM compilers. 2. Enable IAR and GCC_ARM compilers in targets.json. Change-Id: I742a89ae73a4e5ede980a8af0821c3f0e5a461ef Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>pull/4596/head
mattot01
adbridge
parent
29520eaaa4
commit
64d3fd464b
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@ -22,14 +22,16 @@
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*************************************************************
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*************************************************************
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*/
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*/
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LR_IROM1 0x00000000 0x00400000 { ; load region size_region
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LR_IROM1 0x00000000 0x00040000 { ; load region size_region
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ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
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ER_IROM1 0x00000000 0x00040000 { ; load address = execution address
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*.o (RESET, +First)
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*.o (RESET, +First)
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*(InRoot$$Sections)
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*(InRoot$$Sections)
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.ANY (+RO)
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.ANY (+RO)
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}
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}
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; Total: 80 vectors = 320 bytes (0x140) to be reserved in RAM
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; Total: 80 vectors = 320 bytes (0x140) to be reserved in RAM
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RW_IRAM1 (0x20000000+0x140) (0x400000-0x140) { ; RW data
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; This is a bit more than is necessary based on the number of
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; exception handlers.
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RW_IRAM1 (0x20000000+0x140) (0x20000-0x140) { ; RW data
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.ANY (+RW +ZI)
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.ANY (+RW +ZI)
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}
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}
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}
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}
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@ -0,0 +1,211 @@
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/*
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* MPS2 CMSIS Library
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*/
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/*
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* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* This file is derivative of CMSIS V5.00 gcc_arm.ld
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*/
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/* Linker script for mbed CM3DS on MPS2 */
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/* Linker script to configure memory regions. */
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/* The length of the VECTORS region is a bit larger than
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* is necessary based on the number of exception handlers.
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*/
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MEMORY
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{
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VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
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FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
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}
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/* Linker script to place sections and symbol values. Should be used together
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* with other linker script that defines memory regions FLASH and RAM.
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* It references following symbols, which must be defined in code:
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* Reset_Handler : Entry of reset handler
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*
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* It defines following symbols, which code can use without definition:
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* __exidx_start
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* __exidx_end
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* __etext
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* __data_start__
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* __preinit_array_start
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* __preinit_array_end
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* __init_array_start
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* __init_array_end
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* __fini_array_start
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* __fini_array_end
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* __data_end__
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* __bss_start__
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* __bss_end__
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* __end__
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* end
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* __HeapLimit
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* __StackLimit
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* __StackTop
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* __stack
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*/
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ENTRY(Reset_Handler)
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HEAP_SIZE = 0x4000;
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STACK_SIZE = 0x1000;
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/* Size of the vector table in SRAM */
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M_VECTOR_RAM_SIZE = 0x140;
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SECTIONS
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{
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.isr_vector :
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{
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__vector_table = .;
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KEEP(*(.vector_table))
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. = ALIGN(4);
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} > VECTORS
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.text :
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{
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. = ALIGN(4);
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*(.text*)
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KEEP(*(.init))
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KEEP(*(.fini))
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/* .ctors */
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*crtbegin.o(.ctors)
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*crtbegin?.o(.ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(SORT(.ctors.*))
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*(.ctors)
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/* .dtors */
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*crtbegin.o(.dtors)
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*crtbegin?.o(.dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(SORT(.dtors.*))
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*(.dtors)
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*(.rodata*)
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KEEP(*(.eh_frame*))
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} > FLASH
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > FLASH
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > FLASH
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__exidx_end = .;
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.interrupts_ram :
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{
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. = ALIGN(4);
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__VECTOR_RAM__ = .;
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__interrupts_ram_start__ = .; /* Create a global symbol at data start */
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. += M_VECTOR_RAM_SIZE;
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. = ALIGN(4);
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__interrupts_ram_end__ = .; /* Define a global symbol at data end */
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} > RAM
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.data :
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{
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PROVIDE(__etext = LOADADDR(.data));
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. = ALIGN(4);
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__data_start__ = .;
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*(vtable)
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*(.data)
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*(.data*)
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. = ALIGN(4);
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/* preinit data */
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PROVIDE (__preinit_array_start = .);
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KEEP(*(.preinit_array))
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PROVIDE (__preinit_array_end = .);
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. = ALIGN(4);
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/* init data */
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PROVIDE (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE (__init_array_end = .);
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. = ALIGN(4);
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/* finit data */
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PROVIDE (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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PROVIDE (__fini_array_end = .);
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. = ALIGN(4);
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/* All data end */
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__data_end__ = .;
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} > RAM AT > FLASH
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.uninitialized (NOLOAD):
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{
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. = ALIGN(32);
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__uninitialized_start = .;
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*(.uninitialized)
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KEEP(*(.keep.uninitialized))
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. = ALIGN(32);
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__uninitialized_end = .;
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} > RAM
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.bss :
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{
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. = ALIGN(4);
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__START_BSS = .;
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__bss_start__ = .;
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*(.bss)
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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__bss_end__ = .;
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__END_BSS = .;
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} > RAM
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bss_size = __bss_end__ - __bss_start__;
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.heap :
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{
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. = ALIGN(8);
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__end__ = .;
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PROVIDE(end = .);
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__HeapBase = .;
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. += HEAP_SIZE;
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__HeapLimit = .;
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__heap_limit = .; /* Add for _sbrk */
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} > RAM
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/* Set stack top to end of RAM, and stack limit move down by
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* size of stack_dummy section */
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__StackTop = ORIGIN(RAM) + LENGTH(RAM);
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__StackLimit = __StackTop - STACK_SIZE;
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PROVIDE(__stack = __StackTop);
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/* Check if data + heap + stack exceeds RAM limit */
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ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
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} /* End of sections */
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@ -0,0 +1,257 @@
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/*
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* MPS2 CMSIS Library
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*/
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/*
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* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* This file is derivative of CMSIS V5.00 startup_ARMCM3.S
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*/
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.syntax unified
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.arch armv7-m
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.section .vector_table,"a",%progbits
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.align 2
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.globl __isr_vector
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__isr_vector:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long NMI_Handler /* NMI Handler */
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.long HardFault_Handler /* Hard Fault Handler */
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.long MemManage_Handler /* MPU Fault Handler */
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.long BusFault_Handler /* Bus Fault Handler */
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.long UsageFault_Handler /* Usage Fault Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long SVC_Handler /* SVCall Handler */
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.long DebugMon_Handler /* Debug Monitor Handler */
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.long 0 /* Reserved */
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.long PendSV_Handler /* PendSV Handler */
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.long SysTick_Handler /* SysTick Handler */
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/* External Interrupts */
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.long UART0_IRQHandler /* 0: UART 0 RX and TX Combined Interrupt */
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.long Spare_IRQHandler /* 1: Undefined */
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.long UART1_IRQHandler /* 2: UART 1 RX and TX Combined Interrupt */
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.long APB_Slave0_IRQHandler /* 3: Reserved for APB Slave */
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.long APB_Slave1_IRQHandler /* 4: Reserved for APB Slave */
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.long RTC_IRQHandler /* 5: RTC Interrupt */
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.long PORT0_IRQHandler /* 6: GPIO Port 0 combined Interrupt */
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.long PORT1_ALL_IRQHandler /* 7: GPIO Port 1 combined Interrupt */
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.long TIMER0_IRQHandler /* 8: TIMER 0 Interrupt */
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.long TIMER1_IRQHandler /* 9: TIMER 1 Interrupt */
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.long DUALTIMER_IRQHandler /* 10: Dual Timer Interrupt */
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.long APB_Slave2_IRQHandler /* 11: Reserved for APB Slave */
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.long UARTOVF_IRQHandler /* 12: UART 0,1,2 Overflow Interrupt */
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.long APB_Slave3_IRQHandler /* 13: Reserved for APB Slave */
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.long RESERVED0_IRQHandler /* 14: Reserved */
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.long TSC_IRQHandler /* 15: Touch Screen Interrupt */
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.long PORT0_0_IRQHandler /* 16: GPIO Port 0 pin 0 Handler */
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.long PORT0_1_IRQHandler /* 17: GPIO Port 0 pin 1 Handler */
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.long PORT0_2_IRQHandler /* 18: GPIO Port 0 pin 2 Handler */
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.long PORT0_3_IRQHandler /* 19: GPIO Port 0 pin 3 Handler */
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.long PORT0_4_IRQHandler /* 20: GPIO Port 0 pin 4 Handler */
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.long PORT0_5_IRQHandler /* 21: GPIO Port 0 pin 5 Handler */
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.long PORT0_6_IRQHandler /* 22: GPIO Port 0 pin 6 Handler */
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.long PORT0_7_IRQHandler /* 23: GPIO Port 0 pin 7 Handler */
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.long PORT0_8_IRQHandler /* 24: GPIO Port 0 pin 8 Handler */
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.long PORT0_9_IRQHandler /* 25: GPIO Port 0 pin 9 Handler */
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.long PORT0_10_IRQHandler /* 26: GPIO Port 0 pin 10 Handler */
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.long PORT0_11_IRQHandler /* 27: GPIO Port 0 pin 11 Handler */
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.long PORT0_12_IRQHandler /* 28: GPIO Port 0 pin 12 Handler */
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.long PORT0_13_IRQHandler /* 29: GPIO Port 0 pin 13 Handler */
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.long PORT0_14_IRQHandler /* 30: GPIO Port 0 pin 14 Handler */
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.long PORT0_15_IRQHandler /* 31: GPIO Port 0 pin 15 Handler */
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.long FLASH0_IRQHandler /* 32: Reserved for Flash */
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.long FLASH1_IRQHandler /* 33: Reserved for Flash */
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.long RESERVED1_IRQHandler /* 34: Reserved */
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.long RESERVED2_IRQHandler /* 35: Reserved */
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.long RESERVED3_IRQHandler /* 36: Reserved */
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.long RESERVED4_IRQHandler /* 37: Reserved */
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.long RESERVED5_IRQHandler /* 38: Reserved */
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.long RESERVED6_IRQHandler /* 39: Reserved */
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.long RESERVED7_IRQHandler /* 40: Reserved */
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.long RESERVED8_IRQHandler /* 41: Reserved */
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.long PORT2_ALL_IRQHandler /* 42: GPIO Port 2 combined Interrupt */
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.long PORT3_ALL_IRQHandler /* 43: GPIO Port 3 combined Interrupt */
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.long TRNG_IRQHandler /* 44: Random number generator Interrupt */
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.long UART2_IRQHandler /* 45: UART 2 RX and TX Combined Interrupt */
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.long UART3_IRQHandler /* 46: UART 3 RX and TX Combined Interrupt */
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.long ETHERNET_IRQHandler /* 47: Ethernet interrupt t.b.a. */
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.long I2S_IRQHandler /* 48: I2S Interrupt */
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.long MPS2_SPI0_IRQHandler /* 49: SPI Interrupt (spi header) */
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.long MPS2_SPI1_IRQHandler /* 50: SPI Interrupt (clcd) */
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.long MPS2_SPI2_IRQHandler /* 51: SPI Interrupt (spi 1 ADC replacement) */
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.long MPS2_SPI3_IRQHandler /* 52: SPI Interrupt (spi 0 shield 0 replacement) */
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.long MPS2_SPI4_IRQHandler /* 53: SPI Interrupt (shield 1) */
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.long PORT4_ALL_IRQHandler /* 54: GPIO Port 4 combined Interrupt */
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.long PORT5_ALL_IRQHandler /* 55: GPIO Port 5 combined Interrupt */
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.long UART4_IRQHandler /* 56: UART 4 RX and TX Combined Interrupt */
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.size __isr_vector, . - __isr_vector
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.section .text.Reset_Handler
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.thumb
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.thumb_func
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.align 2
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.globl Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr r0, =SystemInit
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blx r0
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/*
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* Loop to copy data from read only memory to RAM. The ranges
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* of copy from/to are specified by following symbols evaluated in
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* linker script.
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* _etext: End of code section, i.e., begin of data sections to copy from.
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* __data_start__/__data_end__: RAM address range that data should be
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* copied to. Both must be aligned to 4 bytes boundary.
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*/
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ldr r1, =__etext
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ldr r2, =__data_start__
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ldr r3, =__data_end__
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subs r3, r2
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ble .Lflash_to_ram_loop_end
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movs r4, 0
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.Lflash_to_ram_loop:
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||||||
|
ldr r0, [r1,r4]
|
||||||
|
str r0, [r2,r4]
|
||||||
|
adds r4, 4
|
||||||
|
cmp r4, r3
|
||||||
|
blt .Lflash_to_ram_loop
|
||||||
|
.Lflash_to_ram_loop_end:
|
||||||
|
|
||||||
|
/* Initialize .bss */
|
||||||
|
init_bss:
|
||||||
|
ldr r1, =__bss_start__
|
||||||
|
ldr r2, =__bss_end__
|
||||||
|
ldr r3, =bss_size
|
||||||
|
|
||||||
|
cmp r3, #0
|
||||||
|
beq system_startup
|
||||||
|
|
||||||
|
mov r4, #0
|
||||||
|
zero:
|
||||||
|
strb r4, [r1], #1
|
||||||
|
subs r3, r3, #1
|
||||||
|
bne zero
|
||||||
|
|
||||||
|
system_startup:
|
||||||
|
ldr r0, =SystemInit
|
||||||
|
blx r0
|
||||||
|
ldr r0, =_start
|
||||||
|
bx r0
|
||||||
|
.pool
|
||||||
|
.size Reset_Handler, . - Reset_Handler
|
||||||
|
|
||||||
|
.text
|
||||||
|
/*
|
||||||
|
* Macro to define default handlers. Default handler
|
||||||
|
* will be weak symbol and just dead loops. They can be
|
||||||
|
* overwritten by other handlers
|
||||||
|
*/
|
||||||
|
.macro def_default_handler handler_name
|
||||||
|
.align 1
|
||||||
|
.thumb_func
|
||||||
|
.weak \handler_name
|
||||||
|
.type \handler_name, %function
|
||||||
|
\handler_name :
|
||||||
|
b .
|
||||||
|
.size \handler_name, . - \handler_name
|
||||||
|
.endm
|
||||||
|
|
||||||
|
def_default_handler NMI_Handler
|
||||||
|
def_default_handler HardFault_Handler
|
||||||
|
def_default_handler MemManage_Handler
|
||||||
|
def_default_handler BusFault_Handler
|
||||||
|
def_default_handler UsageFault_Handler
|
||||||
|
def_default_handler SVC_Handler
|
||||||
|
def_default_handler DebugMon_Handler
|
||||||
|
def_default_handler PendSV_Handler
|
||||||
|
def_default_handler SysTick_Handler
|
||||||
|
def_default_handler Default_Handler
|
||||||
|
|
||||||
|
.macro def_irq_default_handler handler_name
|
||||||
|
.weak \handler_name
|
||||||
|
.set \handler_name, Default_Handler
|
||||||
|
.endm
|
||||||
|
|
||||||
|
/* External interrupts */
|
||||||
|
def_irq_default_handler UART0_IRQHandler /* 0: UART 0 RX and TX Combined Interrupt */
|
||||||
|
def_irq_default_handler Spare_IRQHandler /* 1: Undefined */
|
||||||
|
def_irq_default_handler UART1_IRQHandler /* 2: UART 1 RX and TX Combined Interrupt */
|
||||||
|
def_irq_default_handler APB_Slave0_IRQHandler /* 3: Reserved for APB Slave */
|
||||||
|
def_irq_default_handler APB_Slave1_IRQHandler /* 4: Reserved for APB Slave */
|
||||||
|
def_irq_default_handler RTC_IRQHandler /* 5: RTC Interrupt */
|
||||||
|
def_irq_default_handler PORT0_IRQHandler /* 6: GPIO Port 0 combined Interrupt */
|
||||||
|
def_irq_default_handler PORT1_ALL_IRQHandler /* 7: GPIO Port 1 combined Interrupt */
|
||||||
|
def_irq_default_handler TIMER0_IRQHandler /* 8: TIMER 0 Interrupt */
|
||||||
|
def_irq_default_handler TIMER1_IRQHandler /* 9: TIMER 1 Interrupt */
|
||||||
|
def_irq_default_handler DUALTIMER_IRQHandler /* 10: Dual Timer Interrupt */
|
||||||
|
def_irq_default_handler APB_Slave2_IRQHandler /* 11: Reserved for APB Slave */
|
||||||
|
def_irq_default_handler UARTOVF_IRQHandler /* 12: UART 0,1,2 Overflow Interrupt */
|
||||||
|
def_irq_default_handler APB_Slave3_IRQHandler /* 13: Reserved for APB Slave */
|
||||||
|
def_irq_default_handler RESERVED0_IRQHandler /* 14: Reserved */
|
||||||
|
def_irq_default_handler TSC_IRQHandler /* 15: Touch Screen Interrupt */
|
||||||
|
def_irq_default_handler PORT0_0_IRQHandler /* 16: GPIO Port 0 pin 0 Handler */
|
||||||
|
def_irq_default_handler PORT0_1_IRQHandler /* 17: GPIO Port 0 pin 1 Handler */
|
||||||
|
def_irq_default_handler PORT0_2_IRQHandler /* 18: GPIO Port 0 pin 2 Handler */
|
||||||
|
def_irq_default_handler PORT0_3_IRQHandler /* 19: GPIO Port 0 pin 3 Handler */
|
||||||
|
def_irq_default_handler PORT0_4_IRQHandler /* 20: GPIO Port 0 pin 4 Handler */
|
||||||
|
def_irq_default_handler PORT0_5_IRQHandler /* 21: GPIO Port 0 pin 5 Handler */
|
||||||
|
def_irq_default_handler PORT0_6_IRQHandler /* 22: GPIO Port 0 pin 6 Handler */
|
||||||
|
def_irq_default_handler PORT0_7_IRQHandler /* 23: GPIO Port 0 pin 7 Handler */
|
||||||
|
def_irq_default_handler PORT0_8_IRQHandler /* 24: GPIO Port 0 pin 8 Handler */
|
||||||
|
def_irq_default_handler PORT0_9_IRQHandler /* 25: GPIO Port 0 pin 9 Handler */
|
||||||
|
def_irq_default_handler PORT0_10_IRQHandler /* 26: GPIO Port 0 pin 10 Handler */
|
||||||
|
def_irq_default_handler PORT0_11_IRQHandler /* 27: GPIO Port 0 pin 11 Handler */
|
||||||
|
def_irq_default_handler PORT0_12_IRQHandler /* 28: GPIO Port 0 pin 12 Handler */
|
||||||
|
def_irq_default_handler PORT0_13_IRQHandler /* 29: GPIO Port 0 pin 13 Handler */
|
||||||
|
def_irq_default_handler PORT0_14_IRQHandler /* 30: GPIO Port 0 pin 14 Handler */
|
||||||
|
def_irq_default_handler PORT0_15_IRQHandler /* 31: GPIO Port 0 pin 15 Handler */
|
||||||
|
def_irq_default_handler FLASH0_IRQHandler /* 32: Reserved for Flash */
|
||||||
|
def_irq_default_handler FLASH1_IRQHandler /* 33: Reserved for Flash */
|
||||||
|
def_irq_default_handler RESERVED1_IRQHandler /* 34: Reserved */
|
||||||
|
def_irq_default_handler RESERVED2_IRQHandler /* 35: Reserved */
|
||||||
|
def_irq_default_handler RESERVED3_IRQHandler /* 36: Reserved */
|
||||||
|
def_irq_default_handler RESERVED4_IRQHandler /* 37: Reserved */
|
||||||
|
def_irq_default_handler RESERVED5_IRQHandler /* 38: Reserved */
|
||||||
|
def_irq_default_handler RESERVED6_IRQHandler /* 39: Reserved */
|
||||||
|
def_irq_default_handler RESERVED7_IRQHandler /* 40: Reserved */
|
||||||
|
def_irq_default_handler RESERVED8_IRQHandler /* 41: Reserved */
|
||||||
|
def_irq_default_handler PORT2_ALL_IRQHandler /* 42: GPIO Port 2 combined Interrupt */
|
||||||
|
def_irq_default_handler PORT3_ALL_IRQHandler /* 43: GPIO Port 3 combined Interrupt */
|
||||||
|
def_irq_default_handler TRNG_IRQHandler /* 44: Random number generator Interrupt */
|
||||||
|
def_irq_default_handler UART2_IRQHandler /* 45: UART 2 RX and TX Combined Interrupt */
|
||||||
|
def_irq_default_handler UART3_IRQHandler /* 46: UART 3 RX and TX Combined Interrupt */
|
||||||
|
def_irq_default_handler ETHERNET_IRQHandler /* 47: Ethernet interrupt t.b.a. */
|
||||||
|
def_irq_default_handler I2S_IRQHandler /* 48: I2S Interrupt */
|
||||||
|
def_irq_default_handler MPS2_SPI0_IRQHandler /* 49: SPI Interrupt (spi header) */
|
||||||
|
def_irq_default_handler MPS2_SPI1_IRQHandler /* 50: SPI Interrupt (clcd) */
|
||||||
|
def_irq_default_handler MPS2_SPI2_IRQHandler /* 51: SPI Interrupt (spi 1 ADC replacement) */
|
||||||
|
def_irq_default_handler MPS2_SPI3_IRQHandler /* 52: SPI Interrupt (spi 0 shield 0 replacement) */
|
||||||
|
def_irq_default_handler MPS2_SPI4_IRQHandler /* 53: SPI Interrupt (shield 1) */
|
||||||
|
def_irq_default_handler PORT4_ALL_IRQHandler /* 54: GPIO Port 4 combined Interrupt */
|
||||||
|
def_irq_default_handler PORT5_ALL_IRQHandler /* 55: GPIO Port 5 combined Interrupt */
|
||||||
|
def_irq_default_handler UART4_IRQHandler /* 56: UART 4 RX and TX Combined Interrupt */
|
||||||
|
|
||||||
|
.end
|
||||||
|
|
@ -0,0 +1,56 @@
|
||||||
|
/*
|
||||||
|
* MPS2 CMSIS Library
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License) you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* The RAM region doesn't start at the beginning of the RAM address
|
||||||
|
* space to create space for the vector table copied over to the RAM by mbed.
|
||||||
|
* The space left is a bit bigger than is necessary based on the number of
|
||||||
|
* interrupt handlers.
|
||||||
|
*/
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20000140;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
/* Heap and Stack size */
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x4000;
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
|
|
@ -0,0 +1,490 @@
|
||||||
|
;/*
|
||||||
|
; * MPS2 CMSIS Library
|
||||||
|
; */
|
||||||
|
;/*
|
||||||
|
; * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||||
|
; *
|
||||||
|
; * SPDX-License-Identifier: Apache-2.0
|
||||||
|
; *
|
||||||
|
; * Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
; * not use this file except in compliance with the License.
|
||||||
|
; * You may obtain a copy of the License at
|
||||||
|
; *
|
||||||
|
; * http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
; *
|
||||||
|
; * Unless required by applicable law or agreed to in writing, software
|
||||||
|
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
; * See the License for the specific language governing permissions and
|
||||||
|
; * limitations under the License.
|
||||||
|
; */
|
||||||
|
;/*
|
||||||
|
; * This file is derivative of CMSIS V5.00 startup_Device.s
|
||||||
|
; */
|
||||||
|
|
||||||
|
|
||||||
|
;
|
||||||
|
; The modules in this file are included in the libraries, and may be replaced
|
||||||
|
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||||
|
; a user defined start symbol.
|
||||||
|
; To override the cstartup defined in the library, simply add your modified
|
||||||
|
; version to the workbench project.
|
||||||
|
;
|
||||||
|
; The vector table is normally located at address 0.
|
||||||
|
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||||
|
; The name "__vector_table" has special meaning for C-SPY:
|
||||||
|
; it is where the SP start value is found, and the NVIC vector
|
||||||
|
; table register (VTOR) is initialized to this address if != 0.
|
||||||
|
;
|
||||||
|
; Cortex-M version
|
||||||
|
;
|
||||||
|
|
||||||
|
MODULE ?cstartup
|
||||||
|
|
||||||
|
;; Forward declaration of sections.
|
||||||
|
SECTION CSTACK:DATA:NOROOT(3)
|
||||||
|
|
||||||
|
SECTION .intvec:CODE:NOROOT(2)
|
||||||
|
|
||||||
|
EXTERN __iar_program_start
|
||||||
|
EXTERN SystemInit
|
||||||
|
PUBLIC __vector_table
|
||||||
|
PUBLIC __vector_table_0x1c
|
||||||
|
PUBLIC __Vectors
|
||||||
|
PUBLIC __Vectors_End
|
||||||
|
PUBLIC __Vectors_Size
|
||||||
|
|
||||||
|
DATA
|
||||||
|
|
||||||
|
__vector_table
|
||||||
|
DCD sfe(CSTACK)
|
||||||
|
DCD Reset_Handler
|
||||||
|
|
||||||
|
DCD NMI_Handler
|
||||||
|
DCD HardFault_Handler
|
||||||
|
DCD MemManage_Handler
|
||||||
|
DCD BusFault_Handler
|
||||||
|
DCD UsageFault_Handler
|
||||||
|
__vector_table_0x1c
|
||||||
|
DCD 0
|
||||||
|
DCD 0
|
||||||
|
DCD 0
|
||||||
|
DCD 0
|
||||||
|
DCD SVC_Handler
|
||||||
|
DCD DebugMon_Handler
|
||||||
|
DCD 0
|
||||||
|
DCD PendSV_Handler
|
||||||
|
DCD SysTick_Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD UART0_IRQHandler ; 0:UART 0 RX and TX Combined Interrupt
|
||||||
|
DCD Spare_IRQHandler ; 1:Undefined
|
||||||
|
DCD UART1_IRQHandler ; 2:UART 1 RX and TX Combined Interrupt
|
||||||
|
DCD APB_Slave0_IRQHandler ; 3:Reserved for APB Slave
|
||||||
|
DCD APB_Slave1_IRQHandler ; 4:Reserved for APB Slave
|
||||||
|
DCD RTC_IRQHandler ; 5:RTC Interrupt
|
||||||
|
DCD PORT0_IRQHandler ; 6:GPIO Port 0 combined Interrupt
|
||||||
|
DCD PORT1_ALL_IRQHandler ; 7:GPIO Port 1 combined Interrupt
|
||||||
|
DCD TIMER0_IRQHandler ; 8:TIMER 0 Interrupt
|
||||||
|
DCD TIMER1_IRQHandler ; 9:TIMER 1 Interrupt
|
||||||
|
DCD DUALTIMER_IRQHandler ; 10:Dual Timer Interrupt
|
||||||
|
DCD APB_Slave2_IRQHandler ; 11:Reserved for APB Slave
|
||||||
|
DCD UARTOVF_IRQHandler ; 12:UART 0,1,2 Overflow Interrupt
|
||||||
|
DCD APB_Slave3_IRQHandler ; 13:Reserved for APB Slave
|
||||||
|
DCD RESERVED0_IRQHandler ; 14:Reserved
|
||||||
|
DCD TSC_IRQHandler ; 15:Touch Screen Interrupt
|
||||||
|
DCD PORT0_0_IRQHandler ; 16:GPIO Port 0 pin 0 Handler
|
||||||
|
DCD PORT0_1_IRQHandler ; 17:GPIO Port 0 pin 1 Handler
|
||||||
|
DCD PORT0_2_IRQHandler ; 18:GPIO Port 0 pin 2 Handler
|
||||||
|
DCD PORT0_3_IRQHandler ; 19:GPIO Port 0 pin 3 Handler
|
||||||
|
DCD PORT0_4_IRQHandler ; 20:GPIO Port 0 pin 4 Handler
|
||||||
|
DCD PORT0_5_IRQHandler ; 21:GPIO Port 0 pin 5 Handler
|
||||||
|
DCD PORT0_6_IRQHandler ; 22:GPIO Port 0 pin 6 Handler
|
||||||
|
DCD PORT0_7_IRQHandler ; 23:GPIO Port 0 pin 7 Handler
|
||||||
|
DCD PORT0_8_IRQHandler ; 24:GPIO Port 0 pin 8 Handler
|
||||||
|
DCD PORT0_9_IRQHandler ; 25:GPIO Port 0 pin 9 Handler
|
||||||
|
DCD PORT0_10_IRQHandler ; 26:GPIO Port 0 pin 10 Handler
|
||||||
|
DCD PORT0_11_IRQHandler ; 27:GPIO Port 0 pin 11 Handler
|
||||||
|
DCD PORT0_12_IRQHandler ; 28:GPIO Port 0 pin 12 Handler
|
||||||
|
DCD PORT0_13_IRQHandler ; 29:GPIO Port 0 pin 13 Handler
|
||||||
|
DCD PORT0_14_IRQHandler ; 30:GPIO Port 0 pin 14 Handler
|
||||||
|
DCD PORT0_15_IRQHandler ; 31:GPIO Port 0 pin 15 Handler
|
||||||
|
DCD FLASH0_IRQHandler ; 32:Reserved for Flash
|
||||||
|
DCD FLASH1_IRQHandler ; 33:Reserved for Flash
|
||||||
|
DCD RESERVED1_IRQHandler ; 34:Reserved
|
||||||
|
DCD RESERVED2_IRQHandler ; 35:Reserved
|
||||||
|
DCD RESERVED3_IRQHandler ; 36:Reserved
|
||||||
|
DCD RESERVED4_IRQHandler ; 37:Reserved
|
||||||
|
DCD RESERVED5_IRQHandler ; 38:Reserved
|
||||||
|
DCD RESERVED6_IRQHandler ; 39:Reserved
|
||||||
|
DCD RESERVED7_IRQHandler ; 40:Reserved
|
||||||
|
DCD RESERVED8_IRQHandler ; 41:Reserved
|
||||||
|
DCD PORT2_ALL_IRQHandler ; 42:GPIO Port 2 combined Interrupt
|
||||||
|
DCD PORT3_ALL_IRQHandler ; 43:GPIO Port 3 combined Interrupt
|
||||||
|
DCD TRNG_IRQHandler ; 44:Random number generator Interrupt
|
||||||
|
DCD UART2_IRQHandler ; 45:UART 2 RX and TX Combined Interrupt
|
||||||
|
DCD UART3_IRQHandler ; 46:UART 3 RX and TX Combined Interrupt
|
||||||
|
DCD ETHERNET_IRQHandler ; 47:Ethernet interrupt t.b.a.
|
||||||
|
DCD I2S_IRQHandler ; 48:I2S Interrupt
|
||||||
|
DCD MPS2_SPI0_IRQHandler ; 49:SPI Interrupt (spi header)
|
||||||
|
DCD MPS2_SPI1_IRQHandler ; 50:SPI Interrupt (clcd)
|
||||||
|
DCD MPS2_SPI2_IRQHandler ; 51:SPI Interrupt (spi 1 ADC replacement)
|
||||||
|
DCD MPS2_SPI3_IRQHandler ; 52:SPI Interrupt (spi 0 shield 0 replacement)
|
||||||
|
DCD MPS2_SPI4_IRQHandler ; 53:SPI Interrupt (shield 1)
|
||||||
|
DCD PORT4_ALL_IRQHandler ; 54:GPIO Port 4 combined Interrupt
|
||||||
|
DCD PORT5_ALL_IRQHandler ; 55:GPIO Port 5 combined Interrupt
|
||||||
|
DCD UART4_IRQHandler ; 56:UART 4 RX and TX Combined Interrupt
|
||||||
|
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors EQU __vector_table
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
|
||||||
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
;;
|
||||||
|
;; Default interrupt handlers.
|
||||||
|
;;
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
PUBWEAK Reset_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||||
|
Reset_Handler
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__iar_program_start
|
||||||
|
BX R0
|
||||||
|
|
||||||
|
PUBWEAK NMI_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
NMI_Handler
|
||||||
|
B NMI_Handler
|
||||||
|
|
||||||
|
PUBWEAK HardFault_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
HardFault_Handler
|
||||||
|
B HardFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK MemManage_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
MemManage_Handler
|
||||||
|
B MemManage_Handler
|
||||||
|
|
||||||
|
PUBWEAK BusFault_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
BusFault_Handler
|
||||||
|
B BusFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK UsageFault_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
UsageFault_Handler
|
||||||
|
B UsageFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK SVC_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
SVC_Handler
|
||||||
|
B SVC_Handler
|
||||||
|
|
||||||
|
PUBWEAK DebugMon_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DebugMon_Handler
|
||||||
|
B DebugMon_Handler
|
||||||
|
|
||||||
|
PUBWEAK PendSV_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PendSV_Handler
|
||||||
|
B PendSV_Handler
|
||||||
|
|
||||||
|
PUBWEAK SysTick_Handler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
SysTick_Handler
|
||||||
|
B SysTick_Handler
|
||||||
|
|
||||||
|
|
||||||
|
PUBWEAK UART0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
UART0_IRQHandler
|
||||||
|
B UART0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK Spare_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
Spare_IRQHandler
|
||||||
|
B Spare_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
UART1_IRQHandler
|
||||||
|
B UART1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK APB_Slave0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
APB_Slave0_IRQHandler
|
||||||
|
B APB_Slave0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK APB_Slave1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
APB_Slave1_IRQHandler
|
||||||
|
B APB_Slave1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
RTC_IRQHandler
|
||||||
|
B RTC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT0_IRQHandler
|
||||||
|
B PORT0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT1_ALL_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT1_ALL_IRQHandler
|
||||||
|
B PORT1_ALL_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TIMER0_IRQHandler
|
||||||
|
B TIMER0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TIMER1_IRQHandler
|
||||||
|
B TIMER1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DUALTIMER_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
DUALTIMER_IRQHandler
|
||||||
|
B DUALTIMER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK APB_Slave2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
APB_Slave2_IRQHandler
|
||||||
|
B APB_Slave2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UARTOVF_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
UARTOVF_IRQHandler
|
||||||
|
B UARTOVF_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK APB_Slave3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
APB_Slave3_IRQHandler
|
||||||
|
B APB_Slave3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RESERVED0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
RESERVED0_IRQHandler
|
||||||
|
B RESERVED0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TSC_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TSC_IRQHandler
|
||||||
|
B TSC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT0_0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT0_0_IRQHandler
|
||||||
|
B PORT0_0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT0_1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT0_1_IRQHandler
|
||||||
|
B PORT0_1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT0_2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT0_2_IRQHandler
|
||||||
|
B PORT0_2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT0_3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT0_3_IRQHandler
|
||||||
|
B PORT0_3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT0_4_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT0_4_IRQHandler
|
||||||
|
B PORT0_4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT0_5_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT0_5_IRQHandler
|
||||||
|
B PORT0_5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT0_6_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT0_6_IRQHandler
|
||||||
|
B PORT0_6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT0_7_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT0_7_IRQHandler
|
||||||
|
B PORT0_7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT0_8_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT0_8_IRQHandler
|
||||||
|
B PORT0_8_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT0_9_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT0_9_IRQHandler
|
||||||
|
B PORT0_9_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT0_10_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT0_10_IRQHandler
|
||||||
|
B PORT0_10_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT0_11_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT0_11_IRQHandler
|
||||||
|
B PORT0_11_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT0_12_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT0_12_IRQHandler
|
||||||
|
B PORT0_12_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT0_13_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT0_13_IRQHandler
|
||||||
|
B PORT0_13_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT0_14_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT0_14_IRQHandler
|
||||||
|
B PORT0_14_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT0_15_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT0_15_IRQHandler
|
||||||
|
B PORT0_15_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FLASH0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
FLASH0_IRQHandler
|
||||||
|
B FLASH0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FLASH1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
FLASH1_IRQHandler
|
||||||
|
B FLASH1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RESERVED1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
RESERVED1_IRQHandler
|
||||||
|
B RESERVED1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RESERVED2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
RESERVED2_IRQHandler
|
||||||
|
B RESERVED2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RESERVED3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
RESERVED3_IRQHandler
|
||||||
|
B RESERVED3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RESERVED4_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
RESERVED4_IRQHandler
|
||||||
|
B RESERVED4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RESERVED5_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
RESERVED5_IRQHandler
|
||||||
|
B RESERVED5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RESERVED6_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
RESERVED6_IRQHandler
|
||||||
|
B RESERVED6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RESERVED7_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
RESERVED7_IRQHandler
|
||||||
|
B RESERVED7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RESERVED8_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
RESERVED8_IRQHandler
|
||||||
|
B RESERVED8_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT2_ALL_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT2_ALL_IRQHandler
|
||||||
|
B PORT2_ALL_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT3_ALL_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT3_ALL_IRQHandler
|
||||||
|
B PORT3_ALL_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TRNG_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
TRNG_IRQHandler
|
||||||
|
B TRNG_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
UART2_IRQHandler
|
||||||
|
B UART2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
UART3_IRQHandler
|
||||||
|
B UART3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ETHERNET_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
ETHERNET_IRQHandler
|
||||||
|
B ETHERNET_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2S_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
I2S_IRQHandler
|
||||||
|
B I2S_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MPS2_SPI0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
MPS2_SPI0_IRQHandler
|
||||||
|
B MPS2_SPI0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MPS2_SPI1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
MPS2_SPI1_IRQHandler
|
||||||
|
B MPS2_SPI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MPS2_SPI2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
MPS2_SPI2_IRQHandler
|
||||||
|
B MPS2_SPI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MPS2_SPI3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
MPS2_SPI3_IRQHandler
|
||||||
|
B MPS2_SPI3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MPS2_SPI4_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
MPS2_SPI4_IRQHandler
|
||||||
|
B MPS2_SPI4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT4_ALL_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT4_ALL_IRQHandler
|
||||||
|
B PORT4_ALL_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PORT5_ALL_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PORT5_ALL_IRQHandler
|
||||||
|
B PORT5_ALL_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART4_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
UART4_IRQHandler
|
||||||
|
B UART4_IRQHandler
|
||||||
|
|
||||||
|
|
||||||
|
END
|
||||||
|
|
@ -1947,7 +1947,7 @@
|
||||||
"ARM_CM3DS_MPS2": {
|
"ARM_CM3DS_MPS2": {
|
||||||
"inherits": ["ARM_IOTSS_Target"],
|
"inherits": ["ARM_IOTSS_Target"],
|
||||||
"core": "Cortex-M3",
|
"core": "Cortex-M3",
|
||||||
"supported_toolchains": ["ARM"],
|
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
|
||||||
"extra_labels": ["ARM_SSG", "CM3DS_MPS2"],
|
"extra_labels": ["ARM_SSG", "CM3DS_MPS2"],
|
||||||
"macros": ["CMSDK_CM3DS"],
|
"macros": ["CMSDK_CM3DS"],
|
||||||
"device_has": ["ETHERNET","INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SPI", "RTC"],
|
"device_has": ["ETHERNET","INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SPI", "RTC"],
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue