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Merge pull request #12775 from MarceloSalazar/platform_cleanup 

Remove unsupported targets
pull/12804/head
Martin Kojtal 2020-04-14 10:59:20 +02:00 committed by GitHub
parent 33563b3cfb 73206b5b69
commit 64bc9d9dd7
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1481 changed files with 24 additions and 577212 deletions
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2
TESTS/integration/COMMON/target_extended.json
View File

@ -172,7 +172,7 @@
"lwip.tcp-enabled" : true,
"mbed-trace.enable" : false
},
"MTB_MXCHIP_EMW3166": {
"WIO_EMW3166": {
"target.components_add" : ["SPIF"],
"spif-driver.SPI_MOSI" : "PB_15",
"spif-driver.SPI_MISO" : "PB_14",

6
TESTS/network/emac/main.cpp
View File

@ -33,13 +33,9 @@
#else
#if (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI) && \
!defined(TARGET_UBLOX_EVK_ODIN_W2) && \
!defined(TARGET_REALTEK_RTL8195AM) && \
!defined(TARGET_MTB_ADV_WISE_1530) && \
!defined(TARGET_MTB_USI_WM_BN_BM_22) && \
!defined(TARGET_MTB_MXCHIP_EMW3166) && \
!defined(TARGET_MTB_UBLOX_ODIN_W2) && \
!defined(TARGET_UNO_91H)
!defined(TARGET_WIO_EMW3166)
#error [NOT_SUPPORTED] Wifi tests are not valid for the target
#else

8
TESTS/network/emac/mbed_lib.json
View File

@ -5,13 +5,7 @@
"NO_SUPPORT_FOR_IPV4_MULTICAST_FILTER": false
},
"target_overrides": {
"MTB_UBLOX_ODIN_W2": {
"NO_SUPPORT_FOR_MULTICAST_FILTER": true
},
"UBLOX_EVK_ODIN_W2": {
"NO_SUPPORT_FOR_MULTICAST_FILTER": true
},
"MTB_MXCHIP_EMW3166": {
"WIO_EMW3166": {
"NO_SUPPORT_FOR_IPV4_MULTICAST_FILTER": true
},
"MTB_ADV_WISE_1530": {

3
TEST_APPS/device/socket_app/mbed_app.json
View File

@ -13,9 +13,6 @@
"platform.stdio-buffered-serial": true,
"platform.stdio-flush-at-exit": true,
"drivers.uart-serial-rxbuf-size": 768
},
"UBLOX_EVK_ODIN_W2" : {
"target.device_has_remove": ["EMAC"]
}
}
}

8
TEST_APPS/readme.md
View File

@ -42,17 +42,15 @@ If you only want to run some specific tests, you can use the `-n` option. You ca
#### Running the tests with a specific test-config
Some devices may offer multiple network interfaces to operate with. For example, `UBLOX_EVK_ODIN_W2` offers ethernet and Wi-Fi capabilities.
The tests can be run for either one of those using already existing test-config -files.
Some devices may offer multiple network interfaces to operate with. The tests can be run for either one of those using already existing test-config -files.
To run the tests with the Wi-Fi interface:
`mbed test -m UBLOX_EVK_ODIN_W2 -t <toolchain> --icetea --test-config tools/test_configs/HeapBlockDeviceAndWifiInterface.json`
`mbed test -m <target> -t <toolchain> --icetea --test-config tools/test_configs/HeapBlockDeviceAndWifiInterface.json`
To run the tests with the ethernet interface:
`mbed test -m UBLOX_EVK_ODIN_W2 -t <toolchain> --icetea --test-config tools/test_configs/HeapBlockDeviceAndEthernetInterface.json`
`mbed test -m <target> -t <toolchain> --icetea --test-config tools/test_configs/HeapBlockDeviceAndEthernetInterface.json`
#### Providing Wi-Fi access point information

2
TEST_APPS/testcases/nanostack_mac_tester/ED_scan.py
View File

@ -42,7 +42,7 @@ class Testcase(Bench):
'*': {
"count":3,
"type": "hardware",
"allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "UBLOX_EVK_ODIN_W2", "KW41Z"],
"allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "KW41Z"],
"application": {
"name": "TEST_APPS-device-nanostack_mac_tester"
}

2
TEST_APPS/testcases/nanostack_mac_tester/address_read_and_write.py
View File

@ -41,7 +41,7 @@ class Testcase(Bench):
'*': {
"count":1,
"type": "hardware",
"allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "UBLOX_EVK_ODIN_W2", "KW41Z"],
"allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "KW41Z"],
"application": {
"name": "TEST_APPS-device-nanostack_mac_tester"
}

2
TEST_APPS/testcases/nanostack_mac_tester/create_and_join_PAN.py
View File

@ -41,7 +41,7 @@ class Testcase(Bench):
'*': {
"count":3,
"type": "hardware",
"allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "UBLOX_EVK_ODIN_W2", "KW41Z"],
"allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "KW41Z"],
"application": {
"name": "TEST_APPS-device-nanostack_mac_tester"
}

2
TEST_APPS/testcases/nanostack_mac_tester/send_data.py
View File

@ -41,7 +41,7 @@ class Testcase(Bench):
'*': {
"count":2,
"type": "hardware",
"allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "UBLOX_EVK_ODIN_W2", "KW41Z"],
"allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "KW41Z"],
"application": {
"name": "TEST_APPS-device-nanostack_mac_tester"
}

2
TEST_APPS/testcases/nanostack_mac_tester/send_data_indirect.py
View File

@ -41,7 +41,7 @@ class Testcase(Bench):
'*': {
"count":3,
"type": "hardware",
"allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "UBLOX_EVK_ODIN_W2", "KW41Z"],
"allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "KW41Z"],
"application": {
"name": "TEST_APPS-device-nanostack_mac_tester"
}

2
TEST_APPS/testcases/nanostack_mac_tester/send_large_payloads.py
View File

@ -41,7 +41,7 @@ class Testcase(Bench):
'*': {
"count":2,
"type": "hardware",
"allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "UBLOX_EVK_ODIN_W2", "KW41Z"],
"allowed_platforms": ["K64F", "K66F", "NUCLEO_F429ZI", "KW24D", "KW41Z"],
"application": {
"name": "TEST_APPS-device-nanostack_mac_tester"
}

18
components/storage/blockdevice/COMPONENT_SD/mbed_lib.json
View File

@ -113,18 +113,6 @@
"SPI_CLK": "D13",
"SPI_CS": "D10"
},
"UBLOX_EVK_ODIN_W2": {
"SPI_CS": "D9",
"SPI_MOSI": "D11",
"SPI_MISO": "D12",
"SPI_CLK": "D13"
},
"MTB_UBLOX_ODIN_W2": {
"SPI_CS": "PG_4",
"SPI_MOSI": "PE_14",
"SPI_MISO": "PE_13",
"SPI_CLK": "PE_12"
},
"RZ_A1H": {
"SPI_MOSI": "P8_5",
"SPI_MISO": "P8_6",
@ -161,12 +149,6 @@
"SPI_CLK": "p7",
"SPI_CS": "p8"
},
"REALTEK_RTL8195AM": {
"SPI_MOSI": "D11",
"SPI_MISO": "D12",
"SPI_CLK": "D13",
"SPI_CS": "D10"
},
"CC3220SF_LAUNCHXL": {
"SPI_MOSI": "D11",
"SPI_MISO": "D12",

8
components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json
View File

@ -37,19 +37,13 @@
"SPI_CLK": "PTD5",
"SPI_CS": "PTD4"
},
"MTB_UBLOX_ODIN_W2": {
"SPI_MOSI": "PE_14",
"SPI_MISO": "PE_13",
"SPI_CLK": "PE_12",
"SPI_CS": "PE_11"
},
"MTB_ADV_WISE_1530": {
"SPI_MOSI": "PC_3",
"SPI_MISO": "PC_2",
"SPI_CLK": "PB_13",
"SPI_CS": "PC_12"
},
"MTB_MXCHIP_EMW3166": {
"WIO_EMW3166": {
"SPI_MOSI": "PB_15",
"SPI_MISO": "PB_14",
"SPI_CLK": "PB_13",

370
features/FEATURE_BLE/targets/TARGET_CORDIO_ODIN_W2/HCIDriver.cpp
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@ -1,370 +0,0 @@
/*
* Copyright (c) 2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "CordioBLE.h"
#include "CordioHCIDriver.h"
#include "hci_defs.h"
#include "hci_api.h"
#include "hci_cmd.h"
#include "hci_core.h"
#include "bstream.h"
#include "wsf_buf.h"
#include <stdbool.h>
#include "hci_mbed_os_adaptation.h"
#include "H4TransportDriver.h"
#include "OdinCordioInterface.h"
namespace ble {
namespace vendor {
namespace odin_w2 {
class HCIDriver : public cordio::CordioHCIDriver {
public:
HCIDriver(cordio::CordioHCITransportDriver &transport_driver, PinName shutdown_name, PinName hci_rts_name) :
cordio::CordioHCIDriver(transport_driver),
shutdown(shutdown_name, 0),
hci_rts(hci_rts_name, 0),
service_pack_index(0),
service_pack_transfered(false) {
};
virtual cordio::buf_pool_desc_t get_buffer_pool_description();
virtual void do_initialize();
virtual void do_terminate();
virtual void start_reset_sequence();
virtual void handle_reset_sequence(uint8_t *pMsg);
private:
void start_service_pack_transfer(void)
{
service_pack_index = 0;
service_pack_transfered = false;
send_service_pack_command();
}
void send_service_pack_command(void)
{
uint16_t cmd_len = odin_service_pack[service_pack_index + HCI_CMD_HDR_LEN];
cmd_opcode_ack_expected = (odin_service_pack[service_pack_index + 2] << 8) | odin_service_pack[service_pack_index + 1];
uint8_t *pBuf = hciCmdAlloc(cmd_opcode_ack_expected, cmd_len);
if (pBuf) {
memcpy(pBuf, odin_service_pack + service_pack_index + 1, cmd_len + HCI_CMD_HDR_LEN);
hciCmdSend(pBuf);
} else {
printf("Error cannot allocate memory for the buffer");
}
}
void ack_service_pack_command(uint16_t opcode, uint8_t *msg)
{
/* check if response opcode is same as expected command opcode */
MBED_ASSERT (cmd_opcode_ack_expected == opcode);
/* update service pack index */
service_pack_index += (1 + HCI_CMD_HDR_LEN + odin_service_pack[service_pack_index + HCI_CMD_HDR_LEN]);
if (service_pack_index < service_pack_size)
send_service_pack_command();
else if (opcode == HCID_VS_WRITE_BD_ADDR) {
/* send an HCI Reset command to start the sequence */
HciResetCmd();
service_pack_transfered = true;
} else {
/* send BT device hardware address write command */
send_hci_vs_cmd(HCID_VS_WRITE_BD_ADDR);
cmd_opcode_ack_expected = HCID_VS_WRITE_BD_ADDR;
}
}
void hci_read_resolving_list_size(void)
{
/* if LL Privacy is supported by Controller and included */
if ((hciCoreCb.leSupFeat & HCI_LE_SUP_FEAT_PRIVACY) &&
(hciLeSupFeatCfg & HCI_LE_SUP_FEAT_PRIVACY)) {
/* send next command in sequence */
HciLeReadResolvingListSize();
} else {
hciCoreCb.resListSize = 0;
/* send next command in sequence */
hci_read_max_data_len();
}
}
void hci_read_max_data_len(void)
{
/* if LE Data Packet Length Extensions is supported by Controller and included */
if ((hciCoreCb.leSupFeat & HCI_LE_SUP_FEAT_DATA_LEN_EXT) &&
(hciLeSupFeatCfg & HCI_LE_SUP_FEAT_DATA_LEN_EXT)) {
/* send next command in sequence */
HciLeReadMaxDataLen();
} else {
/* send next command in sequence */
HciLeRandCmd();
}
}
DigitalOut shutdown; // power/shutdown pin for bt device
DigitalOut hci_rts; // request to sent pin
size_t service_pack_index; // Index of command to be recently sent over hci
bool service_pack_transfered; // Flag to notify if service pack is completely transferred or not
uint16_t cmd_opcode_ack_expected; // Command against which acknowledgment is expected
uint32_t service_pack_size; // size of service pack
char *odin_service_pack ; // Service pack needs to be provided by driver
vs_cmd_send_t send_hci_vs_cmd ; // callback function to call vendor specific call handler
};
} // namespace odin_w2
} // namespace vendor
} // namespace ble
ble::vendor::cordio::buf_pool_desc_t ble::vendor::odin_w2::HCIDriver::get_buffer_pool_description()
{
// Use default buffer pool
return ble::vendor::cordio::CordioHCIDriver::get_default_buffer_pool_description();
}
void ble::vendor::odin_w2::HCIDriver::do_initialize()
{
cordio_callback_s callback;
hci_rts = 1; // Flow Control is OFF
shutdown = 0; // BT Power is OFF
ThisThread::sleep_for(20);
shutdown = 1; // BT Power is ON
ThisThread::sleep_for(500);
hci_rts = 0; // Flow Control is ON
/* ODIN ble driver initialization function */
cbCordio_Btinit(&callback);
odin_service_pack = callback.Service_pack;
send_hci_vs_cmd = callback.vs_command_callback;
service_pack_size = callback.service_pack_size;
}
void ble::vendor::odin_w2::HCIDriver::do_terminate()
{
}
void ble::vendor::odin_w2::HCIDriver::start_reset_sequence()
{
/* Update baudrate of ble to speed up setup time */
send_hci_vs_cmd(HCID_VS_UPDATE_UART_BAUD_RATE);
}
void ble::vendor::odin_w2::HCIDriver::handle_reset_sequence(uint8_t *pMsg)
{
uint16_t opcode;
static uint8_t randCnt;
/* if event is a command complete event */
if (*pMsg == HCI_CMD_CMPL_EVT) {
/* parse parameters */
pMsg += HCI_EVT_HDR_LEN;
pMsg++; /* skip num packets */
BSTREAM_TO_UINT16(opcode, pMsg);
pMsg++; /* skip status */
if (opcode == HCID_VS_UPDATE_UART_BAUD_RATE) {
update_uart_baud_rate();
start_service_pack_transfer();
return;
}
if (service_pack_transfered == false) {
ack_service_pack_command(opcode, pMsg);
return;
}
/* decode opcode */
switch (opcode) {
case HCI_OPCODE_RESET:
/* Send (fast and slow) clock configuration command */
send_hci_vs_cmd(HCID_VS_FAST_CLOCK_CONFIG_BTIP);
break;
case HCID_VS_FAST_CLOCK_CONFIG_BTIP:
/* Send deep-sleep behavior control command (setting retransmission, inactivity and rts pulse width for Bt) */
send_hci_vs_cmd(HCID_VS_HCILL_PARS_CFG);
break;
case HCID_VS_HCILL_PARS_CFG:
/* Send sleep mode configuration command */
send_hci_vs_cmd(HCID_VS_SLEEP_PROTOCOLS_CFG);
break;
case HCID_VS_SLEEP_PROTOCOLS_CFG:
/* initialize rand command count */
randCnt = 0;
/* send next command in sequence */
HciSetEventMaskCmd((uint8_t *)hciEventMask);
break;
case HCI_OPCODE_SET_EVENT_MASK:
/* send next command in sequence */
HciLeSetEventMaskCmd((uint8_t *)hciLeEventMask);
break;
case HCI_OPCODE_LE_SET_EVENT_MASK:
/* send next command in sequence */
HciSetEventMaskPage2Cmd((uint8_t *)hciEventMaskPage2);
break;
case HCI_OPCODE_SET_EVENT_MASK_PAGE2:
/* send next command in sequence */
HciReadBdAddrCmd();
break;
case HCI_OPCODE_READ_BD_ADDR:
/* parse and store event parameters */
BdaCpy(hciCoreCb.bdAddr, pMsg);
/* send next command in sequence */
HciLeReadBufSizeCmd();
break;
case HCI_OPCODE_LE_READ_BUF_SIZE:
/* parse and store event parameters */
BSTREAM_TO_UINT16(hciCoreCb.bufSize, pMsg);
BSTREAM_TO_UINT8(hciCoreCb.numBufs, pMsg);
/* initialize ACL buffer accounting */
hciCoreCb.availBufs = hciCoreCb.numBufs;
/* send next command in sequence */
HciLeReadSupStatesCmd();
break;
case HCI_OPCODE_LE_READ_SUP_STATES:
/* parse and store event parameters */
memcpy(hciCoreCb.leStates, pMsg, HCI_LE_STATES_LEN);
/* send next command in sequence */
HciLeReadWhiteListSizeCmd();
break;
case HCI_OPCODE_LE_READ_WHITE_LIST_SIZE:
/* parse and store event parameters */
BSTREAM_TO_UINT8(hciCoreCb.whiteListSize, pMsg);
/* send next command in sequence */
HciLeReadLocalSupFeatCmd();
break;
case HCI_OPCODE_LE_READ_LOCAL_SUP_FEAT:
/* parse and store event parameters */
BSTREAM_TO_UINT16(hciCoreCb.leSupFeat, pMsg);
/* send next command in sequence */
hci_read_resolving_list_size();
break;
case HCI_OPCODE_LE_READ_RES_LIST_SIZE:
/* parse and store event parameters */
BSTREAM_TO_UINT8(hciCoreCb.resListSize, pMsg);
/* send next command in sequence */
hci_read_max_data_len();
break;
case HCI_OPCODE_LE_READ_MAX_DATA_LEN:
uint16_t maxTxOctets;
uint16_t maxTxTime;
BSTREAM_TO_UINT16(maxTxOctets, pMsg);
BSTREAM_TO_UINT16(maxTxTime, pMsg);
/* use Controller's maximum supported payload octets and packet duration times
* for transmission as Host's suggested values for maximum transmission number
* of payload octets and maximum packet transmission time for new connections.
*/
HciLeWriteDefDataLen(maxTxOctets, maxTxTime);
break;
case HCI_OPCODE_LE_WRITE_DEF_DATA_LEN:
if (hciCoreCb.extResetSeq) {
/* send first extended command */
(*hciCoreCb.extResetSeq)(pMsg, opcode);
} else {
/* initialize extended parameters */
hciCoreCb.maxAdvDataLen = 0;
hciCoreCb.numSupAdvSets = 0;
hciCoreCb.perAdvListSize = 0;
/* send next command in sequence */
HciLeRandCmd();
}
break;
case HCI_OPCODE_LE_READ_MAX_ADV_DATA_LEN:
case HCI_OPCODE_LE_READ_NUM_SUP_ADV_SETS:
case HCI_OPCODE_LE_READ_PER_ADV_LIST_SIZE:
if (hciCoreCb.extResetSeq) {
/* send next extended command in sequence */
(*hciCoreCb.extResetSeq)(pMsg, opcode);
}
break;
case HCI_OPCODE_LE_RAND:
/* check if need to send second rand command */
if (randCnt < (HCI_RESET_RAND_CNT - 1)) {
randCnt++;
HciLeRandCmd();
} else {
uint8_t addr[6] = { 0 };
memcpy(addr, pMsg, sizeof(addr));
DM_RAND_ADDR_SET(addr, DM_RAND_ADDR_STATIC);
// note: will invoke set rand address
set_random_static_address(addr);
}
break;
case HCI_OPCODE_LE_SET_RAND_ADDR:
/* send next command in sequence */
signal_reset_sequence_done();
break;
default:
break;
}
}
}
ble::vendor::cordio::CordioHCIDriver& ble_cordio_get_hci_driver() {
static ble::vendor::cordio::H4TransportDriver transport_driver (/* cbCFG_PIO_PIN_BT_HCI_TX */ PG_14,
/* cbCFG_PIO_PIN_BT_HCI_RX */ PC_7,
/* cbCFG_PIO_PIN_BT_HCI_CTS */ PG_15,
/* cbCFG_PIO_PIN_BT_HCI_RTS */ PG_12,
115200);
static ble::vendor::odin_w2::HCIDriver hci_driver ( transport_driver,
/* cbCFG_PIO_PIN_BT_ENABLE */ PG_7,
/* cbCFG_PIO_PIN_BT_HCI_RTS */ PG_12);
return hci_driver;
}

45
features/FEATURE_BLE/targets/TARGET_CORDIO_ODIN_W2/OdinCordioInterface.h
View File

@ -1,45 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2017-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef ODIN_CORDIO_INTF_H
#define ODIN_CORDIO_INTF_H
#include <stdio.h>
#include "cb_main.h"
/*------------------------------------------------------------------------------
* Vendor specific commands opcode
* ------------------------------------------------------------------------------
*/
/* Command to write hardware address to BT device */
#define HCID_VS_WRITE_BD_ADDR 0xFC06
/* It configures clk parameters for fast and slow clock */
#define HCID_VS_FAST_CLOCK_CONFIG_BTIP 0xFD1C
/* Command to configure stand-by behavior */
#define HCID_VS_HCILL_PARS_CFG 0xFD2B
/* Command to configures the sleep mode */
#define HCID_VS_SLEEP_PROTOCOLS_CFG 0xFD0C
/* Command to Update BT device baudrate */
#define HCID_VS_UPDATE_UART_BAUD_RATE 0xFF36
#define HCI_RESET_RAND_CNT 4
#endif /* ODIN_CORDIO_INTF_H */

49
features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/LICENSE
View File

@ -1,49 +0,0 @@
Permissive Binary License
Version 1.0, September 2015
Redistribution. Redistribution and use in binary form, without
modification, are permitted provided that the following conditions are
met:
1) Redistributions must reproduce the above copyright notice and the
following disclaimer in the documentation and/or other materials
provided with the distribution.
2) Unless to the extent explicitly permitted by law, no reverse
engineering, decompilation, or disassembly of this software is
permitted.
3) Redistribution as part of a software development kit must include the
accompanying file named "DEPENDENCIES" and any dependencies listed in
that file.
4) Neither the name of the copyright holder nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
Limited patent license. The copyright holders (and contributors) grant a
worldwide, non-exclusive, no-charge, royalty-free patent license to
make, have made, use, offer to sell, sell, import, and otherwise
transfer this software, where such license applies only to those patent
claims licensable by the copyright holders (and contributors) that are
necessarily infringed by this software. This patent license shall not
apply to any combinations that include this software. No hardware is
licensed hereunder.
If you institute patent litigation against any entity (including a
cross-claim or counterclaim in a lawsuit) alleging that the software
itself infringes your patent(s), then your rights granted under this
license shall terminate as of the date such litigation is filed.
DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

BIN
features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/mbed-bootloader-sotp-v3_4_0.bin
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Binary file not shown.

10
features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/mbed_lib.json
View File

@ -1,10 +0,0 @@
{
"name": "bootloader_UBLOX_EVK_ODIN_W2",
"target_overrides": {
"*": {
"target.app_offset": "0x10400",
"target.header_offset": "0x10000",
"target.bootloader_img": "mbed-bootloader-sotp-v3_4_0.bin"
}
}
}

7
features/lwipstack/mbed_lib.json
View File

@ -156,13 +156,6 @@
}
},
"target_overrides": {
"REALTEK_RTL8195AM": {
"tcpip-thread-stacksize": 1600,
"mem-size": 12800
},
"UBLOX_EVK_ODIN_W2": {
"pbuf-pool-size" : 10
},
"STM": {
"mem-size": 2310
},

4
features/mbedtls/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/mbedtls_device.h
View File

@ -20,8 +20,4 @@
#ifndef MBEDTLS_DEVICE_H
#define MBEDTLS_DEVICE_H
#ifdef TARGET_UBLOX_EVK_ODIN_W2
#define MBEDTLS_MPI_WINDOW_SIZE 3 /**< Maximum windows size used. */
#endif
#endif /* MBEDTLS_DEVICE_H */

3
features/storage/kvstore/conf/global/mbed_lib.json
View File

@ -35,9 +35,6 @@
"DISCO_H747I_CM4": {
"storage_type": "TDB_INTERNAL"
},
"UBLOX_EVK_ODIN_W2": {
"storage_type": "TDB_INTERNAL"
},
"LPC55S69_S": {
"storage_type": "TDB_INTERNAL"
},

4
platform/mbed_lib.json
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@ -209,10 +209,6 @@
"crash-capture-enabled": true,
"fatal-error-auto-reboot-enabled": true
},
"UBLOX_EVK_ODIN_W2": {
"crash-capture-enabled": true,
"fatal-error-auto-reboot-enabled": true
},
"UBLOX_C030_U201": {
"crash-capture-enabled": true,
"fatal-error-auto-reboot-enabled": true

35
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/PortNames.h
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@ -1,35 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB,
#if defined(TARGET_SAMR21G18A)
PortC,
#endif
PortMax
} PortName;
#ifdef __cplusplus
}
#endif
#endif

13
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/device/cmsis.h
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@ -1,13 +0,0 @@
/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in samd21j18a specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "samd21.h"
#include "cmsis_nvic.h"
#endif

37
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/device/cmsis_nvic.h
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@ -1,37 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2011 ARM Limited. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 29) // CORE + MCU Peripherals
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM
#endif

150
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralNames.h
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@ -1,150 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include <compiler.h>
#include "cmsis.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
#define _SERCOM_SPI_NAME(n, unused) \
SPI##n,
#define _SERCOM_PAD_NAME(n, pad) \
SERCOM##n##_PAD##pad = ((n & 0xF) | ((pad & 0xF) << 4)),
#define _SERCOM_I2C_NAME(n, unused) \
I2C##n,
typedef enum {
UART_0 = (int)0x42000800UL, // Base address of SERCOM0
UART_1 = (int)0x42000C00UL, // Base address of SERCOM1
UART_2 = (int)0x42001000UL, // Base address of SERCOM2
UART_3 = (int)0x42001400UL, // Base address of SERCOM3
UART_4 = (int)0x42001800UL, // Base address of SERCOM4
UART_5 = (int)0x42001C00UL // Base address of SERCOM5
} UARTName;
typedef enum {
ADC_0 = 0x0ul,
ADC_1 = 0x1ul,
ADC_2 = 0x2ul,
ADC_3 = 0x3ul,
ADC_4 = 0x4ul,
ADC_5 = 0x5ul,
ADC_6 = 0x6ul,
ADC_7 = 0x7ul,
ADC_10 = 0xAul,
ADC_11 = 0xBul,
ADC_16 = 0x10ul,
ADC_17 = 0x11ul,
ADC_18 = 0x12ul,
ADC_19 = 0x13ul
} ADCName;
typedef enum {
DAC_0 = 0x42004800UL
} DACName;
typedef enum { // for each channel
EXTINT_0 = 0,
EXTINT_1,
EXTINT_2,
EXTINT_3,
EXTINT_4,
EXTINT_5,
EXTINT_6,
EXTINT_7,
EXTINT_8,
EXTINT_9,
EXTINT_10,
EXTINT_11,
EXTINT_12,
EXTINT_13,
EXTINT_14,
EXTINT_15
} EXTINTName;
typedef enum {
MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_NAME, ~)
} SPIName;
typedef enum {
MREPEAT(SERCOM_INST_NUM, _SERCOM_I2C_NAME, ~)
} I2CName;
typedef enum {
/* Pad 0 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 0)
/* Pad 1 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 1)
/* Pad 2 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 2)
/* Pad 3 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 3)
} SercomPadName;
typedef enum {
PWM_0 = (0x42002000UL), /**< \brief (TCC0) APB Base Address */
PWM_1 = (0x42002400UL), /**< \brief (TCC1) APB Base Address */
PWM_2 = (0x42002800UL), /**< \brief (TCC2) APB Base Address */
} PWMName;
struct pwm_pin_channel {
PinName pin;
PWMName pwm;
uint8_t channel_index;
};
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_3
// Default peripherals
#define MBED_SPI0 PA18, PA16, PA19, PA17
#define MBED_UART0 PA04, PA05
#define MBED_UARTUSB USBTX, USBRX
#define MBED_I2C0 PA08, PA09
#define MBED_ANALOGOUT0 PA02
#define MBED_ANALOGIN0 PA03
#define MBED_ANALOGIN1 PA08
#define MBED_ANALOGIN2 PB09
#define MBED_ANALOGIN3 PA04
#define MBED_ANALOGIN4 PA05
#define MBED_ANALOGIN5 PA06
#define MBED_ANALOGIN7 PA07
#define MBED_PWMOUT0 PA18
#define MBED_PWMOUT1 PA19
#ifdef __cplusplus
}
#endif
#endif

244
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralPins.c
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@ -1,244 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************ADC***************/
const PinMap PinMap_ADC[] = {
{PA02, ADC_0, 1},
{PA03, ADC_1, 1},
{PB08, ADC_2, 1},
{PB09, ADC_3, 1},
{PA04, ADC_4, 1},
{PA05, ADC_5, 1},
{PA06, ADC_6, 1},
{PA07, ADC_7, 1},
{PB02, ADC_10, 1},
{PB03, ADC_11, 1},
{PA08, ADC_16, 1},
{PA09, ADC_17, 1},
{PA10, ADC_18, 1},
{PA11, ADC_19, 1},
/* Not connected */
{NC , NC , NC}
};
/************DAC***************/
const PinMap PinMap_DAC[] = {
{PA02, DAC_0, 1},
/* Not connected */
{NC , NC , NC}
};
/************SERCOM Pins***********/
const PinMap PinMap_SERCOM_PAD[] = {
{PA00, SERCOM1_PAD0, 3},
{PA01, SERCOM1_PAD1, 3},
{PA04, SERCOM0_PAD0, 3},
{PA05, SERCOM0_PAD1, 3},
{PA06, SERCOM0_PAD2, 3},
{PA07, SERCOM0_PAD3, 3},
{PA08, SERCOM0_PAD0, 2},
{PA09, SERCOM0_PAD1, 2},
{PA10, SERCOM0_PAD2, 2},
{PA11, SERCOM0_PAD3, 2},
{PA12, SERCOM2_PAD0, 2},
{PA13, SERCOM2_PAD1, 2},
{PA14, SERCOM2_PAD2, 2},
{PA15, SERCOM2_PAD3, 2},
{PA16, SERCOM1_PAD0, 2},
{PA17, SERCOM1_PAD1, 2},
{PA18, SERCOM1_PAD2, 2},
{PA19, SERCOM1_PAD3, 2},
{PA20, SERCOM3_PAD2, 3},
{PA21, SERCOM3_PAD3, 3},
{PA22, SERCOM3_PAD0, 2},
{PA23, SERCOM3_PAD1, 2},
{PA24, SERCOM3_PAD2, 2},
{PA25, SERCOM3_PAD3, 2},
{PA30, SERCOM1_PAD2, 3},
{PA31, SERCOM1_PAD3, 3},
{PB02, SERCOM5_PAD0, 3},
{PB03, SERCOM5_PAD1, 3},
{PB08, SERCOM4_PAD0, 3},
{PB09, SERCOM4_PAD1, 3},
{PB10, SERCOM4_PAD2, 3},
{PB11, SERCOM4_PAD3, 3},
{PB22, SERCOM5_PAD2, 3},
{PB23, SERCOM5_PAD3, 3},
/* Not connected */
{NC , NC , NC}
};
/*******SERCOM Pins extended*******/
const PinMap PinMap_SERCOM_PADEx[] = {
{PA08, SERCOM2_PAD0, 3},
{PA09, SERCOM2_PAD1, 3},
{PA10, SERCOM2_PAD2, 3},
{PA11, SERCOM2_PAD3, 3},
{PA12, SERCOM4_PAD0, 3},
{PA13, SERCOM4_PAD1, 3},
{PA14, SERCOM4_PAD2, 3},
{PA15, SERCOM4_PAD3, 3},
{PA16, SERCOM3_PAD0, 3},
{PA17, SERCOM3_PAD1, 3},
{PA18, SERCOM3_PAD2, 3},
{PA19, SERCOM3_PAD3, 3},
{PA20, SERCOM5_PAD2, 2},
{PA21, SERCOM5_PAD3, 2},
{PA22, SERCOM5_PAD0, 3},
{PA23, SERCOM5_PAD1, 3},
{PA24, SERCOM5_PAD2, 3},
{PA25, SERCOM5_PAD3, 3},
/* Not connected */
{NC , NC , NC}
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
{PA00, PWM_2, 4},
{PA01, PWM_2, 4},
{PA04, PWM_0, 4},
{PA05, PWM_0, 4},
{PA06, PWM_1, 4},
{PA07, PWM_1, 4},
{PA08, PWM_1, 5},
{PA09, PWM_1, 5},
{PA10, PWM_1, 4},
{PA11, PWM_1, 4},
{PA12, PWM_2, 4},
{PA13, PWM_2, 4},
{PA14, PWM_0, 5},
{PA15, PWM_0, 5},
{PA16, PWM_2, 4},
{PA17, PWM_2, 4},
{PA18, PWM_0, 5},
{PA19, PWM_0, 5},
{PA20, PWM_0, 5},
{PA21, PWM_0, 5},
{PA22, PWM_0, 5},
{PA23, PWM_0, 5},
{PA24, PWM_1, 5},
{PA25, PWM_1, 5},
{PA30, PWM_1, 4},
{PA31, PWM_1, 4},
{PB10, PWM_0, 5},
{PB11, PWM_0, 5},
/* Not connected */
{NC , NC , NC}
};
/**********EXTINT*************/
const PinMap PinMap_EXTINT[] = {
{PA16, EXTINT_0, 0},
{PA00, EXTINT_0, 0},
{PA17, EXTINT_1, 0},
{PA01, EXTINT_1, 0},
{PA18, EXTINT_2, 0},
{PA02, EXTINT_2, 0},
{PB02, EXTINT_2, 0},
{PA03, EXTINT_3, 0},
{PA19, EXTINT_3, 0},
{PB03, EXTINT_3, 0},
{PA04, EXTINT_4, 0},
{PA20, EXTINT_4, 0},
{PA05, EXTINT_5, 0},
{PA21, EXTINT_5, 0},
{PA06, EXTINT_6, 0},
{PA22, EXTINT_6, 0},
{PB22, EXTINT_6, 0},
{PA07, EXTINT_7, 0},
{PA23, EXTINT_7, 0},
{PB23, EXTINT_7, 0},
{PA28, EXTINT_8, 0},
{PB08, EXTINT_8, 0},
{PA09, EXTINT_9, 0},
{PB09, EXTINT_9, 0},
{PA10, EXTINT_10, 0},
{PA30, EXTINT_10, 0},
{PB10, EXTINT_10, 0},
{PA11, EXTINT_11, 0},
{PA31, EXTINT_11, 0},
{PB11, EXTINT_11, 0},
{PA12, EXTINT_12, 0},
{PA24, EXTINT_12, 0},
{PA13, EXTINT_13, 0},
{PA25, EXTINT_13, 0},
{PA14, EXTINT_14, 0},
{PA15, EXTINT_15, 0},
{PA27, EXTINT_15, 0},
/* Not connected */
{NC , NC , NC}
};
const struct pwm_pin_channel pwn_pins[] = {
{PA00, PWM_2, 0},
{PA01, PWM_2, 1},
{PA04, PWM_0, 0},
{PA05, PWM_0, 1},
{PA06, PWM_1, 0},
{PA07, PWM_1, 1},
{PA08, PWM_1, 2},
{PA09, PWM_1, 3},
{PA10, PWM_1, 0},
{PA11, PWM_1, 1},
{PA12, PWM_2, 0},
{PA13, PWM_2, 1},
{PA14, PWM_0, 4},
{PA15, PWM_0, 5},
{PA16, PWM_2, 0},
{PA17, PWM_2, 1},
{PA18, PWM_0, 2},
{PA19, PWM_0, 3},
{PA20, PWM_0, 6},
{PA21, PWM_0, 7},
{PA22, PWM_0, 4},
{PA23, PWM_0, 5},
{PA24, PWM_1, 2},
{PA25, PWM_1, 3},
{PA30, PWM_1, 0},
{PA31, PWM_1, 1},
{PB10, PWM_0, 4},
{PB11, PWM_0, 5},
/* Not connected */
{NC , NC , NC}
};

40
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralPins.h
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@ -1,40 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H
#include "pinmap.h"
#include "PeripheralNames.h"
/************ADC***************/
extern const PinMap PinMap_ADC[];
/************DAC***************/
extern const PinMap PinMap_DAC[];
/*********SERCOM*************/
extern const PinMap PinMap_SERCOM_PAD[];
extern const PinMap PinMap_SERCOM_PADEx[];
/************PWM***************/
extern const PinMap PinMap_PWM[];
/**********EXTINT*************/
extern const PinMap PinMap_EXTINT[];
#endif

95
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PinNames.h
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@ -1,95 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT,
PIN_INPUT_OUTPUT //pin state can be set and read back
} PinDirection;
typedef enum {
PA00 = 0,
PA01 = 1,
PA02 = 2,
PA03 = 3,
PA04 = 4,
PA05 = 5,
PA06 = 6,
PA07 = 7,
PA08 = 8,
PA09 = 9,
PA10 = 10,
PA11 = 11,
PA12 = 12,
PA13 = 13,
PA14 = 14,
PA15 = 15,
PA16 = 16,
PA17 = 17,
PA18 = 18,
PA19 = 19,
PA20 = 20,
PA21 = 21,
PA22 = 22,
PA23 = 23,
PA24 = 24,
PA25 = 25,
PA27 = 27,
PA28 = 28,
PA30 = 30,
PA31 = 31,
PB02 = 34,
PB03 = 35,
PB08 = 40,
PB09 = 41,
PB10 = 42,
PB11 = 43,
PB22 = 54,
PB23 = 55,
USBTX = PB10,
USBRX = PB11,
LED1 = PA23,
LED2 = PA23,
LED3 = PA23,
LED4 = PA23,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

32
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/SAMW25_XPLAINED_PRO/mbed_overrides.c
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@ -1,32 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "compiler.h"
#include "system.h"
uint8_t g_sys_init = 0;
//called before main - implement here if board needs it ortherwise, let
// the application override this if necessary
//TODO: To be implemented by adding system init and board init
void mbed_sdk_init()
{
if(g_sys_init == 0) {
g_sys_init = 1;
system_init();
}
}
/***************************************************************/

530
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/SAMW25_XPLAINED_PRO/samw25_xplained_pro.h
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@ -1,530 +0,0 @@
/**
* \file
*
* \brief SAM W25 Xplained Pro board definition
*
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef SAMW25_XPLAINED_PRO_H_INCLUDED
#define SAMW25_XPLAINED_PRO_H_INCLUDED
#include <conf_board.h>
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \ingroup group_common_boards
* \defgroup samd21_xplained_pro_group SAM D21 Xplained Pro board
*
* @{
*/
void system_board_init(void);
/**
* \defgroup samd21_xplained_pro_features_group Features
*
* Symbols that describe features and capabilities of the board.
*
* @{
*/
/** Name string macro */
#define BOARD_NAME "SAMW25_XPLAINED_PRO"
/** \name Resonator definitions
* @{ */
#define BOARD_FREQ_SLCK_XTAL (32768U)
#define BOARD_FREQ_SLCK_BYPASS (32768U)
#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */
#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */
#define BOARD_MCK CHIP_FREQ_CPU_MAX
#define BOARD_OSC_STARTUP_US 15625
/** @} */
/** \name LED0 definitions
* @{ */
#define LED0_PIN PIN_PA23
#define LED0_ACTIVE false
#define LED0_INACTIVE !LED0_ACTIVE
/** @} */
/** \name SW0 definitions
* @{ */
#define SW0_PIN PIN_PB23
#define SW0_ACTIVE false
#define SW0_INACTIVE !SW0_ACTIVE
#define SW0_EIC_PIN PIN_PB23A_EIC_EXTINT7
#define SW0_EIC_MUX MUX_PA23A_EIC_EXTINT7
#define SW0_EIC_PINMUX PINMUX_PA23A_EIC_EXTINT7
#define SW0_EIC_LINE 7
/** @} */
/**
* \name LED #0 definitions
*
* Wrapper macros for LED0, to ensure common naming across all Xplained Pro
* boards.
*
* @{ */
#define LED_0_NAME "LED0 (yellow)"
#define LED_0_PIN LED0_PIN
#define LED_0_ACTIVE LED0_ACTIVE
#define LED_0_INACTIVE LED0_INACTIVE
#define LED0_GPIO LED0_PIN
#define LED0 LED0_PIN
#define LED_0_PWM_MODULE TCC0
#define LED_0_PWM_CHANNEL 0
#define LED_0_PWM_OUTPUT 0
#define LED_0_PWM_PIN PIN_PA23F_TCC0_WO5
#define LED_0_PWM_MUX MUX_PA23F_TCC0_WO5
#define LED_0_PWM_PINMUX PINMUX_PA23F_TCC0_WO5
/** @} */
/** Number of on-board LEDs */
#define LED_COUNT 1
/**
* \name Button #0 definitions
*
* Wrapper macros for SW0, to ensure common naming across all Xplained Pro
* boards.
*
* @{ */
#define BUTTON_0_NAME "SW0"
#define BUTTON_0_PIN SW0_PIN
#define BUTTON_0_ACTIVE SW0_ACTIVE
#define BUTTON_0_INACTIVE SW0_INACTIVE
#define BUTTON_0_EIC_PIN SW0_EIC_PIN
#define BUTTON_0_EIC_MUX SW0_EIC_MUX
#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX
#define BUTTON_0_EIC_LINE SW0_EIC_LINE
/** @} */
/** Number of on-board buttons */
#define BUTTON_COUNT 1
/** \name Extension header #1 pin definitions
* @{
*/
#define EXT1_PIN_3 PIN_PA02
#define EXT1_PIN_4 PIN_PA03
#define EXT1_PIN_5 PIN_PB02
#define EXT1_PIN_6 PIN_PB03
#define EXT1_PIN_7 PIN_PA10
#define EXT1_PIN_8 PIN_PA11
#define EXT1_PIN_9 PIN_PA20
#define EXT1_PIN_10 PIN_PA21
#define EXT1_PIN_11 PIN_PA08
#define EXT1_PIN_12 PIN_PA09
#define EXT1_PIN_13 PIN_PB11
#define EXT1_PIN_14 PIN_PB10
#define EXT1_PIN_15 PIN_PA17
#define EXT1_PIN_16 PIN_PA18
#define EXT1_PIN_17 PIN_PA16
#define EXT1_PIN_18 PIN_PA19
/** @} */
/** \name Extension header #1 pin definitions by function
* @{
*/
#define EXT1_PIN_ADC_0 EXT1_PIN_3
#define EXT1_PIN_ADC_1 EXT1_PIN_4
#define EXT1_PIN_GPIO_0 EXT1_PIN_5
#define EXT1_PIN_GPIO_1 EXT1_PIN_6
#define EXT1_PIN_PWM_0 EXT1_PIN_7
#define EXT1_PIN_PWM_1 EXT1_PIN_8
#define EXT1_PIN_IRQ EXT1_PIN_9
#define EXT1_PIN_I2C_SDA EXT1_PIN_11
#define EXT1_PIN_I2C_SCL EXT1_PIN_12
#define EXT1_PIN_UART_RX EXT1_PIN_13
#define EXT1_PIN_UART_TX EXT1_PIN_14
#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10
#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15
#define EXT1_PIN_SPI_MOSI EXT1_PIN_16
#define EXT1_PIN_SPI_MISO EXT1_PIN_17
#define EXT1_PIN_SPI_SCK EXT1_PIN_18
/** @} */
/** \name Extension header #1 ADC definitions
* @{
*/
#define EXT1_ADC_MODULE ADC
#define EXT1_ADC_0_CHANNEL 0
#define EXT1_ADC_0_PIN PIN_PA02B_ADC_AIN0
#define EXT1_ADC_0_MUX MUX_PA02B_ADC_AIN0
#define EXT1_ADC_0_PINMUX PINMUX_PA02B_ADC_AIN0
#define EXT1_ADC_1_CHANNEL 1
#define EXT1_ADC_1_PIN PIN_PA03B_ADC_AIN1
#define EXT1_ADC_1_MUX MUX_PA03B_ADC_AIN1
#define EXT1_ADC_1_PINMUX PINMUX_PA03B_ADC_AIN1
/** @} */
/** \name Extension header #1 PWM definitions
* @{
*/
#define EXT1_PWM_MODULE TCC0
#define EXT1_PWM_0_CHANNEL 2
#define EXT1_PWM_0_PIN PIN_PA10F_TCC0_WO2
#define EXT1_PWM_0_MUX MUX_PA10F_TCC0_WO2
#define EXT1_PWM_0_PINMUX PINMUX_PA10F_TCC0_WO2
#define EXT1_PWM_1_CHANNEL 3
#define EXT1_PWM_1_PIN PIN_PA11F_TCC0_WO3
#define EXT1_PWM_1_MUX MUX_PA11F_TCC0_WO3
#define EXT1_PWM_1_PINMUX PINMUX_PA11F_TCC0_WO3
/** @} */
/** \name Extension header #1 IRQ/External interrupt definitions
* @{
*/
#define EXT1_IRQ_MODULE EIC
#define EXT1_IRQ_INPUT 4
#define EXT1_IRQ_PIN PIN_PA20A_EIC_EXTINT4
#define EXT1_IRQ_MUX MUX_PA20A_EIC_EXTINT4
#define EXT1_IRQ_PINMUX PINMUX_PA20A_EIC_EXTINT4
/** @} */
/** \name Extension header #1 I2C definitions
* @{
*/
#define EXT1_I2C_MODULE SERCOM0
#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08C_SERCOM0_PAD0
#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09C_SERCOM0_PAD1
/** @} */
/** \name Extension header #1 UART definitions
* @{
*/
#define EXT1_UART_MODULE SERCOM4
#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3
#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED
#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_PB10D_SERCOM4_PAD2
#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_PB11D_SERCOM4_PAD3
/** @} */
/** \name Extension header #1 SPI definitions
* @{
*/
#define EXT1_SPI_MODULE SERCOM1
#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0
#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1
#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2
#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3
/** \name Extension header #3 pin definitions
* @{
*/
#define EXT3_PIN_3 PIN_PA04
#define EXT3_PIN_4 PIN_PA05
#define EXT3_PIN_5 PIN_PB22
#define EXT3_PIN_6 PIN_PB23
#define EXT3_PIN_7 PIN_PA22
#define EXT3_PIN_8 PIN_PA23
#define EXT3_PIN_9 PIN_PA06
#define EXT3_PIN_10 0
#define EXT3_PIN_11 PIN_PA08
#define EXT3_PIN_12 PIN_PA09
#define EXT3_PIN_13 PIN_PA01
#define EXT3_PIN_14 PIN_PA00
#define EXT3_PIN_15 PIN_PA07
#define EXT3_PIN_16 PIN_PA18
#define EXT3_PIN_17 PIN_PA16
#define EXT3_PIN_18 PIN_PA19
/** @} */
/** \name Extension header #3 pin definitions by function
* @{
*/
#define EXT3_PIN_ADC_0 EXT3_PIN_3
#define EXT3_PIN_ADC_1 EXT3_PIN_4
#define EXT3_PIN_GPIO_0 EXT3_PIN_5
#define EXT3_PIN_GPIO_1 EXT3_PIN_6
#define EXT3_PIN_PWM_0 EXT3_PIN_7
#define EXT3_PIN_PWM_1 EXT3_PIN_8
#define EXT3_PIN_IRQ EXT3_PIN_9
#define EXT3_PIN_I2C_SDA EXT3_PIN_11
#define EXT3_PIN_I2C_SCL EXT3_PIN_12
#define EXT3_PIN_UART_RX EXT3_PIN_13
#define EXT3_PIN_UART_TX EXT3_PIN_14
#define EXT3_PIN_SPI_SS_0 EXT3_PIN_15
#define EXT3_PIN_SPI_MOSI EXT3_PIN_16
#define EXT3_PIN_SPI_MISO EXT3_PIN_17
#define EXT3_PIN_SPI_SCK EXT3_PIN_18
/** @} */
/** \name Extension header #3 ADC definitions
* @{
*/
#define EXT3_ADC_MODULE ADC
#define EXT3_ADC_0_CHANNEL 4
#define EXT3_ADC_0_PIN PIN_PA04B_ADC_AIN4
#define EXT3_ADC_0_MUX MUX_PA04B_ADC_AIN4
#define EXT3_ADC_0_PINMUX PINMUX_PA04B_ADC_AIN4
#define EXT3_ADC_1_CHANNEL 5
#define EXT3_ADC_1_PIN PIN_PA05B_ADC_AIN5
#define EXT3_ADC_1_MUX MUX_PA05B_ADC_AIN5
#define EXT3_ADC_1_PINMUX PINMUX_PA05B_ADC_AIN5
/** @} */
/** \name Extension header #3 PWM definitions
* @{
*/
#define EXT3_PWM_MODULE TC4
#define EXT3_PWM_0_CHANNEL 0
#define EXT3_PWM_0_PIN PIN_PA22E_TC4_WO0
#define EXT3_PWM_0_MUX MUX_PA22E_TC4_WO0
#define EXT3_PWM_0_PINMUX PINMUX_PA22E_TC4_WO0
#define EXT3_PWM_1_CHANNEL 1
#define EXT3_PWM_1_PIN PIN_PA23E_TC4_WO1
#define EXT3_PWM_1_MUX MUX_PA23E_TC4_WO1
#define EXT3_PWM_1_PINMUX PINMUX_PA23E_TC4_WO1
/** @} */
/** \name Extension header #3 IRQ/External interrupt definitions
* @{
*/
#define EXT3_IRQ_MODULE EIC
#define EXT3_IRQ_INPUT 6
#define EXT3_IRQ_PIN PIN_PA06A_EIC_EXTINT6
#define EXT3_IRQ_MUX MUX_PA06A_EIC_EXTINT6
#define EXT3_IRQ_PINMUX PINMUX_PA06A_EIC_EXTINT6
/** @} */
/** \name Extension header #3 I2C definitions
* @{
*/
#define EXT3_I2C_MODULE SERCOM0
#define EXT3_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08C_SERCOM0_PAD0
#define EXT3_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09C_SERCOM0_PAD1
/** @} */
/** \name Extension header #3 UART definitions
* @{
*/
#define EXT3_UART_MODULE SERCOM1
#define EXT3_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EXT3_UART_SERCOM_PINMUX_PAD0 PINMUX_PA00D_SERCOM1_PAD0
#define EXT3_UART_SERCOM_PINMUX_PAD1 PINMUX_PA01D_SERCOM1_PAD1
#define EXT3_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EXT3_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
/** @} */
/** \name Extension header #3 SPI definitions
* @{
*/
#define EXT3_SPI_MODULE SERCOM1
#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0
#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED /* PA07 */
#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2
#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3
/** @} */
/** \name Extension header #3 Dataflash
* @{
*/
#define EXT3_DATAFLASH_SPI_MODULE EXT3_SPI_MODULE
#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING
#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0
#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1
#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2
#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3
/** @} */
/** \name USB definitions
* @{
*/
#define USB_ID
#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP
#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP
#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP
#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM
#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM
#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM
#define USB_VBUS_PIN PIN_PA05
#define USB_VBUS_EIC_LINE 5
#define USB_VBUS_EIC_MUX MUX_PA05A_EIC_EXTINT5
#define USB_VBUS_EIC_PINMUX PINMUX_PA05A_EIC_EXTINT5
#define USB_ID_PIN PIN_PA04
#define USB_ID_EIC_LINE 4
#define USB_ID_EIC_MUX MUX_PA04A_EIC_EXTINT4
#define USB_ID_EIC_PINMUX PINMUX_PA04A_EIC_EXTINT4
/** @} */
/** \name Embedded debugger GPIO interface definitions
* @{
*/
#define EDBG_GPIO0_PIN PIN_PB22
#define EDBG_GPIO1_PIN PIN_PB23
#define EDBG_GPIO2_PIN PIN_PA22
#define EDBG_GPIO3_PIN PIN_PA24
/** @} */
/** \name Embedded debugger USART interface definitions
* @{
*/
#define EDBG_UART_MODULE -1 /* Not available on this board */
#define EDBG_UART_RX_PIN -1 /* Not available on this board */
#define EDBG_UART_RX_MUX -1 /* Not available on this board */
#define EDBG_UART_RX_PINMUX -1 /* Not available on this board */
#define EDBG_UART_RX_SERCOM_PAD -1 /* Not available on this board */
#define EDBG_UART_TX_PIN -1 /* Not available on this board */
#define EDBG_UART_TX_MUX -1 /* Not available on this board */
#define EDBG_UART_TX_PINMUX -1 /* Not available on this board */
#define EDBG_UART_TX_SERCOM_PAD -1 /* Not available on this board */
/** @} */
/** \name Embedded debugger I2C interface definitions
* @{
*/
#define EDBG_I2C_MODULE SERCOM0
#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08C_SERCOM0_PAD0
#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09C_SERCOM0_PAD1
/** @} */
/** \name Embedded debugger SPI interface definitions
* @{
*/
#define EDBG_SPI_MODULE SERCOM1
#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0
#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED /* PA_06 */
#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2
#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3
/** @} */
/** \name Embedded debugger CDC Gateway USART interface definitions
* @{
*/
#define EDBG_CDC_MODULE SERCOM4
#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3
#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_PB10D_SERCOM4_PAD2
#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_PB11D_SERCOM4_PAD3
/** @} */
/** @} */
/** \name 802.15.4 TRX Interface definitions
* @{
*/
#define AT86RFX_SPI EXT1_SPI_MODULE
#define AT86RFX_RST_PIN EXT1_PIN_7
#define AT86RFX_MISC_PIN EXT1_PIN_12
#define AT86RFX_IRQ_PIN EXT1_PIN_9
#define AT86RFX_SLP_PIN EXT1_PIN_10
#define AT86RFX_SPI_CS EXT1_PIN_15
#define AT86RFX_SPI_MOSI EXT1_PIN_16
#define AT86RFX_SPI_MISO EXT1_PIN_17
#define AT86RFX_SPI_SCK EXT1_PIN_18
#define AT86RFX_CSD EXT1_PIN_5
#define AT86RFX_CPS EXT1_PIN_8
#define AT86RFX_SPI_SERCOM_MUX_SETTING EXT1_SPI_SERCOM_MUX_SETTING
#define AT86RFX_SPI_SERCOM_PINMUX_PAD0 EXT1_SPI_SERCOM_PINMUX_PAD0
#define AT86RFX_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define AT86RFX_SPI_SERCOM_PINMUX_PAD2 EXT1_SPI_SERCOM_PINMUX_PAD2
#define AT86RFX_SPI_SERCOM_PINMUX_PAD3 EXT1_SPI_SERCOM_PINMUX_PAD3
#define AT86RFX_IRQ_CHAN EXT1_IRQ_INPUT
#define AT86RFX_IRQ_PINMUX EXT1_IRQ_PINMUX
/** Enables the transceiver main interrupt. */
#define ENABLE_TRX_IRQ()
/** Disables the transceiver main interrupt. */
#define DISABLE_TRX_IRQ()
/** Clears the transceiver main interrupt. */
#define CLEAR_TRX_IRQ()
/*
* This macro saves the trx interrupt status and disables the trx interrupt.
*/
#define ENTER_TRX_REGION()
/*
* This macro restores the transceiver interrupt status
*/
#define LEAVE_TRX_REGION()
/** @} */
/**
* \brief Turns off the specified LEDs.
*
* \param led_gpio LED to turn off (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true)
/**
* \brief Turns on the specified LEDs.
*
* \param led_gpio LED to turn on (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false)
/**
* \brief Toggles the specified LEDs.
*
* \param led_gpio LED to toggle (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio)
#ifdef __cplusplus
}
#endif
#endif /* SAMW25_XPLAINED_PRO_H_INCLUDED */

115
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/analogout_api.c
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@ -1,115 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogout_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "PeripheralPins.h"
#include "dac.h"
struct dac_module dac_instance;
extern uint8_t g_sys_init;
#define MAX_VAL_10BIT 0x03FF
void analogout_init(dac_t *obj, PinName pin)
{
MBED_ASSERT(obj);
if (g_sys_init == 0) {
system_init();
g_sys_init = 1;
}
struct dac_config config_dac;
struct dac_chan_config config_dac_chan;
uint32_t pos_input;
pos_input = pinmap_find_peripheral(pin, PinMap_DAC);
MBED_ASSERT(pos_input != NC);
obj->dac = DAC_0;
dac_get_config_defaults(&config_dac);
dac_init(&dac_instance, (Dac *)DAC_0, &config_dac);
dac_chan_get_config_defaults(&config_dac_chan);
dac_chan_set_config(&dac_instance, DAC_CHANNEL_0, &config_dac_chan);
dac_chan_enable(&dac_instance, DAC_CHANNEL_0);
dac_enable(&dac_instance);
}
void analogout_free(dac_t *obj)
{
MBED_ASSERT(obj);
struct system_pinmux_config pin_conf;
dac_disable(&dac_instance);
pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_UP;
pin_conf.powersave = false;
pin_conf.mux_position = SYSTEM_PINMUX_GPIO;
system_pinmux_pin_set_config(PA02, &pin_conf); /*PA02 is the only DAC pin available*/
}
void analogout_write(dac_t *obj, float value)
{
MBED_ASSERT(obj);
uint16_t count_val = 0;
if (value < 0.0f) {
count_val = 0;
} else if (value > 1.0f) {
count_val = MAX_VAL_10BIT;
} else {
count_val = (uint16_t)(value * (float)MAX_VAL_10BIT);
}
dac_chan_write(&dac_instance, DAC_CHANNEL_0, count_val);
}
void analogout_write_u16(dac_t *obj, uint16_t value)
{
MBED_ASSERT(obj);
uint16_t count_val;
count_val = (uint16_t)((value * (float)MAX_VAL_10BIT) / 0xFFFF); /*Normalization to the value 0xFFFF*/
dac_chan_write(&dac_instance, DAC_CHANNEL_0, count_val);
}
static uint32_t data_reg_read(dac_t *obj)
{
Dac *const dac_module = (Dac *)obj->dac;
return (uint32_t)dac_module->DATA.reg;
}
float analogout_read(dac_t *obj)
{
MBED_ASSERT(obj);
uint32_t data_val = data_reg_read(obj);
return data_val/(float)MAX_VAL_10BIT;
}
uint16_t analogout_read_u16(dac_t *obj)
{
MBED_ASSERT(obj);
uint32_t data_val = data_reg_read(obj);
return (uint16_t)((data_val / (float)MAX_VAL_10BIT) * 0xFFFF); /*Normalization to the value 0xFFFF*/
}
const PinMap *analogout_pinmap()
{
return PinMap_DAC;
}

38
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device.h
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@ -1,38 +0,0 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

50
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/SAMD21G18A.sct
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@ -1,50 +0,0 @@
#! armcc -E
;SAMD21G18A
; 256KB FLASH (0x40000) @ 0x000000000
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
; SAMD21G18A: 256KB FLASH (0x40000)
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x40000
#endif
; 32KB RAM (0x8000) @ 0x20000000
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x8000
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment
#define VECTOR_SIZE 0xB8
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

190
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.S
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@ -1,190 +0,0 @@
;/*****************************************************************************
; * @file startup_SAMD21.s
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
; * Atmel SAMD21 Device Series
; * @version V1.00
; * @date 24. February 2014
; *
; * @note
; * Copyright (C) 2014 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PM_Handler ; 0 Power Manager
DCD SYSCTRL_Handler ; 1 System Control
DCD WDT_Handler ; 2 Watchdog Timer
DCD RTC_Handler ; 3 Real-Time Counter
DCD EIC_Handler ; 4 External Interrupt Controller
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
DCD DMAC_Handler ; 6 Direct Memory Access Controller
DCD USB_Handler ; 7 Universal Serial Bus
DCD EVSYS_Handler ; 8 Event System Interface
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
DCD TCC0_Handler ; 15 Timer Counter Control 0
DCD TCC1_Handler ; 16 Timer Counter Control 1
DCD TCC2_Handler ; 17 Timer Counter Control 2
DCD TC3_Handler ; 18 Basic Timer Counter 0
DCD TC4_Handler ; 19 Basic Timer Counter 1
DCD TC5_Handler ; 20 Basic Timer Counter 2
DCD TC6_Handler ; 21 Basic Timer Counter 3
DCD TC7_Handler ; 22 Basic Timer Counter 4
DCD ADC_Handler ; 23 Analog Digital Converter
DCD AC_Handler ; 24 Analog Comparators
DCD DAC_Handler ; 25 Digital Analog Converter
DCD PTC_Handler ; 26 Peripheral Touch Controller
DCD I2S_Handler ; 27 Inter-IC Sound Interface
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PM_Handler [WEAK]
EXPORT PM_Handler [WEAK]
EXPORT SYSCTRL_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT EIC_Handler [WEAK]
EXPORT NVMCTRL_Handler [WEAK]
EXPORT DMAC_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT EVSYS_Handler [WEAK]
EXPORT SERCOM0_Handler [WEAK]
EXPORT SERCOM1_Handler [WEAK]
EXPORT SERCOM2_Handler [WEAK]
EXPORT SERCOM3_Handler [WEAK]
EXPORT SERCOM4_Handler [WEAK]
EXPORT SERCOM5_Handler [WEAK]
EXPORT TCC0_Handler [WEAK]
EXPORT TCC1_Handler [WEAK]
EXPORT TCC2_Handler [WEAK]
EXPORT TC3_Handler [WEAK]
EXPORT TC4_Handler [WEAK]
EXPORT TC5_Handler [WEAK]
EXPORT TC6_Handler [WEAK]
EXPORT TC7_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT AC_Handler [WEAK]
EXPORT DAC_Handler [WEAK]
EXPORT PTC_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
PM_Handler
SYSCTRL_Handler
WDT_Handler
RTC_Handler
EIC_Handler
NVMCTRL_Handler
DMAC_Handler
USB_Handler
EVSYS_Handler
SERCOM0_Handler
SERCOM1_Handler
SERCOM2_Handler
SERCOM3_Handler
SERCOM4_Handler
SERCOM5_Handler
TCC0_Handler
TCC1_Handler
TCC2_Handler
TC3_Handler
TC4_Handler
TC5_Handler
TC6_Handler
TC7_Handler
ADC_Handler
AC_Handler
DAC_Handler
PTC_Handler
I2S_Handler
B .
ENDP
ALIGN
END

27
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/SAMD21G18A.sct
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@ -1,27 +0,0 @@
#! armcc -E
;SAMD21G18A
;256KB FLASH (0x40000) @ 0x000000000
;2KB RAM (0x8000) @ 0x20000000
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define Stack_Size MBED_BOOT_STACK_SIZE
;SAMD21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
LR_IROM1 0x00000000 0x40000 { ; load region size_region
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment
RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK 0x20000000+0x8000 EMPTY -Stack_Size { ; Stack region growing down
}
}

190
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.S
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@ -1,190 +0,0 @@
;/*****************************************************************************
; * @file startup_SAMD21.s
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
; * Atmel SAMD21 Device Series
; * @version V1.00
; * @date 24. February 2014
; *
; * @note
; * Copyright (C) 2014 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PM_Handler ; 0 Power Manager
DCD SYSCTRL_Handler ; 1 System Control
DCD WDT_Handler ; 2 Watchdog Timer
DCD RTC_Handler ; 3 Real-Time Counter
DCD EIC_Handler ; 4 External Interrupt Controller
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
DCD DMAC_Handler ; 6 Direct Memory Access Controller
DCD USB_Handler ; 7 Universal Serial Bus
DCD EVSYS_Handler ; 8 Event System Interface
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
DCD TCC0_Handler ; 15 Timer Counter Control 0
DCD TCC1_Handler ; 16 Timer Counter Control 1
DCD TCC2_Handler ; 17 Timer Counter Control 2
DCD TC3_Handler ; 18 Basic Timer Counter 0
DCD TC4_Handler ; 19 Basic Timer Counter 1
DCD TC5_Handler ; 20 Basic Timer Counter 2
DCD TC6_Handler ; 21 Basic Timer Counter 3
DCD TC7_Handler ; 22 Basic Timer Counter 4
DCD ADC_Handler ; 23 Analog Digital Converter
DCD AC_Handler ; 24 Analog Comparators
DCD DAC_Handler ; 25 Digital Analog Converter
DCD PTC_Handler ; 26 Peripheral Touch Controller
DCD I2S_Handler ; 27 Inter-IC Sound Interface
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PM_Handler [WEAK]
EXPORT PM_Handler [WEAK]
EXPORT SYSCTRL_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT EIC_Handler [WEAK]
EXPORT NVMCTRL_Handler [WEAK]
EXPORT DMAC_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT EVSYS_Handler [WEAK]
EXPORT SERCOM0_Handler [WEAK]
EXPORT SERCOM1_Handler [WEAK]
EXPORT SERCOM2_Handler [WEAK]
EXPORT SERCOM3_Handler [WEAK]
EXPORT SERCOM4_Handler [WEAK]
EXPORT SERCOM5_Handler [WEAK]
EXPORT TCC0_Handler [WEAK]
EXPORT TCC1_Handler [WEAK]
EXPORT TCC2_Handler [WEAK]
EXPORT TC3_Handler [WEAK]
EXPORT TC4_Handler [WEAK]
EXPORT TC5_Handler [WEAK]
EXPORT TC6_Handler [WEAK]
EXPORT TC7_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT AC_Handler [WEAK]
EXPORT DAC_Handler [WEAK]
EXPORT PTC_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
PM_Handler
SYSCTRL_Handler
WDT_Handler
RTC_Handler
EIC_Handler
NVMCTRL_Handler
DMAC_Handler
USB_Handler
EVSYS_Handler
SERCOM0_Handler
SERCOM1_Handler
SERCOM2_Handler
SERCOM3_Handler
SERCOM4_Handler
SERCOM5_Handler
TCC0_Handler
TCC1_Handler
TCC2_Handler
TC3_Handler
TC4_Handler
TC5_Handler
TC6_Handler
TC7_Handler
ADC_Handler
AC_Handler
DAC_Handler
PTC_Handler
I2S_Handler
B .
ENDP
ALIGN
END

127
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_GCC_ARM/samd21g18a.ld
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@ -1,127 +0,0 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Memory Spaces Definitions */
MEMORY {
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
ram (rwx) : ORIGIN = 0x20000000 + 0xB8, LENGTH = 0x00008000 - 0xB8
}
/* Section Definitions */
SECTIONS {
.text :
{
. = ALIGN(8);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(8);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(8);
KEEP(*(.fini))
. = ALIGN(8);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(8);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(8);
_etext = .;
.relocate :
AT (_etext)
{
. = ALIGN(8);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(8);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(8);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(8);
_ebss = . ;
_ezero = .;
} > ram
.heap (NOLOAD) :
{
. = ALIGN(8);
__end__ = . ;
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
__HeapLimit = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
__StackLimit = __StackTop - STACK_SIZE;
. = ALIGN(8);
}

158
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_GCC_ARM/startup_samd21.c
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@ -1,158 +0,0 @@
#include "samd21.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M0+ core handlers */
void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Exception Table */
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
(void*) (&_estack),
(void*) Reset_Handler,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
(void*) USB_Handler, /* 7 Universal Serial Bus */
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
(void*) ADC_Handler, /* 23 Analog Digital Converter */
(void*) AC_Handler, /* 24 Analog Comparators */
(void*) DAC_Handler, /* 25 Digital Analog Converter */
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
(void*) I2S_Handler /* 27 Inter-IC Sound Interface */
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */ // expected to be done by MBED OS
main();
/* Infinite loop */
while (1);
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

173
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_IAR/startup_samd21.c
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@ -1,173 +0,0 @@
#include "samd21.h"
void __iar_program_start(void);
int __low_level_init(void);
void Dummy_Handler(void);
void Reset_Handler(void);
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}
/* Cortex-M0+ core handlers */
void NMI_Handler ( void );
void HardFault_Handler ( void );
void SVC_Handler ( void );
void PendSV_Handler ( void );
void SysTick_Handler ( void );
/* Peripherals handlers */
void PM_Handler ( void );
void SYSCTRL_Handler ( void );
void WDT_Handler ( void );
void RTC_Handler ( void );
void EIC_Handler ( void );
void NVMCTRL_Handler ( void );
void DMAC_Handler ( void );
void USB_Handler ( void );
void EVSYS_Handler ( void );
void SERCOM0_Handler ( void );
void SERCOM1_Handler ( void );
void SERCOM2_Handler ( void );
void SERCOM3_Handler ( void );
void SERCOM4_Handler ( void );
void SERCOM5_Handler ( void );
void TCC0_Handler ( void );
void TCC1_Handler ( void );
void TCC2_Handler ( void );
void TC3_Handler ( void );
void TC4_Handler ( void );
void TC5_Handler ( void );
void TC6_Handler ( void );
void TC7_Handler ( void );
void ADC_Handler ( void );
void AC_Handler ( void );
void DAC_Handler ( void );
void PTC_Handler ( void );
void I2S_Handler ( void );
/* Cortex-M0+ core handlers */
#pragma weak NMI_Handler = Dummy_Handler
#pragma weak HardFault_Handler = Dummy_Handler
#pragma weak SVC_Handler = Dummy_Handler
#pragma weak PendSV_Handler = Dummy_Handler
#pragma weak SysTick_Handler = Dummy_Handler
/* Peripherals handlers */
#pragma weak PM_Handler = Dummy_Handler
#pragma weak SYSCTRL_Handler = Dummy_Handler
#pragma weak WDT_Handler = Dummy_Handler
#pragma weak RTC_Handler = Dummy_Handler
#pragma weak EIC_Handler = Dummy_Handler
#pragma weak NVMCTRL_Handler = Dummy_Handler
#pragma weak DMAC_Handler = Dummy_Handler
#pragma weak USB_Handler = Dummy_Handler
#pragma weak EVSYS_Handler = Dummy_Handler
#pragma weak SERCOM0_Handler = Dummy_Handler
#pragma weak SERCOM1_Handler = Dummy_Handler
#pragma weak SERCOM2_Handler = Dummy_Handler
#pragma weak SERCOM3_Handler = Dummy_Handler
#pragma weak SERCOM4_Handler = Dummy_Handler
#pragma weak SERCOM5_Handler = Dummy_Handler
#pragma weak TCC0_Handler = Dummy_Handler
#pragma weak TCC1_Handler = Dummy_Handler
#pragma weak TCC2_Handler = Dummy_Handler
#pragma weak TC3_Handler = Dummy_Handler
#pragma weak TC4_Handler = Dummy_Handler
#pragma weak TC5_Handler = Dummy_Handler
#pragma weak TC6_Handler = Dummy_Handler
#pragma weak TC7_Handler = Dummy_Handler
#pragma weak ADC_Handler = Dummy_Handler
#pragma weak AC_Handler = Dummy_Handler
#pragma weak DAC_Handler = Dummy_Handler
#pragma weak PTC_Handler = Dummy_Handler
#pragma weak I2S_Handler = Dummy_Handler
/* Exception Table */
#pragma language=extended
#pragma segment="CSTACK"
/* The name "__vector_table" has special meaning for C-SPY: */
/* it is where the SP start value is found, and the NVIC vector */
/* table register (VTOR) is initialized to this address if != 0 */
#pragma section = ".intvec"
#pragma location = ".intvec"
//! [startup_vector_table]
const DeviceVectors __vector_table[] = {
__sfe("CSTACK"),
(void*) __iar_program_start,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
(void*) USB_Handler, /* 7 Universal Serial Bus */
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
(void*) ADC_Handler, /* 23 Analog Digital Converter */
(void*) AC_Handler, /* 24 Analog Comparators */
(void*) DAC_Handler, /* 25 Digital Analog Converter */
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
(void*) I2S_Handler /* 27 Inter-IC Sound Interface */
};
//! [startup_vector_table]
/**------------------------------------------------------------------------------
* This is the code that gets called on processor reset. To initialize the
* device.
*------------------------------------------------------------------------------*/
int __low_level_init(void)
{
uint32_t *pSrc = __section_begin(".intvec");
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
return 1; /* if return 0, the data sections will not be initialized */
}
/**------------------------------------------------------------------------------
* This is the code that gets called on processor reset. To initialize the
* device.
*------------------------------------------------------------------------------*/
void Reset_Handler(void)
{
__iar_program_start();
}

158
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include <compiler.h>
#include "cmsis.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
#define _SERCOM_SPI_NAME(n, unused) \
SPI##n,
#define _SERCOM_PAD_NAME(n, pad) \
SERCOM##n##_PAD##pad = ((n & 0xF) | ((pad & 0xF) << 4)),
#define _SERCOM_I2C_NAME(n, unused) \
I2C##n,
typedef enum {
UART_0 = (int)0x42000800UL, // Base address of SERCOM0
UART_1 = (int)0x42000C00UL, // Base address of SERCOM1
UART_2 = (int)0x42001000UL, // Base address of SERCOM2
UART_3 = (int)0x42001400UL, // Base address of SERCOM3
UART_4 = (int)0x42001800UL, // Base address of SERCOM4
UART_5 = (int)0x42001C00UL // Base address of SERCOM5
} UARTName;
typedef enum {
ADC_0 = 0x0ul,
ADC_1 = 0x1ul,
ADC_2 = 0x2ul,
ADC_3 = 0x3ul,
ADC_4 = 0x4ul,
ADC_5 = 0x5ul,
ADC_6 = 0x6ul,
ADC_7 = 0x7ul,
ADC_8 = 0x8ul,
ADC_9 = 0x8ul,
ADC_10 = 0xAul,
ADC_11 = 0xBul,
ADC_12 = 0xCul,
ADC_13 = 0xDul,
ADC_14 = 0xEul,
ADC_15 = 0xFul,
ADC_16 = 0x10ul,
ADC_17 = 0x11ul,
ADC_18 = 0x12ul,
ADC_19 = 0x13ul
} ADCName;
typedef enum {
DAC_0 = 0x42004800UL
} DACName;
typedef enum { // for each channel
EXTINT_0 = 0,
EXTINT_1,
EXTINT_2,
EXTINT_3,
EXTINT_4,
EXTINT_5,
EXTINT_6,
EXTINT_7,
EXTINT_8,
EXTINT_9,
EXTINT_10,
EXTINT_11,
EXTINT_12,
EXTINT_13,
EXTINT_14,
EXTINT_15
} EXTINTName;
typedef enum {
MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_NAME, ~)
} SPIName;
typedef enum {
MREPEAT(SERCOM_INST_NUM, _SERCOM_I2C_NAME, ~)
} I2CName;
typedef enum {
/* Pad 0 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 0)
/* Pad 1 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 1)
/* Pad 2 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 2)
/* Pad 3 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 3)
} SercomPadName;
typedef enum {
PWM_0 = (0x42002000UL), /**< \brief (TCC0) APB Base Address */
PWM_1 = (0x42002400UL), /**< \brief (TCC1) APB Base Address */
PWM_2 = (0x42002800UL), /**< \brief (TCC2) APB Base Address */
} PWMName;
struct pwm_pin_channel {
PinName pin;
PWMName pwm;
uint8_t channel_index;
};
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_3
// Default peripherals
#define MBED_SPI0 PA18, PA16, PA19, PA17
#define MBED_UART0 PA04, PA05
#define MBED_UARTUSB USBTX, USBRX
#define MBED_I2C0 PA08, PA09
#define MBED_ANALOGOUT0 PA02
#define MBED_ANALOGIN0 PA03
#define MBED_ANALOGIN1 PA08
#define MBED_ANALOGIN2 PB09
#define MBED_ANALOGIN3 PA04
#define MBED_ANALOGIN4 PA05
#define MBED_ANALOGIN5 PA06
#define MBED_ANALOGIN7 PA07
#define MBED_ANALOGIN8 PB00
#define MBED_ANALOGIN9 PB01
#define MBED_PWMOUT0 PA18
#define MBED_PWMOUT1 PA19
#ifdef __cplusplus
}
#endif
#endif

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@ -1,286 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************ADC***************/
const PinMap PinMap_ADC[] = {
{PA02, ADC_0, 1},
{PA03, ADC_1, 1},
{PB08, ADC_2, 1},
{PB09, ADC_3, 1},
{PA04, ADC_4, 1},
{PA05, ADC_5, 1},
{PA06, ADC_6, 1},
{PA07, ADC_7, 1},
{PB00, ADC_8, 1},
{PB01, ADC_9, 1},
{PB02, ADC_10, 1},
{PB03, ADC_11, 1},
{PB04, ADC_12, 1},
{PB05, ADC_13, 1},
{PB06, ADC_14, 1},
{PB07, ADC_15, 1},
{PA08, ADC_16, 1},
{PA09, ADC_17, 1},
{PA10, ADC_18, 1},
{PA11, ADC_19, 1},
/* Not connected */
{NC , NC , NC}
};
/************DAC***************/
const PinMap PinMap_DAC[] = {
{PA02, DAC_0, 1},
/* Not connected */
{NC , NC , NC}
};
/************SERCOM Pins***********/
const PinMap PinMap_SERCOM_PAD[] = {
{PA00, SERCOM1_PAD0, 3},
{PA01, SERCOM1_PAD1, 3},
{PA04, SERCOM0_PAD0, 3},
{PA05, SERCOM0_PAD1, 3},
{PA06, SERCOM0_PAD2, 3},
{PA07, SERCOM0_PAD3, 3},
{PA08, SERCOM0_PAD0, 2},
{PA09, SERCOM0_PAD1, 2},
{PA10, SERCOM0_PAD2, 2},
{PA11, SERCOM0_PAD3, 2},
{PA12, SERCOM2_PAD0, 2},
{PA13, SERCOM2_PAD1, 2},
{PA14, SERCOM2_PAD2, 2},
{PA15, SERCOM2_PAD3, 2},
{PA16, SERCOM1_PAD0, 2},
{PA17, SERCOM1_PAD1, 2},
{PA18, SERCOM1_PAD2, 2},
{PA19, SERCOM1_PAD3, 2},
{PA20, SERCOM3_PAD2, 3},
{PA21, SERCOM3_PAD3, 3},
{PA22, SERCOM3_PAD0, 2},
{PA23, SERCOM3_PAD1, 2},
{PA24, SERCOM3_PAD2, 2},
{PA25, SERCOM3_PAD3, 2},
{PA30, SERCOM1_PAD2, 3},
{PA31, SERCOM1_PAD3, 3},
{PB00, SERCOM5_PAD2, 3},
{PB01, SERCOM5_PAD3, 3},
{PB02, SERCOM5_PAD0, 3},
{PB03, SERCOM5_PAD1, 3},
{PB08, SERCOM4_PAD0, 3},
{PB09, SERCOM4_PAD1, 3},
{PB10, SERCOM4_PAD2, 3},
{PB11, SERCOM4_PAD3, 3},
{PB12, SERCOM4_PAD0, 2},
{PB13, SERCOM4_PAD1, 2},
{PB14, SERCOM4_PAD2, 2},
{PB15, SERCOM4_PAD3, 2},
{PB16, SERCOM5_PAD0, 2},
{PB17, SERCOM5_PAD1, 2},
{PB22, SERCOM5_PAD2, 3},
{PB23, SERCOM5_PAD3, 3},
{PB30, SERCOM5_PAD0, 3},
{PB31, SERCOM5_PAD1, 3},
/* Not connected */
{NC , NC , NC}
};
/*******SERCOM Pins extended*******/
const PinMap PinMap_SERCOM_PADEx[] = {
{PA08, SERCOM2_PAD0, 3},
{PA09, SERCOM2_PAD1, 3},
{PA10, SERCOM2_PAD2, 3},
{PA11, SERCOM2_PAD3, 3},
{PA12, SERCOM4_PAD0, 3},
{PA13, SERCOM4_PAD1, 3},
{PA14, SERCOM4_PAD2, 3},
{PA15, SERCOM4_PAD3, 3},
{PA16, SERCOM3_PAD0, 3},
{PA17, SERCOM3_PAD1, 3},
{PA18, SERCOM3_PAD2, 3},
{PA19, SERCOM3_PAD3, 3},
{PA20, SERCOM5_PAD2, 2},
{PA21, SERCOM5_PAD3, 2},
{PA22, SERCOM5_PAD0, 3},
{PA23, SERCOM5_PAD1, 3},
{PA24, SERCOM5_PAD2, 3},
{PA25, SERCOM5_PAD3, 3},
/* Not connected */
{NC , NC , NC}
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
{PA00, PWM_2, 4},
{PA01, PWM_2, 4},
{PA04, PWM_0, 4},
{PA05, PWM_0, 4},
{PA06, PWM_1, 4},
{PA07, PWM_1, 4},
{PA08, PWM_1, 5},
{PA09, PWM_1, 5},
{PA10, PWM_1, 4},
{PA11, PWM_1, 4},
{PA12, PWM_2, 4},
{PA13, PWM_2, 4},
{PA14, PWM_0, 5},
{PA15, PWM_0, 5},
{PA16, PWM_2, 4},
{PA17, PWM_2, 4},
{PA18, PWM_0, 5},
{PA19, PWM_0, 5},
{PA20, PWM_0, 5},
{PA21, PWM_0, 5},
{PA22, PWM_0, 5},
{PA23, PWM_0, 5},
{PA24, PWM_1, 5},
{PA25, PWM_1, 5},
{PA30, PWM_1, 4},
{PA31, PWM_1, 4},
{PB10, PWM_0, 5},
{PB11, PWM_0, 5},
{PB12, PWM_0, 5},
{PB13, PWM_0, 5},
{PB16, PWM_0, 5},
{PB17, PWM_0, 5},
{PB30, PWM_1, 5},
{PB31, PWM_1, 5},
/* Not connected */
{NC , NC , NC}
};
/**********EXTINT*************/
const PinMap PinMap_EXTINT[] = {
{PA16, EXTINT_0, 0},
{PB00, EXTINT_0, 0},
{PB16, EXTINT_0, 0},
{PA00, EXTINT_0, 0},
{PA17, EXTINT_1, 0},
{PB01, EXTINT_1, 0},
{PB17, EXTINT_1, 0},
{PA01, EXTINT_1, 0},
{PA18, EXTINT_2, 0},
{PA02, EXTINT_2, 0},
{PB02, EXTINT_2, 0},
{PA03, EXTINT_3, 0},
{PA19, EXTINT_3, 0},
{PB03, EXTINT_3, 0},
{PA04, EXTINT_4, 0},
{PA20, EXTINT_4, 0},
{PB04, EXTINT_4, 0},
{PA05, EXTINT_5, 0},
{PA21, EXTINT_5, 0},
{PB05, EXTINT_5, 0},
{PA06, EXTINT_6, 0},
{PA22, EXTINT_6, 0},
{PB06, EXTINT_6, 0},
{PB22, EXTINT_6, 0},
{PA07, EXTINT_7, 0},
{PA23, EXTINT_7, 0},
{PB07, EXTINT_7, 0},
{PB23, EXTINT_7, 0},
{PA28, EXTINT_8, 0},
{PB08, EXTINT_8, 0},
{PA09, EXTINT_9, 0},
{PB09, EXTINT_9, 0},
{PA10, EXTINT_10, 0},
{PA30, EXTINT_10, 0},
{PB10, EXTINT_10, 0},
{PA11, EXTINT_11, 0},
{PA31, EXTINT_11, 0},
{PB11, EXTINT_11, 0},
{PA12, EXTINT_12, 0},
{PA24, EXTINT_12, 0},
{PB12, EXTINT_12, 0},
{PA13, EXTINT_13, 0},
{PA25, EXTINT_13, 0},
{PB13, EXTINT_13, 0},
{PB14, EXTINT_14, 0},
{PB30, EXTINT_14, 0},
{PA14, EXTINT_14, 0},
{PA15, EXTINT_15, 0},
{PA27, EXTINT_15, 0},
{PB15, EXTINT_15, 0},
{PB31, EXTINT_15, 0},
/* Not connected */
{NC , NC , NC}
};
const struct pwm_pin_channel pwn_pins[] = {
{PA00, PWM_2, 0},
{PA01, PWM_2, 1},
{PA04, PWM_0, 0},
{PA05, PWM_0, 1},
{PA06, PWM_1, 0},
{PA07, PWM_1, 1},
{PA08, PWM_1, 2},
{PA09, PWM_1, 3},
{PA10, PWM_1, 0},
{PA11, PWM_1, 1},
{PA12, PWM_2, 0},
{PA13, PWM_2, 1},
{PA14, PWM_0, 4},
{PA15, PWM_0, 5},
{PA16, PWM_2, 0},
{PA17, PWM_2, 1},
{PA18, PWM_0, 2},
{PA19, PWM_0, 3},
{PA20, PWM_0, 6},
{PA21, PWM_0, 7},
{PA22, PWM_0, 4},
{PA23, PWM_0, 5},
{PA24, PWM_1, 2},
{PA25, PWM_1, 3},
{PA30, PWM_1, 0},
{PA31, PWM_1, 1},
{PB10, PWM_0, 4},
{PB11, PWM_0, 5},
{PB12, PWM_0, 6},
{PB13, PWM_0, 7},
{PB16, PWM_0, 4},
{PB17, PWM_0, 5},
{PB30, PWM_1, 2},
{PB31, PWM_1, 3},
/* Not connected */
{NC , NC , NC}
};

40
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralPins.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H
#include "pinmap.h"
#include "PeripheralNames.h"
/************ADC***************/
extern const PinMap PinMap_ADC[];
/************DAC***************/
extern const PinMap PinMap_DAC[];
/*********SERCOM*************/
extern const PinMap PinMap_SERCOM_PAD[];
extern const PinMap PinMap_SERCOM_PADEx[];
/************PWM***************/
extern const PinMap PinMap_PWM[];
/**********EXTINT*************/
extern const PinMap PinMap_EXTINT[];
#endif

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT,
PIN_INPUT_OUTPUT //pin state can be set and read back
} PinDirection;
typedef enum {
PA00 = 0,
PA01 = 1,
PA02 = 2,
PA03 = 3,
PA04 = 4,
PA05 = 5,
PA06 = 6,
PA07 = 7,
PA08 = 8,
PA09 = 9,
PA10 = 10,
PA11 = 11,
PA12 = 12,
PA13 = 13,
PA14 = 14,
PA15 = 15,
PA16 = 16,
PA17 = 17,
PA18 = 18,
PA19 = 19,
PA20 = 20,
PA21 = 21,
PA22 = 22,
PA23 = 23,
PA24 = 24,
PA25 = 25,
PA27 = 27,
PA28 = 28,
PA30 = 30,
PA31 = 31,
PB00 = 32,
PB01 = 33,
PB02 = 34,
PB03 = 35,
PB04 = 36,
PB05 = 37,
PB06 = 38,
PB07 = 39,
PB08 = 40,
PB09 = 41,
PB10 = 42,
PB11 = 43,
PB12 = 44,
PB13 = 45,
PB14 = 46,
PB15 = 47,
PB16 = 48,
PB17 = 49,
PB22 = 54,
PB23 = 55,
PB30 = 62,
PB31 = 63,
USBTX = PA22,
USBRX = PA23,
LED1 = PB30,
LED2 = PB30,
LED3 = PB30,
LED4 = PB30,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/mbed_overrides.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "compiler.h"
#include "system.h"
uint8_t g_sys_init = 0;
//called before main - implement here if board needs it ortherwise, let
// the application override this if necessary
//TODO: To be implemented by adding system init and board init
void mbed_sdk_init()
{
if(g_sys_init == 0) {
g_sys_init = 1;
system_init();
}
}
/***************************************************************/

662
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/samd21_xplained_pro.h
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@ -1,662 +0,0 @@
#ifndef SAMD21_XPLAINED_PRO_H_INCLUDED
#define SAMD21_XPLAINED_PRO_H_INCLUDED
#include <conf_board.h>
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \ingroup group_common_boards
* \defgroup samd21_xplained_pro_group SAM D21 Xplained Pro board
*
* @{
*/
void system_board_init(void);
/**
* \defgroup samd21_xplained_pro_features_group Features
*
* Symbols that describe features and capabilities of the board.
*
* @{
*/
/** Name string macro */
#define BOARD_NAME "SAMD21_XPLAINED_PRO"
/** \name Resonator definitions
* @{ */
#define BOARD_FREQ_SLCK_XTAL (32768U)
#define BOARD_FREQ_SLCK_BYPASS (32768U)
#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */
#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */
#define BOARD_MCK CHIP_FREQ_CPU_MAX
#define BOARD_OSC_STARTUP_US 15625
/** @} */
/** \name LED0 definitions
* @{ */
#define LED0_PIN PIN_PB30
#define LED0_ACTIVE false
#define LED0_INACTIVE !LED0_ACTIVE
/** @} */
/** \name SW0 definitions
* @{ */
#define SW0_PIN PIN_PA15
#define SW0_ACTIVE false
#define SW0_INACTIVE !SW0_ACTIVE
#define SW0_EIC_PIN PIN_PA15A_EIC_EXTINT15
#define SW0_EIC_MUX MUX_PA15A_EIC_EXTINT15
#define SW0_EIC_PINMUX PINMUX_PA15A_EIC_EXTINT15
#define SW0_EIC_LINE 15
/** @} */
/**
* \name LED #0 definitions
*
* Wrapper macros for LED0, to ensure common naming across all Xplained Pro
* boards.
*
* @{ */
#define LED_0_NAME "LED0 (yellow)"
#define LED_0_PIN LED0_PIN
#define LED_0_ACTIVE LED0_ACTIVE
#define LED_0_INACTIVE LED0_INACTIVE
#define LED0_GPIO LED0_PIN
#define LED0 LED0_PIN
#define LED_0_PWM4CTRL_MODULE TCC0
#define LED_0_PWM4CTRL_CHANNEL 0
#define LED_0_PWM4CTRL_OUTPUT 0
#define LED_0_PWM4CTRL_PIN PIN_PB30E_TCC0_WO0
#define LED_0_PWM4CTRL_MUX MUX_PB30E_TCC0_WO0
#define LED_0_PWM4CTRL_PINMUX PINMUX_PB30E_TCC0_WO0
/** @} */
/** Number of on-board LEDs */
#define LED_COUNT 1
/**
* \name Serialflash definitions
*
* On board Serialflash definitions.
*
* @{ */
#define SERIALFLASH_SPI_MODULE SERCOM5
#define SERIALFLASH_SPI_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define SERIALFLASH_SPI_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
#define SERIALFLASH_SPI_PINMUX_PAD1 PINMUX_UNUSED
#define SERIALFLASH_SPI_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define SERIALFLASH_SPI_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define SERIALFLASH_SPI_CS PIN_PA13
/** @} */
/**
* \name Button #0 definitions
*
* Wrapper macros for SW0, to ensure common naming across all Xplained Pro
* boards.
*
* @{ */
#define BUTTON_0_NAME "SW0"
#define BUTTON_0_PIN SW0_PIN
#define BUTTON_0_ACTIVE SW0_ACTIVE
#define BUTTON_0_INACTIVE SW0_INACTIVE
#define BUTTON_0_EIC_PIN SW0_EIC_PIN
#define BUTTON_0_EIC_MUX SW0_EIC_MUX
#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX
#define BUTTON_0_EIC_LINE SW0_EIC_LINE
/** @} */
/** Number of on-board buttons */
#define BUTTON_COUNT 1
/** \name Extension header #1 pin definitions
* @{
*/
#define EXT1_PIN_3 PIN_PB00
#define EXT1_PIN_4 PIN_PB01
#define EXT1_PIN_5 PIN_PB06
#define EXT1_PIN_6 PIN_PB07
#define EXT1_PIN_7 PIN_PB02
#define EXT1_PIN_8 PIN_PB03
#define EXT1_PIN_9 PIN_PB04
#define EXT1_PIN_10 PIN_PB05
#define EXT1_PIN_11 PIN_PA08
#define EXT1_PIN_12 PIN_PA09
#define EXT1_PIN_13 PIN_PB09
#define EXT1_PIN_14 PIN_PB08
#define EXT1_PIN_15 PIN_PA05
#define EXT1_PIN_16 PIN_PA06
#define EXT1_PIN_17 PIN_PA04
#define EXT1_PIN_18 PIN_PA07
/** @} */
/** \name Extension header #1 pin definitions by function
* @{
*/
#define EXT1_PIN_ADC_0 EXT1_PIN_3
#define EXT1_PIN_ADC_1 EXT1_PIN_4
#define EXT1_PIN_GPIO_0 EXT1_PIN_5
#define EXT1_PIN_GPIO_1 EXT1_PIN_6
#define EXT1_PIN_PWM_0 EXT1_PIN_7
#define EXT1_PIN_PWM_1 EXT1_PIN_8
#define EXT1_PIN_IRQ EXT1_PIN_9
#define EXT1_PIN_I2C_SDA EXT1_PIN_11
#define EXT1_PIN_I2C_SCL EXT1_PIN_12
#define EXT1_PIN_UART_RX EXT1_PIN_13
#define EXT1_PIN_UART_TX EXT1_PIN_14
#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10
#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15
#define EXT1_PIN_SPI_MOSI EXT1_PIN_16
#define EXT1_PIN_SPI_MISO EXT1_PIN_17
#define EXT1_PIN_SPI_SCK EXT1_PIN_18
/** @} */
/** \name Extension header #1 ADC definitions
* @{
*/
#define EXT1_ADC_MODULE ADC
#define EXT1_ADC_0_CHANNEL 8
#define EXT1_ADC_0_PIN PIN_PB00B_ADC_AIN8
#define EXT1_ADC_0_MUX MUX_PB00B_ADC_AIN8
#define EXT1_ADC_0_PINMUX PINMUX_PB00B_ADC_AIN8
#define EXT1_ADC_1_CHANNEL 9
#define EXT1_ADC_1_PIN PIN_PB01B_ADC_AIN9
#define EXT1_ADC_1_MUX MUX_PB01B_ADC_AIN9
#define EXT1_ADC_1_PINMUX PINMUX_PB01B_ADC_AIN9
/** @} */
/** \name Extension header #1 PWM definitions
* @{
*/
#define EXT1_PWM_MODULE TC6
#define EXT1_PWM_0_CHANNEL 0
#define EXT1_PWM_0_PIN PIN_PB02E_TC6_WO0
#define EXT1_PWM_0_MUX MUX_PB02E_TC6_WO0
#define EXT1_PWM_0_PINMUX PINMUX_PB02E_TC6_WO0
#define EXT1_PWM_1_CHANNEL 1
#define EXT1_PWM_1_PIN PIN_PB03E_TC6_WO1
#define EXT1_PWM_1_MUX MUX_PB03E_TC6_WO1
#define EXT1_PWM_1_PINMUX PINMUX_PB03E_TC6_WO1
/** @} */
/** \name Extension header #1 IRQ/External interrupt definitions
* @{
*/
#define EXT1_IRQ_MODULE EIC
#define EXT1_IRQ_INPUT 4
#define EXT1_IRQ_PIN PIN_PB04A_EIC_EXTINT4
#define EXT1_IRQ_MUX MUX_PB04A_EIC_EXTINT4
#define EXT1_IRQ_PINMUX PINMUX_PB04A_EIC_EXTINT4
/** @} */
/** \name Extension header #1 I2C definitions
* @{
*/
#define EXT1_I2C_MODULE SERCOM2
#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EXT1_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EXT1_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Extension header #1 UART definitions
* @{
*/
#define EXT1_UART_MODULE SERCOM4
#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_PB08D_SERCOM4_PAD0
#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_PB09D_SERCOM4_PAD1
#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EXT1_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
#define EXT1_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
/** @} */
/** \name Extension header #1 SPI definitions
* @{
*/
#define EXT1_SPI_MODULE SERCOM0
#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0
#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1
#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA06D_SERCOM0_PAD2
#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA07D_SERCOM0_PAD3
#define EXT1_SPI_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX
#define EXT1_SPI_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX
/** @} */
/** \name Extension header #2 pin definitions
* @{
*/
#define EXT2_PIN_3 PIN_PA10
#define EXT2_PIN_4 PIN_PA11
#define EXT2_PIN_5 PIN_PA20
#define EXT2_PIN_6 PIN_PA21
#define EXT2_PIN_7 PIN_PB12
#define EXT2_PIN_8 PIN_PB13
#define EXT2_PIN_9 PIN_PB14
#define EXT2_PIN_10 PIN_PB15
#define EXT2_PIN_11 PIN_PA08
#define EXT2_PIN_12 PIN_PA09
#define EXT2_PIN_13 PIN_PB11
#define EXT2_PIN_14 PIN_PB10
#define EXT2_PIN_15 PIN_PA17
#define EXT2_PIN_16 PIN_PA18
#define EXT2_PIN_17 PIN_PA16
#define EXT2_PIN_18 PIN_PA19
/** @} */
/** \name Extension header #2 pin definitions by function
* @{
*/
#define EXT2_PIN_ADC_0 EXT2_PIN_3
#define EXT2_PIN_ADC_1 EXT2_PIN_4
#define EXT2_PIN_GPIO_0 EXT2_PIN_5
#define EXT2_PIN_GPIO_1 EXT2_PIN_6
#define EXT2_PIN_PWM_0 EXT2_PIN_7
#define EXT2_PIN_PWM_1 EXT2_PIN_8
#define EXT2_PIN_IRQ EXT2_PIN_9
#define EXT2_PIN_I2C_SDA EXT2_PIN_11
#define EXT2_PIN_I2C_SCL EXT2_PIN_12
#define EXT2_PIN_UART_RX EXT2_PIN_13
#define EXT2_PIN_UART_TX EXT2_PIN_14
#define EXT2_PIN_SPI_SS_1 EXT2_PIN_10
#define EXT2_PIN_SPI_SS_0 EXT2_PIN_15
#define EXT2_PIN_SPI_MOSI EXT2_PIN_16
#define EXT2_PIN_SPI_MISO EXT2_PIN_17
#define EXT2_PIN_SPI_SCK EXT2_PIN_18
/** @} */
/** \name Extension header #2 ADC definitions
* @{
*/
#define EXT2_ADC_MODULE ADC
#define EXT2_ADC_0_CHANNEL 18
#define EXT2_ADC_0_PIN PIN_PA10B_ADC_AIN18
#define EXT2_ADC_0_MUX MUX_PA10B_ADC_AIN18
#define EXT2_ADC_0_PINMUX PINMUX_PA10B_ADC_AIN18
#define EXT2_ADC_1_CHANNEL 19
#define EXT2_ADC_1_PIN PIN_PA11B_ADC_AIN19
#define EXT2_ADC_1_MUX MUX_PA11B_ADC_AIN19
#define EXT2_ADC_1_PINMUX PINMUX_PA11B_ADC_AIN19
/** @} */
/** \name Extension header #2 PWM definitions
* @{
*/
#define EXT2_PWM_MODULE TC4
#define EXT2_PWM_0_CHANNEL 0
#define EXT2_PWM_0_PIN PIN_PB12E_TC4_WO0
#define EXT2_PWM_0_MUX MUX_PB12E_TC4_WO0
#define EXT2_PWM_0_PINMUX PINMUX_PB12E_TC4_WO0
#define EXT2_PWM_1_CHANNEL 1
#define EXT2_PWM_1_PIN PIN_PB13E_TC4_WO1
#define EXT2_PWM_1_MUX MUX_PB13E_TC4_WO1
#define EXT2_PWM_1_PINMUX PINMUX_PB13E_TC4_WO1
/** @} */
/** \name Extension header #2 PWM for Control definitions
* @{
*/
#define EXT2_PWM4CTRL_MODULE TCC0
#define EXT2_PWM4CTRL_0_CHANNEL 2
#define EXT2_PWM4CTRL_0_OUTPUT 6
#define EXT2_PWM4CTRL_0_PIN PIN_PB12F_TCC0_WO6
#define EXT2_PWM4CTRL_0_MUX MUX_PB12F_TCC0_WO6
#define EXT2_PWM4CTRL_0_PINMUX PINMUX_PB12F_TCC0_WO6
#define EXT2_PWM4CTRL_1_CHANNEL 3
#define EXT2_PWM4CTRL_1_OUTPUT 7
#define EXT2_PWM4CTRL_1_PIN PIN_PB13F_TCC0_WO7
#define EXT2_PWM4CTRL_1_MUX MUX_PB13F_TCC0_WO7
#define EXT2_PWM4CTRL_1_PINMUX PINMUX_PB13F_TCC0_WO7
/** @} */
/** \name Extension header #2 IRQ/External interrupt definitions
* @{
*/
#define EXT2_IRQ_MODULE EIC
#define EXT2_IRQ_INPUT 14
#define EXT2_IRQ_PIN PIN_PB14A_EIC_EXTINT14
#define EXT2_IRQ_MUX MUX_PB14A_EIC_EXTINT14
#define EXT2_IRQ_PINMUX PINMUX_PB14A_EIC_EXTINT14
/** @} */
/** \name Extension header #2 I2C definitions
* @{
*/
#define EXT2_I2C_MODULE SERCOM2
#define EXT2_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EXT2_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EXT2_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EXT2_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Extension header #2 UART definitions
* @{
*/
#define EXT2_UART_MODULE SERCOM4
#define EXT2_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EXT2_UART_SERCOM_PINMUX_PAD0 PINMUX_PB12C_SERCOM4_PAD0
#define EXT2_UART_SERCOM_PINMUX_PAD1 PINMUX_PB13C_SERCOM4_PAD1
#define EXT2_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EXT2_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EXT2_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
#define EXT2_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
/** @} */
/** \name Extension header #2 SPI definitions
* @{
*/
#define EXT2_SPI_MODULE SERCOM1
#define EXT2_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT2_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0
#define EXT2_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1
#define EXT2_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2
#define EXT2_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3
#define EXT2_SPI_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX
#define EXT2_SPI_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX
/** @} */
/** \name Extension header #3 pin definitions
* @{
*/
#define EXT3_PIN_3 PIN_PA02
#define EXT3_PIN_4 PIN_PA03
#define EXT3_PIN_5 PIN_PB30
#define EXT3_PIN_6 PIN_PA15
#define EXT3_PIN_7 PIN_PA12
#define EXT3_PIN_8 PIN_PA13
#define EXT3_PIN_9 PIN_PA28
#define EXT3_PIN_10 PIN_PA27
#define EXT3_PIN_11 PIN_PA08
#define EXT3_PIN_12 PIN_PA09
#define EXT3_PIN_13 PIN_PB11
#define EXT3_PIN_14 PIN_PB10
#define EXT3_PIN_15 PIN_PB17
#define EXT3_PIN_16 PIN_PB22
#define EXT3_PIN_17 PIN_PB16
#define EXT3_PIN_18 PIN_PB23
/** @} */
/** \name Extension header #3 pin definitions by function
* @{
*/
#define EXT3_PIN_ADC_0 EXT3_PIN_3
#define EXT3_PIN_ADC_1 EXT3_PIN_4
#define EXT3_PIN_GPIO_0 EXT3_PIN_5
#define EXT3_PIN_GPIO_1 EXT3_PIN_6
#define EXT3_PIN_PWM_0 EXT3_PIN_7
#define EXT3_PIN_PWM_1 EXT3_PIN_8
#define EXT3_PIN_IRQ EXT3_PIN_9
#define EXT3_PIN_I2C_SDA EXT3_PIN_11
#define EXT3_PIN_I2C_SCL EXT3_PIN_12
#define EXT3_PIN_UART_RX EXT3_PIN_13
#define EXT3_PIN_UART_TX EXT3_PIN_14
#define EXT3_PIN_SPI_SS_1 EXT3_PIN_10
#define EXT3_PIN_SPI_SS_0 EXT3_PIN_15
#define EXT3_PIN_SPI_MOSI EXT3_PIN_16
#define EXT3_PIN_SPI_MISO EXT3_PIN_17
#define EXT3_PIN_SPI_SCK EXT3_PIN_18
/** @} */
/** \name Extension header #3 ADC definitions
* @{
*/
#define EXT3_ADC_MODULE ADC
#define EXT3_ADC_0_CHANNEL 0
#define EXT3_ADC_0_PIN PIN_PA02B_ADC_AIN0
#define EXT3_ADC_0_MUX MUX_PA02B_ADC_AIN0
#define EXT3_ADC_0_PINMUX PINMUX_PA02B_ADC_AIN0
#define EXT3_ADC_1_CHANNEL 1
#define EXT3_ADC_1_PIN PIN_PA03B_ADC_AIN1
#define EXT3_ADC_1_MUX MUX_PA03B_ADC_AIN1
#define EXT3_ADC_1_PINMUX PINMUX_PA03B_ADC_AIN1
/** @} */
/** \name Extension header #3 PWM for Control definitions
* @{
*/
#define EXT3_PWM4CTRL_MODULE TCC2
#define EXT3_PWM4CTRL_0_CHANNEL 0
#define EXT3_PWM4CTRL_0_OUTPUT 0
#define EXT3_PWM4CTRL_0_PIN PIN_PA12E_TCC2_WO0
#define EXT3_PWM4CTRL_0_MUX MUX_PA12E_TCC2_WO0
#define EXT3_PWM4CTRL_0_PINMUX PINMUX_PA12E_TCC2_WO0
#define EXT3_PWM4CTRL_1_CHANNEL 1
#define EXT3_PWM4CTRL_1_OUTPUT 1
#define EXT3_PWM4CTRL_1_PIN PIN_PA13E_TCC2_WO1
#define EXT3_PWM4CTRL_1_MUX MUX_PA13E_TCC2_WO1
#define EXT3_PWM4CTRL_1_PINMUX PINMUX_PA13E_TCC2_WO1
/** @} */
/** \name Extension header #3 IRQ/External interrupt definitions
* @{
*/
#define EXT3_IRQ_MODULE EIC
#define EXT3_IRQ_INPUT 8
#define EXT3_IRQ_PIN PIN_PA28A_EIC_EXTINT8
#define EXT3_IRQ_MUX MUX_PA28A_EIC_EXTINT8
#define EXT3_IRQ_PINMUX PINMUX_PA28A_EIC_EXTINT8
/** @} */
/** \name Extension header #3 I2C definitions
* @{
*/
#define EXT3_I2C_MODULE SERCOM2
#define EXT3_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EXT3_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EXT3_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EXT3_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Extension header #3 UART definitions
* @{
*/
#define EXT3_UART_MODULE SERCOM4
#define EXT3_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3
#define EXT3_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED
#define EXT3_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define EXT3_UART_SERCOM_PINMUX_PAD2 PINMUX_PB10D_SERCOM4_PAD2
#define EXT3_UART_SERCOM_PINMUX_PAD3 PINMUX_PB11D_SERCOM4_PAD3
#define EXT3_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
#define EXT3_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
/** @} */
/** \name Extension header #3 SPI definitions
* @{
*/
#define EXT3_SPI_MODULE SERCOM5
#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB17C_SERCOM5_PAD1
#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EXT3_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EXT3_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Extension header #3 Dataflash
* @{
*/
#define EXT3_DATAFLASH_SPI_MODULE EXT3_SPI_MODULE
#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING
#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0
#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1
#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2
#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3
/** @} */
/** \name USB definitions
* @{
*/
#define USB_ID
#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP
#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP
#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP
#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM
#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM
#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM
#define USB_VBUS_PIN PIN_PA14
#define USB_VBUS_EIC_LINE 14
#define USB_VBUS_EIC_MUX MUX_PA14A_EIC_EXTINT14
#define USB_VBUS_EIC_PINMUX PINMUX_PA14A_EIC_EXTINT14
#define USB_ID_PIN PIN_PA03
#define USB_ID_EIC_LINE 3
#define USB_ID_EIC_MUX MUX_PA03A_EIC_EXTINT3
#define USB_ID_EIC_PINMUX PINMUX_PA03A_EIC_EXTINT3
/** @} */
/** \name Embedded debugger GPIO interface definitions
* @{
*/
#define EDBG_GPIO0_PIN PIN_PA27
#define EDBG_GPIO1_PIN PIN_PA28
#define EDBG_GPIO2_PIN PIN_PA20
#define EDBG_GPIO3_PIN PIN_PA21
/** @} */
/** \name Embedded debugger USART interface definitions
* @{
*/
#define EDBG_UART_MODULE -1 /* Not available on this board */
#define EDBG_UART_RX_PIN -1 /* Not available on this board */
#define EDBG_UART_RX_MUX -1 /* Not available on this board */
#define EDBG_UART_RX_PINMUX -1 /* Not available on this board */
#define EDBG_UART_RX_SERCOM_PAD -1 /* Not available on this board */
#define EDBG_UART_TX_PIN -1 /* Not available on this board */
#define EDBG_UART_TX_MUX -1 /* Not available on this board */
#define EDBG_UART_TX_PINMUX -1 /* Not available on this board */
#define EDBG_UART_TX_SERCOM_PAD -1 /* Not available on this board */
/** @} */
/** \name Embedded debugger I2C interface definitions
* @{
*/
#define EDBG_I2C_MODULE SERCOM2
#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EDBG_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EDBG_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Embedded debugger SPI interface definitions
* @{
*/
#define EDBG_SPI_MODULE SERCOM5
#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB31D_SERCOM5_PAD1
#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EDBG_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EDBG_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Embedded debugger CDC Gateway USART interface definitions
* @{
*/
#define EDBG_CDC_MODULE SERCOM3
#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_PA22C_SERCOM3_PAD0
#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_PA23C_SERCOM3_PAD1
#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_DMAC_ID_TX SERCOM3_DMAC_ID_TX
#define EDBG_CDC_SERCOM_DMAC_ID_RX SERCOM3_DMAC_ID_RX
/** @} */
/** @} */
/** \name 802.15.4 TRX Interface definitions
* @{
*/
#define AT86RFX_SPI EXT1_SPI_MODULE
#define AT86RFX_RST_PIN EXT1_PIN_7
#define AT86RFX_MISC_PIN EXT1_PIN_12
#define AT86RFX_IRQ_PIN EXT1_PIN_9
#define AT86RFX_SLP_PIN EXT1_PIN_10
#define AT86RFX_SPI_CS EXT1_PIN_15
#define AT86RFX_SPI_MOSI EXT1_PIN_16
#define AT86RFX_SPI_MISO EXT1_PIN_17
#define AT86RFX_SPI_SCK EXT1_PIN_18
#define AT86RFX_CSD EXT1_PIN_5
#define AT86RFX_CPS EXT1_PIN_8
#define AT86RFX_SPI_SERCOM_MUX_SETTING EXT1_SPI_SERCOM_MUX_SETTING
#define AT86RFX_SPI_SERCOM_PINMUX_PAD0 EXT1_SPI_SERCOM_PINMUX_PAD0
#define AT86RFX_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define AT86RFX_SPI_SERCOM_PINMUX_PAD2 EXT1_SPI_SERCOM_PINMUX_PAD2
#define AT86RFX_SPI_SERCOM_PINMUX_PAD3 EXT1_SPI_SERCOM_PINMUX_PAD3
#define AT86RFX_IRQ_CHAN EXT1_IRQ_INPUT
#define AT86RFX_IRQ_PINMUX EXT1_IRQ_PINMUX
/** Enables the transceiver main interrupt. */
#define ENABLE_TRX_IRQ() \
extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
/** Disables the transceiver main interrupt. */
#define DISABLE_TRX_IRQ() \
extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
/** Clears the transceiver main interrupt. */
#define CLEAR_TRX_IRQ() \
extint_chan_clear_detected(AT86RFX_IRQ_CHAN);
/*
* This macro saves the trx interrupt status and disables the trx interrupt.
*/
#define ENTER_TRX_REGION() \
{ extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
/*
* This macro restores the transceiver interrupt status
*/
#define LEAVE_TRX_REGION() \
extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); }
/** @} */
/**
* \brief Turns off the specified LEDs.
*
* \param led_gpio LED to turn off (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true)
/**
* \brief Turns on the specified LEDs.
*
* \param led_gpio LED to turn on (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false)
/**
* \brief Toggles the specified LEDs.
*
* \param led_gpio LED to toggle (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* SAMD21_XPLAINED_PRO_H_INCLUDED */

115
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/analogout_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogout_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "PeripheralPins.h"
#include "dac.h"
struct dac_module dac_instance;
extern uint8_t g_sys_init;
#define MAX_VAL_10BIT 0x03FF
void analogout_init(dac_t *obj, PinName pin)
{
MBED_ASSERT(obj);
if (g_sys_init == 0) {
system_init();
g_sys_init = 1;
}
struct dac_config config_dac;
struct dac_chan_config config_dac_chan;
uint32_t pos_input;
pos_input = pinmap_find_peripheral(pin, PinMap_DAC);
MBED_ASSERT(pos_input != NC);
obj->dac = DAC_0;
dac_get_config_defaults(&config_dac);
dac_init(&dac_instance, (Dac *)DAC_0, &config_dac);
dac_chan_get_config_defaults(&config_dac_chan);
dac_chan_set_config(&dac_instance, DAC_CHANNEL_0, &config_dac_chan);
dac_chan_enable(&dac_instance, DAC_CHANNEL_0);
dac_enable(&dac_instance);
}
void analogout_free(dac_t *obj)
{
MBED_ASSERT(obj);
struct system_pinmux_config pin_conf;
dac_disable(&dac_instance);
pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_UP;
pin_conf.powersave = false;
pin_conf.mux_position = SYSTEM_PINMUX_GPIO;
system_pinmux_pin_set_config(PA02, &pin_conf); /*PA02 is the only DAC pin available*/
}
void analogout_write(dac_t *obj, float value)
{
MBED_ASSERT(obj);
uint16_t count_val = 0;
if (value < 0.0f) {
count_val = 0;
} else if (value > 1.0f) {
count_val = MAX_VAL_10BIT;
} else {
count_val = (uint16_t)(value * (float)MAX_VAL_10BIT);
}
dac_chan_write(&dac_instance, DAC_CHANNEL_0, count_val);
}
void analogout_write_u16(dac_t *obj, uint16_t value)
{
MBED_ASSERT(obj);
uint16_t count_val;
count_val = (uint16_t)((value * (float)MAX_VAL_10BIT) / 0xFFFF); /*Normalization to the value 0xFFFF*/
dac_chan_write(&dac_instance, DAC_CHANNEL_0, count_val);
}
static uint32_t data_reg_read(dac_t *obj)
{
Dac *const dac_module = (Dac *)obj->dac;
return (uint32_t)dac_module->DATA.reg;
}
float analogout_read(dac_t *obj)
{
MBED_ASSERT(obj);
uint32_t data_val = data_reg_read(obj);
return data_val/(float)MAX_VAL_10BIT;
}
uint16_t analogout_read_u16(dac_t *obj)
{
MBED_ASSERT(obj);
uint32_t data_val = data_reg_read(obj);
return (uint16_t)((data_val / (float)MAX_VAL_10BIT) * 0xFFFF); /*Normalization to the value 0xFFFF*/
}
const PinMap *analogout_pinmap()
{
return PinMap_DAC;
}

38
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device.h
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@ -1,38 +0,0 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

50
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/SAMD21J18A.sct
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@ -1,50 +0,0 @@
#! armcc -E
;SAMD21J18A
; 256KB FLASH (0x40000) @ 0x000000000
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
; SAMD21J18A: 256KB FLASH (0x40000)
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x40000
#endif
; 32KB RAM (0x8000) @ 0x20000000
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x8000
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment
#define VECTOR_SIZE 0xB8
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

190
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.S
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@ -1,190 +0,0 @@
;/*****************************************************************************
; * @file startup_SAMD21.s
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
; * Atmel SAMD21 Device Series
; * @version V1.00
; * @date 24. February 2014
; *
; * @note
; * Copyright (C) 2014 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PM_Handler ; 0 Power Manager
DCD SYSCTRL_Handler ; 1 System Control
DCD WDT_Handler ; 2 Watchdog Timer
DCD RTC_Handler ; 3 Real-Time Counter
DCD EIC_Handler ; 4 External Interrupt Controller
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
DCD DMAC_Handler ; 6 Direct Memory Access Controller
DCD USB_Handler ; 7 Universal Serial Bus
DCD EVSYS_Handler ; 8 Event System Interface
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
DCD TCC0_Handler ; 15 Timer Counter Control 0
DCD TCC1_Handler ; 16 Timer Counter Control 1
DCD TCC2_Handler ; 17 Timer Counter Control 2
DCD TC3_Handler ; 18 Basic Timer Counter 0
DCD TC4_Handler ; 19 Basic Timer Counter 1
DCD TC5_Handler ; 20 Basic Timer Counter 2
DCD TC6_Handler ; 21 Basic Timer Counter 3
DCD TC7_Handler ; 22 Basic Timer Counter 4
DCD ADC_Handler ; 23 Analog Digital Converter
DCD AC_Handler ; 24 Analog Comparators
DCD DAC_Handler ; 25 Digital Analog Converter
DCD PTC_Handler ; 26 Peripheral Touch Controller
DCD I2S_Handler ; 27 Inter-IC Sound Interface
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PM_Handler [WEAK]
EXPORT PM_Handler [WEAK]
EXPORT SYSCTRL_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT EIC_Handler [WEAK]
EXPORT NVMCTRL_Handler [WEAK]
EXPORT DMAC_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT EVSYS_Handler [WEAK]
EXPORT SERCOM0_Handler [WEAK]
EXPORT SERCOM1_Handler [WEAK]
EXPORT SERCOM2_Handler [WEAK]
EXPORT SERCOM3_Handler [WEAK]
EXPORT SERCOM4_Handler [WEAK]
EXPORT SERCOM5_Handler [WEAK]
EXPORT TCC0_Handler [WEAK]
EXPORT TCC1_Handler [WEAK]
EXPORT TCC2_Handler [WEAK]
EXPORT TC3_Handler [WEAK]
EXPORT TC4_Handler [WEAK]
EXPORT TC5_Handler [WEAK]
EXPORT TC6_Handler [WEAK]
EXPORT TC7_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT AC_Handler [WEAK]
EXPORT DAC_Handler [WEAK]
EXPORT PTC_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
PM_Handler
SYSCTRL_Handler
WDT_Handler
RTC_Handler
EIC_Handler
NVMCTRL_Handler
DMAC_Handler
USB_Handler
EVSYS_Handler
SERCOM0_Handler
SERCOM1_Handler
SERCOM2_Handler
SERCOM3_Handler
SERCOM4_Handler
SERCOM5_Handler
TCC0_Handler
TCC1_Handler
TCC2_Handler
TC3_Handler
TC4_Handler
TC5_Handler
TC6_Handler
TC7_Handler
ADC_Handler
AC_Handler
DAC_Handler
PTC_Handler
I2S_Handler
B .
ENDP
ALIGN
END

27
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/SAMD21J18A.sct
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@ -1,27 +0,0 @@
#! armcc -E
;SAMD21J18A
;256KB FLASH (0x40000) @ 0x000000000
;2KB RAM (0x8000) @ 0x20000000
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define Stack_Size MBED_BOOT_STACK_SIZE
;SAMD21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
LR_IROM1 0x00000000 0x40000 { ; load region size_region
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment
RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8-Stack_Size) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK 0x20000000+0x8000 EMPTY -Stack_Size { ; Stack region growing down
}
}

190
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.S
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@ -1,190 +0,0 @@
;/*****************************************************************************
; * @file startup_SAMD21.s
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
; * Atmel SAMD21 Device Series
; * @version V1.00
; * @date 24. February 2014
; *
; * @note
; * Copyright (C) 2014 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PM_Handler ; 0 Power Manager
DCD SYSCTRL_Handler ; 1 System Control
DCD WDT_Handler ; 2 Watchdog Timer
DCD RTC_Handler ; 3 Real-Time Counter
DCD EIC_Handler ; 4 External Interrupt Controller
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
DCD DMAC_Handler ; 6 Direct Memory Access Controller
DCD USB_Handler ; 7 Universal Serial Bus
DCD EVSYS_Handler ; 8 Event System Interface
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
DCD TCC0_Handler ; 15 Timer Counter Control 0
DCD TCC1_Handler ; 16 Timer Counter Control 1
DCD TCC2_Handler ; 17 Timer Counter Control 2
DCD TC3_Handler ; 18 Basic Timer Counter 0
DCD TC4_Handler ; 19 Basic Timer Counter 1
DCD TC5_Handler ; 20 Basic Timer Counter 2
DCD TC6_Handler ; 21 Basic Timer Counter 3
DCD TC7_Handler ; 22 Basic Timer Counter 4
DCD ADC_Handler ; 23 Analog Digital Converter
DCD AC_Handler ; 24 Analog Comparators
DCD DAC_Handler ; 25 Digital Analog Converter
DCD PTC_Handler ; 26 Peripheral Touch Controller
DCD I2S_Handler ; 27 Inter-IC Sound Interface
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PM_Handler [WEAK]
EXPORT PM_Handler [WEAK]
EXPORT SYSCTRL_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT EIC_Handler [WEAK]
EXPORT NVMCTRL_Handler [WEAK]
EXPORT DMAC_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT EVSYS_Handler [WEAK]
EXPORT SERCOM0_Handler [WEAK]
EXPORT SERCOM1_Handler [WEAK]
EXPORT SERCOM2_Handler [WEAK]
EXPORT SERCOM3_Handler [WEAK]
EXPORT SERCOM4_Handler [WEAK]
EXPORT SERCOM5_Handler [WEAK]
EXPORT TCC0_Handler [WEAK]
EXPORT TCC1_Handler [WEAK]
EXPORT TCC2_Handler [WEAK]
EXPORT TC3_Handler [WEAK]
EXPORT TC4_Handler [WEAK]
EXPORT TC5_Handler [WEAK]
EXPORT TC6_Handler [WEAK]
EXPORT TC7_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT AC_Handler [WEAK]
EXPORT DAC_Handler [WEAK]
EXPORT PTC_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
PM_Handler
SYSCTRL_Handler
WDT_Handler
RTC_Handler
EIC_Handler
NVMCTRL_Handler
DMAC_Handler
USB_Handler
EVSYS_Handler
SERCOM0_Handler
SERCOM1_Handler
SERCOM2_Handler
SERCOM3_Handler
SERCOM4_Handler
SERCOM5_Handler
TCC0_Handler
TCC1_Handler
TCC2_Handler
TC3_Handler
TC4_Handler
TC5_Handler
TC6_Handler
TC7_Handler
ADC_Handler
AC_Handler
DAC_Handler
PTC_Handler
I2S_Handler
B .
ENDP
ALIGN
END

127
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_GCC_ARM/samd21j18a.ld
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@ -1,127 +0,0 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Memory Spaces Definitions */
MEMORY {
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
ram (rwx) : ORIGIN = 0x20000000 + 0xB8, LENGTH = 0x00008000 - 0xB8
}
/* Section Definitions */
SECTIONS {
.text :
{
. = ALIGN(8);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(8);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(8);
KEEP(*(.fini))
. = ALIGN(8);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(8);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(8);
_etext = .;
.relocate :
AT (_etext)
{
. = ALIGN(8);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(8);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(8);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(8);
_ebss = . ;
_ezero = .;
} > ram
.heap (NOLOAD) :
{
. = ALIGN(8);
__end__ = . ;
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
__HeapLimit = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
. = ALIGN(8);
}

158
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_GCC_ARM/startup_samd21.c
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@ -1,158 +0,0 @@
#include "samd21.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M0+ core handlers */
void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Exception Table */
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
(void*) (&_estack),
(void*) Reset_Handler,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
(void*) USB_Handler, /* 7 Universal Serial Bus */
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
(void*) ADC_Handler, /* 23 Analog Digital Converter */
(void*) AC_Handler, /* 24 Analog Comparators */
(void*) DAC_Handler, /* 25 Digital Analog Converter */
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
(void*) I2S_Handler /* 27 Inter-IC Sound Interface */
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */ // expected to be done by MBED OS
main();
/* Infinite loop */
while (1);
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

173
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_IAR/startup_samd21.c
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@ -1,173 +0,0 @@
#include "samd21.h"
void __iar_program_start(void);
int __low_level_init(void);
void Dummy_Handler(void);
void Reset_Handler(void);
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}
/* Cortex-M0+ core handlers */
void NMI_Handler ( void );
void HardFault_Handler ( void );
void SVC_Handler ( void );
void PendSV_Handler ( void );
void SysTick_Handler ( void );
/* Peripherals handlers */
void PM_Handler ( void );
void SYSCTRL_Handler ( void );
void WDT_Handler ( void );
void RTC_Handler ( void );
void EIC_Handler ( void );
void NVMCTRL_Handler ( void );
void DMAC_Handler ( void );
void USB_Handler ( void );
void EVSYS_Handler ( void );
void SERCOM0_Handler ( void );
void SERCOM1_Handler ( void );
void SERCOM2_Handler ( void );
void SERCOM3_Handler ( void );
void SERCOM4_Handler ( void );
void SERCOM5_Handler ( void );
void TCC0_Handler ( void );
void TCC1_Handler ( void );
void TCC2_Handler ( void );
void TC3_Handler ( void );
void TC4_Handler ( void );
void TC5_Handler ( void );
void TC6_Handler ( void );
void TC7_Handler ( void );
void ADC_Handler ( void );
void AC_Handler ( void );
void DAC_Handler ( void );
void PTC_Handler ( void );
void I2S_Handler ( void );
/* Cortex-M0+ core handlers */
#pragma weak NMI_Handler = Dummy_Handler
#pragma weak HardFault_Handler = Dummy_Handler
#pragma weak SVC_Handler = Dummy_Handler
#pragma weak PendSV_Handler = Dummy_Handler
#pragma weak SysTick_Handler = Dummy_Handler
/* Peripherals handlers */
#pragma weak PM_Handler = Dummy_Handler
#pragma weak SYSCTRL_Handler = Dummy_Handler
#pragma weak WDT_Handler = Dummy_Handler
#pragma weak RTC_Handler = Dummy_Handler
#pragma weak EIC_Handler = Dummy_Handler
#pragma weak NVMCTRL_Handler = Dummy_Handler
#pragma weak DMAC_Handler = Dummy_Handler
#pragma weak USB_Handler = Dummy_Handler
#pragma weak EVSYS_Handler = Dummy_Handler
#pragma weak SERCOM0_Handler = Dummy_Handler
#pragma weak SERCOM1_Handler = Dummy_Handler
#pragma weak SERCOM2_Handler = Dummy_Handler
#pragma weak SERCOM3_Handler = Dummy_Handler
#pragma weak SERCOM4_Handler = Dummy_Handler
#pragma weak SERCOM5_Handler = Dummy_Handler
#pragma weak TCC0_Handler = Dummy_Handler
#pragma weak TCC1_Handler = Dummy_Handler
#pragma weak TCC2_Handler = Dummy_Handler
#pragma weak TC3_Handler = Dummy_Handler
#pragma weak TC4_Handler = Dummy_Handler
#pragma weak TC5_Handler = Dummy_Handler
#pragma weak TC6_Handler = Dummy_Handler
#pragma weak TC7_Handler = Dummy_Handler
#pragma weak ADC_Handler = Dummy_Handler
#pragma weak AC_Handler = Dummy_Handler
#pragma weak DAC_Handler = Dummy_Handler
#pragma weak PTC_Handler = Dummy_Handler
#pragma weak I2S_Handler = Dummy_Handler
/* Exception Table */
#pragma language=extended
#pragma segment="CSTACK"
/* The name "__vector_table" has special meaning for C-SPY: */
/* it is where the SP start value is found, and the NVIC vector */
/* table register (VTOR) is initialized to this address if != 0 */
#pragma section = ".intvec"
#pragma location = ".intvec"
//! [startup_vector_table]
const DeviceVectors __vector_table[] = {
__sfe("CSTACK"),
(void*) __iar_program_start,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
(void*) USB_Handler, /* 7 Universal Serial Bus */
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
(void*) ADC_Handler, /* 23 Analog Digital Converter */
(void*) AC_Handler, /* 24 Analog Comparators */
(void*) DAC_Handler, /* 25 Digital Analog Converter */
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
(void*) I2S_Handler /* 27 Inter-IC Sound Interface */
};
//! [startup_vector_table]
/**------------------------------------------------------------------------------
* This is the code that gets called on processor reset. To initialize the
* device.
*------------------------------------------------------------------------------*/
int __low_level_init(void)
{
uint32_t *pSrc = __section_begin(".intvec");
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
return 1; /* if return 0, the data sections will not be initialized */
}
/**------------------------------------------------------------------------------
* This is the code that gets called on processor reset. To initialize the
* device.
*------------------------------------------------------------------------------*/
void Reset_Handler(void)
{
__iar_program_start();
}

13
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/device/cmsis.h
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@ -1,13 +0,0 @@
/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in samr21j18a specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "saml21.h"
#include "cmsis_nvic.h"
#endif

37
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/device/cmsis_nvic.h
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@ -1,37 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2011 ARM Limited. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 29) // CORE + MCU Peripherals
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM
#endif

161
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralNames.h
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@ -1,161 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include <compiler.h>
#include "cmsis.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
#define _SERCOM_SPI_NAME(n, unused) \
SPI##n,
#define _SERCOM_PAD_NAME(n, pad) \
SERCOM##n##_PAD##pad = ((n & 0xF) | ((pad & 0xF) << 4)),
#define _SERCOM_I2C_NAME(n, unused) \
I2C##n,
typedef enum {
UART_0 = (int)0x42000000UL, // Base address of SERCOM0
UART_1 = (int)0x42000400UL, // Base address of SERCOM1
UART_2 = (int)0x42000800UL, // Base address of SERCOM2
UART_3 = (int)0x42000C00UL, // Base address of SERCOM3
UART_4 = (int)0x42001000UL, // Base address of SERCOM4
UART_5 = (int)0x43000400UL // Base address of SERCOM5
} UARTName;
typedef enum {
ADC_0 = 0x0ul,
ADC_1 = 0x1ul,
ADC_2 = 0x2ul,
ADC_3 = 0x3ul,
ADC_4 = 0x4ul,
ADC_5 = 0x5ul,
ADC_6 = 0x6ul,
ADC_7 = 0x7ul,
ADC_8 = 0x8ul,
ADC_9 = 0x9ul,
ADC_10 = 0xAul,
ADC_11 = 0xBul,
ADC_12 = 0xCul,
ADC_13 = 0xDul,
ADC_14 = 0xEul,
ADC_15 = 0xFul,
ADC_16 = 0x10ul,
ADC_17 = 0x11ul,
ADC_18 = 0x12ul,
ADC_19 = 0x13ul
} ADCName;
typedef enum {
DAC_0 = 0x42003000UL
} DACName;
typedef enum { // for each channel
EXTINT_0 = 0,
EXTINT_1,
EXTINT_2,
EXTINT_3,
EXTINT_4,
EXTINT_5,
EXTINT_6,
EXTINT_7,
EXTINT_8,
EXTINT_9,
EXTINT_10,
EXTINT_11,
EXTINT_12,
EXTINT_13,
EXTINT_14,
EXTINT_15
} EXTINTName;
typedef enum {
MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_NAME, ~)
} SPIName;
typedef enum {
MREPEAT(SERCOM_INST_NUM, _SERCOM_I2C_NAME, ~)
} I2CName;
typedef enum {
/* Pad 0 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 0)
/* Pad 1 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 1)
/* Pad 2 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 2)
/* Pad 3 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 3)
} SercomPadName;
typedef enum {
PWM_0 = (0x42001400UL), /**< \brief (TCC0) APB Base Address */
PWM_1 = (0x42001800UL), /**< \brief (TCC1) APB Base Address */
PWM_2 = (0x42001C00UL), /**< \brief (TCC2) APB Base Address */
} PWMName;
struct pwm_pin_channel {
PinName pin;
PWMName pwm;
uint8_t channel_index;
};
struct dac_pin_channel {
PinName pin;
DACName dac;
uint8_t channel_index;
};
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_3
// Default peripherals
#define MBED_SPI0 PA06, PA04, PA07, PA05
#define MBED_UART0 PB08, PB09
#define MBED_UARTUSB USBTX, USBRX
#define MBED_I2C0 PA08, PA09
#define MBED_ANALOGIN0 PB05
#define MBED_ANALOGIN1 PA03
#define MBED_ANALOGIN2 PA06
#define MBED_ANALOGIN3 PA07
#define MBED_ANALOGIN4 PB02
#define MBED_ANALOGIN5 PB03
#define MBED_ANALOGIN7 PA08
#define MBED_ANALOGIN8 PA09
#define MBED_PWMOUT0 PB12
#define MBED_PWMOUT1 PB13
#ifdef __cplusplus
}
#endif
#endif

313
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralPins.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************ADC***************/
const PinMap PinMap_ADC[] = {
{PA02, ADC_0, 1},
{PA03, ADC_1, 1},
{PB08, ADC_2, 1},
{PB09, ADC_3, 1},
{PA04, ADC_4, 1},
{PA05, ADC_5, 1},
{PA06, ADC_6, 1},
{PA07, ADC_7, 1},
{PB00, ADC_8, 1},
{PB01, ADC_9, 1},
{PB02, ADC_10, 1},
{PB03, ADC_11, 1},
{PB04, ADC_12, 1},
{PB05, ADC_13, 1},
{PB06, ADC_14, 1},
{PB07, ADC_15, 1},
{PA08, ADC_16, 1},
{PA09, ADC_17, 1},
{PA10, ADC_18, 1},
{PA11, ADC_19, 1},
/* Not connected */
{NC , NC , NC}
};
/************DAC***************/
const PinMap PinMap_DAC[] = {
{PA02, DAC_0, 1},
{PA05, DAC_0, 1},
/* Not connected */
{NC , NC , NC}
};
/************SERCOM Pins***********/
const PinMap PinMap_SERCOM_PAD[] = {
{PA04, SERCOM0_PAD0, 3},
{PA08, SERCOM0_PAD0, 2},
{PA05, SERCOM0_PAD1, 3},
{PA09, SERCOM0_PAD1, 2},
{PA06, SERCOM0_PAD2, 3},
{PA10, SERCOM0_PAD2, 2},
{PA07, SERCOM0_PAD3, 3},
{PA11, SERCOM0_PAD3, 2},
{PA16, SERCOM1_PAD0, 2},
{PA00, SERCOM1_PAD0, 3},
{PA17, SERCOM1_PAD1, 2},
{PA01, SERCOM1_PAD1, 3},
{PA30, SERCOM1_PAD2, 3},
{PA18, SERCOM1_PAD2, 2},
{PA31, SERCOM1_PAD3, 3},
{PA19, SERCOM1_PAD3, 2},
{PA12, SERCOM2_PAD0, 2},
{PA13, SERCOM2_PAD1, 2},
{PA14, SERCOM2_PAD2, 2},
{PA15, SERCOM2_PAD3, 2},
{PA22, SERCOM3_PAD0, 2},
{PA27, SERCOM3_PAD0, 5},
{PA23, SERCOM3_PAD1, 2},
{PA20, SERCOM3_PAD2, 3},
{PA24, SERCOM3_PAD2, 2},
{PA21, SERCOM3_PAD3, 3},
{PA25, SERCOM3_PAD3, 2},
{PB08, SERCOM4_PAD0, 3},
{PB12, SERCOM4_PAD0, 2},
{PB09, SERCOM4_PAD1, 3},
{PB13, SERCOM4_PAD1, 2},
{PB31, SERCOM4_PAD1, 5},
{PB10, SERCOM4_PAD2, 3},
{PB14, SERCOM4_PAD2, 2},
{PB30, SERCOM4_PAD2, 5},
{PB11, SERCOM4_PAD3, 3},
{PB15, SERCOM4_PAD3, 2},
{PB02, SERCOM5_PAD0, 3},
{PB16, SERCOM5_PAD0, 2},
{PB03, SERCOM5_PAD1, 3},
{PB17, SERCOM5_PAD1, 2},
{PB00, SERCOM5_PAD2, 3},
{PB22, SERCOM5_PAD2, 3},
{PB01, SERCOM5_PAD3, 3},
{PB23, SERCOM5_PAD3, 3},
/* Not connected */
{NC , NC , NC}
};
/*******SERCOM Pins extended*******/
const PinMap PinMap_SERCOM_PADEx[] = {
{PA08, SERCOM2_PAD0, 3},
{PA09, SERCOM2_PAD1, 3},
{PA10, SERCOM2_PAD2, 3},
{PA11, SERCOM2_PAD3, 3},
{PA16, SERCOM3_PAD0, 3},
{PA17, SERCOM3_PAD1, 3},
{PA18, SERCOM3_PAD2, 3},
{PA19, SERCOM3_PAD3, 3},
{PA12, SERCOM4_PAD0, 3},
{PA13, SERCOM4_PAD1, 3},
{PA14, SERCOM4_PAD2, 3},
{PA15, SERCOM4_PAD3, 3},
{PA22, SERCOM5_PAD0, 3},
{PA23, SERCOM5_PAD1, 3},
{PA20, SERCOM5_PAD2, 2},
{PA24, SERCOM5_PAD2, 3},
{PA21, SERCOM5_PAD3, 2},
{PA25, SERCOM5_PAD3, 3},
{PB31, SERCOM5_PAD1, 3},
{PB30, SERCOM5_PAD0, 3},
/* Not connected */
{NC , NC , NC}
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
{PA04, PWM_0, 4},
{PA08, PWM_0, 4},
{PB30, PWM_0, 4},
{PA16, PWM_0, 5},
{PA05, PWM_0, 4},
{PA09, PWM_0, 4},
{PB31, PWM_0, 4},
{PA17, PWM_2, 4},
{PA10, PWM_0, 5},
{PA18, PWM_0, 5},
{PA11, PWM_0, 5},
{PA19, PWM_0, 5},
{PA22, PWM_0, 5},
{PB10, PWM_0, 5},
{PB16, PWM_0, 5},
{PA14, PWM_0, 5},
{PA15, PWM_0, 5},
{PA23, PWM_0, 5},
{PB11, PWM_0, 5},
{PB17, PWM_0, 5},
{PA12, PWM_0, 5},
{PA16, PWM_0, 5},
{PA20, PWM_0, 5},
{PB12, PWM_0, 5},
{PA13, PWM_0, 5},
{PA17, PWM_0, 5},
{PA21, PWM_0, 5},
{PB13, PWM_0, 5},
{PA06, PWM_1, 4},
{PA10, PWM_1, 4},
{PA30, PWM_1, 4},
{PA07, PWM_1, 4},
{PA11, PWM_1, 4},
{PA31, PWM_1, 4},
{PA08, PWM_1, 5},
{PA24, PWM_1, 5},
{PB30, PWM_1, 5},
{PA09, PWM_1, 5},
{PA25, PWM_1, 5},
{PB31, PWM_1, 5},
{PA12, PWM_2, 4},
{PA16, PWM_2, 4},
{PA00, PWM_2, 4},
{PA13, PWM_2, 4},
{PA17, PWM_2, 4},
{PA01, PWM_2, 4},
/* Not connected */
{NC , NC , NC}
};
/**********EXTINT*************/
const PinMap PinMap_EXTINT[] = {
{PA16, EXTINT_0, 0},
{PB00, EXTINT_0, 0},
{PB16, EXTINT_0, 0},
{PA00, EXTINT_0, 0},
{PA17, EXTINT_1, 0},
{PB01, EXTINT_1, 0},
{PB17, EXTINT_1, 0},
{PA01, EXTINT_1, 0},
{PA02, EXTINT_2, 0},
{PA18, EXTINT_2, 0},
{PB02, EXTINT_2, 0},
{PA03, EXTINT_3, 0},
{PA19, EXTINT_3, 0},
{PB03, EXTINT_3, 0},
{PA04, EXTINT_4, 0},
{PA20, EXTINT_4, 0},
{PB04, EXTINT_4, 0},
{PA05, EXTINT_5, 0},
{PA21, EXTINT_5, 0},
{PB05, EXTINT_5, 0},
{PA06, EXTINT_6, 0},
{PA22, EXTINT_6, 0},
{PB06, EXTINT_6, 0},
{PB22, EXTINT_6, 0},
{PA07, EXTINT_7, 0},
{PA23, EXTINT_7, 0},
{PB07, EXTINT_7, 0},
{PB23, EXTINT_7, 0},
{PB08, EXTINT_8, 0},
{PA09, EXTINT_9, 0},
{PB09, EXTINT_9, 0},
{PA10, EXTINT_10, 0},
{PA30, EXTINT_10, 0},
{PB10, EXTINT_10, 0},
{PA11, EXTINT_11, 0},
{PA31, EXTINT_11, 0},
{PB11, EXTINT_11, 0},
{PA12, EXTINT_12, 0},
{PA24, EXTINT_12, 0},
{PB12, EXTINT_12, 0},
{PA13, EXTINT_13, 0},
{PA25, EXTINT_13, 0},
{PB13, EXTINT_13, 0},
{PB14, EXTINT_14, 0},
{PB30, EXTINT_14, 0},
{PA14, EXTINT_14, 0},
{PA27, EXTINT_15, 0},
{PB15, EXTINT_15, 0},
{PB31, EXTINT_15, 0},
{PA15, EXTINT_15, 0},
/* Not connected */
{NC , NC , NC}
};
const struct pwm_pin_channel pwn_pins[] = {
{PA04, PWM_0, 0},
{PA08, PWM_0, 0},
{PB30, PWM_0, 0},
{PA16, PWM_0, 6},
{PA05, PWM_0, 1},
{PA09, PWM_0, 1},
{PB31, PWM_0, 1},
{PA17, PWM_0, 1},
{PA10, PWM_0, 2},
{PA18, PWM_0, 2},
{PA11, PWM_0, 3},
{PA19, PWM_0, 3},
{PA22, PWM_0, 4},
{PB10, PWM_0, 4},
{PB16, PWM_0, 4},
{PA14, PWM_0, 4},
{PA15, PWM_0, 5},
{PA23, PWM_0, 5},
{PB11, PWM_0, 5},
{PB17, PWM_0, 5},
{PA12, PWM_0, 6},
{PA16, PWM_0, 6},
{PA20, PWM_0, 6},
{PB12, PWM_0, 6},
{PA13, PWM_0, 7},
{PA17, PWM_2, 1},
{PA21, PWM_0, 7},
{PB13, PWM_0, 7},
{PA06, PWM_1, 0},
{PA10, PWM_1, 0},
{PA30, PWM_1, 0},
{PA07, PWM_1, 1},
{PA11, PWM_1, 1},
{PA31, PWM_1, 1},
{PA08, PWM_1, 2},
{PA24, PWM_1, 2},
{PB30, PWM_1, 2},
{PA09, PWM_1, 3},
{PA25, PWM_1, 3},
{PB31, PWM_1, 3},
{PA12, PWM_2, 0},
{PA16, PWM_2, 0},
{PA00, PWM_2, 0},
{PA13, PWM_2, 1},
{PA17, PWM_2, 1},
{PA01, PWM_2, 1},
/* Not connected */
{NC , NC , NC}
};

40
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralPins.h
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@ -1,40 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H
#include "pinmap.h"
#include "PeripheralNames.h"
/************ADC***************/
extern const PinMap PinMap_ADC[];
/************DAC***************/
extern const PinMap PinMap_DAC[];
/*********SERCOM*************/
extern const PinMap PinMap_SERCOM_PAD[];
extern const PinMap PinMap_SERCOM_PADEx[];
/************PWM***************/
extern const PinMap PinMap_PWM[];
/**********EXTINT*************/
extern const PinMap PinMap_EXTINT[];
#endif

107
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT,
PIN_INPUT_OUTPUT //pin state can be set and read back
} PinDirection;
typedef enum {
PA00 = 0,
PA01 = 1,
PA02 = 2,
PA03 = 3,
PA04 = 4,
PA05 = 5,
PA06 = 6,
PA07 = 7,
PA08 = 8,
PA09 = 9,
PA10 = 10,
PA11 = 11,
PA12 = 12,
PA13 = 13,
PA14 = 14,
PA15 = 15,
PA16 = 16,
PA17 = 17,
PA18 = 18,
PA19 = 19,
PA20 = 20,
PA21 = 21,
PA22 = 22,
PA23 = 23,
PA24 = 24,
PA25 = 25,
PA27 = 27,
PA30 = 30,
PA31 = 31,
PB00 = 32,
PB01 = 33,
PB02 = 34,
PB03 = 35,
PB04 = 36,
PB05 = 37,
PB06 = 38,
PB07 = 39,
PB08 = 40,
PB09 = 41,
PB10 = 42,
PB11 = 43,
PB12 = 44,
PB13 = 45,
PB14 = 46,
PB15 = 47,
PB16 = 48,
PB17 = 49,
PB22 = 54,
PB23 = 55,
PB30 = 62,
PB31 = 63,
USBTX = PA22,
USBRX = PA23,
LED1 = PB10,
LED2 = PB10,
LED3 = PB10,
LED4 = PB10,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

32
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/SAML21_XPLAINED_PRO/mbed_overrides.c
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@ -1,32 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "compiler.h"
#include "system.h"
uint8_t g_sys_init = 0;
//called before main - implement here if board needs it ortherwise, let
// the application override this if necessary
//TODO: To be implemented by adding system init and board init
void mbed_sdk_init()
{
if(g_sys_init == 0) {
g_sys_init = 1;
system_init();
}
}
/***************************************************************/

599
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/SAML21_XPLAINED_PRO/saml21_xplained_pro.h
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@ -1,599 +0,0 @@
/**
* \file
*
* \brief SAM L21 Xplained Pro board definition
*
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef SAML21_XPLAINED_PRO_H_INCLUDED
#define SAML21_XPLAINED_PRO_H_INCLUDED
#include <conf_board.h>
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \ingroup group_common_boards
* \defgroup saml21_xplained_pro_group SAM L21 Xplained Pro board
*
* @{
*/
void system_board_init(void);
/**
* \defgroup saml21_xplained_pro_features_group Features
*
* Symbols that describe features and capabilities of the board.
*
* @{
*/
/** Name string macro */
#define BOARD_NAME "SAML21_XPLAINED_PRO"
/** \name Resonator definitions
* @{ */
#define BOARD_FREQ_SLCK_XTAL (32768U)
#define BOARD_FREQ_SLCK_BYPASS (32768U)
#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */
#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */
#define BOARD_MCK CHIP_FREQ_CPU_MAX
#define BOARD_OSC_STARTUP_US 15625
/** @} */
/** \name LED0 definitions
* @{ */
#define LED0_PIN PIN_PB10
#define LED0_ACTIVE false
#define LED0_INACTIVE !LED0_ACTIVE
/** @} */
/** \name SW0 definitions
* @{ */
#define SW0_PIN PIN_PA02
#define SW0_ACTIVE false
#define SW0_INACTIVE !SW0_ACTIVE
#define SW0_EIC_PIN PIN_PA02A_EIC_EXTINT2
#define SW0_EIC_MUX MUX_PA02A_EIC_EXTINT2
#define SW0_EIC_PINMUX PINMUX_PA02A_EIC_EXTINT2
#define SW0_EIC_LINE 2
/** @} */
/**
* \name LED #0 definitions
*
* Wrapper macros for LED0, to ensure common naming across all Xplained Pro
* boards.
*
* @{ */
#define LED_0_NAME "LED0 (yellow)"
#define LED_0_PIN LED0_PIN
#define LED_0_ACTIVE LED0_ACTIVE
#define LED_0_INACTIVE LED0_INACTIVE
#define LED0_GPIO LED0_PIN
#define LED0 LED0_PIN
#define LED_0_PWM4CTRL_MODULE TCC0
#define LED_0_PWM4CTRL_CHANNEL 0
#define LED_0_PWM4CTRL_OUTPUT 0
#define LED_0_PWM4CTRL_PIN PIN_PB10F_TCC0_WO4
#define LED_0_PWM4CTRL_MUX MUX_PB10F_TCC0_WO4
#define LED_0_PWM4CTRL_PINMUX PINMUX_PB10F_TCC0_WO4
/** @} */
/** Number of on-board LEDs */
#define LED_COUNT 1
/**
* \name Button #0 definitions
*
* Wrapper macros for SW0, to ensure common naming across all Xplained Pro
* boards.
*
* @{ */
#define BUTTON_0_NAME "SW0"
#define BUTTON_0_PIN SW0_PIN
#define BUTTON_0_ACTIVE SW0_ACTIVE
#define BUTTON_0_INACTIVE SW0_INACTIVE
#define BUTTON_0_EIC_PIN SW0_EIC_PIN
#define BUTTON_0_EIC_MUX SW0_EIC_MUX
#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX
#define BUTTON_0_EIC_LINE SW0_EIC_LINE
/** @} */
/** Number of on-board buttons */
#define BUTTON_COUNT 1
/** \name Extension header #1 pin definitions
* @{
*/
#define EXT1_PIN_3 PIN_PB05
#define EXT1_PIN_4 PIN_PA03
#define EXT1_PIN_5 PIN_PB06
#define EXT1_PIN_6 PIN_PB07
#define EXT1_PIN_7 PIN_PA12
#define EXT1_PIN_8 PIN_PA13
#define EXT1_PIN_9 PIN_PB04
#define EXT1_PIN_10 PIN_PA02
#define EXT1_PIN_11 PIN_PA08
#define EXT1_PIN_12 PIN_PA09
#define EXT1_PIN_13 PIN_PB09
#define EXT1_PIN_14 PIN_PB08
#define EXT1_PIN_15 PIN_PA05
#define EXT1_PIN_16 PIN_PA06
#define EXT1_PIN_17 PIN_PA04
#define EXT1_PIN_18 PIN_PA07
/** @} */
/** \name Extension header #1 pin definitions by function
* @{
*/
#define EXT1_PIN_ADC_0 EXT1_PIN_3
#define EXT1_PIN_ADC_1 EXT1_PIN_4
#define EXT1_PIN_GPIO_0 EXT1_PIN_5
#define EXT1_PIN_GPIO_1 EXT1_PIN_6
#define EXT1_PIN_PWM_0 EXT1_PIN_7
#define EXT1_PIN_PWM_1 EXT1_PIN_8
#define EXT1_PIN_IRQ EXT1_PIN_9
#define EXT1_PIN_I2C_SDA EXT1_PIN_11
#define EXT1_PIN_I2C_SCL EXT1_PIN_12
#define EXT1_PIN_UART_RX EXT1_PIN_13
#define EXT1_PIN_UART_TX EXT1_PIN_14
#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10
#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15
#define EXT1_PIN_SPI_MOSI EXT1_PIN_16
#define EXT1_PIN_SPI_MISO EXT1_PIN_17
#define EXT1_PIN_SPI_SCK EXT1_PIN_18
/** @} */
/** \name Extension header #1 ADC definitions
* @{
*/
#define EXT1_ADC_MODULE ADC
#define EXT1_ADC_13_CHANNEL 13
#define EXT1_ADC_13_PIN PIN_PB05B_ADC_AIN13
#define EXT1_ADC_13_MUX MUX_PB05B_ADC_AIN13
#define EXT1_ADC_13_PINMUX PINMUX_PB05B_ADC_AIN13
#define EXT1_ADC_1_CHANNEL 1
#define EXT1_ADC_1_PIN PIN_PA03B_ADC_AIN1
#define EXT1_ADC_1_MUX MUX_PA03B_ADC_AIN1
#define EXT1_ADC_1_PINMUX PINMUX_PA03B_ADC_AIN1
/** @} */
/** \name Extension header #1 PWM definitions
* @{
*/
#define EXT1_PWM_MODULE TC2
#define EXT1_PWM_0_CHANNEL 0
#define EXT1_PWM_0_PIN PIN_PB02E_TC2_WO0
#define EXT1_PWM_0_MUX MUX_PB02E_TC2_WO0
#define EXT1_PWM_0_PINMUX PINMUX_PB02E_TC2_WO0
#define EXT1_PWM_1_CHANNEL 1
#define EXT1_PWM_1_PIN PIN_PB03E_TC2_WO1
#define EXT1_PWM_1_MUX MUX_PB03E_TC2_WO1
#define EXT1_PWM_1_PINMUX PINMUX_PB03E_TC2_WO1
/** @} */
/** \name Extension header #1 IRQ/External interrupt definitions
* @{
*/
#define EXT1_IRQ_MODULE EIC
#define EXT1_IRQ_INPUT 4
#define EXT1_IRQ_PIN PIN_PB04A_EIC_EXTINT4
#define EXT1_IRQ_MUX MUX_PB04A_EIC_EXTINT4
#define EXT1_IRQ_PINMUX PINMUX_PB04A_EIC_EXTINT4
/** @} */
/** \name Extension header #1 I2C definitions
* @{
*/
#define EXT1_I2C_MODULE SERCOM2
#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EXT1_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EXT1_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Extension header #1 UART definitions
* @{
*/
#define EXT1_UART_MODULE SERCOM4
#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_PB08D_SERCOM4_PAD0
#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_PB09D_SERCOM4_PAD1
#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EXT1_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
#define EXT1_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
/** @} */
/** \name Extension header #1 SPI definitions
* @{
*/
#define EXT1_SPI_MODULE SERCOM0
#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0
#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1
#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA06D_SERCOM0_PAD2
#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA07D_SERCOM0_PAD3
#define EXT1_SPI_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX
#define EXT1_SPI_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX
/** @} */
/** \name Extension header #2 pin definitions
* @{
*/
#define EXT2_PIN_3 PIN_PA10
#define EXT2_PIN_4 PIN_PA11
#define EXT2_PIN_5 PIN_PA20
#define EXT2_PIN_6 PIN_PA21
#define EXT2_PIN_7 PIN_PB12
#define EXT2_PIN_8 PIN_PB13
#define EXT2_PIN_9 PIN_PB14
#define EXT2_PIN_10 PIN_PB15
#define EXT2_PIN_11 PIN_PA08
#define EXT2_PIN_12 PIN_PA09
#define EXT2_PIN_13 PIN_PA19
#define EXT2_PIN_14 PIN_PA18
#define EXT2_PIN_15 PIN_PA17
#define EXT2_PIN_16 PIN_PB22
#define EXT2_PIN_17 PIN_PB16
#define EXT2_PIN_18 PIN_PB23
/** @} */
/** \name Extension header #2 pin definitions by function
* @{
*/
#define EXT2_PIN_ADC_0 EXT2_PIN_3
#define EXT2_PIN_ADC_1 EXT2_PIN_4
#define EXT2_PIN_GPIO_0 EXT2_PIN_5
#define EXT2_PIN_GPIO_1 EXT2_PIN_6
#define EXT2_PIN_PWM_0 EXT2_PIN_7
#define EXT2_PIN_PWM_1 EXT2_PIN_8
#define EXT2_PIN_IRQ EXT2_PIN_9
#define EXT2_PIN_I2C_SDA EXT2_PIN_11
#define EXT2_PIN_I2C_SCL EXT2_PIN_12
#define EXT2_PIN_UART_RX EXT2_PIN_13
#define EXT2_PIN_UART_TX EXT2_PIN_14
#define EXT2_PIN_SPI_SS_1 EXT2_PIN_10
#define EXT2_PIN_SPI_SS_0 EXT2_PIN_15
#define EXT2_PIN_SPI_MOSI EXT2_PIN_16
#define EXT2_PIN_SPI_MISO EXT2_PIN_17
#define EXT2_PIN_SPI_SCK EXT2_PIN_18
/** @} */
/** \name Extension header #2 ADC definitions
* @{
*/
#define EXT2_ADC_MODULE ADC
#define EXT2_ADC_0_CHANNEL 18
#define EXT2_ADC_0_PIN PIN_PA10B_ADC_AIN18
#define EXT2_ADC_0_MUX MUX_PA10B_ADC_AIN18
#define EXT2_ADC_0_PINMUX PINMUX_PA10B_ADC_AIN18
#define EXT2_ADC_1_CHANNEL 19
#define EXT2_ADC_1_PIN PIN_PA11B_ADC_AIN19
#define EXT2_ADC_1_MUX MUX_PA11B_ADC_AIN19
#define EXT2_ADC_1_PINMUX PINMUX_PA11B_ADC_AIN19
/** @} */
/** \name Extension header #2 PWM definitions
* @{
*/
#define EXT2_PWM_MODULE TC0
#define EXT2_PWM_0_CHANNEL 0
#define EXT2_PWM_0_PIN PIN_PB12E_TC0_WO0
#define EXT2_PWM_0_MUX MUX_PB12E_TC0_WO0
#define EXT2_PWM_0_PINMUX PINMUX_PB12E_TC0_WO0
#define EXT2_PWM_1_CHANNEL 1
#define EXT2_PWM_1_PIN PIN_PB13E_TC0_WO1
#define EXT2_PWM_1_MUX MUX_PB13E_TC0_WO1
#define EXT2_PWM_1_PINMUX PINMUX_PB13E_TC0_WO1
/** @} */
/** \name Extension header #2 IRQ/External interrupt definitions
* @{
*/
#define EXT2_IRQ_MODULE EIC
#define EXT2_IRQ_INPUT 14
#define EXT2_IRQ_PIN PIN_PB14A_EIC_EXTINT14
#define EXT2_IRQ_MUX MUX_PB14A_EIC_EXTINT14
#define EXT2_IRQ_PINMUX PINMUX_PB14A_EIC_EXTINT14
/** @} */
/** \name Extension header #2 I2C definitions
* @{
*/
#define EXT2_I2C_MODULE SERCOM2
#define EXT2_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EXT2_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EXT2_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EXT2_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Extension header #2 UART definitions
* @{
*/
#define EXT2_UART_MODULE SERCOM1
#define EXT2_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3
#define EXT2_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED
#define EXT2_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define EXT2_UART_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2
#define EXT2_UART_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3
#define EXT2_UART_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX
#define EXT2_UART_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX
/** @} */
/** \name Extension header #2 SPI definitions
* @{
*/
#define EXT2_SPI_MODULE SERCOM5
#define EXT2_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT2_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
#define EXT2_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define EXT2_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EXT2_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EXT2_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EXT2_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Extension header #3 pin definitions
* @{
*/
#define EXT3_PIN_3 PIN_PB00
#define EXT3_PIN_4 PIN_PB01
#define EXT3_PIN_5 PIN_PB30
#define EXT3_PIN_6 PIN_PA15
#define EXT3_PIN_7 PIN_PB10
#define EXT3_PIN_8 PIN_PB11
#define EXT3_PIN_9 PIN_PA16
#define EXT3_PIN_10 PIN_PA27
#define EXT3_PIN_11 PIN_PA08
#define EXT3_PIN_12 PIN_PA09
#define EXT3_PIN_13 PIN_PA19
#define EXT3_PIN_14 PIN_PA18
#define EXT3_PIN_15 PIN_PB17
#define EXT3_PIN_16 PIN_PB22
#define EXT3_PIN_17 PIN_PB16
#define EXT3_PIN_18 PIN_PB23
/** @} */
/** \name Extension header #3 pin definitions by function
* @{
*/
#define EXT3_PIN_ADC_0 EXT3_PIN_3
#define EXT3_PIN_ADC_1 EXT3_PIN_4
#define EXT3_PIN_GPIO_0 EXT3_PIN_5
#define EXT3_PIN_GPIO_1 EXT3_PIN_6
#define EXT3_PIN_PWM_0 EXT3_PIN_7
#define EXT3_PIN_PWM_1 EXT3_PIN_8
#define EXT3_PIN_IRQ EXT3_PIN_9
#define EXT3_PIN_I2C_SDA EXT3_PIN_11
#define EXT3_PIN_I2C_SCL EXT3_PIN_12
#define EXT3_PIN_UART_RX EXT3_PIN_13
#define EXT3_PIN_UART_TX EXT3_PIN_14
#define EXT3_PIN_SPI_SS_1 EXT3_PIN_10
#define EXT3_PIN_SPI_SS_0 EXT3_PIN_15
#define EXT3_PIN_SPI_MOSI EXT3_PIN_16
#define EXT3_PIN_SPI_MISO EXT3_PIN_17
#define EXT3_PIN_SPI_SCK EXT3_PIN_18
/** @} */
/** \name Extension header #3 ADC definitions
* @{
*/
#define EXT3_ADC_MODULE ADC
#define EXT3_ADC_0_CHANNEL 8
#define EXT3_ADC_0_PIN PIN_PB00B_ADC_AIN8
#define EXT3_ADC_0_MUX MUX_PB00B_ADC_AIN8
#define EXT3_ADC_0_PINMUX PINMUX_PB00B_ADC_AIN8
#define EXT3_ADC_1_CHANNEL 9
#define EXT3_ADC_1_PIN PIN_PB01B_ADC_AIN9
#define EXT3_ADC_1_MUX MUX_PB01B_ADC_AIN9
#define EXT3_ADC_1_PINMUX PINMUX_PB01B_ADC_AIN9
/** @} */
/** \name Extension header #3 IRQ/External interrupt definitions
* @{
*/
#define EXT3_IRQ_MODULE EIC
#define EXT3_IRQ_INPUT 0
#define EXT3_IRQ_PIN PIN_PA16A_EIC_EXTINT0
#define EXT3_IRQ_MUX MUX_PA16A_EIC_EXTINT0
#define EXT3_IRQ_PINMUX PINMUX_PA16A_EIC_EXTINT0
/** @} */
/** \name Extension header #3 I2C definitions
* @{
*/
#define EXT3_I2C_MODULE SERCOM2
#define EXT3_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EXT3_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EXT3_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EXT3_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Extension header #3 UART definitions
* @{
*/
#define EXT3_UART_MODULE SERCOM1
#define EXT3_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3
#define EXT3_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED
#define EXT3_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define EXT3_UART_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2
#define EXT3_UART_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3
#define EXT3_UART_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX
#define EXT3_UART_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX
/** @} */
/** \name Extension header #3 SPI definitions
* @{
*/
#define EXT3_SPI_MODULE SERCOM5
#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB17C_SERCOM5_PAD1
#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EXT3_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EXT3_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Embedded debugger I2C interface definitions
* @{
*/
#define EDBG_I2C_MODULE SERCOM2
#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EDBG_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EDBG_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Embedded debugger SPI interface definitions
* @{
*/
#define EDBG_SPI_MODULE SERCOM5
#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB31D_SERCOM5_PAD1
#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EDBG_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EDBG_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Embedded debugger CDC Gateway USART interface definitions
* @{
*/
#define EDBG_CDC_MODULE SERCOM3
#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_PA22C_SERCOM3_PAD0
#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_PA23C_SERCOM3_PAD1
#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_DMAC_ID_TX SERCOM3_DMAC_ID_TX
#define EDBG_CDC_SERCOM_DMAC_ID_RX SERCOM3_DMAC_ID_RX
/** @} */
/** \name USB definitions
* @{
*/
#define USB_ID
#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP
#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP
#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP
#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM
#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM
#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM
#define USB_VBUS_PIN PIN_PA14
#define USB_VBUS_EIC_LINE 14
#define USB_VBUS_EIC_MUX MUX_PA14A_EIC_EXTINT14
#define USB_VBUS_EIC_PINMUX PINMUX_PA14A_EIC_EXTINT14
#define USB_ID_PIN PIN_PB02
#define USB_ID_EIC_LINE 2
#define USB_ID_EIC_MUX MUX_PB02A_EIC_EXTINT2
#define USB_ID_EIC_PINMUX PINMUX_PB02A_EIC_EXTINT2
/** @} */
/** \name CCL interface definitions
* @{
*/
#define CCL_LUT0_IN0_MUX MUX_PA04I_CCL_IN0
#define CCL_LUT0_IN1_MUX MUX_PA05I_CCL_IN1
#define CCL_LUT0_IN2_MUX MUX_PA06I_CCL_IN2
#define CCL_LUT0_OUT_MUX MUX_PA07I_CCL_OUT0
#define CCL_LUT0_IN0_PIN PIN_PA04I_CCL_IN0
#define CCL_LUT0_IN1_PIN PIN_PA05I_CCL_IN1
#define CCL_LUT0_IN2_PIN PIN_PA06I_CCL_IN2
#define CCL_LUT0_OUT_PIN PIN_PA07I_CCL_OUT0
#define CCL_LUT1_IN0_MUX MUX_PA08I_CCL_IN3
#define CCL_LUT1_IN1_MUX MUX_PA09I_CCL_IN4
#define CCL_LUT1_IN2_MUX MUX_PA10I_CCL_IN5
#define CCL_LUT1_OUT_MUX MUX_PA11I_CCL_OUT1
#define CCL_LUT1_IN0_PIN PIN_PA08I_CCL_IN3
#define CCL_LUT1_IN1_PIN PIN_PA09I_CCL_IN4
#define CCL_LUT1_IN2_PIN PIN_PA10I_CCL_IN5
#define CCL_LUT1_OUT_PIN PIN_PA11I_CCL_OUT1
/** @} */
/**
* \brief Turns off the specified LEDs.
*
* \param led_gpio LED to turn off (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true)
/**
* \brief Turns on the specified LEDs.
*
* \param led_gpio LED to turn on (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false)
/**
* \brief Toggles the specified LEDs.
*
* \param led_gpio LED to toggle (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* SAML21_XPLAINED_PRO_H_INCLUDED */

125
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/analogout_api.c
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@ -1,125 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogout_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "PeripheralPins.h"
#include "dac.h"
#if DEVICE_ANALOGOUT
extern uint8_t g_sys_init;
#define MAX_VAL_12BIT 0x0FFF /*12 Bit DAC for SAML21*/
void analogout_init(dac_t *obj, PinName pin)
{
MBED_ASSERT(obj);
if (g_sys_init == 0) {
system_init();
g_sys_init = 1;
}
struct dac_config config_dac;
struct dac_chan_config config_dac_chan;
uint32_t dacperipheral;
uint32_t ch_index;
dacperipheral = pinmap_find_peripheral(pin, PinMap_DAC);
MBED_ASSERT(dacperipheral != NC);
obj->pin = pin;
obj->dac = dacperipheral;
if (pin == PA02) {
ch_index = 0;
} else if (pin == PA05) {
ch_index = 1;
} else { /*Only 2 pins for DAC*/
return 0;
}
obj->channel = ch_index;
dac_get_config_defaults(&config_dac);
dac_init(&(obj->dac_instance), (Dac *)dacperipheral, &config_dac);
dac_chan_get_config_defaults(&config_dac_chan);
dac_chan_set_config(&(obj->dac_instance), ch_index, &config_dac_chan);
dac_chan_enable(&(obj->dac_instance), ch_index);
dac_enable(&(obj->dac_instance));
}
void analogout_free(dac_t *obj)
{
MBED_ASSERT(obj);
struct system_pinmux_config pin_conf;
dac_disable(&(obj->dac_instance));
pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_UP;
pin_conf.powersave = false;
pin_conf.mux_position = SYSTEM_PINMUX_GPIO;
system_pinmux_pin_set_config(obj->pin, &pin_conf);
}
void analogout_write(dac_t *obj, float value)
{
MBED_ASSERT(obj);
uint16_t count_val = 0;
if (value < 0.0f) {
count_val = 0;
} else if (value > 1.0f) {
count_val = MAX_VAL_12BIT;
} else {
count_val = (uint16_t)(value * (float)MAX_VAL_12BIT);
}
dac_chan_write(&(obj->dac_instance), obj->channel, count_val);
}
void analogout_write_u16(dac_t *obj, uint16_t value)
{
MBED_ASSERT(obj);
uint16_t count_val;
count_val = (uint16_t)((value * (float)MAX_VAL_12BIT) / 0xFFFF); /*Normalization to the value 0xFFFF*/
dac_chan_write(&(obj->dac_instance), obj->channel, count_val);
}
static uint32_t data_reg_read(dac_t *obj)
{
Dac *const dac_module = (Dac *)obj->dac;
return (uint32_t)dac_module->DATA[obj->channel].reg;
}
float analogout_read(dac_t *obj)
{
MBED_ASSERT(obj);
uint32_t data_val = data_reg_read(obj);
return data_val/(float)MAX_VAL_12BIT;
}
uint16_t analogout_read_u16(dac_t *obj)
{
MBED_ASSERT(obj);
uint32_t data_val = data_reg_read(obj);
return (uint16_t)((data_val / (float)MAX_VAL_12BIT) * 0xFFFF); /*Normalization to the value 0xFFFF*/
}
const PinMap *analogout_pinmap()
{
return PinMap_DAC;
}
#endif // DEVICE_ANALOGOUT

38
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device.h
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@ -1,38 +0,0 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

50
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/SAML21J18A.sct
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#! armcc -E
;SAMD21J18A
; 256KB FLASH (0x40000) @ 0x000000000
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
; SAMD21J18A: 256KB FLASH (0x40000)
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x40000
#endif
; 32KB RAM (0x8000) @ 0x20000000
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x8000
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment
#define VECTOR_SIZE 0xB8
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

194
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAML21.S
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;/**************************************************************************//**
; * @file startup_SAML21.s
; * @brief CMSIS Cortex-M4 Core Device Startup File for
; * Atmel SAML21 Device Series
; * @version V1.00
; * @date 10. February 2015
; *
; * @note
; * Copyright (C) 2015 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
;Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ;Reset Handler
DCD NMI_Handler ;NMI Handler
DCD HardFault_Handler ;Hard Fault Handler
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD SVC_Handler ;SVCall Handler
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD PendSV_Handler ;PendSV Handler
DCD SysTick_Handler ;SysTick Handler
;External Interrupts
DCD SYSTEM_Handler ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator
DCD WDT_Handler ;1 Watchdog Timer
DCD RTC_Handler ;2 Real-Time Counter
DCD EIC_Handler ;3 External Interrupt Controller
DCD NVMCTRL_Handler ;4 Non-Volatile Memory Controller
DCD DMAC_Handler ;5 Direct Memory Access Controller
DCD USB_Handler ;6 Universal Serial Bus
DCD EVSYS_Handler ;7 Event System Interface
DCD SERCOM0_Handler ;8 Serial Communication Interface 0
DCD SERCOM1_Handler ;9 Serial Communication Interface 1
DCD SERCOM2_Handler ;10 Serial Communication Interface 2
DCD SERCOM3_Handler ;11 Serial Communication Interface 3
DCD SERCOM4_Handler ;12 Serial Communication Interface 4
DCD SERCOM5_Handler ;13 Serial Communication Interface 5
DCD TCC0_Handler ;14 Timer Counter Control 0
DCD TCC1_Handler ;15 Timer Counter Control 1
DCD TCC2_Handler ;16 Timer Counter Control 2
DCD TC0_Handler ;17 Basic Timer Counter 0
DCD TC1_Handler ;18 Basic Timer Counter 1
DCD TC2_Handler ;19 Basic Timer Counter 2
DCD TC3_Handler ;20 Basic Timer Counter 3
DCD TC4_Handler ;21 Basic Timer Counter 4
DCD ADC_Handler ;22 Analog Digital Converter
DCD AC_Handler ;23 Analog Comparators
DCD DAC_Handler ;24 Digital-to-Analog Converter
DCD PTC_Handler ;25 Peripheral Touch Controller
DCD AES_Handler ;26 Advanced Encryption Standard
DCD TRNG_Handler ;27 True Random Generator
DCD PICOP_Handler ;28 PicoProcessor
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
;Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
;Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT SYSTEM_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT EIC_Handler [WEAK]
EXPORT NVMCTRL_Handler [WEAK]
EXPORT DMAC_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT EVSYS_Handler [WEAK]
EXPORT SERCOM0_Handler [WEAK]
EXPORT SERCOM1_Handler [WEAK]
EXPORT SERCOM2_Handler [WEAK]
EXPORT SERCOM3_Handler [WEAK]
EXPORT SERCOM4_Handler [WEAK]
EXPORT SERCOM5_Handler [WEAK]
EXPORT TCC0_Handler [WEAK]
EXPORT TCC1_Handler [WEAK]
EXPORT TCC2_Handler [WEAK]
EXPORT TC0_Handler [WEAK]
EXPORT TC1_Handler [WEAK]
EXPORT TC2_Handler [WEAK]
EXPORT TC3_Handler [WEAK]
EXPORT TC4_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT AC_Handler [WEAK]
EXPORT DAC_Handler [WEAK]
EXPORT PTC_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT TRNG_Handler [WEAK]
EXPORT PICOP_Handler [WEAK]
SYSTEM_Handler
WDT_Handler
RTC_Handler
EIC_Handler
NVMCTRL_Handler
DMAC_Handler
USB_Handler
EVSYS_Handler
SERCOM0_Handler
SERCOM1_Handler
SERCOM2_Handler
SERCOM3_Handler
SERCOM4_Handler
SERCOM5_Handler
TCC0_Handler
TCC1_Handler
TCC2_Handler
TC0_Handler
TC1_Handler
TC2_Handler
TC3_Handler
TC4_Handler
ADC_Handler
AC_Handler
DAC_Handler
PTC_Handler
AES_Handler
TRNG_Handler
PICOP_Handler
B .
ENDP
ALIGN
END

27
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/SAML21J18A.sct
View File

@ -1,27 +0,0 @@
#! armcc -E
;SAML21J18A
;256KB FLASH (0x40000) @ 0x000000000
;32KB RAM (0x8000) @ 0x20000000
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define Stack_Size MBED_BOOT_STACK_SIZE
;SAML21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
LR_IROM1 0x00000000 0x40000 { ; load region size_region
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment
RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8-Stack_Size) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK 0x20000000+0x8000 EMPTY -Stack_Size { ; Stack region growing down
}
}

194
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/startup_SAML21.S
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@ -1,194 +0,0 @@
;/**************************************************************************//**
; * @file startup_SAML21.s
; * @brief CMSIS Cortex-M4 Core Device Startup File for
; * Atmel SAML21 Device Series
; * @version V1.00
; * @date 10. February 2015
; *
; * @note
; * Copyright (C) 2015 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
;Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ;Reset Handler
DCD NMI_Handler ;NMI Handler
DCD HardFault_Handler ;Hard Fault Handler
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD SVC_Handler ;SVCall Handler
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD PendSV_Handler ;PendSV Handler
DCD SysTick_Handler ;SysTick Handler
;External Interrupts
DCD SYSTEM_Handler ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator
DCD WDT_Handler ;1 Watchdog Timer
DCD RTC_Handler ;2 Real-Time Counter
DCD EIC_Handler ;3 External Interrupt Controller
DCD NVMCTRL_Handler ;4 Non-Volatile Memory Controller
DCD DMAC_Handler ;5 Direct Memory Access Controller
DCD USB_Handler ;6 Universal Serial Bus
DCD EVSYS_Handler ;7 Event System Interface
DCD SERCOM0_Handler ;8 Serial Communication Interface 0
DCD SERCOM1_Handler ;9 Serial Communication Interface 1
DCD SERCOM2_Handler ;10 Serial Communication Interface 2
DCD SERCOM3_Handler ;11 Serial Communication Interface 3
DCD SERCOM4_Handler ;12 Serial Communication Interface 4
DCD SERCOM5_Handler ;13 Serial Communication Interface 5
DCD TCC0_Handler ;14 Timer Counter Control 0
DCD TCC1_Handler ;15 Timer Counter Control 1
DCD TCC2_Handler ;16 Timer Counter Control 2
DCD TC0_Handler ;17 Basic Timer Counter 0
DCD TC1_Handler ;18 Basic Timer Counter 1
DCD TC2_Handler ;19 Basic Timer Counter 2
DCD TC3_Handler ;20 Basic Timer Counter 3
DCD TC4_Handler ;21 Basic Timer Counter 4
DCD ADC_Handler ;22 Analog Digital Converter
DCD AC_Handler ;23 Analog Comparators
DCD DAC_Handler ;24 Digital-to-Analog Converter
DCD PTC_Handler ;25 Peripheral Touch Controller
DCD AES_Handler ;26 Advanced Encryption Standard
DCD TRNG_Handler ;27 True Random Generator
DCD PICOP_Handler ;28 PicoProcessor
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
;Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
;Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT SYSTEM_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT EIC_Handler [WEAK]
EXPORT NVMCTRL_Handler [WEAK]
EXPORT DMAC_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT EVSYS_Handler [WEAK]
EXPORT SERCOM0_Handler [WEAK]
EXPORT SERCOM1_Handler [WEAK]
EXPORT SERCOM2_Handler [WEAK]
EXPORT SERCOM3_Handler [WEAK]
EXPORT SERCOM4_Handler [WEAK]
EXPORT SERCOM5_Handler [WEAK]
EXPORT TCC0_Handler [WEAK]
EXPORT TCC1_Handler [WEAK]
EXPORT TCC2_Handler [WEAK]
EXPORT TC0_Handler [WEAK]
EXPORT TC1_Handler [WEAK]
EXPORT TC2_Handler [WEAK]
EXPORT TC3_Handler [WEAK]
EXPORT TC4_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT AC_Handler [WEAK]
EXPORT DAC_Handler [WEAK]
EXPORT PTC_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT TRNG_Handler [WEAK]
EXPORT PICOP_Handler [WEAK]
SYSTEM_Handler
WDT_Handler
RTC_Handler
EIC_Handler
NVMCTRL_Handler
DMAC_Handler
USB_Handler
EVSYS_Handler
SERCOM0_Handler
SERCOM1_Handler
SERCOM2_Handler
SERCOM3_Handler
SERCOM4_Handler
SERCOM5_Handler
TCC0_Handler
TCC1_Handler
TCC2_Handler
TC0_Handler
TC1_Handler
TC2_Handler
TC3_Handler
TC4_Handler
ADC_Handler
AC_Handler
DAC_Handler
PTC_Handler
AES_Handler
TRNG_Handler
PICOP_Handler
B .
ENDP
ALIGN
END

127
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_GCC_ARM/saml21j18a.ld
View File

@ -1,127 +0,0 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Memory Spaces Definitions */
MEMORY {
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
ram (rwx) : ORIGIN = 0x20000000 + 0xB8, LENGTH = 0x00008000 - 0xB8
}
/* Section Definitions */
SECTIONS {
.text :
{
. = ALIGN(8);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(8);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(8);
KEEP(*(.fini))
. = ALIGN(8);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(8);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(8);
_etext = .;
.relocate :
AT (_etext)
{
. = ALIGN(8);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(8);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(8);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(8);
_ebss = . ;
_ezero = .;
} > ram
.heap (NOLOAD) :
{
. = ALIGN(8);
__end__ = . ;
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
__HeapLimit = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
. = ALIGN(8);
}

281
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_GCC_ARM/startup_saml21.c
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@ -1,281 +0,0 @@
/**
* \file
*
* \brief gcc starttup file for SAML21
*
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include "saml21.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M0+ core handlers */
void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void SYSTEM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* MCLK, OSCCTRL, OSC32KCTRL, PAC, PM, SUPC, TAL */
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef ID_USB
void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef ID_SERCOM4
void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_SERCOM5
void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef ID_TC2
void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_TC3
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef ID_ADC
void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_AC
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_DAC
void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_PTC
void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_AES
void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_TRNG
void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_PICOP
void PICOP_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
/* Exception Table */
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
(void*) (&_estack),
(void*) Reset_Handler,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) SYSTEM_Handler, /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
(void*) WDT_Handler, /* 1 Watchdog Timer */
(void*) RTC_Handler, /* 2 Real-Time Counter */
(void*) EIC_Handler, /* 3 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 4 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 5 Direct Memory Access Controller */
#ifdef ID_USB
(void*) USB_Handler, /* 6 Universal Serial Bus */
#else
(void*) (0UL), /* Reserved */
#endif
(void*) EVSYS_Handler, /* 7 Event System Interface */
(void*) SERCOM0_Handler, /* 8 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 9 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 10 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 11 Serial Communication Interface 3 */
#ifdef ID_SERCOM4
(void*) SERCOM4_Handler, /* 12 Serial Communication Interface 4 */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef ID_SERCOM5
(void*) SERCOM5_Handler, /* 13 Serial Communication Interface 5 */
#else
(void*) (0UL), /* Reserved */
#endif
(void*) TCC0_Handler, /* 14 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 15 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 16 Timer Counter Control 2 */
(void*) TC0_Handler, /* 17 Basic Timer Counter 0 */
(void*) TC1_Handler, /* 18 Basic Timer Counter 1 */
#ifdef ID_TC2
(void*) TC2_Handler, /* 19 Basic Timer Counter 2 */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef ID_TC3
(void*) TC3_Handler, /* 20 Basic Timer Counter 3 */
#else
(void*) (0UL), /* Reserved */
#endif
(void*) TC4_Handler, /* 21 Basic Timer Counter 4 */
#ifdef ID_ADC
(void*) ADC_Handler, /* 22 Analog Digital Converter */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef ID_AC
(void*) AC_Handler, /* 23 Analog Comparators */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef ID_DAC
(void*) DAC_Handler, /* 24 Digital-to-Analog Converter */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef ID_PTC
(void*) PTC_Handler, /* 25 Peripheral Touch Controller */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef ID_AES
(void*) AES_Handler, /* 26 Advanced Encryption Standard */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef ID_TRNG
(void*) TRNG_Handler, /* 27 True Random Generator */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef ID_PICOP
(void*) PICOP_Handler /* 28 PicoProcessor */
#else
(void*) (0UL) /* Reserved */
#endif
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
NVMCTRL->CTRLB.bit.MANW = 1;
/* Branch to main function */
main();
/* Infinite loop */
while (1);
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

261
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_IAR/startup_saml21.c
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@ -1,261 +0,0 @@
/**
* \file
*
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include "saml21.h"
typedef void (*intfunc) (void);
typedef union {
intfunc __fun;
void * __ptr;
} intvec_elem;
void __iar_program_start(void);
int __low_level_init(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M0+ core handlers */
#pragma weak NMI_Handler = Dummy_Handler
#pragma weak HardFault_Handler = Dummy_Handler
#pragma weak SVC_Handler = Dummy_Handler
#pragma weak PendSV_Handler = Dummy_Handler
#pragma weak SysTick_Handler = Dummy_Handler
/* Peripherals handlers */
#pragma weak SYSTEM_Handler = Dummy_Handler /* MCLK, OSCCTRL, OSC32KCTRL, PAC, PM, SUPC, TAL */
#pragma weak WDT_Handler = Dummy_Handler
#pragma weak RTC_Handler = Dummy_Handler
#pragma weak EIC_Handler = Dummy_Handler
#pragma weak NVMCTRL_Handler = Dummy_Handler
#pragma weak DMAC_Handler = Dummy_Handler
#ifdef ID_USB
#pragma weak USB_Handler = Dummy_Handler
#endif
#pragma weak EVSYS_Handler = Dummy_Handler
#pragma weak SERCOM0_Handler = Dummy_Handler
#pragma weak SERCOM1_Handler = Dummy_Handler
#pragma weak SERCOM2_Handler = Dummy_Handler
#pragma weak SERCOM3_Handler = Dummy_Handler
#ifdef ID_SERCOM4
#pragma weak SERCOM4_Handler = Dummy_Handler
#endif
#ifdef ID_SERCOM5
#pragma weak SERCOM5_Handler = Dummy_Handler
#endif
#pragma weak TCC0_Handler = Dummy_Handler
#pragma weak TCC1_Handler = Dummy_Handler
#pragma weak TCC2_Handler = Dummy_Handler
#pragma weak TC0_Handler = Dummy_Handler
#pragma weak TC1_Handler = Dummy_Handler
#ifdef ID_TC2
#pragma weak TC2_Handler = Dummy_Handler
#endif
#ifdef ID_TC3
#pragma weak TC3_Handler = Dummy_Handler
#endif
#pragma weak TC4_Handler = Dummy_Handler
#ifdef ID_ADC
#pragma weak ADC_Handler = Dummy_Handler
#endif
#ifdef ID_AC
#pragma weak AC_Handler = Dummy_Handler
#endif
#ifdef ID_DAC
#pragma weak DAC_Handler = Dummy_Handler
#endif
#ifdef ID_PTC
#pragma weak PTC_Handler = Dummy_Handler
#endif
#ifdef ID_AES
#pragma weak AES_Handler = Dummy_Handler
#endif
#ifdef ID_TRNG
#pragma weak TRNG_Handler = Dummy_Handler
#endif
#ifdef ID_PICOP
#pragma weak PICOP_Handler = Dummy_Handler
#endif
/* Exception Table */
#pragma language = extended
#pragma segment = "CSTACK"
/* The name "__vector_table" has special meaning for C-SPY: */
/* it is where the SP start value is found, and the NVIC vector */
/* table register (VTOR) is initialized to this address if != 0 */
#pragma section = ".intvec"
#pragma location = ".intvec"
const DeviceVectors __vector_table[] = {
__sfe("CSTACK"),
(void*) __iar_program_start,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) SYSTEM_Handler, /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
(void*) WDT_Handler, /* 1 Watchdog Timer */
(void*) RTC_Handler, /* 2 Real-Time Counter */
(void*) EIC_Handler, /* 3 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 4 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 5 Direct Memory Access Controller */
#ifdef ID_USB
(void*) USB_Handler, /* 6 Universal Serial Bus */
#else
(void*) (0UL), /* Reserved*/
#endif
(void*) EVSYS_Handler, /* 7 Event System Interface */
(void*) SERCOM0_Handler, /* 8 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 9 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 10 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 11 Serial Communication Interface 3 */
#ifdef ID_SERCOM4
(void*) SERCOM4_Handler, /* 12 Serial Communication Interface 4 */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_SERCOM5
(void*) SERCOM5_Handler, /* 13 Serial Communication Interface 5 */
#else
(void*) (0UL), /* Reserved*/
#endif
(void*) TCC0_Handler, /* 14 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 15 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 16 Timer Counter Control 2 */
(void*) TC0_Handler, /* 17 Basic Timer Counter 0 */
(void*) TC1_Handler, /* 18 Basic Timer Counter 1 */
#ifdef ID_TC2
(void*) TC2_Handler, /* 19 Basic Timer Counter 2 */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_TC3
(void*) TC3_Handler, /* 20 Basic Timer Counter 3 */
#else
(void*) (0UL), /* Reserved*/
#endif
(void*) TC4_Handler, /* 21 Basic Timer Counter 4 */
#ifdef ID_ADC
(void*) ADC_Handler, /* 22 Analog Digital Converter */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_AC
(void*) AC_Handler, /* 23 Analog Comparators */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_DAC
(void*) DAC_Handler, /* 24 Digital-to-Analog Converter */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_PTC
(void*) PTC_Handler, /* 25 Peripheral Touch Controller */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_AES
(void*) AES_Handler, /* 26 Advanced Encryption Standard */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_TRNG
(void*) TRNG_Handler, /* 27 True Random Generator */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_PICOP
(void*) PICOP_Handler /* 28 PicoProcessor */
#else
(void*) (0UL) /* Reserved*/
#endif
};
/**------------------------------------------------------------------------------
* This is the code that gets called on processor reset. To initialize the
* device.
*------------------------------------------------------------------------------*/
int __low_level_init(void)
{
uint32_t *pSrc = __section_begin(".intvec");
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
return 1; /* if return 0, the data sections will not be initialized */
}
/**------------------------------------------------------------------------------
* This is the code that gets called on processor reset. To initialize the
* device.
*------------------------------------------------------------------------------*/
void Reset_Handler(void)
{
/* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
NVMCTRL->CTRLB.bit.MANW = 1;
__iar_program_start();
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

13
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/device/cmsis.h
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/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in samr21j18a specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "samr21.h"
#include "cmsis_nvic.h"
#endif

37
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/device/cmsis_nvic.h
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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2011 ARM Limited. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 28) // CORE + MCU Peripherals
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include <compiler.h>
#include "cmsis.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
#define _SERCOM_SPI_NAME(n, unused) \
SPI##n,
#define _SERCOM_PAD_NAME(n, pad) \
SERCOM##n##_PAD##pad = ((n & 0xF) | ((pad & 0xF) << 4)),
#define _SERCOM_I2C_NAME(n, unused) \
I2C##n,
typedef enum {
UART_0 = (int)0x42000800UL, // Base address of SERCOM0
UART_1 = (int)0x42000C00UL, // Base address of SERCOM1
UART_2 = (int)0x42001000UL, // Base address of SERCOM2
UART_3 = (int)0x42001400UL, // Base address of SERCOM3
UART_4 = (int)0x42001800UL, // Base address of SERCOM4
UART_5 = (int)0x42001C00UL // Base address of SERCOM5
} UARTName;
typedef enum { // for each input control mux 4,5,6,7,16,17,10,11 used in R21
ADC_2 = 0x2ul,
ADC_3 = 0x3ul,
ADC_4 = 0x4ul,
ADC_5 = 0x5ul,
ADC_6 = 0x6ul,
ADC_7 = 0x7ul,
ADC_8 = 0x8ul,
ADC_10 = 0xAul,
ADC_11 = 0xBul,
ADC_16 = 0x10ul,
ADC_17 = 0x11ul,
ADC_18 = 0x12ul,
ADC_19 = 0x13ul
} ADCName;
typedef enum { // for each channel
EXTINT_0 = 0,
EXTINT_1,
EXTINT_2,
EXTINT_3,
EXTINT_4,
EXTINT_5,
EXTINT_6,
EXTINT_7,
EXTINT_8,
EXTINT_9,
EXTINT_10,
EXTINT_11,
EXTINT_12,
EXTINT_13,
EXTINT_14,
EXTINT_15
} EXTINTName;
typedef enum {
MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_NAME, ~)
} SPIName;
typedef enum {
MREPEAT(SERCOM_INST_NUM, _SERCOM_I2C_NAME, ~)
} I2CName;
typedef enum {
/* Pad 0 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 0)
/* Pad 1 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 1)
/* Pad 2 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 2)
/* Pad 3 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 3)
} SercomPadName;
typedef enum {
PWM_0 = (0x42002000UL), /**< \brief (TCC0) APB Base Address */
PWM_1 = (0x42002400UL), /**< \brief (TCC1) APB Base Address */
PWM_2 = (0x42002800UL), /**< \brief (TCC2) APB Base Address */
} PWMName;
struct pwm_pin_channel {
PinName pin;
PWMName pwm;
uint8_t channel_index;
};
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_0
// Default peripherals
#define MBED_SPI0 PB22, PB02, PB23, PA14
#define MBED_UART0 PA04, PA05
#define MBED_UARTUSB USBTX, USBRX
#define MBED_I2C0 PA16, PA17
#define MBED_ANALOGIN0 PA04
#define MBED_ANALOGIN1 PA05
#define MBED_ANALOGIN2 PA06
#define MBED_ANALOGIN3 PA07
#define MBED_ANALOGIN4 PB02
#define MBED_ANALOGIN5 PB03
#define MBED_ANALOGIN7 PA08
#define MBED_ANALOGIN8 PA09
#define MBED_PWMOUT0 PA18
#define MBED_PWMOUT1 PA19
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralPins.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************ADC***************/
const PinMap PinMap_ADC[] = {
{PB08, ADC_2, 1},
{PB09, ADC_3, 1},
{PA04, ADC_4, 1},
{PA05, ADC_5, 1},
{PA06, ADC_6, 1},
{PA07, ADC_7, 1},
{PB00, ADC_8, 1},
{PB02, ADC_10, 1},
{PB03, ADC_11, 1},
{PA08, ADC_16, 1},
{PA09, ADC_17, 1},
{PA10, ADC_18, 1},
{PA11, ADC_19, 1},
/* Not connected */
{NC , NC , NC}
};
/************SERCOM Pins***********/
const PinMap PinMap_SERCOM_PAD[] = {
{PA00, SERCOM1_PAD0, 3},
{PA01, SERCOM1_PAD1, 3},
{PA04, SERCOM0_PAD0, 3},
{PA05, SERCOM0_PAD1, 3},
{PA06, SERCOM0_PAD2, 3},
{PA07, SERCOM0_PAD3, 3},
{PA08, SERCOM0_PAD0, 2},
{PA09, SERCOM0_PAD1, 2},
{PA12, SERCOM2_PAD0, 2},
{PA13, SERCOM2_PAD1, 2},
{PA14, SERCOM2_PAD2, 2},
{PA15, SERCOM2_PAD3, 2},
{PA16, SERCOM1_PAD0, 2},
{PA17, SERCOM1_PAD1, 2},
{PA18, SERCOM1_PAD2, 2},
{PA19, SERCOM1_PAD3, 2},
{PA22, SERCOM3_PAD0, 2},
{PA23, SERCOM3_PAD1, 2},
{PA24, SERCOM3_PAD2, 2},
{PA25, SERCOM3_PAD3, 2},
{PA27, SERCOM3_PAD0, 5},
{PA28, SERCOM3_PAD1, 5},
{PA30, SERCOM1_PAD2, 3},
{PA31, SERCOM1_PAD3, 3},
{PB02, SERCOM5_PAD0, 3},
{PB03, SERCOM5_PAD1, 3},
{PB22, SERCOM5_PAD2, 3},
{PB23, SERCOM5_PAD3, 3},
{PB30, SERCOM4_PAD2, 5},
{PB31, SERCOM4_PAD1, 5},
{PC18, SERCOM4_PAD3, 5},
{PC19, SERCOM4_PAD0, 5},
/* Not connected */
{NC , NC , NC}
};
/*******SERCOM Pins extended*******/
const PinMap PinMap_SERCOM_PADEx[] = {
{PA08, SERCOM2_PAD0, 3},
{PA09, SERCOM2_PAD1, 3},
{PA16, SERCOM3_PAD0, 3},
{PA17, SERCOM3_PAD1, 3},
{PA18, SERCOM3_PAD2, 3},
{PA19, SERCOM3_PAD3, 3},
{PA22, SERCOM5_PAD0, 3},
{PA23, SERCOM5_PAD1, 3},
{PA24, SERCOM5_PAD2, 3},
{PA25, SERCOM5_PAD3, 3},
/* Not connected */
{NC , NC , NC}
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
{PA00, PWM_2, 4},
{PA01, PWM_2, 4},
{PA04, PWM_0, 4},
{PA05, PWM_0, 4},
{PA06, PWM_1, 4},
{PA07, PWM_1, 4},
{PA08, PWM_0, 4},
{PA09, PWM_0, 4},
{PA10, PWM_1, 4},
{PA11, PWM_1, 4},
{PA12, PWM_2, 4},
{PA13, PWM_2, 4},
{PA16, PWM_2, 4},
{PA17, PWM_2, 4},
{PA18, PWM_0, 5},
{PA19, PWM_0, 5},
{PA20, PWM_0, 5},
{PA22, PWM_0, 5},
{PA23, PWM_0, 5},
{PA24, PWM_1, 5},
{PA25, PWM_1, 5},
{PA30, PWM_1, 4},
{PA31, PWM_1, 4},
{PB16, PWM_0, 5},
{PB17, PWM_0, 5},
{PB30, PWM_0, 4},
{PB31, PWM_0, 4},
/* Not connected */
{NC , NC , NC}
};
/**********EXTINT*************/
const PinMap PinMap_EXTINT[] = {
{PA16, EXTINT_0, 0},
{PB00, EXTINT_0, 0},
{PB16, EXTINT_0, 0},
{PA00, EXTINT_0, 0},
{PA17, EXTINT_1, 0},
{PB17, EXTINT_1, 0},
{PA01, EXTINT_1, 0},
{PA18, EXTINT_2, 0},
{PB02, EXTINT_2, 0},
{PA19, EXTINT_3, 0},
{PB03, EXTINT_3, 0},
{PA04, EXTINT_4, 0},
{PA20, EXTINT_4, 0},
{PA05, EXTINT_5, 0},
{PA06, EXTINT_6, 0},
{PA22, EXTINT_6, 0},
{PB22, EXTINT_6, 0},
{PA07, EXTINT_7, 0},
{PA23, EXTINT_7, 0},
{PB23, EXTINT_7, 0},
{PA28, EXTINT_8, 0},
{PB08, EXTINT_8, 0},
{PA09, EXTINT_9, 0},
{PB09, EXTINT_9, 0},
{PA30, EXTINT_10, 0},
{PA10, EXTINT_10, 0},
{PA31, EXTINT_11, 0},
{PA11, EXTINT_11, 0},
{PA12, EXTINT_12, 0},
{PA24, EXTINT_12, 0},
{PA13, EXTINT_13, 0},
{PA25, EXTINT_13, 0},
{PB14, EXTINT_14, 0},
{PB30, EXTINT_14, 0},
{PA14, EXTINT_14, 0},
{PA15, EXTINT_15, 0},
{PA27, EXTINT_15, 0},
{PB15, EXTINT_15, 0},
{PB31, EXTINT_15, 0},
/* Not connected */
{NC , NC , NC}
};
const struct pwm_pin_channel pwn_pins[] = {
{PA00, PWM_2, 0},
{PA01, PWM_2, 1},
{PA04, PWM_0, 0},
{PA05, PWM_0, 1},
{PA06, PWM_1, 0},
{PA07, PWM_1, 1},
{PA08, PWM_0, 0},
{PA09, PWM_0, 1},
{PA10, PWM_1, 0},
{PA11, PWM_1, 1},
{PA12, PWM_2, 0},
{PA13, PWM_2, 1},
{PA16, PWM_2, 0},
{PA17, PWM_2, 1},
{PA18, PWM_0, 2},
{PA19, PWM_0, 3},
{PA20, PWM_0, 6},
{PA22, PWM_0, 4},
{PA23, PWM_0, 5},
{PA24, PWM_1, 2},
{PA25, PWM_1, 3},
{PA30, PWM_1, 0},
{PA31, PWM_1, 1},
{PB16, PWM_0, 4},
{PB17, PWM_0, 5},
{PB30, PWM_0, 0},
{PB31, PWM_0, 1},
/* Not connected */
{(PinName) NC ,(PWMName) NC ,(uint8_t) NC}
};

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralPins.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H
#include "pinmap.h"
#include "PeripheralNames.h"
/************ADC***************/
extern const PinMap PinMap_ADC[];
//*********SERCOM*************/
extern const PinMap PinMap_SERCOM_PAD[];
extern const PinMap PinMap_SERCOM_PADEx[];
/************PWM***************/
extern const PinMap PinMap_PWM[];
/**********EXTINT*************/
extern const PinMap PinMap_EXTINT[];
#endif

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT,
PIN_INPUT_OUTPUT //pin state can be set and read back
} PinDirection;
typedef enum {
PA00 = 0,
PA01 = 1,
PA04 = 4,
PA05 = 5,
PA06 = 6,
PA07 = 7,
PA08 = 8,
PA09 = 9,
PA10 = 10,
PA11 = 11,
PA12 = 12,
PA13 = 13,
PA14 = 14,
PA15 = 15,
PA16 = 16,
PA17 = 17,
PA18 = 18,
PA19 = 19,
PA20 = 20,
PA22 = 22,
PA23 = 23,
PA24 = 24,
PA25 = 25,
PA27 = 27,
PA28 = 28,
PA30 = 30,
PA31 = 31,
PB00 = 32,
PB02 = 34,
PB03 = 35,
PB08 = 40,
PB09 = 41,
PB14 = 46,
PB15 = 47,
PB16 = 48,
PB17 = 49,
PB22 = 54,
PB23 = 55,
PB30 = 62,
PB31 = 63,
PC16 = 80,
PC18 = 82,
PC19 = 83,
USBTX = PA04,
USBRX = PA05,
LED1 = PA19,
LED2 = PA19,
LED3 = PA19,
LED4 = PA19,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

33
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c
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@ -1,33 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "compiler.h"
#include "system.h"
uint8_t g_sys_init = 0;
//called before main - implement here if board needs it ortherwise, let
// the application override this if necessary
//TODO: To be implemented by adding system init and board init
void mbed_sdk_init()
{
if(g_sys_init == 0) {
g_sys_init = 1;
system_init();
}
}
/***************************************************************/

475
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/samr21_xplained_pro.h
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@ -1,475 +0,0 @@
#ifndef SAMR21_XPLAINED_PRO_H_INCLUDED
#define SAMR21_XPLAINED_PRO_H_INCLUDED
#include <conf_board.h>
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \ingroup group_common_boards
* \defgroup samr21_xplained_pro_group SAM R21 Xplained Pro board
*
* @{
*/
void system_board_init(void);
/**
* \defgroup samr21_xplained_pro_features_group Features
*
* Symbols that describe features and capabilities of the board.
*
* @{
*/
/** Name string macro */
#define BOARD_NAME "SAMR21_XPLAINED_PRO"
/** \name Resonator definitions
* @{ */
#define BOARD_FREQ_SLCK_XTAL (32768U)
#define BOARD_FREQ_SLCK_BYPASS (32768U)
#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */
#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */
#define BOARD_MCK CHIP_FREQ_CPU_MAX
#define BOARD_OSC_STARTUP_US 15625
/** @} */
/** \name LED0 definitions
* @{ */
#define LED0_PIN PIN_PA19
#define LED0_ACTIVE false
#define LED0_INACTIVE !LED0_ACTIVE
#define LED0 LED0_PIN
/** @} */
/** \name SW0 definitions
* @{ */
#define SW0_PIN PIN_PA28
#define SW0_ACTIVE false
#define SW0_INACTIVE !SW0_ACTIVE
#define SW0_EIC_PIN PIN_PA28A_EIC_EXTINT8
#define SW0_EIC_MUX MUX_PA28A_EIC_EXTINT8
#define SW0_EIC_PINMUX PINMUX_PA28A_EIC_EXTINT8
#define SW0_EIC_LINE 8
/** @} */
/**
* \name LED #0 definitions
*
* Wrapper macros for LED0, to ensure common naming across all Xplained Pro
* boards.
*
* @{ */
#define LED_0_NAME "LED0 (yellow)"
#define LED_0_PIN LED0_PIN
#define LED_0_ACTIVE LED0_ACTIVE
#define LED_0_INACTIVE LED0_INACTIVE
#define LED0_GPIO LED0_PIN
#define LED_0_PWM_MODULE TC3
#define LED_0_PWM_CHANNEL 1
#define LED_0_PWM_OUTPUT 1
#define LED_0_PWM_PIN PIN_PA19E_TC3_WO1
#define LED_0_PWM_MUX MUX_PA19E_TC3_WO1
#define LED_0_PWM_PINMUX PINMUX_PA19E_TC3_WO1
#define LED_0_PWM4CTRL_MODULE TCC0
#define LED_0_PWM4CTRL_CHANNEL 3
#define LED_0_PWM4CTRL_OUTPUT 3
#define LED_0_PWM4CTRL_PIN PIN_PA19F_TCC0_WO3
#define LED_0_PWM4CTRL_MUX MUX_PA19F_TCC0_WO3
#define LED_0_PWM4CTRL_PINMUX PINMUX_PA19F_TCC0_WO3
/** @} */
/** Number of on-board LEDs */
#define LED_COUNT 1
/**
* \name Button #0 definitions
*
* Wrapper macros for SW0, to ensure common naming across all Xplained Pro
* boards.
*
* @{ */
#define BUTTON_0_NAME "SW0"
#define BUTTON_0_PIN SW0_PIN
#define BUTTON_0_ACTIVE SW0_ACTIVE
#define BUTTON_0_INACTIVE SW0_INACTIVE
#define BUTTON_0_EIC_PIN SW0_EIC_PIN
#define BUTTON_0_EIC_MUX SW0_EIC_MUX
#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX
#define BUTTON_0_EIC_LINE SW0_EIC_LINE
/** @} */
/** Number of on-board buttons */
#define BUTTON_COUNT 1
/** \name Extension header #1 pin definitions
* @{
*/
#define EXT1_PIN_3 PIN_PA06
#define EXT1_PIN_4 PIN_PA07
#define EXT1_PIN_5 PIN_PA13
#define EXT1_PIN_6 PIN_PA28
#define EXT1_PIN_7 PIN_PA18
#define EXT1_PIN_8 PIN_PA19
#define EXT1_PIN_9 PIN_PA22
#define EXT1_PIN_10 PIN_PA23
#define EXT1_PIN_11 PIN_PA16
#define EXT1_PIN_12 PIN_PA17
#define EXT1_PIN_13 PIN_PA05
#define EXT1_PIN_14 PIN_PA04
#define EXT1_PIN_15 PIN_PB03
#define EXT1_PIN_16 PIN_PB22
#define EXT1_PIN_17 PIN_PB02
#define EXT1_PIN_18 PIN_PB23
/** @} */
/** \name Extension header #1 pin definitions by function
* @{
*/
#define EXT1_PIN_ADC_0 EXT1_PIN_3
#define EXT1_PIN_ADC_1 EXT1_PIN_4
#define EXT1_PIN_GPIO_0 EXT1_PIN_5
#define EXT1_PIN_GPIO_1 EXT1_PIN_6
#define EXT1_PIN_PWM_0 EXT1_PIN_7
#define EXT1_PIN_PWM_1 EXT1_PIN_8
#define EXT1_PIN_GPIO_3 EXT1_PIN_9
#define EXT1_PIN_GPIO_4 EXT1_PIN_10
#define EXT1_PIN_I2C_SDA EXT1_PIN_11
#define EXT1_PIN_I2C_SCL EXT1_PIN_12
#define EXT1_PIN_UART_RX EXT1_PIN_13
#define EXT1_PIN_UART_TX EXT1_PIN_14
#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15
#define EXT1_PIN_SPI_MOSI EXT1_PIN_16
#define EXT1_PIN_SPI_MISO EXT1_PIN_17
#define EXT1_PIN_SPI_SCK EXT1_PIN_18
/** @} */
/** \name Extension header #1 ADC definitions
* @{
*/
#define EXT1_ADC_MODULE ADC
#define EXT1_ADC_0_CHANNEL 6
#define EXT1_ADC_0_PIN PIN_PA06B_ADC_AIN6
#define EXT1_ADC_0_MUX MUX_PA06B_ADC_AIN6
#define EXT1_ADC_0_PINMUX PINMUX_PA06B_ADC_AIN6
#define EXT1_ADC_1_CHANNEL 7
#define EXT1_ADC_1_PIN PIN_PA07B_ADC_AIN7
#define EXT1_ADC_1_MUX MUX_PA07B_ADC_AIN7
#define EXT1_ADC_1_PINMUX PINMUX_PA07B_ADC_AIN7
/** @} */
/** \name Extension header #1 PWM definitions
* @{
*/
#define EXT1_PWM_MODULE TC3
#define EXT1_PWM_0_CHANNEL 0
#define EXT1_PWM_0_PIN PIN_PA18E_TC3_WO0
#define EXT1_PWM_0_MUX MUX_PA18E_TC3_WO0
#define EXT1_PWM_0_PINMUX PINMUX_PA18E_TC3_WO0
#define EXT1_PWM_1_CHANNEL 1
#define EXT1_PWM_1_PIN PIN_PA19E_TC3_WO1
#define EXT1_PWM_1_MUX MUX_PA19E_TC3_WO1
#define EXT1_PWM_1_PINMUX PINMUX_PA19E_TC3_WO1
/** @} */
/** \name Extension header #1 PWM for Control definitions
* @{
*/
#define EXT1_PWM4CTRL_MODULE TCC0
#define EXT1_PWM4CTRL_0_CHANNEL 2
#define EXT1_PWM4CTRL_0_OUTPUT 2
#define EXT1_PWM4CTRL_0_PIN PIN_PA18F_TCC0_WO2
#define EXT1_PWM4CTRL_0_MUX MUX_PA18F_TCC0_WO2
#define EXT1_PWM4CTRL_0_PINMUX PINMUX_PA18F_TCC0_WO2
#define EXT1_PWM4CTRL_1_CHANNEL 3
#define EXT1_PWM4CTRL_1_OUTPUT 3
#define EXT1_PWM4CTRL_1_PIN PIN_PA19F_TCC0_WO3
#define EXT1_PWM4CTRL_1_MUX MUX_PA19F_TCC0_WO3
#define EXT1_PWM4CTRL_1_PINMUX PINMUX_PA19F_TCC0_WO3
/** @} */
/** \name Extension header #1 IRQ/External interrupt definitions
* @{
*/
#define EXT1_IRQ_MODULE EIC
#define EXT1_IRQ_INPUT 6
#define EXT1_IRQ_PIN PIN_PA22A_EIC_EXTINT6
#define EXT1_IRQ_MUX MUX_PA22A_EIC_EXTINT6
#define EXT1_IRQ_PINMUX PINMUX_PA22A_EIC_EXTINT6
/** @} */
/** \name Extension header #1 I2C definitions
* @{
*/
#define EXT1_I2C_MODULE SERCOM1
#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0
#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1
#define EXT1_I2C_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX
#define EXT1_I2C_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX
/** @} */
/** \name Extension header #1 UART definitions
* @{
*/
#define EXT1_UART_MODULE SERCOM0
#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0
#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1
#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EXT1_UART_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX
#define EXT1_UART_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX
/** @} */
/** \name Extension header #1 SPI definitions
* @{
*/
#define EXT1_SPI_MODULE SERCOM5
#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB02D_SERCOM5_PAD0
#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB03D_SERCOM5_PAD1
#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EXT1_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EXT1_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Extension header #3 pin definitions
* @{
*/
#define EXT3_PIN_5 PIN_PA15
#define EXT3_PIN_10 PIN_PA08
#define EXT3_PIN_11 PIN_PA16
#define EXT3_PIN_12 PIN_PA17
#define EXT3_PIN_15 PIN_PA14
#define EXT3_PIN_16 PIN_PB22
#define EXT3_PIN_17 PIN_PB02
#define EXT3_PIN_18 PIN_PB23
/** @} */
/** \name Extension header #3 pin definitions by function
* @{
*/
#define EXT3_PIN_GPIO_0 EXT3_PIN_5
#define EXT3_PIN_GPIO_1 EXT3_PIN_10
#define EXT3_PIN_I2C_SDA EXT3_PIN_11
#define EXT3_PIN_I2C_SCL EXT3_PIN_12
#define EXT3_PIN_GPIO_2 EXT3_PIN_15
#define EXT3_PIN_SPI_MOSI EXT3_PIN_16
#define EXT3_PIN_SPI_MISO EXT3_PIN_17
#define EXT3_PIN_SPI_SCK EXT3_PIN_18
/** @} */
/** \name Extension header #3 SPI definitions
* @{
*/
#define EXT3_SPI_SLAVE_SELECT_PIN PIN_PA14
#define EXT3_SPI_MODULE SERCOM5
#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB02D_SERCOM5_PAD0
#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EXT3_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EXT3_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Extension header #3 Dataflash
* @{
*/
#define EXT3_DATAFLASH_SPI_MODULE EXT3_SPI_MODULE
#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING
#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0
#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1
#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2
#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3
/** @} */
/** \name USB definitions
* @{
*/
#define USB_ID
#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP
#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP
#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP
#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM
#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM
#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM
#define USB_VBUS_PIN PIN_PA07
#define USB_VBUS_EIC_LINE 7
#define USB_VBUS_EIC_MUX MUX_PA07A_EIC_EXTINT7
#define USB_VBUS_EIC_PINMUX PINMUX_PA07A_EIC_EXTINT7
/* USB ID pin is not connected */
//#define USB_ID_PIN -1
//#define USB_ID_EIC_LINE -1
//#define USB_ID_EIC_MUX -1
//#define USB_ID_EIC_PINMUX -1
/** @} */
/** \name Embedded debugger GPIO interface definitions
* @{
*/
#define EDBG_GPIO0_PIN PIN_PA08
#define EDBG_GPIO1_PIN PIN_PA09
#define EDBG_GPIO2_PIN PIN_PA12
#define EDBG_GPIO3_PIN PIN_PA14
/** @} */
/** \name Embedded debugger USART interface definitions
* @{
*/
#define EDBG_UART_MODULE -1 /* Not available on this board */
#define EDBG_UART_RX_PIN -1 /* Not available on this board */
#define EDBG_UART_RX_MUX -1 /* Not available on this board */
#define EDBG_UART_RX_PINMUX -1 /* Not available on this board */
#define EDBG_UART_RX_SERCOM_PAD -1 /* Not available on this board */
#define EDBG_UART_TX_PIN -1 /* Not available on this board */
#define EDBG_UART_TX_MUX -1 /* Not available on this board */
#define EDBG_UART_TX_PINMUX -1 /* Not available on this board */
#define EDBG_UART_TX_SERCOM_PAD -1 /* Not available on this board */
/** @} */
/** \name Embedded debugger I2C interface definitions
* @{
*/
#define EDBG_I2C_MODULE SERCOM1
#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0
#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1
#define EDBG_I2C_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX
#define EDBG_I2C_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX
/** @} */
/** \name Embedded debugger SPI interface definitions
* @{
*/
#define EDBG_SPI_SLAVE_SELECT_PIN PIN_PA27
#define EDBG_SPI_MODULE SERCOM5
#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB02D_SERCOM5_PAD0
#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EDBG_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EDBG_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Embedded debugger CDC Gateway USART interface definitions
* @{
*/
#define EDBG_CDC_MODULE SERCOM0
#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0
#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1
#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX
#define EDBG_CDC_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX
/** @} */
#define RF_SPI_MODULE SERCOM4
#define RF_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define RF_SPI_SERCOM_PINMUX_PAD0 PINMUX_PC19F_SERCOM4_PAD0
#define RF_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB31D_SERCOM5_PAD1
#define RF_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB30F_SERCOM4_PAD2
#define RF_SPI_SERCOM_PINMUX_PAD3 PINMUX_PC18F_SERCOM4_PAD3
#define RF_IRQ_MODULE EIC
#define RF_IRQ_INPUT 0
#define RF_IRQ_PIN PIN_PB00A_EIC_EXTINT0
#define RF_IRQ_MUX MUX_PB00A_EIC_EXTINT0
#define RF_IRQ_PINMUX PINMUX_PB00A_EIC_EXTINT0
/** \name 802.15.4 TRX Interface definitions
* @{
*/
#define AT86RFX_SPI SERCOM4
#define AT86RFX_RST_PIN PIN_PB15
#define AT86RFX_IRQ_PIN PIN_PB00
#define AT86RFX_SLP_PIN PIN_PA20
#define AT86RFX_SPI_CS PIN_PB31
#define AT86RFX_SPI_MOSI PIN_PB30
#define AT86RFX_SPI_MISO PIN_PC19
#define AT86RFX_SPI_SCK PIN_PC18
#define PIN_RFCTRL1 PIN_PA09
#define PIN_RFCTRL2 PIN_PA12
#define RFCTRL_CFG_ANT_DIV 4
#define AT86RFX_SPI_SERCOM_MUX_SETTING RF_SPI_SERCOM_MUX_SETTING
#define AT86RFX_SPI_SERCOM_PINMUX_PAD0 RF_SPI_SERCOM_PINMUX_PAD0
#define AT86RFX_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define AT86RFX_SPI_SERCOM_PINMUX_PAD2 RF_SPI_SERCOM_PINMUX_PAD2
#define AT86RFX_SPI_SERCOM_PINMUX_PAD3 RF_SPI_SERCOM_PINMUX_PAD3
#define AT86RFX_IRQ_CHAN RF_IRQ_INPUT
#define AT86RFX_IRQ_PINMUX RF_IRQ_PINMUX
/** Enables the transceiver main interrupt. */
#define ENABLE_TRX_IRQ() \
extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
/** Disables the transceiver main interrupt. */
#define DISABLE_TRX_IRQ() \
extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
/** Clears the transceiver main interrupt. */
#define CLEAR_TRX_IRQ() \
extint_chan_clear_detected(AT86RFX_IRQ_CHAN);
/*
* This macro saves the trx interrupt status and disables the trx interrupt.
*/
#define ENTER_TRX_REGION() \
{ extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
/*
* This macro restores the transceiver interrupt status
*/
#define LEAVE_TRX_REGION() \
extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); }
/** @} */
/**
* \brief Turns off the specified LEDs.
*
* \param led_gpio LED to turn off (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true)
/**
* \brief Turns on the specified LEDs.
*
* \param led_gpio LED to turn on (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false)
/**
* \brief Toggles the specified LEDs.
*
* \param led_gpio LED to toggle (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio)
#ifdef __cplusplus
}
#endif
#endif /* SAMR21_XPLAINED_PRO_H_INCLUDED */

38
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device.h
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@ -1,38 +0,0 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

50
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/SAMR21G18A.sct
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@ -1,50 +0,0 @@
#! armcc -E
;SAMR21G18A
; 256KB FLASH (0x40000) @ 0x000000000
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
; SAMR21G18A: 256KB FLASH (0x40000)
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x40000
#endif
; 32KB RAM (0x8000) @ 0x20000000
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x8000
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment
#define VECTOR_SIZE 0xB0
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

189
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMR21.S
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@ -1,189 +0,0 @@
;/*****************************************************************************
; * @file startup_SAMR21.s
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
; * Atmel SAMR21 Device Series
; * @version V1.00
; * @date 24. February 2014
; *
; * @note
; * Copyright (C) 2014 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PM_Handler ; 0 Power Manager
DCD SYSCTRL_Handler ; 1 System Control
DCD WDT_Handler ; 2 Watchdog Timer
DCD RTC_Handler ; 3 Real-Time Counter
DCD EIC_Handler ; 4 External Interrupt Controller
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
DCD DMAC_Handler ; 6 Direct Memory Access Controller
DCD USB_Handler ; 7 Universal Serial Bus
DCD EVSYS_Handler ; 8 Event System Interface
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
DCD TCC0_Handler ; 15 Timer Counter Control 0
DCD TCC1_Handler ; 16 Timer Counter Control 1
DCD TCC2_Handler ; 17 Timer Counter Control 2
DCD TC3_Handler ; 18 Basic Timer Counter 0
DCD TC4_Handler ; 19 Basic Timer Counter 1
DCD TC5_Handler ; 20 Basic Timer Counter 2
DCD TC6_Handler ; 21 Basic Timer Counter 3
DCD TC7_Handler ; 22 Basic Timer Counter 4
DCD ADC_Handler ; 23 Analog Digital Converter
DCD AC_Handler ; 24 Analog Comparators
DCD DAC_Handler ; 25 Digital Analog Converter
DCD PTC_Handler ; 26 Peripheral Touch Controller
DCD I2S_Handler ; 27 Inter-IC Sound Interface
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PM_Handler [WEAK]
EXPORT SYSCTRL_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT EIC_Handler [WEAK]
EXPORT NVMCTRL_Handler [WEAK]
EXPORT DMAC_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT EVSYS_Handler [WEAK]
EXPORT SERCOM0_Handler [WEAK]
EXPORT SERCOM1_Handler [WEAK]
EXPORT SERCOM2_Handler [WEAK]
EXPORT SERCOM3_Handler [WEAK]
EXPORT SERCOM4_Handler [WEAK]
EXPORT SERCOM5_Handler [WEAK]
EXPORT TCC0_Handler [WEAK]
EXPORT TCC1_Handler [WEAK]
EXPORT TCC2_Handler [WEAK]
EXPORT TC3_Handler [WEAK]
EXPORT TC4_Handler [WEAK]
EXPORT TC5_Handler [WEAK]
EXPORT TC6_Handler [WEAK]
EXPORT TC7_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT AC_Handler [WEAK]
EXPORT DAC_Handler [WEAK]
EXPORT PTC_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
PM_Handler
SYSCTRL_Handler
WDT_Handler
RTC_Handler
EIC_Handler
NVMCTRL_Handler
DMAC_Handler
USB_Handler
EVSYS_Handler
SERCOM0_Handler
SERCOM1_Handler
SERCOM2_Handler
SERCOM3_Handler
SERCOM4_Handler
SERCOM5_Handler
TCC0_Handler
TCC1_Handler
TCC2_Handler
TC3_Handler
TC4_Handler
TC5_Handler
TC6_Handler
TC7_Handler
ADC_Handler
AC_Handler
DAC_Handler
PTC_Handler
I2S_Handler
B .
ENDP
ALIGN
END

27
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_STD/SAMR21G18A.sct
View File

@ -1,27 +0,0 @@
#! armcc -E
;SAMR21G18A
;256KB FLASH (0x40000) @ 0x000000000
;2KB RAM (0x8000) @ 0x20000000
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define Stack_Size MBED_BOOT_STACK_SIZE
;SAMR21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
LR_IROM1 0x00000000 0x40000 { ; load region size_region
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment
RW_IRAM1 (0x20000000+0xB0) (0x8000-0xB0-Stack_Size) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK 0x20000000+0x8000 EMPTY -Stack_Size { ; Stack region growing down
}
}

189
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMR21.S
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@ -1,189 +0,0 @@
;/*****************************************************************************
; * @file startup_SAMR21.s
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
; * Atmel SAMR21 Device Series
; * @version V1.00
; * @date 24. February 2014
; *
; * @note
; * Copyright (C) 2014 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PM_Handler ; 0 Power Manager
DCD SYSCTRL_Handler ; 1 System Control
DCD WDT_Handler ; 2 Watchdog Timer
DCD RTC_Handler ; 3 Real-Time Counter
DCD EIC_Handler ; 4 External Interrupt Controller
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
DCD DMAC_Handler ; 6 Direct Memory Access Controller
DCD USB_Handler ; 7 Universal Serial Bus
DCD EVSYS_Handler ; 8 Event System Interface
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
DCD TCC0_Handler ; 15 Timer Counter Control 0
DCD TCC1_Handler ; 16 Timer Counter Control 1
DCD TCC2_Handler ; 17 Timer Counter Control 2
DCD TC3_Handler ; 18 Basic Timer Counter 0
DCD TC4_Handler ; 19 Basic Timer Counter 1
DCD TC5_Handler ; 20 Basic Timer Counter 2
DCD TC6_Handler ; 21 Basic Timer Counter 3
DCD TC7_Handler ; 22 Basic Timer Counter 4
DCD ADC_Handler ; 23 Analog Digital Converter
DCD AC_Handler ; 24 Analog Comparators
DCD DAC_Handler ; 25 Digital Analog Converter
DCD PTC_Handler ; 26 Peripheral Touch Controller
DCD I2S_Handler ; 27 Inter-IC Sound Interface
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PM_Handler [WEAK]
EXPORT SYSCTRL_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT EIC_Handler [WEAK]
EXPORT NVMCTRL_Handler [WEAK]
EXPORT DMAC_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT EVSYS_Handler [WEAK]
EXPORT SERCOM0_Handler [WEAK]
EXPORT SERCOM1_Handler [WEAK]
EXPORT SERCOM2_Handler [WEAK]
EXPORT SERCOM3_Handler [WEAK]
EXPORT SERCOM4_Handler [WEAK]
EXPORT SERCOM5_Handler [WEAK]
EXPORT TCC0_Handler [WEAK]
EXPORT TCC1_Handler [WEAK]
EXPORT TCC2_Handler [WEAK]
EXPORT TC3_Handler [WEAK]
EXPORT TC4_Handler [WEAK]
EXPORT TC5_Handler [WEAK]
EXPORT TC6_Handler [WEAK]
EXPORT TC7_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT AC_Handler [WEAK]
EXPORT DAC_Handler [WEAK]
EXPORT PTC_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
PM_Handler
SYSCTRL_Handler
WDT_Handler
RTC_Handler
EIC_Handler
NVMCTRL_Handler
DMAC_Handler
USB_Handler
EVSYS_Handler
SERCOM0_Handler
SERCOM1_Handler
SERCOM2_Handler
SERCOM3_Handler
SERCOM4_Handler
SERCOM5_Handler
TCC0_Handler
TCC1_Handler
TCC2_Handler
TC3_Handler
TC4_Handler
TC5_Handler
TC6_Handler
TC7_Handler
ADC_Handler
AC_Handler
DAC_Handler
PTC_Handler
I2S_Handler
B .
ENDP
ALIGN
END

127
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_GCC_ARM/samr21g18a.ld
View File

@ -1,127 +0,0 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Memory Spaces Definitions */
MEMORY {
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
ram (rwx) : ORIGIN = 0x20000000 + 0xB0, LENGTH = 0x00008000 - 0xB0
}
/* Section Definitions */
SECTIONS {
.text :
{
. = ALIGN(8);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(8);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(8);
KEEP(*(.fini))
. = ALIGN(8);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(8);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(8);
_etext = .;
.relocate :
AT (_etext)
{
. = ALIGN(8);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(8);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(8);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(8);
_ebss = . ;
_ezero = .;
} > ram
.heap (NOLOAD) :
{
. = ALIGN(8);
__end__ = . ;
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
__HeapLimit = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
. = ALIGN(8);
}

212
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_GCC_ARM/startup_samr21.c
View File

@ -1,212 +0,0 @@
#include "samr21.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M0+ core handlers */
void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef USB_IRQn
void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef SERCOM4_IRQn
void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef SERCOM5_IRQn
void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef TC6_IRQn
void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef TC7_IRQn
void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ADC_IRQn
void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef AC_IRQn
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef DAC_IRQn
void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef PTC_IRQn
void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Exception Table */
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
(void*) (&_estack),
(void*) Reset_Handler,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
#ifdef USB_IRQn
(void*) USB_Handler, /* 7 Universal Serial Bus */
#else
(void*) (0UL), /* Reserved */
#endif
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
#ifdef SERCOM4_IRQn
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef SERCOM5_IRQn
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
#else
(void*) (0UL), /* Reserved */
#endif
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
#ifdef TC6_IRQn
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef TC7_IRQn
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef ADC_IRQn
(void*) ADC_Handler, /* 23 Analog Digital Converter */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef AC_IRQn
(void*) AC_Handler, /* 24 Analog Comparators */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef DAC_IRQn
(void*) DAC_Handler, /* 25 Digital Analog Converter */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef PTC_IRQn
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
#else
(void*) (0UL), /* Reserved */
#endif
(void*) I2S_Handler /* 27 Inter-IC Sound Interface */
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */
main();
/* Infinite loop */
while (1);
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

249
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_IAR/startup_samr21.c
View File

@ -1,249 +0,0 @@
/**
* \file
*
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include "samr21.h"
typedef void (*intfunc) (void);
typedef union {
intfunc __fun;
void * __ptr;
} intvec_elem;
void __iar_program_start(void);
int __low_level_init(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M0+ core handlers */
#pragma weak NMI_Handler = Dummy_Handler
#pragma weak HardFault_Handler = Dummy_Handler
#pragma weak SVC_Handler = Dummy_Handler
#pragma weak PendSV_Handler = Dummy_Handler
#pragma weak SysTick_Handler = Dummy_Handler
/* Peripherals handlers */
#pragma weak PM_Handler = Dummy_Handler
#pragma weak SYSCTRL_Handler = Dummy_Handler
#pragma weak WDT_Handler = Dummy_Handler
#pragma weak RTC_Handler = Dummy_Handler
#pragma weak EIC_Handler = Dummy_Handler
#pragma weak NVMCTRL_Handler = Dummy_Handler
#pragma weak DMAC_Handler = Dummy_Handler
#ifdef ID_USB
#pragma weak USB_Handler = Dummy_Handler
#endif
#pragma weak EVSYS_Handler = Dummy_Handler
#pragma weak SERCOM0_Handler = Dummy_Handler
#pragma weak SERCOM1_Handler = Dummy_Handler
#pragma weak SERCOM2_Handler = Dummy_Handler
#pragma weak SERCOM3_Handler = Dummy_Handler
#ifdef ID_SERCOM4
#pragma weak SERCOM4_Handler = Dummy_Handler
#endif
#ifdef ID_SERCOM5
#pragma weak SERCOM5_Handler = Dummy_Handler
#endif
#pragma weak TCC0_Handler = Dummy_Handler
#pragma weak TCC1_Handler = Dummy_Handler
#pragma weak TCC2_Handler = Dummy_Handler
#pragma weak TC3_Handler = Dummy_Handler
#pragma weak TC4_Handler = Dummy_Handler
#pragma weak TC5_Handler = Dummy_Handler
#ifdef ID_TC6
#pragma weak TC6_Handler = Dummy_Handler
#endif
#ifdef ID_TC7
#pragma weak TC7_Handler = Dummy_Handler
#endif
#ifdef ID_ADC
#pragma weak ADC_Handler = Dummy_Handler
#endif
#ifdef ID_AC
#pragma weak AC_Handler = Dummy_Handler
#endif
#ifdef ID_DAC
#pragma weak DAC_Handler = Dummy_Handler
#endif
#ifdef ID_PTC
#pragma weak PTC_Handler = Dummy_Handler
#endif
#pragma weak I2S_Handler = Dummy_Handler
/* Exception Table */
#pragma language = extended
#pragma segment = "CSTACK"
/* The name "__vector_table" has special meaning for C-SPY: */
/* it is where the SP start value is found, and the NVIC vector */
/* table register (VTOR) is initialized to this address if != 0 */
#pragma section = ".intvec"
#pragma location = ".intvec"
const DeviceVectors __vector_table[] = {
__sfe("CSTACK"),
(void*) __iar_program_start,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
#ifdef ID_USB
(void*) USB_Handler, /* 7 Universal Serial Bus */
#else
(void*) (0UL), /* Reserved*/
#endif
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
#ifdef ID_SERCOM4
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_SERCOM5
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
#else
(void*) (0UL), /* Reserved*/
#endif
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
#ifdef ID_TC6
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_TC7
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_ADC
(void*) ADC_Handler, /* 23 Analog Digital Converter */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_AC
(void*) AC_Handler, /* 24 Analog Comparators */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_DAC
(void*) DAC_Handler, /* 25 Digital Analog Converter */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_PTC
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
#else
(void*) (0UL), /* Reserved*/
#endif
(void*) I2S_Handler, /* 27 Inter-IC Sound Interface */
(void*) (0UL), /* Reserved */
};
/**------------------------------------------------------------------------------
* This is the code that gets called on processor reset. To initialize the
* device.
*------------------------------------------------------------------------------*/
int __low_level_init(void)
{
uint32_t *pSrc = __section_begin(".intvec");
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
return 1; /* if return 0, the data sections will not be initialized */
}
/**------------------------------------------------------------------------------
* This is the code that gets called on processor reset. To initialize the
* device.
*------------------------------------------------------------------------------*/
void Reset_Handler(void)
{
/* Change default QOS values to have the best performance and correct USB behaviour */
SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
#if defined(ID_USB)
USB->DEVICE.QOSCTRL.bit.CQOS = 2;
USB->DEVICE.QOSCTRL.bit.DQOS = 2;
#endif
DMAC->QOSCTRL.bit.DQOS = 2;
DMAC->QOSCTRL.bit.FQOS = 2;
DMAC->QOSCTRL.bit.WRBQOS = 2;
/* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
NVMCTRL->CTRLB.bit.MANW = 1;
__iar_program_start();
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

231
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/analogin_api.c
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@ -1,231 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogin_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "PeripheralPins.h"
#include "adc.h"
#include "status_codes.h"
extern uint8_t g_sys_init;
struct adc_module adc_instance;
void adc_configure_ain_pin(uint32_t pin)
{
#define PIN_INVALID_ADC_AIN 0xFFFFUL
/* Pinmapping table for AINxx -> GPIO pin number */
const uint32_t pinmapping[] = {
#if (SAMD20E | SAMD21E)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
#elif (SAMD20G | SAMD21G)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
#elif (SAMD20J | SAMD21J)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9,
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
#elif SAMR21E
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif SAMR21G
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_PB00B_ADC_AIN8, PIN_INVALID_ADC_AIN,
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
#elif (SAMD10C | SAMD11C)
PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN,
PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif (SAMD10DS | SAMD11DS)
PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN,
PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3,
PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5,
PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif (SAMD10DM | SAMD11DM)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3,
PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5,
PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7,
PIN_PA10B_ADC_AIN8, PIN_PA11B_ADC_AIN9,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif (SAML21E)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif (SAML21G)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif (SAML21J)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9,
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#else
# error ADC pin mappings are not defined for this device.
#endif
};
uint32_t pin_map_result = PIN_INVALID_ADC_AIN;
if (pin <= ADC_EXTCHANNEL_MSB) {
pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
Assert(pin_map_result != PIN_INVALID_ADC_AIN);
struct system_pinmux_config config;
system_pinmux_get_config_defaults(&config);
/* Analog functions are all on MUX setting B */
config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
config.mux_position = 1;
system_pinmux_pin_set_config(pin_map_result, &config);
}
}
void analogin_init(analogin_t *obj, PinName pin)
{
MBED_ASSERT(obj);
if (g_sys_init == 0) {
system_init();
g_sys_init = 1;
}
uint32_t pos_input;
static uint8_t init_flag = 0;
pos_input = pinmap_find_peripheral(pin, PinMap_ADC);
MBED_ASSERT(pos_input != (uint32_t)NC);
adc_get_config_defaults(&(obj->config_adc));
obj->config_adc.positive_input = (enum adc_positive_input)pos_input;
if (init_flag == 0) { // ADC init and enable to be done only once.
adc_init(&adc_instance, ADC, &(obj->config_adc));
adc_enable(&adc_instance);
init_flag = 1;
}
adc_configure_ain_pin(obj->config_adc.positive_input);
adc_configure_ain_pin(obj->config_adc.negative_input);
}
uint16_t analogin_read_u16(analogin_t *obj)
{
MBED_ASSERT(obj);
uint16_t result;
adc_set_positive_input(&adc_instance, obj->config_adc.positive_input);
adc_set_negative_input(&adc_instance, obj->config_adc.negative_input);
adc_start_conversion(&adc_instance);
do {
} while(adc_read(&(adc_instance), &result) == STATUS_BUSY); // 12 bit value
return (uint16_t)(((uint32_t)result * 0xFFFF) / 0x0FFF); // for normalizing to 16 bit value
}
float analogin_read(analogin_t *obj)
{
MBED_ASSERT(obj);
uint16_t value = analogin_read_u16(obj);
return (float)value * (1.0f / (float)0xFFFF);
}
const PinMap *analogin_pinmap()
{
return PinMap_ADC;
}

50
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_board.h
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@ -1,50 +0,0 @@
/**
* \file
*
* \brief SAM D21 Xplained Pro board configuration.
*
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_BOARD_H_INCLUDED
#define CONF_BOARD_H_INCLUDED
#endif /* CONF_BOARD_H_INCLUDED */

198
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_clocks.h
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/**
* \file
*
* \brief SAM D21 Clock configuration
*
* Copyright (C) 2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include <clock.h>
#ifndef CONF_CLOCKS_H_INCLUDED
# define CONF_CLOCKS_H_INCLUDED
/* System clock bus configuration */
# define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT false
# define CONF_CLOCK_FLASH_WAIT_STATES 0
# define CONF_CLOCK_CPU_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_APBA_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_APBB_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_APBC_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */
# define CONF_CLOCK_OSC8M_PRESCALER SYSTEM_OSC8M_DIV_1
# define CONF_CLOCK_OSC8M_ON_DEMAND true
# define CONF_CLOCK_OSC8M_RUN_IN_STANDBY true
/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */
# define CONF_CLOCK_XOSC_ENABLE false
# define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL
# define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY 12000000UL
# define CONF_CLOCK_XOSC_STARTUP_TIME SYSTEM_XOSC_STARTUP_32768
# define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL true
# define CONF_CLOCK_XOSC_ON_DEMAND true
# define CONF_CLOCK_XOSC_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */
# define CONF_CLOCK_XOSC32K_ENABLE false
# define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL
# define CONF_CLOCK_XOSC32K_STARTUP_TIME SYSTEM_XOSC32K_STARTUP_65536
# define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL false
# define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT false
# define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT true
# define CONF_CLOCK_XOSC32K_ON_DEMAND false
# define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY true
/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */
# define CONF_CLOCK_OSC32K_ENABLE false
# define CONF_CLOCK_OSC32K_STARTUP_TIME SYSTEM_OSC32K_STARTUP_130
# define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT false
# define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT true
# define CONF_CLOCK_OSC32K_ON_DEMAND true
# define CONF_CLOCK_OSC32K_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */
# define CONF_CLOCK_DFLL_ENABLE false
# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN
# define CONF_CLOCK_DFLL_ON_DEMAND false
/* DFLL open loop mode configuration */
# define CONF_CLOCK_DFLL_FINE_VALUE (0xff / 4)
/* DFLL closed loop mode configuration */
# define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR GCLK_GENERATOR_1
# define CONF_CLOCK_DFLL_MULTIPLY_FACTOR (48000000 / 32768)
# define CONF_CLOCK_DFLL_QUICK_LOCK true
# define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK true
# define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP true
# define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE true
# define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE (0x1f / 8)
# define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE (0xff / 8)
/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */
# define CONF_CLOCK_DPLL_ENABLE false
# define CONF_CLOCK_DPLL_ON_DEMAND false
# define CONF_CLOCK_DPLL_RUN_IN_STANDBY true
# define CONF_CLOCK_DPLL_LOCK_BYPASS false
# define CONF_CLOCK_DPLL_WAKE_UP_FAST false
# define CONF_CLOCK_DPLL_LOW_POWER_ENABLE true
# define CONF_CLOCK_DPLL_LOCK_TIME SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT
# define CONF_CLOCK_DPLL_REFERENCE_CLOCK SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K
# define CONF_CLOCK_DPLL_FILTER SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT
# define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY 32768
# define CONF_CLOCK_DPLL_REFERENCE_DIVIDER 1
# define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY 48000000
/* DPLL GCLK reference configuration */
# define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR GCLK_GENERATOR_1
/* DPLL GCLK lock timer configuration */
# define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR GCLK_GENERATOR_1
/* Set this to true to configure the GCLK when running clocks_init. If set to
* false, none of the GCLK generators will be configured in clocks_init(). */
# define CONF_CLOCK_CONFIGURE_GCLK true
/* Configure GCLK generator 0 (Main Clock) */
# define CONF_CLOCK_GCLK_0_ENABLE true
# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_0_PRESCALER 1
# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false
/* Configure GCLK generator 1 */
# define CONF_CLOCK_GCLK_1_ENABLE true
# define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY true
# define CONF_CLOCK_GCLK_1_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_1_PRESCALER 1
# define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE false
/* Configure GCLK generator 2 (RTC) */
# define CONF_CLOCK_GCLK_2_ENABLE true
# define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY true
# define CONF_CLOCK_GCLK_2_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_ULP32K
# define CONF_CLOCK_GCLK_2_PRESCALER 32
# define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE false
/* Configure GCLK generator 3 */
# define CONF_CLOCK_GCLK_3_ENABLE false
# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_3_PRESCALER 1
# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE false
/* Configure GCLK generator 4 */
# define CONF_CLOCK_GCLK_4_ENABLE false
# define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_4_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_4_PRESCALER 1
# define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE false
/* Configure GCLK generator 5 */
# define CONF_CLOCK_GCLK_5_ENABLE false
# define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_5_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_5_PRESCALER 1
# define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE false
/* Configure GCLK generator 6 */
# define CONF_CLOCK_GCLK_6_ENABLE false
# define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_6_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_6_PRESCALER 1
# define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE false
/* Configure GCLK generator 7 */
# define CONF_CLOCK_GCLK_7_ENABLE false
# define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_7_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_7_PRESCALER 1
# define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE false
/* Configure GCLK generator 8 */
# define CONF_CLOCK_GCLK_8_ENABLE false
# define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_8_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_8_PRESCALER 1
# define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE false
#endif /* CONF_CLOCKS_H_INCLUDED */

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/**
* \file
*
* \brief SAM D21 Direct Memory Access Driver Configuration Header
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_DMA_H_INCLUDED
#define CONF_DMA_H_INCLUDED
# define CONF_MAX_USED_CHANNEL_NUM 1
#endif

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_extint.h
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/**
* \file
*
* \brief SAM D21 External Interrupt Driver Configuration Header
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_EXTINT_H_INCLUDED
#define CONF_EXTINT_H_INCLUDED
# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0
#endif

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/**
* \file
*
* \brief SAM D21 SPI configuration
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_SPI_H_INCLUDED
# define CONF_SPI_H_INCLUDED
# define CONF_SPI_MASTER_ENABLE true
# define CONF_SPI_SLAVE_ENABLE false
# define CONF_SPI_TIMEOUT 10000
#endif /* CONF_SPI_H_INCLUDED */

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/**
* \file
*
* \brief SAM D21 Xplained Pro test configuration.
*
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_TEST_H_INCLUDED
#define CONF_TEST_H_INCLUDED
#define CONF_STDIO_USART EDBG_CDC_MODULE
#define CONF_STDIO_MUX_SETTING EDBG_CDC_SERCOM_MUX_SETTING
#define CONF_STDIO_PINMUX_PAD0 EDBG_CDC_SERCOM_PINMUX_PAD0
#define CONF_STDIO_PINMUX_PAD1 EDBG_CDC_SERCOM_PINMUX_PAD1
#define CONF_STDIO_PINMUX_PAD2 EDBG_CDC_SERCOM_PINMUX_PAD2
#define CONF_STDIO_PINMUX_PAD3 EDBG_CDC_SERCOM_PINMUX_PAD3
#define CONF_STDIO_BAUDRATE 38400
#endif /* CONF_TEST_H_INCLUDED */

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_board.h
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/**
* \file
*
* \brief SAM L21 Xplained Pro board configuration.
*
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_BOARD_H_INCLUDED
#define CONF_BOARD_H_INCLUDED
#endif /* CONF_BOARD_H_INCLUDED */

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/**
* \file
*
* \brief SAM L21 Clock configuration
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include <clock.h>
#ifndef CONF_CLOCKS_H_INCLUDED
# define CONF_CLOCKS_H_INCLUDED
/* System clock bus configuration */
# define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT false
# define CONF_CLOCK_FLASH_WAIT_STATES 0
# define CONF_CLOCK_CPU_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_LOW_POWER_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_BACKUP_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
/* SYSTEM_CLOCK_SOURCE_OSC16M configuration - Internal 16MHz oscillator */
# define CONF_CLOCK_OSC16M_FREQ_SEL SYSTEM_OSC16M_4M
# define CONF_CLOCK_OSC16M_ON_DEMAND true
# define CONF_CLOCK_OSC16M_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */
# define CONF_CLOCK_XOSC_ENABLE false
# define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL
# define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY 12000000UL
# define CONF_CLOCK_XOSC_STARTUP_TIME SYSTEM_XOSC_STARTUP_32768
# define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL true
# define CONF_CLOCK_XOSC_ON_DEMAND true
# define CONF_CLOCK_XOSC_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */
# define CONF_CLOCK_XOSC32K_ENABLE false
# define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL
# define CONF_CLOCK_XOSC32K_STARTUP_TIME SYSTEM_XOSC32K_STARTUP_65536
# define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT false
# define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT true
# define CONF_CLOCK_XOSC32K_ON_DEMAND true
# define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */
# define CONF_CLOCK_OSC32K_ENABLE false
# define CONF_CLOCK_OSC32K_STARTUP_TIME SYSTEM_OSC32K_STARTUP_130
# define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT true
# define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT true
# define CONF_CLOCK_OSC32K_ON_DEMAND true
# define CONF_CLOCK_OSC32K_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */
# define CONF_CLOCK_DFLL_ENABLE false
# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN
# define CONF_CLOCK_DFLL_ON_DEMAND false
# define CONF_CLOCK_DFLL_RUN_IN_STANDBY false
/* DFLL open loop mode configuration */
# define CONF_CLOCK_DFLL_FINE_VALUE (0xff / 4)
/* DFLL closed loop mode configuration */
# define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR GCLK_GENERATOR_1
# define CONF_CLOCK_DFLL_MULTIPLY_FACTOR (48000000 / 32768)
# define CONF_CLOCK_DFLL_QUICK_LOCK true
# define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK true
# define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP true
# define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE true
# define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE (0x1f / 4)
# define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE (0xff / 4)
/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */
# define CONF_CLOCK_DPLL_ENABLE false
# define CONF_CLOCK_DPLL_ON_DEMAND true
# define CONF_CLOCK_DPLL_RUN_IN_STANDBY false
# define CONF_CLOCK_DPLL_LOCK_BYPASS false
# define CONF_CLOCK_DPLL_WAKE_UP_FAST false
# define CONF_CLOCK_DPLL_LOW_POWER_ENABLE false
# define CONF_CLOCK_DPLL_LOCK_TIME SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT
# define CONF_CLOCK_DPLL_REFERENCE_CLOCK SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K
# define CONF_CLOCK_DPLL_FILTER SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT
# define CONF_CLOCK_DPLL_PRESCALER SYSTEM_CLOCK_SOURCE_DPLL_DIV_1
# define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY 32768
# define CONF_CLOCK_DPLL_REFERENCE_DIVIDER 1
# define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY 48000000
/* DPLL GCLK reference configuration */
# define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR GCLK_GENERATOR_1
/* DPLL GCLK lock timer configuration */
# define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR GCLK_GENERATOR_1
/* Set this to true to configure the GCLK when running clocks_init. If set to
* false, none of the GCLK generators will be configured in clocks_init(). */
# define CONF_CLOCK_CONFIGURE_GCLK true
/* Configure GCLK generator 0 (Main Clock) */
# define CONF_CLOCK_GCLK_0_ENABLE true
# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M
# define CONF_CLOCK_GCLK_0_PRESCALER 1
# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false
/* Configure GCLK generator 1 */
# define CONF_CLOCK_GCLK_1_ENABLE false
# define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_1_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_XOSC32K
# define CONF_CLOCK_GCLK_1_PRESCALER 1
# define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE false
/* Configure GCLK generator 2 */
# define CONF_CLOCK_GCLK_2_ENABLE false
# define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_2_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M
# define CONF_CLOCK_GCLK_2_PRESCALER 1
# define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE false
/* Configure GCLK generator 3 */
# define CONF_CLOCK_GCLK_3_ENABLE false
# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M
# define CONF_CLOCK_GCLK_3_PRESCALER 1
# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE false
/* Configure GCLK generator 4 */
# define CONF_CLOCK_GCLK_4_ENABLE false
# define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_4_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M
# define CONF_CLOCK_GCLK_4_PRESCALER 1
# define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE false
/* Configure GCLK generator 5 */
# define CONF_CLOCK_GCLK_5_ENABLE false
# define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_5_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M
# define CONF_CLOCK_GCLK_5_PRESCALER 1
# define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE false
/* Configure GCLK generator 6 */
# define CONF_CLOCK_GCLK_6_ENABLE false
# define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_6_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M
# define CONF_CLOCK_GCLK_6_PRESCALER 1
# define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE false
/* Configure GCLK generator 7 */
# define CONF_CLOCK_GCLK_7_ENABLE false
# define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_7_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M
# define CONF_CLOCK_GCLK_7_PRESCALER 1
# define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE false
/* Configure GCLK generator 8 */
# define CONF_CLOCK_GCLK_8_ENABLE false
# define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_8_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M
# define CONF_CLOCK_GCLK_8_PRESCALER 1
# define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE false
#endif /* CONF_CLOCKS_H_INCLUDED */

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/**
* \file
*
* \brief SAM L21 Direct Memory Access Driver Configuration Header
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_DMA_H_INCLUDED
#define CONF_DMA_H_INCLUDED
# define CONF_MAX_USED_CHANNEL_NUM 1
#endif

52
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_extint.h
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@ -1,52 +0,0 @@
/**
* \file
*
* \brief SAM L21 External Interrupt Driver Configuration Header
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_EXTINT_H_INCLUDED
#define CONF_EXTINT_H_INCLUDED
# define EXTINT_CLOCK_SELECTION EXTINT_CLK_GCLK
# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0
#endif

56
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_spi.h
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@ -1,56 +0,0 @@
/**
* \file
*
* \brief SAM L21 SPI configuration
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_SPI_H_INCLUDED
# define CONF_SPI_H_INCLUDED
# define CONF_SPI_MASTER_ENABLE true
# define CONF_SPI_SLAVE_ENABLE false
# define CONF_SPI_TIMEOUT 10000
#endif /* CONF_SPI_H_INCLUDED */

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