From 64072a925e84162c1379aeceb0c5b0397af8ac02 Mon Sep 17 00:00:00 2001
From: JojoS62 <sn2010@onlinehome.de>
Date: Thu, 22 Oct 2020 20:11:15 +0200
Subject: [PATCH] fix for targets with non-modifiable transconductance

---
 targets/TARGET_STM/mbed_overrides.c | 35 ++++++++++++++++-------------
 1 file changed, 20 insertions(+), 15 deletions(-)

diff --git a/targets/TARGET_STM/mbed_overrides.c b/targets/TARGET_STM/mbed_overrides.c
index ff1bb1b8c6..4461d9ffa4 100644
--- a/targets/TARGET_STM/mbed_overrides.c
+++ b/targets/TARGET_STM/mbed_overrides.c
@@ -32,19 +32,24 @@
 int mbed_sdk_inited = 0;
 extern void SetSysClock(void);
 
-#if MBED_CONF_TARGET_LSE_AVAILABLE
-
-// set defaults for LSE drive load level, with exception for F4_g2 MCU
-#if MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL
-#   define LSE_DRIVE_LOAD_LEVEL    MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL
-#else
-#   ifdef RCC_LSE_HIGHDRIVE_MODE
-#       define LSE_DRIVE_LOAD_LEVEL    RCC_LSE_HIGHDRIVE_MODE
-#   else
-#       define LSE_DRIVE_LOAD_LEVEL    RCC_LSEDRIVE_MEDIUMHIGH
-#   endif
+#if defined(RCC_LSE_HIGHDRIVE_MODE) || defined(RCC_LSEDRIVE_HIGH)
+#   define LSE_CONFIG_AVAILABLE
 #endif
 
+// set defaults for LSE drive load level
+#if defined(LSE_CONFIG_AVAILABLE)
+
+#   ifdef MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL
+#       define LSE_DRIVE_LOAD_LEVEL    MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL
+#   else
+#       ifdef RCC_LSE_HIGHDRIVE_MODE
+#           define LSE_DRIVE_LOAD_LEVEL    RCC_LSE_HIGHDRIVE_MODE
+#       else
+#           define LSE_DRIVE_LOAD_LEVEL    RCC_LSEDRIVE_MEDIUMHIGH
+#       endif
+#   endif
+
+
 /**
  * @brief configure the LSE crystal driver load
  * This settings ist target hardware dependend and 
@@ -77,13 +82,13 @@ static void LSEDriveConfig(void) {
 
    // set LSE drive level. Exception only for F4_g2 series
     HAL_PWR_EnableBkUpAccess();
-    #ifdef  __HAL_RCC_LSEDRIVE_CONFIG
+    #if defined(LSE_CONFIG_AVAILABLE)
         __HAL_RCC_LSEDRIVE_CONFIG(LSE_DRIVE_LOAD_LEVEL);
     #else
         HAL_RCCEx_SelectLSEMode(LSE_DRIVE_LOAD_LEVEL);
     #endif
 }
-#endif  // MBED_CONF_TARGET_LSE_AVAILABLE
+#endif  // LSE_CONFIG_AVAILABLE
 
 /**
  * @brief Setup the target board-specific configuration
@@ -174,7 +179,7 @@ void mbed_sdk_init()
 
     /* Configure the System clock source, PLL Multiplier and Divider factors,
        AHB/APBx prescalers and Flash settings */
-#if MBED_CONF_TARGET_LSE_AVAILABLE
+#if defined(LSE_CONFIG_AVAILABLE)
     // LSE maybe used later, but crystal load drive setting is necessary before 
     // enabling LSE
     LSEDriveConfig();
@@ -201,7 +206,7 @@ void mbed_sdk_init()
 
     /* Configure the System clock source, PLL Multiplier and Divider factors,
        AHB/APBx prescalers and Flash settings */
-#if MBED_CONF_TARGET_LSE_AVAILABLE
+#if defined(LSE_CONFIG_AVAILABLE)
     LSEDriveConfig();
 #endif
     SetSysClock();