mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #14578 from jeromecoutant/PR_WB55MMG
STM32 : new DISCO_WB5MMG targetpull/13791/head
Martin Kojtal
GitHub
commit
6330299ac5
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@ -15,8 +15,8 @@ elseif("STM32L4S5xI" IN_LIST MBED_TARGET_LABELS)
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add_subdirectory(TARGET_STM32L4S5xI)
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elseif("STM32L562xx" IN_LIST MBED_TARGET_LABELS)
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add_subdirectory(TARGET_STM32L562xx)
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elseif("STM32WB55xx" IN_LIST MBED_TARGET_LABELS)
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add_subdirectory(TARGET_STM32WB55xx)
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elseif("STM32WB" IN_LIST MBED_TARGET_LABELS)
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add_subdirectory(TARGET_STM32WB)
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endif()
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target_sources(mbed-mbedtls
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@ -3,6 +3,8 @@
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add_subdirectory(TARGET_STM32WB50xx EXCLUDE_FROM_ALL)
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add_subdirectory(TARGET_STM32WB55xx EXCLUDE_FROM_ALL)
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add_subdirectory(TARGET_STM32WB5Mxx EXCLUDE_FROM_ALL)
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add_subdirectory(STM32Cube_FW EXCLUDE_FROM_ALL)
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add_library(mbed-stm32wb INTERFACE)
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@ -51,7 +51,9 @@
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#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
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#define __NVIC_PRIO_BITS 4U /*!< STM32WBxx uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
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#ifndef __FPU_PRESENT
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#define __FPU_PRESENT 1U /*!< FPU present */
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#endif
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/**
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* @}
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*/
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@ -0,0 +1,29 @@
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# Copyright (c) 2020 ARM Limited. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory(TARGET_DISCO_WB5MMG EXCLUDE_FROM_ALL)
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if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
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set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32wb5mxx.S)
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set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32wb5mxx.ld)
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elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
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set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32wb5mxx.S)
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set(LINKER_FILE TOOLCHAIN_ARM/stm32wb5mxx.sct)
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endif()
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add_library(mbed-stm32wb5mxx INTERFACE)
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target_sources(mbed-stm32wb5mxx
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INTERFACE
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${STARTUP_FILE}
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system_clock.c
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)
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target_include_directories(mbed-stm32wb5mxx
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INTERFACE
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.
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)
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mbed_set_linker_script(mbed-stm32wb5mxx ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
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target_link_libraries(mbed-stm32wb5mxx INTERFACE mbed-stm32wb)
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@ -0,0 +1,16 @@
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# Copyright (c) 2020 ARM Limited. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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add_library(mbed-disco-wb5mmg INTERFACE)
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target_sources(mbed-disco-wb5mmg
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INTERFACE
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PeripheralPins.c
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)
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target_include_directories(mbed-disco-wb5mmg
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INTERFACE
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.
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)
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target_link_libraries(mbed-disco-wb5mmg INTERFACE mbed-stm32wb5mxx)
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@ -0,0 +1,274 @@
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/* mbed Microcontroller Library
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* SPDX-License-Identifier: BSD-3-Clause
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******************************************************************************
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*
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* Copyright (c) 2016-2021 STMicroelectronics.
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*
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* Automatically generated from STM32CubeMX/db/mcu/STM32WB5MMGHx.xml
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*/
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#include "PeripheralPins.h"
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#include "mbed_toolchain.h"
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//==============================================================================
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// Notes
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//
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// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
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// HW peripheral instances. You can use them the same way as any other "normal"
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// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
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// pinout image on mbed.org.
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//
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// - The pins which are connected to other components present on the board have
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// the comment "Connected to xxx". The pin function may not work properly in this
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// case. These pins may not be displayed on the board pinout image on mbed.org.
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// Please read the board reference manual and schematic for more information.
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//
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// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
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// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
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//
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//==============================================================================
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const PinList *pinmap_gpio_restricted_pins()
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{
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static const PinName pins[] = {
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PC_0, // connected to LPUART switch
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PB_5, // connected to LPUART switch
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PB_8, // I2C HW Pull-up
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PA_10, // I2C HW Pull-up
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};
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static const PinList pin_list = {
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sizeof(pins) / sizeof(pins[0]),
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pins
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};
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return &pin_list;
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}
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//*** ADC ***
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MBED_WEAK const PinMap PinMap_ADC[] = {
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{PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to ADCx_IN5
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{PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 // Connected to SPI1_SCK
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{PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // Connected to ADCx_IN7
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{PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // Connected to QSPI_BK_SCK
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{PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 // Connected to SPI1_NSS
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{PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // Connected to ADCx_IN10
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{PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // Connected to LPUART1_CTS
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{PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 // Connected to SPI1_MOSI
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{PA_8, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 // Connected to SAI1_CK2
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{PA_9, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 // Connected to SAI1_D2
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{PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 // Connected to LPUART1_RX_MCU
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{PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to ADCx_IN2
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{PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to GPIO_Input
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{PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // Connected to ADCx_IN4
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{PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 // Connected to ADCx_IN13
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{PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 // Connected to ADCx_IN14
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
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{ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
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{ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)},
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{ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
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{NC, NC, 0}
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};
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//*** I2C ***
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MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
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{PA_10, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to I2C1_SDA
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{PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to SPI1_MISO
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// {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to STDIO_UART_RX
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{PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to QSPI_BK_IO0
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{PB_11, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to I2C3_SDA
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{PB_14, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to SPI2_MISO
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{PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to ADCx_IN2
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
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{PA_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to SPI1_MOSI
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{PA_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to SAI1_D2
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// {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to STDIO_UART_TX
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{PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to I2C1_SCL
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{PB_10, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to S_TIM2_CH3
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{PB_13, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to I2C3_SCL
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{PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to LPUART1_RX_MCU
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{NC, NC, 0}
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};
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//*** PWM ***
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// TIM16 cannot be used because already used by the us_ticker
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// (update us_ticker_data.h file if another timer is chosen)
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MBED_WEAK const PinMap PinMap_PWM[] = {
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{PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to ADCx_IN5
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{PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to SPI1_SCK
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{PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to ADCx_IN7
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{PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to QSPI_BK_SCK
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{PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to ADCx_IN10
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// {PA_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // Connected to LPUART1_CTS
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{PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to SPI1_MOSI
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{PA_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // Connected to SPI1_MOSI
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{PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to SAI1_CK2
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{PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to SAI1_D2
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{PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to I2C1_SDA
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{PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to USB_N
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{PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to S_TIM2_CH1
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{PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to T_SWO
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// {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N // Connected to STDIO_UART_TX
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// {PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N // Connected to STDIO_UART_RX
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{PB_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to I2C1_SCL
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// {PB_8, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // Connected to I2C1_SCL
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{PB_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to QSPI_BK_IO0
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{PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // Connected to QSPI_BK_IO0
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{PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to S_TIM2_CH3
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{PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to I2C3_SDA
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{PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to I2C3_SCL
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{PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to SPI2_MISO
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{PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to SPI2_MOSI
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{PD_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to S_TIM1_CH1
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{PD_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to S_TIM1_CH2
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// {PE_0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // Connected to S_TIM16_CH1
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{PE_1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // Connected to DRDY
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{NC, NC, 0}
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};
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//*** SERIAL ***
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MBED_WEAK const PinMap PinMap_UART_TX[] = {
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{PA_2, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ADCx_IN7
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{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to SAI1_D2
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{PB_5, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LPUART1_TX_MCU
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{PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX
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{PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to I2C3_SDA
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{PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ADCx_IN2
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_UART_RX[] = {
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{PA_3, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to QSPI_BK_SCK
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{PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to I2C1_SDA
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{PA_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to USB_P
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{PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX
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{PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to S_TIM2_CH3
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{PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LPUART1_RX_MCU
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_UART_RTS[] = {
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{PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_P
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{PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to T_SWO
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{PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LPUART1_RTS
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_UART_CTS[] = {
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{PA_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LPUART1_CTS
|
||||
{PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_N
|
||||
{PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to SPI1_MISO
|
||||
{PB_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to I2C3_SCL
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** SPI ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
|
||||
{PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SPI1_MOSI
|
||||
{PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to USB_P
|
||||
{PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to LPUART1_TX_MCU
|
||||
{PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to SPI2_MOSI
|
||||
{PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_SPI2)}, // Connected to ADCx_IN2
|
||||
{PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ADCx_IN4
|
||||
{PD_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to GPIO_Input
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
|
||||
{PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to LPUART1_CTS
|
||||
{PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to USB_N
|
||||
{PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SPI1_MISO
|
||||
{PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to SPI2_MISO
|
||||
{PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to GPIO_Input
|
||||
{PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to QSPI_BK_NCS
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
|
||||
{PA_1, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SPI1_SCK
|
||||
{PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ADCx_IN10
|
||||
{PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to SAI1_D2
|
||||
{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to T_SWO
|
||||
{PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to S_TIM2_CH3
|
||||
{PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to I2C3_SCL
|
||||
{PD_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to SPI2_SCK
|
||||
{PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_SPI2)}, // Connected to QSPI_BK_NCS
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
|
||||
{PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SPI1_NSS
|
||||
{PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to S_TIM2_CH1
|
||||
{PB_2, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to GPIO_Input
|
||||
{PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to QSPI_BK_IO0
|
||||
{PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to LPUART1_RTS
|
||||
{PD_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to SPI2_NSS
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** QUADSPI ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = {
|
||||
{PB_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to QSPI_BK_IO0
|
||||
{PD_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to GPIO_Input
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {
|
||||
{PB_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to I2C1_SCL
|
||||
{PD_5, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to QSPI_BK_IO1
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {
|
||||
{PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to SPI1_MOSI
|
||||
{PD_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to QSPI_BK_IO2
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = {
|
||||
{PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to LPUART1_CTS
|
||||
{PD_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to QSPI_BK_IO3
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
|
||||
{PA_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // Connected to QSPI_BK_SCK
|
||||
{PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // Connected to S_TIM2_CH3
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
|
||||
{PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to ADCx_IN7
|
||||
{PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to I2C3_SDA
|
||||
{PD_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_BK_NCS
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** USBDEVICE ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_USB_FS[] = {
|
||||
{PA_11, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM // Connected to USB_N
|
||||
{PA_12, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP // Connected to USB_P
|
||||
// {PA_13, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE // Connected to T_SWDIO
|
||||
// {PC_9, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE // Connected to D/C_DISP
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
|
@ -0,0 +1,196 @@
|
|||
/* mbed Microcontroller Library
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright (c) 2016-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*
|
||||
* Automatically generated from STM32CubeMX/db/mcu/STM32WB5MMGHx.xml
|
||||
*/
|
||||
|
||||
/* MBED TARGET LIST: DISCO_WB5MMG */
|
||||
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "PinNamesTypes.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
ALT0 = 0x100,
|
||||
} ALTx;
|
||||
|
||||
typedef enum {
|
||||
PA_0 = 0x00,
|
||||
PA_1 = 0x01,
|
||||
PA_2 = 0x02,
|
||||
PA_3 = 0x03,
|
||||
PA_4 = 0x04,
|
||||
PA_5 = 0x05,
|
||||
PA_6 = 0x06,
|
||||
PA_7 = 0x07,
|
||||
PA_7_ALT0 = PA_7 | ALT0, // same pin used for alternate HW
|
||||
PA_8 = 0x08,
|
||||
PA_9 = 0x09,
|
||||
PA_10 = 0x0A,
|
||||
PA_11 = 0x0B,
|
||||
PA_12 = 0x0C,
|
||||
PA_13 = 0x0D,
|
||||
PA_14 = 0x0E,
|
||||
PA_15 = 0x0F,
|
||||
PB_2 = 0x12,
|
||||
PB_3 = 0x13,
|
||||
PB_4 = 0x14,
|
||||
PB_5 = 0x15,
|
||||
PB_6 = 0x16,
|
||||
PB_7 = 0x17,
|
||||
PB_8 = 0x18,
|
||||
PB_9 = 0x19,
|
||||
PB_9_ALT0 = PB_9 | ALT0, // same pin used for alternate HW
|
||||
PB_10 = 0x1A,
|
||||
PB_11 = 0x1B,
|
||||
PB_12 = 0x1C,
|
||||
PB_13 = 0x1D,
|
||||
PB_14 = 0x1E,
|
||||
PB_15 = 0x1F,
|
||||
PC_0 = 0x20,
|
||||
PC_1 = 0x21,
|
||||
PC_2 = 0x22,
|
||||
PC_3 = 0x23,
|
||||
PC_4 = 0x24,
|
||||
PC_5 = 0x25,
|
||||
PC_6 = 0x26,
|
||||
PC_7 = 0x27,
|
||||
PC_8 = 0x28,
|
||||
PC_9 = 0x29,
|
||||
PC_10 = 0x2A,
|
||||
PC_11 = 0x2B,
|
||||
PC_12 = 0x2C,
|
||||
PC_13 = 0x2D,
|
||||
PD_0 = 0x30,
|
||||
PD_1 = 0x31,
|
||||
PD_2 = 0x32,
|
||||
PD_3 = 0x33,
|
||||
PD_4 = 0x34,
|
||||
PD_5 = 0x35,
|
||||
PD_6 = 0x36,
|
||||
PD_7 = 0x37,
|
||||
PD_8 = 0x38,
|
||||
PD_9 = 0x39,
|
||||
PD_10 = 0x3A,
|
||||
PD_11 = 0x3B,
|
||||
PD_12 = 0x3C,
|
||||
PD_13 = 0x3D,
|
||||
PD_14 = 0x3E,
|
||||
PD_15 = 0x3F,
|
||||
PE_0 = 0x40,
|
||||
PE_1 = 0x41,
|
||||
PE_2 = 0x42,
|
||||
PE_3 = 0x43,
|
||||
PE_4 = 0x44,
|
||||
PH_0 = 0x70,
|
||||
PH_1 = 0x71,
|
||||
PH_3 = 0x73,
|
||||
|
||||
/**** ADC internal channels ****/
|
||||
|
||||
ADC_TEMP = 0xF0, // Internal pin virtual value
|
||||
ADC_VREF = 0xF1, // Internal pin virtual value
|
||||
ADC_VBAT = 0xF2, // Internal pin virtual value
|
||||
|
||||
#ifdef TARGET_FF_ARDUINO_UNO
|
||||
// Arduino Uno (Rev3) pins
|
||||
ARDUINO_UNO_A0 = PC_3,
|
||||
ARDUINO_UNO_A1 = PA_2,
|
||||
ARDUINO_UNO_A2 = PA_5,
|
||||
ARDUINO_UNO_A3 = PC_1,
|
||||
ARDUINO_UNO_A4 = PC_4,
|
||||
ARDUINO_UNO_A5 = PC_5,
|
||||
ARDUINO_UNO_D0 = PC_0, // connected to LPUART switch
|
||||
ARDUINO_UNO_D1 = PB_5, // connected to LPUART switch
|
||||
ARDUINO_UNO_D2 = PD_12,
|
||||
ARDUINO_UNO_D3 = PD_14,
|
||||
ARDUINO_UNO_D4 = PE_4,
|
||||
ARDUINO_UNO_D5 = PB_10,
|
||||
ARDUINO_UNO_D6 = PE_0,
|
||||
ARDUINO_UNO_D7 = PB_2,
|
||||
ARDUINO_UNO_D8 = PD_13,
|
||||
ARDUINO_UNO_D9 = PD_15,
|
||||
ARDUINO_UNO_D10= PA_4,
|
||||
ARDUINO_UNO_D11= PA_7,
|
||||
ARDUINO_UNO_D12= PB_4,
|
||||
ARDUINO_UNO_D13= PA_1,
|
||||
ARDUINO_UNO_D14= PA_10,
|
||||
ARDUINO_UNO_D15= PB_8,
|
||||
#endif
|
||||
|
||||
// STDIO for console print
|
||||
#ifdef MBED_CONF_TARGET_STDIO_UART_TX
|
||||
CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX,
|
||||
#else
|
||||
CONSOLE_TX = PB_6,
|
||||
#endif
|
||||
#ifdef MBED_CONF_TARGET_STDIO_UART_RX
|
||||
CONSOLE_RX = MBED_CONF_TARGET_STDIO_UART_RX,
|
||||
#else
|
||||
CONSOLE_RX = PB_7,
|
||||
#endif
|
||||
|
||||
/**** USB pins ****/
|
||||
USB_DM = PA_11,
|
||||
USB_DP = PA_12,
|
||||
USB_NOE = PA_13,
|
||||
USB_NOE_ALT0 = PC_9,
|
||||
|
||||
/**** DEBUG pins ****/
|
||||
SYS_JTCK_SWCLK = PA_14,
|
||||
SYS_JTDI = PA_15,
|
||||
SYS_JTDO_SWO = PB_3,
|
||||
SYS_JTMS_SWDIO = PA_13,
|
||||
SYS_JTRST = PB_4,
|
||||
SYS_PVD_IN = PB_7,
|
||||
SYS_TRACECLK = PE_2,
|
||||
SYS_TRACED0 = PD_9,
|
||||
SYS_TRACED1 = PC_10,
|
||||
SYS_TRACED2 = PD_2,
|
||||
SYS_TRACED3 = PC_12,
|
||||
SYS_TRIG_INOUT = PD_10,
|
||||
SYS_WKUP1 = PA_0,
|
||||
SYS_WKUP2 = PC_13,
|
||||
SYS_WKUP3 = PC_12,
|
||||
SYS_WKUP4 = PA_2,
|
||||
SYS_WKUP5 = PC_5,
|
||||
|
||||
/**** QSPI FLASH pins ****/
|
||||
QSPI_FLASH1_IO0 = PB_9,
|
||||
QSPI_FLASH1_IO1 = PD_5,
|
||||
QSPI_FLASH1_IO2 = PD_6,
|
||||
QSPI_FLASH1_IO3 = PD_7,
|
||||
QSPI_FLASH1_SCK = PA_3,
|
||||
QSPI_FLASH1_CSN = PD_3,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
// Standardized LED and button names
|
||||
#define LED1 PA_7 // LD4 is a RGB LED connected to a PWM LED driver // TODO
|
||||
#define BUTTON1 PC_12
|
||||
#define BUTTON2 PC_13
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,323 @@
|
|||
;******************************************************************************
|
||||
;* File Name : startup_stm32wb55xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32WB55xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;*
|
||||
;******************************************************************************
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
|
||||
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
||||
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 Interrupt
|
||||
DCD USB_HP_IRQHandler ; USB High Priority Interrupt
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority Interrupt
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD SAI1_IRQHandler ; SAI Interrupt
|
||||
DCD TSC_IRQHandler ; TSC Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD CRS_IRQHandler ; CRS interrupt
|
||||
DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD LCD_IRQHandler ; LCD Interrupt
|
||||
DCD QUADSPI_IRQHandler ; QUADSPI Interrupt
|
||||
DCD AES1_IRQHandler ; AES1 Interrupt
|
||||
DCD AES2_IRQHandler ; AES2 Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD FPU_IRQHandler ; FPU Interrupt
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_LSECSS_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT USB_HP_IRQHandler [WEAK]
|
||||
EXPORT USB_LP_IRQHandler [WEAK]
|
||||
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
|
||||
EXPORT COMP_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT PKA_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT SAI1_IRQHandler [WEAK]
|
||||
EXPORT TSC_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT CRS_IRQHandler [WEAK]
|
||||
EXPORT PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
|
||||
EXPORT HSEM_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT LCD_IRQHandler [WEAK]
|
||||
EXPORT QUADSPI_IRQHandler [WEAK]
|
||||
EXPORT AES1_IRQHandler [WEAK]
|
||||
EXPORT AES2_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel7_IRQHandler [WEAK]
|
||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_PVM_IRQHandler
|
||||
TAMP_STAMP_LSECSS_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
USB_HP_IRQHandler
|
||||
USB_LP_IRQHandler
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
COMP_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
PKA_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
SAI1_IRQHandler
|
||||
TSC_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
CRS_IRQHandler
|
||||
PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
IPCC_C1_RX_IRQHandler
|
||||
IPCC_C1_TX_IRQHandler
|
||||
HSEM_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
LCD_IRQHandler
|
||||
QUADSPI_IRQHandler
|
||||
AES1_IRQHandler
|
||||
AES2_IRQHandler
|
||||
RNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
DMA2_Channel1_IRQHandler
|
||||
DMA2_Channel2_IRQHandler
|
||||
DMA2_Channel3_IRQHandler
|
||||
DMA2_Channel4_IRQHandler
|
||||
DMA2_Channel5_IRQHandler
|
||||
DMA2_Channel6_IRQHandler
|
||||
DMA2_Channel7_IRQHandler
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
|
||||
; Scatter-Loading Description File
|
||||
;
|
||||
; SPDX-License-Identifier: BSD-3-Clause
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2016-2020 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;*
|
||||
;******************************************************************************
|
||||
|
||||
#include "../cmsis_nvic.h"
|
||||
|
||||
#if !defined(MBED_APP_START)
|
||||
#define MBED_APP_START MBED_ROM_START
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_APP_SIZE)
|
||||
; 768KB FLASH // BLE firmware is being flashed strating from @ 0x080C0000
|
||||
#define MBED_APP_SIZE 0xC0000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
|
||||
/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
|
||||
#if defined(MBED_BOOT_STACK_SIZE)
|
||||
#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
|
||||
#else
|
||||
#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Round up VECTORS_SIZE to 8 bytes */
|
||||
#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
|
||||
|
||||
; RAM_SIZE = 192KB SRAM (0x30000) + Shared mem
|
||||
LR_IROM1 MBED_APP_START MBED_APP_SIZE {
|
||||
|
||||
ER_IROM1 MBED_APP_START MBED_APP_SIZE {
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + 0x30000 - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
|
||||
}
|
||||
|
||||
ARM_LIB_STACK (MBED_RAM_START + 0x30000) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
|
||||
}
|
||||
|
||||
; SRAM2 - Shared memory
|
||||
RW_IRAM2a 0x20030000 0x00002800 { ; RW data
|
||||
*(MAPPING_TABLE)
|
||||
*(MB_MEM1)
|
||||
}
|
||||
|
||||
RW_IRAM2b 0x20038000 0x00005000 { ; RW data
|
||||
*(MB_MEM2)
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,443 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32wb55xx_cm4.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32WB55xx devices vector table GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* start address for the .MB_MEM2 section. defined in linker script */
|
||||
.word _sMB_MEM2
|
||||
/* end address for the .MB_MEM2 section. defined in linker script */
|
||||
.word _eMB_MEM2
|
||||
|
||||
/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
|
||||
.macro INIT_BSS start, end
|
||||
ldr r0, =\start
|
||||
ldr r1, =\end
|
||||
movs r3, #0
|
||||
bl LoopFillZerobss
|
||||
.endm
|
||||
|
||||
/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
|
||||
.macro INIT_DATA start, end, src
|
||||
ldr r0, =\start
|
||||
ldr r1, =\end
|
||||
ldr r2, =\src
|
||||
movs r3, #0
|
||||
bl LoopCopyDataInit
|
||||
.endm
|
||||
|
||||
.section .text.data_initializers
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
bx lr
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r0]
|
||||
adds r0, r0, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r0, r1
|
||||
bcc FillZerobss
|
||||
bx lr
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
INIT_DATA _sdata, _edata, _sidata
|
||||
|
||||
/* Zero fill the bss segments. */
|
||||
INIT_BSS _sbss, _ebss
|
||||
INIT_BSS _sMB_MEM2, _eMB_MEM2
|
||||
|
||||
bl _start
|
||||
bx lr
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex-M4. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_PVM_IRQHandler
|
||||
.word TAMP_STAMP_LSECSS_IRQHandler
|
||||
.word RTC_WKUP_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word DMA1_Channel1_IRQHandler
|
||||
.word DMA1_Channel2_IRQHandler
|
||||
.word DMA1_Channel3_IRQHandler
|
||||
.word DMA1_Channel4_IRQHandler
|
||||
.word DMA1_Channel5_IRQHandler
|
||||
.word DMA1_Channel6_IRQHandler
|
||||
.word DMA1_Channel7_IRQHandler
|
||||
.word ADC1_IRQHandler
|
||||
.word USB_HP_IRQHandler
|
||||
.word USB_LP_IRQHandler
|
||||
.word C2SEV_PWR_C2H_IRQHandler
|
||||
.word COMP_IRQHandler
|
||||
.word EXTI9_5_IRQHandler
|
||||
.word TIM1_BRK_IRQHandler
|
||||
.word TIM1_UP_TIM16_IRQHandler
|
||||
.word TIM1_TRG_COM_TIM17_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word PKA_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word I2C3_EV_IRQHandler
|
||||
.word I2C3_ER_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word SPI2_IRQHandler
|
||||
.word USART1_IRQHandler
|
||||
.word LPUART1_IRQHandler
|
||||
.word SAI1_IRQHandler
|
||||
.word TSC_IRQHandler
|
||||
.word EXTI15_10_IRQHandler
|
||||
.word RTC_Alarm_IRQHandler
|
||||
.word CRS_IRQHandler
|
||||
.word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
.word IPCC_C1_RX_IRQHandler
|
||||
.word IPCC_C1_TX_IRQHandler
|
||||
.word HSEM_IRQHandler
|
||||
.word LPTIM1_IRQHandler
|
||||
.word LPTIM2_IRQHandler
|
||||
.word LCD_IRQHandler
|
||||
.word QUADSPI_IRQHandler
|
||||
.word AES1_IRQHandler
|
||||
.word AES2_IRQHandler
|
||||
.word RNG_IRQHandler
|
||||
.word FPU_IRQHandler
|
||||
.word DMA2_Channel1_IRQHandler
|
||||
.word DMA2_Channel2_IRQHandler
|
||||
.word DMA2_Channel3_IRQHandler
|
||||
.word DMA2_Channel4_IRQHandler
|
||||
.word DMA2_Channel5_IRQHandler
|
||||
.word DMA2_Channel6_IRQHandler
|
||||
.word DMA2_Channel7_IRQHandler
|
||||
.word DMAMUX1_OVR_IRQHandler
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_LSECSS_IRQHandler
|
||||
.thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_IRQHandler
|
||||
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_HP_IRQHandler
|
||||
.thumb_set USB_HP_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_LP_IRQHandler
|
||||
.thumb_set USB_LP_IRQHandler,Default_Handler
|
||||
|
||||
.weak C2SEV_PWR_C2H_IRQHandler
|
||||
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMP_IRQHandler
|
||||
.thumb_set COMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_TIM16_IRQHandler
|
||||
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_TIM17_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak PKA_IRQHandler
|
||||
.thumb_set PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TSC_IRQHandler
|
||||
.thumb_set TSC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
.thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_RX_IRQHandler
|
||||
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_TX_IRQHandler
|
||||
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM_IRQHandler
|
||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LCD_IRQHandler
|
||||
.thumb_set LCD_IRQHandler,Default_Handler
|
||||
|
||||
.weak QUADSPI_IRQHandler
|
||||
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES1_IRQHandler
|
||||
.thumb_set AES1_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES2_IRQHandler
|
||||
.thumb_set AES2_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel1_IRQHandler
|
||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel2_IRQHandler
|
||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel3_IRQHandler
|
||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel4_IRQHandler
|
||||
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel5_IRQHandler
|
||||
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel6_IRQHandler
|
||||
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel7_IRQHandler
|
||||
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,220 @@
|
|||
/* Linker script to configure memory regions. */
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016-2020 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include "../cmsis_nvic.h"
|
||||
|
||||
|
||||
#if !defined(MBED_APP_START)
|
||||
#define MBED_APP_START MBED_ROM_START
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_APP_SIZE)
|
||||
/* 768KB FLASH - BLE firmware is being flashed strating from @ 0x080C0000 */
|
||||
#define MBED_APP_SIZE 768K
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
|
||||
/* This value is normally defined by the tools
|
||||
to 0x1000 for bare metal and 0x400 for RTOS */
|
||||
#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
|
||||
/* Round up VECTORS_SIZE to 8 bytes */
|
||||
#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)
|
||||
|
||||
/* RAM_SIZE = 192KB SRAM (0x30000) + Shared mem */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
|
||||
RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = 0x30000 - VECTORS_SIZE
|
||||
RAM2a (rw) : ORIGIN = 0x20030000, LENGTH = 10K
|
||||
RAM2b (rw) : ORIGIN = 0x20038000, LENGTH = 20K
|
||||
}
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
* _estack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
__etext = .;
|
||||
_sidata = .;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
_sdata = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(8);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(8);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
_edata = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
/* Uninitialized data section
|
||||
* This region is not initialized by the C/C++ library and can be used to
|
||||
* store state across soft reboots. */
|
||||
.uninitialized (NOLOAD):
|
||||
{
|
||||
. = ALIGN(32);
|
||||
__uninitialized_start = .;
|
||||
*(.uninitialized)
|
||||
KEEP(*(.keep.uninitialized))
|
||||
. = ALIGN(32);
|
||||
__uninitialized_end = .;
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__bss_start__ = .;
|
||||
_sbss = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(8);
|
||||
__bss_end__ = .;
|
||||
_ebss = .;
|
||||
} > RAM
|
||||
|
||||
.heap (COPY):
|
||||
{
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
*(.heap*)
|
||||
. = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE;
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy (COPY):
|
||||
{
|
||||
*(.stack*)
|
||||
} > RAM
|
||||
|
||||
.ble_stby_mem (NOLOAD) :
|
||||
{
|
||||
*(MAPPING_TABLE);
|
||||
*(MB_MEM1);
|
||||
} >RAM2a
|
||||
|
||||
.ble_shared_no_ret (NOLOAD) :
|
||||
{
|
||||
_sMB_MEM2 = . ;
|
||||
*(MB_MEM2);
|
||||
_eMB_MEM2 = . ;
|
||||
} >RAM2b
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
_estack = __StackTop;
|
||||
__StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE;
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
}
|
||||
|
|
@ -0,0 +1,517 @@
|
|||
;******************************************************************************
|
||||
;* File Name : startup_stm32wb55xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : M4 core vector table of the STM32WB55xx devices for the
|
||||
;* IAR (EWARM) toolchain.
|
||||
;*
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;*
|
||||
;******************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
||||
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 Interrupt
|
||||
DCD USB_HP_IRQHandler ; USB High Priority Interrupt
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority Interrupt
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD SAI1_IRQHandler ; SAI Interrupt
|
||||
DCD TSC_IRQHandler ; TSC Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD CRS_IRQHandler ; CRS interrupt
|
||||
DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD LCD_IRQHandler ; LCD Interrupt
|
||||
DCD QUADSPI_IRQHandler ; QUADSPI Interrupt
|
||||
DCD AES1_IRQHandler ; AES1 Interrupt
|
||||
DCD AES2_IRQHandler ; AES2 Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD FPU_IRQHandler ; FPU Interrupt
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_PVM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_PVM_IRQHandler
|
||||
B PVD_PVM_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMP_STAMP_LSECSS_IRQHandler
|
||||
B TAMP_STAMP_LSECSS_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK ADC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC1_IRQHandler
|
||||
B ADC1_IRQHandler
|
||||
|
||||
PUBWEAK USB_HP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USB_HP_IRQHandler
|
||||
B USB_HP_IRQHandler
|
||||
|
||||
PUBWEAK USB_LP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USB_LP_IRQHandler
|
||||
B USB_LP_IRQHandler
|
||||
|
||||
PUBWEAK C2SEV_PWR_C2H_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
B C2SEV_PWR_C2H_IRQHandler
|
||||
|
||||
PUBWEAK COMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
COMP_IRQHandler
|
||||
B COMP_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_5_IRQHandler
|
||||
B EXTI9_5_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_BRK_IRQHandler
|
||||
B TIM1_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_TIM16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
B TIM1_UP_TIM16_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
B TIM1_TRG_COM_TIM17_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK PKA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PKA_IRQHandler
|
||||
B PKA_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_EV_IRQHandler
|
||||
B I2C3_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_ER_IRQHandler
|
||||
B I2C3_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
PUBWEAK SAI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SAI1_IRQHandler
|
||||
B SAI1_IRQHandler
|
||||
|
||||
PUBWEAK TSC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TSC_IRQHandler
|
||||
B TSC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK CRS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CRS_IRQHandler
|
||||
B CRS_IRQHandler
|
||||
|
||||
PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_RX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_RX_IRQHandler
|
||||
B IPCC_C1_RX_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_TX_IRQHandler
|
||||
B IPCC_C1_TX_IRQHandler
|
||||
|
||||
PUBWEAK HSEM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HSEM_IRQHandler
|
||||
B HSEM_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK LCD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LCD_IRQHandler
|
||||
B LCD_IRQHandler
|
||||
|
||||
PUBWEAK QUADSPI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
QUADSPI_IRQHandler
|
||||
B QUADSPI_IRQHandler
|
||||
|
||||
PUBWEAK AES1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES1_IRQHandler
|
||||
B AES1_IRQHandler
|
||||
|
||||
PUBWEAK AES2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES2_IRQHandler
|
||||
B AES2_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel1_IRQHandler
|
||||
B DMA2_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel2_IRQHandler
|
||||
B DMA2_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel3_IRQHandler
|
||||
B DMA2_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel4_IRQHandler
|
||||
B DMA2_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel5_IRQHandler
|
||||
B DMA2_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel6_IRQHandler
|
||||
B DMA2_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel7_IRQHandler
|
||||
B DMA2_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK DMAMUX1_OVR_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
B DMAMUX1_OVR_IRQHandler
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
/* Linker script to configure memory regions.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016-2020 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* Device specific values */
|
||||
|
||||
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
|
||||
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0xC0000; }
|
||||
|
||||
/* [ROM = 768kb = 0xC0000] */
|
||||
define symbol __intvec_start__ = MBED_APP_START;
|
||||
define symbol __region_ROM_start__ = MBED_APP_START;
|
||||
define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
|
||||
|
||||
/* [RAM1 = 192kb = 0x30000] */
|
||||
/* Total: 79 vectors = 316 bytes (0x13C) to be reserved in RAM */
|
||||
define symbol __NVIC_start__ = 0x20000000;
|
||||
define symbol __NVIC_end__ = 0x2000013F;
|
||||
define symbol __region_RAM_start__ = 0x20000140; /* Aligned on 8 bytes */
|
||||
define symbol __region_RAM_end__ = 0x2002FFFF;
|
||||
/* [RAM2aRet = 10kb = 0x2800] */
|
||||
define symbol __ICFEDIT_region_RAM2aRet_SHARED_start__ = 0x20030000;
|
||||
define symbol __ICFEDIT_region_RAM2aRet_SHARED_end__ = 0x200327FF;
|
||||
/* [RAM2bRet = 20kb = 0x5000] */
|
||||
define symbol __ICFEDIT_region_RAM2b_SHARED_start__ = 0x20038000;
|
||||
define symbol __ICFEDIT_region_RAM2b_SHARED_end__ = 0x2003CFFF;
|
||||
|
||||
/* Memory regions */
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
|
||||
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
|
||||
define region RAM2aRet_SHARED_region = mem:[from __ICFEDIT_region_RAM2aRet_SHARED_start__ to __ICFEDIT_region_RAM2aRet_SHARED_end__];
|
||||
define region RAM2b_SHARED_region = mem:[from __ICFEDIT_region_RAM2b_SHARED_start__ to __ICFEDIT_region_RAM2b_SHARED_end__];
|
||||
|
||||
if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
|
||||
/* This value is normally defined by the tools
|
||||
to 0x1000 for bare metal and 0x400 for RTOS */
|
||||
define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400;
|
||||
}
|
||||
|
||||
/* Stack and Heap */
|
||||
define symbol __size_cstack__ = MBED_CONF_TARGET_BOOT_STACK_SIZE;
|
||||
define symbol __size_heap__ = 0x10000;
|
||||
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __size_heap__ { };
|
||||
define block STACKHEAP with fixed order { block HEAP, block CSTACK };
|
||||
|
||||
initialize by copy with packing = zeros { readwrite };
|
||||
do not initialize { section .noinit,
|
||||
section MAPPING_TABLE,
|
||||
section MB_MEM1,
|
||||
section MB_MEM2
|
||||
};
|
||||
|
||||
place at address mem:__intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite, block STACKHEAP };
|
||||
|
||||
place in RAM2aRet_SHARED_region { first section MAPPING_TABLE};
|
||||
place in RAM2aRet_SHARED_region { section MB_MEM1};
|
||||
place in RAM2b_SHARED_region { section MB_MEM2};
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/* mbed Microcontroller Library
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016-2020 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
#if !defined(MBED_ROM_START)
|
||||
#define MBED_ROM_START 0x8000000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_ROM_SIZE)
|
||||
#define MBED_ROM_SIZE 0x100000 // 1.0 MB
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_RAM_START)
|
||||
#define MBED_RAM_START 0x20000000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_RAM_SIZE)
|
||||
#define MBED_RAM_SIZE 0x40000 // 256 KB
|
||||
#endif
|
||||
|
||||
#define NVIC_NUM_VECTORS 79
|
||||
#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2019 ARM Limited
|
||||
* Copyright (c) 2019 STMicroelectronics
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* This file configures the system clock as follows:
|
||||
*-----------------------------------------------------------------------------
|
||||
* System clock source | HSE (external 32 MHz clock)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(MHz) | 32
|
||||
* AHBCLK (MHz) | 32
|
||||
* APB1CLK (MHz) | 32
|
||||
* APB2CLK (MHz) | 32
|
||||
* USB capable | YES
|
||||
*-----------------------------------------------------------------------------
|
||||
**/
|
||||
|
||||
#include "stm32wbxx.h"
|
||||
#include "mbed_error.h"
|
||||
#include "stm32wbxx_ll_hsem.h"
|
||||
#include "otp.h"
|
||||
|
||||
|
||||
static void Config_HSE(void)
|
||||
{
|
||||
OTP_ID0_t *p_otp;
|
||||
|
||||
/**
|
||||
* Read HSE_Tuning from OTP
|
||||
*/
|
||||
p_otp = (OTP_ID0_t *) OTP_Read(0);
|
||||
if (p_otp) {
|
||||
LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
MBED_WEAK void SetSysClock(void)
|
||||
{
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
|
||||
__HAL_RCC_HSEM_CLK_ENABLE();
|
||||
|
||||
/* This prevents the CPU2 (M0+) to configure RCC */
|
||||
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID));
|
||||
|
||||
Config_HSE();
|
||||
|
||||
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
|
||||
|
||||
/* This prevents the CPU2 (M0+) to disable the HSI48 oscillator */
|
||||
while (LL_HSEM_1StepLock(HSEM, CFG_HW_CLK48_CONFIG_SEMID));
|
||||
|
||||
/* Initializes the CPU, AHB and APB busses clocks */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
||||
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
error("HAL_RCC_OscConfig error\n");
|
||||
}
|
||||
|
||||
/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
*/
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2
|
||||
| RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
|
||||
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
||||
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
|
||||
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
|
||||
error("HAL_RCC_ClockConfig error\n");
|
||||
}
|
||||
|
||||
/* Initializes the peripherals clocks */
|
||||
/* RNG needs to be configured like in M0 core, i.e. with HSI48 */
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB;
|
||||
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
|
||||
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
|
||||
PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
|
||||
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
|
||||
PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
|
||||
error("HAL_RCCEx_PeriphCLKConfig error\n");
|
||||
}
|
||||
|
||||
LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
|
||||
LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
|
||||
// LL_PWR_SMPS_Enable();
|
||||
|
||||
/* Select HSI as system clock source after Wake Up from Stop mode */
|
||||
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
|
||||
|
||||
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0);
|
||||
}
|
||||
|
|
@ -4216,6 +4216,31 @@
|
|||
],
|
||||
"device_name": "STM32WB55RGVx"
|
||||
},
|
||||
"MCU_STM32WB5Mxx": {
|
||||
"inherits": [
|
||||
"MCU_STM32WB"
|
||||
],
|
||||
"public": false,
|
||||
"extra_labels_add": [
|
||||
"STM32WB5Mxx"
|
||||
],
|
||||
"macros_add": [
|
||||
"STM32WB5Mxx",
|
||||
"MBEDTLS_CONFIG_HW_SUPPORT"
|
||||
]
|
||||
},
|
||||
"DISCO_WB5MMG": {
|
||||
"inherits": [
|
||||
"MCU_STM32WB5Mxx"
|
||||
],
|
||||
"supported_form_factors": [
|
||||
"ARDUINO_UNO"
|
||||
],
|
||||
"detect_code": [
|
||||
"0884"
|
||||
],
|
||||
"device_name": "STM32WB55VGYx"
|
||||
},
|
||||
"MCU_STM32WL": {
|
||||
"inherits": [
|
||||
"MCU_STM32"
|
||||
|
|
|
|||
Loading…
Reference in New Issue