diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_def.h index 01f5b99771..e8050fc752 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_def.h @@ -203,3 +203,4 @@ typedef enum #endif /* ___STM32L0xx_HAL_DEF */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.c index 91fde8d78d..d99695721c 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.c @@ -348,10 +348,6 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); -/* Private functions to centralize the enable/disable of Interrupts */ -static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); -static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); - /* Private functions to flush TXDR register */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); @@ -2158,10 +2154,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - /* Prepare transfer parameters */ - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; @@ -2600,7 +2592,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; - hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); + hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); // MBED commit 23926a2418 hi2c->XferISR = I2C_Master_ISR_IT; /* If size > MAX_NBYTE_SIZE, use reload mode */ @@ -2615,12 +2607,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, xfermode = hi2c->XferOptions; } + // MBED commit 23926a2418 /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) - { - xferrequest = I2C_NO_STARTSTOP; - } + //if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + //{ + // xferrequest = I2C_NO_STARTSTOP; + //} /* Send Slave Address and set NBYTES to write */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); @@ -2673,7 +2666,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; - hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); + hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); // MBED commit 23926a2418 hi2c->XferISR = I2C_Master_ISR_IT; /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ @@ -2688,12 +2681,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, xfermode = hi2c->XferOptions; } + // MBED commit 23926a2418 /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) - { - xferrequest = I2C_NO_STARTSTOP; - } + //if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + //{ + // xferrequest = I2C_NO_STARTSTOP; + //} /* Send Slave Address and set NBYTES to read */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); @@ -2983,13 +2977,6 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* I2C events treatment -------------------------------------*/ if (hi2c->XferISR != NULL) - { - hi2c->XferISR(hi2c, itflags, itsources); - uint32_t itflags = READ_REG(hi2c->Instance->ISR); - uint32_t itsources = READ_REG(hi2c->Instance->CR1); - - /* I2C events treatment -------------------------------------*/ - if(hi2c->XferISR != NULL) { hi2c->XferISR(hi2c, itflags, itsources); } @@ -3584,11 +3571,6 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); } - else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, ITFlags); - } /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -4794,79 +4776,6 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr return HAL_OK; } -/** - * @brief Manage the disabling of Interrupts. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) -{ - uint32_t tmpisr = 0U; - - if((hi2c->XferISR == I2C_Master_ISR_DMA) || \ - (hi2c->XferISR == I2C_Slave_ISR_DMA)) - { - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Enable ERR, STOP, NACK and ADDR interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) - { - /* Enable ERR and NACK interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; - } - - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - - if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= I2C_IT_TCI; - } - } - else - { - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Enable ERR, STOP, NACK, and ADDR interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) - { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; - } - - if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) - { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; - } - - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - } - - /* Enable interrupts only at the end */ - /* to avoid the risk of I2C interrupt handle execution before */ - /* all interrupts requested done */ - __HAL_I2C_ENABLE_IT(hi2c, tmpisr); - - return HAL_OK; -} - /** * @brief Manage the disabling of Interrupts. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.h index 66f5ded5fb..e8d14e187a 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.h @@ -225,8 +225,6 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t ErrorCode; /*!< I2C Error code */ - __IO uint32_t ErrorCode; /*!< I2C Error code */ - __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ } I2C_HandleTypeDef; /** @@ -621,73 +619,6 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /* Private macros ------------------------------------------------------------*/ /** @defgroup I2C_Private_Macro I2C Private Macros - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2C_Private_Macro I2C Private Macros - * @{ - */ - -#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ - ((MODE) == I2C_ADDRESSINGMODE_10BIT)) - -#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) - -#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ - ((MASK) == I2C_OA2_MASK01) || \ - ((MASK) == I2C_OA2_MASK02) || \ - ((MASK) == I2C_OA2_MASK03) || \ - ((MASK) == I2C_OA2_MASK04) || \ - ((MASK) == I2C_OA2_MASK05) || \ - ((MASK) == I2C_OA2_MASK06) || \ - ((MASK) == I2C_OA2_MASK07)) - -#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ - ((CALL) == I2C_GENERALCALL_ENABLE)) - -#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ - ((STRETCH) == I2C_NOSTRETCH_ENABLE)) - -#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ - ((SIZE) == I2C_MEMADD_SIZE_16BIT)) - -#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ - ((MODE) == I2C_AUTOEND_MODE) || \ - ((MODE) == I2C_SOFTEND_MODE)) - -#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ - ((REQUEST) == I2C_GENERATE_START_READ) || \ - ((REQUEST) == I2C_GENERATE_START_WRITE) || \ - ((REQUEST) == I2C_NO_STARTSTOP)) - -#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ - ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ - ((REQUEST) == I2C_NEXT_FRAME) || \ - ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ - ((REQUEST) == I2C_LAST_FRAME)) - -#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) - -#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U) -#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) -#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) -#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1) -#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2) - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) - -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) -#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) - -#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) -/** - * @} - */ - -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Functions I2C Private Functions * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_spi.c index 9ef6dcd9f1..97cfd49e66 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_spi.c @@ -167,12 +167,13 @@ * @{ */ #define SPI_TIMEOUT_VALUE 10U -#define SPI_DEFAULT_TIMEOUT 100U +#define SPI_DEFAULT_TIMEOUT 100U // MBED commit 64a037cc /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +// MBED commit 64a037cc static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart); static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); @@ -1026,6 +1027,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; + // MBED commit 64a037cc /* Set the function for IT treatment */ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) { @@ -1109,6 +1111,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; + // MBED commit 64a037cc /* Set the function for IT treatment */ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) { @@ -1216,6 +1219,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p hspi->RxXferSize = Size; hspi->RxXferCount = Size; + // MBED commit 64a037cc /* Set the function for IT treatment */ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) { @@ -1861,6 +1865,8 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) * @{ */ +// MBED commit 64a037cc + /** * @brief DMA SPI transmit process complete callback * @param hdma: pointer to a DMA_HandleTypeDef structure that contains @@ -2210,6 +2216,7 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin * @} */ +// MBED commit 64a037cc /** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains