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Merge pull request #12828 from dustin-crossman/pr/update-cysbsyskit_01 

Update CYSBSYSKIT_01
pull/12841/head
Martin Kojtal 2020-04-21 10:13:38 +02:00 committed by GitHub
parent aec6303437 d9655da2e8
commit 6111b8dfcc
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
24 changed files with 1397 additions and 347 deletions
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45
features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.cpp
View File

@ -32,14 +32,16 @@
/** @file
* Provides SCL interface functions to be used with WiFiInterface or NetworkInterface Objects
*/
#define MIN_SSID_LENGTH (0)
#define MIN_PASSWORD_LENGTH (0)
struct scl_tx_nw_credentials {
struct scl_tx_net_credentials {
nsapi_security_t network_security_type;
int ssid_len;
int pass_len;
const char *network_ssid;
const char *network_passphrase;
} scl_tx_nw_credentials_t;
} scl_tx_network_credentials;
network_params_t network_parameter;
@ -177,20 +179,24 @@ nsapi_error_t SclSTAInterface::connect()
nsapi_error_t interface_status;
uint32_t connection_status = 0;
scl_tx_nw_credentials_t.network_ssid = _ssid;
if (strlen(_ssid) < MAX_SSID_LENGTH) {
scl_tx_nw_credentials_t.ssid_len = strlen(_ssid);
scl_tx_network_credentials.network_ssid = _ssid;
if ((strlen(_ssid) < MAX_SSID_LENGTH) && (strlen(_ssid) > MIN_SSID_LENGTH)) {
scl_tx_network_credentials.ssid_len = strlen(_ssid);
} else {
return NSAPI_ERROR_PARAMETER;
}
scl_tx_nw_credentials_t.network_passphrase = _pass;
if (strlen(_pass) < MAX_PASSWORD_LENGTH) {
scl_tx_nw_credentials_t.pass_len = strlen(_pass);
scl_tx_network_credentials.network_passphrase = _pass;
if (((strlen(_pass) < MAX_PASSWORD_LENGTH) && (strlen(_pass) > MIN_PASSWORD_LENGTH)) || (_security == NSAPI_SECURITY_NONE)) {
scl_tx_network_credentials.pass_len = strlen(_pass);
} else {
return NSAPI_ERROR_PARAMETER;
}
scl_tx_nw_credentials_t.network_security_type = _security;
scl_tx_network_credentials.network_security_type = _security;
ret_val = scl_send_data(SCL_TX_CONNECT, (char *)&scl_tx_nw_credentials_t, TIMER_DEFAULT_VALUE);
ret_val = scl_send_data(SCL_TX_CONNECT, (char *)&scl_tx_network_credentials, TIMER_DEFAULT_VALUE);
if (ret_val == SCL_SUCCESS) {
SCL_LOG(("wifi provisioning in progress"));
SCL_LOG(("wifi provisioning in progress\r\n"));
}
network_parameter.connection_status = NSAPI_STATUS_DISCONNECTED;
@ -230,7 +236,9 @@ nsapi_error_t SclSTAInterface::connect()
network_parameter.gateway,
DEFAULT_STACK);
if (interface_status == NSAPI_ERROR_OK) {
scl_send_data(SCL_TX_CONNECTION_STATUS, (char *)&connection_status, TIMER_DEFAULT_VALUE);
}
return interface_status;
}
@ -246,6 +254,8 @@ nsapi_error_t SclSTAInterface::disconnect()
{
scl_result_t ret_val;
nsapi_error_t disconnect_status;
uint32_t delay_timeout = 0;
ret_val = scl_send_data(SCL_TX_DISCONNECT, (char *)&disconnect_status, TIMER_DEFAULT_VALUE);
if (ret_val == SCL_ERROR) {
@ -253,7 +263,18 @@ nsapi_error_t SclSTAInterface::disconnect()
}
if (!_interface) {
return NSAPI_STATUS_DISCONNECTED;
return NSAPI_ERROR_NO_CONNECTION;
}
// block till disconnected from network
while ((network_parameter.connection_status != NSAPI_STATUS_DISCONNECTED) && delay_timeout < NW_DISCONNECT_TIMEOUT) {
ret_val = scl_get_nw_parameters(&network_parameter);
wait_us(NW_DELAY_TIME_US);
delay_timeout++;
}
if (delay_timeout >= NW_DISCONNECT_TIMEOUT) {
return NSAPI_ERROR_TIMEOUT;
}
// bring down

13
features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.cpp
View File

@ -89,8 +89,11 @@ void SCL_EMAC::power_down()
bool SCL_EMAC::power_up()
{
if (!powered_up) {
if (scl_wifi_on() != true) {
SCL_LOG(("returning False in scl_wifi_on()\n"));
#ifdef MBED_TEST_MODE
scl_init();
#endif
if (!scl_wifi_on()) {
SCL_LOG(("WiFi failed to turn on\r\n"));
return false;
}
powered_up = true;
@ -109,10 +112,9 @@ bool SCL_EMAC::get_hwaddr(uint8_t *addr) const
memcpy(addr, mac.octet, sizeof(mac.octet));
return true;
} else {
SCL_LOG(("return False in SCL_EMAC::gethwaddr\n"));
SCL_LOG(("Unable to get MAC address\r\n"));
return false;
}
}
void SCL_EMAC::set_hwaddr(const uint8_t *addr)
@ -150,7 +152,8 @@ bool SCL_EMAC::link_out(emac_mem_buf_t *buf)
if (buf == NULL) {
return false;
}
retval = scl_network_send_ethernet_data(scl_tx_data);
retval = scl_network_send_ethernet_data(scl_tx_data); //Buffer is copied on Network Processor
if (retval != SCL_SUCCESS) {
return false;
}

1
targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_common.h
View File

@ -15,6 +15,7 @@
* limitations under the License.
*/
/** @file scl_common.h
* Defines common data types used in SCL
*/

4
targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_ipc.h
View File

@ -53,6 +53,10 @@ extern "C"
* Default timeout value (in seconds) for Wi-Fi connection
*/
#define NW_CONNECT_TIMEOUT (30)
/**
* Default timeout value (in seconds) for Wi-Fi disconnection
*/
#define NW_DISCONNECT_TIMEOUT (30)
/**
* Default interval (in micro seconds) for polling the Network Processor
*/

44
targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/IPC/scl_ipc.c
View File

@ -15,6 +15,7 @@
* limitations under the License.
*/
/** @file
* Provides SCL functionality to communicate with Network Processor
*/
@ -40,6 +41,7 @@
#define DELAY_TIME (1000)
#define SEMAPHORE_MAXCOUNT (1)
#define SEMAPHORE_INITCOUNT (0)
#define INTIAL_VALUE (0)
/******************************************************
** Function Declarations
*******************************************************/
@ -55,13 +57,13 @@ scl_result_t scl_init(void);
* Variables Definitions
*****************************************************/
/* Structure of SCL thread info
* scl_thread_quit_flag: flag used to determine if thread is to be quit
* scl_inited: flag used to determine if thread is started
* scl_thread: variable for thread handle
* scl_thread_quit_flag: flag used to determine if thread is to be quit
* scl_thread_stack_start: pointer to start of thread stack
* scl_thread: variable for thread handle
* scl_rx_ready: semaphore for blocking the thread
* scl_thread_stack_size: size of thread stack
* scl_thread_priority: priority of thread
* scl_rx_ready: semaphore for blocking the thread
*/
struct scl_thread_info_t {
volatile scl_bool_t scl_inited;
@ -113,9 +115,10 @@ static void scl_config(void)
*/
static scl_result_t scl_thread_init(void)
{
cy_rslt_t retval, tmp = 0;
cy_rslt_t retval = CY_RSLT_SUCCESS;
cy_rslt_t tmp = INTIAL_VALUE;
memset(&g_scl_thread_info, 0, sizeof(g_scl_thread_info));
g_scl_thread_info.scl_thread_stack_start = (uint8_t *) malloc(SCL_THREAD_STACK_SIZE);;
g_scl_thread_info.scl_thread_stack_start = (uint8_t *) malloc(SCL_THREAD_STACK_SIZE);
g_scl_thread_info.scl_thread_stack_size = (uint32_t) SCL_THREAD_STACK_SIZE;
g_scl_thread_info.scl_thread_priority = (cy_thread_priority_t) SCL_THREAD_PRIORITY;
@ -141,7 +144,7 @@ static scl_result_t scl_thread_init(void)
scl_result_t scl_init(void)
{
scl_result_t retval = SCL_SUCCESS;
uint32_t configuration_parameters = 0;
uint32_t configuration_parameters = INTIAL_VALUE;
#ifdef MBED_CONF_TARGET_NP_CLOUD_DISABLE
configuration_parameters = (MBED_CONF_TARGET_NP_CLOUD_DISABLE << 1);
#else
@ -152,12 +155,12 @@ scl_result_t scl_init(void)
#else
configuration_parameters |= false;
#endif
//SCL_LOG("configuration_parameters = %lu\n", configuration_parameters);
//SCL_LOG("configuration_parameters = %lu\r\n", configuration_parameters);
scl_config();
if (g_scl_thread_info.scl_inited != SCL_TRUE) {
retval = scl_thread_init();
if (retval != SCL_SUCCESS) {
SCL_LOG(("Thread init failed\n"));
SCL_LOG(("Thread init failed\r\n"));
return SCL_ERROR;
} else {
retval = scl_send_data(SCL_TX_CONFIG_PARAMETERS, (char *) &configuration_parameters, TIMER_DEFAULT_VALUE);
@ -173,7 +176,7 @@ scl_result_t scl_send_data(int index, char *buffer, uint32_t timeout)
IPC_STRUCT_Type *scl_send = NULL;
uint32_t delay_timeout;
SCL_LOG(("scl_send_data index = %d\n", index));
SCL_LOG(("scl_send_data index = %d\r\n", index));
scl_send = Cy_IPC_Drv_GetIpcBaseAddress(SCL_TX_CHANNEL);
CHECK_BUFFER_NULL(buffer);
if (!(REG_IPC_STRUCT_LOCK_STATUS(scl_send) & SCL_LOCK_ACQUIRE_STATUS)) {
@ -198,7 +201,7 @@ scl_result_t scl_send_data(int index, char *buffer, uint32_t timeout)
return SCL_SUCCESS;
}
} else {
SCL_LOG(("unable to acquire lock\n"));
SCL_LOG(("unable to acquire lock\r\n"));
return SCL_ERROR;
}
}
@ -230,27 +233,22 @@ static void scl_rx_handler(void)
uint32_t index;
IPC_STRUCT_Type *scl_receive = NULL;
scl_buffer_t cp_buffer;
scl_buffer_t scl_buffer;
uint32_t rx_ipc_size;
struct rx_ipc_info {
uint32_t size;
int *buf_alloc;
}*rx_cp = NULL;
int *rx_cp_buffer;
SCL_LOG(("Starting CP Rx thread\r\n"));
scl_receive = Cy_IPC_Drv_GetIpcBaseAddress(SCL_RX_CHANNEL);
while (SCL_TRUE) {
cy_rtos_get_semaphore(&g_scl_thread_info.scl_rx_ready, CY_RTOS_NEVER_TIMEOUT, SCL_FALSE);
index = (uint32_t)REG_IPC_STRUCT_DATA0(scl_receive);
SCL_LOG(("scl_rx_handler index = %lu\n", index));
SCL_LOG(("scl_rx_handler index = %lu\r\n", index));
switch (index) {
case SCL_RX_DATA: {
rx_cp = (struct rx_ipc_info *) REG_IPC_STRUCT_DATA1(scl_receive);
scl_buffer = rx_cp->buf_alloc;
SCL_LOG(("on CP the rxd address = %lx\r\n", REG_IPC_STRUCT_DATA1(scl_receive)));
rx_cp_buffer = (int *) REG_IPC_STRUCT_DATA1(scl_receive);
SCL_LOG(("rx_cp_buffer = %p \r\n", rx_cp_buffer));
REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE;
SCL_LOG(("scl_buffer = %p\n", scl_buffer));
scl_network_process_ethernet_data(scl_buffer);
scl_network_process_ethernet_data(rx_cp_buffer);
break;
}
case SCL_RX_TEST_MSG: {
@ -273,11 +271,11 @@ static void scl_rx_handler(void)
} else {
scl_emac_wifi_link_state_changed(false);
}
SCL_LOG(("connection status = %d\n", connection_status));
SCL_LOG(("connection status = %d\r\n", connection_status));
break;
}
default: {
SCL_LOG(("incorrect IPC from Network Processor\n"));
SCL_LOG(("incorrect IPC from Network Processor\r\n"));
REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE;
break;
}

4
targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/include/scl_buffer_api.h
View File

@ -36,10 +36,6 @@ extern "C"
/******************************************************
* Constants
******************************************************/
/**
* Size of the SDIO block
*/
#define SDIO_BLOCK_SIZE (64U)
/******************************************************
* Macros

3
targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_buffer_api.c
View File

@ -45,10 +45,9 @@ scl_result_t scl_host_buffer_get(scl_buffer_t *buffer, scl_buffer_dir_t directio
if ((direction == SCL_NETWORK_TX) && (size <= PBUF_POOL_BUFSIZE)) {
p = pbuf_alloc(PBUF_RAW, size, PBUF_POOL);
} else {
p = pbuf_alloc(PBUF_RAW, size + SDIO_BLOCK_SIZE, PBUF_RAM);
p = pbuf_alloc(PBUF_RAW, size, PBUF_RAM);
if (p != NULL) {
p->len = size;
p->tot_len -= SDIO_BLOCK_SIZE;
}
}
if (p != NULL) {

18
targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_wifi_api.c
View File

@ -38,7 +38,7 @@ scl_result_t scl_wifi_is_ready_to_transceive(void)
result = scl_send_data(SCL_TX_TRANSCEIVE_READY, (char *)&retval, TIMER_DEFAULT_VALUE);
if (result == SCL_ERROR) {
SCL_LOG(("Ready to tranceive error\n"));
SCL_LOG(("Ready to tranceive error\r\n"));
return SCL_ERROR;
} else {
return retval;
@ -51,7 +51,7 @@ bool scl_wifi_on(void)
scl_result_t result = SCL_SUCCESS;
result = scl_send_data(SCL_TX_WIFI_ON, (char *)&retval, WIFI_ON_TIMEOUT);
if (result == SCL_ERROR) {
SCL_LOG(("wifi_on Error\n"));
SCL_LOG(("wifi_on Error\r\n"));
return false;
} else {
return retval;
@ -66,7 +66,7 @@ scl_result_t scl_wifi_set_up(void)
if (result == SCL_SUCCESS) {
return retval;
} else {
SCL_LOG(("Wifi set up error\n"));
SCL_LOG(("Wifi set up error\r\n"));
return SCL_ERROR;
}
}
@ -85,7 +85,7 @@ scl_result_t scl_wifi_get_mac_address(scl_mac_t *mac)
if (scl_retval == SCL_SUCCESS) {
return scl_mac_data.retval;
} else {
SCL_LOG(("Get MAC address error\n"));
SCL_LOG(("Get MAC address error\r\n"));
return SCL_ERROR;
}
}
@ -98,7 +98,7 @@ scl_result_t scl_wifi_get_bssid(scl_mac_t *bssid)
} scl_bssid_t;
scl_result_t scl_retval = SCL_SUCCESS;
scl_bssid_t.bssid = bssid;
scl_bssid_t.retval = 0;
scl_bssid_t.retval = SCL_SUCCESS;
if (bssid == NULL) {
return SCL_BADARG;
}
@ -106,7 +106,7 @@ scl_result_t scl_wifi_get_bssid(scl_mac_t *bssid)
if (scl_retval == SCL_SUCCESS) {
return scl_bssid_t.retval;
} else {
SCL_LOG(("get bssid error\n"));
SCL_LOG(("get bssid error\r\n"));
return SCL_ERROR;
}
}
@ -115,14 +115,14 @@ scl_result_t scl_wifi_register_multicast_address(scl_mac_t *mac)
{
scl_mac scl_mac_t;
scl_mac_t.mac = mac;
scl_mac_t.retval = 0;
scl_mac_t.retval = SCL_SUCCESS;
scl_result_t scl_retval = SCL_SUCCESS;
if (mac == NULL) {
return SCL_BADARG;
}
scl_retval = scl_send_data(SCL_TX_REGISTER_MULTICAST_ADDRESS, (char *)&scl_mac_t, TIMER_DEFAULT_VALUE);
if (scl_retval != SCL_SUCCESS) {
SCL_LOG(("Register Multicast Address IPC Error"));
SCL_LOG(("Register Multicast Address IPC Error\r\n"));
return SCL_ERROR;
}
return (scl_mac_t.retval);
@ -154,7 +154,7 @@ scl_result_t scl_wifi_get_rssi(int32_t *rssi)
if (scl_retval == SCL_SUCCESS) {
return tx_param_t.retval;
} else {
SCL_LOG(("get rssi error\n"));
SCL_LOG(("get rssi error\r\n"));
return SCL_ERROR;
}
}

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
View File

@ -28,6 +28,8 @@
void init_cycfg_all(void)
{
init_cycfg_system();
init_cycfg_routing();
init_cycfg_peripherals();
init_cycfg_pins();
}

1
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
View File

@ -34,6 +34,7 @@ extern "C" {
#include "cycfg_notices.h"
#include "cycfg_system.h"
#include "cycfg_routing.h"
#include "cycfg_peripherals.h"
#include "cycfg_pins.h"
void init_cycfg_all(void);

49
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c Normal file
View File

@ -0,0 +1,49 @@
/*******************************************************************************
* File Name: cycfg_peripherals.c
*
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_peripherals.h"
const cy_stc_smif_config_t CYBSP_QSPI_config = {
.mode = (uint32_t)CY_SMIF_NORMAL,
.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_obj = {
.type = CYHAL_RSC_SMIF,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void)
{
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
#endif //defined (CY_USING_HAL)
}

72
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h Normal file
View File

@ -0,0 +1,72 @@
/*******************************************************************************
* File Name: cycfg_peripherals.h
*
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_PERIPHERALS_H)
#define CYCFG_PERIPHERALS_H
#include "cycfg_notices.h"
#include "cy_smif.h"
#include "cycfg_qspi_memslot.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#if defined(__cplusplus)
extern "C" {
#endif
#define CYBSP_QSPI_ENABLED 1U
#define CYBSP_QSPI_HW SMIF0
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
#define CYBSP_QSPI_DATALINES0_1 (1UL)
#define CYBSP_QSPI_DATALINES2_3 (1UL)
#define CYBSP_QSPI_DATALINES4_5 (0UL)
#define CYBSP_QSPI_DATALINES6_7 (0UL)
#define CYBSP_QSPI_SS0 (1UL)
#define CYBSP_QSPI_SS1 (0UL)
#define CYBSP_QSPI_SS2 (0UL)
#define CYBSP_QSPI_SS3 (0UL)
#define CYBSP_QSPI_DESELECT_DELAY 7
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_PERIPHERALS_H */

175
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
View File

@ -26,8 +26,7 @@
#include "cycfg_pins.h"
const cy_stc_gpio_pin_config_t CYBSP_SW1_config =
{
const cy_stc_gpio_pin_config_t CYBSP_SW1_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_SW1_HSIOM,
@ -43,15 +42,13 @@ const cy_stc_gpio_pin_config_t CYBSP_SW1_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SW1_obj =
{
const cyhal_resource_inst_t CYBSP_SW1_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SW1_PORT_NUM,
.channel_num = CYBSP_SW1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_LED1_config =
{
const cy_stc_gpio_pin_config_t CYBSP_LED1_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED1_HSIOM,
@ -67,18 +64,16 @@ const cy_stc_gpio_pin_config_t CYBSP_LED1_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_LED1_obj =
{
const cyhal_resource_inst_t CYBSP_LED1_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_LED1_PORT_NUM,
.channel_num = CYBSP_LED1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_SWO_HSIOM,
.hsiom = CYBSP_QSPI_SS0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
@ -91,15 +86,123 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWO_obj =
{
const cyhal_resource_inst_t CYBSP_QSPI_SS0_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWO_PORT_NUM,
.channel_num = CYBSP_SWO_PIN,
.block_num = CYBSP_QSPI_SS0_PORT_NUM,
.channel_num = CYBSP_QSPI_SS0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_QSPI_DATA3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_DATA3_PORT_NUM,
.channel_num = CYBSP_QSPI_DATA3_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_QSPI_DATA2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_DATA2_PORT_NUM,
.channel_num = CYBSP_QSPI_DATA2_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_QSPI_DATA1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_DATA1_PORT_NUM,
.channel_num = CYBSP_QSPI_DATA1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_QSPI_DATA0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_DATA0_PORT_NUM,
.channel_num = CYBSP_QSPI_DATA0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_QSPI_SPI_CLOCK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_SPI_CLOCK_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_SPI_CLOCK_PORT_NUM,
.channel_num = CYBSP_QSPI_SPI_CLOCK_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
.hsiom = CYBSP_SWDIO_HSIOM,
@ -115,15 +218,13 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
{
const cyhal_resource_inst_t CYBSP_SWDIO_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDIO_PORT_NUM,
.channel_num = CYBSP_SWDIO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
{
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLDOWN,
.hsiom = CYBSP_SWDCK_HSIOM,
@ -139,8 +240,7 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
{
const cyhal_resource_inst_t CYBSP_SWDCK_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDCK_PORT_NUM,
.channel_num = CYBSP_SWDCK_PIN,
@ -160,9 +260,34 @@ void init_cycfg_pins(void)
cyhal_hwmgr_reserve(&CYBSP_LED1_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
Cy_GPIO_Pin_Init(CYBSP_QSPI_SS0_PORT, CYBSP_QSPI_SS0_PIN, &CYBSP_QSPI_SS0_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
cyhal_hwmgr_reserve(&CYBSP_QSPI_SS0_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA3_PORT, CYBSP_QSPI_DATA3_PIN, &CYBSP_QSPI_DATA3_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA3_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA2_PORT, CYBSP_QSPI_DATA2_PIN, &CYBSP_QSPI_DATA2_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA2_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA1_PORT, CYBSP_QSPI_DATA1_PIN, &CYBSP_QSPI_DATA1_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA1_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA0_PORT, CYBSP_QSPI_DATA0_PIN, &CYBSP_QSPI_DATA0_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA0_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_SPI_CLOCK_PORT, CYBSP_QSPI_SPI_CLOCK_PIN, &CYBSP_QSPI_SPI_CLOCK_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_SPI_CLOCK_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);

174
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

@ -86,29 +86,149 @@ extern "C" {
#if defined (CY_USING_HAL)
#define CYBSP_LED1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_SWO_ENABLED 1U
#define CYBSP_SWO_PORT GPIO_PRT6
#define CYBSP_SWO_PORT_NUM 6U
#define CYBSP_SWO_PIN 4U
#define CYBSP_SWO_NUM 4U
#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_SWO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_4_HSIOM
#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
#define CYBSP_QSPI_SS0_ENABLED 1U
#define CYBSP_QSPI_SS0_PORT GPIO_PRT11
#define CYBSP_QSPI_SS0_PORT_NUM 11U
#define CYBSP_QSPI_SS0_PIN 2U
#define CYBSP_QSPI_SS0_NUM 2U
#define CYBSP_QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_QSPI_SS0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_2_HSIOM
#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
#define CYBSP_QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM
#define CYBSP_QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_PORT_PIN P6_4
#define CYBSP_QSPI_SS0_HAL_PORT_PIN P11_2
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_QSPI_SS0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#define CYBSP_QSPI_SS0_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#define CYBSP_QSPI_SS0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA3_ENABLED 1U
#define CYBSP_QSPI_DATA3_PORT GPIO_PRT11
#define CYBSP_QSPI_DATA3_PORT_NUM 11U
#define CYBSP_QSPI_DATA3_PIN 3U
#define CYBSP_QSPI_DATA3_NUM 3U
#define CYBSP_QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_DATA3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_3_HSIOM
#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
#define CYBSP_QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA3_HAL_PORT_PIN P11_3
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA2_ENABLED 1U
#define CYBSP_QSPI_DATA2_PORT GPIO_PRT11
#define CYBSP_QSPI_DATA2_PORT_NUM 11U
#define CYBSP_QSPI_DATA2_PIN 4U
#define CYBSP_QSPI_DATA2_NUM 4U
#define CYBSP_QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_DATA2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_4_HSIOM
#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
#define CYBSP_QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA2_HAL_PORT_PIN P11_4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA1_ENABLED 1U
#define CYBSP_QSPI_DATA1_PORT GPIO_PRT11
#define CYBSP_QSPI_DATA1_PORT_NUM 11U
#define CYBSP_QSPI_DATA1_PIN 5U
#define CYBSP_QSPI_DATA1_NUM 5U
#define CYBSP_QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_DATA1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_5_HSIOM
#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
#define CYBSP_QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA1_HAL_PORT_PIN P11_5
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA0_ENABLED 1U
#define CYBSP_QSPI_DATA0_PORT GPIO_PRT11
#define CYBSP_QSPI_DATA0_PORT_NUM 11U
#define CYBSP_QSPI_DATA0_PIN 6U
#define CYBSP_QSPI_DATA0_NUM 6U
#define CYBSP_QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_DATA0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_6_HSIOM
#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
#define CYBSP_QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA0_HAL_PORT_PIN P11_6
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_SPI_CLOCK_ENABLED 1U
#define CYBSP_QSPI_SPI_CLOCK_PORT GPIO_PRT11
#define CYBSP_QSPI_SPI_CLOCK_PORT_NUM 11U
#define CYBSP_QSPI_SPI_CLOCK_PIN 7U
#define CYBSP_QSPI_SPI_CLOCK_NUM 7U
#define CYBSP_QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_QSPI_SPI_CLOCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_7_HSIOM
#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM
#define CYBSP_QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SPI_CLOCK_HAL_PORT_PIN P11_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SPI_CLOCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SPI_CLOCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SPI_CLOCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_SWDIO_ENABLED 1U
#define CYBSP_SWDIO_PORT GPIO_PRT6
@ -167,9 +287,29 @@ extern const cy_stc_gpio_pin_config_t CYBSP_LED1_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_LED1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWO_obj;
extern const cyhal_resource_inst_t CYBSP_QSPI_SS0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_SPI_CLOCK_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
#if defined (CY_USING_HAL)

36
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
View File

@ -25,8 +25,7 @@
#include "cycfg_qspi_memslot.h"
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
{
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd = {
/* The 8-bit command. 1 x I/O read command. */
.command = 0xEBU,
/* The width of the command transfer. */
@ -43,8 +42,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
{
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd = {
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
/* The width of the command transfer. */
@ -61,8 +59,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
{
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd = {
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
/* The width of the command transfer. */
@ -79,8 +76,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
{
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd = {
/* The 8-bit command. 1 x I/O read command. */
.command = 0xD8U,
/* The width of the command transfer. */
@ -97,8 +93,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
{
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd = {
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
/* The width of the command transfer. */
@ -115,8 +110,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
{
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd = {
/* The 8-bit command. 1 x I/O read command. */
.command = 0x38U,
/* The width of the command transfer. */
@ -133,8 +127,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
{
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd = {
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
/* The width of the command transfer. */
@ -151,8 +144,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
{
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd = {
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
/* The width of the command transfer. */
@ -169,8 +161,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
{
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd = {
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
/* The width of the command transfer. */
@ -187,8 +178,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
{
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 = {
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x03U,
/* The size of the memory. */
@ -227,8 +217,7 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
.programTime = 1300U
};
const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
{
const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 = {
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
/* Flags. */
@ -252,8 +241,7 @@ const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
&S25FL512S_SlaveSlot_0
};
const cy_stc_smif_block_config_t smifBlockConfig =
{
const cy_stc_smif_block_config_t smifBlockConfig = {
/* The number of SMIF memories defined. */
.memCount = CY_SMIF_DEVICE_NUM,
/* The pointer to the array of memory config structures of size memCount. */

7
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
View File

@ -34,7 +34,12 @@ extern "C" {
#include "cycfg_notices.h"
void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK

420
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
View File

@ -26,3 +26,423 @@
#include "cycfg_system.h"
#define CY_CFG_SYSCLK_ECO_ERROR 1
#define CY_CFG_SYSCLK_ALTHF_ERROR 2
#define CY_CFG_SYSCLK_PLL_ERROR 3
#define CY_CFG_SYSCLK_FLL_ERROR 4
#define CY_CFG_SYSCLK_WCO_ERROR 5
#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
#define CY_CFG_SYSCLK_ILO_ENABLED 1
#define CY_CFG_SYSCLK_IMO_ENABLED 1
#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
#define CY_CFG_SYSCLK_PLL0_ENABLED 1
#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = {
.type = CYHAL_RSC_CLKPATH,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = {
.type = CYHAL_RSC_CLKPATH,
.block_num = 1U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = {
.feedbackDiv = 25,
.referenceDiv = 1,
.outputDiv = 2,
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
};
__WEAK void cycfg_ClockStartupError(uint32_t error)
{
(void)error; /* Suppress the compiler warning */
while (1);
}
__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
{
Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);
}
__STATIC_INLINE void Cy_SysClk_ClkBakInit()
{
Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
}
__STATIC_INLINE void Cy_SysClk_ClkFastInit()
{
Cy_SysClk_ClkFastSetDivider(0U);
}
__STATIC_INLINE void Cy_SysClk_ClkHf0Init()
{
Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
}
__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
}
__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
}
__STATIC_INLINE void Cy_SysClk_IloInit()
{
/* The WDT is unlocked in the default startup code */
Cy_SysClk_IloEnable();
Cy_SysClk_IloHibernateOn(true);
}
__STATIC_INLINE void Cy_SysClk_ClkLfInit()
{
/* The WDT is unlocked in the default startup code */
Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);
}
__STATIC_INLINE void Cy_SysClk_ClkPath0Init()
{
Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPath1Init()
{
Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
{
Cy_SysClk_ClkPeriSetDivider(0U);
}
__STATIC_INLINE void Cy_SysClk_Pll0Init()
{
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig)) {
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u)) {
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
}
__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
{
Cy_SysClk_ClkSlowSetDivider(0U);
}
__STATIC_INLINE void Cy_SysClk_ClkTimerInit()
{
Cy_SysClk_ClkTimerDisable();
Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
Cy_SysClk_ClkTimerSetDivider(0U);
Cy_SysClk_ClkTimerEnable();
}
void init_cycfg_system(void)
{
/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
Cy_SysLib_SetWaitStates(false, 150UL);
#ifdef CY_CFG_PWR_ENABLED
#ifdef CY_CFG_PWR_INIT
init_cycfg_power();
#else
#warning Power system will not be configured. Update power personality to v1.20 or later.
#endif /* CY_CFG_PWR_INIT */
#endif /* CY_CFG_PWR_ENABLED */
/* Reset the core clock path to default and disable all the FLLs/PLLs */
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkFastSetDivider(0U);
Cy_SysClk_ClkPeriSetDivider(1U);
Cy_SysClk_ClkSlowSetDivider(0U);
for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) { /* PLL 1 is the first PLL. 0 is invalid. */
(void)Cy_SysClk_PllDisable(pll);
}
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
(CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) {
Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
}
Cy_SysClk_FllDisable();
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
#ifdef CY_IP_MXBLESS
(void)Cy_BLE_EcoReset();
#endif
/* Enable all source clocks */
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
Cy_SysClk_PiloInit();
#endif
#ifdef CY_CFG_SYSCLK_WCO_ENABLED
Cy_SysClk_WcoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
Cy_SysClk_ClkLfInit();
#endif
#ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
Cy_SysClk_AltHfInit();
#endif
#ifdef CY_CFG_SYSCLK_ECO_ENABLED
Cy_SysClk_EcoInit();
#endif
#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
Cy_SysClk_ExtClkInit();
#endif
/* Configure CPU clock dividers */
#ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
Cy_SysClk_ClkFastInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
Cy_SysClk_ClkPeriInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
Cy_SysClk_ClkSlowInit();
#endif
#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
/* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
#else
#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
Cy_SysClk_ClkPath1Init();
#endif
#endif
/* Configure Path Clocks */
#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
Cy_SysClk_ClkPath0Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
Cy_SysClk_ClkPath2Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
Cy_SysClk_ClkPath3Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
Cy_SysClk_ClkPath4Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
Cy_SysClk_ClkPath5Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
Cy_SysClk_ClkPath6Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
Cy_SysClk_ClkPath7Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
Cy_SysClk_ClkPath8Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
Cy_SysClk_ClkPath9Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
Cy_SysClk_ClkPath10Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
Cy_SysClk_ClkPath11Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
Cy_SysClk_ClkPath12Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
Cy_SysClk_ClkPath13Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
Cy_SysClk_ClkPath14Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
Cy_SysClk_ClkPath15Init();
#endif
/* Configure and enable FLL */
#ifdef CY_CFG_SYSCLK_FLL_ENABLED
Cy_SysClk_FllInit();
#endif
Cy_SysClk_ClkHf0Init();
#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
/* Apply the ClkPath1 user setting */
Cy_SysClk_ClkPath1Init();
#endif
#endif
/* Configure and enable PLLs */
#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
Cy_SysClk_Pll0Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL1_ENABLED
Cy_SysClk_Pll1Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL2_ENABLED
Cy_SysClk_Pll2Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL3_ENABLED
Cy_SysClk_Pll3Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL4_ENABLED
Cy_SysClk_Pll4Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL5_ENABLED
Cy_SysClk_Pll5Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL6_ENABLED
Cy_SysClk_Pll6Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL7_ENABLED
Cy_SysClk_Pll7Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL8_ENABLED
Cy_SysClk_Pll8Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL9_ENABLED
Cy_SysClk_Pll9Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL10_ENABLED
Cy_SysClk_Pll10Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL11_ENABLED
Cy_SysClk_Pll11Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL12_ENABLED
Cy_SysClk_Pll12Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL13_ENABLED
Cy_SysClk_Pll13Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL14_ENABLED
Cy_SysClk_Pll14Init();
#endif
/* Configure HF clocks */
#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
Cy_SysClk_ClkHf1Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
Cy_SysClk_ClkHf2Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
Cy_SysClk_ClkHf3Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
Cy_SysClk_ClkHf4Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
Cy_SysClk_ClkHf5Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
Cy_SysClk_ClkHf6Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
Cy_SysClk_ClkHf7Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
Cy_SysClk_ClkHf8Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
Cy_SysClk_ClkHf9Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
Cy_SysClk_ClkHf10Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
Cy_SysClk_ClkHf11Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
Cy_SysClk_ClkHf12Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
Cy_SysClk_ClkHf13Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
Cy_SysClk_ClkHf14Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
Cy_SysClk_ClkHf15Init();
#endif
/* Configure miscellaneous clocks */
#ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
Cy_SysClk_ClkTimerInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
Cy_SysClk_ClkAltSysTickInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
Cy_SysClk_ClkPumpInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
Cy_SysClk_ClkBakInit();
#endif
/* Configure default enabled clocks */
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
Cy_SysClk_IloInit();
#else
Cy_SysClk_IloDisable();
#endif
#ifndef CY_CFG_SYSCLK_IMO_ENABLED
#error the IMO must be enabled for proper chip operation
#endif
#ifdef CY_CFG_SYSCLK_MFO_ENABLED
Cy_SysClk_MfoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
Cy_SysClk_ClkMfInit();
#endif
/* Set accurate flash wait states */
#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
#endif
/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
SystemCoreClockUpdate();
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
#endif //defined (CY_USING_HAL)
}

34
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
View File

@ -28,12 +28,46 @@
#define CYCFG_SYSTEM_H
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#include "cy_systick.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#if defined(__cplusplus)
extern "C" {
#endif
#define cpuss_0_dap_0_ENABLED 1U
#define srss_0_clock_0_ENABLED 1U
#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
#define srss_0_clock_0_bakclk_0_ENABLED 1U
#define srss_0_clock_0_fastclk_0_ENABLED 1U
#define srss_0_clock_0_hfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF0 0UL
#define srss_0_clock_0_hfclk_2_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF2 2UL
#define srss_0_clock_0_hfclk_4_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF4 4UL
#define srss_0_clock_0_ilo_0_ENABLED 1U
#define srss_0_clock_0_imo_0_ENABLED 1U
#define srss_0_clock_0_lfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000
#define srss_0_clock_0_pathmux_0_ENABLED 1U
#define srss_0_clock_0_pathmux_1_ENABLED 1U
#define srss_0_clock_0_periclk_0_ENABLED 1U
#define srss_0_clock_0_pll_0_ENABLED 1U
#define srss_0_clock_0_slowclk_0_ENABLED 1U
#define srss_0_clock_0_timerclk_0_ENABLED 1U
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_system(void);
#if defined(__cplusplus)
}

38
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
View File

@ -50,45 +50,17 @@ scb[10]
ioss[0].port[5].pin[4]
# CYBSP_DEBUG_UART_TX
ioss[0].port[5].pin[5]
# CYBSP_DEBUG_UART_RTS
ioss[0].port[5].pin[6]
# CYBSP_DEBUG_UART_CTS
ioss[0].port[5].pin[7]
# CYBSP_DEBUG_UART_CLK_DIV
peri[0].div_16[0]
# POWER
srss[0].power[0]
# SYSTEM CLOCK
srss[0].clock[0]
# CLK_ALT_SYS_TICK
srss[0].clock[0].altsystickclk[0]
# CLK_BAK
srss[0].clock[0].bakclk[0]
# CLK_FAST
srss[0].clock[0].fastclk[0]
# CLK_HF0
srss[0].clock[0].hfclk[0]
# CLK_HF2
srss[0].clock[0].hfclk[2]
# CLK_HF4
srss[0].clock[0].hfclk[4]
# CLK_ILO
srss[0].clock[0].ilo[0]
# CLK_IMO
srss[0].clock[0].imo[0]
# CLK_LF
srss[0].clock[0].lfclk[0]
# PATH_MUX0
srss[0].clock[0].pathmux[0]
# PATH_MUX1
srss[0].clock[0].pathmux[1]
# CLK_PERI
srss[0].clock[0].periclk[0]
# CLK_PLL0
srss[0].clock[0].pll[0]
# CLK_SLOW
srss[0].clock[0].slowclk[0]
# CLK_TIMER
srss[0].clock[0].timerclk[0]
# RTC
srss[0].rtc[0]

200
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -36,8 +36,8 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[6].pin[4]">
<Alias value="CYBSP_SWO"/>
<Block location="ioss[0].port[11].pin[2]">
<Alias value="CYBSP_QSPI_SS0"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
@ -49,6 +49,72 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[11].pin[3]">
<Alias value="CYBSP_QSPI_DATA3"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[11].pin[4]">
<Alias value="CYBSP_QSPI_DATA2"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[11].pin[5]">
<Alias value="CYBSP_QSPI_DATA1"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[11].pin[6]">
<Alias value="CYBSP_QSPI_DATA0"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[11].pin[7]">
<Alias value="CYBSP_QSPI_SPI_CLOCK"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[6].pin[4]"/>
<Block location="ioss[0].port[6].pin[6]">
<Alias value="CYBSP_SWDIO"/>
<Personality template="mxs40pin" version="1.1">
@ -84,6 +150,104 @@
<Block location="ioss[0].port[8].pin[7]">
<Alias value="CYBSP_CSD_SLD4"/>
</Block>
<Block location="smif[0]">
<Alias value="CYBSP_QSPI"/>
<Personality template="mxs40smif" version="1.1">
<Param id="configurator" value="0"/>
<Param id="isrAlignment" value="false"/>
<Param id="isrUnderflow" value="false"/>
<Param id="isrCmdOverflow" value="false"/>
<Param id="isrDataOverflow" value="false"/>
<Param id="rxTriggerLevel" value="0"/>
<Param id="txTriggerLevel" value="0"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="srss[0].clock[0]">
<Personality template="mxs40sysclocks" version="1.2"/>
</Block>
<Block location="srss[0].clock[0].altsystickclk[0]">
<Personality template="mxs40altsystick" version="1.0">
<Param id="sourceClock" value="lfclk"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].bakclk[0]">
<Personality template="mxs40bakclk" version="1.0">
<Param id="sourceClock" value="lfclk"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].fastclk[0]">
<Personality template="mxs40fastclk" version="1.0">
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].hfclk[0]">
<Personality template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="1"/>
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].hfclk[2]">
<Personality template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="1"/>
<Param id="divider" value="2"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].hfclk[4]">
<Personality template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="1"/>
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].ilo[0]">
<Personality template="mxs40ilo" version="1.0">
<Param id="hibernate" value="true"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].imo[0]">
<Personality template="mxs40imo" version="1.0">
<Param id="trim" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].lfclk[0]">
<Personality template="mxs40lfclk" version="1.1">
<Param id="sourceClock" value="ilo"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pathmux[0]">
<Personality template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pathmux[1]">
<Personality template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].periclk[0]">
<Personality template="mxs40periclk" version="1.0">
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pll[0]">
<Personality template="mxs40pll" version="1.0">
<Param id="lowFrequencyMode" value="false"/>
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="100.000"/>
<Param id="optimization" value="MinPower"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].slowclk[0]">
<Personality template="mxs40slowclk" version="1.0">
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].timerclk[0]">
<Personality template="mxs40timerclk" version="1.0">
<Param id="sourceClock" value="imo"/>
<Param id="timerDivider" value="1"/>
</Personality>
</Block>
</BlockConfig>
<Netlist>
<Net>
@ -95,8 +259,36 @@
<Port name="ioss[0].port[6].pin[6].digital_inout[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swo_tdo[0]"/>
<Port name="ioss[0].port[6].pin[4].digital_out[0]"/>
<Port name="ioss[0].port[11].pin[2].digital_out[0]"/>
<Port name="smif[0].spi_select0[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[3].digital_out[0]"/>
<Port name="smif[0].spi_data3[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[4].digital_out[0]"/>
<Port name="smif[0].spi_data2[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[5].digital_out[0]"/>
<Port name="smif[0].spi_data1[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[6].digital_out[0]"/>
<Port name="smif[0].spi_data0[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[7].digital_inout[0]"/>
<Port name="smif[0].spi_clk[0]"/>
</Net>
<Net>
<Port name="smif[0].clk_hf[0]"/>
<Port name="srss[0].clock[0].hfclk[0].root_clk[0]"/>
</Net>
<Net>
<Port name="smif[0].clk_if[0]"/>
<Port name="srss[0].clock[0].hfclk[2].root_clk[0]"/>
</Net>
</Netlist>
</Device>

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c
View File

@ -73,8 +73,7 @@ static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
.order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
};
if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
{
if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) {
result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
}
return result;
@ -93,8 +92,7 @@ cy_rslt_t cybsp_init(void)
init_cycfg_all();
#endif
if (CY_RSLT_SUCCESS == result)
{
if (CY_RSLT_SUCCESS == result) {
result = cybsp_register_sysclk_pm_callback();
}

122
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h
View File

@ -33,10 +33,6 @@
extern "C" {
#endif
#ifndef CY_CFG_SYSCLK_CLKLF_FREQ_HZ
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ (32000U)
#endif
/**
* \addtogroup group_bsp_settings BSP Settings
* \{
@ -113,50 +109,15 @@ extern "C" {
* \{
*/
/** Pin: WIFI SDIO D0 */
#define CYBSP_WIFI_SDIO_D0 (P2_0)
/** Pin: WIFI SDIO D1 */
#define CYBSP_WIFI_SDIO_D1 (P2_1)
/** Pin: WIFI SDIO D2 */
#define CYBSP_WIFI_SDIO_D2 (P2_2)
/** Pin: WIFI SDIO D3 */
#define CYBSP_WIFI_SDIO_D3 (P2_3)
/** Pin: WIFI SDIO CMD */
#define CYBSP_WIFI_SDIO_CMD (P2_4)
/** Pin: WIFI SDIO CLK */
#define CYBSP_WIFI_SDIO_CLK (P2_5)
/** Pin: WIFI ON */
#define CYBSP_WIFI_WL_REG_ON (P2_6)
/** Pin: WIFI Host Wakeup */
#define CYBSP_WIFI_HOST_WAKE (P1_4)
/** Host-wake GPIO drive mode */
#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
/** Host-wake IRQ event */
#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE)
/** Pin: BT UART RX */
#define CYBSP_BT_UART_RX (P13_4)
/** Pin: BT UART TX */
#define CYBSP_BT_UART_TX (P13_5)
/** Pin: BT UART RTS */
#define CYBSP_BT_UART_RTS (P13_6)
/** Pin: BT UART CTS */
#define CYBSP_BT_UART_CTS (P13_7)
/** Pin: BT Power */
#define CYBSP_BT_POWER (P12_0)
/** Pin: BT Host Wakeup */
#define CYBSP_BT_HOST_WAKE (P12_3)
/** Pin: BT Device Wakeup */
#define CYBSP_BT_DEVICE_WAKE (P12_2)
/** Pin: UART RX */
#define CYBSP_DEBUG_UART_RX (P5_4)
/** Pin: UART TX */
#define CYBSP_DEBUG_UART_TX (P5_5)
/** Pin: UART_RTS */
#define CYBSP_DEBUG_UART_RTS (P5_6)
/** Pin: UART_CTS */
#define CYBSP_DEBUG_UART_CTS (P5_7)
/** Pin: SWO */
#define CYBSP_SWO (P6_4)
/** Pin: SWDIO */
#define CYBSP_SWDIO (P6_6)
/** Pin: SWDCK */
@ -180,13 +141,82 @@ extern "C" {
/** Pin: I2C SDA */
#define CYBSP_I2C_SDA (P6_1)
/** Pin: SPI MOSI */
#define CYBSP_SPI_MOSI (P5_0)
/** Pin: SPI MISO */
#define CYBSP_SPI_MISO (P5_1)
/** Pin: SPI CLK */
#define CYBSP_SPI_CLK (P5_2)
/** Pin: SPI CS */
#define CYBSP_SPI_CS (P5_3)
/** Pin: FEATHER UART RX */
#define CYBSP_FEATHER_UART_RX (P6_4)
/** Pin: FEATHER UART TX */
#define CYBSP_FEATHER_UART_TX (P6_5)
/** \} group_bsp_pins_comm */
/**
* \addtogroup group_bsp_pins_therm Thermister Pins
* \{
*/
/** Pin: Thermister VDD */
#define CYBSP_THERM_VDD (P10_6)
/** Pin: Thermister output */
#define CYBSP_THERM_OUT (P10_7)
/** \} group_bsp_pins_therm */
/**
* \addtogroup group_bsp_pins_eco ECO Pins
* \{
*/
/** Pin: ECO IN */
#define CYBSP_ECO_IN (P12_6)
/** Pin: ECO IN */
#define CYBSP_ECO_OUT (P12_7)
/** \} group_bsp_pins_eco */
/**
* \addtogroup group_bsp_pins_feather Feather Header Pins
* \{
*/
/** GPIOA0 */
#define CYBSP_GPIOA0 (P10_0)
/** GPIOA1 */
#define CYBSP_GPIOA1 (P10_1)
/** GPIOA2 */
#define CYBSP_GPIOA2 (P10_2)
/** GPIOA3 */
#define CYBSP_GPIOA3 (P10_3)
/** GPIOA4 */
#define CYBSP_GPIOA4 (P10_4)
/** GPIOA5 */
#define CYBSP_GPIOA5 (P10_5)
/** GPIO5 */
#define CYBSP_GPIO5 (P8_4)
/** GPIO6 */
#define CYBSP_GPIO6 (P9_7)
/** GPIO9 */
#define CYBSP_GPIO9 (P9_4)
/** GPIO10 */
#define CYBSP_GPIO10 (P9_3)
/** GPIO11 */
#define CYBSP_GPIO11 (P9_2)
/** GPIO12 */
#define CYBSP_GPIO12 (P9_1)
/** GPIO13 */
#define CYBSP_GPIO13 (P9_0)
/** \} group_bsp_pins_feather */
/** \} group_bsp_pins */
#endif /* defined(CY_USING_HAL) */
#if defined(__cplusplus)