mirror of https://github.com/ARMmbed/mbed-os.git
Merge branch 'master' of https://github.com/mbedmicro/mbed
bcostm
commit
60320cc3f0
|
|
@ -36,9 +36,7 @@ Includes <System Includes> , "Project Includes"
|
|||
#include <MBRZA1H.h>
|
||||
#include "r_typedefs.h"
|
||||
#include "usb0_function_api.h"
|
||||
#if 0
|
||||
#include "usb1_function_api.h"
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
|
|
|||
|
|
@ -0,0 +1,171 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_function.h
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
*******************************************************************************/
|
||||
#ifndef USB1_FUNCTION_H
|
||||
#define USB1_FUNCTION_H
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include "devdrv_usb_function_api.h"
|
||||
#include "usb_function.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
extern const uint16_t g_usb1_function_bit_set[];
|
||||
extern uint32_t g_usb1_function_data_count[USB_FUNCTION_MAX_PIPE_NO + 1];
|
||||
extern uint8_t *g_usb1_function_data_pointer[USB_FUNCTION_MAX_PIPE_NO + 1];
|
||||
|
||||
extern uint16_t g_usb1_function_PipeIgnore[];
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||||
extern uint16_t g_usb1_function_PipeTbl[];
|
||||
extern uint16_t g_usb1_function_pipe_status[];
|
||||
extern uint32_t g_usb1_function_PipeDataSize[];
|
||||
|
||||
extern USB_FUNCTION_DMA_t g_usb1_function_DmaInfo[];
|
||||
extern uint16_t g_usb1_function_DmaPipe[];
|
||||
extern uint16_t g_usb1_function_DmaBval[];
|
||||
extern uint16_t g_usb1_function_DmaStatus[];
|
||||
|
||||
extern uint16_t g_usb1_function_CtrZeroLengthFlag;
|
||||
|
||||
extern uint16_t g_usb1_function_ConfigNum;
|
||||
extern uint16_t g_usb1_function_Alternate[USB_FUNCTION_ALT_NO];
|
||||
extern uint16_t g_usb1_function_RemoteWakeupFlag;
|
||||
extern uint16_t g_usb1_function_TestModeFlag;
|
||||
extern uint16_t g_usb1_function_TestModeSelectors;
|
||||
|
||||
extern uint16_t g_usb1_function_ReqType;
|
||||
extern uint16_t g_usb1_function_ReqTypeType;
|
||||
extern uint16_t g_usb1_function_ReqTypeRecip;
|
||||
extern uint16_t g_usb1_function_ReqRequest;
|
||||
extern uint16_t g_usb1_function_ReqValue;
|
||||
extern uint16_t g_usb1_function_ReqIndex;
|
||||
extern uint16_t g_usb1_function_ReqLength;
|
||||
|
||||
extern uint16_t g_usb1_function_EPTableIndex[USB_FUNCTION_MAX_EP_NO + 1];
|
||||
|
||||
extern uint16_t g_usb1_function_pipecfg[USB_FUNCTION_MAX_PIPE_NO + 1];
|
||||
extern uint16_t g_usb1_function_pipebuf[USB_FUNCTION_MAX_PIPE_NO + 1];
|
||||
extern uint16_t g_usb1_function_pipemaxp[USB_FUNCTION_MAX_PIPE_NO + 1];
|
||||
extern uint16_t g_usb1_function_pipeperi[USB_FUNCTION_MAX_PIPE_NO + 1];
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
/* ==== common ==== */
|
||||
void usb1_function_dma_stop_d0(uint16_t pipe, uint32_t remain);
|
||||
void usb1_function_dma_stop_d1(uint16_t pipe, uint32_t remain);
|
||||
uint16_t usb1_function_is_hispeed(void);
|
||||
uint16_t usb1_function_is_hispeed_enable(void);
|
||||
uint16_t usb1_function_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
|
||||
uint16_t usb1_function_write_buffer(uint16_t pipe);
|
||||
uint16_t usb1_function_write_buffer_c(uint16_t pipe);
|
||||
uint16_t usb1_function_write_buffer_d0(uint16_t pipe);
|
||||
uint16_t usb1_function_write_buffer_d1(uint16_t pipe);
|
||||
void usb1_function_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
|
||||
uint16_t usb1_function_read_buffer(uint16_t pipe);
|
||||
uint16_t usb1_function_read_buffer_c(uint16_t pipe);
|
||||
uint16_t usb1_function_read_buffer_d0(uint16_t pipe);
|
||||
uint16_t usb1_function_read_buffer_d1(uint16_t pipe);
|
||||
uint16_t usb1_function_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
|
||||
void usb1_function_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
|
||||
void usb1_function_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc);
|
||||
uint16_t usb1_function_get_mbw(uint32_t trncount, uint32_t dtptr);
|
||||
uint16_t usb1_function_read_dma(uint16_t pipe);
|
||||
void usb1_function_brdy_int(uint16_t status, uint16_t int_enb);
|
||||
void usb1_function_nrdy_int(uint16_t status, uint16_t int_enb);
|
||||
void usb1_function_bemp_int(uint16_t status, uint16_t int_enb);
|
||||
void usb1_function_setting_interrupt(uint8_t level);
|
||||
void usb1_function_reset_module(uint16_t clockmode);
|
||||
uint16_t usb1_function_get_buf_size(uint16_t pipe);
|
||||
uint16_t usb1_function_get_mxps(uint16_t pipe);
|
||||
void usb1_function_clear_brdy_sts(uint16_t pipe);
|
||||
void usb1_function_clear_bemp_sts(uint16_t pipe);
|
||||
void usb1_function_clear_nrdy_sts(uint16_t pipe);
|
||||
void usb1_function_set_pid_buf(uint16_t pipe);
|
||||
void usb1_function_set_pid_nak(uint16_t pipe);
|
||||
void usb1_function_set_pid_stall(uint16_t pipe);
|
||||
void usb1_function_clear_pid_stall(uint16_t pipe);
|
||||
uint16_t usb1_function_get_pid(uint16_t pipe);
|
||||
void usb1_function_set_sqclr(uint16_t pipe);
|
||||
void usb1_function_set_sqset(uint16_t pipe);
|
||||
void usb1_function_set_csclr(uint16_t pipe);
|
||||
void usb1_function_aclrm(uint16_t pipe);
|
||||
void usb1_function_set_aclrm(uint16_t pipe);
|
||||
void usb1_function_clr_aclrm(uint16_t pipe);
|
||||
uint16_t usb1_function_get_sqmon(uint16_t pipe);
|
||||
uint16_t usb1_function_get_inbuf(uint16_t pipe);
|
||||
|
||||
/* ==== function ==== */
|
||||
void usb1_function_init_status(void);
|
||||
void usb1_function_InitModule(uint16_t mode);
|
||||
uint16_t usb1_function_CheckVBUStaus(void);
|
||||
void usb1_function_USB_FUNCTION_Attach(void);
|
||||
void usb1_function_USB_FUNCTION_Detach(void);
|
||||
void usb1_function_USB_FUNCTION_BusReset(void);
|
||||
void usb1_function_USB_FUNCTION_Resume(void);
|
||||
void usb1_function_USB_FUNCTION_Suspend(void);
|
||||
void usb1_function_USB_FUNCTION_TestMode(void);
|
||||
void usb1_function_ResetDCP(void);
|
||||
void usb1_function_ResetEP(uint16_t num);
|
||||
uint16_t usb1_function_EpToPipe(uint16_t ep);
|
||||
void usb1_function_InitEPTable(uint16_t Con_Num, uint16_t Int_Num, uint16_t Alt_Num);
|
||||
uint16_t usb1_function_GetConfigNum(void);
|
||||
uint16_t usb1_function_GetAltNum(uint16_t Con_Num, uint16_t Int_Num);
|
||||
uint16_t usb1_function_CheckRemoteWakeup(void);
|
||||
void usb1_function_clear_alt(void);
|
||||
void usb1_function_clear_pipe_tbl(void);
|
||||
void usb1_function_clear_ep_table_index(void);
|
||||
uint16_t usb1_function_GetInterfaceNum(uint16_t num);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* USB1_FUNCTION_H */
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_function_api.h
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
*******************************************************************************/
|
||||
#ifndef USB1_FUNCTION_API_H
|
||||
#define USB1_FUNCTION_API_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Variable Externs
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
void usb1_api_function_init(uint8_t int_level, uint16_t mode, uint16_t clockmode);
|
||||
uint16_t usb1_api_function_IsConfigured(void);
|
||||
uint16_t usb1_function_GetDeviceState(void);
|
||||
uint16_t usb1_api_function_CtrlReadStart(uint32_t size, uint8_t *data);
|
||||
void usb1_api_function_CtrlWriteStart(uint32_t size, uint8_t *data);
|
||||
uint16_t usb1_api_function_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
|
||||
uint16_t usb1_api_function_check_pipe_status(uint16_t pipe, uint32_t *size);
|
||||
void usb1_api_function_clear_pipe_status(uint16_t pipe);
|
||||
void usb1_api_function_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
|
||||
void usb1_api_function_set_pid_buf(uint16_t pipe);
|
||||
void usb1_api_function_set_pid_nak(uint16_t pipe);
|
||||
void usb1_api_function_set_pid_stall(uint16_t pipe);
|
||||
void usb1_api_function_clear_pid_stall(uint16_t pipe);
|
||||
uint16_t usb1_api_function_get_pid(uint16_t pipe);
|
||||
int32_t usb1_api_function_check_stall(uint16_t pipe);
|
||||
void usb1_api_function_set_sqclr(uint16_t pipe);
|
||||
void usb1_api_function_set_sqset(uint16_t pipe);
|
||||
void usb1_api_function_set_csclr(uint16_t pipe);
|
||||
void usb1_api_function_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
|
||||
void usb1_api_function_clear_brdy_sts(uint16_t pipe);
|
||||
void usb1_api_function_clear_bemp_sts(uint16_t pipe);
|
||||
void usb1_api_function_clear_nrdy_sts(uint16_t pipe);
|
||||
|
||||
void usb1_function_ClearFeature(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
|
||||
void usb1_function_SetFeature(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
|
||||
void usb1_function_SetAddress(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
|
||||
void usb1_function_SetDescriptor(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
|
||||
void usb1_function_SetConfiguration(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
|
||||
void usb1_function_SetInterface(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
|
||||
void usb1_function_SynchFrame(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
|
||||
void usb1_function_GetStatus(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
|
||||
void usb1_function_GetDescriptor(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
|
||||
void usb1_function_GetConfiguration(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
|
||||
void usb1_function_GetInterface(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
|
||||
void usb1_function_Resrv_0(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
|
||||
void usb1_function_Resrv_123(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
|
||||
void usb1_function_Resrv_4(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
|
||||
void usb1_function_Resrv_5(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* USB1_FUNCTION_API_H */
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,142 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_function_dmacdrv.h
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
*******************************************************************************/
|
||||
#ifndef USB1_FUNCTION_DMACDRV_H
|
||||
#define USB1_FUNCTION_DMACDRV_H
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
typedef struct dmac_transinfo
|
||||
{
|
||||
uint32_t src_addr; /* Transfer source address */
|
||||
uint32_t dst_addr; /* Transfer destination address */
|
||||
uint32_t count; /* Transfer byte count */
|
||||
uint32_t src_size; /* Transfer source data size */
|
||||
uint32_t dst_size; /* Transfer destination data size */
|
||||
uint32_t saddr_dir; /* Transfer source address direction */
|
||||
uint32_t daddr_dir; /* Transfer destination address direction */
|
||||
} dmac_transinfo_t;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
/* ==== Transfer specification of the sample program ==== */
|
||||
#define DMAC_SAMPLE_SINGLE (0) /* Single transfer */
|
||||
#define DMAC_SAMPLE_CONTINUATION (1) /* Continuous transfer (use REN bit) */
|
||||
|
||||
/* ==== DMA modes ==== */
|
||||
#define DMAC_MODE_REGISTER (0) /* Register mode */
|
||||
#define DMAC_MODE_LINK (1) /* Link mode */
|
||||
|
||||
/* ==== Transfer requests ==== */
|
||||
#define DMAC_REQ_MODE_EXT (0) /* External request */
|
||||
#define DMAC_REQ_MODE_PERI (1) /* On-chip peripheral module request */
|
||||
#define DMAC_REQ_MODE_SOFT (2) /* Auto-request (request by software) */
|
||||
|
||||
/* ==== DMAC transfer sizes ==== */
|
||||
#define DMAC_TRANS_SIZE_8 (0) /* 8 bits */
|
||||
#define DMAC_TRANS_SIZE_16 (1) /* 16 bits */
|
||||
#define DMAC_TRANS_SIZE_32 (2) /* 32 bits */
|
||||
#define DMAC_TRANS_SIZE_64 (3) /* 64 bits */
|
||||
#define DMAC_TRANS_SIZE_128 (4) /* 128 bits */
|
||||
#define DMAC_TRANS_SIZE_256 (5) /* 256 bits */
|
||||
#define DMAC_TRANS_SIZE_512 (6) /* 512 bits */
|
||||
#define DMAC_TRANS_SIZE_1024 (7) /* 1024 bits */
|
||||
|
||||
/* ==== Address increment for transferring ==== */
|
||||
#define DMAC_TRANS_ADR_NO_INC (1) /* Not increment */
|
||||
#define DMAC_TRANS_ADR_INC (0) /* Increment */
|
||||
|
||||
/* ==== Method for detecting DMA request ==== */
|
||||
#define DMAC_REQ_DET_FALL (0) /* Falling edge detection */
|
||||
#define DMAC_REQ_DET_RISE (1) /* Rising edge detection */
|
||||
#define DMAC_REQ_DET_LOW (2) /* Low level detection */
|
||||
#define DMAC_REQ_DET_HIGH (3) /* High level detection */
|
||||
|
||||
/* ==== Request Direction ==== */
|
||||
#define DMAC_REQ_DIR_SRC (0) /* DMAREQ is the source/ DMAACK is active when reading */
|
||||
#define DMAC_REQ_DIR_DST (1) /* DMAREQ is the destination/ DMAACK is active when writing */
|
||||
|
||||
/* ==== Descriptors ==== */
|
||||
#define DMAC_DESC_HEADER (0) /* Header */
|
||||
#define DMAC_DESC_SRC_ADDR (1) /* Source Address */
|
||||
#define DMAC_DESC_DST_ADDR (2) /* Destination Address */
|
||||
#define DMAC_DESC_COUNT (3) /* Transaction Byte */
|
||||
#define DMAC_DESC_CHCFG (4) /* Channel Confg */
|
||||
#define DMAC_DESC_CHITVL (5) /* Channel Interval */
|
||||
#define DMAC_DESC_CHEXT (6) /* Channel Extension */
|
||||
#define DMAC_DESC_LINK_ADDR (7) /* Link Address */
|
||||
|
||||
/* ==== On-chip peripheral module requests ===== */
|
||||
typedef enum dmac_request_factor
|
||||
{
|
||||
DMAC_REQ_USB0_DMA0_TX, /* USB_0 channel 0 transmit FIFO empty */
|
||||
DMAC_REQ_USB0_DMA0_RX, /* USB_0 channel 0 receive FIFO full */
|
||||
DMAC_REQ_USB0_DMA1_TX, /* USB_0 channel 1 transmit FIFO empty */
|
||||
DMAC_REQ_USB0_DMA1_RX, /* USB_0 channel 1 receive FIFO full */
|
||||
DMAC_REQ_USB1_DMA0_TX, /* USB_1 channel 0 transmit FIFO empty */
|
||||
DMAC_REQ_USB1_DMA0_RX, /* USB_1 channel 0 receive FIFO full */
|
||||
DMAC_REQ_USB1_DMA1_TX, /* USB_1 channel 1 transmit FIFO empty */
|
||||
DMAC_REQ_USB1_DMA1_RX, /* USB_1 channel 1 receive FIFO full */
|
||||
} dmac_request_factor_t;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
void usb1_function_DMAC3_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
|
||||
uint32_t request_factor, uint32_t req_direction);
|
||||
int32_t usb1_function_DMAC3_Open(uint32_t req);
|
||||
void usb1_function_DMAC3_Close(uint32_t *remain);
|
||||
void usb1_function_DMAC3_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
|
||||
|
||||
void usb1_function_DMAC4_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
|
||||
uint32_t request_factor, uint32_t req_direction);
|
||||
int32_t usb1_function_DMAC4_Open(uint32_t req);
|
||||
void usb1_function_DMAC4_Close(uint32_t *remain);
|
||||
void usb1_function_DMAC4_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* USB1_FUNCTION_DMACDRV_H */
|
||||
|
||||
/* End of File */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,346 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_function_dma.c
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Device(s) : RZ/A1H
|
||||
* Tool-Chain :
|
||||
* OS : None
|
||||
* H/W Platform :
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
* Operation :
|
||||
* Limitations :
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include "usb1_function.h"
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private global variables and functions
|
||||
*******************************************************************************/
|
||||
static void usb1_function_dmaint(uint16_t fifo);
|
||||
static void usb1_function_dmaint_buf2fifo(uint16_t pipe);
|
||||
static void usb1_function_dmaint_fifo2buf(uint16_t pipe);
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_dma_stop_d0
|
||||
* Description : D0FIFO DMA stop
|
||||
* Arguments : uint16_t pipe : pipe number
|
||||
* : uint32_t remain : transfer byte
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_function_dma_stop_d0 (uint16_t pipe, uint32_t remain)
|
||||
{
|
||||
uint16_t dtln;
|
||||
uint16_t dfacc;
|
||||
uint16_t buffer;
|
||||
uint16_t sds_b = 1;
|
||||
|
||||
dfacc = RZA_IO_RegRead_16(&USB201.D0FBCFG, USB_DnFBCFG_DFACC_SHIFT, USB_DnFBCFG_DFACC);
|
||||
|
||||
if (dfacc == 2)
|
||||
{
|
||||
sds_b = 32;
|
||||
}
|
||||
else if (dfacc == 1)
|
||||
{
|
||||
sds_b = 16;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size == 2)
|
||||
{
|
||||
sds_b = 4;
|
||||
}
|
||||
else if (g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size == 1)
|
||||
{
|
||||
sds_b = 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
sds_b = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
|
||||
{
|
||||
if (g_usb1_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE)
|
||||
{
|
||||
buffer = USB201.D0FIFOCTR;
|
||||
dtln = (buffer & USB_FUNCTION_BITDTLN);
|
||||
|
||||
if ((dtln % sds_b) != 0)
|
||||
{
|
||||
remain += (sds_b - (dtln % sds_b));
|
||||
}
|
||||
g_usb1_function_PipeDataSize[pipe] = (g_usb1_function_data_count[pipe] - remain);
|
||||
g_usb1_function_data_count[pipe] = remain;
|
||||
}
|
||||
}
|
||||
|
||||
RZA_IO_RegWrite_16(&USB201.D0FIFOSEL, 0, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_dma_stop_d1
|
||||
* Description : D1FIFO DMA stop
|
||||
* Arguments : uint16_t pipe : pipe number
|
||||
* : uint32_t remain : transfer byte
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_function_dma_stop_d1 (uint16_t pipe, uint32_t remain)
|
||||
{
|
||||
uint16_t dtln;
|
||||
uint16_t dfacc;
|
||||
uint16_t buffer;
|
||||
uint16_t sds_b = 1;
|
||||
|
||||
dfacc = RZA_IO_RegRead_16(&USB201.D1FBCFG, USB_DnFBCFG_DFACC_SHIFT, USB_DnFBCFG_DFACC);
|
||||
|
||||
if (dfacc == 2)
|
||||
{
|
||||
sds_b = 32;
|
||||
}
|
||||
else if (dfacc == 1)
|
||||
{
|
||||
sds_b = 16;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size == 2)
|
||||
{
|
||||
sds_b = 4;
|
||||
}
|
||||
else if (g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size == 1)
|
||||
{
|
||||
sds_b = 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
sds_b = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
|
||||
{
|
||||
if (g_usb1_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE)
|
||||
{
|
||||
buffer = USB201.D1FIFOCTR;
|
||||
dtln = (buffer & USB_FUNCTION_BITDTLN);
|
||||
|
||||
if ((dtln % sds_b) != 0)
|
||||
{
|
||||
remain += (sds_b - (dtln % sds_b));
|
||||
}
|
||||
g_usb1_function_PipeDataSize[pipe] = (g_usb1_function_data_count[pipe] - remain);
|
||||
g_usb1_function_data_count[pipe] = remain;
|
||||
}
|
||||
}
|
||||
|
||||
RZA_IO_RegWrite_16(&USB201.D1FIFOSEL, 0, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_dma_interrupt_d0fifo
|
||||
* Description : This function is DMA interrupt handler entry.
|
||||
* : Execute usb1_function_dmaint() after disabling DMA interrupt in this function.
|
||||
* : Disable DMA interrupt to DMAC executed when USB_FUNCTION_D0FIFO_DMA is
|
||||
* : specified by dma->fifo.
|
||||
* : Register this function as DMA complete interrupt.
|
||||
* Arguments : uint32_t int_sense ; Interrupts detection mode
|
||||
* : ; INTC_LEVEL_SENSITIVE : Level sense
|
||||
* : ; INTC_EDGE_TRIGGER : Edge trigger
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_function_dma_interrupt_d0fifo (uint32_t int_sense)
|
||||
{
|
||||
usb1_function_dmaint(USB_FUNCTION_D0FIFO);
|
||||
g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_READY;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_dma_interrupt_d1fifo
|
||||
* Description : This function is DMA interrupt handler entry.
|
||||
* : Execute usb1_function_dmaint() after disabling DMA interrupt in this function.
|
||||
* : Disable DMA interrupt to DMAC executed when USB_FUNCTION_D1FIFO_DMA is
|
||||
* : specified by dma->fifo.
|
||||
* : Register this function as DMA complete interrupt.
|
||||
* Arguments : uint32_t int_sense ; Interrupts detection mode
|
||||
* : ; INTC_LEVEL_SENSITIVE : Level sense
|
||||
* : ; INTC_EDGE_TRIGGER : Edge trigger
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_function_dma_interrupt_d1fifo (uint32_t int_sense)
|
||||
{
|
||||
usb1_function_dmaint(USB_FUNCTION_D1FIFO);
|
||||
g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_READY;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_dmaint
|
||||
* Description : This function is DMA transfer end interrupt
|
||||
* Arguments : uint16_t fifo ; fifo number
|
||||
* : ; USB_FUNCTION_D0FIFO
|
||||
* : ; USB_FUNCTION_D1FIFO
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
static void usb1_function_dmaint (uint16_t fifo)
|
||||
{
|
||||
uint16_t pipe;
|
||||
|
||||
pipe = g_usb1_function_DmaPipe[fifo];
|
||||
|
||||
if (g_usb1_function_DmaInfo[fifo].dir == USB_FUNCTION_BUF2FIFO)
|
||||
{
|
||||
usb1_function_dmaint_buf2fifo(pipe);
|
||||
}
|
||||
else
|
||||
{
|
||||
usb1_function_dmaint_fifo2buf(pipe);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_dmaint_fifo2buf
|
||||
* Description : Executes read completion from FIFO by DMAC.
|
||||
* Arguments : uint16_t pipe : pipe number
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
static void usb1_function_dmaint_fifo2buf (uint16_t pipe)
|
||||
{
|
||||
uint32_t remain;
|
||||
uint16_t useport;
|
||||
|
||||
if (g_usb1_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE)
|
||||
{
|
||||
useport = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
|
||||
|
||||
if (useport == USB_FUNCTION_D0FIFO_DMA)
|
||||
{
|
||||
remain = Userdef_USB_usb1_function_stop_dma0();
|
||||
usb1_function_dma_stop_d0(pipe, remain);
|
||||
|
||||
if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
|
||||
{
|
||||
if (g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] == USB_FUNCTION_DMA_BUSYEND)
|
||||
{
|
||||
USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR;
|
||||
g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
usb1_function_enable_brdy_int(pipe);
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
remain = Userdef_USB_usb1_function_stop_dma1();
|
||||
usb1_function_dma_stop_d1(pipe, remain);
|
||||
|
||||
if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
|
||||
{
|
||||
if (g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] == USB_FUNCTION_DMA_BUSYEND)
|
||||
{
|
||||
USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR;
|
||||
g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
usb1_function_enable_brdy_int(pipe);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_dmaint_buf2fifo
|
||||
* Description : Executes write completion in FIFO by DMAC.
|
||||
* Arguments : uint16_t pipe : pipe number
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
static void usb1_function_dmaint_buf2fifo (uint16_t pipe)
|
||||
{
|
||||
uint32_t remain;
|
||||
uint16_t useport;
|
||||
|
||||
useport = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
|
||||
|
||||
if (useport == USB_FUNCTION_D0FIFO_DMA)
|
||||
{
|
||||
remain = Userdef_USB_usb1_function_stop_dma0();
|
||||
usb1_function_dma_stop_d0(pipe, remain);
|
||||
|
||||
if (g_usb1_function_DmaBval[USB_FUNCTION_D0FIFO] != 0)
|
||||
{
|
||||
RZA_IO_RegWrite_16(&USB201.D0FIFOCTR,
|
||||
1,
|
||||
USB_DnFIFOCTR_BVAL_SHIFT,
|
||||
USB_DnFIFOCTR_BVAL);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
remain = Userdef_USB_usb1_function_stop_dma1();
|
||||
usb1_function_dma_stop_d1(pipe, remain);
|
||||
|
||||
if (g_usb1_function_DmaBval[USB_FUNCTION_D1FIFO] != 0)
|
||||
{
|
||||
RZA_IO_RegWrite_16(&USB201.D1FIFOCTR,
|
||||
1,
|
||||
USB_DnFIFOCTR_BVAL_SHIFT,
|
||||
USB_DnFIFOCTR_BVAL);
|
||||
}
|
||||
}
|
||||
|
||||
usb1_function_enable_bemp_int(pipe);
|
||||
}
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,249 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_function_intrn.c
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Device(s) : RZ/A1H
|
||||
* Tool-Chain :
|
||||
* OS : None
|
||||
* H/W Platform :
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
* Operation :
|
||||
* Limitations :
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include "usb1_function.h"
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private global variables and functions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_brdy_int
|
||||
* Description : Executes BRDY interrupt(USB_FUNCTION_PIPE1-9).
|
||||
* : According to the pipe that interrupt is generated in,
|
||||
* : reads/writes buffer allocated in the pipe.
|
||||
* : This function is executed in the BRDY interrupt handler.
|
||||
* : This function clears BRDY interrupt status and BEMP interrupt
|
||||
* : status.
|
||||
* Arguments : uint16_t Status ; BRDYSTS Register Value
|
||||
* : uint16_t Int_enbl ; BRDYENB Register Value
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
#if 0
|
||||
void usb1_function_brdy_int (uint16_t status, uint16_t int_enb)
|
||||
{
|
||||
uint32_t int_sense = 0;
|
||||
uint16_t pipe;
|
||||
uint16_t pipebit;
|
||||
|
||||
for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
|
||||
{
|
||||
pipebit = g_usb1_function_bit_set[pipe];
|
||||
|
||||
if ((status & pipebit) && (int_enb & pipebit))
|
||||
{
|
||||
USB201.BRDYSTS = (uint16_t)~pipebit;
|
||||
USB201.BEMPSTS = (uint16_t)~pipebit;
|
||||
if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA)
|
||||
{
|
||||
if (g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] != USB_FUNCTION_DMA_READY)
|
||||
{
|
||||
usb1_function_dma_interrupt_d0fifo(int_sense);
|
||||
}
|
||||
|
||||
if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
|
||||
{
|
||||
usb1_function_read_dma(pipe);
|
||||
usb1_function_disable_brdy_int(pipe);
|
||||
}
|
||||
else
|
||||
{
|
||||
USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR;
|
||||
g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
|
||||
}
|
||||
}
|
||||
else if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_DMA)
|
||||
{
|
||||
if (g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] != USB_FUNCTION_DMA_READY)
|
||||
{
|
||||
usb1_function_dma_interrupt_d1fifo(int_sense);
|
||||
}
|
||||
|
||||
if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
|
||||
{
|
||||
usb1_function_read_dma(pipe);
|
||||
usb1_function_disable_brdy_int(pipe);
|
||||
}
|
||||
else
|
||||
{
|
||||
USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR;
|
||||
g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
|
||||
{
|
||||
usb1_function_read_buffer(pipe);
|
||||
}
|
||||
else
|
||||
{
|
||||
usb1_function_write_buffer(pipe);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_nrdy_int
|
||||
* Description : Executes NRDY interrupt(USB_FUNCTION_PIPE1-9).
|
||||
* : Checks NRDY interrupt cause by PID. When the cause if STALL,
|
||||
* : regards the pipe state as STALL and ends the processing.
|
||||
* : Then the cause is not STALL, increments the error count to
|
||||
* : communicate again. When the error count is 3, determines
|
||||
* : the pipe state as DEVDRV_USBF_PIPE_NORES and ends the processing.
|
||||
* : This function is executed in the NRDY interrupt handler.
|
||||
* : This function clears NRDY interrupt status.
|
||||
* Arguments : uint16_t status ; NRDYSTS Register Value
|
||||
* : uint16_t int_enb ; NRDYENB Register Value
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_function_nrdy_int (uint16_t status, uint16_t int_enb)
|
||||
{
|
||||
uint16_t pid;
|
||||
uint16_t pipe;
|
||||
uint16_t bitcheck;
|
||||
|
||||
bitcheck = (uint16_t)(status & int_enb);
|
||||
|
||||
USB201.NRDYSTS = (uint16_t)~status;
|
||||
|
||||
for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
|
||||
{
|
||||
if ((bitcheck&g_usb1_function_bit_set[pipe]) == g_usb1_function_bit_set[pipe])
|
||||
{
|
||||
if (RZA_IO_RegRead_16(&USB201.SYSCFG0, USB_SYSCFG_DCFM_SHIFT, USB_SYSCFG_DCFM) == 1)
|
||||
{
|
||||
if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_WAIT)
|
||||
{
|
||||
pid = usb1_function_get_pid(pipe);
|
||||
if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2))
|
||||
{
|
||||
g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL;
|
||||
}
|
||||
else
|
||||
{
|
||||
g_usb1_function_PipeIgnore[pipe]++;
|
||||
if (g_usb1_function_PipeIgnore[pipe] == 3)
|
||||
{
|
||||
g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_NORES;
|
||||
}
|
||||
else
|
||||
{
|
||||
usb1_function_set_pid_buf(pipe);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* USB Function */
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_bemp_int
|
||||
* Description : Executes BEMP interrupt(USB_FUNCTION_PIPE1-9).
|
||||
* Arguments : uint16_t status ; BEMPSTS Register Value
|
||||
* : uint16_t int_enb ; BEMPENB Register Value
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_function_bemp_int (uint16_t status, uint16_t int_enb)
|
||||
{
|
||||
uint16_t pid;
|
||||
uint16_t pipe;
|
||||
uint16_t bitcheck;
|
||||
uint16_t inbuf;
|
||||
|
||||
bitcheck = (uint16_t)(status & int_enb);
|
||||
|
||||
USB201.BEMPSTS = (uint16_t)~status;
|
||||
|
||||
for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
|
||||
{
|
||||
if ((bitcheck&g_usb1_function_bit_set[pipe]) == g_usb1_function_bit_set[pipe])
|
||||
{
|
||||
pid = usb1_function_get_pid(pipe);
|
||||
|
||||
if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2))
|
||||
{
|
||||
g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL;
|
||||
}
|
||||
else
|
||||
{
|
||||
inbuf = usb1_function_get_inbuf(pipe);
|
||||
|
||||
if (inbuf == 0)
|
||||
{
|
||||
usb1_function_disable_bemp_int(pipe);
|
||||
usb1_function_set_pid_nak(pipe);
|
||||
g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* End of File */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,441 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_function_api.c
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Device(s) : RZ/A1H
|
||||
* Tool-Chain :
|
||||
* OS : None
|
||||
* H/W Platform :
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
* Operation :
|
||||
* Limitations :
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include "usb1_function.h"
|
||||
#include "dev_drv.h"
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private global variables and functions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_init
|
||||
* Description : Initializes the USB module in the USB function mode.
|
||||
* Arguments : uint8_t int_level ; interruput level
|
||||
* : uint16_t mode : Speed modes
|
||||
* : : USB_FUCNTION_HIGH_SPEED: High-speed device
|
||||
* : : USB_FUCNTION_FULL_SPEED: Full-speed device
|
||||
* : uint16_t clockmode ; 48MHz ; USBFCLOCK_X1_48MHZ
|
||||
* : ; 12MHz ; USBFCLOCK_EXTAL_12MHZ
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
#if 0
|
||||
void usb1_api_function_init (uint8_t int_level, uint16_t mode, uint16_t clockmode)
|
||||
{
|
||||
volatile uint8_t dummy_buf;
|
||||
|
||||
CPG.STBCR7 &= 0xfc; /*The clock of USB0/1 modules is permitted */
|
||||
dummy_buf = CPG.STBCR7; /* (Dummy read) */
|
||||
|
||||
usb1_function_setting_interrupt(int_level);
|
||||
|
||||
usb1_function_reset_module(clockmode); /* reset USB module with setting tranciever */
|
||||
/* and HSE=1 */
|
||||
|
||||
usb1_function_init_status(); /* clear variables */
|
||||
|
||||
usb1_function_InitModule(mode); /* select USB Function and Interrupt Enable */
|
||||
/* Detect USB Device to attach or detach */
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_IsConfigured
|
||||
* Description : Checks if the USB device is configured to return the result as
|
||||
* : the return value.
|
||||
* Arguments : none
|
||||
* Return Value : DEVDRV_USBF_YES : Configured & Configured Suspend
|
||||
* : DEVDRV_USBF_NO : not Configured
|
||||
*******************************************************************************/
|
||||
uint16_t usb1_api_function_IsConfigured (void)
|
||||
{
|
||||
uint16_t dvst;
|
||||
|
||||
dvst = usb1_function_GetDeviceState();
|
||||
|
||||
if ((dvst == USB_FUNCTION_DVST_CONFIGURED) ||
|
||||
(dvst == USB_FUNCTION_DVST_CONFIGURED_SUSPEND))
|
||||
{
|
||||
return DEVDRV_USBF_YES;
|
||||
}
|
||||
|
||||
return DEVDRV_USBF_NO;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_GetDeviceState
|
||||
* Description : Returns the state of USB device.
|
||||
* Arguments : none
|
||||
* Return Value : Device States
|
||||
*******************************************************************************/
|
||||
uint16_t usb1_function_GetDeviceState (void)
|
||||
{
|
||||
uint16_t dvsq;
|
||||
uint16_t dvst;
|
||||
|
||||
dvsq = USB201.INTSTS0;
|
||||
switch (dvsq & USB_FUNCTION_BITDVSQ)
|
||||
{
|
||||
case USB_FUNCTION_DS_POWR: /* Power state *//* power-on */
|
||||
dvst = USB_FUNCTION_DVST_POWERED;
|
||||
break;
|
||||
|
||||
case USB_FUNCTION_DS_DFLT: /* Default state *//* bus-reset */
|
||||
dvst = USB_FUNCTION_DVST_DEFAULT;
|
||||
break;
|
||||
|
||||
case USB_FUNCTION_DS_ADDS: /* Address state */
|
||||
dvst = USB_FUNCTION_DVST_ADDRESS;
|
||||
break;
|
||||
|
||||
case USB_FUNCTION_DS_CNFG: /* Configured state */
|
||||
dvst = USB_FUNCTION_DVST_CONFIGURED;
|
||||
break;
|
||||
|
||||
case USB_FUNCTION_DS_SPD_CNFG: /* Configured Suspend state */
|
||||
dvst = USB_FUNCTION_DVST_CONFIGURED_SUSPEND;
|
||||
break;
|
||||
|
||||
case USB_FUNCTION_DS_SPD_POWR: /* Power Suspend state */
|
||||
case USB_FUNCTION_DS_SPD_DFLT: /* Default Suspend state */
|
||||
case USB_FUNCTION_DS_SPD_ADDR: /* Address Suspend state */
|
||||
dvst = USB_FUNCTION_DVST_SUSPEND;
|
||||
break;
|
||||
|
||||
default: /* error */
|
||||
dvst = USB_FUNCTION_DVST_SUSPEND;
|
||||
break;
|
||||
}
|
||||
|
||||
return dvst;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_start_receive_transfer
|
||||
* Description : Starts USB data reception using the pipe specified in the argument.
|
||||
* : The FIFO for using is set in the pipe definition table.
|
||||
* Arguments : uint16_t pipe ; Pipe Number
|
||||
* : uint32_t size ; Data Size
|
||||
* : uint8_t *data ; Data data Address
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_api_function_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
|
||||
{
|
||||
usb1_function_start_receive_transfer(pipe, size, data);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_start_send_transfer
|
||||
* Description : Starts the USB data communication using pipe specified by the argument.
|
||||
* Arguments : uint16_t pipe ; Pipe Number
|
||||
* : uint32_t size ; Data Size
|
||||
* : uint8_t *data ; Data data Address
|
||||
* Return Value : DEVDRV_USBF_WRITEEND ; Write end
|
||||
* : DEVDRV_USBF_WRITESHRT ; short data
|
||||
* : DEVDRV_USBF_WRITING ; Continue of data write
|
||||
* : DEVDRV_USBF_WRITEDMA ; Write DMA
|
||||
* : DEVDRV_USBF_FIFOERROR ; FIFO status
|
||||
*******************************************************************************/
|
||||
uint16_t usb1_api_function_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
|
||||
{
|
||||
uint16_t status;
|
||||
|
||||
status = usb1_function_start_send_transfer(pipe, size, data);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_check_pipe_status
|
||||
* Description : Starts USB data reception using the pipe specified in the argument.
|
||||
* : The FIFO for using is set in the pipe definition table.
|
||||
* Arguments : uint16_t pipe ; Pipe Number
|
||||
* : uint32_t *size ; Data Size
|
||||
* Return Value : Pipe Status
|
||||
*******************************************************************************/
|
||||
uint16_t usb1_api_function_check_pipe_status (uint16_t pipe, uint32_t * size)
|
||||
{
|
||||
if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_DONE)
|
||||
{
|
||||
*size = g_usb1_function_PipeDataSize[pipe];
|
||||
g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
|
||||
|
||||
return DEVDRV_USBF_PIPE_DONE;
|
||||
}
|
||||
else if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_NORES)
|
||||
{
|
||||
*size = 0;
|
||||
g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
|
||||
|
||||
return DEVDRV_USBF_PIPE_NORES;
|
||||
}
|
||||
else if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_STALL)
|
||||
{
|
||||
*size = 0;
|
||||
g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
|
||||
|
||||
return DEVDRV_USBF_PIPE_STALL;
|
||||
}
|
||||
else if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_FIFOERROR)
|
||||
{
|
||||
*size = 0;
|
||||
g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
|
||||
|
||||
return DEVDRV_USBF_FIFOERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do Nothing */
|
||||
}
|
||||
|
||||
return g_usb1_function_pipe_status[pipe];
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_clear_pipe_status
|
||||
* Description : Starts USB data reception using the pipe specified in the argument.
|
||||
* : The FIFO for using is set in the pipe definition table.
|
||||
* Arguments : uint16_t pipe ; Pipe Number
|
||||
* Return Value : Pipe Status
|
||||
*******************************************************************************/
|
||||
void usb1_api_function_clear_pipe_status (uint16_t pipe)
|
||||
{
|
||||
g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
|
||||
g_usb1_function_PipeDataSize[pipe] = 0;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_set_pid_buf
|
||||
* Description : Enables communicaqtion in the pipe specified by the argument
|
||||
* : (BUF).
|
||||
* Arguments : uint16_t pipe ; pipe Number
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_api_function_set_pid_buf (uint16_t pipe)
|
||||
{
|
||||
usb1_function_set_pid_buf(pipe);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_set_pid_nak
|
||||
* Description : Disables communication (NAK) in the pipe specified by the argument.
|
||||
* : When the pipe status was enabling communication (BUF) before
|
||||
* : executing before executing this function, waits in the software
|
||||
* : until the pipe becomes ready after setting disabled.
|
||||
* Arguments : uint16_t pipe ; pipe Number
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_api_function_set_pid_nak (uint16_t pipe)
|
||||
{
|
||||
usb1_function_set_pid_nak(pipe);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_set_pid_stall
|
||||
* Description : Disables communication (STALL) in the pipe specified by the
|
||||
* : argument.
|
||||
* Arguments : uint16_t pipe ; pipe Number
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_api_function_set_pid_stall (uint16_t pipe)
|
||||
{
|
||||
usb1_function_set_pid_stall(pipe);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_clear_pid_stall
|
||||
* Description : Disables communication (NAK) in the pipe specified by the argument.
|
||||
* Arguments : uint16_t pipe ; pipe Number
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_api_function_clear_pid_stall (uint16_t pipe)
|
||||
{
|
||||
usb1_function_clear_pid_stall(pipe);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_get_pid
|
||||
* Description : Returns the pipe state specified by the argument.
|
||||
* Arguments : uint16_t pipe ; Pipe Number
|
||||
* Return Value : PID
|
||||
*******************************************************************************/
|
||||
uint16_t usb1_api_function_get_pid (uint16_t pipe)
|
||||
{
|
||||
uint16_t pid;
|
||||
|
||||
pid = usb1_function_get_pid(pipe);
|
||||
|
||||
return pid;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_check_stall
|
||||
* Description :
|
||||
* Arguments : uint16_t pipe ; Pipe Number
|
||||
* Return Value : PID
|
||||
*******************************************************************************/
|
||||
int32_t usb1_api_function_check_stall (uint16_t pipe)
|
||||
{
|
||||
uint16_t pid;
|
||||
|
||||
pid = usb1_function_get_pid(pipe);
|
||||
|
||||
if ((pid & DEVDRV_USBF_PID_STALL) == DEVDRV_USBF_PID_STALL)
|
||||
{
|
||||
return DEVDRV_USBF_STALL;
|
||||
}
|
||||
|
||||
return DEVDRV_SUCCESS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_set_sqclr
|
||||
* Description : Sets the sequence bit of the pipe specified by the argument to
|
||||
* : DATA0.
|
||||
* Arguments : uint16_t pipe ; Pipe Number
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_api_function_set_sqclr (uint16_t pipe)
|
||||
{
|
||||
usb1_function_set_sqclr(pipe);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_set_sqset
|
||||
* Description : Sets the sequence bit of the pipe specified by the argument to
|
||||
* : DATA1.
|
||||
* Arguments : uint16_t pipe ; Pipe number
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_api_function_set_sqset (uint16_t pipe)
|
||||
{
|
||||
usb1_function_set_sqset(pipe);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_set_csclr
|
||||
* Description : CSPLIT status clear setting of sprit transaction in specified
|
||||
* : pipe is performed.
|
||||
* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit
|
||||
* : in DCPCTR register are continuously changed (when the sequence
|
||||
* : toggle bit of data PID is continuously changed over two or more pipes),
|
||||
* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary.
|
||||
* : Do not set both SQCLR bit and SQSET bit to 1 at the same time.
|
||||
* : In addition, both bits should be operated after PID is set to NAK.
|
||||
* : However, when it is set to the isochronous transfer as the transfer type
|
||||
* : (TYPE=11), writing in SQSET bit is disabled.
|
||||
* Arguments : uint16_t pipe ; Pipe number
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_api_function_set_csclr (uint16_t pipe)
|
||||
{
|
||||
usb1_function_set_csclr(pipe);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_set_curpipe
|
||||
* Description : Allocates FIF0 specifed by the argument in the pipe assigned
|
||||
* : by the argument.
|
||||
* Arguments : uint16_t pipe ; Pipe Number
|
||||
* : uint16_t fifosel ; Select FIFO
|
||||
* : uint16_t isel ; FIFO Access Direction
|
||||
* : uint16_t mbw ; FIFO Port Access Bit Width
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_api_function_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
|
||||
{
|
||||
usb1_function_set_curpipe(pipe, fifosel, isel, mbw);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_clear_brdy_sts
|
||||
* Description : Clear BRDY interrupt status in the pipe spceified by the argument.
|
||||
* Arguments : uint16_t pipe ; pipe Number
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_api_function_clear_brdy_sts (uint16_t pipe)
|
||||
{
|
||||
usb1_function_clear_brdy_sts(pipe);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_clear_bemp_sts
|
||||
* Description : Clear BEMP interrupt status in the pipe spceified by the argument.
|
||||
* Arguments : uint16_t pipe ; pipe Number
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_api_function_clear_bemp_sts (uint16_t pipe)
|
||||
{
|
||||
usb1_function_clear_bemp_sts(pipe);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_clear_nrdy_sts
|
||||
* Description : Clear NRDY interrupt status in the pipe spceified by the argument.
|
||||
* Arguments : uint16_t pipe ; pipe Number
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_api_function_clear_nrdy_sts (uint16_t pipe)
|
||||
{
|
||||
usb1_function_clear_nrdy_sts(pipe);
|
||||
}
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,142 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_function_controlrw.c
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Device(s) : RZ/A1H
|
||||
* Tool-Chain :
|
||||
* OS : None
|
||||
* H/W Platform :
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
* Operation :
|
||||
* Limitations :
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include "usb1_function.h"
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private global variables and functions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_CtrlReadStart
|
||||
* Description : Executes the USB control read transfer.
|
||||
* : USB host controller <- USB device
|
||||
* Arguments : uint16_t size ; Data Size
|
||||
* : uint8_t *data ; Data Address
|
||||
* Return Value : DEVDRV_USBF_WRITEEND ; End of data write
|
||||
* : DEVDRV_USBF_WRITESHRT ; End of short data write
|
||||
* : DEVDRV_USBF_WRITING ; Continue of data write
|
||||
* : DEVDRV_USBF_FIFOERROR ; FIFO access error
|
||||
*******************************************************************************/
|
||||
uint16_t usb1_api_function_CtrlReadStart (uint32_t size, uint8_t * data)
|
||||
{
|
||||
uint16_t status;
|
||||
uint16_t mbw;
|
||||
|
||||
usb1_function_set_pid_nak(USB_FUNCTION_PIPE0);
|
||||
|
||||
g_usb1_function_data_count[USB_FUNCTION_PIPE0] = size;
|
||||
g_usb1_function_data_pointer[USB_FUNCTION_PIPE0] = data;
|
||||
|
||||
mbw = usb1_function_get_mbw(g_usb1_function_data_count[USB_FUNCTION_PIPE0],
|
||||
(uint32_t)g_usb1_function_data_pointer[USB_FUNCTION_PIPE0]);
|
||||
usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw);
|
||||
USB201.CFIFOCTR = USB_FUNCTION_BITBCLR;
|
||||
|
||||
status = usb1_function_write_buffer_c(USB_FUNCTION_PIPE0);
|
||||
|
||||
/* Peripheral Control sequence */
|
||||
switch (status)
|
||||
{
|
||||
case DEVDRV_USBF_WRITESHRT: /* End of data write */
|
||||
case DEVDRV_USBF_WRITEEND: /* End of data write (not null) */
|
||||
case DEVDRV_USBF_WRITING: /* Continue of data write */
|
||||
usb1_function_enable_bemp_int(USB_FUNCTION_PIPE0); /* Enable Empty Interrupt */
|
||||
usb1_function_set_pid_buf(USB_FUNCTION_PIPE0); /* Set BUF */
|
||||
break;
|
||||
|
||||
case DEVDRV_USBF_FIFOERROR: /* FIFO access error */
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return status; /* End or Err or Continue */
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_function_CtrlWriteStart
|
||||
* Description : Executes the USB control write transfer.
|
||||
* : USB host controller -> USB device
|
||||
* Arguments : uint16_t size ; Data Size
|
||||
* : uint8_t *data ; Data Address
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_api_function_CtrlWriteStart (uint32_t size, uint8_t * data)
|
||||
{
|
||||
uint16_t mbw;
|
||||
|
||||
usb1_function_set_pid_nak(USB_FUNCTION_PIPE0);
|
||||
|
||||
g_usb1_function_data_count[USB_FUNCTION_PIPE0] = size;
|
||||
g_usb1_function_data_pointer[USB_FUNCTION_PIPE0] = data;
|
||||
|
||||
mbw = usb1_function_get_mbw(g_usb1_function_data_count[USB_FUNCTION_PIPE0],
|
||||
(uint32_t)g_usb1_function_data_pointer[USB_FUNCTION_PIPE0]);
|
||||
usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw);
|
||||
USB201.CFIFOCTR = USB_FUNCTION_BITBCLR;
|
||||
|
||||
usb1_function_enable_brdy_int(USB_FUNCTION_PIPE0);
|
||||
usb1_function_set_pid_buf(USB_FUNCTION_PIPE0);
|
||||
}
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,144 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_function_global.c
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Device(s) : RZ/A1H
|
||||
* Tool-Chain :
|
||||
* OS : None
|
||||
* H/W Platform :
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
* Operation :
|
||||
* Limitations :
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include "usb1_function.h"
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private global variables and functions
|
||||
*******************************************************************************/
|
||||
const uint16_t g_usb1_function_bit_set[16] =
|
||||
{
|
||||
0x0001, 0x0002, 0x0004, 0x0008,
|
||||
0x0010, 0x0020, 0x0040, 0x0080,
|
||||
0x0100, 0x0200, 0x0400, 0x0800,
|
||||
0x1000, 0x2000, 0x4000, 0x8000
|
||||
};
|
||||
|
||||
uint32_t g_usb1_function_data_count[USB_FUNCTION_MAX_PIPE_NO + 1];
|
||||
uint8_t * g_usb1_function_data_pointer[USB_FUNCTION_MAX_PIPE_NO + 1];
|
||||
|
||||
uint16_t g_usb1_function_PipeIgnore[USB_FUNCTION_MAX_PIPE_NO + 1];
|
||||
uint16_t g_usb1_function_PipeTbl[USB_FUNCTION_MAX_PIPE_NO + 1];
|
||||
uint16_t g_usb1_function_pipe_status[USB_FUNCTION_MAX_PIPE_NO + 1];
|
||||
uint32_t g_usb1_function_PipeDataSize[USB_FUNCTION_MAX_PIPE_NO + 1];
|
||||
|
||||
USB_FUNCTION_DMA_t g_usb1_function_DmaInfo[2];
|
||||
uint16_t g_usb1_function_DmaPipe[2];
|
||||
uint16_t g_usb1_function_DmaBval[2];
|
||||
uint16_t g_usb1_function_DmaStatus[2];
|
||||
|
||||
uint16_t g_usb1_function_CtrZeroLengthFlag;
|
||||
|
||||
//uint16_t g_usb1_function_ConfigNum;
|
||||
//uint16_t g_usb1_function_Alternate[USB_FUNCTION_ALT_NO];
|
||||
//uint16_t g_usb1_function_RemoteWakeupFlag;
|
||||
uint16_t g_usb1_function_TestModeFlag;
|
||||
uint16_t g_usb1_function_TestModeSelectors;
|
||||
|
||||
//uint16_t g_usb1_function_ReqType;
|
||||
//uint16_t g_usb1_function_ReqTypeType;
|
||||
//uint16_t g_usb1_function_ReqTypeRecip;
|
||||
//uint16_t g_usb1_function_ReqRequest;
|
||||
//uint16_t g_usb1_function_ReqValue;
|
||||
//uint16_t g_usb1_function_ReqIndex;
|
||||
//uint16_t g_usb1_function_ReqLength;
|
||||
|
||||
//uint16_t g_usb1_function_EPTableIndex[USB_FUNCTION_MAX_EP_NO + 1];
|
||||
|
||||
uint16_t g_usb1_function_pipecfg[USB_FUNCTION_MAX_PIPE_NO + 1];
|
||||
uint16_t g_usb1_function_pipebuf[USB_FUNCTION_MAX_PIPE_NO + 1];
|
||||
uint16_t g_usb1_function_pipemaxp[USB_FUNCTION_MAX_PIPE_NO + 1];
|
||||
uint16_t g_usb1_function_pipeperi[USB_FUNCTION_MAX_PIPE_NO + 1];
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_init_status
|
||||
* Description : Initialization USB Sample Driver Variable.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_function_init_status (void)
|
||||
{
|
||||
uint16_t pipe;
|
||||
|
||||
//g_usb1_function_ConfigNum = 0;
|
||||
//g_usb1_function_RemoteWakeupFlag = DEVDRV_USBF_OFF;
|
||||
g_usb1_function_TestModeFlag = DEVDRV_USBF_OFF;
|
||||
g_usb1_function_CtrZeroLengthFlag = 0;
|
||||
|
||||
#if 0
|
||||
usb1_function_clear_alt();
|
||||
#endif
|
||||
|
||||
for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe)
|
||||
{
|
||||
g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
|
||||
g_usb1_function_PipeDataSize[pipe] = 0;
|
||||
g_usb1_function_data_count[pipe] = 0;
|
||||
|
||||
/* pipe configuration in usb1_function_ResetEP() */
|
||||
g_usb1_function_pipecfg[pipe] = 0;
|
||||
g_usb1_function_pipebuf[pipe] = 0;
|
||||
g_usb1_function_pipemaxp[pipe] = 0;
|
||||
g_usb1_function_pipeperi[pipe] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,330 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_function_sig.c
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Device(s) : RZ/A1H
|
||||
* Tool-Chain :
|
||||
* OS : None
|
||||
* H/W Platform :
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
* Operation :
|
||||
* Limitations :
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include "usb1_function.h"
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
static void usb1_function_EnableINTModule(void);
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private global variables and functions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_InitModule
|
||||
* Description : Initializes the USB module in the USB function mode.
|
||||
* Arguments : uint16_t mode ; USB_FUNCTION_HIGH_SPEED ; Hi-Speed Mode
|
||||
* : ; other ; Full-speed Mode
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_function_InitModule (uint16_t mode)
|
||||
{
|
||||
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
|
||||
0,
|
||||
USB_SYSCFG_DCFM_SHIFT,
|
||||
USB_SYSCFG_DCFM); /* USB function */
|
||||
|
||||
/* USB module operation enabled */
|
||||
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
|
||||
1,
|
||||
USB_SYSCFG_USBE_SHIFT,
|
||||
USB_SYSCFG_USBE);
|
||||
|
||||
if (mode == USB_FUNCTION_HIGH_SPEED)
|
||||
{
|
||||
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
|
||||
1,
|
||||
USB_SYSCFG_HSE_SHIFT,
|
||||
USB_SYSCFG_HSE); /* Hi-Speed Mode */
|
||||
}
|
||||
else
|
||||
{
|
||||
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
|
||||
0,
|
||||
USB_SYSCFG_HSE_SHIFT,
|
||||
USB_SYSCFG_HSE);
|
||||
}
|
||||
|
||||
/* for power-on */
|
||||
if (usb1_function_CheckVBUStaus() == DEVDRV_USBF_ON)
|
||||
{
|
||||
usb1_function_EnableINTModule(); /* Interrupt Enable */
|
||||
usb1_function_USB_FUNCTION_Attach(); /* pull-up D+ and open D- */
|
||||
}
|
||||
else
|
||||
{
|
||||
usb1_function_USB_FUNCTION_Detach(); /* USB Detach */
|
||||
/* with Interrupt Enable */
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_CheckVBUStaus
|
||||
* Description : Checks the USB-VBUS state to returns the connection state to
|
||||
* : the USB host.
|
||||
* Arguments : none
|
||||
* Return Value : DEVDRV_USBF_ON : VBUS ON
|
||||
* : DEVDRV_USBF_OFF : VBUS OFF
|
||||
*******************************************************************************/
|
||||
uint16_t usb1_function_CheckVBUStaus (void)
|
||||
{
|
||||
uint16_t buf1;
|
||||
uint16_t buf2;
|
||||
uint16_t buf3;
|
||||
|
||||
/* monitor VBUS pins */
|
||||
do
|
||||
{
|
||||
buf1 = RZA_IO_RegRead_16(&USB201.INTSTS0,
|
||||
USB_INTSTS0_VBSTS_SHIFT,
|
||||
USB_INTSTS0_VBSTS);
|
||||
Userdef_USB_usb1_function_delay_10us(1);
|
||||
buf2 = RZA_IO_RegRead_16(&USB201.INTSTS0,
|
||||
USB_INTSTS0_VBSTS_SHIFT,
|
||||
USB_INTSTS0_VBSTS);
|
||||
Userdef_USB_usb1_function_delay_10us(1);
|
||||
buf3 = RZA_IO_RegRead_16(&USB201.INTSTS0,
|
||||
USB_INTSTS0_VBSTS_SHIFT,
|
||||
USB_INTSTS0_VBSTS);
|
||||
} while ((buf1 != buf2) || (buf2 != buf3));
|
||||
|
||||
if (buf1 == DEVDRV_USBF_OFF)
|
||||
{
|
||||
return DEVDRV_USBF_OFF; /* detach */
|
||||
}
|
||||
|
||||
return DEVDRV_USBF_ON; /* attach */
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_USB_FUNCTION_Attach
|
||||
* Description : Connects to the USB host controller.
|
||||
* : This function pulls up D+.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_function_USB_FUNCTION_Attach (void)
|
||||
{
|
||||
Userdef_USB_usb1_function_attach();
|
||||
|
||||
Userdef_USB_usb1_function_delay_xms(10);
|
||||
|
||||
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
|
||||
1,
|
||||
USB_SYSCFG_DPRPU_SHIFT,
|
||||
USB_SYSCFG_DPRPU); /* Pull-up D+ and open D- */
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_USB_FUNCTION_Detach
|
||||
* Description : Disconnects from the USB host controller.
|
||||
* : This function opens D+/D-.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_function_USB_FUNCTION_Detach (void)
|
||||
{
|
||||
uint16_t pipe;
|
||||
|
||||
Userdef_USB_usb1_function_detach();
|
||||
|
||||
for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe)
|
||||
{
|
||||
if (g_usb1_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_IDLE)
|
||||
{
|
||||
usb1_function_stop_transfer(pipe);
|
||||
}
|
||||
}
|
||||
|
||||
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
|
||||
0,
|
||||
USB_SYSCFG_DPRPU_SHIFT,
|
||||
USB_SYSCFG_DPRPU); /* open D+ and D- */
|
||||
|
||||
/* Detach Recovery */
|
||||
Userdef_USB_usb1_function_delay_500ns(); /* need 1us=500ns * 2 wait */
|
||||
Userdef_USB_usb1_function_delay_500ns();
|
||||
|
||||
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
|
||||
1,
|
||||
USB_SYSCFG_DCFM_SHIFT,
|
||||
USB_SYSCFG_DCFM);
|
||||
Userdef_USB_usb1_function_delay_500ns(); /* need 100ns wait but 500ns S/W wait */
|
||||
|
||||
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
|
||||
0,
|
||||
USB_SYSCFG_DCFM_SHIFT,
|
||||
USB_SYSCFG_DCFM);
|
||||
|
||||
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
|
||||
0,
|
||||
USB_SYSCFG_USBE_SHIFT,
|
||||
USB_SYSCFG_USBE); /* soft reset module */
|
||||
Userdef_USB_usb1_function_delay_500ns();
|
||||
|
||||
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
|
||||
1,
|
||||
USB_SYSCFG_USBE_SHIFT,
|
||||
USB_SYSCFG_USBE);
|
||||
|
||||
usb1_function_EnableINTModule(); /* Interrupt Enable */
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_USB_FUNCTION_BusReset
|
||||
* Description : This function is executed when the USB device is transitioned
|
||||
* : to POWERD_STATE. Sets the device descriptor according to the
|
||||
* : connection speed determined by the USB reset hand shake.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
#if 0 /*The USBHAL in mbed does not need this function*/
|
||||
void usb1_function_USB_FUNCTION_BusReset (void)
|
||||
{
|
||||
usb1_function_init_status(); /* memory clear */
|
||||
|
||||
if (usb1_function_is_hispeed() == USB_FUNCTION_HIGH_SPEED)
|
||||
{
|
||||
usb1_function_ResetDescriptor(USB_FUNCTION_HIGH_SPEED); /* Device Descriptor reset */
|
||||
}
|
||||
else
|
||||
{
|
||||
usb1_function_ResetDescriptor(USB_FUNCTION_FULL_SPEED); /* Device Descriptor reset */
|
||||
}
|
||||
|
||||
usb1_function_ResetDCP(); /* Default Control PIPE reset */
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_USB_FUNCTION_Resume
|
||||
* Description : This function is executed when the USB device detects a resume
|
||||
* : signal.
|
||||
* : The USB sample driver does not operate for this function.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
#if 0 /*The USBHAL in mbed does not need this function*/
|
||||
void usb1_function_USB_FUNCTION_Resume (void)
|
||||
{
|
||||
/* NOP */
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_USB_FUNCTION_Suspend
|
||||
* Description : This function is executed when the USB device detects a suspend
|
||||
* : signal.
|
||||
* : The USB sample driver does not operate for this function.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
#if 0 /*The USBHAL in mbed does not need this function*/
|
||||
void usb1_function_USB_FUNCTION_Suspend (void)
|
||||
{
|
||||
/* NOP */
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_USB_FUNCTION_TestMode
|
||||
* Description : This function is executed when the USB device is transitioned U
|
||||
* : to TEST_MODE by the USB standard request.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_function_USB_FUNCTION_TestMode (void)
|
||||
{
|
||||
switch (g_usb1_function_TestModeSelectors & USB_FUNCTION_FUNCTION_TEST_SELECT)
|
||||
{
|
||||
case USB_FUNCTION_FUNCTION_TEST_J:
|
||||
case USB_FUNCTION_FUNCTION_TEST_K:
|
||||
case USB_FUNCTION_FUNCTION_TEST_SE0_NAK:
|
||||
case USB_FUNCTION_FUNCTION_TEST_PACKET:
|
||||
RZA_IO_RegWrite_16(&USB201.TESTMODE,
|
||||
(g_usb1_function_TestModeSelectors >> 8),
|
||||
USB_TESTMODE_UTST_SHIFT,
|
||||
USB_TESTMODE_UTST);
|
||||
break;
|
||||
|
||||
case USB_FUNCTION_FUNCTION_TEST_FORCE_ENABLE:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_EnableINTModule
|
||||
* Description : Enables USB interrupt.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
static void usb1_function_EnableINTModule (void)
|
||||
{
|
||||
uint16_t buf;
|
||||
|
||||
buf = USB201.INTENB0;
|
||||
buf |= (USB_FUNCTION_BITVBSE | USB_FUNCTION_BITDVSE | USB_FUNCTION_BITCTRE |
|
||||
USB_FUNCTION_BITBEMPE | USB_FUNCTION_BITNRDYE | USB_FUNCTION_BITBRDYE);
|
||||
USB201.INTENB0 = buf;
|
||||
|
||||
usb1_function_enable_bemp_int(USB_FUNCTION_PIPE0);
|
||||
}
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,453 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_function_sub.c
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Device(s) : RZ/A1H
|
||||
* Tool-Chain :
|
||||
* OS : None
|
||||
* H/W Platform :
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
* Operation :
|
||||
* Limitations :
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include "usb1_function.h"
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
#if 0
|
||||
extern const uint16_t *g_usb1_function_EndPntPtr[];
|
||||
extern uint8_t g_usb1_function_DeviceDescriptor[];
|
||||
extern uint8_t *g_usb1_function_ConfigurationPtr[];
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private global variables and functions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_ResetDCP
|
||||
* Description : Initializes the default control pipe(DCP).
|
||||
* Outline : Reset default control pipe
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_function_ResetDCP (void)
|
||||
{
|
||||
USB201.DCPCFG = 0;
|
||||
#if 0
|
||||
USB201.DCPMAXP = g_usb1_function_DeviceDescriptor[7];
|
||||
#else
|
||||
USB201.DCPMAXP = 64;
|
||||
#endif
|
||||
|
||||
USB201.CFIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
|
||||
USB201.D0FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
|
||||
USB201.D1FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_ResetEP
|
||||
* Description : Initializes the end point.
|
||||
* Arguments : uint16_t num ; Configuration Number
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
#if 0
|
||||
void usb1_function_ResetEP (uint16_t num)
|
||||
{
|
||||
uint16_t pipe;
|
||||
uint16_t ep;
|
||||
uint16_t index;
|
||||
uint16_t buf;
|
||||
uint16_t * tbl;
|
||||
|
||||
tbl = (uint16_t *)(g_usb1_function_EndPntPtr[num - 1]);
|
||||
|
||||
for (ep = 1; ep <= USB_FUNCTION_MAX_EP_NO; ++ep)
|
||||
{
|
||||
if (g_usb1_function_EPTableIndex[ep] != USB_FUNCTION_EP_ERROR)
|
||||
{
|
||||
index = (uint16_t)(USB_FUNCTION_EPTABLE_LENGTH * g_usb1_function_EPTableIndex[ep]);
|
||||
pipe = (uint16_t)(tbl[index + 0] & USB_FUNCTION_BITCURPIPE);
|
||||
|
||||
g_usb1_function_PipeTbl[pipe] = (uint16_t)(((tbl[index + 1] & USB_FUNCTION_DIRFIELD) << 3) |
|
||||
ep |
|
||||
(tbl[index + 0] & USB_FUNCTION_FIFO_USE));
|
||||
|
||||
if ((tbl[index + 1] & USB_FUNCTION_DIRFIELD) == USB_FUNCTION_DIR_P_OUT)
|
||||
{
|
||||
tbl[index + 1] |= USB_FUNCTION_SHTNAKON;
|
||||
#ifdef __USB_DMA_BFRE_ENABLE__
|
||||
/* this routine cannnot be perfomred if read operation is executed in buffer size */
|
||||
if (((tbl[index + 0] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA) ||
|
||||
((tbl[index + 0] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_DMA))
|
||||
{
|
||||
tbl[index + 1] |= USB_FUNCTION_BFREON;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Interrupt Disable */
|
||||
buf = USB201.BRDYENB;
|
||||
buf &= (uint16_t)~g_usb1_function_bit_set[pipe];
|
||||
USB201.BRDYENB = buf;
|
||||
buf = USB201.NRDYENB;
|
||||
buf &= (uint16_t)~g_usb1_function_bit_set[pipe];
|
||||
USB201.NRDYENB = buf;
|
||||
buf = USB201.BEMPENB;
|
||||
buf &= (uint16_t)~g_usb1_function_bit_set[pipe];
|
||||
USB201.BEMPENB = buf;
|
||||
|
||||
usb1_function_set_pid_nak(pipe);
|
||||
|
||||
/* CurrentPIPE Clear */
|
||||
if (RZA_IO_RegRead_16(&USB201.CFIFOSEL,
|
||||
USB_CFIFOSEL_CURPIPE_SHIFT,
|
||||
USB_CFIFOSEL_CURPIPE) == pipe)
|
||||
{
|
||||
RZA_IO_RegWrite_16(&USB201.CFIFOSEL,
|
||||
0,
|
||||
USB_CFIFOSEL_CURPIPE_SHIFT,
|
||||
USB_CFIFOSEL_CURPIPE);
|
||||
}
|
||||
|
||||
if (RZA_IO_RegRead_16(&USB201.D0FIFOSEL,
|
||||
USB_DnFIFOSEL_CURPIPE_SHIFT,
|
||||
USB_DnFIFOSEL_CURPIPE) == pipe)
|
||||
{
|
||||
RZA_IO_RegWrite_16(&USB201.D0FIFOSEL,
|
||||
0,
|
||||
USB_DnFIFOSEL_CURPIPE_SHIFT,
|
||||
USB_DnFIFOSEL_CURPIPE);
|
||||
}
|
||||
|
||||
if (RZA_IO_RegRead_16(&USB201.D1FIFOSEL,
|
||||
USB_DnFIFOSEL_CURPIPE_SHIFT,
|
||||
USB_DnFIFOSEL_CURPIPE) == pipe)
|
||||
{
|
||||
RZA_IO_RegWrite_16(&USB201.D1FIFOSEL,
|
||||
0,
|
||||
USB_DnFIFOSEL_CURPIPE_SHIFT,
|
||||
USB_DnFIFOSEL_CURPIPE);
|
||||
}
|
||||
|
||||
/* PIPE Configuration */
|
||||
USB201.PIPESEL = pipe;
|
||||
USB201.PIPECFG = tbl[index + 1];
|
||||
USB201.PIPEBUF = tbl[index + 2];
|
||||
USB201.PIPEMAXP = tbl[index + 3];
|
||||
USB201.PIPEPERI = tbl[index + 4];
|
||||
|
||||
g_usb1_function_pipecfg[pipe] = tbl[index + 1];
|
||||
g_usb1_function_pipebuf[pipe] = tbl[index + 2];
|
||||
g_usb1_function_pipemaxp[pipe] = tbl[index + 3];
|
||||
g_usb1_function_pipeperi[pipe] = tbl[index + 4];
|
||||
|
||||
/* Buffer Clear */
|
||||
usb1_function_set_sqclr(pipe);
|
||||
usb1_function_aclrm(pipe);
|
||||
|
||||
/* init Global */
|
||||
g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
|
||||
g_usb1_function_PipeDataSize[pipe] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_EpToPipe
|
||||
* Description : Returns the pipe which end point specified by the argument is
|
||||
* : allocated to.
|
||||
* Arguments : uint16_t ep ; Direction + Endpoint Number
|
||||
* Return Value : USB_FUNCTION_EP_ERROR : Error
|
||||
* : Others : Pipe Number
|
||||
*******************************************************************************/
|
||||
uint16_t usb1_function_EpToPipe (uint16_t ep)
|
||||
{
|
||||
uint16_t pipe;
|
||||
|
||||
for (pipe = 1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
|
||||
{
|
||||
if ((g_usb1_function_PipeTbl[pipe] & 0x00ff) == ep)
|
||||
{
|
||||
return pipe;
|
||||
}
|
||||
}
|
||||
|
||||
return USB_FUNCTION_EP_ERROR;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_InitEPTable
|
||||
* Description : Sets the end point by the Alternate setting value of the
|
||||
* : configuration number and the interface number specified by the
|
||||
* : argument.
|
||||
* Arguments : uint16_t Con_Num ; Configuration Number
|
||||
* : uint16_t Int_Num ; Interface Number
|
||||
* : uint16_t Alt_Num ; Alternate Setting
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
#if 0
|
||||
void usb1_function_InitEPTable (uint16_t Con_Num, uint16_t Int_Num, uint16_t Alt_Num)
|
||||
{
|
||||
uint8_t * ptr;
|
||||
uint16_t point_interface;
|
||||
uint16_t point_endpoint;
|
||||
uint16_t length;
|
||||
uint16_t start;
|
||||
uint16_t numbers;
|
||||
uint16_t endpoint;
|
||||
|
||||
ptr = (uint8_t *)g_usb1_function_ConfigurationPtr[Con_Num - 1];
|
||||
point_interface = *ptr;
|
||||
length = (uint16_t)((uint16_t)*(ptr + 3) << 8 | (uint16_t)*(ptr + 2));
|
||||
ptr += *ptr;
|
||||
start = 0;
|
||||
numbers = 0;
|
||||
point_endpoint = 0;
|
||||
|
||||
for (; point_interface < length;)
|
||||
{
|
||||
switch (*(ptr + 1)) /* Descriptor Type ? */
|
||||
{
|
||||
case USB_FUNCTION_DT_INTERFACE: /* Interface */
|
||||
if ((*(ptr + 2) == Int_Num) && (*(ptr + 3) == Alt_Num))
|
||||
{
|
||||
numbers = *(ptr + 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
start += *(ptr + 4);
|
||||
}
|
||||
point_interface += *ptr;
|
||||
ptr += *ptr;
|
||||
break;
|
||||
|
||||
case USB_FUNCTION_DT_ENDPOINT: /* Endpoint */
|
||||
if (point_endpoint < numbers)
|
||||
{
|
||||
endpoint = (uint16_t)(*(ptr + 2) & 0x0f);
|
||||
g_usb1_function_EPTableIndex[endpoint] = (uint16_t)(start + point_endpoint);
|
||||
++point_endpoint;
|
||||
}
|
||||
point_interface += *ptr;
|
||||
ptr += *ptr;
|
||||
break;
|
||||
|
||||
case USB_FUNCTION_DT_DEVICE: /* Device */
|
||||
case USB_FUNCTION_DT_CONFIGURATION: /* Configuration */
|
||||
case USB_FUNCTION_DT_STRING: /* String */
|
||||
default: /* Class, Vendor, else */
|
||||
point_interface += *ptr;
|
||||
ptr += *ptr;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_GetConfigNum
|
||||
* Description : Returns the number of configuration referring to the number of
|
||||
* : configuration described in the device descriptor.
|
||||
* Arguments : none
|
||||
* Return Value : Number of possible configurations (bNumConfigurations).
|
||||
*******************************************************************************/
|
||||
#if 0
|
||||
uint16_t usb1_function_GetConfigNum (void)
|
||||
{
|
||||
return (uint16_t)g_usb1_function_DeviceDescriptor[17];
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_GetInterfaceNum
|
||||
* Description : Returns the number of interface referring to the number of
|
||||
* : interface described in the configuration descriptor.
|
||||
* Arguments : uint16_t num ; Configuration Number
|
||||
* Return Value : Number of this interface (bNumInterfaces).
|
||||
*******************************************************************************/
|
||||
#if 0
|
||||
uint16_t usb1_function_GetInterfaceNum (uint16_t num)
|
||||
{
|
||||
return (uint16_t)(*(g_usb1_function_ConfigurationPtr[num - 1] + 4));
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_GetAltNum
|
||||
* Description : Returns the Alternate setting value of the configuration number
|
||||
* : and the interface number specified by the argument.
|
||||
* Arguments : uint16_t Con_Num ; Configuration Number
|
||||
* : uint16_t Int_Num ; Interface Number
|
||||
* Return Value : Value used to select this alternate setting(bAlternateSetting).
|
||||
*******************************************************************************/
|
||||
#if 0
|
||||
uint16_t usb1_function_GetAltNum (uint16_t Con_Num, uint16_t Int_Num)
|
||||
{
|
||||
uint8_t * ptr;
|
||||
uint16_t point;
|
||||
uint16_t alt_num = 0;
|
||||
uint16_t length;
|
||||
|
||||
ptr = (uint8_t *)(g_usb1_function_ConfigurationPtr[Con_Num - 1]);
|
||||
point = ptr[0];
|
||||
ptr += ptr[0]; /* InterfaceDescriptor[0] */
|
||||
length = (uint16_t)(*(g_usb1_function_ConfigurationPtr[Con_Num - 1] + 2));
|
||||
length |= (uint16_t)((uint16_t)(*(g_usb1_function_ConfigurationPtr[Con_Num - 1] + 3)) << 8);
|
||||
|
||||
for (; point < length;) /* Search Descriptor Table size */
|
||||
{
|
||||
switch (ptr[1]) /* Descriptor Type ? */
|
||||
{
|
||||
case USB_FUNCTION_DT_INTERFACE: /* Interface */
|
||||
if (Int_Num == ptr[2])
|
||||
{
|
||||
alt_num = (uint16_t)ptr[3]; /* Alternate Number count */
|
||||
}
|
||||
point += ptr[0];
|
||||
ptr += ptr[0];
|
||||
break;
|
||||
|
||||
case USB_FUNCTION_DT_DEVICE: /* Device */
|
||||
case USB_FUNCTION_DT_CONFIGURATION: /* Configuration */
|
||||
case USB_FUNCTION_DT_STRING: /* String */
|
||||
case USB_FUNCTION_DT_ENDPOINT: /* Endpoint */
|
||||
default: /* Class, Vendor, else */
|
||||
point += ptr[0];
|
||||
ptr += ptr[0];
|
||||
break;
|
||||
}
|
||||
}
|
||||
return alt_num;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_CheckRemoteWakeup
|
||||
* Description : Returns the result of the remote wake up function is supported
|
||||
* : or not referring to the configuration descriptor.
|
||||
* Arguments : none
|
||||
* Return Value : DEVDRV_USBF_ON : Support Remote Wakeup
|
||||
* : DEVDRV_USBF_OFF : not Support Remote Wakeup
|
||||
*******************************************************************************/
|
||||
#if 0
|
||||
uint16_t usb1_function_CheckRemoteWakeup (void)
|
||||
{
|
||||
uint8_t atr;
|
||||
|
||||
if (g_usb1_function_ConfigNum == 0)
|
||||
{
|
||||
return DEVDRV_USBF_OFF;
|
||||
}
|
||||
|
||||
atr = *(g_usb1_function_ConfigurationPtr[g_usb1_function_ConfigNum - 1] + 7);
|
||||
|
||||
if (atr & USB_FUNCTION_CF_RWUP)
|
||||
{
|
||||
return DEVDRV_USBF_ON;
|
||||
}
|
||||
|
||||
return DEVDRV_USBF_OFF;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_clear_alt
|
||||
* Description : Initializes the Alternate setting area.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
#if 0
|
||||
void usb1_function_clear_alt (void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < USB_FUNCTION_ALT_NO; ++i)
|
||||
{
|
||||
g_usb1_function_Alternate[i] = 0; /* Alternate */
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_clear_pipe_tbl
|
||||
* Description : Initializes pipe definition table.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_function_clear_pipe_tbl (void)
|
||||
{
|
||||
int pipe;
|
||||
|
||||
for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe)
|
||||
{
|
||||
g_usb1_function_PipeTbl[pipe] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_clear_ep_table_index
|
||||
* Description : Initializes the end point table index.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
#if 0
|
||||
void usb1_function_clear_ep_table_index (void)
|
||||
{
|
||||
int ep;
|
||||
|
||||
for (ep = 0; ep <= USB_FUNCTION_MAX_EP_NO; ++ep)
|
||||
{
|
||||
g_usb1_function_EPTableIndex[ep] = USB_FUNCTION_EP_ERROR;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,698 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_function_dmacdrv.c
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Device(s) : RZ/A1H
|
||||
* Tool-Chain :
|
||||
* OS : None
|
||||
* H/W Platform :
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
* Operation :
|
||||
* Limitations :
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include <stdio.h>
|
||||
#include "r_typedefs.h"
|
||||
#include "iodefine.h"
|
||||
#include "rza_io_regrw.h"
|
||||
#include "usb1_function_dmacdrv.h"
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
|
||||
|
||||
/* ==== Request setting information for on-chip peripheral module ==== */
|
||||
typedef enum dmac_peri_req_reg_type
|
||||
{
|
||||
DMAC_REQ_MID,
|
||||
DMAC_REQ_RID,
|
||||
DMAC_REQ_AM,
|
||||
DMAC_REQ_LVL,
|
||||
DMAC_REQ_REQD
|
||||
} dmac_peri_req_reg_type_t;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private global variables and functions
|
||||
*******************************************************************************/
|
||||
/* ==== Prototype declaration ==== */
|
||||
|
||||
/* ==== Global variable ==== */
|
||||
/* On-chip peripheral module request setting table */
|
||||
static const uint8_t usb1_function_dmac_peri_req_init_table[8][5] =
|
||||
{
|
||||
/* MID,RID,AM,LVL,REQD */
|
||||
{32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
|
||||
{32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
|
||||
{33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
|
||||
{33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
|
||||
{34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
|
||||
{34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
|
||||
{35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
|
||||
{35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
|
||||
};
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_DMAC3_PeriReqInit
|
||||
* Description : Sets the register mode for DMA mode and the on-chip peripheral
|
||||
* : module request for transfer request for DMAC channel 1.
|
||||
* : Executes DMAC initial setting using the DMA information
|
||||
* : specified by the argument *trans_info and the enabled/disabled
|
||||
* : continuous transfer specified by the argument continuation.
|
||||
* : Registers DMAC channel 1 interrupt handler function and sets
|
||||
* : the interrupt priority level. Then enables transfer completion
|
||||
* : interrupt.
|
||||
* Arguments : dmac_transinfo_t *trans_info : Setting information to DMAC register
|
||||
* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
|
||||
* : uint32_t continuation : Set continuous transfer to be valid
|
||||
* : after DMA transfer has been completed
|
||||
* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
|
||||
* : DMAC_SAMPLE_SINGLE : Do not execute continuous transfer
|
||||
* : uint32_t request_factor : Factor for on-chip peripheral module request
|
||||
* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
|
||||
* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
|
||||
* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
|
||||
* : :
|
||||
* : uint32_t req_direction: Setting value of CHCFG_n register REQD bit
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_function_DMAC3_PeriReqInit (const dmac_transinfo_t * trans_info,
|
||||
uint32_t dmamode, uint32_t continuation,
|
||||
uint32_t request_factor, uint32_t req_direction)
|
||||
{
|
||||
/* ==== Register mode ==== */
|
||||
if (DMAC_MODE_REGISTER == dmamode)
|
||||
{
|
||||
/* ==== Next0 register set ==== */
|
||||
DMAC3.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
|
||||
DMAC3.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
|
||||
DMAC3.N0TB_n = trans_info->count; /* Total transfer byte count */
|
||||
|
||||
/* DAD : Transfer destination address counting direction */
|
||||
/* SAD : Transfer source address counting direction */
|
||||
/* DDS : Transfer destination transfer size */
|
||||
/* SDS : Transfer source transfer size */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
trans_info->daddr_dir,
|
||||
DMAC3_CHCFG_n_DAD_SHIFT,
|
||||
DMAC3_CHCFG_n_DAD);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
trans_info->saddr_dir,
|
||||
DMAC3_CHCFG_n_SAD_SHIFT,
|
||||
DMAC3_CHCFG_n_SAD);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
trans_info->dst_size,
|
||||
DMAC3_CHCFG_n_DDS_SHIFT,
|
||||
DMAC3_CHCFG_n_DDS);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
trans_info->src_size,
|
||||
DMAC3_CHCFG_n_SDS_SHIFT,
|
||||
DMAC3_CHCFG_n_SDS);
|
||||
|
||||
/* DMS : Register mode */
|
||||
/* RSEL : Select Next0 register set */
|
||||
/* SBE : No discharge of buffer data when aborted */
|
||||
/* DEM : No DMA interrupt mask */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
0,
|
||||
DMAC3_CHCFG_n_DMS_SHIFT,
|
||||
DMAC3_CHCFG_n_DMS);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
0,
|
||||
DMAC3_CHCFG_n_RSEL_SHIFT,
|
||||
DMAC3_CHCFG_n_RSEL);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
0,
|
||||
DMAC3_CHCFG_n_SBE_SHIFT,
|
||||
DMAC3_CHCFG_n_SBE);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
0,
|
||||
DMAC3_CHCFG_n_DEM_SHIFT,
|
||||
DMAC3_CHCFG_n_DEM);
|
||||
|
||||
/* ---- Continuous transfer ---- */
|
||||
if (DMAC_SAMPLE_CONTINUATION == continuation)
|
||||
{
|
||||
/* REN : Execute continuous transfer */
|
||||
/* RSW : Change register set when DMA transfer is completed. */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
1,
|
||||
DMAC3_CHCFG_n_REN_SHIFT,
|
||||
DMAC3_CHCFG_n_REN);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
1,
|
||||
DMAC3_CHCFG_n_RSW_SHIFT,
|
||||
DMAC3_CHCFG_n_RSW);
|
||||
}
|
||||
/* ---- Single transfer ---- */
|
||||
else
|
||||
{
|
||||
/* REN : Do not execute continuous transfer */
|
||||
/* RSW : Do not change register set when DMA transfer is completed. */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
0,
|
||||
DMAC3_CHCFG_n_REN_SHIFT,
|
||||
DMAC3_CHCFG_n_REN);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
0,
|
||||
DMAC3_CHCFG_n_RSW_SHIFT,
|
||||
DMAC3_CHCFG_n_RSW);
|
||||
}
|
||||
|
||||
/* TM : Single transfer */
|
||||
/* SEL : Channel setting */
|
||||
/* HIEN, LOEN : On-chip peripheral module request */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
0,
|
||||
DMAC3_CHCFG_n_TM_SHIFT,
|
||||
DMAC3_CHCFG_n_TM);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
3,
|
||||
DMAC3_CHCFG_n_SEL_SHIFT,
|
||||
DMAC3_CHCFG_n_SEL);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
1,
|
||||
DMAC3_CHCFG_n_HIEN_SHIFT,
|
||||
DMAC3_CHCFG_n_HIEN);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
0,
|
||||
DMAC3_CHCFG_n_LOEN_SHIFT,
|
||||
DMAC3_CHCFG_n_LOEN);
|
||||
|
||||
/* ---- Set factor by specified on-chip peripheral module request ---- */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
|
||||
DMAC3_CHCFG_n_AM_SHIFT,
|
||||
DMAC3_CHCFG_n_AM);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
|
||||
DMAC3_CHCFG_n_LVL_SHIFT,
|
||||
DMAC3_CHCFG_n_LVL);
|
||||
|
||||
if (usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
|
||||
{
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
|
||||
DMAC3_CHCFG_n_REQD_SHIFT,
|
||||
DMAC3_CHCFG_n_REQD);
|
||||
}
|
||||
else
|
||||
{
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
req_direction,
|
||||
DMAC3_CHCFG_n_REQD_SHIFT,
|
||||
DMAC3_CHCFG_n_REQD);
|
||||
}
|
||||
|
||||
RZA_IO_RegWrite_32(&DMAC23.DMARS,
|
||||
usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
|
||||
DMAC23_DMARS_CH3_RID_SHIFT,
|
||||
DMAC23_DMARS_CH3_RID);
|
||||
RZA_IO_RegWrite_32(&DMAC23.DMARS,
|
||||
usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
|
||||
DMAC23_DMARS_CH3_MID_SHIFT,
|
||||
DMAC23_DMARS_CH3_MID);
|
||||
|
||||
/* PR : Round robin mode */
|
||||
RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
|
||||
1,
|
||||
DMAC07_DCTRL_0_7_PR_SHIFT,
|
||||
DMAC07_DCTRL_0_7_PR);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_DMAC3_Open
|
||||
* Description : Enables DMAC channel 3 transfer.
|
||||
* Arguments : uint32_t req : DMAC request mode
|
||||
* Return Value : 0 : Succeeded in enabling DMA transfer
|
||||
* : -1 : Failed to enable DMA transfer (due to DMA operation)
|
||||
*******************************************************************************/
|
||||
int32_t usb1_function_DMAC3_Open (uint32_t req)
|
||||
{
|
||||
int32_t ret;
|
||||
volatile uint8_t dummy;
|
||||
|
||||
/* Transferable? */
|
||||
if ((0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
|
||||
DMAC3_CHSTAT_n_EN_SHIFT,
|
||||
DMAC3_CHSTAT_n_EN)) &&
|
||||
(0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
|
||||
DMAC3_CHSTAT_n_TACT_SHIFT,
|
||||
DMAC3_CHSTAT_n_TACT)))
|
||||
{
|
||||
/* Clear Channel Status Register */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
|
||||
1,
|
||||
DMAC3_CHCTRL_n_SWRST_SHIFT,
|
||||
DMAC3_CHCTRL_n_SWRST);
|
||||
dummy = RZA_IO_RegRead_32(&DMAC3.CHCTRL_n,
|
||||
DMAC3_CHCTRL_n_SWRST_SHIFT,
|
||||
DMAC3_CHCTRL_n_SWRST);
|
||||
/* Enable DMA transfer */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
|
||||
1,
|
||||
DMAC3_CHCTRL_n_SETEN_SHIFT,
|
||||
DMAC3_CHCTRL_n_SETEN);
|
||||
|
||||
/* ---- Request by software ---- */
|
||||
if (DMAC_REQ_MODE_SOFT == req)
|
||||
{
|
||||
/* DMA transfer Request by software */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
|
||||
1,
|
||||
DMAC3_CHCTRL_n_STG_SHIFT,
|
||||
DMAC3_CHCTRL_n_STG);
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = -1;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_DMAC3_Close
|
||||
* Description : Aborts DMAC channel 3 transfer. Returns the remaining transfer
|
||||
* : byte count at the time of DMA transfer abort to the argument
|
||||
* : *remain.
|
||||
* Arguments : uint32_t * remain : Remaining transfer byte count when
|
||||
* : : DMA transfer is aborted
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_function_DMAC3_Close (uint32_t * remain)
|
||||
{
|
||||
|
||||
/* ==== Abort transfer ==== */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
|
||||
1,
|
||||
DMAC3_CHCTRL_n_CLREN_SHIFT,
|
||||
DMAC3_CHCTRL_n_CLREN);
|
||||
|
||||
while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
|
||||
DMAC3_CHSTAT_n_TACT_SHIFT,
|
||||
DMAC3_CHSTAT_n_TACT))
|
||||
{
|
||||
/* Loop until transfer is aborted */
|
||||
}
|
||||
|
||||
while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
|
||||
DMAC3_CHSTAT_n_EN_SHIFT,
|
||||
DMAC3_CHSTAT_n_EN))
|
||||
{
|
||||
/* Loop until 0 is set in EN before checking the remaining transfer byte count */
|
||||
}
|
||||
/* ==== Obtain remaining transfer byte count ==== */
|
||||
*remain = DMAC3.CRTB_n;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_DMAC3_Load_Set
|
||||
* Description : Sets the transfer source address, transfer destination
|
||||
* : address, and total transfer byte count respectively
|
||||
* : specified by the argument src_addr, dst_addr, and count to
|
||||
* : DMAC channel 3 as DMA transfer information.
|
||||
* : Sets the register set selected by the CHCFG_n register
|
||||
* : RSEL bit from the Next0 or Next1 register set.
|
||||
* : This function should be called when DMA transfer of DMAC
|
||||
* : channel 3 is aboted.
|
||||
* Arguments : uint32_t src_addr : Transfer source address
|
||||
* : uint32_t dst_addr : Transfer destination address
|
||||
* : uint32_t count : Total transfer byte count
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_function_DMAC3_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
|
||||
{
|
||||
uint8_t reg_set;
|
||||
|
||||
/* Obtain register set in use */
|
||||
reg_set = RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
|
||||
DMAC3_CHSTAT_n_SR_SHIFT,
|
||||
DMAC3_CHSTAT_n_SR);
|
||||
|
||||
/* ==== Load ==== */
|
||||
if (0 == reg_set)
|
||||
{
|
||||
/* ---- Next0 Register Set ---- */
|
||||
DMAC3.N0SA_n = src_addr; /* Start address of transfer source */
|
||||
DMAC3.N0DA_n = dst_addr; /* Start address of transfer destination */
|
||||
DMAC3.N0TB_n = count; /* Total transfer byte count */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* ---- Next1 Register Set ---- */
|
||||
DMAC3.N1SA_n = src_addr; /* Start address of transfer source */
|
||||
DMAC3.N1DA_n = dst_addr; /* Start address of transfer destination */
|
||||
DMAC3.N1TB_n = count; /* Total transfer byte count */
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_DMAC4_PeriReqInit
|
||||
* Description : Sets the register mode for DMA mode and the on-chip peripheral
|
||||
* : module request for transfer request for DMAC channel 2.
|
||||
* : Executes DMAC initial setting using the DMA information
|
||||
* : specified by the argument *trans_info and the enabled/disabled
|
||||
* : continuous transfer specified by the argument continuation.
|
||||
* : Registers DMAC channel 2 interrupt handler function and sets
|
||||
* : the interrupt priority level. Then enables transfer completion
|
||||
* : interrupt.
|
||||
* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
|
||||
* : : register
|
||||
* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
|
||||
* : uint32_t continuation : Set continuous transfer to be valid
|
||||
* : : after DMA transfer has been completed
|
||||
* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
|
||||
* : DMAC_SAMPLE_SINGLE : Do not execute continuous
|
||||
* : : transfer
|
||||
* : uint32_t request_factor : Factor for on-chip peripheral module
|
||||
* : : request
|
||||
* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
|
||||
* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
|
||||
* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
|
||||
* : :
|
||||
* : uint32_t req_direction : Setting value of CHCFG_n register
|
||||
* : : REQD bit
|
||||
*******************************************************************************/
|
||||
void usb1_function_DMAC4_PeriReqInit (const dmac_transinfo_t * trans_info,
|
||||
uint32_t dmamode, uint32_t continuation,
|
||||
uint32_t request_factor, uint32_t req_direction)
|
||||
{
|
||||
/* ==== Register mode ==== */
|
||||
if (DMAC_MODE_REGISTER == dmamode)
|
||||
{
|
||||
/* ==== Next0 register set ==== */
|
||||
DMAC4.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
|
||||
DMAC4.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
|
||||
DMAC4.N0TB_n = trans_info->count; /* Total transfer byte count */
|
||||
|
||||
/* DAD : Transfer destination address counting direction */
|
||||
/* SAD : Transfer source address counting direction */
|
||||
/* DDS : Transfer destination transfer size */
|
||||
/* SDS : Transfer source transfer size */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
trans_info->daddr_dir,
|
||||
DMAC4_CHCFG_n_DAD_SHIFT,
|
||||
DMAC4_CHCFG_n_DAD);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
trans_info->saddr_dir,
|
||||
DMAC4_CHCFG_n_SAD_SHIFT,
|
||||
DMAC4_CHCFG_n_SAD);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
trans_info->dst_size,
|
||||
DMAC4_CHCFG_n_DDS_SHIFT,
|
||||
DMAC4_CHCFG_n_DDS);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
trans_info->src_size,
|
||||
DMAC4_CHCFG_n_SDS_SHIFT,
|
||||
DMAC4_CHCFG_n_SDS);
|
||||
|
||||
/* DMS : Register mode */
|
||||
/* RSEL : Select Next0 register set */
|
||||
/* SBE : No discharge of buffer data when aborted */
|
||||
/* DEM : No DMA interrupt mask */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
0,
|
||||
DMAC4_CHCFG_n_DMS_SHIFT,
|
||||
DMAC4_CHCFG_n_DMS);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
0,
|
||||
DMAC4_CHCFG_n_RSEL_SHIFT,
|
||||
DMAC4_CHCFG_n_RSEL);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
0,
|
||||
DMAC4_CHCFG_n_SBE_SHIFT,
|
||||
DMAC4_CHCFG_n_SBE);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
0,
|
||||
DMAC4_CHCFG_n_DEM_SHIFT,
|
||||
DMAC4_CHCFG_n_DEM);
|
||||
|
||||
/* ---- Continuous transfer ---- */
|
||||
if (DMAC_SAMPLE_CONTINUATION == continuation)
|
||||
{
|
||||
/* REN : Execute continuous transfer */
|
||||
/* RSW : Change register set when DMA transfer is completed. */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
1,
|
||||
DMAC4_CHCFG_n_REN_SHIFT,
|
||||
DMAC4_CHCFG_n_REN);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
1,
|
||||
DMAC4_CHCFG_n_RSW_SHIFT,
|
||||
DMAC4_CHCFG_n_RSW);
|
||||
}
|
||||
/* ---- Single transfer ---- */
|
||||
else
|
||||
{
|
||||
/* REN : Do not execute continuous transfer */
|
||||
/* RSW : Do not change register set when DMA transfer is completed. */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
0,
|
||||
DMAC4_CHCFG_n_REN_SHIFT,
|
||||
DMAC4_CHCFG_n_REN);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
0,
|
||||
DMAC4_CHCFG_n_RSW_SHIFT,
|
||||
DMAC4_CHCFG_n_RSW);
|
||||
}
|
||||
|
||||
/* TM : Single transfer */
|
||||
/* SEL : Channel setting */
|
||||
/* HIEN, LOEN : On-chip peripheral module request */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
0,
|
||||
DMAC4_CHCFG_n_TM_SHIFT,
|
||||
DMAC4_CHCFG_n_TM);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
4,
|
||||
DMAC4_CHCFG_n_SEL_SHIFT,
|
||||
DMAC4_CHCFG_n_SEL);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
1,
|
||||
DMAC4_CHCFG_n_HIEN_SHIFT,
|
||||
DMAC4_CHCFG_n_HIEN);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
0,
|
||||
DMAC4_CHCFG_n_LOEN_SHIFT,
|
||||
DMAC4_CHCFG_n_LOEN);
|
||||
|
||||
/* ---- Set factor by specified on-chip peripheral module request ---- */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
|
||||
DMAC4_CHCFG_n_AM_SHIFT,
|
||||
DMAC4_CHCFG_n_AM);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
|
||||
DMAC4_CHCFG_n_LVL_SHIFT,
|
||||
DMAC4_CHCFG_n_LVL);
|
||||
if (usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
|
||||
{
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
|
||||
DMAC4_CHCFG_n_REQD_SHIFT,
|
||||
DMAC4_CHCFG_n_REQD);
|
||||
}
|
||||
else
|
||||
{
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
req_direction,
|
||||
DMAC4_CHCFG_n_REQD_SHIFT,
|
||||
DMAC4_CHCFG_n_REQD);
|
||||
}
|
||||
RZA_IO_RegWrite_32(&DMAC45.DMARS,
|
||||
usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
|
||||
DMAC45_DMARS_CH4_RID_SHIFT,
|
||||
DMAC45_DMARS_CH4_RID);
|
||||
RZA_IO_RegWrite_32(&DMAC45.DMARS,
|
||||
usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
|
||||
DMAC45_DMARS_CH4_MID_SHIFT,
|
||||
DMAC45_DMARS_CH4_MID);
|
||||
|
||||
/* PR : Round robin mode */
|
||||
RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
|
||||
1,
|
||||
DMAC07_DCTRL_0_7_PR_SHIFT,
|
||||
DMAC07_DCTRL_0_7_PR);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_DMAC4_Open
|
||||
* Description : Enables DMAC channel 4 transfer.
|
||||
* Arguments : uint32_t req : DMAC request mode
|
||||
* Return Value : 0 : Succeeded in enabling DMA transfer
|
||||
* : -1 : Failed to enable DMA transfer (due to DMA operation)
|
||||
*******************************************************************************/
|
||||
int32_t usb1_function_DMAC4_Open (uint32_t req)
|
||||
{
|
||||
int32_t ret;
|
||||
volatile uint8_t dummy;
|
||||
|
||||
/* Transferable? */
|
||||
if ((0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
|
||||
DMAC4_CHSTAT_n_EN_SHIFT,
|
||||
DMAC4_CHSTAT_n_EN)) &&
|
||||
(0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
|
||||
DMAC4_CHSTAT_n_TACT_SHIFT,
|
||||
DMAC4_CHSTAT_n_TACT)))
|
||||
{
|
||||
/* Clear Channel Status Register */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
|
||||
1,
|
||||
DMAC4_CHCTRL_n_SWRST_SHIFT,
|
||||
DMAC4_CHCTRL_n_SWRST);
|
||||
dummy = RZA_IO_RegRead_32(&DMAC4.CHCTRL_n,
|
||||
DMAC4_CHCTRL_n_SWRST_SHIFT,
|
||||
DMAC4_CHCTRL_n_SWRST);
|
||||
/* Enable DMA transfer */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
|
||||
1,
|
||||
DMAC4_CHCTRL_n_SETEN_SHIFT,
|
||||
DMAC4_CHCTRL_n_SETEN);
|
||||
|
||||
/* ---- Request by software ---- */
|
||||
if (DMAC_REQ_MODE_SOFT == req)
|
||||
{
|
||||
/* DMA transfer Request by software */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
|
||||
1,
|
||||
DMAC4_CHCTRL_n_STG_SHIFT,
|
||||
DMAC4_CHCTRL_n_STG);
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = -1;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_DMAC4_Close
|
||||
* Description : Aborts DMAC channel 4 transfer. Returns the remaining transfer
|
||||
* : byte count at the time of DMA transfer abort to the argument
|
||||
* : *remain.
|
||||
* Arguments : uint32_t * remain : Remaining transfer byte count when
|
||||
* : : DMA transfer is aborted
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_function_DMAC4_Close (uint32_t * remain)
|
||||
{
|
||||
|
||||
/* ==== Abort transfer ==== */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
|
||||
1,
|
||||
DMAC4_CHCTRL_n_CLREN_SHIFT,
|
||||
DMAC4_CHCTRL_n_CLREN);
|
||||
|
||||
while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
|
||||
DMAC4_CHSTAT_n_TACT_SHIFT,
|
||||
DMAC4_CHSTAT_n_TACT))
|
||||
{
|
||||
/* Loop until transfer is aborted */
|
||||
}
|
||||
|
||||
while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
|
||||
DMAC4_CHSTAT_n_EN_SHIFT,
|
||||
DMAC4_CHSTAT_n_EN))
|
||||
{
|
||||
/* Loop until 0 is set in EN before checking the remaining transfer byte count */
|
||||
}
|
||||
/* ==== Obtain remaining transfer byte count ==== */
|
||||
*remain = DMAC4.CRTB_n;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_DMAC4_Load_Set
|
||||
* Description : Sets the transfer source address, transfer destination
|
||||
* : address, and total transfer byte count respectively
|
||||
* : specified by the argument src_addr, dst_addr, and count to
|
||||
* : DMAC channel 4 as DMA transfer information.
|
||||
* : Sets the register set selected by the CHCFG_n register
|
||||
* : RSEL bit from the Next0 or Next1 register set.
|
||||
* : This function should be called when DMA transfer of DMAC
|
||||
* : channel 4 is aboted.
|
||||
* Arguments : uint32_t src_addr : Transfer source address
|
||||
* : uint32_t dst_addr : Transfer destination address
|
||||
* : uint32_t count : Total transfer byte count
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_function_DMAC4_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
|
||||
{
|
||||
uint8_t reg_set;
|
||||
|
||||
/* Obtain register set in use */
|
||||
reg_set = RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
|
||||
DMAC4_CHSTAT_n_SR_SHIFT,
|
||||
DMAC4_CHSTAT_n_SR);
|
||||
|
||||
/* ==== Load ==== */
|
||||
if (0 == reg_set)
|
||||
{
|
||||
/* ---- Next0 Register Set ---- */
|
||||
DMAC4.N0SA_n = src_addr; /* Start address of transfer source */
|
||||
DMAC4.N0DA_n = dst_addr; /* Start address of transfer destination */
|
||||
DMAC4.N0TB_n = count; /* Total transfer byte count */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* ---- Next1 Register Set ---- */
|
||||
DMAC4.N1SA_n = src_addr; /* Start address of transfer source */
|
||||
DMAC4.N1DA_n = dst_addr; /* Start address of transfer destination */
|
||||
DMAC4.N1TB_n = count; /* Total transfer byte count */
|
||||
}
|
||||
}
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,762 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_function_userdef.c
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Device(s) : RZ/A1H
|
||||
* Tool-Chain :
|
||||
* OS : None
|
||||
* H/W Platform :
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
* Operation :
|
||||
* Limitations :
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include <stdio.h>
|
||||
#include "r_typedefs.h"
|
||||
#include "iodefine.h"
|
||||
#include "devdrv_usb_function_api.h"
|
||||
#include "usb1_function_dmacdrv.h" /* common DMAC driver for USB */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
#define DUMMY_ACCESS OSTM0CNT
|
||||
|
||||
/* #define CACHE_WRITEBACK */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
extern int32_t io_cwb(unsigned long start, unsigned long end);
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
static void usb1_function_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count,
|
||||
uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
|
||||
static void usb1_function_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count,
|
||||
uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
|
||||
static void Userdef_USB_usb1_function_delay_10us_2(void);
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private global variables and functions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_function_d0fifo_dmaintid
|
||||
* Description : get D0FIFO DMA Interrupt ID
|
||||
* Arguments : none
|
||||
* Return Value : D0FIFO DMA Interrupt ID
|
||||
*******************************************************************************/
|
||||
IRQn_Type Userdef_USB_usb1_function_d0fifo_dmaintid (void)
|
||||
{
|
||||
#if 0
|
||||
return DMAINT1_IRQn;
|
||||
#else
|
||||
return 0xFFFF;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_function_d1fifo_dmaintid
|
||||
* Description : get D1FIFO DMA Interrupt ID
|
||||
* Arguments : none
|
||||
* Return Value : D1FIFO DMA Interrupt ID
|
||||
*******************************************************************************/
|
||||
IRQn_Type Userdef_USB_usb1_function_d1fifo_dmaintid (void)
|
||||
{
|
||||
#if 0
|
||||
return DMAINT1_IRQn;
|
||||
#else
|
||||
return 0xFFFF;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_function_attach
|
||||
* Description : Wait for the software of 1ms.
|
||||
* : Alter this function according to the user's system.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void Userdef_USB_usb1_function_attach (void)
|
||||
{
|
||||
printf("\n");
|
||||
printf("channel 1 attach device\n");
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_function_detach
|
||||
* Description : Wait for the software of 1ms.
|
||||
* : Alter this function according to the user's system.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void Userdef_USB_usb1_function_detach (void)
|
||||
{
|
||||
printf("\n");
|
||||
printf("channel 1 detach device\n");
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_function_delay_1ms
|
||||
* Description : Wait for the software of 1ms.
|
||||
* : Alter this function according to the user's system.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void Userdef_USB_usb1_function_delay_1ms (void)
|
||||
{
|
||||
volatile int i;
|
||||
volatile unsigned long tmp;
|
||||
|
||||
/*
|
||||
* Wait 1ms (Please change for your MCU).
|
||||
*/
|
||||
for (i = 0; i < 1440; ++i)
|
||||
{
|
||||
tmp = DUMMY_ACCESS;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_function_delay_xms
|
||||
* Description : Wait for the software in the period of time specified by the
|
||||
* : argument.
|
||||
* : Alter this function according to the user's system.
|
||||
* Arguments : uint32_t msec ; Wait Time (msec)
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void Userdef_USB_usb1_function_delay_xms (uint32_t msec)
|
||||
{
|
||||
volatile unsigned short i;
|
||||
|
||||
for (i = 0; i < msec; ++i)
|
||||
{
|
||||
Userdef_USB_usb1_function_delay_1ms();
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_function_delay_10us
|
||||
* Description : Waits for software for the period specified by the argument.
|
||||
* : Alter this function according to the user's system.
|
||||
* Arguments : uint32_t usec ; Wait Time(x 10usec)
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void Userdef_USB_usb1_function_delay_10us (uint32_t usec)
|
||||
{
|
||||
volatile int i;
|
||||
|
||||
/* Wait 10us (Please change for your MCU) */
|
||||
for (i = 0; i < usec; ++i)
|
||||
{
|
||||
Userdef_USB_usb1_function_delay_10us_2();
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_function_delay_10us_2
|
||||
* Description : Waits for software for the period specified by the argument.
|
||||
* : Alter this function according to the user's system.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
static void Userdef_USB_usb1_function_delay_10us_2 (void)
|
||||
{
|
||||
volatile int i;
|
||||
volatile unsigned long tmp;
|
||||
|
||||
/* Wait 1us (Please change for your MCU) */
|
||||
for (i = 0; i < 14; ++i)
|
||||
{
|
||||
tmp = DUMMY_ACCESS;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_function_delay_500ns
|
||||
* Description : Wait for software for 500ns.
|
||||
* : Alter this function according to the user's system.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void Userdef_USB_usb1_function_delay_500ns (void)
|
||||
{
|
||||
volatile int i;
|
||||
volatile unsigned long tmp;
|
||||
|
||||
/* Wait 500ns (Please change for your MCU) */
|
||||
/* Wait 500ns I clock 266MHz */
|
||||
tmp = DUMMY_ACCESS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_function_start_dma
|
||||
* Description : Enables DMA transfer on the information specified by the argument.
|
||||
* : Set DMAC register by this function to enable DMA transfer.
|
||||
* : After executing this function, USB module is set to start DMA
|
||||
* : transfer. DMA transfer should not wait for DMA transfer complete.
|
||||
* Arguments : USB_FUNCTION_DMA_t *dma : DMA parameter
|
||||
* : typedef struct{
|
||||
* : uint32_t fifo; FIFO for using
|
||||
* : uint32_t buffer; Start address of transfer source/destination
|
||||
* : uint32_t bytes; Transfer size(Byte)
|
||||
* : uint32_t dir; Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer)
|
||||
* : uint32_t size; DMA transfer size
|
||||
* : } USB_FUNCTION_DMA_t;
|
||||
* : uint16_t dfacc ; 0 : cycle steal mode
|
||||
* : 1 : 16byte continuous mode
|
||||
* : 2 : 32byte continuous mode
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void Userdef_USB_usb1_function_start_dma (USB_FUNCTION_DMA_t * dma, uint16_t dfacc)
|
||||
{
|
||||
uint32_t trncount;
|
||||
uint32_t src;
|
||||
uint32_t dst;
|
||||
uint32_t size;
|
||||
uint32_t dir;
|
||||
#ifdef CACHE_WRITEBACK
|
||||
uint32_t ptr;
|
||||
#endif
|
||||
|
||||
trncount = dma->bytes;
|
||||
dir = dma->dir;
|
||||
|
||||
if (dir == USB_FUNCTION_FIFO2BUF)
|
||||
{
|
||||
/* DxFIFO determination */
|
||||
dst = dma->buffer;
|
||||
#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
|
||||
if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
|
||||
{
|
||||
src = (uint32_t)(&USB201.D0FIFO.UINT32);
|
||||
}
|
||||
else
|
||||
{
|
||||
src = (uint32_t)(&USB201.D1FIFO.UINT32);
|
||||
}
|
||||
size = dma->size;
|
||||
|
||||
if (size == 0)
|
||||
{
|
||||
src += 3; /* byte access */
|
||||
}
|
||||
else if (size == 1)
|
||||
{
|
||||
src += 2; /* short access */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do Nothing */
|
||||
}
|
||||
#else
|
||||
size = dma->size;
|
||||
|
||||
if (size == 2)
|
||||
{
|
||||
/* 32bit access */
|
||||
if (dfacc == 2)
|
||||
{
|
||||
/* 32byte access */
|
||||
if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
|
||||
{
|
||||
src = (uint32_t)(&USB201.D0FIFOB0);
|
||||
}
|
||||
else
|
||||
{
|
||||
src = (uint32_t)(&USB201.D1FIFOB0);
|
||||
}
|
||||
}
|
||||
else if (dfacc == 1)
|
||||
{
|
||||
/* 16byte access */
|
||||
if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
|
||||
{
|
||||
src = (uint32_t)(&USB201.D0FIFOB0);
|
||||
}
|
||||
else
|
||||
{
|
||||
src = (uint32_t)(&USB201.D1FIFOB0);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* normal access */
|
||||
if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
|
||||
{
|
||||
src = (uint32_t)(&USB201.D0FIFO.UINT32);
|
||||
}
|
||||
else
|
||||
{
|
||||
src = (uint32_t)(&USB201.D1FIFO.UINT32);
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (size == 1)
|
||||
{
|
||||
/* 16bit access */
|
||||
dfacc = 0; /* force normal access */
|
||||
|
||||
if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
|
||||
{
|
||||
src = (uint32_t)(&USB201.D0FIFO.UINT32);
|
||||
}
|
||||
else
|
||||
{
|
||||
src = (uint32_t)(&USB201.D1FIFO.UINT32);
|
||||
}
|
||||
src += 2; /* short access */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 8bit access */
|
||||
dfacc = 0; /* force normal access */
|
||||
|
||||
if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
|
||||
{
|
||||
src = (uint32_t)(&USB201.D0FIFO.UINT32);
|
||||
}
|
||||
else
|
||||
{
|
||||
src = (uint32_t)(&USB201.D1FIFO.UINT32);
|
||||
}
|
||||
src += 3; /* byte access */
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DxFIFO determination */
|
||||
src = dma->buffer;
|
||||
#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
|
||||
if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D0FIFO.UINT32);
|
||||
}
|
||||
else
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D1FIFO.UINT32);
|
||||
}
|
||||
size = dma->size;
|
||||
|
||||
if (size == 0)
|
||||
{
|
||||
dst += 3; /* byte access */
|
||||
}
|
||||
else if (size == 1)
|
||||
{
|
||||
dst += 2; /* short access */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do Nothing */
|
||||
}
|
||||
#else
|
||||
size = dma->size;
|
||||
|
||||
if (size == 2)
|
||||
{
|
||||
/* 32bit access */
|
||||
if (dfacc == 2)
|
||||
{
|
||||
/* 32byte access */
|
||||
if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D0FIFOB0);
|
||||
}
|
||||
else
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D1FIFOB0);
|
||||
}
|
||||
}
|
||||
else if (dfacc == 1)
|
||||
{
|
||||
/* 16byte access */
|
||||
if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D0FIFOB0);
|
||||
}
|
||||
else
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D1FIFOB0);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* normal access */
|
||||
if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D0FIFO.UINT32);
|
||||
}
|
||||
else
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D1FIFO.UINT32);
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (size == 1)
|
||||
{
|
||||
/* 16bit access */
|
||||
dfacc = 0; /* force normal access */
|
||||
if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D0FIFO.UINT32);
|
||||
}
|
||||
else
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D1FIFO.UINT32);
|
||||
}
|
||||
dst += 2; /* short access */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 8bit access */
|
||||
dfacc = 0; /* force normal access */
|
||||
|
||||
if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D0FIFO.UINT32);
|
||||
}
|
||||
else
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D1FIFO.UINT32);
|
||||
}
|
||||
dst += 3; /* byte access */
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CACHE_WRITEBACK
|
||||
ptr = (uint32_t)dma->buffer;
|
||||
|
||||
if ((ptr & 0x20000000ul) == 0)
|
||||
{
|
||||
io_cwb((uint32_t)ptr, (uint32_t)(ptr) + trncount);
|
||||
}
|
||||
#endif
|
||||
|
||||
if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
|
||||
{
|
||||
usb1_function_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc);
|
||||
}
|
||||
else
|
||||
{
|
||||
usb1_function_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_enable_dmac0
|
||||
* Description : Enables DMA transfer on the information specified by the argument.
|
||||
* Arguments : uint32_t src : src address
|
||||
* : uint32_t dst : dst address
|
||||
* : uint32_t count : transfer byte
|
||||
* : uint32_t size : transfer size
|
||||
* : uint32_t dir : direction
|
||||
* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
|
||||
* : uint16_t dfacc : 0 : normal access
|
||||
* : : 1 : 16byte access
|
||||
* : : 2 : 32byte access
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
static void usb1_function_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count,
|
||||
uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
|
||||
{
|
||||
dmac_transinfo_t trans_info;
|
||||
uint32_t request_factor = 0;
|
||||
int32_t ret;
|
||||
|
||||
/* ==== Variable setting for DMAC initialization ==== */
|
||||
trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
|
||||
trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
|
||||
trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
|
||||
#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
|
||||
if (size == 0)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (size == 1)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (size == 2)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
|
||||
}
|
||||
else
|
||||
{
|
||||
printf("size error!!\n");
|
||||
}
|
||||
#else
|
||||
if (dfacc == 2)
|
||||
{
|
||||
/* 32byte access */
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (dfacc == 1)
|
||||
{
|
||||
/* 16byte access */
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* normal access */
|
||||
if (size == 0)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (size == 1)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (size == 2)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
|
||||
}
|
||||
else
|
||||
{
|
||||
printf("size error!!\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
if (dir == USB_FUNCTION_FIFO2BUF)
|
||||
{
|
||||
request_factor =DMAC_REQ_USB1_DMA0_RX; /* USB_0 channel 0 receive FIFO full */
|
||||
trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
|
||||
trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
|
||||
}
|
||||
else if (dir == USB_FUNCTION_BUF2FIFO)
|
||||
{
|
||||
request_factor =DMAC_REQ_USB1_DMA0_TX; /* USB_0 channel 0 receive FIFO empty */
|
||||
trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
|
||||
trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do Nothing */
|
||||
}
|
||||
|
||||
/* ==== DMAC initialization ==== */
|
||||
usb1_function_DMAC3_PeriReqInit((const dmac_transinfo_t *)&trans_info,
|
||||
DMAC_MODE_REGISTER,
|
||||
DMAC_SAMPLE_SINGLE,
|
||||
request_factor,
|
||||
0); /* Don't care DMAC_REQ_REQD is setting in
|
||||
usb1_function_DMAC3_PeriReqInit() */
|
||||
|
||||
/* ==== DMAC startup ==== */
|
||||
ret = usb1_function_DMAC3_Open(DMAC_REQ_MODE_PERI);
|
||||
if (ret != 0)
|
||||
{
|
||||
printf("DMAC3 Open error!!\n");
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_function_enable_dmac1
|
||||
* Description : Enables DMA transfer on the information specified by the argument.
|
||||
* Arguments : uint32_t src : src address
|
||||
* : uint32_t dst : dst address
|
||||
* : uint32_t count : transfer byte
|
||||
* : uint32_t size : transfer size
|
||||
* : uint32_t dir : direction
|
||||
* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
|
||||
* : uint16_t dfacc : 0 : normal access
|
||||
* : : 1 : 16byte access
|
||||
* : : 2 : 32byte access
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
static void usb1_function_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count,
|
||||
uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
|
||||
{
|
||||
dmac_transinfo_t trans_info;
|
||||
uint32_t request_factor = 0;
|
||||
int32_t ret;
|
||||
|
||||
/* ==== Variable setting for DMAC initialization ==== */
|
||||
trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
|
||||
trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
|
||||
trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
|
||||
#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
|
||||
if (size == 0)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (size == 1)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (size == 2)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
|
||||
}
|
||||
else
|
||||
{
|
||||
printf("size error!!\n");
|
||||
}
|
||||
#else
|
||||
if (dfacc == 2)
|
||||
{
|
||||
/* 32byte access */
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (dfacc == 1)
|
||||
{
|
||||
/* 16byte access */
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* normal access */
|
||||
if (size == 0)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (size == 1)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (size == 2)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
|
||||
}
|
||||
else
|
||||
{
|
||||
printf("size error!!\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
if (dir == USB_FUNCTION_FIFO2BUF)
|
||||
{
|
||||
request_factor =DMAC_REQ_USB1_DMA1_RX; /* USB_0 channel 0 receive FIFO full */
|
||||
trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
|
||||
trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
|
||||
}
|
||||
else if (dir == USB_FUNCTION_BUF2FIFO)
|
||||
{
|
||||
request_factor =DMAC_REQ_USB1_DMA1_TX; /* USB_0 channel 0 receive FIFO empty */
|
||||
trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
|
||||
trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do Nothing */
|
||||
}
|
||||
|
||||
/* ==== DMAC initialization ==== */
|
||||
usb1_function_DMAC4_PeriReqInit((const dmac_transinfo_t *)&trans_info,
|
||||
DMAC_MODE_REGISTER,
|
||||
DMAC_SAMPLE_SINGLE,
|
||||
request_factor,
|
||||
0); /* Don't care DMAC_REQ_REQD is setting in
|
||||
usb1_function_DMAC4_PeriReqInit() */
|
||||
|
||||
/* ==== DMAC startup ==== */
|
||||
ret = usb1_function_DMAC4_Open(DMAC_REQ_MODE_PERI);
|
||||
if (ret != 0)
|
||||
{
|
||||
printf("DMAC4 Open error!!\n");
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_function_stop_dma0
|
||||
* Description : Disables DMA transfer.
|
||||
* : This function should be executed to DMAC executed at the time
|
||||
* : of specification of D0_FIF0_DMA in dma->fifo.
|
||||
* Arguments : none
|
||||
* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
|
||||
* : regarding to the bus width.
|
||||
*******************************************************************************/
|
||||
uint32_t Userdef_USB_usb1_function_stop_dma0 (void)
|
||||
{
|
||||
uint32_t remain;
|
||||
|
||||
/* ==== DMAC release ==== */
|
||||
usb1_function_DMAC3_Close(&remain);
|
||||
|
||||
return remain;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_function_stop_dma1
|
||||
* Description : Disables DMA transfer.
|
||||
* : This function should be executed to DMAC executed at the time
|
||||
* : of specification of D1_FIF0_DMA in dma->fifo.
|
||||
* Arguments : none
|
||||
* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
|
||||
* : regarding to the bus width.
|
||||
*******************************************************************************/
|
||||
uint32_t Userdef_USB_usb1_function_stop_dma1 (void)
|
||||
{
|
||||
uint32_t remain;
|
||||
|
||||
/* ==== DMAC release ==== */
|
||||
usb1_function_DMAC4_Close(&remain);
|
||||
|
||||
return remain;
|
||||
}
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,173 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2014 - 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef USB_FUNCTION_SETTING_H
|
||||
#define USB_FUNCTION_SETTING_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define USB_FUNCTION_CH 0
|
||||
#define USB_FUNCTION_HISPEED 1
|
||||
|
||||
#if (USB_FUNCTION_CH == 0)
|
||||
#include "usb0_function.h"
|
||||
#define USB20X USB200
|
||||
#define USBIX_IRQn USBI0_IRQn
|
||||
#define g_usbx_function_bit_set g_usb0_function_bit_set
|
||||
#define g_usbx_function_PipeDataSize g_usb0_function_PipeDataSize
|
||||
#define g_usbx_function_data_count g_usb0_function_data_count
|
||||
#define g_usbx_function_PipeTbl g_usb0_function_PipeTbl
|
||||
#define g_usbx_function_DmaStatus g_usb0_function_DmaStatus
|
||||
#define g_usbx_function_pipecfg g_usb0_function_pipecfg
|
||||
#define g_usbx_function_pipe_status g_usb0_function_pipe_status
|
||||
#define g_usbx_function_data_pointer g_usb0_function_data_pointer
|
||||
#define g_usbx_function_pipebuf g_usb0_function_pipebuf
|
||||
#define g_usbx_function_pipemaxp g_usb0_function_pipemaxp
|
||||
#define g_usbx_function_pipeperi g_usb0_function_pipeperi
|
||||
#define g_usbx_function_TestModeFlag g_usb0_function_TestModeFlag
|
||||
#define usbx_function_BRDYInterruptPIPE0 usb0_function_BRDYInterruptPIPE0
|
||||
#define usbx_function_BRDYInterrupt usb0_function_BRDYInterrupt
|
||||
#define usbx_function_NRDYInterruptPIPE0 usb0_function_NRDYInterruptPIPE0
|
||||
#define usbx_function_NRDYInterrupt usb0_function_NRDYInterrupt
|
||||
#define usbx_function_BEMPInterruptPIPE0 usb0_function_BEMPInterruptPIPE0
|
||||
#define usbx_function_BEMPInterrupt usb0_function_BEMPInterrupt
|
||||
#define usbx_function_read_buffer_c usb0_function_read_buffer_c
|
||||
#define usbx_function_set_pid_buf usb0_function_set_pid_buf
|
||||
#define usbx_function_disable_brdy_int usb0_function_disable_brdy_int
|
||||
#define usbx_function_set_pid_stall usb0_function_set_pid_stall
|
||||
#define usbx_function_dma_interrupt_d0fifo usb0_function_dma_interrupt_d0fifo
|
||||
#define usbx_function_read_dma usb0_function_read_dma
|
||||
#define usbx_function_dma_interrupt_d1fifo usb0_function_dma_interrupt_d1fifo
|
||||
#define usbx_function_write_buffer usb0_function_write_buffer
|
||||
#define usbx_function_set_pid_nak usb0_function_set_pid_nak
|
||||
#define usbx_function_get_mbw usb0_function_get_mbw
|
||||
#define usbx_function_set_curpipe usb0_function_set_curpipe
|
||||
#define usbx_function_aclrm usb0_function_aclrm
|
||||
#define usbx_function_enable_nrdy_int usb0_function_enable_nrdy_int
|
||||
#define usbx_function_enable_brdy_int usb0_function_enable_brdy_int
|
||||
#define usbx_function_get_pid usb0_function_get_pid
|
||||
#define usbx_function_get_inbuf usb0_function_get_inbuf
|
||||
#define usbx_function_disable_bemp_int usb0_function_disable_bemp_int
|
||||
#define usbx_function_EpToPipe usb0_function_EpToPipe
|
||||
#define usbx_function_clear_pipe_tbl usb0_function_clear_pipe_tbl
|
||||
#define Userdef_USB_usbx_function_d0fifo_dmaintid Userdef_USB_usb0_function_d0fifo_dmaintid
|
||||
#define Userdef_USB_usbx_function_d1fifo_dmaintid Userdef_USB_usb0_function_d1fifo_dmaintid
|
||||
#define usbx_function_reset_module usb0_function_reset_module
|
||||
#define usbx_function_init_status usb0_function_init_status
|
||||
#define usbx_function_InitModule usb0_function_InitModule
|
||||
#define usbx_function_clear_alt usb0_function_clear_alt
|
||||
#define usbx_function_set_sqclr usb0_function_set_sqclr
|
||||
#define usbx_api_function_CtrlWriteStart usb0_api_function_CtrlWriteStart
|
||||
#define usbx_api_function_CtrlReadStart usb0_api_function_CtrlReadStart
|
||||
#define usbx_function_write_buffer_c usb0_function_write_buffer_c
|
||||
#define usbx_api_function_check_pipe_status usb0_api_function_check_pipe_status
|
||||
#define usbx_api_function_set_pid_nak usb0_api_function_set_pid_nak
|
||||
#define usbx_api_function_clear_pipe_status usb0_api_function_clear_pipe_status
|
||||
#define usbx_api_function_start_receive_transfer usb0_api_function_start_receive_transfer
|
||||
#define usbx_function_read_buffer usb0_function_read_buffer
|
||||
#define usbx_api_function_start_send_transfer usb0_api_function_start_send_transfer
|
||||
#define usbx_function_stop_transfer usb0_function_stop_transfer
|
||||
#define usbx_function_clear_pid_stall usb0_function_clear_pid_stall
|
||||
#define usbx_function_CheckVBUStaus usb0_function_CheckVBUStaus
|
||||
#define usbx_function_USB_FUNCTION_Attach usb0_function_USB_FUNCTION_Attach
|
||||
#define usbx_function_USB_FUNCTION_Detach usb0_function_USB_FUNCTION_Detach
|
||||
#define usbx_function_is_hispeed usb0_function_is_hispeed
|
||||
#define usbx_function_ResetDescriptor usb0_function_ResetDescriptor
|
||||
#define usbx_function_USB_FUNCTION_Suspend usb0_function_USB_FUNCTION_Suspend
|
||||
#define usbx_function_USB_FUNCTION_TestMode usb0_function_USB_FUNCTION_TestMode
|
||||
#else
|
||||
#include "usb1_function.h"
|
||||
#define USB20X USB201
|
||||
#define USBIX_IRQn USBI1_IRQn
|
||||
#define g_usbx_function_bit_set g_usb1_function_bit_set
|
||||
#define g_usbx_function_PipeDataSize g_usb1_function_PipeDataSize
|
||||
#define g_usbx_function_data_count g_usb1_function_data_count
|
||||
#define g_usbx_function_PipeTbl g_usb1_function_PipeTbl
|
||||
#define g_usbx_function_DmaStatus g_usb1_function_DmaStatus
|
||||
#define g_usbx_function_pipecfg g_usb1_function_pipecfg
|
||||
#define g_usbx_function_pipe_status g_usb1_function_pipe_status
|
||||
#define g_usbx_function_data_pointer g_usb1_function_data_pointer
|
||||
#define g_usbx_function_pipebuf g_usb1_function_pipebuf
|
||||
#define g_usbx_function_pipemaxp g_usb1_function_pipemaxp
|
||||
#define g_usbx_function_pipeperi g_usb1_function_pipeperi
|
||||
#define g_usbx_function_TestModeFlag g_usb1_function_TestModeFlag
|
||||
#define usbx_function_BRDYInterruptPIPE0 usb1_function_BRDYInterruptPIPE0
|
||||
#define usbx_function_BRDYInterrupt usb1_function_BRDYInterrupt
|
||||
#define usbx_function_NRDYInterruptPIPE0 usb1_function_NRDYInterruptPIPE0
|
||||
#define usbx_function_NRDYInterrupt usb1_function_NRDYInterrupt
|
||||
#define usbx_function_BEMPInterruptPIPE0 usb1_function_BEMPInterruptPIPE0
|
||||
#define usbx_function_BEMPInterrupt usb1_function_BEMPInterrupt
|
||||
#define usbx_function_read_buffer_c usb1_function_read_buffer_c
|
||||
#define usbx_function_set_pid_buf usb1_function_set_pid_buf
|
||||
#define usbx_function_disable_brdy_int usb1_function_disable_brdy_int
|
||||
#define usbx_function_set_pid_stall usb1_function_set_pid_stall
|
||||
#define usbx_function_dma_interrupt_d0fifo usb1_function_dma_interrupt_d0fifo
|
||||
#define usbx_function_read_dma usb1_function_read_dma
|
||||
#define usbx_function_dma_interrupt_d1fifo usb1_function_dma_interrupt_d1fifo
|
||||
#define usbx_function_write_buffer usb1_function_write_buffer
|
||||
#define usbx_function_set_pid_nak usb1_function_set_pid_nak
|
||||
#define usbx_function_get_mbw usb1_function_get_mbw
|
||||
#define usbx_function_set_curpipe usb1_function_set_curpipe
|
||||
#define usbx_function_aclrm usb1_function_aclrm
|
||||
#define usbx_function_enable_nrdy_int usb1_function_enable_nrdy_int
|
||||
#define usbx_function_enable_brdy_int usb1_function_enable_brdy_int
|
||||
#define usbx_function_get_pid usb1_function_get_pid
|
||||
#define usbx_function_get_inbuf usb1_function_get_inbuf
|
||||
#define usbx_function_disable_bemp_int usb1_function_disable_bemp_int
|
||||
#define usbx_function_EpToPipe usb1_function_EpToPipe
|
||||
#define usbx_function_clear_pipe_tbl usb1_function_clear_pipe_tbl
|
||||
#define Userdef_USB_usbx_function_d0fifo_dmaintid Userdef_USB_usb1_function_d0fifo_dmaintid
|
||||
#define Userdef_USB_usbx_function_d1fifo_dmaintid Userdef_USB_usb1_function_d1fifo_dmaintid
|
||||
#define usbx_function_reset_module usb1_function_reset_module
|
||||
#define usbx_function_init_status usb1_function_init_status
|
||||
#define usbx_function_InitModule usb1_function_InitModule
|
||||
#define usbx_function_clear_alt usb1_function_clear_alt
|
||||
#define usbx_function_set_sqclr usb1_function_set_sqclr
|
||||
#define usbx_api_function_CtrlWriteStart usb1_api_function_CtrlWriteStart
|
||||
#define usbx_api_function_CtrlReadStart usb1_api_function_CtrlReadStart
|
||||
#define usbx_function_write_buffer_c usb1_function_write_buffer_c
|
||||
#define usbx_api_function_check_pipe_status usb1_api_function_check_pipe_status
|
||||
#define usbx_api_function_set_pid_nak usb1_api_function_set_pid_nak
|
||||
#define usbx_api_function_clear_pipe_status usb1_api_function_clear_pipe_status
|
||||
#define usbx_api_function_start_receive_transfer usb1_api_function_start_receive_transfer
|
||||
#define usbx_function_read_buffer usb1_function_read_buffer
|
||||
#define usbx_api_function_start_send_transfer usb1_api_function_start_send_transfer
|
||||
#define usbx_function_stop_transfer usb1_function_stop_transfer
|
||||
#define usbx_function_clear_pid_stall usb1_function_clear_pid_stall
|
||||
#define usbx_function_CheckVBUStaus usb1_function_CheckVBUStaus
|
||||
#define usbx_function_USB_FUNCTION_Attach usb1_function_USB_FUNCTION_Attach
|
||||
#define usbx_function_USB_FUNCTION_Detach usb1_function_USB_FUNCTION_Detach
|
||||
#define usbx_function_is_hispeed usb1_function_is_hispeed
|
||||
#define usbx_function_ResetDescriptor usb1_function_ResetDescriptor
|
||||
#define usbx_function_USB_FUNCTION_Suspend usb1_function_USB_FUNCTION_Suspend
|
||||
#define usbx_function_USB_FUNCTION_TestMode usb1_function_USB_FUNCTION_TestMode
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* USB_FUNCTION_SETTING_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -48,7 +48,7 @@ USBHAL::USBHAL(void) {
|
|||
// Enable power and clocking
|
||||
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
|
||||
|
||||
#if defined(TARGET_STM32F407VG) || defined(TARGET_STM32F401RE)
|
||||
#if defined(TARGET_STM32F407VG) || defined(TARGET_STM32F401RE) || defined(TARGET_STM32F411RE)
|
||||
pin_function(PA_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
|
||||
pin_function(PA_9, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLDOWN, GPIO_AF10_OTG_FS));
|
||||
pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS));
|
||||
|
|
|
|||
|
|
@ -286,10 +286,7 @@ void R_USB_api_host_elt_get_desc(uint16_t root);
|
|||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include "usb0_host_api.h"
|
||||
#if(1) /* ohci_wrapp */
|
||||
#else
|
||||
#include "usb1_host_api.h"
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -23,32 +23,32 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define OHCI_REG_REVISION (0x00)
|
||||
#define OHCI_REG_CONTROL (0x04)
|
||||
#define OHCI_REG_COMMANDSTATUS (0x08)
|
||||
#define OHCI_REG_INTERRUPTSTATUS (0x0C)
|
||||
#define OHCI_REG_INTERRUPTENABLE (0x10)
|
||||
#define OHCI_REG_INTERRUPTDISABLE (0x14)
|
||||
#define OHCI_REG_HCCA (0x18)
|
||||
#define OHCI_REG_PERIODCURRENTED (0x1C)
|
||||
#define OHCI_REG_CONTROLHEADED (0x20)
|
||||
#define OHCI_REG_CONTROLCURRENTED (0x24)
|
||||
#define OHCI_REG_BULKHEADED (0x28)
|
||||
#define OHCI_REG_BULKCURRENTED (0x2C)
|
||||
#define OHCI_REG_DONEHEADED (0x30)
|
||||
#define OHCI_REG_FMINTERVAL (0x34)
|
||||
#define OHCI_REG_FMREMAINING (0x38)
|
||||
#define OHCI_REG_FMNUMBER (0x3C)
|
||||
#define OHCI_REG_PERIODICSTART (0x40)
|
||||
#define OHCI_REG_LSTHRESHOLD (0x44)
|
||||
#define OHCI_REG_RHDESCRIPTORA (0x48)
|
||||
#define OHCI_REG_RHDESCRIPTORB (0x4C)
|
||||
#define OHCI_REG_RHSTATUS (0x50)
|
||||
#define OHCI_REG_RHPORTSTATUS1 (0x54)
|
||||
#define OHCI_REG_REVISION (0x00) /* HcRevision */
|
||||
#define OHCI_REG_CONTROL (0x04) /* HcControl */
|
||||
#define OHCI_REG_COMMANDSTATUS (0x08) /* HcCommandStatus */
|
||||
#define OHCI_REG_INTERRUPTSTATUS (0x0C) /* HcInterruptStatus */
|
||||
#define OHCI_REG_INTERRUPTENABLE (0x10) /* HcInterruptEnable */
|
||||
#define OHCI_REG_INTERRUPTDISABLE (0x14) /* HcInterruptDisable */
|
||||
#define OHCI_REG_HCCA (0x18) /* HcHCCA */
|
||||
#define OHCI_REG_PERIODCURRENTED (0x1C) /* HcPeriodCurrentED */
|
||||
#define OHCI_REG_CONTROLHEADED (0x20) /* HcControlHeadED */
|
||||
#define OHCI_REG_CONTROLCURRENTED (0x24) /* HcControlCurrentED */
|
||||
#define OHCI_REG_BULKHEADED (0x28) /* HcBulkHeadED */
|
||||
#define OHCI_REG_BULKCURRENTED (0x2C) /* HcBulkCurrentED */
|
||||
#define OHCI_REG_DONEHEADED (0x30) /* HcDoneHead */
|
||||
#define OHCI_REG_FMINTERVAL (0x34) /* HcFmInterval */
|
||||
#define OHCI_REG_FMREMAINING (0x38) /* HcFmRemaining */
|
||||
#define OHCI_REG_FMNUMBER (0x3C) /* HcFmNumber */
|
||||
#define OHCI_REG_PERIODICSTART (0x40) /* HcPeriodicStart */
|
||||
#define OHCI_REG_LSTHRESHOLD (0x44) /* HcLSThreshold */
|
||||
#define OHCI_REG_RHDESCRIPTORA (0x48) /* HcRhDescriptorA */
|
||||
#define OHCI_REG_RHDESCRIPTORB (0x4C) /* HcRhDescriptorB */
|
||||
#define OHCI_REG_RHSTATUS (0x50) /* HcRhStatus */
|
||||
#define OHCI_REG_RHPORTSTATUS1 (0x54) /* HcRhPortStatus1 */
|
||||
|
||||
typedef void (usbisr_fnc_t)(void);
|
||||
|
||||
extern void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc, uint32_t hi_speed);
|
||||
extern void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc);
|
||||
extern uint32_t ohciwrapp_reg_r(uint32_t reg_ofs);
|
||||
extern void ohciwrapp_reg_w(uint32_t reg_ofs, uint32_t set_data);
|
||||
extern void ohciwrapp_interrupt(uint32_t int_sense);
|
||||
|
|
|
|||
|
|
@ -77,10 +77,10 @@ Exported global variables and functions (to be accessed by other files)
|
|||
/********************************************************************************************************/
|
||||
|
||||
/* Device Address 1 */
|
||||
USB_HOST_CFG_PIPETBL_t usb0_host_blk_ep_tbl1[ ] =
|
||||
USB_HOST_CFG_PIPETBL_t usb_host_blk_ep_tbl1[ ] =
|
||||
{
|
||||
{
|
||||
USB_HOST_PIPE1,
|
||||
USB_HOST_PIPE3,
|
||||
/* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
|
||||
USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
|
||||
(uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(8),
|
||||
|
|
@ -100,7 +100,7 @@ USB_HOST_CFG_PIPETBL_t usb0_host_blk_ep_tbl1[ ] =
|
|||
}
|
||||
};
|
||||
|
||||
USB_HOST_CFG_PIPETBL_t usb0_host_int_ep_tbl1[ ] =
|
||||
USB_HOST_CFG_PIPETBL_t usb_host_int_ep_tbl1[ ] =
|
||||
{
|
||||
{
|
||||
USB_HOST_PIPE6,
|
||||
|
|
@ -153,4 +153,38 @@ USB_HOST_CFG_PIPETBL_t usb0_host_int_ep_tbl1[ ] =
|
|||
}
|
||||
};
|
||||
|
||||
USB_HOST_CFG_PIPETBL_t usb_host_iso_ep_tbl1[ ] =
|
||||
{
|
||||
{
|
||||
USB_HOST_PIPE1,
|
||||
/* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
|
||||
USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
|
||||
(uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(44),
|
||||
USB_HOST_NONE,
|
||||
USB_HOST_NONE,
|
||||
USB_HOST_D1USE
|
||||
},
|
||||
|
||||
{
|
||||
USB_HOST_PIPE2,
|
||||
/* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
|
||||
USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
|
||||
(uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(60),
|
||||
USB_HOST_NONE,
|
||||
USB_HOST_NONE,
|
||||
USB_HOST_D1USE
|
||||
},
|
||||
|
||||
{
|
||||
/* Pipe end */
|
||||
0xFFFF,
|
||||
0xFFFF,
|
||||
0xFFFF,
|
||||
0xFFFF,
|
||||
0xFFFF,
|
||||
0xFFFF
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -209,7 +209,7 @@ void usb0_host_nrdy_int (uint16_t status, uint16_t int_enb)
|
|||
{
|
||||
#if(1) /* ohci_wrapp */
|
||||
g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
|
||||
ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
|
||||
ohciwrapp_loc_TransEnd(pipe, TD_CC_DEVICENOTRESPONDING);
|
||||
#else
|
||||
g_usb0_host_PipeIgnore[pipe]++;
|
||||
|
||||
|
|
@ -90,7 +90,11 @@ Private global variables and functions
|
|||
*******************************************************************************/
|
||||
uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid (void)
|
||||
{
|
||||
#if(1) /* ohci_wrapp */
|
||||
return 0xFFFF;
|
||||
#else
|
||||
return DMAINT1_IRQn;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
@ -101,7 +105,11 @@ uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid (void)
|
|||
*******************************************************************************/
|
||||
uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid (void)
|
||||
{
|
||||
#if(1) /* ohci_wrapp */
|
||||
return 0xFFFF;
|
||||
#else
|
||||
return DMAINT2_IRQn;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_host.h
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
*******************************************************************************/
|
||||
#ifndef USB1_HOST_H
|
||||
#define USB1_HOST_H
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include "devdrv_usb_host_api.h"
|
||||
#include "usb_host.h"
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
extern const uint16_t g_usb1_host_bit_set[];
|
||||
extern uint32_t g_usb1_host_data_count[USB_HOST_MAX_PIPE_NO + 1];
|
||||
extern uint8_t *g_usb1_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1];
|
||||
|
||||
extern uint16_t g_usb1_host_PipeIgnore[];
|
||||
extern uint16_t g_usb1_host_PipeTbl[];
|
||||
extern uint16_t g_usb1_host_pipe_status[];
|
||||
extern uint32_t g_usb1_host_PipeDataSize[];
|
||||
|
||||
extern USB_HOST_DMA_t g_usb1_host_DmaInfo[];
|
||||
extern uint16_t g_usb1_host_DmaPipe[];
|
||||
extern uint16_t g_usb1_host_DmaBval[];
|
||||
extern uint16_t g_usb1_host_DmaStatus[];
|
||||
|
||||
extern uint16_t g_usb1_host_driver_state;
|
||||
extern uint16_t g_usb1_host_ConfigNum;
|
||||
extern uint16_t g_usb1_host_CmdStage;
|
||||
extern uint16_t g_usb1_host_bchg_flag;
|
||||
extern uint16_t g_usb1_host_detach_flag;
|
||||
extern uint16_t g_usb1_host_attach_flag;
|
||||
|
||||
extern uint16_t g_usb1_host_UsbAddress;
|
||||
extern uint16_t g_usb1_host_setUsbAddress;
|
||||
extern uint16_t g_usb1_host_default_max_packet[USB_HOST_MAX_DEVICE + 1];
|
||||
extern uint16_t g_usb1_host_UsbDeviceSpeed;
|
||||
extern uint16_t g_usb1_host_SupportUsbDeviceSpeed;
|
||||
|
||||
extern uint16_t g_usb1_host_SavReq;
|
||||
extern uint16_t g_usb1_host_SavVal;
|
||||
extern uint16_t g_usb1_host_SavIndx;
|
||||
extern uint16_t g_usb1_host_SavLen;
|
||||
|
||||
extern uint16_t g_usb1_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1];
|
||||
extern uint16_t g_usb1_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1];
|
||||
extern uint16_t g_usb1_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1];
|
||||
extern uint16_t g_usb1_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1];
|
||||
|
||||
/*******************************************************************************
|
||||
Functions Prototypes
|
||||
*******************************************************************************/
|
||||
/* ==== common ==== */
|
||||
void usb1_host_dma_stop_d0(uint16_t pipe, uint32_t remain);
|
||||
void usb1_host_dma_stop_d1(uint16_t pipe, uint32_t remain);
|
||||
uint16_t usb1_host_is_hispeed(void);
|
||||
uint16_t usb1_host_is_hispeed_enable(void);
|
||||
uint16_t usb1_host_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
|
||||
uint16_t usb1_host_write_buffer(uint16_t pipe);
|
||||
uint16_t usb1_host_write_buffer_c(uint16_t pipe);
|
||||
uint16_t usb1_host_write_buffer_d0(uint16_t pipe);
|
||||
uint16_t usb1_host_write_buffer_d1(uint16_t pipe);
|
||||
void usb1_host_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
|
||||
uint16_t usb1_host_read_buffer(uint16_t pipe);
|
||||
uint16_t usb1_host_read_buffer_c(uint16_t pipe);
|
||||
uint16_t usb1_host_read_buffer_d0(uint16_t pipe);
|
||||
uint16_t usb1_host_read_buffer_d1(uint16_t pipe);
|
||||
uint16_t usb1_host_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
|
||||
void usb1_host_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
|
||||
void usb1_host_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc);
|
||||
uint16_t usb1_host_get_mbw(uint32_t trncount, uint32_t dtptr);
|
||||
uint16_t usb1_host_read_dma(uint16_t pipe);
|
||||
void usb1_host_stop_transfer(uint16_t pipe);
|
||||
void usb1_host_brdy_int(uint16_t status, uint16_t int_enb);
|
||||
void usb1_host_nrdy_int(uint16_t status, uint16_t int_enb);
|
||||
void usb1_host_bemp_int(uint16_t status, uint16_t int_enb);
|
||||
void usb1_host_setting_interrupt(uint8_t level);
|
||||
void usb1_host_reset_module(uint16_t clockmode);
|
||||
uint16_t usb1_host_get_buf_size(uint16_t pipe);
|
||||
uint16_t usb1_host_get_mxps(uint16_t pipe);
|
||||
void usb1_host_enable_brdy_int(uint16_t pipe);
|
||||
void usb1_host_disable_brdy_int(uint16_t pipe);
|
||||
void usb1_host_clear_brdy_sts(uint16_t pipe);
|
||||
void usb1_host_enable_bemp_int(uint16_t pipe);
|
||||
void usb1_host_disable_bemp_int(uint16_t pipe);
|
||||
void usb1_host_clear_bemp_sts(uint16_t pipe);
|
||||
void usb1_host_enable_nrdy_int(uint16_t pipe);
|
||||
void usb1_host_disable_nrdy_int(uint16_t pipe);
|
||||
void usb1_host_clear_nrdy_sts(uint16_t pipe);
|
||||
void usb1_host_set_pid_buf(uint16_t pipe);
|
||||
void usb1_host_set_pid_nak(uint16_t pipe);
|
||||
void usb1_host_set_pid_stall(uint16_t pipe);
|
||||
void usb1_host_clear_pid_stall(uint16_t pipe);
|
||||
uint16_t usb1_host_get_pid(uint16_t pipe);
|
||||
void usb1_host_set_sqclr(uint16_t pipe);
|
||||
void usb1_host_set_sqset(uint16_t pipe);
|
||||
void usb1_host_set_csclr(uint16_t pipe);
|
||||
void usb1_host_aclrm(uint16_t pipe);
|
||||
void usb1_host_set_aclrm(uint16_t pipe);
|
||||
void usb1_host_clr_aclrm(uint16_t pipe);
|
||||
uint16_t usb1_host_get_sqmon(uint16_t pipe);
|
||||
uint16_t usb1_host_get_inbuf(uint16_t pipe);
|
||||
|
||||
/* ==== host ==== */
|
||||
void usb1_host_init_pipe_status(void);
|
||||
int32_t usb1_host_CtrlTransStart(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
|
||||
void usb1_host_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len);
|
||||
void usb1_host_CtrlReadStart(uint32_t Bsize, uint8_t *Table);
|
||||
uint16_t usb1_host_CtrlWriteStart(uint32_t Bsize, uint8_t *Table);
|
||||
void usb1_host_StatusStage(void);
|
||||
void usb1_host_get_devadd(uint16_t addr, uint16_t *devadd);
|
||||
void usb1_host_set_devadd(uint16_t addr, uint16_t *devadd);
|
||||
void usb1_host_InitModule(void);
|
||||
uint16_t usb1_host_CheckAttach(void);
|
||||
void usb1_host_UsbDetach(void);
|
||||
void usb1_host_UsbDetach2(void);
|
||||
void usb1_host_UsbAttach(void);
|
||||
uint16_t usb1_host_UsbBusReset(void);
|
||||
int32_t usb1_host_UsbResume(void);
|
||||
int32_t usb1_host_UsbSuspend(void);
|
||||
void usb1_host_Enable_DetachINT(void);
|
||||
void usb1_host_Disable_DetachINT(void);
|
||||
void usb1_host_UsbStateManager(void);
|
||||
|
||||
|
||||
#endif /* USB1_HOST_H */
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_host_api.h
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
*******************************************************************************/
|
||||
#ifndef USB1_HOST_API_H
|
||||
#define USB1_HOST_API_H
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Variable Externs
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Functions Prototypes
|
||||
*******************************************************************************/
|
||||
void usb1_host_interrupt(uint32_t int_sense);
|
||||
void usb1_host_dma_interrupt_d0fifo(uint32_t int_sense);
|
||||
void usb1_host_dma_interrupt_d1fifo(uint32_t int_sense);
|
||||
|
||||
uint16_t usb1_api_host_init(uint8_t int_level, uint16_t mode, uint16_t clockmode);
|
||||
int32_t usb1_api_host_enumeration(uint16_t devadr);
|
||||
int32_t usb1_api_host_detach(void);
|
||||
int32_t usb1_api_host_data_in(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
|
||||
int32_t usb1_api_host_data_out(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
|
||||
int32_t usb1_api_host_control_transfer(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
|
||||
int32_t usb1_api_host_set_endpoint(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor);
|
||||
int32_t usb1_api_host_clear_endpoint(USB_HOST_CFG_PIPETBL_t *user_table);
|
||||
int32_t usb1_api_host_clear_endpoint_pipe(uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table);
|
||||
uint16_t usb1_api_host_SetEndpointTable(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *Table);
|
||||
int32_t usb1_api_host_data_count(uint16_t pipe, uint32_t *data_count);
|
||||
|
||||
int32_t usb1_api_host_GetDeviceDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf);
|
||||
int32_t usb1_api_host_GetConfigDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf);
|
||||
int32_t usb1_api_host_SetConfig(uint16_t devadr, uint16_t confignum);
|
||||
int32_t usb1_api_host_SetInterface(uint16_t devadr, uint16_t interface_alt, uint16_t interface_index);
|
||||
int32_t usb1_api_host_ClearStall(uint16_t devadr, uint16_t ep_dir);
|
||||
uint16_t usb1_api_host_GetUsbDeviceState(void);
|
||||
|
||||
void usb1_api_host_elt_4_4(void);
|
||||
void usb1_api_host_elt_4_5(void);
|
||||
void usb1_api_host_elt_4_6(void);
|
||||
void usb1_api_host_elt_4_7(void);
|
||||
void usb1_api_host_elt_4_8(void);
|
||||
void usb1_api_host_elt_4_9(void);
|
||||
void usb1_api_host_elt_get_desc(void);
|
||||
|
||||
void usb1_host_EL_ModeInit(void);
|
||||
void usb1_host_EL_SetUACT(void);
|
||||
void usb1_host_EL_ClearUACT(void);
|
||||
void usb1_host_EL_SetTESTMODE(uint16_t mode);
|
||||
void usb1_host_EL_ClearNRDYSTS(uint16_t pipe);
|
||||
uint16_t usb1_host_EL_GetINTSTS1(void);
|
||||
void usb1_host_EL_UsbBusReset(void);
|
||||
void usb1_host_EL_UsbAttach(void);
|
||||
void usb1_host_EL_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len);
|
||||
void usb1_host_EL_StatusStage(void);
|
||||
void usb1_host_EL_CtrlReadStart(uint32_t Bsize, uint8_t *Table);
|
||||
int32_t usb1_host_EL_UsbSuspend(void);
|
||||
int32_t usb1_host_EL_UsbResume(void);
|
||||
|
||||
#if 0 /* prototype in devdrv_usb_host_api.h */
|
||||
uint16_t Userdef_USB_usb1_host_d0fifo_dmaintid(void);
|
||||
uint16_t Userdef_USB_usb1_host_d1fifo_dmaintid(void);
|
||||
void Userdef_USB_usb1_host_attach(void);
|
||||
void Userdef_USB_usb1_host_detach(void);
|
||||
void Userdef_USB_usb1_host_delay_1ms(void);
|
||||
void Userdef_USB_usb1_host_delay_xms(uint32_t msec);
|
||||
void Userdef_USB_usb1_host_delay_10us(uint32_t usec);
|
||||
void Userdef_USB_usb1_host_delay_500ns(void);
|
||||
void Userdef_USB_usb1_host_start_dma(USB_HOST_DMA_t *dma, uint16_t dfacc);
|
||||
uint32_t Userdef_USB_usb1_host_stop_dma0(void);
|
||||
uint32_t Userdef_USB_usb1_host_stop_dma1(void);
|
||||
#endif
|
||||
|
||||
#endif /* USB1_HOST_API_H */
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,139 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_host_dmacdrv.h
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
*******************************************************************************/
|
||||
#ifndef USB1_HOST_DMACDRV_H
|
||||
#define USB1_HOST_DMACDRV_H
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
typedef struct dmac_transinfo
|
||||
{
|
||||
uint32_t src_addr; /* Transfer source address */
|
||||
uint32_t dst_addr; /* Transfer destination address */
|
||||
uint32_t count; /* Transfer byte count */
|
||||
uint32_t src_size; /* Transfer source data size */
|
||||
uint32_t dst_size; /* Transfer destination data size */
|
||||
uint32_t saddr_dir; /* Transfer source address direction */
|
||||
uint32_t daddr_dir; /* Transfer destination address direction */
|
||||
} dmac_transinfo_t;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
/* ==== Transfer specification of the sample program ==== */
|
||||
#define DMAC_SAMPLE_SINGLE (0) /* Single transfer */
|
||||
#define DMAC_SAMPLE_CONTINUATION (1) /* Continuous transfer (use REN bit) */
|
||||
|
||||
/* ==== DMA modes ==== */
|
||||
#define DMAC_MODE_REGISTER (0) /* Register mode */
|
||||
#define DMAC_MODE_LINK (1) /* Link mode */
|
||||
|
||||
/* ==== Transfer requests ==== */
|
||||
#define DMAC_REQ_MODE_EXT (0) /* External request */
|
||||
#define DMAC_REQ_MODE_PERI (1) /* On-chip peripheral module request */
|
||||
#define DMAC_REQ_MODE_SOFT (2) /* Auto-request (request by software) */
|
||||
|
||||
/* ==== DMAC transfer sizes ==== */
|
||||
#define DMAC_TRANS_SIZE_8 (0) /* 8 bits */
|
||||
#define DMAC_TRANS_SIZE_16 (1) /* 16 bits */
|
||||
#define DMAC_TRANS_SIZE_32 (2) /* 32 bits */
|
||||
#define DMAC_TRANS_SIZE_64 (3) /* 64 bits */
|
||||
#define DMAC_TRANS_SIZE_128 (4) /* 128 bits */
|
||||
#define DMAC_TRANS_SIZE_256 (5) /* 256 bits */
|
||||
#define DMAC_TRANS_SIZE_512 (6) /* 512 bits */
|
||||
#define DMAC_TRANS_SIZE_1024 (7) /* 1024 bits */
|
||||
|
||||
/* ==== Address increment for transferring ==== */
|
||||
#define DMAC_TRANS_ADR_NO_INC (1) /* Not increment */
|
||||
#define DMAC_TRANS_ADR_INC (0) /* Increment */
|
||||
|
||||
/* ==== Method for detecting DMA request ==== */
|
||||
#define DMAC_REQ_DET_FALL (0) /* Falling edge detection */
|
||||
#define DMAC_REQ_DET_RISE (1) /* Rising edge detection */
|
||||
#define DMAC_REQ_DET_LOW (2) /* Low level detection */
|
||||
#define DMAC_REQ_DET_HIGH (3) /* High level detection */
|
||||
|
||||
/* ==== Request Direction ==== */
|
||||
#define DMAC_REQ_DIR_SRC (0) /* DMAREQ is the source/ DMAACK is active when reading */
|
||||
#define DMAC_REQ_DIR_DST (1) /* DMAREQ is the destination/ DMAACK is active when writing */
|
||||
|
||||
/* ==== Descriptors ==== */
|
||||
#define DMAC_DESC_HEADER (0) /* Header */
|
||||
#define DMAC_DESC_SRC_ADDR (1) /* Source Address */
|
||||
#define DMAC_DESC_DST_ADDR (2) /* Destination Address */
|
||||
#define DMAC_DESC_COUNT (3) /* Transaction Byte */
|
||||
#define DMAC_DESC_CHCFG (4) /* Channel Confg */
|
||||
#define DMAC_DESC_CHITVL (5) /* Channel Interval */
|
||||
#define DMAC_DESC_CHEXT (6) /* Channel Extension */
|
||||
#define DMAC_DESC_LINK_ADDR (7) /* Link Address */
|
||||
|
||||
/* ==== On-chip peripheral module requests ===== */
|
||||
typedef enum dmac_request_factor
|
||||
{
|
||||
DMAC_REQ_USB0_DMA0_TX, /* USB_0 channel 0 transmit FIFO empty */
|
||||
DMAC_REQ_USB0_DMA0_RX, /* USB_0 channel 0 receive FIFO full */
|
||||
DMAC_REQ_USB0_DMA1_TX, /* USB_0 channel 1 transmit FIFO empty */
|
||||
DMAC_REQ_USB0_DMA1_RX, /* USB_0 channel 1 receive FIFO full */
|
||||
DMAC_REQ_USB1_DMA0_TX, /* USB_1 channel 0 transmit FIFO empty */
|
||||
DMAC_REQ_USB1_DMA0_RX, /* USB_1 channel 0 receive FIFO full */
|
||||
DMAC_REQ_USB1_DMA1_TX, /* USB_1 channel 1 transmit FIFO empty */
|
||||
DMAC_REQ_USB1_DMA1_RX, /* USB_1 channel 1 receive FIFO full */
|
||||
} dmac_request_factor_t;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Variable Externs
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Functions Prototypes
|
||||
*******************************************************************************/
|
||||
void usb1_host_DMAC3_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
|
||||
uint32_t request_factor, uint32_t req_direction);
|
||||
int32_t usb1_host_DMAC3_Open(uint32_t req);
|
||||
void usb1_host_DMAC3_Close(uint32_t *remain);
|
||||
void usb1_host_DMAC3_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
|
||||
|
||||
void usb1_host_DMAC4_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
|
||||
uint32_t request_factor, uint32_t req_direction);
|
||||
int32_t usb1_host_DMAC4_Open(uint32_t req);
|
||||
void usb1_host_DMAC4_Close(uint32_t *remain);
|
||||
void usb1_host_DMAC4_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
|
||||
|
||||
#endif /* USB1_HOST_DMACDRV_H */
|
||||
|
||||
/* End of File */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,355 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_host_dma.c
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Device(s) : RZ/A1H
|
||||
* Tool-Chain :
|
||||
* OS : None
|
||||
* H/W Platform :
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
* Operation :
|
||||
* Limitations :
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include "usb1_host.h"
|
||||
/* #include "usb1_host_dmacdrv.h" */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private global variables and functions
|
||||
*******************************************************************************/
|
||||
static void usb1_host_dmaint(uint16_t fifo);
|
||||
static void usb1_host_dmaint_buf2fifo(uint16_t pipe);
|
||||
static void usb1_host_dmaint_fifo2buf(uint16_t pipe);
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_dma_stop_d0
|
||||
* Description : D0FIFO DMA stop
|
||||
* Arguments : uint16_t pipe : pipe number
|
||||
* : uint32_t remain : transfer byte
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_dma_stop_d0 (uint16_t pipe, uint32_t remain)
|
||||
{
|
||||
uint16_t dtln;
|
||||
uint16_t dfacc;
|
||||
uint16_t buffer;
|
||||
uint16_t sds_b = 1;
|
||||
|
||||
dfacc = RZA_IO_RegRead_16(&USB201.D0FBCFG,
|
||||
USB_DnFBCFG_DFACC_SHIFT,
|
||||
USB_DnFBCFG_DFACC);
|
||||
if (dfacc == 2)
|
||||
{
|
||||
sds_b = 32;
|
||||
}
|
||||
else if (dfacc == 1)
|
||||
{
|
||||
sds_b = 16;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size == 2)
|
||||
{
|
||||
sds_b = 4;
|
||||
}
|
||||
else if (g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size == 1)
|
||||
{
|
||||
sds_b = 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
sds_b = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
|
||||
{
|
||||
if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
|
||||
{
|
||||
buffer = USB201.D0FIFOCTR;
|
||||
dtln = (buffer & USB_HOST_BITDTLN);
|
||||
|
||||
if ((dtln % sds_b) != 0)
|
||||
{
|
||||
remain += (sds_b - (dtln % sds_b));
|
||||
}
|
||||
g_usb1_host_PipeDataSize[pipe] = (g_usb1_host_data_count[pipe] - remain);
|
||||
g_usb1_host_data_count[pipe] = remain;
|
||||
}
|
||||
}
|
||||
|
||||
RZA_IO_RegWrite_16(&USB201.D0FIFOSEL,
|
||||
0,
|
||||
USB_DnFIFOSEL_DREQE_SHIFT,
|
||||
USB_DnFIFOSEL_DREQE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_dma_stop_d1
|
||||
* Description : D1FIFO DMA stop
|
||||
* Arguments : uint16_t pipe : pipe number
|
||||
* : uint32_t remain : transfer byte
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_dma_stop_d1 (uint16_t pipe, uint32_t remain)
|
||||
{
|
||||
uint16_t dtln;
|
||||
uint16_t dfacc;
|
||||
uint16_t buffer;
|
||||
uint16_t sds_b = 1;
|
||||
|
||||
dfacc = RZA_IO_RegRead_16(&USB201.D1FBCFG,
|
||||
USB_DnFBCFG_DFACC_SHIFT,
|
||||
USB_DnFBCFG_DFACC);
|
||||
if (dfacc == 2)
|
||||
{
|
||||
sds_b = 32;
|
||||
}
|
||||
else if (dfacc == 1)
|
||||
{
|
||||
sds_b = 16;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size == 2)
|
||||
{
|
||||
sds_b = 4;
|
||||
}
|
||||
else if (g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size == 1)
|
||||
{
|
||||
sds_b = 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
sds_b = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
|
||||
{
|
||||
if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
|
||||
{
|
||||
buffer = USB201.D1FIFOCTR;
|
||||
dtln = (buffer & USB_HOST_BITDTLN);
|
||||
|
||||
if ((dtln % sds_b) != 0)
|
||||
{
|
||||
remain += (sds_b - (dtln % sds_b));
|
||||
}
|
||||
g_usb1_host_PipeDataSize[pipe] = (g_usb1_host_data_count[pipe] - remain);
|
||||
g_usb1_host_data_count[pipe] = remain;
|
||||
}
|
||||
}
|
||||
|
||||
RZA_IO_RegWrite_16(&USB201.D1FIFOSEL,
|
||||
0,
|
||||
USB_DnFIFOSEL_DREQE_SHIFT,
|
||||
USB_DnFIFOSEL_DREQE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_dma_interrupt_d0fifo
|
||||
* Description : This function is DMA interrupt handler entry.
|
||||
* : Execute usb1_host_dmaint() after disabling DMA interrupt in this function.
|
||||
* : Disable DMA interrupt to DMAC executed when USB_HOST_D0FIFO_DMA is
|
||||
* : specified by dma->fifo.
|
||||
* : Register this function as DMA complete interrupt.
|
||||
* Arguments : uint32_t int_sense ; Interrupts detection mode
|
||||
* : ; INTC_LEVEL_SENSITIVE : Level sense
|
||||
* : ; INTC_EDGE_TRIGGER : Edge trigger
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_dma_interrupt_d0fifo (uint32_t int_sense)
|
||||
{
|
||||
usb1_host_dmaint(USB_HOST_D0FIFO);
|
||||
g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_dma_interrupt_d1fifo
|
||||
* Description : This function is DMA interrupt handler entry.
|
||||
* : Execute usb0_host_dmaint() after disabling DMA interrupt in this function.
|
||||
* : Disable DMA interrupt to DMAC executed when USB_HOST_D1FIFO_DMA is
|
||||
* : specified by dma->fifo.
|
||||
* : Register this function as DMA complete interrupt.
|
||||
* Arguments : uint32_t int_sense ; Interrupts detection mode
|
||||
* : ; INTC_LEVEL_SENSITIVE : Level sense
|
||||
* : ; INTC_EDGE_TRIGGER : Edge trigger
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_dma_interrupt_d1fifo (uint32_t int_sense)
|
||||
{
|
||||
usb1_host_dmaint(USB_HOST_D1FIFO);
|
||||
g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_dmaint
|
||||
* Description : This function is DMA transfer end interrupt
|
||||
* Arguments : uint16_t fifo ; fifo number
|
||||
* : ; USB_HOST_D0FIFO
|
||||
* : ; USB_HOST_D1FIFO
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
static void usb1_host_dmaint (uint16_t fifo)
|
||||
{
|
||||
uint16_t pipe;
|
||||
|
||||
pipe = g_usb1_host_DmaPipe[fifo];
|
||||
|
||||
if (g_usb1_host_DmaInfo[fifo].dir == USB_HOST_BUF2FIFO)
|
||||
{
|
||||
usb1_host_dmaint_buf2fifo(pipe);
|
||||
}
|
||||
else
|
||||
{
|
||||
usb1_host_dmaint_fifo2buf(pipe);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_dmaint_fifo2buf
|
||||
* Description : Executes read completion from FIFO by DMAC.
|
||||
* Arguments : uint16_t pipe : pipe number
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
static void usb1_host_dmaint_fifo2buf (uint16_t pipe)
|
||||
{
|
||||
uint32_t remain;
|
||||
uint16_t useport;
|
||||
|
||||
if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
|
||||
{
|
||||
useport = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
|
||||
|
||||
if (useport == USB_HOST_D0FIFO_DMA)
|
||||
{
|
||||
remain = Userdef_USB_usb1_host_stop_dma0();
|
||||
usb1_host_dma_stop_d0(pipe, remain);
|
||||
|
||||
if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
|
||||
{
|
||||
if (g_usb1_host_DmaStatus[USB_HOST_D0FIFO] == USB_HOST_DMA_BUSYEND)
|
||||
{
|
||||
USB201.D0FIFOCTR = USB_HOST_BITBCLR;
|
||||
g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
usb1_host_enable_brdy_int(pipe);
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
remain = Userdef_USB_usb1_host_stop_dma1();
|
||||
usb1_host_dma_stop_d1(pipe, remain);
|
||||
|
||||
if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
|
||||
{
|
||||
if (g_usb1_host_DmaStatus[USB_HOST_D1FIFO] == USB_HOST_DMA_BUSYEND)
|
||||
{
|
||||
USB201.D1FIFOCTR = USB_HOST_BITBCLR;
|
||||
g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
usb1_host_enable_brdy_int(pipe);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_dmaint_buf2fifo
|
||||
* Description : Executes write completion in FIFO by DMAC.
|
||||
* Arguments : uint16_t pipe : pipe number
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
static void usb1_host_dmaint_buf2fifo (uint16_t pipe)
|
||||
{
|
||||
uint16_t useport;
|
||||
uint32_t remain;
|
||||
|
||||
useport = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
|
||||
|
||||
if (useport == USB_HOST_D0FIFO_DMA)
|
||||
{
|
||||
remain = Userdef_USB_usb1_host_stop_dma0();
|
||||
usb1_host_dma_stop_d0(pipe, remain);
|
||||
|
||||
if (g_usb1_host_DmaBval[USB_HOST_D0FIFO] != 0)
|
||||
{
|
||||
RZA_IO_RegWrite_16(&USB201.D0FIFOCTR,
|
||||
1,
|
||||
USB_DnFIFOCTR_BVAL_SHIFT,
|
||||
USB_DnFIFOCTR_BVAL);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
remain = Userdef_USB_usb1_host_stop_dma1();
|
||||
usb1_host_dma_stop_d1(pipe, remain);
|
||||
|
||||
if (g_usb1_host_DmaBval[USB_HOST_D1FIFO] != 0)
|
||||
{
|
||||
RZA_IO_RegWrite_16(&USB201.D1FIFOCTR,
|
||||
1,
|
||||
USB_DnFIFOCTR_BVAL_SHIFT,
|
||||
USB_DnFIFOCTR_BVAL);
|
||||
}
|
||||
}
|
||||
|
||||
usb1_host_enable_bemp_int(pipe);
|
||||
}
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,285 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_host_intrn.c
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Device(s) : RZ/A1H
|
||||
* Tool-Chain :
|
||||
* OS : None
|
||||
* H/W Platform :
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
* Operation :
|
||||
* Limitations :
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include "usb1_host.h"
|
||||
#if(1) /* ohci_wrapp */
|
||||
#include "ohci_wrapp_RZ_A1_local.h"
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private global variables and functions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_brdy_int
|
||||
* Description : Executes BRDY interrupt(USB_HOST_PIPE1-9).
|
||||
* : According to the pipe that interrupt is generated in,
|
||||
* : reads/writes buffer allocated in the pipe.
|
||||
* : This function is executed in the BRDY interrupt handler.
|
||||
* : This function clears BRDY interrupt status and BEMP interrupt
|
||||
* : status.
|
||||
* Arguments : uint16_t status ; BRDYSTS Register Value
|
||||
* : uint16_t int_enb ; BRDYENB Register Value
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_brdy_int (uint16_t status, uint16_t int_enb)
|
||||
{
|
||||
uint32_t int_sense = 0;
|
||||
uint16_t pipe;
|
||||
uint16_t pipebit;
|
||||
|
||||
for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
|
||||
{
|
||||
pipebit = g_usb1_host_bit_set[pipe];
|
||||
|
||||
if ((status & pipebit) && (int_enb & pipebit))
|
||||
{
|
||||
USB201.BRDYSTS = (uint16_t)~pipebit;
|
||||
USB201.BEMPSTS = (uint16_t)~pipebit;
|
||||
|
||||
if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA)
|
||||
{
|
||||
if (g_usb1_host_DmaStatus[USB_HOST_D0FIFO] != USB_HOST_DMA_READY)
|
||||
{
|
||||
usb1_host_dma_interrupt_d0fifo(int_sense);
|
||||
}
|
||||
|
||||
if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
|
||||
{
|
||||
usb1_host_read_dma(pipe);
|
||||
usb1_host_disable_brdy_int(pipe);
|
||||
}
|
||||
else
|
||||
{
|
||||
USB201.D0FIFOCTR = USB_HOST_BITBCLR;
|
||||
g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
|
||||
}
|
||||
}
|
||||
else if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_DMA)
|
||||
{
|
||||
if (g_usb1_host_DmaStatus[USB_HOST_D1FIFO] != USB_HOST_DMA_READY)
|
||||
{
|
||||
usb1_host_dma_interrupt_d1fifo(int_sense);
|
||||
}
|
||||
|
||||
if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
|
||||
{
|
||||
usb1_host_read_dma(pipe);
|
||||
usb1_host_disable_brdy_int(pipe);
|
||||
}
|
||||
else
|
||||
{
|
||||
USB201.D1FIFOCTR = USB_HOST_BITBCLR;
|
||||
g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
|
||||
{
|
||||
usb1_host_read_buffer(pipe);
|
||||
}
|
||||
else
|
||||
{
|
||||
usb1_host_write_buffer(pipe);
|
||||
}
|
||||
}
|
||||
#if(1) /* ohci_wrapp */
|
||||
switch (g_usb1_host_pipe_status[pipe])
|
||||
{
|
||||
case USB_HOST_PIPE_DONE:
|
||||
ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
|
||||
break;
|
||||
case USB_HOST_PIPE_NORES:
|
||||
case USB_HOST_PIPE_STALL:
|
||||
case USB_HOST_PIPE_ERROR:
|
||||
ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
|
||||
break;
|
||||
default:
|
||||
/* Do Nothing */
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_nrdy_int
|
||||
* Description : Executes NRDY interrupt(USB_HOST_PIPE1-9).
|
||||
* : Checks NRDY interrupt cause by PID. When the cause if STALL,
|
||||
* : regards the pipe state as STALL and ends the processing.
|
||||
* : Then the cause is not STALL, increments the error count to
|
||||
* : communicate again. When the error count is 3, determines
|
||||
* : the pipe state as USB_HOST_PIPE_NORES and ends the processing.
|
||||
* : This function is executed in the NRDY interrupt handler.
|
||||
* : This function clears NRDY interrupt status.
|
||||
* Arguments : uint16_t status ; NRDYSTS Register Value
|
||||
* : uint16_t int_enb ; NRDYENB Register Value
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_nrdy_int (uint16_t status, uint16_t int_enb)
|
||||
{
|
||||
uint16_t pid;
|
||||
uint16_t pipe;
|
||||
uint16_t bitcheck;
|
||||
|
||||
bitcheck = (uint16_t)(status & int_enb);
|
||||
|
||||
USB201.NRDYSTS = (uint16_t)~status;
|
||||
|
||||
for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
|
||||
{
|
||||
if ((bitcheck&g_usb1_host_bit_set[pipe]) == g_usb1_host_bit_set[pipe])
|
||||
{
|
||||
if (RZA_IO_RegRead_16(&USB201.SYSCFG0,
|
||||
USB_SYSCFG_DCFM_SHIFT,
|
||||
USB_SYSCFG_DCFM) == 1)
|
||||
{
|
||||
if (g_usb1_host_pipe_status[pipe] == USB_HOST_PIPE_WAIT)
|
||||
{
|
||||
pid = usb1_host_get_pid(pipe);
|
||||
|
||||
if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
|
||||
{
|
||||
g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
|
||||
#if(1) /* ohci_wrapp */
|
||||
ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
#if(1) /* ohci_wrapp */
|
||||
g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
|
||||
ohciwrapp_loc_TransEnd(pipe, TD_CC_DEVICENOTRESPONDING);
|
||||
#else
|
||||
g_usb1_host_PipeIgnore[pipe]++;
|
||||
|
||||
if (g_usb1_host_PipeIgnore[pipe] == 3)
|
||||
{
|
||||
g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
|
||||
}
|
||||
else
|
||||
{
|
||||
usb1_host_set_pid_buf(pipe);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* USB Function */
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_bemp_int
|
||||
* Description : Executes BEMP interrupt(USB_HOST_PIPE1-9).
|
||||
* Arguments : uint16_t status ; BEMPSTS Register Value
|
||||
* : uint16_t int_enb ; BEMPENB Register Value
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_bemp_int (uint16_t status, uint16_t int_enb)
|
||||
{
|
||||
uint16_t pid;
|
||||
uint16_t pipe;
|
||||
uint16_t bitcheck;
|
||||
uint16_t inbuf;
|
||||
|
||||
bitcheck = (uint16_t)(status & int_enb);
|
||||
|
||||
USB201.BEMPSTS = (uint16_t)~status;
|
||||
|
||||
for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
|
||||
{
|
||||
if ((bitcheck&g_usb1_host_bit_set[pipe]) == g_usb1_host_bit_set[pipe])
|
||||
{
|
||||
pid = usb1_host_get_pid(pipe);
|
||||
|
||||
if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
|
||||
{
|
||||
g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
|
||||
#if(1) /* ohci_wrapp */
|
||||
ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
inbuf = usb1_host_get_inbuf(pipe);
|
||||
|
||||
if (inbuf == 0)
|
||||
{
|
||||
usb1_host_disable_bemp_int(pipe);
|
||||
usb1_host_set_pid_nak(pipe);
|
||||
g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
|
||||
#if(1) /* ohci_wrapp */
|
||||
ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* End of File */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,434 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_host_controlrw.c
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Device(s) : RZ/A1H
|
||||
* Tool-Chain :
|
||||
* OS : None
|
||||
* H/W Platform :
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
* Operation :
|
||||
* Limitations :
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include "usb1_host.h"
|
||||
#include "dev_drv.h"
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private global variables and functions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_CtrlTransStart
|
||||
* Description : Executes USB control transfer.
|
||||
* Arguments : uint16_t devadr ; device address
|
||||
* : uint16_t Req ; bmRequestType & bRequest
|
||||
* : uint16_t Val ; wValue
|
||||
* : uint16_t Indx ; wIndex
|
||||
* : uint16_t Len ; wLength
|
||||
* : uint8_t *Buf ; Data buffer
|
||||
* Return Value : DEVDRV_SUCCESS ; SUCCESS
|
||||
* : DEVDRV_ERROR ; ERROR
|
||||
*******************************************************************************/
|
||||
int32_t usb1_host_CtrlTransStart (uint16_t devadr, uint16_t Req, uint16_t Val,
|
||||
uint16_t Indx, uint16_t Len, uint8_t * Buf)
|
||||
{
|
||||
if (g_usb1_host_UsbDeviceSpeed == USB_HOST_LOW_SPEED)
|
||||
{
|
||||
RZA_IO_RegWrite_16(&USB201.SOFCFG,
|
||||
1,
|
||||
USB_SOFCFG_TRNENSEL_SHIFT,
|
||||
USB_SOFCFG_TRNENSEL);
|
||||
}
|
||||
else
|
||||
{
|
||||
RZA_IO_RegWrite_16(&USB201.SOFCFG,
|
||||
0,
|
||||
USB_SOFCFG_TRNENSEL_SHIFT,
|
||||
USB_SOFCFG_TRNENSEL);
|
||||
}
|
||||
|
||||
USB201.DCPMAXP = (uint16_t)((uint16_t)(devadr << 12) + g_usb1_host_default_max_packet[devadr]);
|
||||
|
||||
if (g_usb1_host_pipe_status[USB_HOST_PIPE0] == USB_HOST_PIPE_IDLE)
|
||||
{
|
||||
g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT;
|
||||
g_usb1_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
|
||||
g_usb1_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE);
|
||||
|
||||
if (Len == 0)
|
||||
{
|
||||
g_usb1_host_CmdStage |= USB_HOST_MODE_NO_DATA; /* No-data Control */
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((Req & 0x0080) != 0)
|
||||
{
|
||||
g_usb1_host_CmdStage |= USB_HOST_MODE_READ; /* Control Read */
|
||||
}
|
||||
else
|
||||
{
|
||||
g_usb1_host_CmdStage |= USB_HOST_MODE_WRITE; /* Control Write */
|
||||
}
|
||||
}
|
||||
|
||||
g_usb1_host_SavReq = Req; /* save request */
|
||||
g_usb1_host_SavVal = Val;
|
||||
g_usb1_host_SavIndx = Indx;
|
||||
g_usb1_host_SavLen = Len;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((g_usb1_host_SavReq != Req) || (g_usb1_host_SavVal != Val)
|
||||
|| (g_usb1_host_SavIndx != Indx) || (g_usb1_host_SavLen != Len))
|
||||
{
|
||||
return DEVDRV_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
switch ((g_usb1_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
|
||||
{
|
||||
/* --------------- SETUP STAGE --------------- */
|
||||
case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE):
|
||||
usb1_host_SetupStage(Req, Val, Indx, Len);
|
||||
break;
|
||||
|
||||
case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DOING):
|
||||
/* do nothing */
|
||||
break;
|
||||
|
||||
case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DONE): /* goto next stage */
|
||||
g_usb1_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
|
||||
switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD)))
|
||||
{
|
||||
case USB_HOST_MODE_WRITE:
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_STAGE_DATA;
|
||||
break;
|
||||
|
||||
case USB_HOST_MODE_READ:
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_STAGE_DATA;
|
||||
break;
|
||||
|
||||
case USB_HOST_MODE_NO_DATA:
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
|
||||
break;
|
||||
|
||||
case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_NORES):
|
||||
if (g_usb1_host_PipeIgnore[USB_HOST_PIPE0] == 3)
|
||||
{
|
||||
g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
|
||||
}
|
||||
else
|
||||
{
|
||||
g_usb1_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
|
||||
}
|
||||
break;
|
||||
|
||||
/* --------------- DATA STAGE --------------- */
|
||||
case (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE):
|
||||
switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD)))
|
||||
{
|
||||
case USB_HOST_MODE_WRITE:
|
||||
usb1_host_CtrlWriteStart((uint32_t)Len, Buf);
|
||||
break;
|
||||
|
||||
case USB_HOST_MODE_READ:
|
||||
usb1_host_CtrlReadStart((uint32_t)Len, Buf);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
|
||||
/* do nothing */
|
||||
break;
|
||||
|
||||
case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DONE): /* goto next stage */
|
||||
g_usb1_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
|
||||
break;
|
||||
|
||||
case (USB_HOST_STAGE_DATA | USB_HOST_CMD_NORES):
|
||||
if (g_usb1_host_PipeIgnore[USB_HOST_PIPE0] == 3)
|
||||
{
|
||||
g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
|
||||
}
|
||||
else
|
||||
{
|
||||
g_usb1_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
|
||||
usb1_host_clear_pid_stall(USB_HOST_PIPE0);
|
||||
usb1_host_set_pid_buf(USB_HOST_PIPE0);
|
||||
}
|
||||
break;
|
||||
|
||||
case (USB_HOST_STAGE_DATA | USB_HOST_CMD_STALL):
|
||||
g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
|
||||
break;
|
||||
|
||||
/* --------------- STATUS STAGE --------------- */
|
||||
case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE):
|
||||
usb1_host_StatusStage();
|
||||
break;
|
||||
|
||||
case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
|
||||
/* do nothing */
|
||||
break;
|
||||
|
||||
case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DONE): /* end of Control transfer */
|
||||
usb1_host_set_pid_nak(USB_HOST_PIPE0);
|
||||
g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_DONE; /* exit DONE */
|
||||
break;
|
||||
|
||||
case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_NORES):
|
||||
if (g_usb1_host_PipeIgnore[USB_HOST_PIPE0] == 3)
|
||||
{
|
||||
g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
|
||||
}
|
||||
else
|
||||
{
|
||||
g_usb1_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
|
||||
usb1_host_clear_pid_stall(USB_HOST_PIPE0);
|
||||
usb1_host_set_pid_buf(USB_HOST_PIPE0);
|
||||
}
|
||||
break;
|
||||
|
||||
case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_STALL):
|
||||
g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (g_usb1_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT)
|
||||
{
|
||||
RZA_IO_RegWrite_16(&USB201.SOFCFG,
|
||||
0,
|
||||
USB_SOFCFG_TRNENSEL_SHIFT,
|
||||
USB_SOFCFG_TRNENSEL);
|
||||
}
|
||||
|
||||
return DEVDRV_SUCCESS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_SetupStage
|
||||
* Description : Executes USB control transfer/set up stage.
|
||||
* Arguments : uint16_t Req ; bmRequestType & bRequest
|
||||
* : uint16_t Val ; wValue
|
||||
* : uint16_t Indx ; wIndex
|
||||
* : uint16_t Len ; wLength
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_SetupStage (uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len)
|
||||
{
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
|
||||
|
||||
USB201.INTSTS1 = (uint16_t)~(USB_HOST_BITSACK | USB_HOST_BITSIGN); /* Status Clear */
|
||||
USB201.USBREQ = Req;
|
||||
USB201.USBVAL = Val;
|
||||
USB201.USBINDX = Indx;
|
||||
USB201.USBLENG = Len;
|
||||
USB201.DCPCTR = USB_HOST_BITSUREQ; /* PID=NAK & Send Setup */
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_StatusStage
|
||||
* Description : Executes USB control transfer/status stage.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_StatusStage (void)
|
||||
{
|
||||
uint8_t Buf1[16];
|
||||
|
||||
switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD)))
|
||||
{
|
||||
case USB_HOST_MODE_READ:
|
||||
usb1_host_CtrlWriteStart((uint32_t)0, (uint8_t*)&Buf1);
|
||||
break;
|
||||
|
||||
case USB_HOST_MODE_WRITE:
|
||||
usb1_host_CtrlReadStart((uint32_t)0, (uint8_t*)&Buf1);
|
||||
break;
|
||||
|
||||
case USB_HOST_MODE_NO_DATA:
|
||||
usb1_host_CtrlReadStart((uint32_t)0, (uint8_t*)&Buf1);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_CtrlWriteStart
|
||||
* Description : Executes USB control transfer/data stage(write).
|
||||
* Arguments : uint32_t Bsize ; Data Size
|
||||
* : uint8_t *Table ; Data Table Address
|
||||
* Return Value : USB_HOST_WRITESHRT ; End of data write
|
||||
* : USB_HOST_WRITEEND ; End of data write (not null)
|
||||
* : USB_HOST_WRITING ; Continue of data write
|
||||
* : USB_HOST_FIFOERROR ; FIFO access error
|
||||
*******************************************************************************/
|
||||
uint16_t usb1_host_CtrlWriteStart (uint32_t Bsize, uint8_t * Table)
|
||||
{
|
||||
uint16_t EndFlag_K;
|
||||
uint16_t mbw;
|
||||
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
|
||||
|
||||
usb1_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */
|
||||
g_usb1_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */
|
||||
g_usb1_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */
|
||||
|
||||
USB201.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */
|
||||
#if(1) /* ohci_wrapp */
|
||||
Userdef_USB_usb1_host_delay_10us(3);
|
||||
#endif
|
||||
RZA_IO_RegWrite_16(&USB201.DCPCFG,
|
||||
1,
|
||||
USB_DCPCFG_DIR_SHIFT,
|
||||
USB_DCPCFG_DIR);
|
||||
|
||||
mbw = usb1_host_get_mbw(g_usb1_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb1_host_data_pointer[USB_HOST_PIPE0]);
|
||||
usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_BITISEL, mbw);
|
||||
USB201.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
|
||||
|
||||
usb1_host_clear_pid_stall(USB_HOST_PIPE0);
|
||||
EndFlag_K = usb1_host_write_buffer_c(USB_HOST_PIPE0);
|
||||
/* Host Control sequence */
|
||||
switch (EndFlag_K)
|
||||
{
|
||||
case USB_HOST_WRITESHRT: /* End of data write */
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
|
||||
usb1_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
|
||||
usb1_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */
|
||||
break;
|
||||
|
||||
case USB_HOST_WRITEEND: /* End of data write (not null) */
|
||||
case USB_HOST_WRITING: /* Continue of data write */
|
||||
usb1_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
|
||||
usb1_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */
|
||||
break;
|
||||
|
||||
case USB_HOST_FIFOERROR: /* FIFO access error */
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
usb1_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */
|
||||
return (EndFlag_K); /* End or Err or Continue */
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_CtrlReadStart
|
||||
* Description : Executes USB control transfer/data stage(read).
|
||||
* Arguments : uint32_t Bsize ; Data Size
|
||||
* : uint8_t *Table ; Data Table Address
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_CtrlReadStart (uint32_t Bsize, uint8_t * Table)
|
||||
{
|
||||
uint16_t mbw;
|
||||
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
|
||||
|
||||
usb1_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */
|
||||
g_usb1_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */
|
||||
g_usb1_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */
|
||||
|
||||
USB201.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */
|
||||
#if(1) /* ohci_wrapp */
|
||||
Userdef_USB_usb1_host_delay_10us(3);
|
||||
#endif
|
||||
RZA_IO_RegWrite_16(&USB201.DCPCFG,
|
||||
0,
|
||||
USB_DCPCFG_DIR_SHIFT,
|
||||
USB_DCPCFG_DIR);
|
||||
|
||||
mbw = usb1_host_get_mbw(g_usb1_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb1_host_data_pointer[USB_HOST_PIPE0]);
|
||||
usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, mbw);
|
||||
USB201.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
|
||||
|
||||
usb1_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
|
||||
usb1_host_enable_brdy_int(USB_HOST_PIPE0); /* Ok */
|
||||
usb1_host_clear_pid_stall(USB_HOST_PIPE0);
|
||||
usb1_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */
|
||||
}
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,889 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_host_drv_api.c
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Device(s) : RZ/A1H
|
||||
* Tool-Chain :
|
||||
* OS : None
|
||||
* H/W Platform :
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
* Operation :
|
||||
* Limitations :
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include "usb1_host.h"
|
||||
#include "dev_drv.h"
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
static void usb1_host_resetEP(USB_HOST_CFG_PIPETBL_t *tbl);
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private global variables and functions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_host_init
|
||||
* Description : Initializes USB module in the USB host mode.
|
||||
* : USB connection is executed when executing this function in
|
||||
* : the states that USB device isconnected to the USB port.
|
||||
* Arguments : uint8_t int_level : USB Module interrupt level
|
||||
* : USBU16 mode : USB_HOST_HIGH_SPEED
|
||||
* : USB_HOST_FULL_SPEED
|
||||
* : uint16_t clockmode : USB Clock mode
|
||||
* Return Value : USB detach or attach
|
||||
* : USB_HOST_ATTACH
|
||||
* : USB_HOST_DETACH
|
||||
*******************************************************************************/
|
||||
uint16_t usb1_api_host_init (uint8_t int_level, uint16_t mode, uint16_t clockmode)
|
||||
{
|
||||
uint16_t connect;
|
||||
volatile uint8_t dummy_buf;
|
||||
|
||||
CPG.STBCR7 &= 0xfc; /*The clock of USB0/1 modules is permitted */
|
||||
dummy_buf = CPG.STBCR7; /* (Dummy read) */
|
||||
|
||||
g_usb1_host_SupportUsbDeviceSpeed = mode;
|
||||
|
||||
usb1_host_setting_interrupt(int_level);
|
||||
usb1_host_reset_module(clockmode);
|
||||
|
||||
g_usb1_host_bchg_flag = USB_HOST_NO;
|
||||
g_usb1_host_detach_flag = USB_HOST_NO;
|
||||
g_usb1_host_attach_flag = USB_HOST_NO;
|
||||
|
||||
g_usb1_host_driver_state = USB_HOST_DRV_DETACHED;
|
||||
g_usb1_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
|
||||
|
||||
usb1_host_InitModule();
|
||||
|
||||
connect = usb1_host_CheckAttach();
|
||||
|
||||
if (connect == USB_HOST_ATTACH)
|
||||
{
|
||||
g_usb1_host_attach_flag = USB_HOST_YES;
|
||||
}
|
||||
else
|
||||
{
|
||||
usb1_host_UsbDetach2();
|
||||
}
|
||||
|
||||
return connect;
|
||||
}
|
||||
|
||||
#if(1) /* ohci_wrapp */
|
||||
#else
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_host_enumeration
|
||||
* Description : Initializes USB module in the USB host mode.
|
||||
* : USB connection is executed when executing this function in
|
||||
* : the states that USB device isconnected to the USB port.
|
||||
* Arguments : uint16_t devadr : device address
|
||||
* Return Value : DEVDRV_USBH_DETACH_ERR : device detach
|
||||
* : DEVDRV_SUCCESS : device enumeration success
|
||||
* : DEVDRV_ERROR : device enumeration error
|
||||
*******************************************************************************/
|
||||
int32_t usb1_api_host_enumeration (uint16_t devadr)
|
||||
{
|
||||
int32_t ret;
|
||||
uint16_t driver_sts;
|
||||
|
||||
g_usb1_host_setUsbAddress = devadr;
|
||||
|
||||
while (1)
|
||||
{
|
||||
driver_sts = usb1_api_host_GetUsbDeviceState();
|
||||
|
||||
if (driver_sts == USB_HOST_DRV_DETACHED)
|
||||
{
|
||||
ret = DEVDRV_USBH_DETACH_ERR;
|
||||
break;
|
||||
}
|
||||
else if (driver_sts == USB_HOST_DRV_CONFIGURED)
|
||||
{
|
||||
ret = DEVDRV_SUCCESS;
|
||||
break;
|
||||
}
|
||||
else if (driver_sts == USB_HOST_DRV_STALL)
|
||||
{
|
||||
ret = DEVDRV_ERROR;
|
||||
break;
|
||||
}
|
||||
else if (driver_sts == USB_HOST_DRV_NORES)
|
||||
{
|
||||
ret = DEVDRV_ERROR;
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do Nothing */
|
||||
}
|
||||
}
|
||||
|
||||
if (driver_sts == USB_HOST_DRV_NORES)
|
||||
{
|
||||
while (1)
|
||||
{
|
||||
driver_sts = usb1_api_host_GetUsbDeviceState();
|
||||
|
||||
if (driver_sts == USB_HOST_DRV_DETACHED)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_host_detach
|
||||
* Description : USB detach routine
|
||||
* Arguments : none
|
||||
* Return Value : USB_HOST_DETACH : USB detach
|
||||
* : USB_HOST_ATTACH : USB attach
|
||||
* : DEVDRV_ERROR : error
|
||||
*******************************************************************************/
|
||||
int32_t usb1_api_host_detach (void)
|
||||
{
|
||||
int32_t ret;
|
||||
uint16_t driver_sts;
|
||||
|
||||
while (1)
|
||||
{
|
||||
driver_sts = usb1_api_host_GetUsbDeviceState();
|
||||
|
||||
if (driver_sts == USB_HOST_DRV_DETACHED)
|
||||
{
|
||||
ret = USB_HOST_DETACH;
|
||||
break;
|
||||
}
|
||||
else if (driver_sts == USB_HOST_DRV_CONFIGURED)
|
||||
{
|
||||
ret = USB_HOST_ATTACH;
|
||||
break;
|
||||
}
|
||||
else if (driver_sts == USB_HOST_DRV_STALL)
|
||||
{
|
||||
ret = DEVDRV_ERROR;
|
||||
break;
|
||||
}
|
||||
else if (driver_sts == USB_HOST_DRV_NORES)
|
||||
{
|
||||
ret = DEVDRV_ERROR;
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do Nothing */
|
||||
}
|
||||
}
|
||||
|
||||
if (driver_sts == USB_HOST_DRV_NORES)
|
||||
{
|
||||
while (1)
|
||||
{
|
||||
driver_sts = usb1_api_host_GetUsbDeviceState();
|
||||
|
||||
if (driver_sts == USB_HOST_DRV_DETACHED)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_host_data_in
|
||||
* Description : Executes USB transfer as data-in in the argument specified pipe.
|
||||
* Arguments : uint16_t devadr ; device address
|
||||
* : uint16_t Pipe ; Pipe Number
|
||||
* : uint32_t Size ; Data Size
|
||||
* : uint8_t *data_buf ; Data data_buf Address
|
||||
* Return Value : DEVDRV_SUCCESS ; success
|
||||
* : DEVDRV_ERROR ; error
|
||||
*******************************************************************************/
|
||||
int32_t usb1_api_host_data_in (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
|
||||
{
|
||||
int32_t ret;
|
||||
|
||||
if (Pipe == USB_HOST_PIPE0)
|
||||
{
|
||||
return DEVDRV_ERROR;
|
||||
}
|
||||
|
||||
if (RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
|
||||
{
|
||||
return DEVDRV_ERROR;
|
||||
}
|
||||
|
||||
if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 1)
|
||||
{
|
||||
return DEVDRV_ERROR;
|
||||
}
|
||||
|
||||
if (g_usb1_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
|
||||
{
|
||||
usb1_host_start_receive_transfer(Pipe, Size, data_buf);
|
||||
}
|
||||
else
|
||||
{
|
||||
return DEVDRV_ERROR; /* Now pipe is busy */
|
||||
}
|
||||
|
||||
/* waiting for completing routine */
|
||||
do
|
||||
{
|
||||
if (g_usb1_host_detach_flag == USB_HOST_YES)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
if ((g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
} while (1);
|
||||
|
||||
if (g_usb1_host_detach_flag == USB_HOST_YES)
|
||||
{
|
||||
return DEVDRV_USBH_DETACH_ERR;
|
||||
}
|
||||
|
||||
switch (g_usb1_host_pipe_status[Pipe])
|
||||
{
|
||||
case USB_HOST_PIPE_DONE:
|
||||
ret = DEVDRV_SUCCESS;
|
||||
break;
|
||||
|
||||
case USB_HOST_PIPE_STALL:
|
||||
ret = DEVDRV_USBH_STALL;
|
||||
break;
|
||||
|
||||
case USB_HOST_PIPE_NORES:
|
||||
ret = DEVDRV_USBH_COM_ERR;
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = DEVDRV_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
usb1_host_stop_transfer(Pipe);
|
||||
|
||||
g_usb1_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_host_data_out
|
||||
* Description : Executes USB transfer as data-out in the argument specified pipe.
|
||||
* Arguments : uint16_t devadr ; device address
|
||||
* : uint16_t Pipe ; Pipe Number
|
||||
* : uint32_t Size ; Data Size
|
||||
* : uint8_t *data_buf ; Data data_buf Address
|
||||
* Return Value : DEVDRV_SUCCESS ; success
|
||||
* : DEVDRV_ERROR ; error
|
||||
*******************************************************************************/
|
||||
int32_t usb1_api_host_data_out (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
|
||||
{
|
||||
int32_t ret;
|
||||
|
||||
if (Pipe == USB_HOST_PIPE0)
|
||||
{
|
||||
return DEVDRV_ERROR;
|
||||
}
|
||||
|
||||
if (RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
|
||||
{
|
||||
return DEVDRV_ERROR;
|
||||
}
|
||||
|
||||
if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
|
||||
{
|
||||
return DEVDRV_ERROR;
|
||||
}
|
||||
|
||||
if (g_usb1_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
|
||||
{
|
||||
usb1_host_start_send_transfer(Pipe, Size, data_buf);
|
||||
}
|
||||
else
|
||||
{
|
||||
return DEVDRV_ERROR; /* Now pipe is busy */
|
||||
}
|
||||
|
||||
/* waiting for completing routine */
|
||||
do
|
||||
{
|
||||
if (g_usb1_host_detach_flag == USB_HOST_YES)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
if ((g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
} while (1);
|
||||
|
||||
if (g_usb1_host_detach_flag == USB_HOST_YES)
|
||||
{
|
||||
return DEVDRV_USBH_DETACH_ERR;
|
||||
}
|
||||
|
||||
switch (g_usb1_host_pipe_status[Pipe])
|
||||
{
|
||||
case USB_HOST_PIPE_DONE:
|
||||
ret = DEVDRV_SUCCESS;
|
||||
break;
|
||||
|
||||
case USB_HOST_PIPE_STALL:
|
||||
ret = DEVDRV_USBH_STALL;
|
||||
break;
|
||||
|
||||
case USB_HOST_PIPE_NORES:
|
||||
ret = DEVDRV_USBH_COM_ERR;
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = DEVDRV_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
usb1_host_stop_transfer(Pipe);
|
||||
|
||||
g_usb1_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_host_control_transfer
|
||||
* Description : Executes USB control transfer.
|
||||
* Arguments : uint16_t devadr ; device address
|
||||
* : uint16_t Req ; bmRequestType & bRequest
|
||||
* : uint16_t Val ; wValue
|
||||
* : uint16_t Indx ; wIndex
|
||||
* : uint16_t Len ; wLength
|
||||
* : uint8_t *buf ; Buffer
|
||||
* Return Value : DEVDRV_SUCCESS ; success
|
||||
* : DEVDRV_USBH_DETACH_ERR ; device detach
|
||||
* : DEVDRV_USBH_CTRL_COM_ERR ; device no response
|
||||
* : DEVDRV_USBH_STALL ; STALL
|
||||
* : DEVDRV_ERROR ; error
|
||||
*******************************************************************************/
|
||||
int32_t usb1_api_host_control_transfer (uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx,
|
||||
uint16_t Len, uint8_t * Buf)
|
||||
{
|
||||
int32_t ret;
|
||||
|
||||
do
|
||||
{
|
||||
ret = usb1_host_CtrlTransStart(devadr, Req, Val, Indx, Len, Buf);
|
||||
|
||||
if (ret == DEVDRV_SUCCESS)
|
||||
{
|
||||
if (g_usb1_host_detach_flag == USB_HOST_YES)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
if ((g_usb1_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_IDLE)
|
||||
&& (g_usb1_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT))
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
return DEVDRV_ERROR;
|
||||
}
|
||||
} while (1);
|
||||
|
||||
if (g_usb1_host_detach_flag == USB_HOST_YES)
|
||||
{
|
||||
return DEVDRV_USBH_DETACH_ERR;
|
||||
}
|
||||
|
||||
switch (g_usb1_host_pipe_status[USB_HOST_PIPE0])
|
||||
{
|
||||
case USB_HOST_PIPE_DONE:
|
||||
ret = DEVDRV_SUCCESS;
|
||||
break;
|
||||
|
||||
case USB_HOST_PIPE_STALL:
|
||||
ret = DEVDRV_USBH_STALL;
|
||||
break;
|
||||
|
||||
case USB_HOST_PIPE_NORES:
|
||||
ret = DEVDRV_USBH_CTRL_COM_ERR;
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = DEVDRV_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_host_set_endpoint
|
||||
* Description : Sets end point on the information specified in the argument.
|
||||
* Arguments : uint16_t devadr ; device address
|
||||
* : uint8_t *configdescriptor ; device configration descriptor
|
||||
* : USB_HOST_CFG_PIPETBL_t *user_table ; pipe table
|
||||
* Return Value : DEVDRV_SUCCESS ; success
|
||||
* : DEVDRV_ERROR ; error
|
||||
*******************************************************************************/
|
||||
int32_t usb1_api_host_set_endpoint (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * configdescriptor)
|
||||
{
|
||||
uint16_t ret;
|
||||
uint32_t end_point;
|
||||
uint32_t offset;
|
||||
uint32_t totalLength;
|
||||
USB_HOST_CFG_PIPETBL_t * pipe_table;
|
||||
|
||||
/* End Point Search */
|
||||
end_point = 0;
|
||||
offset = configdescriptor[0];
|
||||
totalLength = (uint16_t)(configdescriptor[2] + ((uint16_t)configdescriptor[3] << 8));
|
||||
|
||||
do
|
||||
{
|
||||
if (configdescriptor[offset + 1] == USB_HOST_ENDPOINT_DESC)
|
||||
{
|
||||
pipe_table = &user_table[end_point];
|
||||
|
||||
if (pipe_table->pipe_number == 0xffff)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
ret = usb1_api_host_SetEndpointTable(devadr, pipe_table, (uint8_t *)&configdescriptor[offset]);
|
||||
|
||||
if ((ret != USB_HOST_PIPE_IN) && (ret != USB_HOST_PIPE_OUT))
|
||||
{
|
||||
return DEVDRV_ERROR;
|
||||
}
|
||||
|
||||
++end_point;
|
||||
}
|
||||
|
||||
/* Next End Point Search */
|
||||
offset += configdescriptor[offset];
|
||||
|
||||
} while (offset < totalLength);
|
||||
|
||||
return DEVDRV_SUCCESS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_host_clear_endpoint
|
||||
* Description : Clears the pipe definition table specified in the argument.
|
||||
* Arguments : uint16_t pipe_sel : Pipe Number
|
||||
* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
|
||||
* Return Value : DEVDRV_SUCCESS ; success
|
||||
* : DEVDRV_ERROR ; error
|
||||
*******************************************************************************/
|
||||
int32_t usb1_api_host_clear_endpoint (USB_HOST_CFG_PIPETBL_t * user_table)
|
||||
{
|
||||
uint16_t pipe;
|
||||
|
||||
for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
|
||||
{
|
||||
if (user_table->pipe_number == 0xffff)
|
||||
{
|
||||
break;
|
||||
}
|
||||
user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
|
||||
user_table->pipe_max_pktsize = 0;
|
||||
user_table->pipe_cycle = 0;
|
||||
|
||||
user_table++;
|
||||
}
|
||||
|
||||
return DEVDRV_SUCCESS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_host_clear_endpoint_pipe
|
||||
* Description : Clears the pipe definition table specified in the argument.
|
||||
* Arguments : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
|
||||
* Return Value : DEVDRV_SUCCESS ; success
|
||||
* : DEVDRV_ERROR ; error
|
||||
*******************************************************************************/
|
||||
int32_t usb1_api_host_clear_endpoint_pipe (uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t * user_table)
|
||||
{
|
||||
uint16_t pipe;
|
||||
|
||||
for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
|
||||
{
|
||||
if (user_table->pipe_number == 0xffff)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
if (user_table->pipe_number == pipe_sel)
|
||||
{
|
||||
user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
|
||||
user_table->pipe_max_pktsize = 0;
|
||||
user_table->pipe_cycle = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
user_table++;
|
||||
}
|
||||
|
||||
return DEVDRV_SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_host_SetEndpointTable
|
||||
* Description : Sets the end point on the information specified by the argument.
|
||||
* Arguments : uint16_t devadr : device address
|
||||
* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
|
||||
* : uint8_t *Table : Endpoint descriptor
|
||||
* Return Value : USB_HOST_DIR_H_IN ; IN endpoint
|
||||
* : USB_HOST_DIR_H_OUT ; OUT endpoint
|
||||
* : USB_END_POINT_ERROR ; error
|
||||
*******************************************************************************/
|
||||
uint16_t usb1_api_host_SetEndpointTable (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * Table)
|
||||
{
|
||||
uint16_t PipeCfg;
|
||||
uint16_t PipeMaxp;
|
||||
uint16_t pipe_number;
|
||||
uint16_t ret;
|
||||
uint16_t ret_flag = 0; // avoid warning.
|
||||
|
||||
pipe_number = user_table->pipe_number;
|
||||
|
||||
if (Table[1] != USB_HOST_ENDPOINT_DESC)
|
||||
{
|
||||
return USB_END_POINT_ERROR;
|
||||
}
|
||||
|
||||
switch (Table[3] & USB_HOST_EP_TYPE)
|
||||
{
|
||||
case USB_HOST_EP_CNTRL:
|
||||
ret_flag = USB_END_POINT_ERROR;
|
||||
break;
|
||||
|
||||
case USB_HOST_EP_ISO:
|
||||
if ((pipe_number != USB_HOST_PIPE1) && (pipe_number != USB_HOST_PIPE2))
|
||||
{
|
||||
return USB_END_POINT_ERROR;
|
||||
}
|
||||
|
||||
PipeCfg = USB_HOST_ISO;
|
||||
break;
|
||||
|
||||
case USB_HOST_EP_BULK:
|
||||
if ((pipe_number < USB_HOST_PIPE1) || (pipe_number > USB_HOST_PIPE5))
|
||||
{
|
||||
return USB_END_POINT_ERROR;
|
||||
}
|
||||
|
||||
PipeCfg = USB_HOST_BULK;
|
||||
break;
|
||||
|
||||
case USB_HOST_EP_INT:
|
||||
if ((pipe_number < USB_HOST_PIPE6) || (pipe_number > USB_HOST_PIPE9))
|
||||
{
|
||||
return USB_END_POINT_ERROR;
|
||||
}
|
||||
|
||||
PipeCfg = USB_HOST_INTERRUPT;
|
||||
break;
|
||||
|
||||
default:
|
||||
ret_flag = USB_END_POINT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret_flag == USB_END_POINT_ERROR)
|
||||
{
|
||||
return ret_flag;
|
||||
}
|
||||
|
||||
/* Set pipe configuration table */
|
||||
if ((Table[2] & USB_HOST_EP_DIR_MASK) == USB_HOST_EP_IN) /* IN(receive) */
|
||||
{
|
||||
if (PipeCfg == USB_HOST_ISO)
|
||||
{
|
||||
/* Transfer Type is ISO*/
|
||||
PipeCfg |= USB_HOST_DIR_H_IN;
|
||||
|
||||
switch (user_table->fifo_port)
|
||||
{
|
||||
case USB_HOST_CUSE:
|
||||
case USB_HOST_D0USE:
|
||||
case USB_HOST_D1USE:
|
||||
case USB_HOST_D0DMA:
|
||||
case USB_HOST_D1DMA:
|
||||
PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
|
||||
break;
|
||||
|
||||
default:
|
||||
ret_flag = USB_END_POINT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret_flag == USB_END_POINT_ERROR)
|
||||
{
|
||||
return ret_flag;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Transfer Type is BULK or INT */
|
||||
PipeCfg |= (USB_HOST_SHTNAKON | USB_HOST_DIR_H_IN); /* Compulsory SHTNAK */
|
||||
|
||||
switch (user_table->fifo_port)
|
||||
{
|
||||
case USB_HOST_CUSE:
|
||||
case USB_HOST_D0USE:
|
||||
case USB_HOST_D1USE:
|
||||
PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
|
||||
break;
|
||||
|
||||
case USB_HOST_D0DMA:
|
||||
case USB_HOST_D1DMA:
|
||||
PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
|
||||
#ifdef __USB_DMA_BFRE_ENABLE__
|
||||
/* this routine cannnot be perfomred if read operation is executed in buffer size */
|
||||
PipeCfg |= USB_HOST_BFREON;
|
||||
#endif
|
||||
break;
|
||||
|
||||
default:
|
||||
ret_flag = USB_END_POINT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret_flag == USB_END_POINT_ERROR)
|
||||
{
|
||||
return ret_flag;
|
||||
}
|
||||
}
|
||||
ret = USB_HOST_PIPE_IN;
|
||||
}
|
||||
else /* OUT(send) */
|
||||
{
|
||||
if (PipeCfg == USB_HOST_ISO)
|
||||
{
|
||||
/* Transfer Type is ISO*/
|
||||
PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Transfer Type is BULK or INT */
|
||||
PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
|
||||
}
|
||||
PipeCfg |= USB_HOST_DIR_H_OUT;
|
||||
ret = USB_HOST_PIPE_OUT;
|
||||
}
|
||||
|
||||
switch (user_table->fifo_port)
|
||||
{
|
||||
case USB_HOST_CUSE:
|
||||
g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_CFIFO_USE;
|
||||
break;
|
||||
|
||||
case USB_HOST_D0USE:
|
||||
g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_USE;
|
||||
break;
|
||||
|
||||
case USB_HOST_D1USE:
|
||||
g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_USE;
|
||||
break;
|
||||
|
||||
case USB_HOST_D0DMA:
|
||||
g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_DMA;
|
||||
break;
|
||||
|
||||
case USB_HOST_D1DMA:
|
||||
g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_DMA;
|
||||
break;
|
||||
|
||||
default:
|
||||
ret_flag = USB_END_POINT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret_flag == USB_END_POINT_ERROR)
|
||||
{
|
||||
return ret_flag;
|
||||
}
|
||||
|
||||
/* Endpoint number set */
|
||||
PipeCfg |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
|
||||
g_usb1_host_PipeTbl[pipe_number] |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
|
||||
|
||||
/* Max packet size set */
|
||||
PipeMaxp = (uint16_t)((uint16_t)Table[4] | (uint16_t)((uint16_t)Table[5] << 8));
|
||||
|
||||
if (PipeMaxp == 0u)
|
||||
{
|
||||
return USB_END_POINT_ERROR;
|
||||
}
|
||||
|
||||
/* Set device address */
|
||||
PipeMaxp |= (uint16_t)(devadr << 12);
|
||||
|
||||
user_table->pipe_cfg = PipeCfg;
|
||||
user_table->pipe_max_pktsize = PipeMaxp;
|
||||
|
||||
usb1_host_resetEP(user_table);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_resetEP
|
||||
* Description : Sets the end point on the information specified by the argument.
|
||||
* Arguments : USB_HOST_CFG_PIPETBL_t *tbl : pipe table
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
static void usb1_host_resetEP (USB_HOST_CFG_PIPETBL_t * tbl)
|
||||
{
|
||||
|
||||
uint16_t pipe;
|
||||
|
||||
/* Host pipe */
|
||||
/* The pipe number of pipe definition table is obtained */
|
||||
pipe = (uint16_t)(tbl->pipe_number & USB_HOST_BITCURPIPE); /* Pipe Number */
|
||||
|
||||
/* FIFO port access pipe is set to initial value */
|
||||
/* The connection with FIFO should be cut before setting the pipe */
|
||||
if (RZA_IO_RegRead_16(&USB201.CFIFOSEL,
|
||||
USB_CFIFOSEL_CURPIPE_SHIFT,
|
||||
USB_CFIFOSEL_CURPIPE) == pipe)
|
||||
{
|
||||
usb1_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, USB_HOST_BITMBW_16);
|
||||
}
|
||||
|
||||
if (RZA_IO_RegRead_16(&USB201.D0FIFOSEL,
|
||||
USB_DnFIFOSEL_CURPIPE_SHIFT,
|
||||
USB_DnFIFOSEL_CURPIPE) == pipe)
|
||||
{
|
||||
usb1_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, USB_HOST_BITMBW_16);
|
||||
}
|
||||
|
||||
if (RZA_IO_RegRead_16(&USB201.D1FIFOSEL,
|
||||
USB_DnFIFOSEL_CURPIPE_SHIFT,
|
||||
USB_DnFIFOSEL_CURPIPE) == pipe)
|
||||
{
|
||||
usb1_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, USB_HOST_BITMBW_16);
|
||||
}
|
||||
|
||||
/* Interrupt of pipe set is disabled */
|
||||
usb1_host_disable_brdy_int(pipe);
|
||||
usb1_host_disable_nrdy_int(pipe);
|
||||
usb1_host_disable_bemp_int(pipe);
|
||||
|
||||
/* Pipe to set is set to NAK */
|
||||
usb1_host_set_pid_nak(pipe);
|
||||
|
||||
/* Pipe is set */
|
||||
USB201.PIPESEL = pipe;
|
||||
|
||||
USB201.PIPECFG = tbl->pipe_cfg;
|
||||
USB201.PIPEBUF = tbl->pipe_buf;
|
||||
USB201.PIPEMAXP = tbl->pipe_max_pktsize;
|
||||
USB201.PIPEPERI = tbl->pipe_cycle;
|
||||
|
||||
g_usb1_host_pipecfg[pipe] = tbl->pipe_cfg;
|
||||
g_usb1_host_pipebuf[pipe] = tbl->pipe_buf;
|
||||
g_usb1_host_pipemaxp[pipe] = tbl->pipe_max_pktsize;
|
||||
g_usb1_host_pipeperi[pipe] = tbl->pipe_cycle;
|
||||
|
||||
/* Sequence bit clear */
|
||||
usb1_host_set_sqclr(pipe);
|
||||
|
||||
usb1_host_aclrm(pipe);
|
||||
usb1_host_set_csclr(pipe);
|
||||
|
||||
/* Pipe window selection is set to unused */
|
||||
USB201.PIPESEL = USB_HOST_PIPE0;
|
||||
|
||||
}
|
||||
|
||||
#if(1) /* ohci_wrapp */
|
||||
#else
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_api_host_data_count
|
||||
* Description : Get g_usb0_host_data_count[pipe]
|
||||
* Arguments : uint16_t pipe ; Pipe Number
|
||||
* : uint32_t *data_count ; return g_usb0_data_count[pipe]
|
||||
* Return Value : DEVDRV_SUCCESS ; success
|
||||
* : DEVDRV_ERROR ; error
|
||||
*******************************************************************************/
|
||||
int32_t usb1_api_host_data_count (uint16_t pipe, uint32_t * data_count)
|
||||
{
|
||||
if (pipe > USB_HOST_MAX_PIPE_NO)
|
||||
{
|
||||
return DEVDRV_ERROR;
|
||||
}
|
||||
|
||||
*data_count = g_usb1_host_PipeDataSize[pipe];
|
||||
|
||||
return DEVDRV_SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,137 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_host_global.c
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Device(s) : RZ/A1H
|
||||
* Tool-Chain :
|
||||
* OS : None
|
||||
* H/W Platform :
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
* Operation :
|
||||
* Limitations :
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include "usb1_host.h"
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
const uint16_t g_usb1_host_bit_set[16] =
|
||||
{
|
||||
0x0001, 0x0002, 0x0004, 0x0008,
|
||||
0x0010, 0x0020, 0x0040, 0x0080,
|
||||
0x0100, 0x0200, 0x0400, 0x0800,
|
||||
0x1000, 0x2000, 0x4000, 0x8000
|
||||
};
|
||||
|
||||
uint32_t g_usb1_host_data_count[USB_HOST_MAX_PIPE_NO + 1];
|
||||
uint8_t * g_usb1_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1];
|
||||
|
||||
uint16_t g_usb1_host_PipeIgnore[USB_HOST_MAX_PIPE_NO + 1];
|
||||
uint16_t g_usb1_host_PipeTbl[USB_HOST_MAX_PIPE_NO + 1];
|
||||
uint16_t g_usb1_host_pipe_status[USB_HOST_MAX_PIPE_NO + 1];
|
||||
uint32_t g_usb1_host_PipeDataSize[USB_HOST_MAX_PIPE_NO + 1];
|
||||
|
||||
USB_HOST_DMA_t g_usb1_host_DmaInfo[2];
|
||||
|
||||
uint16_t g_usb1_host_DmaPipe[2];
|
||||
uint16_t g_usb1_host_DmaBval[2];
|
||||
uint16_t g_usb1_host_DmaStatus[2];
|
||||
|
||||
uint16_t g_usb1_host_driver_state;
|
||||
uint16_t g_usb1_host_ConfigNum;
|
||||
uint16_t g_usb1_host_CmdStage;
|
||||
uint16_t g_usb1_host_bchg_flag;
|
||||
uint16_t g_usb1_host_detach_flag;
|
||||
uint16_t g_usb1_host_attach_flag;
|
||||
|
||||
uint16_t g_usb1_host_UsbAddress;
|
||||
uint16_t g_usb1_host_setUsbAddress;
|
||||
uint16_t g_usb1_host_default_max_packet[USB_HOST_MAX_DEVICE + 1];
|
||||
uint16_t g_usb1_host_UsbDeviceSpeed;
|
||||
uint16_t g_usb1_host_SupportUsbDeviceSpeed;
|
||||
|
||||
uint16_t g_usb1_host_SavReq;
|
||||
uint16_t g_usb1_host_SavVal;
|
||||
uint16_t g_usb1_host_SavIndx;
|
||||
uint16_t g_usb1_host_SavLen;
|
||||
|
||||
uint16_t g_usb1_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1];
|
||||
uint16_t g_usb1_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1];
|
||||
uint16_t g_usb1_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1];
|
||||
uint16_t g_usb1_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1];
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private global variables and functions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_init_pipe_status
|
||||
* Description : Initialize pipe status.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_init_pipe_status (void)
|
||||
{
|
||||
uint16_t loop;
|
||||
|
||||
g_usb1_host_ConfigNum = 0;
|
||||
|
||||
for (loop = 0; loop < (USB_HOST_MAX_PIPE_NO + 1); ++loop)
|
||||
{
|
||||
g_usb1_host_pipe_status[loop] = USB_HOST_PIPE_IDLE;
|
||||
g_usb1_host_PipeDataSize[loop] = 0;
|
||||
|
||||
/* pipe configuration in usb1_host_resetEP() */
|
||||
g_usb1_host_pipecfg[loop] = 0;
|
||||
g_usb1_host_pipebuf[loop] = 0;
|
||||
g_usb1_host_pipemaxp[loop] = 0;
|
||||
g_usb1_host_pipeperi[loop] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,497 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_host_usbint.c
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Device(s) : RZ/A1H
|
||||
* Tool-Chain :
|
||||
* OS : None
|
||||
* H/W Platform :
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
* Operation :
|
||||
* Limitations :
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include "usb1_host.h"
|
||||
#if(1) /* ohci_wrapp */
|
||||
#include "ohci_wrapp_RZ_A1_local.h"
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
static void usb1_host_interrupt1(void);
|
||||
static void usb1_host_BRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
|
||||
static void usb1_host_NRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
|
||||
static void usb1_host_BEMPInterrupt(uint16_t Status, uint16_t Int_enbl);
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private global variables and functions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_interrupt
|
||||
* Description : Executes USB interrupt.
|
||||
* : Register this function in the USB interrupt handler.
|
||||
* : Set CFIF0 in the pipe set before the interrupt after executing
|
||||
* : this function.
|
||||
* Arguments : uint32_t int_sense ; Interrupts detection mode
|
||||
* : ; INTC_LEVEL_SENSITIVE : Level sense
|
||||
* : ; INTC_EDGE_TRIGGER : Edge trigger
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_interrupt (uint32_t int_sense)
|
||||
{
|
||||
uint16_t savepipe1;
|
||||
uint16_t savepipe2;
|
||||
uint16_t buffer;
|
||||
|
||||
savepipe1 = USB201.CFIFOSEL;
|
||||
savepipe2 = USB201.PIPESEL;
|
||||
usb1_host_interrupt1();
|
||||
|
||||
/* Control transmission changes ISEL within interruption processing. */
|
||||
/* For this reason, write return of ISEL cannot be performed. */
|
||||
buffer = USB201.CFIFOSEL;
|
||||
buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
|
||||
buffer |= (uint16_t)(savepipe1 & USB_HOST_BITCURPIPE);
|
||||
USB201.CFIFOSEL = buffer;
|
||||
USB201.PIPESEL = savepipe2;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_interrupt1
|
||||
* Description : Execue the USB interrupt.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_interrupt1 (void)
|
||||
{
|
||||
uint16_t intsts0;
|
||||
uint16_t intsts1;
|
||||
uint16_t intenb0;
|
||||
uint16_t intenb1;
|
||||
uint16_t brdysts;
|
||||
uint16_t nrdysts;
|
||||
uint16_t bempsts;
|
||||
uint16_t brdyenb;
|
||||
uint16_t nrdyenb;
|
||||
uint16_t bempenb;
|
||||
volatile uint16_t dumy_sts;
|
||||
|
||||
intsts0 = USB201.INTSTS0;
|
||||
intsts1 = USB201.INTSTS1;
|
||||
intenb0 = USB201.INTENB0;
|
||||
intenb1 = USB201.INTENB1;
|
||||
|
||||
if ((intsts1 & USB_HOST_BITBCHG) && (intenb1 & USB_HOST_BITBCHGE))
|
||||
{
|
||||
USB201.INTSTS1 = (uint16_t)~USB_HOST_BITBCHG;
|
||||
RZA_IO_RegWrite_16(&USB201.INTENB1,
|
||||
0,
|
||||
USB_INTENB1_BCHGE_SHIFT,
|
||||
USB_INTENB1_BCHGE);
|
||||
g_usb1_host_bchg_flag = USB_HOST_YES;
|
||||
}
|
||||
else if ((intsts1 & USB_HOST_BITSACK) && (intenb1 & USB_HOST_BITSACKE))
|
||||
{
|
||||
USB201.INTSTS1 = (uint16_t)~USB_HOST_BITSACK;
|
||||
#if(1) /* ohci_wrapp */
|
||||
ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
|
||||
#else
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
|
||||
#endif
|
||||
}
|
||||
else if ((intsts1 & USB_HOST_BITSIGN) && (intenb1 & USB_HOST_BITSIGNE))
|
||||
{
|
||||
USB201.INTSTS1 = (uint16_t)~USB_HOST_BITSIGN;
|
||||
#if(1) /* ohci_wrapp */
|
||||
g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
|
||||
ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
|
||||
#else
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_NORES;
|
||||
#endif
|
||||
}
|
||||
else if (((intsts1 & USB_HOST_BITDTCH) == USB_HOST_BITDTCH)
|
||||
&& ((intenb1 & USB_HOST_BITDTCHE) == USB_HOST_BITDTCHE))
|
||||
{
|
||||
USB201.INTSTS1 = (uint16_t)~USB_HOST_BITDTCH;
|
||||
RZA_IO_RegWrite_16(&USB201.INTENB1,
|
||||
0,
|
||||
USB_INTENB1_DTCHE_SHIFT,
|
||||
USB_INTENB1_DTCHE);
|
||||
g_usb1_host_detach_flag = USB_HOST_YES;
|
||||
|
||||
Userdef_USB_usb1_host_detach();
|
||||
|
||||
usb1_host_UsbDetach2();
|
||||
}
|
||||
else if (((intsts1 & USB_HOST_BITATTCH) == USB_HOST_BITATTCH)
|
||||
&& ((intenb1 & USB_HOST_BITATTCHE) == USB_HOST_BITATTCHE))
|
||||
{
|
||||
USB201.INTSTS1 = (uint16_t)~USB_HOST_BITATTCH;
|
||||
RZA_IO_RegWrite_16(&USB201.INTENB1,
|
||||
0,
|
||||
USB_INTENB1_ATTCHE_SHIFT,
|
||||
USB_INTENB1_ATTCHE);
|
||||
g_usb1_host_attach_flag = USB_HOST_YES;
|
||||
|
||||
Userdef_USB_usb1_host_attach();
|
||||
|
||||
usb1_host_UsbAttach();
|
||||
}
|
||||
else if ((intsts0 & intenb0 & (USB_HOST_BITBEMP | USB_HOST_BITNRDY | USB_HOST_BITBRDY)))
|
||||
{
|
||||
brdysts = USB201.BRDYSTS;
|
||||
nrdysts = USB201.NRDYSTS;
|
||||
bempsts = USB201.BEMPSTS;
|
||||
brdyenb = USB201.BRDYENB;
|
||||
nrdyenb = USB201.NRDYENB;
|
||||
bempenb = USB201.BEMPENB;
|
||||
|
||||
if ((intsts0 & USB_HOST_BITBRDY) && (intenb0 & USB_HOST_BITBRDYE) && (brdysts & brdyenb))
|
||||
{
|
||||
usb1_host_BRDYInterrupt(brdysts, brdyenb);
|
||||
}
|
||||
else if ((intsts0 & USB_HOST_BITBEMP) && (intenb0 & USB_HOST_BITBEMPE) && (bempsts & bempenb))
|
||||
{
|
||||
usb1_host_BEMPInterrupt(bempsts, bempenb);
|
||||
}
|
||||
else if ((intsts0 & USB_HOST_BITNRDY) && (intenb0 & USB_HOST_BITNRDYE) && (nrdysts & nrdyenb))
|
||||
{
|
||||
usb1_host_NRDYInterrupt(nrdysts, nrdyenb);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do Nothing */
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do Nothing */
|
||||
}
|
||||
|
||||
/* Three dummy read for clearing interrupt requests */
|
||||
dumy_sts = USB201.INTSTS0;
|
||||
dumy_sts = USB201.INTSTS1;
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_BRDYInterrupt
|
||||
* Description : Executes USB BRDY interrupt.
|
||||
* Arguments : uint16_t Status ; BRDYSTS Register Value
|
||||
* : uint16_t Int_enbl ; BRDYENB Register Value
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_BRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
|
||||
{
|
||||
uint16_t buffer;
|
||||
volatile uint16_t dumy_sts;
|
||||
|
||||
if ((Status & g_usb1_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb1_host_bit_set[USB_HOST_PIPE0]))
|
||||
{
|
||||
USB201.BRDYSTS = (uint16_t)~g_usb1_host_bit_set[USB_HOST_PIPE0];
|
||||
|
||||
#if(1) /* ohci_wrapp */
|
||||
switch ((g_usb1_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
|
||||
{
|
||||
case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
|
||||
buffer = usb1_host_read_buffer_c(USB_HOST_PIPE0);
|
||||
usb1_host_disable_brdy_int(USB_HOST_PIPE0);
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
|
||||
ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
|
||||
break;
|
||||
|
||||
case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
|
||||
buffer = usb1_host_read_buffer_c(USB_HOST_PIPE0);
|
||||
switch (buffer)
|
||||
{
|
||||
case USB_HOST_READING: /* Continue of data read */
|
||||
break;
|
||||
|
||||
case USB_HOST_READEND: /* End of data read */
|
||||
case USB_HOST_READSHRT: /* End of data read */
|
||||
usb1_host_disable_brdy_int(USB_HOST_PIPE0);
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
|
||||
ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
|
||||
break;
|
||||
|
||||
case USB_HOST_READOVER: /* buffer over */
|
||||
USB201.CFIFOCTR = USB_HOST_BITBCLR;
|
||||
usb1_host_disable_brdy_int(USB_HOST_PIPE0);
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
|
||||
ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
|
||||
break;
|
||||
|
||||
case USB_HOST_FIFOERROR: /* FIFO access error */
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
#else
|
||||
switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
|
||||
{
|
||||
case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
|
||||
case (USB_HOST_MODE_NO_DATA | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
|
||||
buffer = usb1_host_read_buffer_c(USB_HOST_PIPE0);
|
||||
usb1_host_disable_brdy_int(USB_HOST_PIPE0);
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
|
||||
break;
|
||||
|
||||
case (USB_HOST_MODE_READ | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
|
||||
buffer = usb1_host_read_buffer_c(USB_HOST_PIPE0);
|
||||
|
||||
switch (buffer)
|
||||
{
|
||||
case USB_HOST_READING: /* Continue of data read */
|
||||
break;
|
||||
|
||||
case USB_HOST_READEND: /* End of data read */
|
||||
case USB_HOST_READSHRT: /* End of data read */
|
||||
usb1_host_disable_brdy_int(USB_HOST_PIPE0);
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
|
||||
break;
|
||||
|
||||
case USB_HOST_READOVER: /* buffer over */
|
||||
USB201.CFIFOCTR = USB_HOST_BITBCLR;
|
||||
usb1_host_disable_brdy_int(USB_HOST_PIPE0);
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
|
||||
break;
|
||||
|
||||
case USB_HOST_FIFOERROR: /* FIFO access error */
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
usb1_host_brdy_int(Status, Int_enbl);
|
||||
}
|
||||
|
||||
/* Three dummy reads for clearing interrupt requests */
|
||||
dumy_sts = USB201.BRDYSTS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_NRDYInterrupt
|
||||
* Description : Executes USB NRDY interrupt.
|
||||
* Arguments : uint16_t Status ; NRDYSTS Register Value
|
||||
* : uint16_t Int_enbl ; NRDYENB Register Value
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_NRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
|
||||
{
|
||||
uint16_t pid;
|
||||
volatile uint16_t dumy_sts;
|
||||
|
||||
if ((Status & g_usb1_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb1_host_bit_set[USB_HOST_PIPE0]))
|
||||
{
|
||||
USB201.NRDYSTS = (uint16_t)~g_usb1_host_bit_set[USB_HOST_PIPE0];
|
||||
pid = usb1_host_get_pid(USB_HOST_PIPE0);
|
||||
|
||||
if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
|
||||
{
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_STALL;
|
||||
#if(1) /* ohci_wrapp */
|
||||
g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;
|
||||
ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
|
||||
#endif
|
||||
|
||||
}
|
||||
else if (pid == USB_HOST_PID_NAK)
|
||||
{
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_NORES;
|
||||
#if(1) /* ohci_wrapp */
|
||||
g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;
|
||||
ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do Nothing */
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
usb1_host_nrdy_int(Status, Int_enbl);
|
||||
}
|
||||
|
||||
/* Three dummy reads for clearing interrupt requests */
|
||||
dumy_sts = USB201.NRDYSTS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_BEMPInterrupt
|
||||
* Description : Executes USB BEMP interrupt.
|
||||
* Arguments : uint16_t Status ; BEMPSTS Register Value
|
||||
* : uint16_t Int_enbl ; BEMPENB Register Value
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_BEMPInterrupt (uint16_t Status, uint16_t Int_enbl)
|
||||
{
|
||||
uint16_t buffer;
|
||||
uint16_t pid;
|
||||
volatile uint16_t dumy_sts;
|
||||
|
||||
if ((Status & g_usb1_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb1_host_bit_set[USB_HOST_PIPE0]))
|
||||
{
|
||||
USB201.BEMPSTS = (uint16_t)~g_usb1_host_bit_set[USB_HOST_PIPE0];
|
||||
pid = usb1_host_get_pid(USB_HOST_PIPE0);
|
||||
|
||||
if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
|
||||
{
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_STALL;
|
||||
#if(1) /* ohci_wrapp */
|
||||
g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
|
||||
ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
#if(1) /* ohci_wrapp */
|
||||
switch ((g_usb1_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
|
||||
{
|
||||
case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
|
||||
ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
|
||||
break;
|
||||
|
||||
case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
|
||||
buffer = usb1_host_write_buffer(USB_HOST_PIPE0);
|
||||
switch (buffer)
|
||||
{
|
||||
case USB_HOST_WRITING: /* Continue of data write */
|
||||
case USB_HOST_WRITEEND: /* End of data write (zero-length) */
|
||||
break;
|
||||
|
||||
case USB_HOST_WRITESHRT: /* End of data write */
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
|
||||
ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
|
||||
break;
|
||||
|
||||
case USB_HOST_FIFOERROR: /* FIFO access error */
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
/* do nothing */
|
||||
break;
|
||||
}
|
||||
#else
|
||||
switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
|
||||
{
|
||||
case (USB_HOST_MODE_READ | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
|
||||
break;
|
||||
|
||||
case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
|
||||
buffer = usb1_host_write_buffer(USB_HOST_PIPE0);
|
||||
switch (buffer)
|
||||
{
|
||||
case USB_HOST_WRITING: /* Continue of data write */
|
||||
case USB_HOST_WRITEEND: /* End of data write (zero-length) */
|
||||
break;
|
||||
|
||||
case USB_HOST_WRITESHRT: /* End of data write */
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
|
||||
break;
|
||||
|
||||
case USB_HOST_FIFOERROR: /* FIFO access error */
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
|
||||
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
|
||||
g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
|
||||
break;
|
||||
|
||||
default:
|
||||
/* do nothing */
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
usb1_host_bemp_int(Status, Int_enbl);
|
||||
}
|
||||
|
||||
/* Three dummy reads for clearing interrupt requests */
|
||||
dumy_sts = USB201.BEMPSTS;
|
||||
}
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,637 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_host_usbsig.c
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Device(s) : RZ/A1H
|
||||
* Tool-Chain :
|
||||
* OS : None
|
||||
* H/W Platform :
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
* Operation :
|
||||
* Limitations :
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include "usb1_host.h"
|
||||
#include "dev_drv.h"
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
static void usb1_host_EnableINT_Module(void);
|
||||
static void usb1_host_Enable_AttachINT(void);
|
||||
static void usb1_host_Disable_AttachINT(void);
|
||||
static void usb1_host_Disable_BchgINT(void);
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private global variables and functions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_InitModule
|
||||
* Description : Initializes the USB module in USB host module.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_InitModule (void)
|
||||
{
|
||||
uint16_t buf1;
|
||||
uint16_t buf2;
|
||||
uint16_t buf3;
|
||||
|
||||
usb1_host_init_pipe_status();
|
||||
|
||||
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
|
||||
1,
|
||||
USB_SYSCFG_DCFM_SHIFT,
|
||||
USB_SYSCFG_DCFM); /* HOST mode */
|
||||
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
|
||||
1,
|
||||
USB_SYSCFG_DRPD_SHIFT,
|
||||
USB_SYSCFG_DRPD); /* PORT0 D+, D- setting */
|
||||
|
||||
do
|
||||
{
|
||||
buf1 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
|
||||
USB_SYSSTS0_LNST_SHIFT,
|
||||
USB_SYSSTS0_LNST);
|
||||
Userdef_USB_usb1_host_delay_xms(50);
|
||||
buf2 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
|
||||
USB_SYSSTS0_LNST_SHIFT,
|
||||
USB_SYSSTS0_LNST);
|
||||
Userdef_USB_usb1_host_delay_xms(50);
|
||||
buf3 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
|
||||
USB_SYSSTS0_LNST_SHIFT,
|
||||
USB_SYSSTS0_LNST);
|
||||
|
||||
} while ((buf1 != buf2) || (buf1 != buf3));
|
||||
|
||||
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
|
||||
1,
|
||||
USB_SYSCFG_USBE_SHIFT,
|
||||
USB_SYSCFG_USBE);
|
||||
|
||||
USB201.CFIFOSEL = (uint16_t)(USB_HOST_BITRCNT | USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
|
||||
USB201.D0FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
|
||||
USB201.D1FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_CheckAttach
|
||||
* Description : Returns the USB device connection state.
|
||||
* Arguments : none
|
||||
* Return Value : uint16_t ; USB_HOST_ATTACH : Attached
|
||||
* : ; USB_HOST_DETACH : not Attached
|
||||
*******************************************************************************/
|
||||
uint16_t usb1_host_CheckAttach (void)
|
||||
{
|
||||
uint16_t buf1;
|
||||
uint16_t buf2;
|
||||
uint16_t buf3;
|
||||
uint16_t rhst;
|
||||
|
||||
do
|
||||
{
|
||||
buf1 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
|
||||
USB_SYSSTS0_LNST_SHIFT,
|
||||
USB_SYSSTS0_LNST);
|
||||
Userdef_USB_usb1_host_delay_xms(50);
|
||||
buf2 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
|
||||
USB_SYSSTS0_LNST_SHIFT,
|
||||
USB_SYSSTS0_LNST);
|
||||
Userdef_USB_usb1_host_delay_xms(50);
|
||||
buf3 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
|
||||
USB_SYSSTS0_LNST_SHIFT,
|
||||
USB_SYSSTS0_LNST);
|
||||
|
||||
} while ((buf1 != buf2) || (buf1 != buf3));
|
||||
|
||||
rhst = RZA_IO_RegRead_16(&USB201.DVSTCTR0,
|
||||
USB_DVSTCTR0_RHST_SHIFT,
|
||||
USB_DVSTCTR0_RHST);
|
||||
if (rhst == USB_HOST_UNDECID)
|
||||
{
|
||||
if (buf1 == USB_HOST_FS_JSTS)
|
||||
{
|
||||
if (g_usb1_host_SupportUsbDeviceSpeed == USB_HOST_HIGH_SPEED)
|
||||
{
|
||||
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
|
||||
1,
|
||||
USB_SYSCFG_HSE_SHIFT,
|
||||
USB_SYSCFG_HSE);
|
||||
}
|
||||
else
|
||||
{
|
||||
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
|
||||
0,
|
||||
USB_SYSCFG_HSE_SHIFT,
|
||||
USB_SYSCFG_HSE);
|
||||
}
|
||||
return USB_HOST_ATTACH;
|
||||
}
|
||||
else if (buf1 == USB_HOST_LS_JSTS)
|
||||
{
|
||||
/* Low Speed Device */
|
||||
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
|
||||
0,
|
||||
USB_SYSCFG_HSE_SHIFT,
|
||||
USB_SYSCFG_HSE);
|
||||
return USB_HOST_ATTACH;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do Nothing */
|
||||
}
|
||||
}
|
||||
else if ((rhst == USB_HOST_HSMODE) || (rhst == USB_HOST_FSMODE))
|
||||
{
|
||||
return USB_HOST_ATTACH;
|
||||
}
|
||||
else if (rhst == USB_HOST_LSMODE)
|
||||
{
|
||||
return USB_HOST_ATTACH;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do Nothing */
|
||||
}
|
||||
|
||||
return USB_HOST_DETACH;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_UsbAttach
|
||||
* Description : Connects the USB device.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_UsbAttach (void)
|
||||
{
|
||||
usb1_host_EnableINT_Module();
|
||||
usb1_host_Disable_BchgINT();
|
||||
usb1_host_Disable_AttachINT();
|
||||
usb1_host_Enable_DetachINT();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_UsbDetach
|
||||
* Description : Disconnects the USB device.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_UsbDetach (void)
|
||||
{
|
||||
uint16_t pipe;
|
||||
uint16_t devadr;
|
||||
|
||||
g_usb1_host_driver_state = USB_HOST_DRV_DETACHED;
|
||||
|
||||
/* Terminate all the pipes in which communications on port */
|
||||
/* are currently carried out */
|
||||
for (pipe = 0; pipe < (USB_HOST_MAX_PIPE_NO + 1); ++pipe)
|
||||
{
|
||||
if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_IDLE)
|
||||
{
|
||||
if (pipe == USB_HOST_PIPE0)
|
||||
{
|
||||
devadr = RZA_IO_RegRead_16(&USB201.DCPMAXP,
|
||||
USB_DCPMAXP_DEVSEL_SHIFT,
|
||||
USB_DCPMAXP_DEVSEL);
|
||||
}
|
||||
else
|
||||
{
|
||||
devadr = RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL);
|
||||
}
|
||||
|
||||
if (devadr == g_usb1_host_UsbAddress)
|
||||
{
|
||||
usb1_host_stop_transfer(pipe);
|
||||
}
|
||||
|
||||
g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_IDLE;
|
||||
}
|
||||
}
|
||||
|
||||
g_usb1_host_ConfigNum = 0;
|
||||
g_usb1_host_UsbAddress = 0;
|
||||
g_usb1_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
|
||||
|
||||
usb1_host_UsbDetach2();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_UsbDetach2
|
||||
* Description : Disconnects the USB device.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_UsbDetach2 (void)
|
||||
{
|
||||
usb1_host_Disable_DetachINT();
|
||||
usb1_host_Disable_BchgINT();
|
||||
usb1_host_Enable_AttachINT();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_UsbBusReset
|
||||
* Description : Issues the USB bus reset signal.
|
||||
* Arguments : none
|
||||
* Return Value : uint16_t ; RHST
|
||||
*******************************************************************************/
|
||||
uint16_t usb1_host_UsbBusReset (void)
|
||||
{
|
||||
uint16_t buffer;
|
||||
uint16_t loop;
|
||||
|
||||
RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
|
||||
1,
|
||||
USB_DVSTCTR0_USBRST_SHIFT,
|
||||
USB_DVSTCTR0_USBRST);
|
||||
RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
|
||||
0,
|
||||
USB_DVSTCTR0_UACT_SHIFT,
|
||||
USB_DVSTCTR0_UACT);
|
||||
|
||||
Userdef_USB_usb1_host_delay_xms(50);
|
||||
|
||||
buffer = USB201.DVSTCTR0;
|
||||
buffer &= (uint16_t)(~(USB_HOST_BITRST));
|
||||
buffer |= USB_HOST_BITUACT;
|
||||
USB201.DVSTCTR0 = buffer;
|
||||
|
||||
Userdef_USB_usb1_host_delay_xms(20);
|
||||
|
||||
for (loop = 0, buffer = USB_HOST_HSPROC; loop < 3; ++loop)
|
||||
{
|
||||
buffer = RZA_IO_RegRead_16(&USB201.DVSTCTR0,
|
||||
USB_DVSTCTR0_RHST_SHIFT,
|
||||
USB_DVSTCTR0_RHST);
|
||||
if (buffer == USB_HOST_HSPROC)
|
||||
{
|
||||
Userdef_USB_usb1_host_delay_xms(10);
|
||||
}
|
||||
else
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return buffer;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_UsbResume
|
||||
* Description : Issues the USB resume signal.
|
||||
* Arguments : none
|
||||
* Return Value : int32_t ; DEVDRV_SUCCESS
|
||||
* : ; DEVDRV_ERROR
|
||||
*******************************************************************************/
|
||||
int32_t usb1_host_UsbResume (void)
|
||||
{
|
||||
uint16_t buf;
|
||||
|
||||
if ((g_usb1_host_driver_state & USB_HOST_DRV_SUSPEND) == 0)
|
||||
{
|
||||
/* not SUSPEND */
|
||||
return DEVDRV_ERROR;
|
||||
}
|
||||
|
||||
RZA_IO_RegWrite_16(&USB201.INTENB1,
|
||||
0,
|
||||
USB_INTENB1_BCHGE_SHIFT,
|
||||
USB_INTENB1_BCHGE);
|
||||
RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
|
||||
1,
|
||||
USB_DVSTCTR0_RESUME_SHIFT,
|
||||
USB_DVSTCTR0_RESUME);
|
||||
Userdef_USB_usb1_host_delay_xms(20);
|
||||
|
||||
buf = USB201.DVSTCTR0;
|
||||
buf &= (uint16_t)(~(USB_HOST_BITRESUME));
|
||||
buf |= USB_HOST_BITUACT;
|
||||
USB201.DVSTCTR0 = buf;
|
||||
|
||||
g_usb1_host_driver_state &= (uint16_t)~USB_HOST_DRV_SUSPEND;
|
||||
|
||||
return DEVDRV_SUCCESS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_UsbSuspend
|
||||
* Description : Issues the USB suspend signal.
|
||||
* Arguments : none
|
||||
* Return Value : int32_t ; DEVDRV_SUCCESS :not SUSPEND
|
||||
* : ; DEVDRV_ERROR :SUSPEND
|
||||
*******************************************************************************/
|
||||
int32_t usb1_host_UsbSuspend (void)
|
||||
{
|
||||
uint16_t buf;
|
||||
|
||||
if ((g_usb1_host_driver_state & USB_HOST_DRV_SUSPEND) != 0)
|
||||
{
|
||||
/* SUSPEND */
|
||||
return DEVDRV_ERROR;
|
||||
}
|
||||
|
||||
RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
|
||||
0,
|
||||
USB_DVSTCTR0_UACT_SHIFT,
|
||||
USB_DVSTCTR0_UACT);
|
||||
|
||||
Userdef_USB_usb1_host_delay_xms(5);
|
||||
|
||||
buf = RZA_IO_RegRead_16(&USB201.SYSSTS0,
|
||||
USB_SYSSTS0_LNST_SHIFT,
|
||||
USB_SYSSTS0_LNST);
|
||||
if ((buf != USB_HOST_FS_JSTS) && (buf != USB_HOST_LS_JSTS))
|
||||
{
|
||||
usb1_host_UsbDetach();
|
||||
}
|
||||
else
|
||||
{
|
||||
g_usb1_host_driver_state |= USB_HOST_DRV_SUSPEND;
|
||||
}
|
||||
|
||||
return DEVDRV_SUCCESS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_Enable_DetachINT
|
||||
* Description : Enables the USB disconnection interrupt.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_Enable_DetachINT (void)
|
||||
{
|
||||
USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
|
||||
RZA_IO_RegWrite_16(&USB201.INTENB1,
|
||||
1,
|
||||
USB_INTENB1_DTCHE_SHIFT,
|
||||
USB_INTENB1_DTCHE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_Disable_DetachINT
|
||||
* Description : Disables the USB disconnection interrupt.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_Disable_DetachINT (void)
|
||||
{
|
||||
USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
|
||||
RZA_IO_RegWrite_16(&USB201.INTENB1,
|
||||
0,
|
||||
USB_INTENB1_DTCHE_SHIFT,
|
||||
USB_INTENB1_DTCHE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_Enable_AttachINT
|
||||
* Description : Enables the USB connection detection interrupt.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_Enable_AttachINT (void)
|
||||
{
|
||||
USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
|
||||
RZA_IO_RegWrite_16(&USB201.INTENB1,
|
||||
1,
|
||||
USB_INTENB1_ATTCHE_SHIFT,
|
||||
USB_INTENB1_ATTCHE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_Disable_AttachINT
|
||||
* Description : Disables the USB connection detection interrupt.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_Disable_AttachINT (void)
|
||||
{
|
||||
USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
|
||||
RZA_IO_RegWrite_16(&USB201.INTENB1,
|
||||
0,
|
||||
USB_INTENB1_ATTCHE_SHIFT,
|
||||
USB_INTENB1_ATTCHE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_Disable_BchgINT
|
||||
* Description : Disables the USB bus change detection interrupt.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_Disable_BchgINT (void)
|
||||
{
|
||||
USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITBCHG));
|
||||
RZA_IO_RegWrite_16(&USB201.INTENB1,
|
||||
0,
|
||||
USB_INTENB1_BCHGE_SHIFT,
|
||||
USB_INTENB1_BCHGE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_set_devadd
|
||||
* Description : DEVADDn register is set by specified value
|
||||
* Arguments : uint16_t addr : Device address
|
||||
* : uint16_t *devadd : Set value
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_set_devadd (uint16_t addr, uint16_t * devadd)
|
||||
{
|
||||
uint16_t * ptr;
|
||||
uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning.
|
||||
|
||||
switch (addr)
|
||||
{
|
||||
case USB_HOST_DEVICE_0:
|
||||
ptr = (uint16_t *)&USB201.DEVADD0;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_1:
|
||||
ptr = (uint16_t *)&USB201.DEVADD1;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_2:
|
||||
ptr = (uint16_t *)&USB201.DEVADD2;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_3:
|
||||
ptr = (uint16_t *)&USB201.DEVADD3;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_4:
|
||||
ptr = (uint16_t *)&USB201.DEVADD4;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_5:
|
||||
ptr = (uint16_t *)&USB201.DEVADD5;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_6:
|
||||
ptr = (uint16_t *)&USB201.DEVADD6;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_7:
|
||||
ptr = (uint16_t *)&USB201.DEVADD7;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_8:
|
||||
ptr = (uint16_t *)&USB201.DEVADD8;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_9:
|
||||
ptr = (uint16_t *)&USB201.DEVADD9;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_10:
|
||||
ptr = (uint16_t *)&USB201.DEVADDA;
|
||||
break;
|
||||
|
||||
default:
|
||||
ret_flag = DEVDRV_FLAG_OFF;
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret_flag == DEVDRV_FLAG_ON)
|
||||
{
|
||||
*ptr = (uint16_t)(*devadd & USB_HOST_DEVADD_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_get_devadd
|
||||
* Description : DEVADDn register is obtained
|
||||
* Arguments : uint16_t addr : Device address
|
||||
* : uint16_t *devadd : USB_HOST_DEVADD register value
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_get_devadd (uint16_t addr, uint16_t * devadd)
|
||||
{
|
||||
uint16_t * ptr;
|
||||
uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning.
|
||||
|
||||
switch (addr)
|
||||
{
|
||||
case USB_HOST_DEVICE_0:
|
||||
ptr = (uint16_t *)&USB201.DEVADD0;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_1:
|
||||
ptr = (uint16_t *)&USB201.DEVADD1;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_2:
|
||||
ptr = (uint16_t *)&USB201.DEVADD2;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_3:
|
||||
ptr = (uint16_t *)&USB201.DEVADD3;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_4:
|
||||
ptr = (uint16_t *)&USB201.DEVADD4;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_5:
|
||||
ptr = (uint16_t *)&USB201.DEVADD5;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_6:
|
||||
ptr = (uint16_t *)&USB201.DEVADD6;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_7:
|
||||
ptr = (uint16_t *)&USB201.DEVADD7;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_8:
|
||||
ptr = (uint16_t *)&USB201.DEVADD8;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_9:
|
||||
ptr = (uint16_t *)&USB201.DEVADD9;
|
||||
break;
|
||||
|
||||
case USB_HOST_DEVICE_10:
|
||||
ptr = (uint16_t *)&USB201.DEVADDA;
|
||||
break;
|
||||
|
||||
default:
|
||||
ret_flag = DEVDRV_FLAG_OFF;
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret_flag == DEVDRV_FLAG_ON)
|
||||
{
|
||||
*devadd = *ptr;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_EnableINT_Module
|
||||
* Description : Enables BEMP/NRDY/BRDY interrupt and SIGN/SACK interrupt.
|
||||
* : Enables NRDY/BEMP interrupt in the pipe0.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_EnableINT_Module (void)
|
||||
{
|
||||
uint16_t buf;
|
||||
|
||||
buf = USB201.INTENB0;
|
||||
buf |= (USB_HOST_BITBEMPE | USB_HOST_BITNRDYE | USB_HOST_BITBRDYE);
|
||||
USB201.INTENB0 = buf;
|
||||
|
||||
buf = USB201.INTENB1;
|
||||
buf |= (USB_HOST_BITSIGNE | USB_HOST_BITSACKE);
|
||||
USB201.INTENB1 = buf;
|
||||
|
||||
usb1_host_enable_nrdy_int(USB_HOST_PIPE0);
|
||||
usb1_host_enable_bemp_int(USB_HOST_PIPE0);
|
||||
}
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,698 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_host_dmacdrv.c
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Device(s) : RZ/A1H
|
||||
* Tool-Chain :
|
||||
* OS : None
|
||||
* H/W Platform :
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
* Operation :
|
||||
* Limitations :
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include "r_typedefs.h"
|
||||
#include "iodefine.h"
|
||||
#include "rza_io_regrw.h"
|
||||
#include "usb1_host_dmacdrv.h"
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
|
||||
|
||||
/* ==== Request setting information for on-chip peripheral module ==== */
|
||||
typedef enum dmac_peri_req_reg_type
|
||||
{
|
||||
DMAC_REQ_MID,
|
||||
DMAC_REQ_RID,
|
||||
DMAC_REQ_AM,
|
||||
DMAC_REQ_LVL,
|
||||
DMAC_REQ_REQD
|
||||
} dmac_peri_req_reg_type_t;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private global variables and functions
|
||||
*******************************************************************************/
|
||||
/* ==== Prototype declaration ==== */
|
||||
|
||||
/* ==== Global variable ==== */
|
||||
/* On-chip peripheral module request setting table */
|
||||
static const uint8_t usb1_host_dmac_peri_req_init_table[8][5] =
|
||||
{
|
||||
/* MID,RID, AM,LVL,REQD */
|
||||
{ 32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
|
||||
{ 32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
|
||||
{ 33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
|
||||
{ 33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
|
||||
{ 34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
|
||||
{ 34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
|
||||
{ 35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
|
||||
{ 35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
|
||||
};
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_DMAC3_PeriReqInit
|
||||
* Description : Sets the register mode for DMA mode and the on-chip peripheral
|
||||
* : module request for transfer request for DMAC channel 3.
|
||||
* : Executes DMAC initial setting using the DMA information
|
||||
* : specified by the argument *trans_info and the enabled/disabled
|
||||
* : continuous transfer specified by the argument continuation.
|
||||
* : Registers DMAC channel 3 interrupt handler function and sets
|
||||
* : the interrupt priority level. Then enables transfer completion
|
||||
* : interrupt.
|
||||
* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
|
||||
* : : register
|
||||
* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
|
||||
* : uint32_t continuation : Set continuous transfer to be valid
|
||||
* : : after DMA transfer has been completed
|
||||
* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
|
||||
* : DMAC_SAMPLE_SINGLE : Do not execute continuous
|
||||
* : : transfer
|
||||
* : uint32_t request_factor : Factor for on-chip peripheral module
|
||||
* : : request
|
||||
* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
|
||||
* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
|
||||
* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
|
||||
* : :
|
||||
* : uint32_t req_direction : Setting value of CHCFG_n register
|
||||
* : : REQD bit
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_DMAC3_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
|
||||
uint32_t request_factor, uint32_t req_direction)
|
||||
{
|
||||
/* ==== Register mode ==== */
|
||||
if (DMAC_MODE_REGISTER == dmamode)
|
||||
{
|
||||
/* ==== Next0 register set ==== */
|
||||
DMAC3.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
|
||||
DMAC3.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
|
||||
DMAC3.N0TB_n = trans_info->count; /* Total transfer byte count */
|
||||
|
||||
/* DAD : Transfer destination address counting direction */
|
||||
/* SAD : Transfer source address counting direction */
|
||||
/* DDS : Transfer destination transfer size */
|
||||
/* SDS : Transfer source transfer size */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
trans_info->daddr_dir,
|
||||
DMAC3_CHCFG_n_DAD_SHIFT,
|
||||
DMAC3_CHCFG_n_DAD);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
trans_info->saddr_dir,
|
||||
DMAC3_CHCFG_n_SAD_SHIFT,
|
||||
DMAC3_CHCFG_n_SAD);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
trans_info->dst_size,
|
||||
DMAC3_CHCFG_n_DDS_SHIFT,
|
||||
DMAC3_CHCFG_n_DDS);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
trans_info->src_size,
|
||||
DMAC3_CHCFG_n_SDS_SHIFT,
|
||||
DMAC3_CHCFG_n_SDS);
|
||||
|
||||
/* DMS : Register mode */
|
||||
/* RSEL : Select Next0 register set */
|
||||
/* SBE : No discharge of buffer data when aborted */
|
||||
/* DEM : No DMA interrupt mask */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
0,
|
||||
DMAC3_CHCFG_n_DMS_SHIFT,
|
||||
DMAC3_CHCFG_n_DMS);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
0,
|
||||
DMAC3_CHCFG_n_RSEL_SHIFT,
|
||||
DMAC3_CHCFG_n_RSEL);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
0,
|
||||
DMAC3_CHCFG_n_SBE_SHIFT,
|
||||
DMAC3_CHCFG_n_SBE);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
0,
|
||||
DMAC3_CHCFG_n_DEM_SHIFT,
|
||||
DMAC3_CHCFG_n_DEM);
|
||||
|
||||
/* ---- Continuous transfer ---- */
|
||||
if (DMAC_SAMPLE_CONTINUATION == continuation)
|
||||
{
|
||||
/* REN : Execute continuous transfer */
|
||||
/* RSW : Change register set when DMA transfer is completed. */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
1,
|
||||
DMAC3_CHCFG_n_REN_SHIFT,
|
||||
DMAC3_CHCFG_n_REN);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
1,
|
||||
DMAC3_CHCFG_n_RSW_SHIFT,
|
||||
DMAC3_CHCFG_n_RSW);
|
||||
}
|
||||
/* ---- Single transfer ---- */
|
||||
else
|
||||
{
|
||||
/* REN : Do not execute continuous transfer */
|
||||
/* RSW : Do not change register set when DMA transfer is completed. */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
0,
|
||||
DMAC3_CHCFG_n_REN_SHIFT,
|
||||
DMAC3_CHCFG_n_REN);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
0,
|
||||
DMAC3_CHCFG_n_RSW_SHIFT,
|
||||
DMAC3_CHCFG_n_RSW);
|
||||
}
|
||||
|
||||
/* TM : Single transfer */
|
||||
/* SEL : Channel setting */
|
||||
/* HIEN, LOEN : On-chip peripheral module request */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
0,
|
||||
DMAC3_CHCFG_n_TM_SHIFT,
|
||||
DMAC3_CHCFG_n_TM);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
3,
|
||||
DMAC3_CHCFG_n_SEL_SHIFT,
|
||||
DMAC3_CHCFG_n_SEL);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
1,
|
||||
DMAC3_CHCFG_n_HIEN_SHIFT,
|
||||
DMAC3_CHCFG_n_HIEN);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
0,
|
||||
DMAC3_CHCFG_n_LOEN_SHIFT,
|
||||
DMAC3_CHCFG_n_LOEN);
|
||||
|
||||
/* ---- Set factor by specified on-chip peripheral module request ---- */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
|
||||
DMAC3_CHCFG_n_AM_SHIFT,
|
||||
DMAC3_CHCFG_n_AM);
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
|
||||
DMAC3_CHCFG_n_LVL_SHIFT,
|
||||
DMAC3_CHCFG_n_LVL);
|
||||
if (usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
|
||||
{
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
|
||||
DMAC3_CHCFG_n_REQD_SHIFT,
|
||||
DMAC3_CHCFG_n_REQD);
|
||||
}
|
||||
else
|
||||
{
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
|
||||
req_direction,
|
||||
DMAC3_CHCFG_n_REQD_SHIFT,
|
||||
DMAC3_CHCFG_n_REQD);
|
||||
}
|
||||
RZA_IO_RegWrite_32(&DMAC23.DMARS,
|
||||
usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
|
||||
DMAC23_DMARS_CH3_RID_SHIFT,
|
||||
DMAC23_DMARS_CH3_RID);
|
||||
RZA_IO_RegWrite_32(&DMAC23.DMARS,
|
||||
usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
|
||||
DMAC23_DMARS_CH3_MID_SHIFT,
|
||||
DMAC23_DMARS_CH3_MID);
|
||||
|
||||
/* PR : Round robin mode */
|
||||
RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
|
||||
1,
|
||||
DMAC07_DCTRL_0_7_PR_SHIFT,
|
||||
DMAC07_DCTRL_0_7_PR);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_DMAC3_Open
|
||||
* Description : Enables DMAC channel 3 transfer.
|
||||
* Arguments : uint32_t req : DMAC request mode
|
||||
* Return Value : 0 : Succeeded in enabling DMA transfer
|
||||
* : -1 : Failed to enable DMA transfer (due to DMA operation)
|
||||
*******************************************************************************/
|
||||
int32_t usb1_host_DMAC3_Open (uint32_t req)
|
||||
{
|
||||
int32_t ret;
|
||||
volatile uint8_t dummy;
|
||||
|
||||
/* Transferable? */
|
||||
if ((0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
|
||||
DMAC3_CHSTAT_n_EN_SHIFT,
|
||||
DMAC3_CHSTAT_n_EN)) &&
|
||||
(0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
|
||||
DMAC3_CHSTAT_n_TACT_SHIFT,
|
||||
DMAC3_CHSTAT_n_TACT)))
|
||||
{
|
||||
/* Clear Channel Status Register */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
|
||||
1,
|
||||
DMAC3_CHCTRL_n_SWRST_SHIFT,
|
||||
DMAC3_CHCTRL_n_SWRST);
|
||||
dummy = RZA_IO_RegRead_32(&DMAC3.CHCTRL_n,
|
||||
DMAC3_CHCTRL_n_SWRST_SHIFT,
|
||||
DMAC3_CHCTRL_n_SWRST);
|
||||
/* Enable DMA transfer */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
|
||||
1,
|
||||
DMAC3_CHCTRL_n_SETEN_SHIFT,
|
||||
DMAC3_CHCTRL_n_SETEN);
|
||||
|
||||
/* ---- Request by software ---- */
|
||||
if (DMAC_REQ_MODE_SOFT == req)
|
||||
{
|
||||
/* DMA transfer Request by software */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
|
||||
1,
|
||||
DMAC3_CHCTRL_n_STG_SHIFT,
|
||||
DMAC3_CHCTRL_n_STG);
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = -1;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_DMAC3_Close
|
||||
* Description : Aborts DMAC channel 3 transfer. Returns the remaining transfer
|
||||
* : byte count at the time of DMA transfer abort to the argument
|
||||
* : *remain.
|
||||
* Arguments : uint32_t * remain : Remaining transfer byte count when
|
||||
* : : DMA transfer is aborted
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_DMAC3_Close (uint32_t * remain)
|
||||
{
|
||||
|
||||
/* ==== Abort transfer ==== */
|
||||
RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
|
||||
1,
|
||||
DMAC3_CHCTRL_n_CLREN_SHIFT,
|
||||
DMAC3_CHCTRL_n_CLREN);
|
||||
|
||||
while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
|
||||
DMAC3_CHSTAT_n_TACT_SHIFT,
|
||||
DMAC3_CHSTAT_n_TACT))
|
||||
{
|
||||
/* Loop until transfer is aborted */
|
||||
}
|
||||
|
||||
while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
|
||||
DMAC3_CHSTAT_n_EN_SHIFT,
|
||||
DMAC3_CHSTAT_n_EN))
|
||||
{
|
||||
/* Loop until 0 is set in EN before checking the remaining transfer byte count */
|
||||
}
|
||||
/* ==== Obtain remaining transfer byte count ==== */
|
||||
*remain = DMAC3.CRTB_n;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_DMAC3_Load_Set
|
||||
* Description : Sets the transfer source address, transfer destination
|
||||
* : address, and total transfer byte count respectively
|
||||
* : specified by the argument src_addr, dst_addr, and count to
|
||||
* : DMAC channel 3 as DMA transfer information.
|
||||
* : Sets the register set selected by the CHCFG_n register
|
||||
* : RSEL bit from the Next0 or Next1 register set.
|
||||
* : This function should be called when DMA transfer of DMAC
|
||||
* : channel 3 is aboted.
|
||||
* Arguments : uint32_t src_addr : Transfer source address
|
||||
* : uint32_t dst_addr : Transfer destination address
|
||||
* : uint32_t count : Total transfer byte count
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_DMAC3_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
|
||||
{
|
||||
uint8_t reg_set;
|
||||
|
||||
/* Obtain register set in use */
|
||||
reg_set = RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
|
||||
DMAC3_CHSTAT_n_SR_SHIFT,
|
||||
DMAC3_CHSTAT_n_SR);
|
||||
|
||||
/* ==== Load ==== */
|
||||
if (0 == reg_set)
|
||||
{
|
||||
/* ---- Next0 Register Set ---- */
|
||||
DMAC3.N0SA_n = src_addr; /* Start address of transfer source */
|
||||
DMAC3.N0DA_n = dst_addr; /* Start address of transfer destination */
|
||||
DMAC3.N0TB_n = count; /* Total transfer byte count */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* ---- Next1 Register Set ---- */
|
||||
DMAC3.N1SA_n = src_addr; /* Start address of transfer source */
|
||||
DMAC3.N1DA_n = dst_addr; /* Start address of transfer destination */
|
||||
DMAC3.N1TB_n = count; /* Total transfer byte count */
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_DMAC4_PeriReqInit
|
||||
* Description : Sets the register mode for DMA mode and the on-chip peripheral
|
||||
* : module request for transfer request for DMAC channel 4.
|
||||
* : Executes DMAC initial setting using the DMA information
|
||||
* : specified by the argument *trans_info and the enabled/disabled
|
||||
* : continuous transfer specified by the argument continuation.
|
||||
* : Registers DMAC channel 4 interrupt handler function and sets
|
||||
* : the interrupt priority level. Then enables transfer completion
|
||||
* : interrupt.
|
||||
* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
|
||||
* : : register
|
||||
* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
|
||||
* : uint32_t continuation : Set continuous transfer to be valid
|
||||
* : : after DMA transfer has been completed
|
||||
* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
|
||||
* : DMAC_SAMPLE_SINGLE : Do not execute continuous
|
||||
* : : transfer
|
||||
* : uint32_t request_factor : Factor for on-chip peripheral module
|
||||
* : : request
|
||||
* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
|
||||
* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
|
||||
* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
|
||||
* : :
|
||||
* : uint32_t req_direction : Setting value of CHCFG_n register
|
||||
* : : REQD bit
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_DMAC4_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
|
||||
uint32_t request_factor, uint32_t req_direction)
|
||||
{
|
||||
/* ==== Register mode ==== */
|
||||
if (DMAC_MODE_REGISTER == dmamode)
|
||||
{
|
||||
/* ==== Next0 register set ==== */
|
||||
DMAC4.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
|
||||
DMAC4.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
|
||||
DMAC4.N0TB_n = trans_info->count; /* Total transfer byte count */
|
||||
|
||||
/* DAD : Transfer destination address counting direction */
|
||||
/* SAD : Transfer source address counting direction */
|
||||
/* DDS : Transfer destination transfer size */
|
||||
/* SDS : Transfer source transfer size */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
trans_info->daddr_dir,
|
||||
DMAC4_CHCFG_n_DAD_SHIFT,
|
||||
DMAC4_CHCFG_n_DAD);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
trans_info->saddr_dir,
|
||||
DMAC4_CHCFG_n_SAD_SHIFT,
|
||||
DMAC4_CHCFG_n_SAD);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
trans_info->dst_size,
|
||||
DMAC4_CHCFG_n_DDS_SHIFT,
|
||||
DMAC4_CHCFG_n_DDS);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
trans_info->src_size,
|
||||
DMAC4_CHCFG_n_SDS_SHIFT,
|
||||
DMAC4_CHCFG_n_SDS);
|
||||
|
||||
/* DMS : Register mode */
|
||||
/* RSEL : Select Next0 register set */
|
||||
/* SBE : No discharge of buffer data when aborted */
|
||||
/* DEM : No DMA interrupt mask */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
0,
|
||||
DMAC4_CHCFG_n_DMS_SHIFT,
|
||||
DMAC4_CHCFG_n_DMS);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
0,
|
||||
DMAC4_CHCFG_n_RSEL_SHIFT,
|
||||
DMAC4_CHCFG_n_RSEL);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
0,
|
||||
DMAC4_CHCFG_n_SBE_SHIFT,
|
||||
DMAC4_CHCFG_n_SBE);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
0,
|
||||
DMAC4_CHCFG_n_DEM_SHIFT,
|
||||
DMAC4_CHCFG_n_DEM);
|
||||
|
||||
/* ---- Continuous transfer ---- */
|
||||
if (DMAC_SAMPLE_CONTINUATION == continuation)
|
||||
{
|
||||
/* REN : Execute continuous transfer */
|
||||
/* RSW : Change register set when DMA transfer is completed. */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
1,
|
||||
DMAC4_CHCFG_n_REN_SHIFT,
|
||||
DMAC4_CHCFG_n_REN);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
1,
|
||||
DMAC4_CHCFG_n_RSW_SHIFT,
|
||||
DMAC4_CHCFG_n_RSW);
|
||||
}
|
||||
/* ---- Single transfer ---- */
|
||||
else
|
||||
{
|
||||
/* REN : Do not execute continuous transfer */
|
||||
/* RSW : Do not change register set when DMA transfer is completed. */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
0,
|
||||
DMAC4_CHCFG_n_REN_SHIFT,
|
||||
DMAC4_CHCFG_n_REN);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
0,
|
||||
DMAC4_CHCFG_n_RSW_SHIFT,
|
||||
DMAC4_CHCFG_n_RSW);
|
||||
}
|
||||
|
||||
/* TM : Single transfer */
|
||||
/* SEL : Channel setting */
|
||||
/* HIEN, LOEN : On-chip peripheral module request */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
0,
|
||||
DMAC4_CHCFG_n_TM_SHIFT,
|
||||
DMAC4_CHCFG_n_TM);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
4,
|
||||
DMAC4_CHCFG_n_SEL_SHIFT,
|
||||
DMAC4_CHCFG_n_SEL);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
1,
|
||||
DMAC4_CHCFG_n_HIEN_SHIFT,
|
||||
DMAC4_CHCFG_n_HIEN);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
0,
|
||||
DMAC4_CHCFG_n_LOEN_SHIFT,
|
||||
DMAC4_CHCFG_n_LOEN);
|
||||
|
||||
/* ---- Set factor by specified on-chip peripheral module request ---- */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
|
||||
DMAC4_CHCFG_n_AM_SHIFT,
|
||||
DMAC4_CHCFG_n_AM);
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
|
||||
DMAC4_CHCFG_n_LVL_SHIFT,
|
||||
DMAC4_CHCFG_n_LVL);
|
||||
if (usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
|
||||
{
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
|
||||
DMAC4_CHCFG_n_REQD_SHIFT,
|
||||
DMAC4_CHCFG_n_REQD);
|
||||
}
|
||||
else
|
||||
{
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||||
req_direction,
|
||||
DMAC4_CHCFG_n_REQD_SHIFT,
|
||||
DMAC4_CHCFG_n_REQD);
|
||||
}
|
||||
RZA_IO_RegWrite_32(&DMAC45.DMARS,
|
||||
usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
|
||||
DMAC45_DMARS_CH4_RID_SHIFT,
|
||||
DMAC45_DMARS_CH4_RID);
|
||||
RZA_IO_RegWrite_32(&DMAC45.DMARS,
|
||||
usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
|
||||
DMAC45_DMARS_CH4_MID_SHIFT,
|
||||
DMAC45_DMARS_CH4_MID);
|
||||
|
||||
/* PR : Round robin mode */
|
||||
RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
|
||||
1,
|
||||
DMAC07_DCTRL_0_7_PR_SHIFT,
|
||||
DMAC07_DCTRL_0_7_PR);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_DMAC4_Open
|
||||
* Description : Enables DMAC channel 4 transfer.
|
||||
* Arguments : uint32_t req : DMAC request mode
|
||||
* Return Value : 0 : Succeeded in enabling DMA transfer
|
||||
* : -1 : Failed to enable DMA transfer (due to DMA operation)
|
||||
*******************************************************************************/
|
||||
int32_t usb1_host_DMAC4_Open (uint32_t req)
|
||||
{
|
||||
int32_t ret;
|
||||
volatile uint8_t dummy;
|
||||
|
||||
/* Transferable? */
|
||||
if ((0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
|
||||
DMAC4_CHSTAT_n_EN_SHIFT,
|
||||
DMAC4_CHSTAT_n_EN)) &&
|
||||
(0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
|
||||
DMAC4_CHSTAT_n_TACT_SHIFT,
|
||||
DMAC4_CHSTAT_n_TACT)))
|
||||
{
|
||||
/* Clear Channel Status Register */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
|
||||
1,
|
||||
DMAC4_CHCTRL_n_SWRST_SHIFT,
|
||||
DMAC4_CHCTRL_n_SWRST);
|
||||
dummy = RZA_IO_RegRead_32(&DMAC4.CHCTRL_n,
|
||||
DMAC4_CHCTRL_n_SWRST_SHIFT,
|
||||
DMAC4_CHCTRL_n_SWRST);
|
||||
/* Enable DMA transfer */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
|
||||
1,
|
||||
DMAC4_CHCTRL_n_SETEN_SHIFT,
|
||||
DMAC4_CHCTRL_n_SETEN);
|
||||
|
||||
/* ---- Request by software ---- */
|
||||
if (DMAC_REQ_MODE_SOFT == req)
|
||||
{
|
||||
/* DMA transfer Request by software */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
|
||||
1,
|
||||
DMAC4_CHCTRL_n_STG_SHIFT,
|
||||
DMAC4_CHCTRL_n_STG);
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = -1;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_DMAC4_Close
|
||||
* Description : Aborts DMAC channel 4 transfer. Returns the remaining transfer
|
||||
* : byte count at the time of DMA transfer abort to the argument
|
||||
* : *remain.
|
||||
* Arguments : uint32_t * remain : Remaining transfer byte count when
|
||||
* : : DMA transfer is aborted
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_DMAC4_Close (uint32_t * remain)
|
||||
{
|
||||
|
||||
/* ==== Abort transfer ==== */
|
||||
RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
|
||||
1,
|
||||
DMAC4_CHCTRL_n_CLREN_SHIFT,
|
||||
DMAC4_CHCTRL_n_CLREN);
|
||||
|
||||
while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
|
||||
DMAC4_CHSTAT_n_TACT_SHIFT,
|
||||
DMAC4_CHSTAT_n_TACT))
|
||||
{
|
||||
/* Loop until transfer is aborted */
|
||||
}
|
||||
|
||||
while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
|
||||
DMAC4_CHSTAT_n_EN_SHIFT,
|
||||
DMAC4_CHSTAT_n_EN))
|
||||
{
|
||||
/* Loop until 0 is set in EN before checking the remaining transfer byte count */
|
||||
}
|
||||
/* ==== Obtain remaining transfer byte count ==== */
|
||||
*remain = DMAC4.CRTB_n;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_DMAC4_Load_Set
|
||||
* Description : Sets the transfer source address, transfer destination
|
||||
* : address, and total transfer byte count respectively
|
||||
* : specified by the argument src_addr, dst_addr, and count to
|
||||
* : DMAC channel 4 as DMA transfer information.
|
||||
* : Sets the register set selected by the CHCFG_n register
|
||||
* : RSEL bit from the Next0 or Next1 register set.
|
||||
* : This function should be called when DMA transfer of DMAC
|
||||
* : channel 4 is aboted.
|
||||
* Arguments : uint32_t src_addr : Transfer source address
|
||||
* : uint32_t dst_addr : Transfer destination address
|
||||
* : uint32_t count : Total transfer byte count
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void usb1_host_DMAC4_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
|
||||
{
|
||||
uint8_t reg_set;
|
||||
|
||||
/* Obtain register set in use */
|
||||
reg_set = RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
|
||||
DMAC4_CHSTAT_n_SR_SHIFT,
|
||||
DMAC4_CHSTAT_n_SR);
|
||||
|
||||
/* ==== Load ==== */
|
||||
if (0 == reg_set)
|
||||
{
|
||||
/* ---- Next0 Register Set ---- */
|
||||
DMAC4.N0SA_n = src_addr; /* Start address of transfer source */
|
||||
DMAC4.N0DA_n = dst_addr; /* Start address of transfer destination */
|
||||
DMAC4.N0TB_n = count; /* Total transfer byte count */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* ---- Next1 Register Set ---- */
|
||||
DMAC4.N1SA_n = src_addr; /* Start address of transfer source */
|
||||
DMAC4.N1DA_n = dst_addr; /* Start address of transfer destination */
|
||||
DMAC4.N1TB_n = count; /* Total transfer byte count */
|
||||
}
|
||||
}
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,778 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* File Name : usb1_host_userdef.c
|
||||
* $Rev: 1116 $
|
||||
* $Date:: 2014-07-09 16:29:19 +0900#$
|
||||
* Device(s) : RZ/A1H
|
||||
* Tool-Chain :
|
||||
* OS : None
|
||||
* H/W Platform :
|
||||
* Description : RZ/A1H R7S72100 USB Sample Program
|
||||
* Operation :
|
||||
* Limitations :
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
*******************************************************************************/
|
||||
#include <stdio.h>
|
||||
#include "cmsis_os.h"
|
||||
#include "r_typedefs.h"
|
||||
#include "iodefine.h"
|
||||
#include "devdrv_usb_host_api.h"
|
||||
#include "usb1_host.h"
|
||||
#include "MBRZA1H.h" /* INTC Driver Header */
|
||||
#include "usb1_host_dmacdrv.h"
|
||||
#include "ohci_wrapp_RZ_A1_local.h"
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Typedef definitions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Macro definitions
|
||||
*******************************************************************************/
|
||||
#define DUMMY_ACCESS OSTM0CNT
|
||||
|
||||
/* #define CACHE_WRITEBACK */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
*******************************************************************************/
|
||||
extern int32_t io_cwb(unsigned long start, unsigned long end);
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
*******************************************************************************/
|
||||
static void usb1_host_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count,
|
||||
uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
|
||||
static void usb1_host_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count,
|
||||
uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
|
||||
static void Userdef_USB_usb1_host_delay_10us_2(void);
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
Private global variables and functions
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_host_d0fifo_dmaintid
|
||||
* Description : get D0FIFO DMA Interrupt ID
|
||||
* Arguments : none
|
||||
* Return Value : D0FIFO DMA Interrupt ID
|
||||
*******************************************************************************/
|
||||
uint16_t Userdef_USB_usb1_host_d0fifo_dmaintid (void)
|
||||
{
|
||||
#if(1) /* ohci_wrapp */
|
||||
return 0xFFFF;
|
||||
#else
|
||||
return DMAINT1_IRQn;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_host_d1fifo_dmaintid
|
||||
* Description : get D1FIFO DMA Interrupt ID
|
||||
* Arguments : none
|
||||
* Return Value : D1FIFO DMA Interrupt ID
|
||||
*******************************************************************************/
|
||||
uint16_t Userdef_USB_usb1_host_d1fifo_dmaintid (void)
|
||||
{
|
||||
#if(1) /* ohci_wrapp */
|
||||
return 0xFFFF;
|
||||
#else
|
||||
return DMAINT2_IRQn;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_host_attach
|
||||
* Description : Wait for the software of 1ms.
|
||||
* : Alter this function according to the user's system.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void Userdef_USB_usb1_host_attach (void)
|
||||
{
|
||||
// printf("\n");
|
||||
// printf("channel 1 attach device\n");
|
||||
// printf("\n");
|
||||
ohciwrapp_loc_Connect(1);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_host_detach
|
||||
* Description : Wait for the software of 1ms.
|
||||
* : Alter this function according to the user's system.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void Userdef_USB_usb1_host_detach (void)
|
||||
{
|
||||
// printf("\n");
|
||||
// printf("channel 1 detach device\n");
|
||||
// printf("\n");
|
||||
ohciwrapp_loc_Connect(0);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_host_delay_1ms
|
||||
* Description : Wait for the software of 1ms.
|
||||
* : Alter this function according to the user's system.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void Userdef_USB_usb1_host_delay_1ms (void)
|
||||
{
|
||||
osDelay(1);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_host_delay_xms
|
||||
* Description : Wait for the software in the period of time specified by the
|
||||
* : argument.
|
||||
* : Alter this function according to the user's system.
|
||||
* Arguments : uint32_t msec ; Wait Time (msec)
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void Userdef_USB_usb1_host_delay_xms (uint32_t msec)
|
||||
{
|
||||
osDelay(msec);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_host_delay_10us
|
||||
* Description : Waits for software for the period specified by the argument.
|
||||
* : Alter this function according to the user's system.
|
||||
* Arguments : uint32_t usec ; Wait Time(x 10usec)
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void Userdef_USB_usb1_host_delay_10us (uint32_t usec)
|
||||
{
|
||||
volatile int i;
|
||||
|
||||
/* Wait 10us (Please change for your MCU) */
|
||||
for (i = 0; i < usec; ++i)
|
||||
{
|
||||
Userdef_USB_usb1_host_delay_10us_2();
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_host_delay_10us_2
|
||||
* Description : Waits for software for the period specified by the argument.
|
||||
* : Alter this function according to the user's system.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
static void Userdef_USB_usb1_host_delay_10us_2 (void)
|
||||
{
|
||||
volatile int i;
|
||||
volatile unsigned long tmp;
|
||||
|
||||
/* Wait 1us (Please change for your MCU) */
|
||||
for (i = 0; i < 14; ++i)
|
||||
{
|
||||
tmp = DUMMY_ACCESS;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_host_delay_500ns
|
||||
* Description : Wait for software for 500ns.
|
||||
* : Alter this function according to the user's system.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void Userdef_USB_usb1_host_delay_500ns (void)
|
||||
{
|
||||
volatile int i;
|
||||
volatile unsigned long tmp;
|
||||
|
||||
/* Wait 500ns (Please change for your MCU) */
|
||||
/* Wait 500ns I clock 266MHz */
|
||||
tmp = DUMMY_ACCESS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_host_start_dma
|
||||
* Description : Enables DMA transfer on the information specified by the argument.
|
||||
* : Set DMAC register by this function to enable DMA transfer.
|
||||
* : After executing this function, USB module is set to start DMA
|
||||
* : transfer. DMA transfer should not wait for DMA transfer complete.
|
||||
* Arguments : USB_HOST_DMA_t *dma : DMA parameter
|
||||
* : typedef struct{
|
||||
* : uint32_t fifo; FIFO for using
|
||||
* : uint32_t buffer; Start address of transfer source/destination
|
||||
* : uint32_t bytes; Transfer size(Byte)
|
||||
* : uint32_t dir; Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer)
|
||||
* : uint32_t size; DMA transfer size
|
||||
* : } USB_HOST_DMA_t;
|
||||
* : uint16_t dfacc ; 0 : cycle steal mode
|
||||
* : 1 : 16byte continuous mode
|
||||
* : 2 : 32byte continuous mode
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void Userdef_USB_usb1_host_start_dma (USB_HOST_DMA_t * dma, uint16_t dfacc)
|
||||
{
|
||||
uint32_t trncount;
|
||||
uint32_t src;
|
||||
uint32_t dst;
|
||||
uint32_t size;
|
||||
uint32_t dir;
|
||||
#ifdef CACHE_WRITEBACK
|
||||
uint32_t ptr;
|
||||
#endif
|
||||
|
||||
trncount = dma->bytes;
|
||||
dir = dma->dir;
|
||||
|
||||
if (dir == USB_HOST_FIFO2BUF)
|
||||
{
|
||||
/* DxFIFO determination */
|
||||
dst = dma->buffer;
|
||||
#ifndef __USB_HOST_DF_ACC_ENABLE__
|
||||
if (dma->fifo == USB_HOST_D0FIFO_DMA)
|
||||
{
|
||||
src = (uint32_t)(&USB201.D0FIFO.UINT32);
|
||||
}
|
||||
else
|
||||
{
|
||||
src = (uint32_t)(&USB201.D1FIFO.UINT32);
|
||||
}
|
||||
size = dma->size;
|
||||
|
||||
if (size == 0)
|
||||
{
|
||||
src += 3; /* byte access */
|
||||
}
|
||||
else if (size == 1)
|
||||
{
|
||||
src += 2; /* short access */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do Nothing */
|
||||
}
|
||||
#else
|
||||
size = dma->size;
|
||||
|
||||
if (size == 2)
|
||||
{
|
||||
/* 32bit access */
|
||||
if (dfacc == 2)
|
||||
{
|
||||
/* 32byte access */
|
||||
if (dma->fifo == USB_HOST_D0FIFO_DMA)
|
||||
{
|
||||
src = (uint32_t)(&USB201.D0FIFOB0);
|
||||
}
|
||||
else
|
||||
{
|
||||
src = (uint32_t)(&USB201.D1FIFOB0);
|
||||
}
|
||||
}
|
||||
else if (dfacc == 1)
|
||||
{
|
||||
/* 16byte access */
|
||||
if (dma->fifo == USB_HOST_D0FIFO_DMA)
|
||||
{
|
||||
src = (uint32_t)(&USB201.D0FIFOB0);
|
||||
}
|
||||
else
|
||||
{
|
||||
src = (uint32_t)(&USB201.D1FIFOB0);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* normal access */
|
||||
if (dma->fifo == USB_HOST_D0FIFO_DMA)
|
||||
{
|
||||
src = (uint32_t)(&USB201.D0FIFO.UINT32);
|
||||
}
|
||||
else
|
||||
{
|
||||
src = (uint32_t)(&USB201.D1FIFO.UINT32);
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (size == 1)
|
||||
{
|
||||
/* 16bit access */
|
||||
dfacc = 0; /* force normal access */
|
||||
|
||||
if (dma->fifo == USB_HOST_D0FIFO_DMA)
|
||||
{
|
||||
src = (uint32_t)(&USB201.D0FIFO.UINT32);
|
||||
}
|
||||
else
|
||||
{
|
||||
src = (uint32_t)(&USB201.D1FIFO.UINT32);
|
||||
}
|
||||
src += 2; /* short access */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 8bit access */
|
||||
dfacc = 0; /* force normal access */
|
||||
if (dma->fifo == USB_HOST_D0FIFO_DMA)
|
||||
{
|
||||
src = (uint32_t)(&USB201.D0FIFO.UINT32);
|
||||
}
|
||||
else
|
||||
{
|
||||
src = (uint32_t)(&USB201.D1FIFO.UINT32);
|
||||
}
|
||||
src += 3; /* byte access */
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DxFIFO determination */
|
||||
src = dma->buffer;
|
||||
#ifndef __USB_HOST_DF_ACC_ENABLE__
|
||||
if (dma->fifo == USB_HOST_D0FIFO_DMA)
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D0FIFO.UINT32);
|
||||
}
|
||||
else
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D1FIFO.UINT32);
|
||||
}
|
||||
size = dma->size;
|
||||
|
||||
if (size == 0)
|
||||
{
|
||||
dst += 3; /* byte access */
|
||||
}
|
||||
else if (size == 1)
|
||||
{
|
||||
dst += 2; /* short access */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do Nothing */
|
||||
}
|
||||
#else
|
||||
size = dma->size;
|
||||
if (size == 2)
|
||||
{
|
||||
/* 32bit access */
|
||||
if (dfacc == 2)
|
||||
{
|
||||
/* 32byte access */
|
||||
if (dma->fifo == USB_HOST_D0FIFO_DMA)
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D0FIFOB0);
|
||||
}
|
||||
else
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D1FIFOB0);
|
||||
}
|
||||
}
|
||||
else if (dfacc == 1)
|
||||
{
|
||||
/* 16byte access */
|
||||
if (dma->fifo == USB_HOST_D0FIFO_DMA)
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D0FIFOB0);
|
||||
}
|
||||
else
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D1FIFOB0);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* normal access */
|
||||
if (dma->fifo == USB_HOST_D0FIFO_DMA)
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D0FIFO.UINT32);
|
||||
}
|
||||
else
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D1FIFO.UINT32);
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (size == 1)
|
||||
{
|
||||
/* 16bit access */
|
||||
dfacc = 0; /* force normal access */
|
||||
if (dma->fifo == USB_HOST_D0FIFO_DMA)
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D0FIFO.UINT32);
|
||||
}
|
||||
else
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D1FIFO.UINT32);
|
||||
}
|
||||
dst += 2; /* short access */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 8bit access */
|
||||
dfacc = 0; /* force normal access */
|
||||
if (dma->fifo == USB_HOST_D0FIFO_DMA)
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D0FIFO.UINT32);
|
||||
}
|
||||
else
|
||||
{
|
||||
dst = (uint32_t)(&USB201.D1FIFO.UINT32);
|
||||
}
|
||||
dst += 3; /* byte access */
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CACHE_WRITEBACK
|
||||
ptr = (uint32_t)dma->buffer;
|
||||
if ((ptr & 0x20000000ul) == 0)
|
||||
{
|
||||
io_cwb((uint32_t)ptr,(uint32_t)(ptr)+trncount);
|
||||
}
|
||||
#endif
|
||||
|
||||
if (dma->fifo == USB_HOST_D0FIFO_DMA)
|
||||
{
|
||||
usb1_host_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc);
|
||||
}
|
||||
else
|
||||
{
|
||||
usb1_host_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_enable_dmac0
|
||||
* Description : Enables DMA transfer on the information specified by the argument.
|
||||
* Arguments : uint32_t src : src address
|
||||
* : uint32_t dst : dst address
|
||||
* : uint32_t count : transfer byte
|
||||
* : uint32_t size : transfer size
|
||||
* : uint32_t dir : direction
|
||||
* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
|
||||
* : uint16_t dfacc : 0 : normal access
|
||||
* : : 1 : 16byte access
|
||||
* : : 2 : 32byte access
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
static void usb1_host_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count,
|
||||
uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
|
||||
{
|
||||
dmac_transinfo_t trans_info;
|
||||
uint32_t request_factor = 0;
|
||||
int32_t ret;
|
||||
|
||||
/* ==== Variable setting for DMAC initialization ==== */
|
||||
trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
|
||||
trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
|
||||
trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
|
||||
#ifndef __USB_HOST_DF_ACC_ENABLE__
|
||||
if (size == 0)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (size == 1)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (size == 2)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
|
||||
}
|
||||
else
|
||||
{
|
||||
// printf("size error!!\n");
|
||||
}
|
||||
#else
|
||||
if (dfacc == 2)
|
||||
{
|
||||
/* 32byte access */
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (dfacc == 1)
|
||||
{
|
||||
/* 16byte access */
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* normal access */
|
||||
if (size == 0)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (size == 1)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (size == 2)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
|
||||
}
|
||||
else
|
||||
{
|
||||
// printf("size error!!\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
if (dir == USB_HOST_FIFO2BUF)
|
||||
{
|
||||
request_factor = DMAC_REQ_USB1_DMA0_RX; /* USB_0 channel 0 receive FIFO full */
|
||||
trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
|
||||
trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
|
||||
}
|
||||
else if (dir == USB_HOST_BUF2FIFO)
|
||||
{
|
||||
request_factor = DMAC_REQ_USB1_DMA0_TX; /* USB_0 channel 0 receive FIFO empty */
|
||||
trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
|
||||
trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do Nothing */
|
||||
}
|
||||
|
||||
/* ==== DMAC initialization ==== */
|
||||
usb1_host_DMAC3_PeriReqInit((const dmac_transinfo_t *)&trans_info,
|
||||
DMAC_MODE_REGISTER,
|
||||
DMAC_SAMPLE_SINGLE,
|
||||
request_factor,
|
||||
0); /* Don't care DMAC_REQ_REQD is setting in usb1_host_DMAC3_PeriReqInit() */
|
||||
|
||||
/* ==== DMAC startup ==== */
|
||||
ret = usb1_host_DMAC3_Open(DMAC_REQ_MODE_PERI);
|
||||
|
||||
if (ret != 0)
|
||||
{
|
||||
// printf("DMAC3 Open error!!\n");
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: usb1_host_enable_dmac1
|
||||
* Description : Enables DMA transfer on the information specified by the argument.
|
||||
* Arguments : uint32_t src : src address
|
||||
* : uint32_t dst : dst address
|
||||
* : uint32_t count : transfer byte
|
||||
* : uint32_t size : transfer size
|
||||
* : uint32_t dir : direction
|
||||
* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
|
||||
* : uint16_t dfacc : 0 : normal access
|
||||
* : : 1 : 16byte access
|
||||
* : : 2 : 32byte access
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
static void usb1_host_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count,
|
||||
uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
|
||||
{
|
||||
dmac_transinfo_t trans_info;
|
||||
uint32_t request_factor = 0;
|
||||
int32_t ret;
|
||||
|
||||
/* ==== Variable setting for DMAC initialization ==== */
|
||||
trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
|
||||
trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
|
||||
trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
|
||||
#ifndef __USB_HOST_DF_ACC_ENABLE__
|
||||
if (size == 0)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (size == 1)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (size == 2)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
|
||||
}
|
||||
else
|
||||
{
|
||||
// printf("size error!!\n");
|
||||
}
|
||||
#else
|
||||
if (dfacc == 2)
|
||||
{
|
||||
/* 32byte access */
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (dfacc == 1)
|
||||
{
|
||||
/* 16byte access */
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* normal access */
|
||||
if (size == 0)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (size == 1)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
|
||||
}
|
||||
else if (size == 2)
|
||||
{
|
||||
trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
|
||||
trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
|
||||
}
|
||||
else
|
||||
{
|
||||
// printf("size error!!\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
if (dir == USB_HOST_FIFO2BUF)
|
||||
{
|
||||
request_factor =DMAC_REQ_USB1_DMA1_RX; /* USB_0 channel 0 receive FIFO full */
|
||||
trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
|
||||
trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
|
||||
}
|
||||
else if (dir == USB_HOST_BUF2FIFO)
|
||||
{
|
||||
request_factor =DMAC_REQ_USB1_DMA1_TX; /* USB_0 channel 0 receive FIFO empty */
|
||||
trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
|
||||
trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do Nothing */
|
||||
}
|
||||
|
||||
/* ==== DMAC initialization ==== */
|
||||
usb1_host_DMAC4_PeriReqInit((const dmac_transinfo_t *)&trans_info,
|
||||
DMAC_MODE_REGISTER,
|
||||
DMAC_SAMPLE_SINGLE,
|
||||
request_factor,
|
||||
0); /* Don't care DMAC_REQ_REQD is setting in usb1_host_DMAC4_PeriReqInit() */
|
||||
|
||||
/* ==== DMAC startup ==== */
|
||||
ret = usb1_host_DMAC4_Open(DMAC_REQ_MODE_PERI);
|
||||
|
||||
if (ret != 0)
|
||||
{
|
||||
// printf("DMAC4 Open error!!\n");
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_host_stop_dma0
|
||||
* Description : Disables DMA transfer.
|
||||
* Arguments : none
|
||||
* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
|
||||
* : regarding to the bus width.
|
||||
* Notice : This function should be executed to DMAC executed at the time
|
||||
* : of specification of D0_FIF0_DMA in dma->fifo.
|
||||
*******************************************************************************/
|
||||
uint32_t Userdef_USB_usb1_host_stop_dma0 (void)
|
||||
{
|
||||
uint32_t remain;
|
||||
|
||||
/* ==== DMAC release ==== */
|
||||
usb1_host_DMAC3_Close(&remain);
|
||||
|
||||
return remain;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_host_stop_dma1
|
||||
* Description : Disables DMA transfer.
|
||||
* : This function should be executed to DMAC executed at the time
|
||||
* : of specification of D1_FIF0_DMA in dma->fifo.
|
||||
* Arguments : none
|
||||
* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
|
||||
* : regarding to the bus width.
|
||||
*******************************************************************************/
|
||||
uint32_t Userdef_USB_usb1_host_stop_dma1 (void)
|
||||
{
|
||||
uint32_t remain;
|
||||
|
||||
/* ==== DMAC release ==== */
|
||||
usb1_host_DMAC4_Close(&remain);
|
||||
|
||||
return remain;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_host_notice
|
||||
* Description : Notice of USER
|
||||
* Arguments : const char *format
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void Userdef_USB_usb1_host_notice (const char * format)
|
||||
{
|
||||
// printf(format);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Userdef_USB_usb1_host_user_rdy
|
||||
* Description : This function notify a user and wait for trigger
|
||||
* Arguments : const char *format
|
||||
* : uint16_t data
|
||||
* Return Value : none
|
||||
*******************************************************************************/
|
||||
void Userdef_USB_usb1_host_user_rdy (const char * format, uint16_t data)
|
||||
{
|
||||
// printf(format, data);
|
||||
getchar();
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2014 - 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef USB_HOST_SETTING_H
|
||||
#define USB_HOST_SETTING_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define USB_HOST_CH 0
|
||||
#define USB_HOST_HISPEED 1
|
||||
|
||||
#define INT_TRANS_MAX_NUM 4 /* min:1 max:4 */
|
||||
#define ISO_TRANS_MAX_NUM 0 /* min:0 max:2 */
|
||||
|
||||
#if (USB_HOST_CH == 0)
|
||||
#include "usb0_host.h"
|
||||
#define USB20X USB200
|
||||
#define USBIXUSBIX USBI0_IRQn
|
||||
#define g_usbx_host_SupportUsbDeviceSpeed g_usb0_host_SupportUsbDeviceSpeed
|
||||
#define g_usbx_host_UsbDeviceSpeed g_usb0_host_UsbDeviceSpeed
|
||||
#define g_usbx_host_CmdStage g_usb0_host_CmdStage
|
||||
#define g_usbx_host_pipe_status g_usb0_host_pipe_status
|
||||
#define g_usbx_host_data_pointer g_usb0_host_data_pointer
|
||||
#define g_usbx_host_data_count g_usb0_host_data_count
|
||||
#define usbx_api_host_init usb0_api_host_init
|
||||
#define usbx_host_UsbBusReset usb0_host_UsbBusReset
|
||||
#define usbx_host_get_devadd usb0_host_get_devadd
|
||||
#define usbx_host_set_devadd usb0_host_set_devadd
|
||||
#define usbx_host_SetupStage usb0_host_SetupStage
|
||||
#define usbx_host_CtrlWriteStart usb0_host_CtrlWriteStart
|
||||
#define usbx_host_CtrlReadStart usb0_host_CtrlReadStart
|
||||
#define usbx_api_host_SetEndpointTable usb0_api_host_SetEndpointTable
|
||||
#define usbx_host_start_send_transfer usb0_host_start_send_transfer
|
||||
#define usbx_host_start_receive_transfer usb0_host_start_receive_transfer
|
||||
#define usbx_host_stop_transfer usb0_host_stop_transfer
|
||||
#define usbx_host_set_sqclr usb0_host_set_sqclr
|
||||
#define usbx_host_set_sqset usb0_host_set_sqset
|
||||
#define usbx_host_CheckAttach usb0_host_CheckAttach
|
||||
#define usbx_host_UsbDetach usb0_host_UsbDetach
|
||||
#define usbx_host_UsbAttach usb0_host_UsbAttach
|
||||
#define usbx_host_init_pipe_status usb0_host_init_pipe_status
|
||||
#define usbx_host_get_sqmon usb0_host_get_sqmon
|
||||
#else
|
||||
#include "usb1_host.h"
|
||||
#define USB20X USB201
|
||||
#define USBIXUSBIX USBI1_IRQn
|
||||
#define g_usbx_host_SupportUsbDeviceSpeed g_usb1_host_SupportUsbDeviceSpeed
|
||||
#define g_usbx_host_UsbDeviceSpeed g_usb1_host_UsbDeviceSpeed
|
||||
#define g_usbx_host_CmdStage g_usb1_host_CmdStage
|
||||
#define g_usbx_host_pipe_status g_usb1_host_pipe_status
|
||||
#define g_usbx_host_data_pointer g_usb1_host_data_pointer
|
||||
#define g_usbx_host_data_count g_usb1_host_data_count
|
||||
#define usbx_api_host_init usb1_api_host_init
|
||||
#define usbx_host_UsbBusReset usb1_host_UsbBusReset
|
||||
#define usbx_host_get_devadd usb1_host_get_devadd
|
||||
#define usbx_host_set_devadd usb1_host_set_devadd
|
||||
#define usbx_host_SetupStage usb1_host_SetupStage
|
||||
#define usbx_host_CtrlWriteStart usb1_host_CtrlWriteStart
|
||||
#define usbx_host_CtrlReadStart usb1_host_CtrlReadStart
|
||||
#define usbx_api_host_SetEndpointTable usb1_api_host_SetEndpointTable
|
||||
#define usbx_host_start_send_transfer usb1_host_start_send_transfer
|
||||
#define usbx_host_start_receive_transfer usb1_host_start_receive_transfer
|
||||
#define usbx_host_stop_transfer usb1_host_stop_transfer
|
||||
#define usbx_host_set_sqclr usb1_host_set_sqclr
|
||||
#define usbx_host_set_sqset usb1_host_set_sqset
|
||||
#define usbx_host_CheckAttach usb1_host_CheckAttach
|
||||
#define usbx_host_UsbDetach usb1_host_UsbDetach
|
||||
#define usbx_host_UsbAttach usb1_host_UsbAttach
|
||||
#define usbx_host_init_pipe_status usb1_host_init_pipe_status
|
||||
#define usbx_host_get_sqmon usb1_host_get_sqmon
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* USB_HOST_SETTING_H */
|
||||
|
|
@ -47,7 +47,7 @@ USBHALHost::USBHALHost() {
|
|||
}
|
||||
|
||||
void USBHALHost::init() {
|
||||
ohciwrapp_init(&_usbisr, 1);
|
||||
ohciwrapp_init(&_usbisr);
|
||||
|
||||
ohciwrapp_reg_w(OHCI_REG_CONTROL, 1); // HARDWARE RESET
|
||||
ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, 0); // Initialize Control list head to Zero
|
||||
|
|
@ -266,9 +266,6 @@ void USBHALHost::UsbIrqhandler() {
|
|||
usb_hcca->DoneHead = 0;
|
||||
}
|
||||
|
||||
// wait 200ms to avoid bounce
|
||||
wait_ms(200);
|
||||
|
||||
deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
|
||||
|
||||
if (int_status & OR_INTR_STATUS_WDH) {
|
||||
|
|
|
|||
|
|
@ -644,6 +644,8 @@ typedef enum IRQn
|
|||
|
||||
#include "pl310.h"
|
||||
#include "gic.h"
|
||||
#include "nvic_wrapper.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#include "ostm_iodefine.h"
|
||||
#include "gpio_iodefine.h"
|
||||
|
|
|
|||
|
|
@ -173,7 +173,7 @@ goToSleep:
|
|||
|
||||
@ Setup Stack for each exceptional mode
|
||||
/* ldr r0, =__StackTop */
|
||||
ldr r0, =__initial_sp
|
||||
ldr r0, =(__StackTop - USR_Stack_Size)
|
||||
|
||||
@ Enter Undefined Instruction Mode and set its Stack Pointer
|
||||
msr cpsr_c, #(Mode_UND | I_Bit | F_Bit)
|
||||
|
|
@ -521,9 +521,9 @@ ret_irq:
|
|||
__user_initial_stackheap:
|
||||
|
||||
LDR R0, = __HeapBase
|
||||
LDR R1, =(__StackLimit + USR_Stack_Size)
|
||||
LDR R1, =(__StackTop)
|
||||
LDR R2, = (__HeapBase + Heap_Size)
|
||||
LDR R3, = __StackLimit
|
||||
LDR R3, = (__StackTop - USR_Stack_Size)
|
||||
BX LR
|
||||
|
||||
.endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,42 @@
|
|||
/* mbed Microcontroller Library
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2015 ARM Limited. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "MBRZA1H.h"
|
||||
|
||||
extern IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
||||
InterruptHandlerRegister(IRQn, (IRQHandler)vector);
|
||||
}
|
||||
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
||||
uint32_t vectors = (uint32_t)IRQTable[IRQn];
|
||||
return vectors;
|
||||
}
|
||||
|
|
@ -1,13 +1,7 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_crc.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the CRC firmware
|
||||
* library.
|
||||
/* mbed Microcontroller Library
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* Copyright (c) 2015 ARM Limited. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -18,7 +12,7 @@
|
|||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
|
|
@ -35,75 +29,18 @@
|
|||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_CRC_H
|
||||
#define __STM32F10x_CRC_H
|
||||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void CRC_ResetDR(void);
|
||||
uint32_t CRC_CalcCRC(uint32_t Data);
|
||||
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t CRC_GetCRC(void);
|
||||
void CRC_SetIDRegister(uint8_t IDValue);
|
||||
uint8_t CRC_GetIDRegister(void);
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_CRC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
#endif
|
||||
|
|
@ -0,0 +1,229 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @file nvic_wrapper.c
|
||||
* $Rev: $
|
||||
* $Date:: $
|
||||
* @brief Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9)
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
******************************************************************************/
|
||||
#include "MBRZA1H.h"
|
||||
#include "wdt_iodefine.h"
|
||||
#include "nvic_wrapper.h"
|
||||
#include "gic.h"
|
||||
|
||||
/******************************************************************************
|
||||
Typedef definitions
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
Macro definitions
|
||||
******************************************************************************/
|
||||
#define PRIO_BITS (7) /* Set binary point to 0 in gic.c */
|
||||
#define WDT_WTCNT_WRITE (0x5A00)
|
||||
#define WDT_WTCSR_WRITE (0xA500)
|
||||
#define WDT_WRCSR_WOVF_WRITE (0xA500)
|
||||
#define WDT_WRCSR_RSTE_WRITE (0x5A00)
|
||||
|
||||
/******************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
Private global variables and functions
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||
{
|
||||
GIC_SetBinaryPoint(PriorityGroup);
|
||||
}
|
||||
|
||||
|
||||
uint32_t NVIC_GetPriorityGrouping(void)
|
||||
{
|
||||
return GIC_GetBinaryPoint(0);
|
||||
}
|
||||
|
||||
|
||||
void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
GIC_EnableIRQ(IRQn);
|
||||
}
|
||||
|
||||
|
||||
void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
GIC_DisableIRQ(IRQn);
|
||||
}
|
||||
|
||||
|
||||
uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t pending;
|
||||
|
||||
pending = GIC_GetIRQStatus(IRQn);
|
||||
pending = (pending & 0x00000001);
|
||||
|
||||
return pending;
|
||||
}
|
||||
|
||||
|
||||
void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
GIC_SetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
|
||||
void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
GIC_ClearPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
|
||||
uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t active;
|
||||
|
||||
active = GIC_GetIRQStatus(IRQn);
|
||||
active = ((active >> 1) & 0x00000001);
|
||||
|
||||
return active;
|
||||
}
|
||||
|
||||
|
||||
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
GIC_SetPriority(IRQn, (priority << 3));
|
||||
}
|
||||
|
||||
|
||||
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t priority_field;
|
||||
|
||||
priority_field = GIC_GetPriority(IRQn);
|
||||
priority_field = (priority_field >> 3);
|
||||
return priority_field;
|
||||
}
|
||||
|
||||
|
||||
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp;
|
||||
SubPriorityBits = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS;
|
||||
|
||||
return (
|
||||
((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
|
||||
((SubPriority & ((1 << (SubPriorityBits )) - 1)))
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp;
|
||||
SubPriorityBits = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS;
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
|
||||
*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
|
||||
}
|
||||
|
||||
void NVIC_SystemReset(void)
|
||||
{
|
||||
uint16_t reg;
|
||||
uint8_t dummy_read;
|
||||
/* Use Watch Dog Timer to system reset */
|
||||
|
||||
/* Set WT/IT bit of WTCSR to 1 = Watch Dog */
|
||||
/* CLK = 000, 1xP0phi(=33.3333MHz) = 7.7us */
|
||||
reg = (WDT_WTCSR_WRITE | 0x0058);
|
||||
WDTWTCSR = reg;
|
||||
|
||||
/* Clear Count reg */
|
||||
reg = (WDT_WTCNT_WRITE | 0x0000);
|
||||
WDTWTCNT = reg;
|
||||
|
||||
/* Clear WOVF flag */
|
||||
dummy_read = WDTWRCSR;
|
||||
reg = (WDT_WRCSR_WOVF_WRITE | (dummy_read & 0x0000));
|
||||
WDTWRCSR = reg;
|
||||
/* Enable Internal Reset */
|
||||
reg = (WDT_WRCSR_RSTE_WRITE | 0x005F);
|
||||
WDTWRCSR = reg;
|
||||
|
||||
/* Watch Dog start */
|
||||
reg = (WDT_WTCSR_WRITE | 0x0078);
|
||||
WDTWTCSR = reg;
|
||||
|
||||
while(1); /* wait Internal Reset */
|
||||
}
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
/* Not support this function */
|
||||
/* Use mbed Ticker */
|
||||
return (1); /* impossible */
|
||||
}
|
||||
|
||||
|
||||
/* ##################################### Debug In/Output function ########################################### */
|
||||
uint32_t ITM_SendChar (uint32_t ch)
|
||||
{
|
||||
/* Not support this function */
|
||||
/* Use mbed Serial */
|
||||
return (ch);
|
||||
}
|
||||
|
||||
|
||||
int32_t ITM_ReceiveChar (void) {
|
||||
/* Not support this function */
|
||||
/* Use mbed Serial */
|
||||
return (-1); /* no character available */
|
||||
}
|
||||
|
||||
|
||||
int32_t ITM_CheckChar (void) {
|
||||
/* Not support this function */
|
||||
/* Use mbed Serial */
|
||||
return (0); /* no character available */
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
*******************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @file nvic_wrapper.h
|
||||
* $Rev: $
|
||||
* $Date:: $
|
||||
* @brief Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9)
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef NVIC_WRAPPER_H
|
||||
#define NVIC_WRAPPER_H
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
******************************************************************************/
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
Typedef definitions
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
Macro definitions
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
Variable Externs
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
Functions Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/* NVIC functions */
|
||||
void NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
|
||||
uint32_t NVIC_GetPriorityGrouping(void);
|
||||
void NVIC_EnableIRQ(IRQn_Type IRQn);
|
||||
void NVIC_DisableIRQ(IRQn_Type IRQn);
|
||||
uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
||||
void NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
||||
void NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
||||
uint32_t NVIC_GetActive(IRQn_Type IRQn);
|
||||
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
|
||||
uint32_t NVIC_GetPriority(IRQn_Type IRQn);
|
||||
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority);
|
||||
void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
|
||||
void NVIC_SystemReset(void);
|
||||
/* SysTick function */
|
||||
uint32_t SysTick_Config(uint32_t ticks);
|
||||
/* Debug In/Output function */
|
||||
uint32_t ITM_SendChar (uint32_t ch);
|
||||
int32_t ITM_ReceiveChar (void);
|
||||
int32_t ITM_CheckChar (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* NVIC_WRAPPER_H */
|
||||
|
|
@ -1,398 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32f10x_md_vl.s
|
||||
* @author MCD Application Team
|
||||
* @version V3.3.0
|
||||
* @date 04/16/2010
|
||||
* @brief STM32F10x Medium Density Value Line Devices vector table for RIDE7
|
||||
* toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Configure the clock system
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
*******************************************************************************
|
||||
* @copy
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m3
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
.equ BootRAM, 0xF108F85F
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call the application's entry point.*/
|
||||
bl _start
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_IRQHandler
|
||||
.word TAMPER_IRQHandler
|
||||
.word RTC_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word DMA1_Channel1_IRQHandler
|
||||
.word DMA1_Channel2_IRQHandler
|
||||
.word DMA1_Channel3_IRQHandler
|
||||
.word DMA1_Channel4_IRQHandler
|
||||
.word DMA1_Channel5_IRQHandler
|
||||
.word DMA1_Channel6_IRQHandler
|
||||
.word DMA1_Channel7_IRQHandler
|
||||
.word ADC1_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word EXTI9_5_IRQHandler
|
||||
.word TIM1_BRK_TIM15_IRQHandler
|
||||
.word TIM1_UP_TIM16_IRQHandler
|
||||
.word TIM1_TRG_COM_TIM17_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word TIM3_IRQHandler
|
||||
.word TIM4_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word I2C2_EV_IRQHandler
|
||||
.word I2C2_ER_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word SPI2_IRQHandler
|
||||
.word USART1_IRQHandler
|
||||
.word USART2_IRQHandler
|
||||
.word USART3_IRQHandler
|
||||
.word EXTI15_10_IRQHandler
|
||||
.word RTCAlarm_IRQHandler
|
||||
.word CEC_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word TIM6_DAC_IRQHandler
|
||||
.word TIM7_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word BootRAM /* @0x01CC. This is for boot in RAM mode for
|
||||
STM32F10x Medium Value Line Density devices. */
|
||||
|
||||
/*******************************************************************************
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_IRQHandler
|
||||
.thumb_set PVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMPER_IRQHandler
|
||||
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_IRQHandler
|
||||
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_TIM15_IRQHandler
|
||||
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_TIM16_IRQHandler
|
||||
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_TIM17_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTCAlarm_IRQHandler
|
||||
.thumb_set RTCAlarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak CEC_IRQHandler
|
||||
.thumb_set CEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_DAC_IRQHandler
|
||||
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,240 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file misc.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides all the miscellaneous firmware functions (add-on
|
||||
* to CMSIS functions).
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "misc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC
|
||||
* @brief MISC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the priority grouping: pre-emption priority and subpriority.
|
||||
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
|
||||
* 1 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
|
||||
* 0 bits for subpriority
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
|
||||
|
||||
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
|
||||
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the NVIC peripheral according to the specified
|
||||
* parameters in the NVIC_InitStruct.
|
||||
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
|
||||
* the configuration information for the specified NVIC peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
|
||||
{
|
||||
uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
|
||||
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
|
||||
|
||||
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
|
||||
{
|
||||
/* Compute the Corresponding IRQ Priority --------------------------------*/
|
||||
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
|
||||
tmppre = (0x4 - tmppriority);
|
||||
tmpsub = tmpsub >> tmppriority;
|
||||
|
||||
tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
|
||||
tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
|
||||
tmppriority = tmppriority << 0x04;
|
||||
|
||||
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
|
||||
|
||||
/* Enable the Selected IRQ Channels --------------------------------------*/
|
||||
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
||||
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the Selected IRQ Channels -------------------------------------*/
|
||||
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
||||
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the vector table location and Offset.
|
||||
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_VectTab_RAM
|
||||
* @arg NVIC_VectTab_FLASH
|
||||
* @param Offset: Vector Table base offset field. This value must be a multiple
|
||||
* of 0x200.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
|
||||
assert_param(IS_NVIC_OFFSET(Offset));
|
||||
|
||||
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the condition for the system to enter low power mode.
|
||||
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_LP_SEVONPEND
|
||||
* @arg NVIC_LP_SLEEPDEEP
|
||||
* @arg NVIC_LP_SLEEPONEXIT
|
||||
* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_LP(LowPowerMode));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
SCB->SCR |= LowPowerMode;
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source.
|
||||
* @param SysTick_CLKSource: specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
|
||||
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SysTick_CLKSource_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,235 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file misc.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the miscellaneous
|
||||
* firmware library functions (add-on to CMSIS functions).
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __MISC_H
|
||||
#define __MISC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief NVIC Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
|
||||
This parameter can be a value of @ref IRQn_Type
|
||||
(For the complete STM32 Devices IRQ Channels list, please
|
||||
refer to stm32f10x.h file) */
|
||||
|
||||
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
|
||||
specified in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
|
||||
|
||||
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
|
||||
in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
|
||||
|
||||
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
|
||||
will be enabled or disabled.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
} NVIC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup NVIC_Priority_Table
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
@code
|
||||
The table below gives the allowed values of the pre-emption priority and subpriority according
|
||||
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
|
||||
============================================================================================================================
|
||||
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
||||
============================================================================================================================
|
||||
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
|
||||
| | | 4 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
|
||||
| | | 3 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
|
||||
| | | 2 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
|
||||
| | | 1 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
|
||||
| | | 0 bits for subpriority
|
||||
============================================================================================================================
|
||||
@endcode
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup Vector_Table_Base
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
|
||||
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
|
||||
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
|
||||
((VECTTAB) == NVIC_VectTab_FLASH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup System_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
|
||||
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
|
||||
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
|
||||
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
|
||||
((LP) == NVIC_LP_SLEEPDEEP) || \
|
||||
((LP) == NVIC_LP_SLEEPONEXIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Preemption_Priority_Group
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
|
||||
((GROUP) == NVIC_PriorityGroup_1) || \
|
||||
((GROUP) == NVIC_PriorityGroup_2) || \
|
||||
((GROUP) == NVIC_PriorityGroup_3) || \
|
||||
((GROUP) == NVIC_PriorityGroup_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SysTick_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
||||
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
|
||||
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
|
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MISC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,498 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the ADC firmware
|
||||
* library.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_ADC_H
|
||||
#define __STM32F10x_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ADC Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or
|
||||
dual mode.
|
||||
This parameter can be a value of @ref ADC_mode */
|
||||
|
||||
FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
|
||||
Scan (multichannels) or Single (one channel) mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
|
||||
Continuous or Single mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
|
||||
to digital conversion of regular channels. This parameter
|
||||
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
|
||||
|
||||
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
|
||||
This parameter can be a value of @ref ADC_data_align */
|
||||
|
||||
uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted
|
||||
using the sequencer for regular channel group.
|
||||
This parameter must range from 1 to 16. */
|
||||
}ADC_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
|
||||
((PERIPH) == ADC2) || \
|
||||
((PERIPH) == ADC3))
|
||||
|
||||
#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
|
||||
((PERIPH) == ADC3))
|
||||
|
||||
/** @defgroup ADC_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_Mode_Independent ((uint32_t)0x00000000)
|
||||
#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
|
||||
#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
|
||||
#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
|
||||
#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
|
||||
#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
|
||||
#define ADC_Mode_RegSimult ((uint32_t)0x00060000)
|
||||
#define ADC_Mode_FastInterl ((uint32_t)0x00070000)
|
||||
#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
|
||||
#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
|
||||
|
||||
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
|
||||
((MODE) == ADC_Mode_RegInjecSimult) || \
|
||||
((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
|
||||
((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
|
||||
((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
|
||||
((MODE) == ADC_Mode_InjecSimult) || \
|
||||
((MODE) == ADC_Mode_RegSimult) || \
|
||||
((MODE) == ADC_Mode_FastInterl) || \
|
||||
((MODE) == ADC_Mode_SlowInterl) || \
|
||||
((MODE) == ADC_Mode_AlterTrig))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
|
||||
|
||||
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
|
||||
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
|
||||
|
||||
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */
|
||||
|
||||
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_None) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_data_align
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
|
||||
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
|
||||
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
|
||||
((ALIGN) == ADC_DataAlign_Left))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_channels
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_Channel_0 ((uint8_t)0x00)
|
||||
#define ADC_Channel_1 ((uint8_t)0x01)
|
||||
#define ADC_Channel_2 ((uint8_t)0x02)
|
||||
#define ADC_Channel_3 ((uint8_t)0x03)
|
||||
#define ADC_Channel_4 ((uint8_t)0x04)
|
||||
#define ADC_Channel_5 ((uint8_t)0x05)
|
||||
#define ADC_Channel_6 ((uint8_t)0x06)
|
||||
#define ADC_Channel_7 ((uint8_t)0x07)
|
||||
#define ADC_Channel_8 ((uint8_t)0x08)
|
||||
#define ADC_Channel_9 ((uint8_t)0x09)
|
||||
#define ADC_Channel_10 ((uint8_t)0x0A)
|
||||
#define ADC_Channel_11 ((uint8_t)0x0B)
|
||||
#define ADC_Channel_12 ((uint8_t)0x0C)
|
||||
#define ADC_Channel_13 ((uint8_t)0x0D)
|
||||
#define ADC_Channel_14 ((uint8_t)0x0E)
|
||||
#define ADC_Channel_15 ((uint8_t)0x0F)
|
||||
#define ADC_Channel_16 ((uint8_t)0x10)
|
||||
#define ADC_Channel_17 ((uint8_t)0x11)
|
||||
|
||||
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
|
||||
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
|
||||
|
||||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
|
||||
((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
|
||||
((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
|
||||
((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
|
||||
((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
|
||||
((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
|
||||
((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
|
||||
((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
|
||||
((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_sampling_time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
|
||||
#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
|
||||
#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
|
||||
#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
|
||||
#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
|
||||
#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
|
||||
#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
|
||||
#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
|
||||
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_7Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_13Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_28Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_41Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_55Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_71Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_239Cycles5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
|
||||
|
||||
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
|
||||
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
|
||||
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
|
||||
|
||||
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */
|
||||
|
||||
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_channel_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
|
||||
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
|
||||
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
|
||||
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
|
||||
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_2) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_3) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_analog_watchdog_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
|
||||
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
|
||||
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
|
||||
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
|
||||
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
|
||||
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
|
||||
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_None))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_IT_EOC ((uint16_t)0x0220)
|
||||
#define ADC_IT_AWD ((uint16_t)0x0140)
|
||||
#define ADC_IT_JEOC ((uint16_t)0x0480)
|
||||
|
||||
#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
|
||||
((IT) == ADC_IT_JEOC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_FLAG_AWD ((uint8_t)0x01)
|
||||
#define ADC_FLAG_EOC ((uint8_t)0x02)
|
||||
#define ADC_FLAG_JEOC ((uint8_t)0x04)
|
||||
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
|
||||
#define ADC_FLAG_STRT ((uint8_t)0x10)
|
||||
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
|
||||
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
|
||||
((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
|
||||
((FLAG) == ADC_FLAG_STRT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_thresholds
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_offset
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_rank
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_regular_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_regular_rank
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_regular_discontinuous_mode_number
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void ADC_DeInit(ADC_TypeDef* ADCx);
|
||||
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
|
||||
void ADC_ResetCalibration(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_StartCalibration(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
|
||||
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
|
||||
uint32_t ADC_GetDualModeConversionValue(void);
|
||||
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
|
||||
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
|
||||
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
|
||||
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
|
||||
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
|
||||
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
|
||||
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
||||
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
|
||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
|
||||
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
|
||||
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
||||
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F10x_ADC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,323 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_bkp.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides all the BKP firmware functions.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_bkp.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BKP
|
||||
* @brief BKP driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ------------ BKP registers bit address in the alias region --------------- */
|
||||
#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CR Register ----*/
|
||||
|
||||
/* Alias word address of TPAL bit */
|
||||
#define CR_OFFSET (BKP_OFFSET + 0x30)
|
||||
#define TPAL_BitNumber 0x01
|
||||
#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
|
||||
|
||||
/* Alias word address of TPE bit */
|
||||
#define TPE_BitNumber 0x00
|
||||
#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
|
||||
|
||||
/* --- CSR Register ---*/
|
||||
|
||||
/* Alias word address of TPIE bit */
|
||||
#define CSR_OFFSET (BKP_OFFSET + 0x34)
|
||||
#define TPIE_BitNumber 0x02
|
||||
#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
|
||||
|
||||
/* Alias word address of TIF bit */
|
||||
#define TIF_BitNumber 0x09
|
||||
#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
|
||||
|
||||
/* Alias word address of TEF bit */
|
||||
#define TEF_BitNumber 0x08
|
||||
#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
|
||||
|
||||
/* ---------------------- BKP registers bit mask ------------------------ */
|
||||
|
||||
/* RTCCR register bit mask */
|
||||
#define RTCCR_CAL_MASK ((uint16_t)0xFF80)
|
||||
#define RTCCR_MASK ((uint16_t)0xFC7F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup BKP_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the BKP peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_DeInit(void)
|
||||
{
|
||||
RCC_BackupResetCmd(ENABLE);
|
||||
RCC_BackupResetCmd(DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the Tamper Pin active level.
|
||||
* @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg BKP_TamperPinLevel_High: Tamper pin active on high level
|
||||
* @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
|
||||
*(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Tamper Pin activation.
|
||||
* @param NewState: new state of the Tamper Pin activation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_TamperPinCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
*(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Tamper Pin Interrupt.
|
||||
* @param NewState: new state of the Tamper Pin Interrupt.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_ITConfig(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
*(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the RTC output source to output on the Tamper pin.
|
||||
* @param BKP_RTCOutputSource: specifies the RTC output source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
|
||||
* @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
|
||||
* divided by 64 on the Tamper pin.
|
||||
* @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
|
||||
* the Tamper pin.
|
||||
* @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
|
||||
* the Tamper pin.
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
|
||||
{
|
||||
uint16_t tmpreg = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
|
||||
tmpreg = BKP->RTCCR;
|
||||
/* Clear CCO, ASOE and ASOS bits */
|
||||
tmpreg &= RTCCR_MASK;
|
||||
|
||||
/* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
|
||||
tmpreg |= BKP_RTCOutputSource;
|
||||
/* Store the new value */
|
||||
BKP->RTCCR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets RTC Clock Calibration value.
|
||||
* @param CalibrationValue: specifies the RTC Clock Calibration value.
|
||||
* This parameter must be a number between 0 and 0x7F.
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
|
||||
{
|
||||
uint16_t tmpreg = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
|
||||
tmpreg = BKP->RTCCR;
|
||||
/* Clear CAL[6:0] bits */
|
||||
tmpreg &= RTCCR_CAL_MASK;
|
||||
/* Set CAL[6:0] bits according to CalibrationValue value */
|
||||
tmpreg |= CalibrationValue;
|
||||
/* Store the new value */
|
||||
BKP->RTCCR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes user data to the specified Data Backup Register.
|
||||
* @param BKP_DR: specifies the Data Backup Register.
|
||||
* This parameter can be BKP_DRx where x:[1, 42]
|
||||
* @param Data: data to write
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_DR(BKP_DR));
|
||||
|
||||
tmp = (uint32_t)BKP_BASE;
|
||||
tmp += BKP_DR;
|
||||
|
||||
*(__IO uint32_t *) tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads data from the specified Data Backup Register.
|
||||
* @param BKP_DR: specifies the Data Backup Register.
|
||||
* This parameter can be BKP_DRx where x:[1, 42]
|
||||
* @retval The content of the specified Data Backup Register
|
||||
*/
|
||||
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_DR(BKP_DR));
|
||||
|
||||
tmp = (uint32_t)BKP_BASE;
|
||||
tmp += BKP_DR;
|
||||
|
||||
return (*(__IO uint16_t *) tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the Tamper Pin Event flag is set or not.
|
||||
* @param None
|
||||
* @retval The new state of the Tamper Pin Event flag (SET or RESET).
|
||||
*/
|
||||
FlagStatus BKP_GetFlagStatus(void)
|
||||
{
|
||||
return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears Tamper Pin Event pending flag.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_ClearFlag(void)
|
||||
{
|
||||
/* Set CTE bit to clear Tamper Pin Event flag */
|
||||
BKP->CSR |= BKP_CSR_CTE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the Tamper Pin Interrupt has occurred or not.
|
||||
* @param None
|
||||
* @retval The new state of the Tamper Pin Interrupt (SET or RESET).
|
||||
*/
|
||||
ITStatus BKP_GetITStatus(void)
|
||||
{
|
||||
return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears Tamper Pin Interrupt pending bit.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_ClearITPendingBit(void)
|
||||
{
|
||||
/* Set CTI bit to clear Tamper Pin Interrupt pending bit */
|
||||
BKP->CSR |= BKP_CSR_CTI;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,210 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_bkp.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the BKP firmware
|
||||
* library.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_BKP_H
|
||||
#define __STM32F10x_BKP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup BKP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup Tamper_Pin_active_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BKP_TamperPinLevel_High ((uint16_t)0x0000)
|
||||
#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
|
||||
#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
|
||||
((LEVEL) == BKP_TamperPinLevel_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BKP_RTCOutputSource_None ((uint16_t)0x0000)
|
||||
#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
|
||||
#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
|
||||
#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
|
||||
#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
|
||||
((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
|
||||
((SOURCE) == BKP_RTCOutputSource_Alarm) || \
|
||||
((SOURCE) == BKP_RTCOutputSource_Second))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Data_Backup_Register
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BKP_DR1 ((uint16_t)0x0004)
|
||||
#define BKP_DR2 ((uint16_t)0x0008)
|
||||
#define BKP_DR3 ((uint16_t)0x000C)
|
||||
#define BKP_DR4 ((uint16_t)0x0010)
|
||||
#define BKP_DR5 ((uint16_t)0x0014)
|
||||
#define BKP_DR6 ((uint16_t)0x0018)
|
||||
#define BKP_DR7 ((uint16_t)0x001C)
|
||||
#define BKP_DR8 ((uint16_t)0x0020)
|
||||
#define BKP_DR9 ((uint16_t)0x0024)
|
||||
#define BKP_DR10 ((uint16_t)0x0028)
|
||||
#define BKP_DR11 ((uint16_t)0x0040)
|
||||
#define BKP_DR12 ((uint16_t)0x0044)
|
||||
#define BKP_DR13 ((uint16_t)0x0048)
|
||||
#define BKP_DR14 ((uint16_t)0x004C)
|
||||
#define BKP_DR15 ((uint16_t)0x0050)
|
||||
#define BKP_DR16 ((uint16_t)0x0054)
|
||||
#define BKP_DR17 ((uint16_t)0x0058)
|
||||
#define BKP_DR18 ((uint16_t)0x005C)
|
||||
#define BKP_DR19 ((uint16_t)0x0060)
|
||||
#define BKP_DR20 ((uint16_t)0x0064)
|
||||
#define BKP_DR21 ((uint16_t)0x0068)
|
||||
#define BKP_DR22 ((uint16_t)0x006C)
|
||||
#define BKP_DR23 ((uint16_t)0x0070)
|
||||
#define BKP_DR24 ((uint16_t)0x0074)
|
||||
#define BKP_DR25 ((uint16_t)0x0078)
|
||||
#define BKP_DR26 ((uint16_t)0x007C)
|
||||
#define BKP_DR27 ((uint16_t)0x0080)
|
||||
#define BKP_DR28 ((uint16_t)0x0084)
|
||||
#define BKP_DR29 ((uint16_t)0x0088)
|
||||
#define BKP_DR30 ((uint16_t)0x008C)
|
||||
#define BKP_DR31 ((uint16_t)0x0090)
|
||||
#define BKP_DR32 ((uint16_t)0x0094)
|
||||
#define BKP_DR33 ((uint16_t)0x0098)
|
||||
#define BKP_DR34 ((uint16_t)0x009C)
|
||||
#define BKP_DR35 ((uint16_t)0x00A0)
|
||||
#define BKP_DR36 ((uint16_t)0x00A4)
|
||||
#define BKP_DR37 ((uint16_t)0x00A8)
|
||||
#define BKP_DR38 ((uint16_t)0x00AC)
|
||||
#define BKP_DR39 ((uint16_t)0x00B0)
|
||||
#define BKP_DR40 ((uint16_t)0x00B4)
|
||||
#define BKP_DR41 ((uint16_t)0x00B8)
|
||||
#define BKP_DR42 ((uint16_t)0x00BC)
|
||||
|
||||
#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \
|
||||
((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \
|
||||
((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \
|
||||
((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
|
||||
((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
|
||||
((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
|
||||
((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
|
||||
((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
|
||||
((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
|
||||
((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
|
||||
((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
|
||||
((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
|
||||
((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
|
||||
((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
|
||||
|
||||
#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void BKP_DeInit(void);
|
||||
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
|
||||
void BKP_TamperPinCmd(FunctionalState NewState);
|
||||
void BKP_ITConfig(FunctionalState NewState);
|
||||
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
|
||||
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
|
||||
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
|
||||
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
|
||||
FlagStatus BKP_GetFlagStatus(void);
|
||||
void BKP_ClearFlag(void);
|
||||
ITStatus BKP_GetITStatus(void);
|
||||
void BKP_ClearITPendingBit(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_BKP_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,712 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_can.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the CAN firmware
|
||||
* library.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_CAN_H
|
||||
#define __STM32F10x_CAN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
|
||||
((PERIPH) == CAN2))
|
||||
|
||||
/**
|
||||
* @brief CAN init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
|
||||
It ranges from 1 to 1024. */
|
||||
|
||||
uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
|
||||
This parameter can be a value of
|
||||
@ref CAN_operating_mode */
|
||||
|
||||
uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
|
||||
the CAN hardware is allowed to lengthen or
|
||||
shorten a bit to perform resynchronization.
|
||||
This parameter can be a value of
|
||||
@ref CAN_synchronisation_jump_width */
|
||||
|
||||
uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
|
||||
Segment 1. This parameter can be a value of
|
||||
@ref CAN_time_quantum_in_bit_segment_1 */
|
||||
|
||||
uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit
|
||||
Segment 2.
|
||||
This parameter can be a value of
|
||||
@ref CAN_time_quantum_in_bit_segment_2 */
|
||||
|
||||
FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered
|
||||
communication mode. This parameter can be set
|
||||
either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off
|
||||
management. This parameter can be set either
|
||||
to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
|
||||
This parameter can be set either to ENABLE or
|
||||
DISABLE. */
|
||||
|
||||
FunctionalState CAN_NART; /*!< Enable or disable the no-automatic
|
||||
retransmission mode. This parameter can be
|
||||
set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
|
||||
This parameter can be set either to ENABLE
|
||||
or DISABLE. */
|
||||
|
||||
FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
|
||||
This parameter can be set either to ENABLE
|
||||
or DISABLE. */
|
||||
} CAN_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN filter init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||
configuration, first one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||
configuration, second one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (MSBs for a 32-bit configuration,
|
||||
first one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (LSBs for a 32-bit configuration,
|
||||
second one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
|
||||
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||
|
||||
uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
|
||||
|
||||
uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
|
||||
This parameter can be a value of @ref CAN_filter_mode */
|
||||
|
||||
uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
|
||||
This parameter can be a value of @ref CAN_filter_scale */
|
||||
|
||||
FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
} CAN_FilterInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Tx message structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||
will be transmitted. This parameter can be a value
|
||||
of @ref CAN_identifier_type */
|
||||
|
||||
uint8_t RTR; /*!< Specifies the type of frame for the message that will
|
||||
be transmitted. This parameter can be a value of
|
||||
@ref CAN_remote_transmission_request */
|
||||
|
||||
uint8_t DLC; /*!< Specifies the length of the frame that will be
|
||||
transmitted. This parameter can be a value between
|
||||
0 to 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
|
||||
to 0xFF. */
|
||||
} CanTxMsg;
|
||||
|
||||
/**
|
||||
* @brief CAN Rx message structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||
will be received. This parameter can be a value of
|
||||
@ref CAN_identifier_type */
|
||||
|
||||
uint8_t RTR; /*!< Specifies the type of frame for the received message.
|
||||
This parameter can be a value of
|
||||
@ref CAN_remote_transmission_request */
|
||||
|
||||
uint8_t DLC; /*!< Specifies the length of the frame that will be received.
|
||||
This parameter can be a value between 0 to 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
|
||||
0xFF. */
|
||||
|
||||
uint8_t FMI; /*!< Specifies the index of the filter the message stored in
|
||||
the mailbox passes through. This parameter can be a
|
||||
value between 0 to 0xFF */
|
||||
} CanRxMsg;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_sleep_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
|
||||
#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
|
||||
#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
|
||||
#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
|
||||
#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
|
||||
|
||||
#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
|
||||
((MODE) == CAN_Mode_LoopBack)|| \
|
||||
((MODE) == CAN_Mode_Silent) || \
|
||||
((MODE) == CAN_Mode_Silent_LoopBack))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Operating_Mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
|
||||
#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
|
||||
#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
|
||||
|
||||
|
||||
#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
|
||||
((MODE) == CAN_OperatingMode_Normal)|| \
|
||||
((MODE) == CAN_OperatingMode_Sleep))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Mode_Status
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
|
||||
#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_synchronisation_jump_width
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
|
||||
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
|
||||
((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
|
||||
#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
|
||||
#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
|
||||
#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
|
||||
#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
|
||||
#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
|
||||
#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
|
||||
#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
|
||||
#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
|
||||
#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
|
||||
#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
|
||||
#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
|
||||
|
||||
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_2
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
|
||||
#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
|
||||
#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
|
||||
#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
|
||||
|
||||
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_clock_prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_number
|
||||
* @{
|
||||
*/
|
||||
#ifndef STM32F10X_CL
|
||||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
|
||||
#else
|
||||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
|
||||
#endif /* STM32F10X_CL */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
|
||||
#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
|
||||
|
||||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
|
||||
((MODE) == CAN_FilterMode_IdList))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_scale
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
|
||||
#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
|
||||
|
||||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
|
||||
((SCALE) == CAN_FilterScale_32bit))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_FIFO
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
|
||||
#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
|
||||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
|
||||
((FIFO) == CAN_FilterFIFO1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Start_bank_filter_for_slave_CAN
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Tx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
|
||||
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
|
||||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
|
||||
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_identifier_type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
|
||||
#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
|
||||
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
|
||||
((IDTYPE) == CAN_Id_Extended))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_remote_transmission_request
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
|
||||
#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
|
||||
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_transmit_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
|
||||
#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
|
||||
#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
|
||||
#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_receive_FIFO_number_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
|
||||
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
|
||||
|
||||
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_sleep_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
|
||||
#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_wake_up_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
|
||||
#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Error_Code_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
|
||||
#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
|
||||
#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
|
||||
#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
|
||||
#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
|
||||
#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
|
||||
#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
|
||||
#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_flags
|
||||
* @{
|
||||
*/
|
||||
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
|
||||
and CAN_ClearFlag() functions. */
|
||||
/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */
|
||||
|
||||
/* Transmit Flags */
|
||||
#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
|
||||
#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
|
||||
#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
|
||||
|
||||
/* Receive Flags */
|
||||
#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
|
||||
#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
|
||||
#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
|
||||
#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
|
||||
#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
|
||||
#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
|
||||
|
||||
/* Operating Mode Flags */
|
||||
#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
|
||||
#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
|
||||
/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
|
||||
In this case the SLAK bit can be polled.*/
|
||||
|
||||
/* Error Flags */
|
||||
#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
|
||||
#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
|
||||
#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
|
||||
#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
|
||||
|
||||
#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
|
||||
((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
|
||||
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
|
||||
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
|
||||
((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
|
||||
((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
|
||||
((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
|
||||
((FLAG) == CAN_FLAG_SLAK ))
|
||||
|
||||
#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
|
||||
((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
|
||||
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
|
||||
((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
|
||||
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
|
||||
|
||||
/* Receive Interrupts */
|
||||
#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
|
||||
#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
|
||||
#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
|
||||
#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
|
||||
#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
|
||||
#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
|
||||
|
||||
/* Operating Mode Interrupts */
|
||||
#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
|
||||
#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
|
||||
|
||||
/* Error Interrupts */
|
||||
#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
|
||||
#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
|
||||
#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
|
||||
#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
|
||||
#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
|
||||
|
||||
/* Flags named as Interrupts : kept only for FW compatibility */
|
||||
#define CAN_IT_RQCP0 CAN_IT_TME
|
||||
#define CAN_IT_RQCP1 CAN_IT_TME
|
||||
#define CAN_IT_RQCP2 CAN_IT_TME
|
||||
|
||||
|
||||
#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
|
||||
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
|
||||
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
|
||||
#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
|
||||
((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Legacy
|
||||
* @{
|
||||
*/
|
||||
#define CANINITFAILED CAN_InitStatus_Failed
|
||||
#define CANINITOK CAN_InitStatus_Success
|
||||
#define CAN_FilterFIFO0 CAN_Filter_FIFO0
|
||||
#define CAN_FilterFIFO1 CAN_Filter_FIFO1
|
||||
#define CAN_ID_STD CAN_Id_Standard
|
||||
#define CAN_ID_EXT CAN_Id_Extended
|
||||
#define CAN_RTR_DATA CAN_RTR_Data
|
||||
#define CAN_RTR_REMOTE CAN_RTR_Remote
|
||||
#define CANTXFAILE CAN_TxStatus_Failed
|
||||
#define CANTXOK CAN_TxStatus_Ok
|
||||
#define CANTXPENDING CAN_TxStatus_Pending
|
||||
#define CAN_NO_MB CAN_TxStatus_NoMailBox
|
||||
#define CANSLEEPFAILED CAN_Sleep_Failed
|
||||
#define CANSLEEPOK CAN_Sleep_Ok
|
||||
#define CANWAKEUPFAILED CAN_WakeUp_Failed
|
||||
#define CANWAKEUPOK CAN_WakeUp_Ok
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/* Function used to set the CAN configuration to the default reset state *****/
|
||||
void CAN_DeInit(CAN_TypeDef* CANx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
|
||||
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
|
||||
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
|
||||
void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
|
||||
void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||
void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||
|
||||
/* Transmit functions *********************************************************/
|
||||
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
|
||||
uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
|
||||
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
|
||||
|
||||
/* Receive functions **********************************************************/
|
||||
void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
|
||||
void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||
|
||||
|
||||
/* Operation modes functions **************************************************/
|
||||
uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
|
||||
uint8_t CAN_Sleep(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
|
||||
|
||||
/* Error management functions *************************************************/
|
||||
uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
|
||||
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_CAN_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,448 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_cec.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides all the CEC firmware functions.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_cec.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC
|
||||
* @brief CEC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ------------ CEC registers bit address in the alias region ----------- */
|
||||
#define CEC_OFFSET (CEC_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CFGR Register ---*/
|
||||
|
||||
/* Alias word address of PE bit */
|
||||
#define CFGR_OFFSET (CEC_OFFSET + 0x00)
|
||||
#define PE_BitNumber 0x00
|
||||
#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
|
||||
|
||||
/* Alias word address of IE bit */
|
||||
#define IE_BitNumber 0x01
|
||||
#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
|
||||
|
||||
/* --- CSR Register ---*/
|
||||
|
||||
/* Alias word address of TSOM bit */
|
||||
#define CSR_OFFSET (CEC_OFFSET + 0x10)
|
||||
#define TSOM_BitNumber 0x00
|
||||
#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
|
||||
|
||||
/* Alias word address of TEOM bit */
|
||||
#define TEOM_BitNumber 0x01
|
||||
#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
|
||||
|
||||
#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */
|
||||
#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the CEC peripheral registers to their default reset
|
||||
* values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_DeInit(void)
|
||||
{
|
||||
/* Enable CEC reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
|
||||
/* Release CEC from reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initializes the CEC peripheral according to the specified
|
||||
* parameters in the CEC_InitStruct.
|
||||
* @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
|
||||
* contains the configuration information for the specified
|
||||
* CEC peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
|
||||
{
|
||||
uint16_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode));
|
||||
assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
|
||||
|
||||
/*---------------------------- CEC CFGR Configuration -----------------*/
|
||||
/* Get the CEC CFGR value */
|
||||
tmpreg = CEC->CFGR;
|
||||
|
||||
/* Clear BTEM and BPEM bits */
|
||||
tmpreg &= CFGR_CLEAR_Mask;
|
||||
|
||||
/* Configure CEC: Bit Timing Error and Bit Period Error */
|
||||
tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
|
||||
|
||||
/* Write to CEC CFGR register*/
|
||||
CEC->CFGR = tmpreg;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified CEC peripheral.
|
||||
* @param NewState: new state of the CEC peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_Cmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
|
||||
|
||||
if(NewState == DISABLE)
|
||||
{
|
||||
/* Wait until the PE bit is cleared by hardware (Idle Line detected) */
|
||||
while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
|
||||
{
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the CEC interrupt.
|
||||
* @param NewState: new state of the CEC interrupt.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_ITConfig(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Defines the Own Address of the CEC device.
|
||||
* @param CEC_OwnAddress: The CEC own address
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
|
||||
|
||||
/* Set the CEC own address */
|
||||
CEC->OAR = CEC_OwnAddress;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the CEC prescaler value.
|
||||
* @param CEC_Prescaler: CEC prescaler new value
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_SetPrescaler(uint16_t CEC_Prescaler)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
|
||||
|
||||
/* Set the Prescaler value*/
|
||||
CEC->PRES = CEC_Prescaler;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Transmits single data through the CEC peripheral.
|
||||
* @param Data: the data to transmit.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_SendDataByte(uint8_t Data)
|
||||
{
|
||||
/* Transmit Data */
|
||||
CEC->TXD = Data ;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Returns the most recent received data by the CEC peripheral.
|
||||
* @param None
|
||||
* @retval The received data.
|
||||
*/
|
||||
uint8_t CEC_ReceiveDataByte(void)
|
||||
{
|
||||
/* Receive Data */
|
||||
return (uint8_t)(CEC->RXD);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts a new message.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_StartOfMessage(void)
|
||||
{
|
||||
/* Starts of new message */
|
||||
*(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Transmits message with or without an EOM bit.
|
||||
* @param NewState: new state of the CEC Tx End Of Message.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_EndOfMessageCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* The data byte will be transmitted with or without an EOM bit*/
|
||||
*(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the CEC flag status
|
||||
* @param CEC_FLAG: specifies the CEC flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_FLAG_BTE: Bit Timing Error
|
||||
* @arg CEC_FLAG_BPE: Bit Period Error
|
||||
* @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
|
||||
* @arg CEC_FLAG_SBE: Start Bit Error
|
||||
* @arg CEC_FLAG_ACKE: Block Acknowledge Error
|
||||
* @arg CEC_FLAG_LINE: Line Error
|
||||
* @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
|
||||
* @arg CEC_FLAG_TEOM: Tx End Of Message
|
||||
* @arg CEC_FLAG_TERR: Tx Error
|
||||
* @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
|
||||
* @arg CEC_FLAG_RSOM: Rx Start Of Message
|
||||
* @arg CEC_FLAG_REOM: Rx End Of Message
|
||||
* @arg CEC_FLAG_RERR: Rx Error
|
||||
* @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
|
||||
* @retval The new state of CEC_FLAG (SET or RESET)
|
||||
*/
|
||||
FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
uint32_t cecreg = 0, cecbase = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
|
||||
|
||||
/* Get the CEC peripheral base address */
|
||||
cecbase = (uint32_t)(CEC_BASE);
|
||||
|
||||
/* Read flag register index */
|
||||
cecreg = CEC_FLAG >> 28;
|
||||
|
||||
/* Get bit[23:0] of the flag */
|
||||
CEC_FLAG &= FLAG_Mask;
|
||||
|
||||
if(cecreg != 0)
|
||||
{
|
||||
/* Flag in CEC ESR Register */
|
||||
CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
|
||||
|
||||
/* Get the CEC ESR register address */
|
||||
cecbase += 0xC;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get the CEC CSR register address */
|
||||
cecbase += 0x10;
|
||||
}
|
||||
|
||||
if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
/* CEC_FLAG is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* CEC_FLAG is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
/* Return the CEC_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the CEC's pending flags.
|
||||
* @param CEC_FLAG: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg CEC_FLAG_TERR: Tx Error
|
||||
* @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
|
||||
* @arg CEC_FLAG_RSOM: Rx Start Of Message
|
||||
* @arg CEC_FLAG_REOM: Rx End Of Message
|
||||
* @arg CEC_FLAG_RERR: Rx Error
|
||||
* @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_ClearFlag(uint32_t CEC_FLAG)
|
||||
{
|
||||
uint32_t tmp = 0x0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
|
||||
|
||||
tmp = CEC->CSR & 0x2;
|
||||
|
||||
/* Clear the selected CEC flags */
|
||||
CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified CEC interrupt has occurred or not.
|
||||
* @param CEC_IT: specifies the CEC interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_TERR: Tx Error
|
||||
* @arg CEC_IT_TBTF: Tx Block Transfer Finished
|
||||
* @arg CEC_IT_RERR: Rx Error
|
||||
* @arg CEC_IT_RBTF: Rx Block Transfer Finished
|
||||
* @retval The new state of CEC_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus CEC_GetITStatus(uint8_t CEC_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_GET_IT(CEC_IT));
|
||||
|
||||
/* Get the CEC IT enable bit status */
|
||||
enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
|
||||
|
||||
/* Check the status of the specified CEC interrupt */
|
||||
if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
|
||||
{
|
||||
/* CEC_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* CEC_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the CEC_IT status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the CEC's interrupt pending bits.
|
||||
* @param CEC_IT: specifies the CEC interrupt pending bit to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg CEC_IT_TERR: Tx Error
|
||||
* @arg CEC_IT_TBTF: Tx Block Transfer Finished
|
||||
* @arg CEC_IT_RERR: Rx Error
|
||||
* @arg CEC_IT_RBTF: Rx Block Transfer Finished
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_ClearITPendingBit(uint16_t CEC_IT)
|
||||
{
|
||||
uint32_t tmp = 0x0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_GET_IT(CEC_IT));
|
||||
|
||||
tmp = CEC->CSR & 0x2;
|
||||
|
||||
/* Clear the selected CEC interrupt pending bits */
|
||||
CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,225 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_cec.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the CEC firmware
|
||||
* library.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_CEC_H
|
||||
#define __STM32F10x_CEC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CEC Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode.
|
||||
This parameter can be a value of @ref CEC_BitTiming_Mode */
|
||||
uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode.
|
||||
This parameter can be a value of @ref CEC_BitPeriod_Mode */
|
||||
}CEC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BitTiming_Mode
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
|
||||
#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
|
||||
|
||||
#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
|
||||
((MODE) == CEC_BitTimingErrFreeMode))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BitPeriod_Mode
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */
|
||||
#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
|
||||
|
||||
#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
|
||||
((MODE) == CEC_BitPeriodFlexibleMode))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IT_TERR CEC_CSR_TERR
|
||||
#define CEC_IT_TBTRF CEC_CSR_TBTRF
|
||||
#define CEC_IT_RERR CEC_CSR_RERR
|
||||
#define CEC_IT_RBTF CEC_CSR_RBTF
|
||||
#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
|
||||
((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Own_Address
|
||||
* @{
|
||||
*/
|
||||
#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ESR register flags
|
||||
*/
|
||||
#define CEC_FLAG_BTE ((uint32_t)0x10010000)
|
||||
#define CEC_FLAG_BPE ((uint32_t)0x10020000)
|
||||
#define CEC_FLAG_RBTFE ((uint32_t)0x10040000)
|
||||
#define CEC_FLAG_SBE ((uint32_t)0x10080000)
|
||||
#define CEC_FLAG_ACKE ((uint32_t)0x10100000)
|
||||
#define CEC_FLAG_LINE ((uint32_t)0x10200000)
|
||||
#define CEC_FLAG_TBTFE ((uint32_t)0x10400000)
|
||||
|
||||
/**
|
||||
* @brief CSR register flags
|
||||
*/
|
||||
#define CEC_FLAG_TEOM ((uint32_t)0x00000002)
|
||||
#define CEC_FLAG_TERR ((uint32_t)0x00000004)
|
||||
#define CEC_FLAG_TBTRF ((uint32_t)0x00000008)
|
||||
#define CEC_FLAG_RSOM ((uint32_t)0x00000010)
|
||||
#define CEC_FLAG_REOM ((uint32_t)0x00000020)
|
||||
#define CEC_FLAG_RERR ((uint32_t)0x00000040)
|
||||
#define CEC_FLAG_RBTF ((uint32_t)0x00000080)
|
||||
|
||||
#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
|
||||
((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
|
||||
((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
|
||||
((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
|
||||
((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
|
||||
((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
|
||||
((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
void CEC_DeInit(void);
|
||||
void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
|
||||
void CEC_Cmd(FunctionalState NewState);
|
||||
void CEC_ITConfig(FunctionalState NewState);
|
||||
void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
|
||||
void CEC_SetPrescaler(uint16_t CEC_Prescaler);
|
||||
void CEC_SendDataByte(uint8_t Data);
|
||||
uint8_t CEC_ReceiveDataByte(void);
|
||||
void CEC_StartOfMessage(void);
|
||||
void CEC_EndOfMessageCmd(FunctionalState NewState);
|
||||
FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
|
||||
void CEC_ClearFlag(uint32_t CEC_FLAG);
|
||||
ITStatus CEC_GetITStatus(uint8_t CEC_IT);
|
||||
void CEC_ClearITPendingBit(uint16_t CEC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_CEC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,92 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief Library configuration file.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_CONF_H
|
||||
#define __STM32F10x_CONF_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
|
||||
#include "stm32f10x_adc.h"
|
||||
#include "stm32f10x_bkp.h"
|
||||
#include "stm32f10x_can.h"
|
||||
#include "stm32f10x_cec.h"
|
||||
#include "stm32f10x_crc.h"
|
||||
#include "stm32f10x_dac.h"
|
||||
#include "stm32f10x_dbgmcu.h"
|
||||
#include "stm32f10x_dma.h"
|
||||
#include "stm32f10x_exti.h"
|
||||
#include "stm32f10x_flash.h"
|
||||
#include "stm32f10x_fsmc.h"
|
||||
#include "stm32f10x_gpio.h"
|
||||
#include "stm32f10x_i2c.h"
|
||||
#include "stm32f10x_iwdg.h"
|
||||
#include "stm32f10x_pwr.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
#include "stm32f10x_rtc.h"
|
||||
#include "stm32f10x_sdio.h"
|
||||
#include "stm32f10x_spi.h"
|
||||
#include "stm32f10x_tim.h"
|
||||
#include "stm32f10x_usart.h"
|
||||
#include "stm32f10x_wwdg.h"
|
||||
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Uncomment the line below to expanse the "assert_param" macro in the
|
||||
Standard Peripheral Library drivers code */
|
||||
/* #define USE_FULL_ASSERT 1 */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function which reports
|
||||
* the name of the source file and the source line number of the call
|
||||
* that failed. If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#endif /* __STM32F10x_CONF_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,175 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_crc.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides all the CRC firmware functions.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_crc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC
|
||||
* @brief CRC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Resets the CRC Data register (DR).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_ResetDR(void)
|
||||
{
|
||||
/* Reset CRC generator */
|
||||
CRC->CR = CRC_CR_RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of a given data word(32-bit).
|
||||
* @param Data: data word(32-bit) to compute its CRC
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_CalcCRC(uint32_t Data)
|
||||
{
|
||||
CRC->DR = Data;
|
||||
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
|
||||
* @param pBuffer: pointer to the buffer containing the data to be computed
|
||||
* @param BufferLength: length of the buffer to be computed
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index = 0;
|
||||
|
||||
for(index = 0; index < BufferLength; index++)
|
||||
{
|
||||
CRC->DR = pBuffer[index];
|
||||
}
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the current CRC value.
|
||||
* @param None
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_GetCRC(void)
|
||||
{
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stores a 8-bit data in the Independent Data(ID) register.
|
||||
* @param IDValue: 8-bit value to be stored in the ID register
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_SetIDRegister(uint8_t IDValue)
|
||||
{
|
||||
CRC->IDR = IDValue;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the 8-bit data stored in the Independent Data(ID) register
|
||||
* @param None
|
||||
* @retval 8-bit value of the ID register
|
||||
*/
|
||||
uint8_t CRC_GetIDRegister(void)
|
||||
{
|
||||
return (CRC->IDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,586 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_dac.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides all the DAC firmware functions.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_dac.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC
|
||||
* @brief DAC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* CR register Mask */
|
||||
#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
|
||||
|
||||
/* DAC Dual Channels SWTRIG masks */
|
||||
#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
|
||||
#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
|
||||
|
||||
/* DHR registers offsets */
|
||||
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
|
||||
#define DHR12R2_OFFSET ((uint32_t)0x00000014)
|
||||
#define DHR12RD_OFFSET ((uint32_t)0x00000020)
|
||||
|
||||
/* DOR register offset */
|
||||
#define DOR_OFFSET ((uint32_t)0x0000002C)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DAC peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DeInit(void)
|
||||
{
|
||||
/* Enable DAC reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
|
||||
/* Release DAC from reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DAC peripheral according to the specified
|
||||
* parameters in the DAC_InitStruct.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
|
||||
* contains the configuration information for the specified DAC channel.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg1 = 0, tmpreg2 = 0;
|
||||
/* Check the DAC parameters */
|
||||
assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
|
||||
assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
|
||||
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
|
||||
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
|
||||
/*---------------------------- DAC CR Configuration --------------------------*/
|
||||
/* Get the DAC CR value */
|
||||
tmpreg1 = DAC->CR;
|
||||
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
|
||||
tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
|
||||
/* Configure for the selected DAC channel: buffer output, trigger, wave generation,
|
||||
mask/amplitude for wave generation */
|
||||
/* Set TSELx and TENx bits according to DAC_Trigger value */
|
||||
/* Set WAVEx bits according to DAC_WaveGeneration value */
|
||||
/* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
|
||||
/* Set BOFFx bit according to DAC_OutputBuffer value */
|
||||
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
|
||||
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
|
||||
/* Calculate CR register value depending on DAC_Channel */
|
||||
tmpreg1 |= tmpreg2 << DAC_Channel;
|
||||
/* Write to DAC CR */
|
||||
DAC->CR = tmpreg1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each DAC_InitStruct member with its default value.
|
||||
* @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
|
||||
{
|
||||
/*--------------- Reset DAC init structure parameters values -----------------*/
|
||||
/* Initialize the DAC_Trigger member */
|
||||
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
|
||||
/* Initialize the DAC_WaveGeneration member */
|
||||
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
|
||||
/* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
|
||||
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
|
||||
/* Initialize the DAC_OutputBuffer member */
|
||||
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC channel.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the DAC channel.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC channel */
|
||||
DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC channel */
|
||||
DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel);
|
||||
}
|
||||
}
|
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC interrupts.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @param NewState: new state of the specified DAC interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC interrupts */
|
||||
DAC->CR |= (DAC_IT << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC interrupts */
|
||||
DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC channel DMA request.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the selected DAC channel DMA request.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC channel DMA request */
|
||||
DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC channel DMA request */
|
||||
DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel software trigger.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the selected DAC channel software trigger.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable software trigger for the selected DAC channel */
|
||||
DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable software trigger for the selected DAC channel */
|
||||
DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables simultaneously the two DAC channels software
|
||||
* triggers.
|
||||
* @param NewState: new state of the DAC channels software triggers.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable software trigger for both DAC channels */
|
||||
DAC->SWTRIGR |= DUAL_SWTRIG_SET ;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable software trigger for both DAC channels */
|
||||
DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel wave generation.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_Wave: Specifies the wave type to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Wave_Noise: noise wave generation
|
||||
* @arg DAC_Wave_Triangle: triangle wave generation
|
||||
* @param NewState: new state of the selected DAC channel wave generation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_WAVE(DAC_Wave));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected wave generation for the selected DAC channel */
|
||||
DAC->CR |= DAC_Wave << DAC_Channel;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected wave generation for the selected DAC channel */
|
||||
DAC->CR &= ~(DAC_Wave << DAC_Channel);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel1.
|
||||
* @param DAC_Align: Specifies the data alignment for DAC channel1.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data : Data to be loaded in the selected data holding register.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data));
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DHR12R1_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the DAC channel1 selected data holding register */
|
||||
*(__IO uint32_t *) tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel2.
|
||||
* @param DAC_Align: Specifies the data alignment for DAC channel2.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data : Data to be loaded in the selected data holding register.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data));
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DHR12R2_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the DAC channel2 selected data holding register */
|
||||
*(__IO uint32_t *)tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for dual channel
|
||||
* DAC.
|
||||
* @param DAC_Align: Specifies the data alignment for dual channel DAC.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data2: Data for DAC Channel2 to be loaded in the selected data
|
||||
* holding register.
|
||||
* @param Data1: Data for DAC Channel1 to be loaded in the selected data
|
||||
* holding register.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
|
||||
{
|
||||
uint32_t data = 0, tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data1));
|
||||
assert_param(IS_DAC_DATA(Data2));
|
||||
|
||||
/* Calculate and set dual DAC data holding register value */
|
||||
if (DAC_Align == DAC_Align_8b_R)
|
||||
{
|
||||
data = ((uint32_t)Data2 << 8) | Data1;
|
||||
}
|
||||
else
|
||||
{
|
||||
data = ((uint32_t)Data2 << 16) | Data1;
|
||||
}
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DHR12RD_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the dual DAC selected data holding register */
|
||||
*(__IO uint32_t *)tmp = data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
|
||||
tmp = (uint32_t) DAC_BASE ;
|
||||
tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
return (uint16_t) (*(__IO uint32_t*) tmp);
|
||||
}
|
||||
|
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||
/**
|
||||
* @brief Checks whether the specified DAC flag is set or not.
|
||||
* @param DAC_Channel: thee selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_FLAG: specifies the flag to check.
|
||||
* This parameter can be only of the following value:
|
||||
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
||||
* @retval The new state of DAC_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
||||
|
||||
/* Check the status of the specified DAC flag */
|
||||
if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
|
||||
{
|
||||
/* DAC_FLAG is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DAC_FLAG is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DAC_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DAC channelx's pending flags.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_FLAG: specifies the flag to clear.
|
||||
* This parameter can be of the following value:
|
||||
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
||||
|
||||
/* Clear the selected DAC flags */
|
||||
DAC->SR = (DAC_FLAG << DAC_Channel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DAC interrupt has occurred or not.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt source to check.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @retval The new state of DAC_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
/* Get the DAC_IT enable bit status */
|
||||
enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
|
||||
|
||||
/* Check the status of the specified DAC interrupt */
|
||||
if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
|
||||
{
|
||||
/* DAC_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DAC_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DAC_IT status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DAC channelx's interrupt pending bits.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt pending bit to clear.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
/* Clear the selected DAC interrupt pending bits */
|
||||
DAC->SR = (DAC_IT << DAC_Channel);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,332 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the DAC firmware
|
||||
* library.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_DAC_H
|
||||
#define __STM32F10x_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DAC Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
|
||||
uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
|
||||
are generated, or whether no wave is generated.
|
||||
This parameter can be a value of @ref DAC_wave_generation */
|
||||
|
||||
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
|
||||
the maximum amplitude triangle generation for the DAC channel.
|
||||
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
|
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
}DAC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_trigger_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
|
||||
only in High-density devices*/
|
||||
#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
|
||||
only in Connectivity line, Medium-density and Low-density Value Line devices */
|
||||
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
|
||||
only in Medium-density and Low-density Value Line devices*/
|
||||
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
|
||||
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T5_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
|
||||
((TRIGGER) == DAC_Trigger_Software))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
|
||||
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
|
||||
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
|
||||
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
|
||||
((WAVE) == DAC_WaveGeneration_Noise) || \
|
||||
((WAVE) == DAC_WaveGeneration_Triangle))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_lfsrunmask_triangleamplitude
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
|
||||
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_3) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_7) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_15) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_31) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_63) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_127) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_255) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_511) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1023) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_2047) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_4095))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_output_buffer
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
|
||||
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
|
||||
((STATE) == DAC_OutputBuffer_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Channel_1 ((uint32_t)0x00000000)
|
||||
#define DAC_Channel_2 ((uint32_t)0x00000010)
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
|
||||
((CHANNEL) == DAC_Channel_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignment
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Align_12b_R ((uint32_t)0x00000000)
|
||||
#define DAC_Align_12b_L ((uint32_t)0x00000004)
|
||||
#define DAC_Align_8b_R ((uint32_t)0x00000008)
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
|
||||
((ALIGN) == DAC_Align_12b_L) || \
|
||||
((ALIGN) == DAC_Align_8b_R))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Wave_Noise ((uint32_t)0x00000040)
|
||||
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
|
||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
|
||||
((WAVE) == DAC_Wave_Triangle))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||
/** @defgroup DAC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
|
||||
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
|
||||
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void DAC_DeInit(void);
|
||||
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
|
||||
#endif
|
||||
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
|
||||
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
|
||||
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
|
||||
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
|
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F10x_DAC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,177 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_dbgmcu.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides all the DBGMCU firmware functions.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_dbgmcu.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU
|
||||
* @brief DBGMCU driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the device revision identifier.
|
||||
* @param None
|
||||
* @retval Device revision identifier
|
||||
*/
|
||||
uint32_t DBGMCU_GetREVID(void)
|
||||
{
|
||||
return(DBGMCU->IDCODE >> 16);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device identifier.
|
||||
* @param None
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t DBGMCU_GetDEVID(void)
|
||||
{
|
||||
return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the specified peripheral and low power mode behavior
|
||||
* when the MCU under Debug mode.
|
||||
* @param DBGMCU_Periph: specifies the peripheral and low power mode.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
|
||||
* @arg DBGMCU_STOP: Keep debugger connection during STOP mode
|
||||
* @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
|
||||
* @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
|
||||
* @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
|
||||
* @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
|
||||
* @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
|
||||
* @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
|
||||
* @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
|
||||
* @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
|
||||
* @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
|
||||
* @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
|
||||
* @param NewState: new state of the specified peripheral in Debug mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
DBGMCU->CR |= DBGMCU_Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
DBGMCU->CR &= ~DBGMCU_Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,134 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_dbgmcu.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the DBGMCU
|
||||
* firmware library.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_DBGMCU_H
|
||||
#define __STM32F10x_DBGMCU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DBGMCU
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
|
||||
#define DBGMCU_STOP ((uint32_t)0x00000002)
|
||||
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
|
||||
#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
|
||||
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
|
||||
#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)
|
||||
#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)
|
||||
#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)
|
||||
#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)
|
||||
#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)
|
||||
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
|
||||
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
|
||||
#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)
|
||||
#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)
|
||||
#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
|
||||
#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
|
||||
#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
|
||||
#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000)
|
||||
#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000)
|
||||
#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000)
|
||||
#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000)
|
||||
#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000)
|
||||
#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000)
|
||||
#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000)
|
||||
#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000)
|
||||
#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000)
|
||||
|
||||
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t DBGMCU_GetREVID(void);
|
||||
uint32_t DBGMCU_GetDEVID(void);
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_DBGMCU_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,729 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_dma.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides all the DMA firmware functions.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_dma.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA
|
||||
* @brief DMA driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* DMA1 Channelx interrupt pending bit masks */
|
||||
#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
|
||||
#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
|
||||
#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
|
||||
#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
|
||||
#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
|
||||
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
|
||||
#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
|
||||
|
||||
/* DMA2 Channelx interrupt pending bit masks */
|
||||
#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
|
||||
#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
|
||||
#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
|
||||
#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
|
||||
#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
|
||||
|
||||
/* DMA2 FLAG mask */
|
||||
#define FLAG_Mask ((uint32_t)0x10000000)
|
||||
|
||||
/* DMA registers Masks */
|
||||
#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DMAy Channelx registers to their default reset
|
||||
* values.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
|
||||
/* Disable the selected DMAy Channelx */
|
||||
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
|
||||
|
||||
/* Reset DMAy Channelx control register */
|
||||
DMAy_Channelx->CCR = 0;
|
||||
|
||||
/* Reset DMAy Channelx remaining bytes register */
|
||||
DMAy_Channelx->CNDTR = 0;
|
||||
|
||||
/* Reset DMAy Channelx peripheral address register */
|
||||
DMAy_Channelx->CPAR = 0;
|
||||
|
||||
/* Reset DMAy Channelx memory address register */
|
||||
DMAy_Channelx->CMAR = 0;
|
||||
|
||||
if (DMAy_Channelx == DMA1_Channel1)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel1 */
|
||||
DMA1->IFCR |= DMA1_Channel1_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel2)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel2 */
|
||||
DMA1->IFCR |= DMA1_Channel2_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel3)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel3 */
|
||||
DMA1->IFCR |= DMA1_Channel3_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel4)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel4 */
|
||||
DMA1->IFCR |= DMA1_Channel4_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel5)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel5 */
|
||||
DMA1->IFCR |= DMA1_Channel5_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel6)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel6 */
|
||||
DMA1->IFCR |= DMA1_Channel6_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel7)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel7 */
|
||||
DMA1->IFCR |= DMA1_Channel7_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel1)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel1 */
|
||||
DMA2->IFCR |= DMA2_Channel1_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel2)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel2 */
|
||||
DMA2->IFCR |= DMA2_Channel2_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel3)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel3 */
|
||||
DMA2->IFCR |= DMA2_Channel3_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel4)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel4 */
|
||||
DMA2->IFCR |= DMA2_Channel4_IT_Mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (DMAy_Channelx == DMA2_Channel5)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel5 */
|
||||
DMA2->IFCR |= DMA2_Channel5_IT_Mask;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DMAy Channelx according to the specified
|
||||
* parameters in the DMA_InitStruct.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
|
||||
* contains the configuration information for the specified DMA Channel.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
|
||||
assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
|
||||
assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
|
||||
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
|
||||
assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
|
||||
assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
|
||||
assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
|
||||
assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
|
||||
|
||||
/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
|
||||
/* Get the DMAy_Channelx CCR value */
|
||||
tmpreg = DMAy_Channelx->CCR;
|
||||
/* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
|
||||
tmpreg &= CCR_CLEAR_Mask;
|
||||
/* Configure DMAy Channelx: data transfer, data size, priority level and mode */
|
||||
/* Set DIR bit according to DMA_DIR value */
|
||||
/* Set CIRC bit according to DMA_Mode value */
|
||||
/* Set PINC bit according to DMA_PeripheralInc value */
|
||||
/* Set MINC bit according to DMA_MemoryInc value */
|
||||
/* Set PSIZE bits according to DMA_PeripheralDataSize value */
|
||||
/* Set MSIZE bits according to DMA_MemoryDataSize value */
|
||||
/* Set PL bits according to DMA_Priority value */
|
||||
/* Set the MEM2MEM bit according to DMA_M2M value */
|
||||
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
|
||||
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
|
||||
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
|
||||
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
|
||||
|
||||
/* Write to DMAy Channelx CCR */
|
||||
DMAy_Channelx->CCR = tmpreg;
|
||||
|
||||
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
|
||||
/* Write to DMAy Channelx CNDTR */
|
||||
DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
|
||||
|
||||
/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
|
||||
/* Write to DMAy Channelx CPAR */
|
||||
DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
|
||||
|
||||
/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
|
||||
/* Write to DMAy Channelx CMAR */
|
||||
DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each DMA_InitStruct member with its default value.
|
||||
* @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
|
||||
{
|
||||
/*-------------- Reset DMA init structure parameters values ------------------*/
|
||||
/* Initialize the DMA_PeripheralBaseAddr member */
|
||||
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
|
||||
/* Initialize the DMA_MemoryBaseAddr member */
|
||||
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
|
||||
/* Initialize the DMA_DIR member */
|
||||
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
|
||||
/* Initialize the DMA_BufferSize member */
|
||||
DMA_InitStruct->DMA_BufferSize = 0;
|
||||
/* Initialize the DMA_PeripheralInc member */
|
||||
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
/* Initialize the DMA_MemoryInc member */
|
||||
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
|
||||
/* Initialize the DMA_PeripheralDataSize member */
|
||||
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
/* Initialize the DMA_MemoryDataSize member */
|
||||
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||
/* Initialize the DMA_Mode member */
|
||||
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
|
||||
/* Initialize the DMA_Priority member */
|
||||
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
|
||||
/* Initialize the DMA_M2M member */
|
||||
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DMAy Channelx.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param NewState: new state of the DMAy Channelx.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DMAy Channelx */
|
||||
DMAy_Channelx->CCR |= DMA_CCR1_EN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DMAy Channelx */
|
||||
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DMAy Channelx interrupts.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param DMA_IT: specifies the DMA interrupts sources to be enabled
|
||||
* or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @param NewState: new state of the specified DMA interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
assert_param(IS_DMA_CONFIG_IT(DMA_IT));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DMA interrupts */
|
||||
DMAy_Channelx->CCR |= DMA_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DMA interrupts */
|
||||
DMAy_Channelx->CCR &= ~DMA_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the number of data units in the current DMAy Channelx transfer.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param DataNumber: The number of data units in the current DMAy Channelx
|
||||
* transfer.
|
||||
* @note This function can only be used when the DMAy_Channelx is disabled.
|
||||
* @retval None.
|
||||
*/
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
|
||||
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
|
||||
/* Write to DMAy Channelx CNDTR */
|
||||
DMAy_Channelx->CNDTR = DataNumber;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the number of remaining data units in the current
|
||||
* DMAy Channelx transfer.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @retval The number of remaining data units in the current DMAy Channelx
|
||||
* transfer.
|
||||
*/
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
/* Return the number of remaining data units for DMAy Channelx */
|
||||
return ((uint16_t)(DMAy_Channelx->CNDTR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMAy Channelx flag is set or not.
|
||||
* @param DMAy_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
|
||||
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
|
||||
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
|
||||
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
|
||||
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
|
||||
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
|
||||
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
|
||||
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
|
||||
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
|
||||
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
|
||||
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
|
||||
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
|
||||
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
|
||||
* @retval The new state of DMAy_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
|
||||
|
||||
/* Calculate the used DMAy */
|
||||
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
/* Get DMA2 ISR register value */
|
||||
tmpreg = DMA2->ISR ;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get DMA1 ISR register value */
|
||||
tmpreg = DMA1->ISR ;
|
||||
}
|
||||
|
||||
/* Check the status of the specified DMAy flag */
|
||||
if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
/* DMAy_FLAG is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DMAy_FLAG is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
/* Return the DMAy_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DMAy Channelx's pending flags.
|
||||
* @param DMAy_FLAG: specifies the flag to clear.
|
||||
* This parameter can be any combination (for the same DMA) of the following values:
|
||||
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
|
||||
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
|
||||
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
|
||||
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
|
||||
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
|
||||
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
|
||||
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
|
||||
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
|
||||
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
|
||||
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
|
||||
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
|
||||
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
|
||||
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ClearFlag(uint32_t DMAy_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
|
||||
|
||||
/* Calculate the used DMAy */
|
||||
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
/* Clear the selected DMAy flags */
|
||||
DMA2->IFCR = DMAy_FLAG;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the selected DMAy flags */
|
||||
DMA1->IFCR = DMAy_FLAG;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
|
||||
* @param DMAy_IT: specifies the DMAy interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
||||
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
||||
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
||||
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
||||
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
||||
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
|
||||
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
|
||||
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
|
||||
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
|
||||
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
|
||||
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
|
||||
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
|
||||
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
|
||||
* @retval The new state of DMAy_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_GET_IT(DMAy_IT));
|
||||
|
||||
/* Calculate the used DMA */
|
||||
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
/* Get DMA2 ISR register value */
|
||||
tmpreg = DMA2->ISR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get DMA1 ISR register value */
|
||||
tmpreg = DMA1->ISR;
|
||||
}
|
||||
|
||||
/* Check the status of the specified DMAy interrupt */
|
||||
if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
|
||||
{
|
||||
/* DMAy_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DMAy_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DMA_IT status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DMAy Channelx's interrupt pending bits.
|
||||
* @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
|
||||
* This parameter can be any combination (for the same DMA) of the following values:
|
||||
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
||||
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
||||
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
||||
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
||||
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
||||
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
|
||||
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
|
||||
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
|
||||
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
|
||||
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
|
||||
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
|
||||
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
|
||||
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
|
||||
|
||||
/* Calculate the used DMAy */
|
||||
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
/* Clear the selected DMAy interrupt pending bits */
|
||||
DMA2->IFCR = DMAy_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the selected DMAy interrupt pending bits */
|
||||
DMA1->IFCR = DMAy_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,454 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_dma.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the DMA firmware
|
||||
* library.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_DMA_H
|
||||
#define __STM32F10x_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
|
||||
This parameter can be a value of @ref DMA_data_transfer_direction */
|
||||
|
||||
uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
|
||||
The data unit is equal to the configuration set in DMA_PeripheralDataSize
|
||||
or DMA_MemoryDataSize members depending in the transfer direction. */
|
||||
|
||||
uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
|
||||
|
||||
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_memory_incremented_mode */
|
||||
|
||||
uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_peripheral_data_size */
|
||||
|
||||
uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_memory_data_size */
|
||||
|
||||
uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_circular_normal_mode.
|
||||
@note: The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_priority_level */
|
||||
|
||||
uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
|
||||
This parameter can be a value of @ref DMA_memory_to_memory */
|
||||
}DMA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
|
||||
((PERIPH) == DMA1_Channel2) || \
|
||||
((PERIPH) == DMA1_Channel3) || \
|
||||
((PERIPH) == DMA1_Channel4) || \
|
||||
((PERIPH) == DMA1_Channel5) || \
|
||||
((PERIPH) == DMA1_Channel6) || \
|
||||
((PERIPH) == DMA1_Channel7) || \
|
||||
((PERIPH) == DMA2_Channel1) || \
|
||||
((PERIPH) == DMA2_Channel2) || \
|
||||
((PERIPH) == DMA2_Channel3) || \
|
||||
((PERIPH) == DMA2_Channel4) || \
|
||||
((PERIPH) == DMA2_Channel5))
|
||||
|
||||
/** @defgroup DMA_data_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
|
||||
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
|
||||
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
|
||||
((DIR) == DMA_DIR_PeripheralSRC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_peripheral_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
|
||||
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
|
||||
((STATE) == DMA_PeripheralInc_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
|
||||
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
|
||||
((STATE) == DMA_MemoryInc_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_peripheral_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
|
||||
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_Word))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
|
||||
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
|
||||
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_MemoryDataSize_Word))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_circular_normal_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_Mode_Circular ((uint32_t)0x00000020)
|
||||
#define DMA_Mode_Normal ((uint32_t)0x00000000)
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_priority_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
|
||||
#define DMA_Priority_High ((uint32_t)0x00002000)
|
||||
#define DMA_Priority_Medium ((uint32_t)0x00001000)
|
||||
#define DMA_Priority_Low ((uint32_t)0x00000000)
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
|
||||
((PRIORITY) == DMA_Priority_High) || \
|
||||
((PRIORITY) == DMA_Priority_Medium) || \
|
||||
((PRIORITY) == DMA_Priority_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_to_memory
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_M2M_Enable ((uint32_t)0x00004000)
|
||||
#define DMA_M2M_Disable ((uint32_t)0x00000000)
|
||||
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_IT_TC ((uint32_t)0x00000002)
|
||||
#define DMA_IT_HT ((uint32_t)0x00000004)
|
||||
#define DMA_IT_TE ((uint32_t)0x00000008)
|
||||
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
|
||||
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
|
||||
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
|
||||
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
|
||||
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
|
||||
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
|
||||
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
|
||||
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
|
||||
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
|
||||
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
|
||||
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
|
||||
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
|
||||
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
|
||||
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
|
||||
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
|
||||
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
|
||||
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
|
||||
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
|
||||
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
|
||||
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
|
||||
|
||||
#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
|
||||
((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
|
||||
((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
|
||||
((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
|
||||
((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
|
||||
((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
|
||||
((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
|
||||
((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
|
||||
((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
|
||||
((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
|
||||
((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
|
||||
((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
|
||||
((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
|
||||
((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
|
||||
((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
|
||||
((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
|
||||
((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
|
||||
((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
|
||||
((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
|
||||
((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
|
||||
((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
|
||||
((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
|
||||
((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
|
||||
((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flags_definition
|
||||
* @{
|
||||
*/
|
||||
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
|
||||
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
|
||||
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
|
||||
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
|
||||
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
|
||||
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
|
||||
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
|
||||
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
|
||||
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
|
||||
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
|
||||
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
|
||||
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
|
||||
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
|
||||
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
|
||||
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
|
||||
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
|
||||
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
|
||||
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
|
||||
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
|
||||
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
|
||||
|
||||
#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
|
||||
((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
|
||||
((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
|
||||
((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
|
||||
((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
|
||||
((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
|
||||
((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
|
||||
((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
|
||||
((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
|
||||
((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
|
||||
((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
|
||||
((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
|
||||
((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
|
||||
((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
|
||||
((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
|
||||
((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
|
||||
((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
|
||||
((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
|
||||
((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
|
||||
((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
|
||||
((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
|
||||
((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
|
||||
((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
|
||||
((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Buffer_Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
|
||||
void DMA_ClearFlag(uint32_t DMAy_FLAG);
|
||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
|
||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F10x_DMA_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,284 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_exti.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides all the EXTI firmware functions.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_exti.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI
|
||||
* @brief EXTI driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the EXTI peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_DeInit(void)
|
||||
{
|
||||
EXTI->IMR = 0x00000000;
|
||||
EXTI->EMR = 0x00000000;
|
||||
EXTI->RTSR = 0x00000000;
|
||||
EXTI->FTSR = 0x00000000;
|
||||
EXTI->PR = 0x000FFFFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the EXTI peripheral according to the specified
|
||||
* parameters in the EXTI_InitStruct.
|
||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
|
||||
* that contains the configuration information for the EXTI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
|
||||
assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
|
||||
assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
|
||||
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
|
||||
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
|
||||
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
|
||||
{
|
||||
/* Clear EXTI line configuration */
|
||||
EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
|
||||
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
/* Select the trigger for the selected external interrupts */
|
||||
if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
|
||||
{
|
||||
/* Rising Falling edge */
|
||||
EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
tmp += EXTI_InitStruct->EXTI_Trigger;
|
||||
|
||||
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
|
||||
/* Disable the selected external lines */
|
||||
*(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each EXTI_InitStruct member with its reset value.
|
||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
|
||||
{
|
||||
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
|
||||
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
|
||||
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
|
||||
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt.
|
||||
* @param EXTI_Line: specifies the EXTI lines to be enabled or disabled.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->SWIER |= EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||
* @param EXTI_Line: specifies the EXTI line flag to check.
|
||||
* This parameter can be:
|
||||
* @arg EXTI_Linex: External interrupt line x where x(0..19)
|
||||
* @retval The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||
|
||||
if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending flags.
|
||||
* @param EXTI_Line: specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->PR = EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||
* @param EXTI_Line: specifies the EXTI line to check.
|
||||
* This parameter can be:
|
||||
* @arg EXTI_Linex: External interrupt line x where x(0..19)
|
||||
* @retval The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||
|
||||
enablestatus = EXTI->IMR & EXTI_Line;
|
||||
if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending bits.
|
||||
* @param EXTI_Line: specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->PR = EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,199 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_exti.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the EXTI firmware
|
||||
* library.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_EXTI_H
|
||||
#define __STM32F10x_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief EXTI mode enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Mode_Interrupt = 0x00,
|
||||
EXTI_Mode_Event = 0x04
|
||||
}EXTIMode_TypeDef;
|
||||
|
||||
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
|
||||
|
||||
/**
|
||||
* @brief EXTI Trigger enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Trigger_Rising = 0x08,
|
||||
EXTI_Trigger_Falling = 0x0C,
|
||||
EXTI_Trigger_Rising_Falling = 0x10
|
||||
}EXTITrigger_TypeDef;
|
||||
|
||||
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
|
||||
((TRIGGER) == EXTI_Trigger_Falling) || \
|
||||
((TRIGGER) == EXTI_Trigger_Rising_Falling))
|
||||
/**
|
||||
* @brief EXTI Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
|
||||
This parameter can be any combination of @ref EXTI_Lines */
|
||||
|
||||
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||
|
||||
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTITrigger_TypeDef */
|
||||
|
||||
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
}EXTI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Lines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
|
||||
#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
|
||||
#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
|
||||
#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
|
||||
#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
|
||||
#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
|
||||
#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
|
||||
#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
|
||||
#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
|
||||
#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
|
||||
#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
|
||||
#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
|
||||
#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
|
||||
#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
|
||||
#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
|
||||
#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
|
||||
#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
|
||||
#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||
#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
|
||||
Wakeup from suspend event */
|
||||
#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
|
||||
|
||||
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
|
||||
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
|
||||
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
|
||||
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
|
||||
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
|
||||
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
|
||||
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
|
||||
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
|
||||
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
|
||||
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
|
||||
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void EXTI_DeInit(void);
|
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line);
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_EXTI_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,441 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_flash.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the FLASH
|
||||
* firmware library.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_FLASH_H
|
||||
#define __STM32F10x_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Status
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
FLASH_BUSY = 1,
|
||||
FLASH_ERROR_PG,
|
||||
FLASH_ERROR_WRP,
|
||||
FLASH_COMPLETE,
|
||||
FLASH_TIMEOUT
|
||||
}FLASH_Status;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup Flash_Latency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
|
||||
#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
|
||||
((LATENCY) == FLASH_Latency_1) || \
|
||||
((LATENCY) == FLASH_Latency_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Half_Cycle_Enable_Disable
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */
|
||||
#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */
|
||||
#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
|
||||
((STATE) == FLASH_HalfCycleAccess_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Prefetch_Buffer_Enable_Disable
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
|
||||
#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
|
||||
#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
|
||||
((STATE) == FLASH_PrefetchBuffer_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_Write_Protection
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Values to be used with STM32 Low and Medium density devices */
|
||||
#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */
|
||||
#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */
|
||||
#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */
|
||||
#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */
|
||||
#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */
|
||||
#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */
|
||||
#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */
|
||||
#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */
|
||||
|
||||
/* Values to be used with STM32 Medium-density devices */
|
||||
#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */
|
||||
#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */
|
||||
#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */
|
||||
#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */
|
||||
#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */
|
||||
#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */
|
||||
#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */
|
||||
#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */
|
||||
#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */
|
||||
#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */
|
||||
#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */
|
||||
#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */
|
||||
#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */
|
||||
#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */
|
||||
#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */
|
||||
#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */
|
||||
#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */
|
||||
#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */
|
||||
#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */
|
||||
#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */
|
||||
#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */
|
||||
#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */
|
||||
#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */
|
||||
#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */
|
||||
|
||||
/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */
|
||||
#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 0 to 1 */
|
||||
#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 2 to 3 */
|
||||
#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 4 to 5 */
|
||||
#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 6 to 7 */
|
||||
#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 8 to 9 */
|
||||
#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 10 to 11 */
|
||||
#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 12 to 13 */
|
||||
#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 14 to 15 */
|
||||
#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 16 to 17 */
|
||||
#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 18 to 19 */
|
||||
#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 20 to 21 */
|
||||
#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 22 to 23 */
|
||||
#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 24 to 25 */
|
||||
#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 26 to 27 */
|
||||
#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 28 to 29 */
|
||||
#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 30 to 31 */
|
||||
#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 32 to 33 */
|
||||
#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 34 to 35 */
|
||||
#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 36 to 37 */
|
||||
#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 38 to 39 */
|
||||
#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 40 to 41 */
|
||||
#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 42 to 43 */
|
||||
#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 44 to 45 */
|
||||
#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 46 to 47 */
|
||||
#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 48 to 49 */
|
||||
#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 50 to 51 */
|
||||
#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 52 to 53 */
|
||||
#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 54 to 55 */
|
||||
#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 56 to 57 */
|
||||
#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 58 to 59 */
|
||||
#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 60 to 61 */
|
||||
#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */
|
||||
#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */
|
||||
#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */
|
||||
|
||||
#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
|
||||
|
||||
#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
|
||||
|
||||
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))
|
||||
|
||||
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_IWatchdog
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_nRST_STOP
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_nRST_STDBY
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
|
||||
|
||||
#ifdef STM32F10X_XL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup FLASH_Boot
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position
|
||||
and this parameter is selected the device will boot from Bank1(Default) */
|
||||
#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position
|
||||
and this parameter is selected the device will boot from Bank 2 or Bank 1,
|
||||
depending on the activation of the bank */
|
||||
#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2))
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup FLASH_Interrupts
|
||||
* @{
|
||||
*/
|
||||
#ifdef STM32F10X_XL
|
||||
#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */
|
||||
#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */
|
||||
|
||||
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */
|
||||
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */
|
||||
|
||||
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */
|
||||
#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */
|
||||
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
|
||||
#else
|
||||
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */
|
||||
#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
|
||||
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */
|
||||
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */
|
||||
|
||||
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flags
|
||||
* @{
|
||||
*/
|
||||
#ifdef STM32F10X_XL
|
||||
#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */
|
||||
#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */
|
||||
#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */
|
||||
#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */
|
||||
|
||||
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
|
||||
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */
|
||||
#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */
|
||||
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */
|
||||
|
||||
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
|
||||
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
|
||||
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
|
||||
|
||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
|
||||
((FLAG) == FLASH_FLAG_OPTERR)|| \
|
||||
((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
|
||||
((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR))
|
||||
#else
|
||||
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
|
||||
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
|
||||
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
|
||||
|
||||
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
|
||||
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */
|
||||
#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */
|
||||
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */
|
||||
|
||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
|
||||
((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
|
||||
((FLAG) == FLASH_FLAG_OPTERR))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*------------ Functions used for all STM32F10x devices -----*/
|
||||
void FLASH_SetLatency(uint32_t FLASH_Latency);
|
||||
void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
|
||||
void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
|
||||
void FLASH_Unlock(void);
|
||||
void FLASH_Lock(void);
|
||||
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
|
||||
FLASH_Status FLASH_EraseAllPages(void);
|
||||
FLASH_Status FLASH_EraseOptionBytes(void);
|
||||
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
|
||||
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
|
||||
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
|
||||
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
|
||||
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
|
||||
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
|
||||
uint32_t FLASH_GetUserOptionByte(void);
|
||||
uint32_t FLASH_GetWriteProtectionOptionByte(void);
|
||||
FlagStatus FLASH_GetReadOutProtectionStatus(void);
|
||||
FlagStatus FLASH_GetPrefetchBufferStatus(void);
|
||||
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
|
||||
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
|
||||
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
|
||||
FLASH_Status FLASH_GetStatus(void);
|
||||
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
|
||||
/*------------ New function used for all STM32F10x devices -----*/
|
||||
void FLASH_UnlockBank1(void);
|
||||
void FLASH_LockBank1(void);
|
||||
FLASH_Status FLASH_EraseAllBank1Pages(void);
|
||||
FLASH_Status FLASH_GetBank1Status(void);
|
||||
FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
|
||||
|
||||
#ifdef STM32F10X_XL
|
||||
/*---- New Functions used only with STM32F10x_XL density devices -----*/
|
||||
void FLASH_UnlockBank2(void);
|
||||
void FLASH_LockBank2(void);
|
||||
FLASH_Status FLASH_EraseAllBank2Pages(void);
|
||||
FLASH_Status FLASH_GetBank2Status(void);
|
||||
FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout);
|
||||
FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_FLASH_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,881 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_fsmc.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides all the FSMC firmware functions.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_fsmc.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC
|
||||
* @brief FSMC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* --------------------- FSMC registers bit mask ---------------------------- */
|
||||
|
||||
/* FSMC BCRx Mask */
|
||||
#define BCR_MBKEN_Set ((uint32_t)0x00000001)
|
||||
#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
|
||||
#define BCR_FACCEN_Set ((uint32_t)0x00000040)
|
||||
|
||||
/* FSMC PCRx Mask */
|
||||
#define PCR_PBKEN_Set ((uint32_t)0x00000004)
|
||||
#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
|
||||
#define PCR_ECCEN_Set ((uint32_t)0x00000040)
|
||||
#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
|
||||
#define PCR_MemoryType_NAND ((uint32_t)0x00000008)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
|
||||
* reset values.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
|
||||
* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
|
||||
* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
|
||||
* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
|
||||
|
||||
/* FSMC_Bank1_NORSRAM1 */
|
||||
if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
|
||||
{
|
||||
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
|
||||
}
|
||||
/* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
|
||||
else
|
||||
{
|
||||
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
|
||||
}
|
||||
FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
|
||||
FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the FSMC NAND Banks registers to their default reset values.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NANDDeInit(uint32_t FSMC_Bank)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
|
||||
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
/* Set the FSMC_Bank2 registers to their reset values */
|
||||
FSMC_Bank2->PCR2 = 0x00000018;
|
||||
FSMC_Bank2->SR2 = 0x00000040;
|
||||
FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
|
||||
FSMC_Bank2->PATT2 = 0xFCFCFCFC;
|
||||
}
|
||||
/* FSMC_Bank3_NAND */
|
||||
else
|
||||
{
|
||||
/* Set the FSMC_Bank3 registers to their reset values */
|
||||
FSMC_Bank3->PCR3 = 0x00000018;
|
||||
FSMC_Bank3->SR3 = 0x00000040;
|
||||
FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
|
||||
FSMC_Bank3->PATT3 = 0xFCFCFCFC;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_PCCARDDeInit(void)
|
||||
{
|
||||
/* Set the FSMC_Bank4 registers to their reset values */
|
||||
FSMC_Bank4->PCR4 = 0x00000018;
|
||||
FSMC_Bank4->SR4 = 0x00000000;
|
||||
FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
|
||||
FSMC_Bank4->PATT4 = 0xFCFCFCFC;
|
||||
FSMC_Bank4->PIO4 = 0xFCFCFCFC;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the FSMC NOR/SRAM Banks according to the specified
|
||||
* parameters in the FSMC_NORSRAMInitStruct.
|
||||
* @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
|
||||
* structure that contains the configuration information for
|
||||
* the FSMC NOR/SRAM specified Banks.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
|
||||
assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
|
||||
assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
|
||||
assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
|
||||
assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
|
||||
assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
|
||||
assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
|
||||
assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
|
||||
assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
|
||||
assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
|
||||
assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
|
||||
assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
|
||||
assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
|
||||
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
|
||||
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
|
||||
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
|
||||
assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
|
||||
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
|
||||
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
|
||||
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
|
||||
|
||||
/* Bank1 NOR/SRAM control register configuration */
|
||||
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
|
||||
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
|
||||
FSMC_NORSRAMInitStruct->FSMC_MemoryType |
|
||||
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
|
||||
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
|
||||
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WrapMode |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
|
||||
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
|
||||
|
||||
if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
|
||||
{
|
||||
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
|
||||
}
|
||||
|
||||
/* Bank1 NOR/SRAM timing register configuration */
|
||||
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
|
||||
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
|
||||
|
||||
|
||||
/* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
|
||||
if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
|
||||
{
|
||||
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
|
||||
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
|
||||
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
|
||||
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
|
||||
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
|
||||
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
|
||||
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
|
||||
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
|
||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
|
||||
}
|
||||
else
|
||||
{
|
||||
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the FSMC NAND Banks according to the specified
|
||||
* parameters in the FSMC_NANDInitStruct.
|
||||
* @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
|
||||
* structure that contains the configuration information for the FSMC
|
||||
* NAND specified Banks.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
|
||||
{
|
||||
uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
|
||||
assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
|
||||
assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
|
||||
assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
|
||||
assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
|
||||
assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
|
||||
assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
|
||||
assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
|
||||
assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||
assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||
assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||
assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
|
||||
assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||
assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||
assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||
|
||||
/* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
|
||||
tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
|
||||
PCR_MemoryType_NAND |
|
||||
FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
|
||||
FSMC_NANDInitStruct->FSMC_ECC |
|
||||
FSMC_NANDInitStruct->FSMC_ECCPageSize |
|
||||
(FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
|
||||
(FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
|
||||
|
||||
/* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
|
||||
tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
|
||||
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||
|
||||
/* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
|
||||
tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
|
||||
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||
|
||||
if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
/* FSMC_Bank2_NAND registers configuration */
|
||||
FSMC_Bank2->PCR2 = tmppcr;
|
||||
FSMC_Bank2->PMEM2 = tmppmem;
|
||||
FSMC_Bank2->PATT2 = tmppatt;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* FSMC_Bank3_NAND registers configuration */
|
||||
FSMC_Bank3->PCR3 = tmppcr;
|
||||
FSMC_Bank3->PMEM3 = tmppmem;
|
||||
FSMC_Bank3->PATT3 = tmppatt;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the FSMC PCCARD Bank according to the specified
|
||||
* parameters in the FSMC_PCCARDInitStruct.
|
||||
* @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
|
||||
* structure that contains the configuration information for the FSMC
|
||||
* PCCARD Bank.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
|
||||
assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
|
||||
assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
|
||||
|
||||
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
|
||||
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||
|
||||
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
|
||||
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
|
||||
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||
|
||||
/* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
|
||||
FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
|
||||
FSMC_MemoryDataWidth_16b |
|
||||
(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
|
||||
(FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
|
||||
|
||||
/* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
|
||||
FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
|
||||
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||
|
||||
/* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
|
||||
FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
|
||||
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||
|
||||
/* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
|
||||
FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
|
||||
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
|
||||
* @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
|
||||
* structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
|
||||
{
|
||||
/* Reset NOR/SRAM Init structure parameters values */
|
||||
FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
|
||||
FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
|
||||
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
|
||||
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each FSMC_NANDInitStruct member with its default value.
|
||||
* @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef
|
||||
* structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
|
||||
{
|
||||
/* Reset NAND Init structure parameters values */
|
||||
FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
|
||||
FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
|
||||
FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
|
||||
FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
|
||||
FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
|
||||
FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
|
||||
FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
|
||||
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each FSMC_PCCARDInitStruct member with its default value.
|
||||
* @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
|
||||
* structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
|
||||
{
|
||||
/* Reset PCCARD Init structure parameters values */
|
||||
FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
|
||||
FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
|
||||
FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
|
||||
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified NOR/SRAM Memory Bank.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
|
||||
* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
|
||||
* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
|
||||
* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
|
||||
* @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
|
||||
FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
|
||||
FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified NAND Memory Bank.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
|
||||
}
|
||||
else
|
||||
{
|
||||
FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the PCCARD Memory Bank.
|
||||
* @param NewState: new state of the PCCARD Memory Bank.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_PCCARDCmd(FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
|
||||
FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
|
||||
FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the FSMC NAND ECC feature.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @param NewState: new state of the FSMC NAND ECC feature.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
|
||||
}
|
||||
else
|
||||
{
|
||||
FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the error correction code register value.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @retval The Error Correction Code (ECC) value.
|
||||
*/
|
||||
uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
|
||||
{
|
||||
uint32_t eccval = 0x00000000;
|
||||
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
/* Get the ECCR2 register value */
|
||||
eccval = FSMC_Bank2->ECCR2;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get the ECCR3 register value */
|
||||
eccval = FSMC_Bank3->ECCR3;
|
||||
}
|
||||
/* Return the error correction code value */
|
||||
return(eccval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified FSMC interrupts.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||
* @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
|
||||
* @arg FSMC_IT_Level: Level edge detection interrupt.
|
||||
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
|
||||
* @param NewState: new state of the specified FSMC interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
|
||||
assert_param(IS_FSMC_IT(FSMC_IT));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected FSMC_Bank2 interrupts */
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->SR2 |= FSMC_IT;
|
||||
}
|
||||
/* Enable the selected FSMC_Bank3 interrupts */
|
||||
else if (FSMC_Bank == FSMC_Bank3_NAND)
|
||||
{
|
||||
FSMC_Bank3->SR3 |= FSMC_IT;
|
||||
}
|
||||
/* Enable the selected FSMC_Bank4 interrupts */
|
||||
else
|
||||
{
|
||||
FSMC_Bank4->SR4 |= FSMC_IT;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected FSMC_Bank2 interrupts */
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
|
||||
FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
|
||||
}
|
||||
/* Disable the selected FSMC_Bank3 interrupts */
|
||||
else if (FSMC_Bank == FSMC_Bank3_NAND)
|
||||
{
|
||||
FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
|
||||
}
|
||||
/* Disable the selected FSMC_Bank4 interrupts */
|
||||
else
|
||||
{
|
||||
FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified FSMC flag is set or not.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||
* @param FSMC_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
|
||||
* @arg FSMC_FLAG_Level: Level detection Flag.
|
||||
* @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
|
||||
* @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
|
||||
* @retval The new state of FSMC_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
uint32_t tmpsr = 0x00000000;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
|
||||
assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
|
||||
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
tmpsr = FSMC_Bank2->SR2;
|
||||
}
|
||||
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
||||
{
|
||||
tmpsr = FSMC_Bank3->SR3;
|
||||
}
|
||||
/* FSMC_Bank4_PCCARD*/
|
||||
else
|
||||
{
|
||||
tmpsr = FSMC_Bank4->SR4;
|
||||
}
|
||||
|
||||
/* Get the flag status */
|
||||
if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the FSMC's pending flags.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||
* @param FSMC_FLAG: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
|
||||
* @arg FSMC_FLAG_Level: Level detection Flag.
|
||||
* @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
|
||||
assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
|
||||
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->SR2 &= ~FSMC_FLAG;
|
||||
}
|
||||
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
||||
{
|
||||
FSMC_Bank3->SR3 &= ~FSMC_FLAG;
|
||||
}
|
||||
/* FSMC_Bank4_PCCARD*/
|
||||
else
|
||||
{
|
||||
FSMC_Bank4->SR4 &= ~FSMC_FLAG;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified FSMC interrupt has occurred or not.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||
* @param FSMC_IT: specifies the FSMC interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
|
||||
* @arg FSMC_IT_Level: Level edge detection interrupt.
|
||||
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
|
||||
* @retval The new state of FSMC_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
|
||||
assert_param(IS_FSMC_GET_IT(FSMC_IT));
|
||||
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
tmpsr = FSMC_Bank2->SR2;
|
||||
}
|
||||
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
||||
{
|
||||
tmpsr = FSMC_Bank3->SR3;
|
||||
}
|
||||
/* FSMC_Bank4_PCCARD*/
|
||||
else
|
||||
{
|
||||
tmpsr = FSMC_Bank4->SR4;
|
||||
}
|
||||
|
||||
itstatus = tmpsr & FSMC_IT;
|
||||
|
||||
itenable = tmpsr & (FSMC_IT >> 3);
|
||||
if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the FSMC's interrupt pending bits.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||
* @param FSMC_IT: specifies the interrupt pending bit to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
|
||||
* @arg FSMC_IT_Level: Level edge detection interrupt.
|
||||
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
|
||||
assert_param(IS_FSMC_IT(FSMC_IT));
|
||||
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
|
||||
}
|
||||
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
||||
{
|
||||
FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
|
||||
}
|
||||
/* FSMC_Bank4_PCCARD*/
|
||||
else
|
||||
{
|
||||
FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,748 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_fsmc.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the FSMC firmware
|
||||
* library.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_FSMC_H
|
||||
#define __STM32F10x_FSMC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FSMC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Timing parameters For NOR/SRAM Banks
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address setup time.
|
||||
This parameter can be a value between 0 and 0xF.
|
||||
@note: It is not used with synchronous NOR Flash memories. */
|
||||
|
||||
uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address hold time.
|
||||
This parameter can be a value between 0 and 0xF.
|
||||
@note: It is not used with synchronous NOR Flash memories.*/
|
||||
|
||||
uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the data setup time.
|
||||
This parameter can be a value between 0 and 0xFF.
|
||||
@note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
|
||||
|
||||
uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the bus turnaround.
|
||||
This parameter can be a value between 0 and 0xF.
|
||||
@note: It is only used for multiplexed NOR Flash memories. */
|
||||
|
||||
uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
|
||||
This parameter can be a value between 1 and 0xF.
|
||||
@note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
|
||||
|
||||
uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
|
||||
to the memory before getting the first data.
|
||||
The value of this parameter depends on the memory type as shown below:
|
||||
- It must be set to 0 in case of a CRAM
|
||||
- It is don't care in asynchronous NOR, SRAM or ROM accesses
|
||||
- It may assume a value between 0 and 0xF in NOR Flash memories
|
||||
with synchronous burst mode enable */
|
||||
|
||||
uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
|
||||
This parameter can be a value of @ref FSMC_Access_Mode */
|
||||
}FSMC_NORSRAMTimingInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC NOR/SRAM Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
|
||||
This parameter can be a value of @ref FSMC_NORSRAM_Bank */
|
||||
|
||||
uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
|
||||
multiplexed on the databus or not.
|
||||
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
|
||||
|
||||
uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
|
||||
the corresponding memory bank.
|
||||
This parameter can be a value of @ref FSMC_Memory_Type */
|
||||
|
||||
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be a value of @ref FSMC_Data_Width */
|
||||
|
||||
uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
|
||||
valid only with synchronous burst Flash memories.
|
||||
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
|
||||
|
||||
uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
|
||||
valid only with asynchronous Flash memories.
|
||||
This parameter can be a value of @ref FSMC_AsynchronousWait */
|
||||
|
||||
uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
|
||||
the Flash memory in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
|
||||
|
||||
uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
|
||||
memory, valid only when accessing Flash memories in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wrap_Mode */
|
||||
|
||||
uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
|
||||
clock cycle before the wait state or during the wait state,
|
||||
valid only when accessing memories in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Timing */
|
||||
|
||||
uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
|
||||
This parameter can be a value of @ref FSMC_Write_Operation */
|
||||
|
||||
uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
|
||||
signal, valid for Flash memory access in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Signal */
|
||||
|
||||
uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
|
||||
This parameter can be a value of @ref FSMC_Extended_Mode */
|
||||
|
||||
uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
|
||||
This parameter can be a value of @ref FSMC_Write_Burst */
|
||||
|
||||
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
|
||||
|
||||
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
|
||||
}FSMC_NORSRAMInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Timing parameters For FSMC NAND and PCCARD Banks
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
|
||||
the command assertion for NAND-Flash read or write access
|
||||
to common/Attribute or I/O memory space (depending on
|
||||
the memory space timing to be configured).
|
||||
This parameter can be a value between 0 and 0xFF.*/
|
||||
|
||||
uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
|
||||
command for NAND-Flash read or write access to
|
||||
common/Attribute or I/O memory space (depending on the
|
||||
memory space timing to be configured).
|
||||
This parameter can be a number between 0x00 and 0xFF */
|
||||
|
||||
uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
|
||||
(and data for write access) after the command deassertion
|
||||
for NAND-Flash read or write access to common/Attribute
|
||||
or I/O memory space (depending on the memory space timing
|
||||
to be configured).
|
||||
This parameter can be a number between 0x00 and 0xFF */
|
||||
|
||||
uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
|
||||
databus is kept in HiZ after the start of a NAND-Flash
|
||||
write access to common/Attribute or I/O memory space (depending
|
||||
on the memory space timing to be configured).
|
||||
This parameter can be a number between 0x00 and 0xFF */
|
||||
}FSMC_NAND_PCCARDTimingInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC NAND Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
|
||||
This parameter can be a value of @ref FSMC_NAND_Bank */
|
||||
|
||||
uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
|
||||
This parameter can be any value of @ref FSMC_Wait_feature */
|
||||
|
||||
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be any value of @ref FSMC_Data_Width */
|
||||
|
||||
uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
|
||||
This parameter can be any value of @ref FSMC_ECC */
|
||||
|
||||
uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
|
||||
This parameter can be any value of @ref FSMC_ECC_Page_Size */
|
||||
|
||||
uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low.
|
||||
This parameter can be a value between 0 and 0xFF. */
|
||||
|
||||
uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low.
|
||||
This parameter can be a number between 0x0 and 0xFF */
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
|
||||
}FSMC_NANDInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC PCCARD Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
|
||||
This parameter can be any value of @ref FSMC_Wait_feature */
|
||||
|
||||
uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low.
|
||||
This parameter can be a value between 0 and 0xFF. */
|
||||
|
||||
uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low.
|
||||
This parameter can be a number between 0x0 and 0xFF */
|
||||
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
|
||||
}FSMC_PCCARDInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_NORSRAM_Bank
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
|
||||
#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
|
||||
#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
|
||||
#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_NAND_Bank
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
|
||||
#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_PCCARD_Bank
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
|
||||
((BANK) == FSMC_Bank1_NORSRAM2) || \
|
||||
((BANK) == FSMC_Bank1_NORSRAM3) || \
|
||||
((BANK) == FSMC_Bank1_NORSRAM4))
|
||||
|
||||
#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
|
||||
((BANK) == FSMC_Bank3_NAND))
|
||||
|
||||
#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
|
||||
((BANK) == FSMC_Bank3_NAND) || \
|
||||
((BANK) == FSMC_Bank4_PCCARD))
|
||||
|
||||
#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
|
||||
((BANK) == FSMC_Bank3_NAND) || \
|
||||
((BANK) == FSMC_Bank4_PCCARD))
|
||||
|
||||
/** @defgroup NOR_SRAM_Controller
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Address_Bus_Multiplexing
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
|
||||
#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
|
||||
((MUX) == FSMC_DataAddressMux_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Memory_Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
|
||||
#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
|
||||
#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
|
||||
#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
|
||||
((MEMORY) == FSMC_MemoryType_PSRAM)|| \
|
||||
((MEMORY) == FSMC_MemoryType_NOR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Width
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
|
||||
#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
|
||||
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
|
||||
((WIDTH) == FSMC_MemoryDataWidth_16b))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Burst_Access_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
|
||||
#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
|
||||
((STATE) == FSMC_BurstAccessMode_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_AsynchronousWait
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
|
||||
#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
|
||||
((STATE) == FSMC_AsynchronousWait_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Signal_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
|
||||
#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
|
||||
#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
|
||||
((POLARITY) == FSMC_WaitSignalPolarity_High))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wrap_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
|
||||
#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
|
||||
((MODE) == FSMC_WrapMode_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Timing
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
|
||||
#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
|
||||
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
|
||||
((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Write_Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
|
||||
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
|
||||
((OPERATION) == FSMC_WriteOperation_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Signal
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
|
||||
#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
|
||||
((SIGNAL) == FSMC_WaitSignal_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Extended_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
|
||||
|
||||
#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
|
||||
((MODE) == FSMC_ExtendedMode_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Write_Burst
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
|
||||
#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
|
||||
((BURST) == FSMC_WriteBurst_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Address_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Address_Hold_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Bus_Turn_around_Duration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_CLK_Division
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Latency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Access_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_AccessMode_A ((uint32_t)0x00000000)
|
||||
#define FSMC_AccessMode_B ((uint32_t)0x10000000)
|
||||
#define FSMC_AccessMode_C ((uint32_t)0x20000000)
|
||||
#define FSMC_AccessMode_D ((uint32_t)0x30000000)
|
||||
#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
|
||||
((MODE) == FSMC_AccessMode_B) || \
|
||||
((MODE) == FSMC_AccessMode_C) || \
|
||||
((MODE) == FSMC_AccessMode_D))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup NAND_PCCARD_Controller
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_feature
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
|
||||
#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
|
||||
((FEATURE) == FSMC_Waitfeature_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FSMC_ECC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_ECC_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_ECC_Enable ((uint32_t)0x00000040)
|
||||
#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
|
||||
((STATE) == FSMC_ECC_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_ECC_Page_Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
|
||||
#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
|
||||
#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
|
||||
#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
|
||||
#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
|
||||
#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
|
||||
#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_512Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_8192Bytes))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_TCLR_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_TAR_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Hold_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_HiZ_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Interrupt_sources
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
|
||||
#define FSMC_IT_Level ((uint32_t)0x00000010)
|
||||
#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
|
||||
#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
|
||||
#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
|
||||
((IT) == FSMC_IT_Level) || \
|
||||
((IT) == FSMC_IT_FallingEdge))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
|
||||
#define FSMC_FLAG_Level ((uint32_t)0x00000002)
|
||||
#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
|
||||
#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
|
||||
#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
|
||||
((FLAG) == FSMC_FLAG_Level) || \
|
||||
((FLAG) == FSMC_FLAG_FallingEdge) || \
|
||||
((FLAG) == FSMC_FLAG_FEMPT))
|
||||
|
||||
#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
|
||||
void FSMC_NANDDeInit(uint32_t FSMC_Bank);
|
||||
void FSMC_PCCARDDeInit(void);
|
||||
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
|
||||
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
|
||||
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
|
||||
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
|
||||
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
|
||||
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
|
||||
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||
void FSMC_PCCARDCmd(FunctionalState NewState);
|
||||
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||
uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
|
||||
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
|
||||
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
|
||||
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
|
||||
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
|
||||
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F10x_FSMC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,665 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides all the GPIO firmware functions.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_gpio.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO
|
||||
* @brief GPIO driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ------------ RCC registers bit address in the alias region ----------------*/
|
||||
#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- EVENTCR Register -----*/
|
||||
|
||||
/* Alias word address of EVOE bit */
|
||||
#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
|
||||
#define EVOE_BitNumber ((uint8_t)0x07)
|
||||
#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
|
||||
|
||||
|
||||
/* --- MAPR Register ---*/
|
||||
/* Alias word address of MII_RMII_SEL bit */
|
||||
#define MAPR_OFFSET (AFIO_OFFSET + 0x04)
|
||||
#define MII_RMII_SEL_BitNumber ((u8)0x17)
|
||||
#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
|
||||
|
||||
|
||||
#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
|
||||
#define LSB_MASK ((uint16_t)0xFFFF)
|
||||
#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
|
||||
#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
|
||||
#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
|
||||
#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the GPIOx peripheral registers to their default reset values.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
if (GPIOx == GPIOA)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOB)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOC)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOD)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOE)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOF)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (GPIOx == GPIOG)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the Alternate Functions (remap, event control
|
||||
* and EXTI configuration) registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_AFIODeInit(void)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified
|
||||
* parameters in the GPIO_InitStruct.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
|
||||
* contains the configuration information for the specified GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
|
||||
uint32_t tmpreg = 0x00, pinmask = 0x00;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
|
||||
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
|
||||
|
||||
/*---------------------------- GPIO Mode Configuration -----------------------*/
|
||||
currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
|
||||
if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
|
||||
/* Output mode */
|
||||
currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
|
||||
}
|
||||
/*---------------------------- GPIO CRL Configuration ------------------------*/
|
||||
/* Configure the eight low port pins */
|
||||
if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
|
||||
{
|
||||
tmpreg = GPIOx->CRL;
|
||||
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||
{
|
||||
pos = ((uint32_t)0x01) << pinpos;
|
||||
/* Get the port pins position */
|
||||
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
|
||||
if (currentpin == pos)
|
||||
{
|
||||
pos = pinpos << 2;
|
||||
/* Clear the corresponding low control register bits */
|
||||
pinmask = ((uint32_t)0x0F) << pos;
|
||||
tmpreg &= ~pinmask;
|
||||
/* Write the mode configuration in the corresponding bits */
|
||||
tmpreg |= (currentmode << pos);
|
||||
/* Reset the corresponding ODR bit */
|
||||
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||
{
|
||||
GPIOx->BRR = (((uint32_t)0x01) << pinpos);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the corresponding ODR bit */
|
||||
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||
{
|
||||
GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
GPIOx->CRL = tmpreg;
|
||||
}
|
||||
/*---------------------------- GPIO CRH Configuration ------------------------*/
|
||||
/* Configure the eight high port pins */
|
||||
if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
|
||||
{
|
||||
tmpreg = GPIOx->CRH;
|
||||
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||
{
|
||||
pos = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
/* Get the port pins position */
|
||||
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
|
||||
if (currentpin == pos)
|
||||
{
|
||||
pos = pinpos << 2;
|
||||
/* Clear the corresponding high control register bits */
|
||||
pinmask = ((uint32_t)0x0F) << pos;
|
||||
tmpreg &= ~pinmask;
|
||||
/* Write the mode configuration in the corresponding bits */
|
||||
tmpreg |= (currentmode << pos);
|
||||
/* Reset the corresponding ODR bit */
|
||||
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||
{
|
||||
GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
}
|
||||
/* Set the corresponding ODR bit */
|
||||
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||
{
|
||||
GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
}
|
||||
}
|
||||
}
|
||||
GPIOx->CRH = tmpreg;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each GPIO_InitStruct member with its default value.
|
||||
* @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
/* Reset GPIO init structure parameters values */
|
||||
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
|
||||
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO input data port.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @retval GPIO input data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->IDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified output data port bit.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
* @retval The output port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO output data port.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @retval GPIO output data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->ODR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the selected data port bits.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BSRR = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the selected data port bits.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BRR = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
|
||||
* @param BitVal: specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the BitAction enum values:
|
||||
* @arg Bit_RESET: to clear the port pin
|
||||
* @arg Bit_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_BIT_ACTION(BitVal));
|
||||
|
||||
if (BitVal != Bit_RESET)
|
||||
{
|
||||
GPIOx->BSRR = GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BRR = GPIO_Pin;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes data to the specified GPIO data port.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param PortVal: specifies the value to be written to the port output data register.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
GPIOx->ODR = PortVal;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint32_t tmp = 0x00010000;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
tmp |= GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKK bit */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the GPIO pin used as Event output.
|
||||
* @param GPIO_PortSource: selects the GPIO port to be used as source
|
||||
* for Event output.
|
||||
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
|
||||
* @param GPIO_PinSource: specifies the pin for the Event output.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
|
||||
{
|
||||
uint32_t tmpreg = 0x00;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
|
||||
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
|
||||
|
||||
tmpreg = AFIO->EVCR;
|
||||
/* Clear the PORT[6:4] and PIN[3:0] bits */
|
||||
tmpreg &= EVCR_PORTPINCONFIG_MASK;
|
||||
tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
|
||||
tmpreg |= GPIO_PinSource;
|
||||
AFIO->EVCR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Event Output.
|
||||
* @param NewState: new state of the Event output.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_EventOutputCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Changes the mapping of the specified pin.
|
||||
* @param GPIO_Remap: selects the pin to remap.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping
|
||||
* @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping
|
||||
* @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping
|
||||
* @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping
|
||||
* @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping
|
||||
* @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping
|
||||
* @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping
|
||||
* @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping
|
||||
* @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping
|
||||
* @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping
|
||||
* @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping
|
||||
* @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping
|
||||
* @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping
|
||||
* @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping
|
||||
* @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping
|
||||
* @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping
|
||||
* @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping
|
||||
* @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration
|
||||
* @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping
|
||||
* @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping
|
||||
* @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping
|
||||
* @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping
|
||||
* @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices)
|
||||
* @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices)
|
||||
* @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
|
||||
* @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled
|
||||
* @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP)
|
||||
* @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices)
|
||||
* When the SPI3/I2S3 is remapped using this function, the SWJ is configured
|
||||
* to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST.
|
||||
* @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected
|
||||
* to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices)
|
||||
* If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to
|
||||
* Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.
|
||||
* @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)
|
||||
* @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices)
|
||||
* @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices)
|
||||
* @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices)
|
||||
* @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices)
|
||||
* @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices)
|
||||
* @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices)
|
||||
* @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices)
|
||||
* @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices)
|
||||
* @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)
|
||||
* @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)
|
||||
* @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)
|
||||
* @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)
|
||||
* @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices)
|
||||
* @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
|
||||
* only for High density Value line devices)
|
||||
* @param NewState: new state of the port pin remapping.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
|
||||
{
|
||||
uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_REMAP(GPIO_Remap));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if((GPIO_Remap & 0x80000000) == 0x80000000)
|
||||
{
|
||||
tmpreg = AFIO->MAPR2;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmpreg = AFIO->MAPR;
|
||||
}
|
||||
|
||||
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
|
||||
tmp = GPIO_Remap & LSB_MASK;
|
||||
|
||||
if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
|
||||
{
|
||||
tmpreg &= DBGAFR_SWJCFG_MASK;
|
||||
AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
|
||||
}
|
||||
else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
|
||||
{
|
||||
tmp1 = ((uint32_t)0x03) << tmpmask;
|
||||
tmpreg &= ~tmp1;
|
||||
tmpreg |= ~DBGAFR_SWJCFG_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
|
||||
tmpreg |= ~DBGAFR_SWJCFG_MASK;
|
||||
}
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
|
||||
}
|
||||
|
||||
if((GPIO_Remap & 0x80000000) == 0x80000000)
|
||||
{
|
||||
AFIO->MAPR2 = tmpreg;
|
||||
}
|
||||
else
|
||||
{
|
||||
AFIO->MAPR = tmpreg;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the GPIO pin used as EXTI Line.
|
||||
* @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
|
||||
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
|
||||
* @param GPIO_PinSource: specifies the EXTI line to be configured.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
|
||||
{
|
||||
uint32_t tmp = 0x00;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
|
||||
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
|
||||
|
||||
tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
|
||||
AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
|
||||
AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the Ethernet media interface.
|
||||
* @note This function applies only to STM32 Connectivity line devices.
|
||||
* @param GPIO_ETH_MediaInterface: specifies the Media Interface mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_ETH_MediaInterface_MII: MII mode
|
||||
* @arg GPIO_ETH_MediaInterface_RMII: RMII mode
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
|
||||
{
|
||||
assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface));
|
||||
|
||||
/* Configure MII_RMII selection bit */
|
||||
*(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,400 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the GPIO
|
||||
* firmware library.
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_GPIO_H
|
||||
#define __STM32F10x_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
|
||||
((PERIPH) == GPIOB) || \
|
||||
((PERIPH) == GPIOC) || \
|
||||
((PERIPH) == GPIOD) || \
|
||||
((PERIPH) == GPIOE) || \
|
||||
((PERIPH) == GPIOF) || \
|
||||
((PERIPH) == GPIOG))
|
||||
|
||||
/**
|
||||
* @brief Output Maximum frequency selection
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Speed_10MHz = 1,
|
||||
GPIO_Speed_2MHz,
|
||||
GPIO_Speed_50MHz
|
||||
}GPIOSpeed_TypeDef;
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
|
||||
((SPEED) == GPIO_Speed_50MHz))
|
||||
|
||||
/**
|
||||
* @brief Configuration Mode enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{ GPIO_Mode_AIN = 0x0,
|
||||
GPIO_Mode_IN_FLOATING = 0x04,
|
||||
GPIO_Mode_IPD = 0x28,
|
||||
GPIO_Mode_IPU = 0x48,
|
||||
GPIO_Mode_Out_OD = 0x14,
|
||||
GPIO_Mode_Out_PP = 0x10,
|
||||
GPIO_Mode_AF_OD = 0x1C,
|
||||
GPIO_Mode_AF_PP = 0x18
|
||||
}GPIOMode_TypeDef;
|
||||
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
|
||||
((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
|
||||
((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
|
||||
((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIOSpeed_TypeDef */
|
||||
|
||||
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIOMode_TypeDef */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Bit_SET and Bit_RESET enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{ Bit_RESET = 0,
|
||||
Bit_SET
|
||||
}BitAction;
|
||||
|
||||
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
|
||||
#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
|
||||
#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
|
||||
#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
|
||||
#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
|
||||
#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
|
||||
#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
|
||||
#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
|
||||
#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
|
||||
#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
|
||||
#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
|
||||
#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
|
||||
#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
|
||||
#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
|
||||
#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
|
||||
#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
|
||||
#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
|
||||
|
||||
#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
|
||||
|
||||
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
|
||||
((PIN) == GPIO_Pin_1) || \
|
||||
((PIN) == GPIO_Pin_2) || \
|
||||
((PIN) == GPIO_Pin_3) || \
|
||||
((PIN) == GPIO_Pin_4) || \
|
||||
((PIN) == GPIO_Pin_5) || \
|
||||
((PIN) == GPIO_Pin_6) || \
|
||||
((PIN) == GPIO_Pin_7) || \
|
||||
((PIN) == GPIO_Pin_8) || \
|
||||
((PIN) == GPIO_Pin_9) || \
|
||||
((PIN) == GPIO_Pin_10) || \
|
||||
((PIN) == GPIO_Pin_11) || \
|
||||
((PIN) == GPIO_Pin_12) || \
|
||||
((PIN) == GPIO_Pin_13) || \
|
||||
((PIN) == GPIO_Pin_14) || \
|
||||
((PIN) == GPIO_Pin_15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Remap_define
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */
|
||||
#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */
|
||||
#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */
|
||||
#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */
|
||||
#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */
|
||||
#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */
|
||||
#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */
|
||||
#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */
|
||||
#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */
|
||||
#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */
|
||||
#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */
|
||||
#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */
|
||||
#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */
|
||||
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */
|
||||
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */
|
||||
#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */
|
||||
#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */
|
||||
#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */
|
||||
#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */
|
||||
#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
|
||||
#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */
|
||||
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
|
||||
#define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
|
||||
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected
|
||||
to TIM2 Internal Trigger 1 for calibration
|
||||
(only for Connectivity line devices) */
|
||||
#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
|
||||
|
||||
#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */
|
||||
#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */
|
||||
#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */
|
||||
#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */
|
||||
#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */
|
||||
|
||||
#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */
|
||||
#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */
|
||||
#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */
|
||||
#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */
|
||||
#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */
|
||||
#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */
|
||||
|
||||
#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */
|
||||
#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */
|
||||
#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
|
||||
only for High density Value line devices) */
|
||||
|
||||
#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
|
||||
((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
|
||||
((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
|
||||
((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
|
||||
((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
|
||||
((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
|
||||
((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
|
||||
((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
|
||||
((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
|
||||
((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
|
||||
((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
|
||||
((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \
|
||||
((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \
|
||||
((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \
|
||||
((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \
|
||||
((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \
|
||||
((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \
|
||||
((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \
|
||||
((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \
|
||||
((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \
|
||||
((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \
|
||||
((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Port_Sources
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
|
||||
#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
|
||||
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
|
||||
#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
|
||||
#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
|
||||
#define GPIO_PortSourceGPIOF ((uint8_t)0x05)
|
||||
#define GPIO_PortSourceGPIOG ((uint8_t)0x06)
|
||||
#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOE))
|
||||
|
||||
#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOG))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Pin_sources
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_PinSource0 ((uint8_t)0x00)
|
||||
#define GPIO_PinSource1 ((uint8_t)0x01)
|
||||
#define GPIO_PinSource2 ((uint8_t)0x02)
|
||||
#define GPIO_PinSource3 ((uint8_t)0x03)
|
||||
#define GPIO_PinSource4 ((uint8_t)0x04)
|
||||
#define GPIO_PinSource5 ((uint8_t)0x05)
|
||||
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||
#define GPIO_PinSource8 ((uint8_t)0x08)
|
||||
#define GPIO_PinSource9 ((uint8_t)0x09)
|
||||
#define GPIO_PinSource10 ((uint8_t)0x0A)
|
||||
#define GPIO_PinSource11 ((uint8_t)0x0B)
|
||||
#define GPIO_PinSource12 ((uint8_t)0x0C)
|
||||
#define GPIO_PinSource13 ((uint8_t)0x0D)
|
||||
#define GPIO_PinSource14 ((uint8_t)0x0E)
|
||||
#define GPIO_PinSource15 ((uint8_t)0x0F)
|
||||
|
||||
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
|
||||
((PINSOURCE) == GPIO_PinSource1) || \
|
||||
((PINSOURCE) == GPIO_PinSource2) || \
|
||||
((PINSOURCE) == GPIO_PinSource3) || \
|
||||
((PINSOURCE) == GPIO_PinSource4) || \
|
||||
((PINSOURCE) == GPIO_PinSource5) || \
|
||||
((PINSOURCE) == GPIO_PinSource6) || \
|
||||
((PINSOURCE) == GPIO_PinSource7) || \
|
||||
((PINSOURCE) == GPIO_PinSource8) || \
|
||||
((PINSOURCE) == GPIO_PinSource9) || \
|
||||
((PINSOURCE) == GPIO_PinSource10) || \
|
||||
((PINSOURCE) == GPIO_PinSource11) || \
|
||||
((PINSOURCE) == GPIO_PinSource12) || \
|
||||
((PINSOURCE) == GPIO_PinSource13) || \
|
||||
((PINSOURCE) == GPIO_PinSource14) || \
|
||||
((PINSOURCE) == GPIO_PinSource15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Ethernet_Media_Interface
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
|
||||
#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
|
||||
|
||||
#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
|
||||
((INTERFACE) == GPIO_ETH_MediaInterface_RMII))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
|
||||
void GPIO_AFIODeInit(void);
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
|
||||
void GPIO_EventOutputCmd(FunctionalState NewState);
|
||||
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
|
||||
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
|
||||
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_GPIO_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
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Reference in New Issue