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Merge pull request #5634 from ARMmbed/release-candidate 

Release candidate for mbed-os-5.6.6
mbed-os-5.6 mbed_lib_rev157
Martin Kojtal 2017-12-04 11:55:10 +00:00 committed by GitHub
parent 182bbd51bc 4ad5e42ca7
commit 5f6572179d
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
183 changed files with 21733 additions and 12973 deletions
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210
TESTS/mbedmicro-rtos-mbed/heap_and_stack/main.cpp
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2016, ARM Limited, All Rights Reserved
* Copyright (c) 2016-2017, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
@ -17,11 +17,17 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "greentea-client/test_env.h"
#include "cmsis.h"
#include "mbed.h"
#include "rtos.h"
#include "mbed_assert.h"
#include "cmsis.h"
#include "greentea-client/test_env.h"
#include "utest/utest.h"
#include "unity/unity.h"
using utest::v1::Case;
static const int test_timeout = 30;
// Amount to malloc for each iteration
#define MALLOC_TEST_SIZE 256
@ -33,58 +39,29 @@ extern uint32_t mbed_heap_size;
extern uint32_t mbed_stack_isr_start;
extern uint32_t mbed_stack_isr_size;
static uint32_t max_allocation_size = 0;
static bool inrange(uint32_t addr, uint32_t start, uint32_t size);
static bool rangeinrange(uint32_t addr, uint32_t size, uint32_t start, uint32_t len);
static bool valid_fill(uint8_t * data, uint32_t size, uint8_t fill);
static bool allocate_and_fill_heap(void);
static bool check_and_free_heap(void);
struct linked_list {
linked_list * next;
uint8_t data[MALLOC_TEST_SIZE];
};
int main (void) {
GREENTEA_SETUP(30, "default_auto");
char c;
char * initial_stack = &c;
char *initial_heap;
// Sanity check malloc
initial_heap = (char*)malloc(1);
if (initial_heap == NULL) {
printf("Unable to malloc a single byte\n");
GREENTEA_TESTSUITE_RESULT(false);
}
/* TODO: add memory layout test.
*
* The test was skipped for now since not all devices seems to comply with Mbed OS memory.
*
* @note Mbed OS memory model: https://os.mbed.com/docs/latest/reference/memory.html
*
*/
if (!inrange((uint32_t)initial_heap, mbed_heap_start, mbed_heap_size)) {
printf("Heap in wrong location\n");
GREENTEA_TESTSUITE_RESULT(false);
}
// MSP stack should be very near end (test using within 128 bytes)
uint32_t msp = __get_MSP();
if (!inrange(msp, mbed_stack_isr_start + mbed_stack_isr_size - 128, 128)) {
printf("Interrupt stack in wrong location\n");
GREENTEA_TESTSUITE_RESULT(false);
}
// Fully allocate the heap and stack
bool ret = true;
ret = ret && allocate_and_fill_heap();
ret = ret && check_and_free_heap();
// Force a task switch so a stack check is performed
Thread::wait(10);
printf("Total size dynamically allocated: %lu\n", max_allocation_size);
GREENTEA_TESTSUITE_RESULT(ret);
}
/*
* Return true if addr is in range [start:start+size)
*/
static bool inrange(uint32_t addr, uint32_t start, uint32_t size)
{
return (addr >= start) && (addr < start + size) ? true : false;
return (addr >= start) && (addr < (start + size));
}
/*
@ -92,7 +69,7 @@ static bool inrange(uint32_t addr, uint32_t start, uint32_t size)
*/
static bool rangeinrange(uint32_t addr, uint32_t size, uint32_t start, uint32_t len)
{
if (addr + size > start + len) {
if ((addr + size) > (start + len)) {
return false;
}
if (addr < start) {
@ -102,7 +79,7 @@ static bool rangeinrange(uint32_t addr, uint32_t size, uint32_t start, uint32_t
}
/*
* Return true of the region is filled only the the specified fill value
* Return true if the region is filled only with the specified value
*/
static bool valid_fill(uint8_t * data, uint32_t size, uint8_t fill)
{
@ -114,39 +91,29 @@ static bool valid_fill(uint8_t * data, uint32_t size, uint8_t fill)
return true;
}
struct linked_list {
linked_list * next;
uint8_t data[MALLOC_TEST_SIZE];
};
static linked_list *head = NULL;
static bool allocate_and_fill_heap()
static void allocate_and_fill_heap(linked_list *&head)
{
linked_list *current;
current = (linked_list*) malloc(sizeof(linked_list));
if (0 == current) {
return false;
}
TEST_ASSERT_NOT_NULL(current);
current->next = NULL;
memset((void*) current->data, MALLOC_FILL, sizeof(current->data));
// Allocate until malloc returns NULL
bool pass = true;
head = current;
while (true) {
// Allocate
linked_list *temp = (linked_list*) malloc(sizeof(linked_list));
if (NULL == temp) {
break;
}
if (!rangeinrange((uint32_t)temp, sizeof(linked_list), mbed_heap_start, mbed_heap_size)) {
printf("Memory allocation out of range\n");
pass = false;
break;
}
bool result = rangeinrange((uint32_t) temp, sizeof(linked_list), mbed_heap_start, mbed_heap_size);
TEST_ASSERT_TRUE_MESSAGE(result, "Memory allocation out of range");
// Init
temp->next = NULL;
@ -156,24 +123,123 @@ static bool allocate_and_fill_heap()
current->next = temp;
current = temp;
}
return pass;
}
static bool check_and_free_heap()
static void check_and_free_heap(linked_list *head, uint32_t &max_allocation_size)
{
uint32_t total_size = 0;
linked_list * current = head;
bool pass = true;
while (current != NULL) {
total_size += sizeof(linked_list);
if (!valid_fill(current->data, sizeof(current->data), MALLOC_FILL)) {
pass = false;
}
bool result = valid_fill(current->data, sizeof(current->data), MALLOC_FILL);
TEST_ASSERT_TRUE_MESSAGE(result, "Memory fill check failed");
linked_list * next = current->next;
free(current);
current = next;
}
max_allocation_size = total_size;
return pass;
}
/** Test heap allocation
Given a heap
When memory is allocated from heap
Then the memory is within heap boundary
*/
void test_heap_in_range(void)
{
char *initial_heap;
// Sanity check malloc
initial_heap = (char*) malloc(1);
TEST_ASSERT_NOT_NULL(initial_heap);
bool result = inrange((uint32_t) initial_heap, mbed_heap_start, mbed_heap_size);
TEST_ASSERT_TRUE_MESSAGE(result, "Heap in wrong location");
free(initial_heap);
}
/** Test for Main thread stack
Given a Main thread and its stack
When check Main thread stack pointer
Then the SP is within Main stack boundary
*/
void test_main_stack_in_range(void)
{
os_thread_t *thread = (os_thread_t*) osThreadGetId();
uint32_t psp = __get_PSP();
uint8_t *stack_mem = (uint8_t*) thread->stack_mem;
uint32_t stack_size = thread->stack_size;
// PSP stack should be somewhere in the middle
bool result = inrange(psp, (uint32_t) stack_mem, stack_size);
TEST_ASSERT_TRUE_MESSAGE(result, "Main stack in wrong location");
}
/** Test for Scheduler/ISR thread stack
Given a Scheduler/ISR thread and its stack
When check Scheduler/ISR thread stack pointer
Then the SP is within Scheduler/ISR stack boundary
*/
void test_isr_stack_in_range(void)
{
// MSP stack should be very near end (test using within 128 bytes)
uint32_t msp = __get_MSP();
bool result = inrange(msp, mbed_stack_isr_start + mbed_stack_isr_size - 128, 128);
TEST_ASSERT_TRUE_MESSAGE(result, "Interrupt stack in wrong location");
}
/** Test full heap allocation
Given a heap and linked_list data structure
When linked_list is filled till run out of heap memory
Then the memory is properly initialised and freed
*/
void test_heap_allocation_free(void)
{
linked_list *head = NULL;
uint32_t max_allocation_size = 0;
// Fully allocate the heap and stack
allocate_and_fill_heap(head);
check_and_free_heap(head, max_allocation_size);
// Force a task switch so a stack check is performed
Thread::wait(10);
printf("Total size dynamically allocated: %luB\n", max_allocation_size);
}
// Test cases
Case cases[] = {
Case("Test heap in range", test_heap_in_range),
Case("Test main stack in range", test_main_stack_in_range),
Case("Test isr stack in range", test_isr_stack_in_range),
Case("Test heap allocation and free", test_heap_allocation_free)
};
utest::v1::status_t greentea_test_setup(const size_t number_of_cases)
{
GREENTEA_SETUP(test_timeout, "default_auto");
return utest::v1::greentea_test_setup_handler(number_of_cases);
}
utest::v1::Specification specification(greentea_test_setup, cases);
int main()
{
return !utest::v1::Harness::run(specification);
}

141
TESTS/mbedmicro-rtos-mbed/malloc/main.cpp
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@ -14,14 +14,22 @@
* limitations under the License.
*/
#include "mbed.h"
#include "test_env.h"
#include "rtos.h"
#include "greentea-client/test_env.h"
#include "utest/utest.h"
#include "unity/unity.h"
#if defined(MBED_RTOS_SINGLE_THREAD)
#error [NOT_SUPPORTED] test not supported
#endif
#define NUM_THREADS 5
using utest::v1::Case;
extern uint32_t mbed_heap_size;
static const int test_timeout = 25;
volatile bool thread_should_continue = true;
#define NUM_THREADS 4
#define THREAD_MALLOC_SIZE 100
#if defined(__CORTEX_A9)
#define THREAD_STACK_SIZE DEFAULT_STACK_SIZE
@ -29,65 +37,138 @@
#define THREAD_STACK_SIZE 256
#endif
DigitalOut led1(LED1);
volatile bool should_exit = false;
volatile bool allocation_failure = false;
void task_using_malloc(void)
{
void* data;
while (1) {
void *data = NULL;
while (thread_should_continue) {
// Repeatedly allocate and free memory
data = malloc(100);
if (data != NULL) {
memset(data, 0, 100);
} else {
allocation_failure = true;
}
data = malloc(THREAD_MALLOC_SIZE);
TEST_ASSERT_NOT_NULL(data);
// test whole allocated memory
memset(data, 0, THREAD_MALLOC_SIZE);
free(data);
if (should_exit) {
return;
}
}
}
int main()
/** Test for multithreaded heap allocations
Given multiple threads are started in parallel
When each of the threads allocate memory
Then the memory allocation succeed and @a malloc return valid memory
*/
void test_multithread_allocation(void)
{
// static stack for threads to reduce heap usage on devices with small RAM
// and eliminate run out of heap memory problem
uint8_t stack[NUM_THREADS][THREAD_STACK_SIZE];
bool thread_alloc_failure = false;
Thread *thread_list[NUM_THREADS];
int test_time = 15;
GREENTEA_SETUP(20, "default_auto");
int test_time = 20;
// Allocate threads for the test
for (int i = 0; i < NUM_THREADS; i++) {
thread_list[i] = new Thread(osPriorityNormal, THREAD_STACK_SIZE, stack[i]);
if (NULL == thread_list[i]) {
allocation_failure = true;
thread_alloc_failure = true;
} else {
thread_list[i]->start(task_using_malloc);
}
}
// Give the test time to run
while (test_time) {
led1 = !led1;
while (test_time--) {
Thread::wait(1000);
test_time--;
}
// Join and delete all threads
should_exit = 1;
thread_should_continue = false;
for (int i = 0; i < NUM_THREADS; i++) {
if (NULL == thread_list[i]) {
continue;
}
if (NULL != thread_list[i]) {
thread_list[i]->join();
delete thread_list[i];
thread_list[i] = NULL;
}
}
TEST_ASSERT_FALSE(thread_alloc_failure);
}
GREENTEA_TESTSUITE_RESULT(!allocation_failure);
/** Test for large heap allocation
Given a heap of size mbed_heap_size
When try to allocate memory of size mbed_heap_size/5 (20% of whole heap)
Then the memory is allocated and @a malloc return valid memory
*/
void test_big_allocation(void)
{
const uint32_t alloc_size = mbed_heap_size / 5;
void *data = NULL;
data = malloc(alloc_size);
TEST_ASSERT_NOT_NULL(data);
// test whole allocated memory
memset(data, 0, alloc_size);
free(data);
}
/** Test if allocation of zero size does not cause any undefined behaviour
Given a heap
When try to allocate memory of size 0
Then the return value of @a malloc depends on the particular library implementation
(NULL or smallest possible allocation) and no undefined behaviour happens
@note If allocation size is zero, the return value depends on the particular library implementation
(it may or may not be a null pointer), but the returned pointer shall not be dereferenced
*/
void test_zero_allocation(void)
{
void *data = NULL;
data = malloc(0);
if(data != NULL) {
free(data);
}
TEST_ASSERT_MESSAGE(true, "malloc(0) succeed - no undefined behaviour happens");
}
/** Test if free on NULL pointer does not cause any undefined behaviour
Given a NULL pointer
When try to free it
Then the function @a free does nothing and no undefined behaviour happens
*/
void test_null_free(void)
{
void *data = NULL;
free(data);
TEST_ASSERT_MESSAGE(true, "free(NULL) succeed - no undefined behaviour happens");
}
// Test cases
Case cases[] = {
Case("Test 0 size allocation", test_zero_allocation),
Case("Test NULL pointer free", test_null_free),
Case("Test multithreaded allocations", test_multithread_allocation),
Case("Test large allocation", test_big_allocation)
};
utest::v1::status_t greentea_test_setup(const size_t number_of_cases)
{
GREENTEA_SETUP(test_timeout, "timing_drift_auto");
return utest::v1::greentea_test_setup_handler(number_of_cases);
}
utest::v1::Specification specification(greentea_test_setup, cases);
int main()
{
return !utest::v1::Harness::run(specification);
}

59
TESTS/mbedmicro-rtos-mbed/threads/main.cpp
View File

@ -25,7 +25,9 @@
#error [NOT_SUPPORTED] test not supported
#endif
#define THREAD_STACK_SIZE 768
#define THREAD_STACK_SIZE 512
#define PARALLEL_THREAD_STACK_SIZE 384
#define CHILD_THREAD_STACK_SIZE 384
using namespace utest::v1;
@ -33,6 +35,12 @@ using namespace utest::v1;
// It is internall ysynchronized so read
typedef SynchronizedIntegral<int> counter_t;
template<osPriority P, uint32_t S>
class ParallelThread : public Thread {
public:
ParallelThread() : Thread(P, S) { }
};
// Tasks with different functions to test on threads
void increment(counter_t* counter) {
(*counter)++;
@ -49,9 +57,10 @@ void increment_with_wait(counter_t* counter) {
}
void increment_with_child(counter_t* counter) {
Thread child(osPriorityNormal, THREAD_STACK_SIZE/2);
child.start(callback(increment, counter));
child.join();
Thread *child = new Thread(osPriorityNormal, CHILD_THREAD_STACK_SIZE);
child->start(callback(increment, counter));
child->join();
delete child;
}
void increment_with_murder(counter_t* counter) {
@ -59,9 +68,10 @@ void increment_with_murder(counter_t* counter) {
// take ownership of the counter mutex so it prevent the child to
// modify counter.
LockGuard lock(counter->internal_mutex());
Thread child(osPriorityNormal, THREAD_STACK_SIZE);
child.start(callback(increment, counter));
child.terminate();
Thread *child = new Thread(osPriorityNormal, CHILD_THREAD_STACK_SIZE);
child->start(callback(increment, counter));
child->terminate();
delete child;
}
(*counter)++;
@ -147,16 +157,14 @@ void test_single_thread() {
template <int N, void (*F)(counter_t *)>
void test_parallel_threads() {
counter_t counter(0);
Thread *threads[N];
ParallelThread<osPriorityNormal, PARALLEL_THREAD_STACK_SIZE> threads[N];
for (int i = 0; i < N; i++) {
threads[i] = new Thread(osPriorityNormal, THREAD_STACK_SIZE);
threads[i]->start(callback(F, &counter));
threads[i].start(callback(F, &counter));
}
for (int i = 0; i < N; i++) {
threads[i]->join();
delete threads[i];
threads[i].join();
}
TEST_ASSERT_EQUAL(counter, N);
@ -272,7 +280,7 @@ void signal_wait_multibit_tout()
template <int S, void (*F)()>
void test_thread_signal()
{
Thread t_wait;
Thread t_wait(osPriorityNormal, THREAD_STACK_SIZE);
t_wait.start(callback(F));
@ -308,7 +316,7 @@ void signal_clr()
*/
void test_thread_signal_clr()
{
Thread t_wait;
Thread t_wait(osPriorityNormal, THREAD_STACK_SIZE);
t_wait.start(callback(signal_clr));
@ -413,7 +421,7 @@ void test_deleted_thread()
*/
void test_deleted()
{
Thread t;
Thread t(osPriorityNormal, THREAD_STACK_SIZE);
TEST_ASSERT_EQUAL(Thread::Deleted, t.get_state());
@ -436,7 +444,7 @@ void test_delay_thread()
*/
void test_delay()
{
Thread t;
Thread t(osPriorityNormal, THREAD_STACK_SIZE);
t.start(callback(test_delay_thread));
@ -461,7 +469,7 @@ void test_signal_thread()
*/
void test_signal()
{
Thread t;
Thread t(osPriorityNormal, THREAD_STACK_SIZE);
t.start(callback(test_signal_thread));
@ -485,7 +493,7 @@ void test_evt_flag_thread(osEventFlagsId_t evtflg)
*/
void test_evt_flag()
{
Thread t;
Thread t(osPriorityNormal, THREAD_STACK_SIZE);
mbed_rtos_storage_event_flags_t evtflg_mem;
osEventFlagsAttr_t evtflg_attr;
osEventFlagsId_t evtflg;
@ -517,7 +525,7 @@ void test_mutex_thread(Mutex *mutex)
*/
void test_mutex()
{
Thread t;
Thread t(osPriorityNormal, THREAD_STACK_SIZE);
Mutex mutex;
mutex.lock();
@ -544,7 +552,7 @@ void test_semaphore_thread(Semaphore *sem)
*/
void test_semaphore()
{
Thread t;
Thread t(osPriorityNormal, THREAD_STACK_SIZE);
Semaphore sem;
t.start(callback(test_semaphore_thread, &sem));
@ -569,7 +577,7 @@ void test_msg_get_thread(Queue<int32_t, 1> *queue)
*/
void test_msg_get()
{
Thread t;
Thread t(osPriorityNormal, THREAD_STACK_SIZE);
Queue<int32_t, 1> queue;
t.start(callback(test_msg_get_thread, &queue));
@ -595,7 +603,7 @@ void test_msg_put_thread(Queue<int32_t, 1> *queue)
*/
void test_msg_put()
{
Thread t;
Thread t(osPriorityNormal, THREAD_STACK_SIZE);
Queue<int32_t, 1> queue;
queue.put((int32_t *)0xE1EE7);
@ -643,7 +651,7 @@ void test_thread_ext_stack() {
then priority is changed and can be retrieved using @a get_priority
*/
void test_thread_prio() {
Thread t(osPriorityNormal);
Thread t(osPriorityNormal, THREAD_STACK_SIZE);
t.start(callback(thread_wait_signal));
TEST_ASSERT_EQUAL(osPriorityNormal, t.get_priority());
@ -679,11 +687,11 @@ static const case_t cases[] = {
{"Testing serial threads with wait", test_serial_threads<10, increment_with_wait>, DEFAULT_HANDLERS},
{"Testing single thread with child", test_single_thread<increment_with_child>, DEFAULT_HANDLERS},
{"Testing parallel threads with child", test_parallel_threads<3, increment_with_child>, DEFAULT_HANDLERS},
{"Testing parallel threads with child", test_parallel_threads<2, increment_with_child>, DEFAULT_HANDLERS},
{"Testing serial threads with child", test_serial_threads<10, increment_with_child>, DEFAULT_HANDLERS},
{"Testing single thread with murder", test_single_thread<increment_with_murder>, DEFAULT_HANDLERS},
{"Testing parallel threads with murder", test_parallel_threads<3, increment_with_murder>, DEFAULT_HANDLERS},
{"Testing parallel threads with murder", test_parallel_threads<2, increment_with_murder>, DEFAULT_HANDLERS},
{"Testing serial threads with murder", test_serial_threads<10, increment_with_murder>, DEFAULT_HANDLERS},
{"Testing thread self terminate", test_self_terminate, DEFAULT_HANDLERS},
@ -710,6 +718,7 @@ static const case_t cases[] = {
{"Testing thread with external stack memory", test_thread_ext_stack, DEFAULT_HANDLERS},
{"Testing thread priority ops", test_thread_prio, DEFAULT_HANDLERS}
};
Specification specification(test_setup, cases);

7
features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/source/nRF5xGattServer.cpp
View File

@ -65,6 +65,7 @@ ble_error_t nRF5xGattServer::addService(GattService &service)
return BLE_ERROR_NO_MEM;
}
GattCharacteristic *p_char = service.getCharacteristic(i);
GattAttribute *p_description_descriptor = NULL;
/* Skip any incompletely defined, read-only characteristics. */
if ((p_char->getValueAttribute().getValuePtr() == NULL) &&
@ -83,6 +84,7 @@ ble_error_t nRF5xGattServer::addService(GattService &service)
for (uint8_t j = 0; j < p_char->getDescriptorCount(); j++) {
GattAttribute *p_desc = p_char->getDescriptor(j);
if (p_desc->getUUID() == BLE_UUID_DESCRIPTOR_CHAR_USER_DESC) {
p_description_descriptor = p_desc;
userDescriptionDescriptorValuePtr = p_desc->getValuePtr();
userDescriptionDescriptorValueLen = p_desc->getLength();
}
@ -107,6 +109,11 @@ ble_error_t nRF5xGattServer::addService(GattService &service)
/* Update the characteristic handle */
p_characteristics[characteristicCount] = p_char;
p_char->getValueAttribute().setHandle(nrfCharacteristicHandles[characteristicCount].value_handle);
if (p_description_descriptor) {
p_description_descriptor->setHandle(
nrfCharacteristicHandles[characteristicCount].user_desc_handle
);
}
characteristicCount++;
/* Add optional descriptors if any */

7
features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattServer.cpp
View File

@ -106,6 +106,7 @@ ble_error_t nRF5xGattServer::addService(GattService &service)
return BLE_ERROR_NO_MEM;
}
GattCharacteristic *p_char = service.getCharacteristic(i);
GattAttribute *p_description_descriptor = NULL;
/* Skip any incompletely defined, read-only characteristics. */
if ((p_char->getValueAttribute().getValuePtr() == NULL) &&
@ -124,6 +125,7 @@ ble_error_t nRF5xGattServer::addService(GattService &service)
for (uint8_t j = 0; j < p_char->getDescriptorCount(); j++) {
GattAttribute *p_desc = p_char->getDescriptor(j);
if (p_desc->getUUID() == BLE_UUID_DESCRIPTOR_CHAR_USER_DESC) {
p_description_descriptor = p_desc;
userDescriptionDescriptorValuePtr = p_desc->getValuePtr();
userDescriptionDescriptorValueLen = p_desc->getLength();
}
@ -148,6 +150,11 @@ ble_error_t nRF5xGattServer::addService(GattService &service)
/* Update the characteristic handle */
p_characteristics[characteristicCount] = p_char;
p_char->getValueAttribute().setHandle(nrfCharacteristicHandles[characteristicCount].value_handle);
if (p_description_descriptor) {
p_description_descriptor->setHandle(
nrfCharacteristicHandles[characteristicCount].user_desc_handle
);
}
characteristicCount++;
/* Add optional descriptors if any */

261
features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/harware_init_LPC546XX.c Normal file
View File

@ -0,0 +1,261 @@
/* mbed Microcontroller Library
* Copyright (c) 2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "fsl_iocon.h"
#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */
#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */
#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */
#define IOCON_PIO_FUNC6 0x06u /*!<@brief Selects pin function 6 */
#define IOCON_PIO_FUNC7 0x07u /*!<@brief Selects pin function 7 */
#define IOCON_PIO_INPFILT_OFF 0x0200u /*!<@brief Input filter disabled */
#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */
#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */
#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */
#define IOCON_PIO_SLEW_FAST 0x0400u /*!<@brief Fast mode, slew rate control is disabled */
#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
/*******************************************************************************
* Code
******************************************************************************/
void lpc546xx_init_eth_hardware(void)
{
CLOCK_EnableClock(kCLOCK_InputMux);
/* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */
CLOCK_EnableClock(kCLOCK_Iocon);
const uint32_t port0_pin10_config = (/* Pin is configured as SWO */
IOCON_PIO_FUNC6 |
/* No addition pin function */
IOCON_PIO_MODE_INACT |
/* Input function is not inverted */
IOCON_PIO_INV_DI |
/* Enables digital function */
IOCON_PIO_DIGITAL_EN |
/* Input filter disabled */
IOCON_PIO_INPFILT_OFF |
/* Open drain is disabled */
IOCON_PIO_OPENDRAIN_DI);
/* PORT0 PIN10 (coords: P2) is configured as SWO */
IOCON_PinMuxSet(IOCON, 0U, 10U, port0_pin10_config);
const uint32_t port0_pin17_config = (/* Pin is configured as ENET_TXD1 */
IOCON_PIO_FUNC7 |
/* No addition pin function */
IOCON_PIO_MODE_INACT |
/* Input function is not inverted */
IOCON_PIO_INV_DI |
/* Enables digital function */
IOCON_PIO_DIGITAL_EN |
/* Input filter disabled */
IOCON_PIO_INPFILT_OFF |
/* Standard mode, output slew rate control is enabled */
IOCON_PIO_SLEW_STANDARD |
/* Open drain is disabled */
IOCON_PIO_OPENDRAIN_DI);
/* PORT0 PIN17 (coords: E14) is configured as ENET_TXD1 */
IOCON_PinMuxSet(IOCON, 0U, 17U, port0_pin17_config);
const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI */
IOCON_PIO_FUNC1 |
/* No addition pin function */
IOCON_PIO_MODE_INACT |
/* Input function is not inverted */
IOCON_PIO_INV_DI |
/* Enables digital function */
IOCON_PIO_DIGITAL_EN |
/* Input filter disabled */
IOCON_PIO_INPFILT_OFF |
/* Fast mode, slew rate control is disabled */
IOCON_PIO_SLEW_FAST |
/* Open drain is disabled */
IOCON_PIO_OPENDRAIN_DI);
/* PORT0 PIN29 (coords: B13) is configured as FC0_RXD_SDA_MOSI */
IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config);
const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO */
IOCON_PIO_FUNC1 |
/* No addition pin function */
IOCON_PIO_MODE_INACT |
/* Input function is not inverted */
IOCON_PIO_INV_DI |
/* Enables digital function */
IOCON_PIO_DIGITAL_EN |
/* Input filter disabled */
IOCON_PIO_INPFILT_OFF |
/* Fast mode, slew rate control is disabled */
IOCON_PIO_SLEW_FAST |
/* Open drain is disabled */
IOCON_PIO_OPENDRAIN_DI);
/* PORT0 PIN30 (coords: A2) is configured as FC0_TXD_SCL_MISO */
IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config);
const uint32_t port2_pin26_config = (/* Pin is configured as PIO2_26 */
IOCON_PIO_FUNC0 |
/* Selects pull-up function */
IOCON_PIO_MODE_PULLUP |
/* Input function is not inverted */
IOCON_PIO_INV_DI |
/* Enables digital function */
IOCON_PIO_DIGITAL_EN |
/* Input filter disabled */
IOCON_PIO_INPFILT_OFF |
/* Standard mode, output slew rate control is enabled */
IOCON_PIO_SLEW_STANDARD |
/* Open drain is disabled */
IOCON_PIO_OPENDRAIN_DI);
/* PORT2 PIN26 (coords: H11) is configured as PIO2_26 */
IOCON_PinMuxSet(IOCON, 2U, 26U, port2_pin26_config);
const uint32_t port4_pin10_config = (/* Pin is configured as ENET_RX_DV */
IOCON_PIO_FUNC1 |
/* No addition pin function */
IOCON_PIO_MODE_INACT |
/* Input function is not inverted */
IOCON_PIO_INV_DI |
/* Enables digital function */
IOCON_PIO_DIGITAL_EN |
/* Input filter disabled */
IOCON_PIO_INPFILT_OFF |
/* Standard mode, output slew rate control is enabled */
IOCON_PIO_SLEW_STANDARD |
/* Open drain is disabled */
IOCON_PIO_OPENDRAIN_DI);
/* PORT4 PIN10 (coords: B9) is configured as ENET_RX_DV */
IOCON_PinMuxSet(IOCON, 4U, 10U, port4_pin10_config);
const uint32_t port4_pin11_config = (/* Pin is configured as ENET_RXD0 */
IOCON_PIO_FUNC1 |
/* No addition pin function */
IOCON_PIO_MODE_INACT |
/* Input function is not inverted */
IOCON_PIO_INV_DI |
/* Enables digital function */
IOCON_PIO_DIGITAL_EN |
/* Input filter disabled */
IOCON_PIO_INPFILT_OFF |
/* Standard mode, output slew rate control is enabled */
IOCON_PIO_SLEW_STANDARD |
/* Open drain is disabled */
IOCON_PIO_OPENDRAIN_DI);
/* PORT4 PIN11 (coords: A9) is configured as ENET_RXD0 */
IOCON_PinMuxSet(IOCON, 4U, 11U, port4_pin11_config);
const uint32_t port4_pin12_config = (/* Pin is configured as ENET_RXD1 */
IOCON_PIO_FUNC1 |
/* No addition pin function */
IOCON_PIO_MODE_INACT |
/* Input function is not inverted */
IOCON_PIO_INV_DI |
/* Enables digital function */
IOCON_PIO_DIGITAL_EN |
/* Input filter disabled */
IOCON_PIO_INPFILT_OFF |
/* Standard mode, output slew rate control is enabled */
IOCON_PIO_SLEW_STANDARD |
/* Open drain is disabled */
IOCON_PIO_OPENDRAIN_DI);
/* PORT4 PIN12 (coords: A6) is configured as ENET_RXD1 */
IOCON_PinMuxSet(IOCON, 4U, 12U, port4_pin12_config);
const uint32_t port4_pin13_config = (/* Pin is configured as ENET_TX_EN */
IOCON_PIO_FUNC1 |
/* No addition pin function */
IOCON_PIO_MODE_INACT |
/* Input function is not inverted */
IOCON_PIO_INV_DI |
/* Enables digital function */
IOCON_PIO_DIGITAL_EN |
/* Input filter disabled */
IOCON_PIO_INPFILT_OFF |
/* Standard mode, output slew rate control is enabled */
IOCON_PIO_SLEW_STANDARD |
/* Open drain is disabled */
IOCON_PIO_OPENDRAIN_DI);
/* PORT4 PIN13 (coords: B6) is configured as ENET_TX_EN */
IOCON_PinMuxSet(IOCON, 4U, 13U, port4_pin13_config);
const uint32_t port4_pin14_config = (/* Pin is configured as ENET_RX_CLK */
IOCON_PIO_FUNC1 |
/* No addition pin function */
IOCON_PIO_MODE_INACT |
/* Input function is not inverted */
IOCON_PIO_INV_DI |
/* Enables digital function */
IOCON_PIO_DIGITAL_EN |
/* Input filter disabled */
IOCON_PIO_INPFILT_OFF |
/* Standard mode, output slew rate control is enabled */
IOCON_PIO_SLEW_STANDARD |
/* Open drain is disabled */
IOCON_PIO_OPENDRAIN_DI);
/* PORT4 PIN14 (coords: B5) is configured as ENET_RX_CLK */
IOCON_PinMuxSet(IOCON, 4U, 14U, port4_pin14_config);
const uint32_t port4_pin15_config = (/* Pin is configured as ENET_MDC */
IOCON_PIO_FUNC1 |
/* No addition pin function */
IOCON_PIO_MODE_INACT |
/* Input function is not inverted */
IOCON_PIO_INV_DI |
/* Enables digital function */
IOCON_PIO_DIGITAL_EN |
/* Input filter disabled */
IOCON_PIO_INPFILT_OFF |
/* Standard mode, output slew rate control is enabled */
IOCON_PIO_SLEW_STANDARD |
/* Open drain is disabled */
IOCON_PIO_OPENDRAIN_DI);
/* PORT4 PIN15 (coords: A4) is configured as ENET_MDC */
IOCON_PinMuxSet(IOCON, 4U, 15U, port4_pin15_config);
const uint32_t port4_pin16_config = (/* Pin is configured as ENET_MDIO */
IOCON_PIO_FUNC1 |
/* No addition pin function */
IOCON_PIO_MODE_INACT |
/* Input function is not inverted */
IOCON_PIO_INV_DI |
/* Enables digital function */
IOCON_PIO_DIGITAL_EN |
/* Input filter disabled */
IOCON_PIO_INPFILT_OFF |
/* Standard mode, output slew rate control is enabled */
IOCON_PIO_SLEW_STANDARD |
/* Open drain is disabled */
IOCON_PIO_OPENDRAIN_DI);
/* PORT4 PIN16 (coords: C4) is configured as ENET_MDIO */
IOCON_PinMuxSet(IOCON, 4U, 16U, port4_pin16_config);
const uint32_t port4_pin8_config = (/* Pin is configured as ENET_TXD0 */
IOCON_PIO_FUNC1 |
/* No addition pin function */
IOCON_PIO_MODE_INACT |
/* Input function is not inverted */
IOCON_PIO_INV_DI |
/* Enables digital function */
IOCON_PIO_DIGITAL_EN |
/* Input filter disabled */
IOCON_PIO_INPFILT_OFF |
/* Standard mode, output slew rate control is enabled */
IOCON_PIO_SLEW_STANDARD |
/* Open drain is disabled */
IOCON_PIO_OPENDRAIN_DI);
/* PORT4 PIN8 (coords: B14) is configured as ENET_TXD0 */
IOCON_PinMuxSet(IOCON, 4U, 8U, port4_pin8_config);
}

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features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/lpc546xx_emac.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "lwip/opt.h"
#include "lwip/sys.h"
#include "lwip/def.h"
#include "lwip/mem.h"
#include "lwip/pbuf.h"
#include "lwip/stats.h"
#include "lwip/snmp.h"
#include "lwip/tcpip.h"
#include "lwip/ethip6.h"
#include "netif/etharp.h"
#include "netif/ppp/pppoe.h"
#include "eth_arch.h"
#include "sys_arch.h"
#include "fsl_phy.h"
#include "lpc546xx_emac_config.h"
#include <string.h>
#include "mbed_interface.h"
#if LWIP_ARP || LWIP_ETHERNET
enet_handle_t g_handle;
// RX packet buffer pointers
struct pbuf *rx_buff[ENET_RX_RING_LEN];
// TX packet buffer pointers
uint8_t *tx_buff[ENET_TX_RING_LEN];
// RX packet payload pointers
uint32_t rx_ptr[ENET_RX_RING_LEN];
/** \brief Debug output formatter lock define
*
* When using FreeRTOS and with LWIP_DEBUG enabled, enabling this
* define will allow RX debug messages to not interleave with the
* TX messages (so they are actually readable). Not enabling this
* define when the system is under load will cause the output to
* be unreadable. There is a small tradeoff in performance for this
* so use it only for debug. */
//#define LOCK_RX_THREAD
/* LPC546XX EMAC driver data structure */
struct lpc_enetdata {
struct netif *netif; /**< Reference back to LWIP parent netif */
osThreadId_t thread; /**< Processing thread */
sys_mutex_t TXLockMutex; /**< TX critical section mutex */
sys_sem_t xTXDCountSem; /**< TX free buffer counting semaphore */
};
static struct lpc_enetdata lpc_enetdata;
/* \brief Flags for worker thread */
#define FLAG_TX 1
#define FLAG_RX 2
/** \brief Driver thread priority */
#define THREAD_PRIORITY (osPriorityNormal)
#ifdef LWIP_DEBUG
#define THREAD_STACKSIZE (DEFAULT_THREAD_STACKSIZE * 5)
#else
#define THREAD_STACKSIZE DEFAULT_THREAD_STACKSIZE
#endif
static void lpc546xx_phy_task(void *data);
static void lpc546xx_packet_rx(struct lpc_enetdata *lpc_enet);
static void lpc546xx_packet_tx(struct lpc_enetdata *lpc_enet);
#define PHY_TASK_PERIOD_MS 200
/********************************************************************************
* Buffer management
********************************************************************************/
/*
* This function will queue a new receive buffer
*/
static void update_read_buffer(enet_rx_bd_struct_t *rxDesc, uint8_t *buf)
{
enet_rx_bd_ring_t *rxBdRing = (enet_rx_bd_ring_t *)&g_handle.rxBdRing[0];
uint32_t control = ENET_RXDESCRIP_RD_OWN_MASK | ENET_RXDESCRIP_RD_BUFF1VALID_MASK | ENET_RXDESCRIP_RD_IOC_MASK;
uint32_t index = rxBdRing->rxGenIdx;
/* Increase the index. */
index++;
if (index >= ENET_RX_RING_LEN) {
index = 0;
}
rxBdRing->rxGenIdx = index;
if (buf != NULL) {
rxDesc->buff1Addr = (uint32_t)buf;
}
rxDesc->buff2Addr = 0;
rxDesc->reserved = 0;
rxDesc->control = control;
}
/** \brief Free TX buffers that are complete
*
* \param[in] lpc_enet Pointer to driver data structure
*/
static void lpc546xx_tx_reclaim(struct lpc_enetdata *lpc_enet)
{
static uint8_t consume_index = 0;
enet_tx_bd_ring_t *txBdRing = (enet_tx_bd_ring_t *)&g_handle.txBdRing[0];
while (consume_index != txBdRing->txConsumIdx) {
/* Free the transmit buffer */
free(tx_buff[consume_index]);
tx_buff[consume_index] = NULL;
osSemaphoreRelease(lpc_enetdata.xTXDCountSem.id);
consume_index++;
if (consume_index >= ENET_TX_RING_LEN) {
consume_index = 0;
}
}
}
/********************************************************************************
* Internal data
********************************************************************************/
#define ENET_BuffSizeAlign(n) ENET_ALIGN(n, ENET_BUFF_ALIGNMENT)
#define ENET_ALIGN(x,align) ((unsigned int)((x) + ((align)-1)) & (unsigned int)(~(unsigned int)((align)- 1)))
extern void lpc546xx_init_eth_hardware(void);
/** \brief Allocates a pbuf and returns the data from the incoming packet.
*
* \param[in] netif the lwip network interface structure for this lpc_enetif
* \return a pbuf filled with the received packet (including MAC header)
* NULL on memory error
*/
static struct pbuf *lpc546xx_low_level_input(struct netif *netif)
{
enet_rx_bd_ring_t *rxBdRing = (enet_rx_bd_ring_t *)&g_handle.rxBdRing[0];
enet_rx_bd_struct_t *bdPtr = rxBdRing->rxBdBase + rxBdRing->rxGenIdx;
#ifdef LOCK_RX_THREAD
struct lpc_enetdata *lpc_enet = netif->state;
#endif
struct pbuf *p = NULL;
struct pbuf *temp_rxbuf = NULL;
u32_t length = 0;
/* Determine if a frame has been received */
if ((bdPtr->control & ENET_RXDESCRIP_WR_OWN_MASK) != 0) {
return p;
}
#ifdef LOCK_RX_THREAD
/* Get exclusive access */
sys_mutex_lock(&lpc_enet->TXLockMutex);
#endif
/* Determine if the received frame has an error */
if ((bdPtr->control & ENET_RXDESCRIP_WR_ERRSUM_MASK) != 0) {
LINK_STATS_INC(link.err);
LINK_STATS_INC(link.drop);
/* Re-use the same buffer in case of error */
update_read_buffer(bdPtr, NULL);
} else {
if (bdPtr->control & ENET_RXDESCRIP_WR_LD_MASK) {
length = (bdPtr->control & ENET_RXDESCRIP_WR_PACKETLEN_MASK);
} else {
length = rxBdRing->rxBuffSizeAlign;
}
/* Zero-copy */
p = rx_buff[rxBdRing->rxGenIdx];
p->len = length;
/* Attempt to queue new buffer */
temp_rxbuf = pbuf_alloc(PBUF_RAW, ENET_ALIGN(ENET_ETH_MAX_FLEN, ENET_BUFF_ALIGNMENT), PBUF_RAM);
if (NULL == temp_rxbuf) {
/* Drop frame (out of memory) */
LINK_STATS_INC(link.drop);
LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
("lpc546xx_low_level_input: Packet index %d dropped for OOM\n", rxBdRing->rxGenIdx));
/* Re-queue the same buffer */
update_read_buffer(bdPtr, NULL);
#ifdef LOCK_RX_THREAD
sys_mutex_unlock(&lpc_enet->TXLockMutex);
#endif
return NULL;
}
rx_buff[rxBdRing->rxGenIdx] = temp_rxbuf;
rx_ptr[rxBdRing->rxGenIdx] = (uint32_t)rx_buff[rxBdRing->rxGenIdx]->payload;
LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
("lpc_low_level_input: Packet received: %p, size %"PRIu32" (index=%d)\n", p, length, rxBdRing->rxGenIdx));
update_read_buffer(bdPtr, rx_buff[rxBdRing->rxGenIdx]->payload);
/* Save size */
p->tot_len = (u16_t)length;
LINK_STATS_INC(link.recv);
}
#ifdef LOCK_RX_THREAD
sys_mutex_unlock(&lpc_enet->TXLockMutex);
#endif
return p;
}
/** \brief Attempt to read a packet from the EMAC interface.
*
* \param[in] netif the lwip network interface structure
*/
void lpc546xx_enetif_input(struct netif *netif)
{
struct pbuf *p;
/* move received packet into a new pbuf */
p = lpc546xx_low_level_input(netif);
if (p == NULL)
return;
/* pass all packets to ethernet_input, which decides what packets it supports */
if (netif->input(p, netif) != ERR_OK) {
LWIP_DEBUGF(NETIF_DEBUG, ("lpc546xx_enetif_input: input error\n"));
/* Free buffer */
pbuf_free(p);
}
}
/** \brief Worker thread.
*
* Woken by thread flags to receive packets or clean up transmit
*
* \param[in] pvParameters pointer to the interface data
*/
static void lpc546xx_emac_thread(void* pvParameters)
{
struct lpc_enetdata *lpc_enet = pvParameters;
for (;;) {
uint32_t flags = osThreadFlagsWait(FLAG_RX | FLAG_TX, osFlagsWaitAny, PHY_TASK_PERIOD_MS);
if (flags == osFlagsErrorTimeout) {
// Rather than calling strictly every period, we call when idle
// for that period - hopefully good enough. We run this task
// from lwIP's thread rather than our RX/TX thread, as PHY reads can
// be slow, and we don't want them to interfere with data pumping.
// This is analogous to the way the PHY polling works in the Nanostack
// version of the driver
tcpip_callback_with_block(lpc546xx_phy_task, lpc_enet->netif, 0);
continue;
}
LWIP_ASSERT("osThreadFlagsWait error", !(flags & osFlagsError));
if (flags & FLAG_RX) {
lpc546xx_packet_rx(lpc_enet);
}
if (flags & FLAG_TX) {
lpc546xx_packet_tx(lpc_enet);
}
}
}
/** \brief Low level output of a packet. Never call this from an
* interrupt context, as it may block until TX descriptors
* become available.
*
* \param[in] netif the lwip network interface structure for this lpc_enetif
* \param[in] p the MAC packet to send (e.g. IP packet including MAC addresses and type)
* \return ERR_OK if the packet could be sent or an err_t value if the packet couldn't be sent
*/
static err_t lpc546xx_low_level_output(struct netif *netif, struct pbuf *p)
{
struct lpc_enetdata *lpc_enet = netif->state;
struct pbuf *q;
uint8_t *psend = NULL, *dst;
enet_tx_bd_ring_t *txBdRing = (enet_tx_bd_ring_t *)&g_handle.txBdRing[0];
uint32_t index = txBdRing->txGenIdx;
psend = (uint8_t *)calloc(1, ENET_ALIGN(p->tot_len, ENET_BUFF_ALIGNMENT));
if (NULL == psend)
return ERR_MEM;
if (p->len == p->tot_len) {
MEMCPY(psend, p->payload, p->len);
} else {
for (q = p, dst = psend; q != NULL; q = q->next) {
MEMCPY(dst, q->payload, q->len);
dst += q->len;
}
}
/* Check if a descriptor is available for the transfer. */
osStatus_t stat = osSemaphoreAcquire(lpc_enet->xTXDCountSem.id, 0);
if (stat != osOK)
return ERR_BUF;
/* Save the buffer so that it can be freed when transmit is done */
tx_buff[index] = psend;
if (ENET_SendFrame(ENET, &g_handle, psend, p->tot_len) != kStatus_Success) {
free(psend);
tx_buff[index] = NULL;
return ERR_IF;
}
LINK_STATS_INC(link.xmit);
return ERR_OK;
}
/** \brief Ethernet receive interrupt handler
*
* This function handles the receive interrupt of LPC546XX.
*/
void enet_mac_rx_isr()
{
osThreadFlagsSet(lpc_enetdata.thread, FLAG_RX);
}
void enet_mac_tx_isr()
{
osThreadFlagsSet(lpc_enetdata.thread, FLAG_TX);
}
void ethernet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, uint8_t channel, void *param)
{
switch (event)
{
case kENET_RxIntEvent:
enet_mac_rx_isr();
break;
case kENET_TxIntEvent:
enet_mac_tx_isr();
break;
default:
break;
}
}
#if NO_SYS == 0
/** \brief Packet reception task
*
* This task is called when a packet is received. It will
* pass the packet to the LWIP core.
*
* \param[in] lpc_enet pointer to the interface data
*/
static void lpc546xx_packet_rx(struct lpc_enetdata *lpc_enet)
{
enet_rx_bd_ring_t *rxBdRing = (enet_rx_bd_ring_t *)&g_handle.rxBdRing[0];
enet_rx_bd_struct_t *bdPtr = rxBdRing->rxBdBase + rxBdRing->rxGenIdx;
bool suspend = false;
/* Suspend and command for rx. */
if (ENET->DMA_CH[0].DMA_CHX_STAT & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK) {
suspend = true;
}
while ((bdPtr->control & ENET_RXDESCRIP_WR_OWN_MASK) == 0) {
lpc546xx_enetif_input(lpc_enet->netif);
/* rxGenIdx gets updated, gets the next receive buffer descriptor */
bdPtr = rxBdRing->rxBdBase + rxBdRing->rxGenIdx;
}
/* Set command for rx when it is suspend. */
if (suspend)
{
ENET->DMA_CH[0].DMA_CHX_RXDESC_TAIL_PTR = ENET->DMA_CH[0].DMA_CHX_RXDESC_TAIL_PTR;
}
}
/** \brief Transmit cleanup task
*
* This task is called when a transmit interrupt occurs and
* reclaims the pbuf and descriptor used for the packet once
* the packet has been transferred.
*
* \param[in] lpc_enet pointer to the interface data
*/
static void lpc546xx_packet_tx(struct lpc_enetdata *lpc_enet)
{
lpc546xx_tx_reclaim(lpc_enet);
}
#endif
/** \brief Low level init of the MAC and PHY.
*
* \param[in] netif Pointer to LWIP netif structure
*/
static err_t low_level_init(struct netif *netif)
{
status_t status;
uint8_t i;
uint32_t refClock;
phy_speed_t phy_speed;
phy_duplex_t phy_duplex;
uint32_t phyAddr = 0;
bool link = false;
enet_config_t config;
uint32_t timeout = 0xFFFU;
lpc546xx_init_eth_hardware();
refClock = CLOCK_GetFreq(kCLOCK_CoreSysClk);
status = PHY_Init(ENET, phyAddr, refClock);
if (status != kStatus_Success) {
return ERR_IF;
}
ENET_GetDefaultConfig(&config);
config.multiqueueCfg = NULL;
while ((!link) && timeout) {
PHY_GetLinkStatus(ENET, phyAddr, &link);
if (link) {
/* Get link information from PHY */
PHY_GetLinkSpeedDuplex(ENET, phyAddr, &phy_speed, &phy_duplex);
/* Change the MII speed and duplex for actual link status. */
config.miiSpeed = (enet_mii_speed_t)phy_speed;
config.miiDuplex = (enet_mii_duplex_t)phy_duplex;
}
timeout--;
}
if (!link) {
return ERR_CONN;
}
AT_NONCACHEABLE_SECTION_ALIGN(static enet_rx_bd_struct_t rx_desc_start_addr[ENET_RX_RING_LEN], ENET_BUFF_ALIGNMENT);
AT_NONCACHEABLE_SECTION_ALIGN(static enet_tx_bd_struct_t tx_desc_start_addr[ENET_TX_RING_LEN], ENET_BUFF_ALIGNMENT);
/* Create buffers for each receive BD */
for (i = 0; i < ENET_RX_RING_LEN; i++) {
rx_buff[i] = pbuf_alloc(PBUF_RAW, ENET_ALIGN(ENET_ETH_MAX_FLEN, ENET_BUFF_ALIGNMENT), PBUF_RAM);
if (NULL == rx_buff[i])
return ERR_MEM;
rx_ptr[i] = (uint32_t)rx_buff[i]->payload;
}
/* prepare the buffer configuration. */
enet_buffer_config_t buffCfg = {
ENET_RX_RING_LEN,
ENET_TX_RING_LEN,
&tx_desc_start_addr[0],
&tx_desc_start_addr[0],
&rx_desc_start_addr[0],
&rx_desc_start_addr[ENET_RX_RING_LEN],
rx_ptr,
ENET_ALIGN(ENET_ETH_MAX_FLEN, ENET_BUFF_ALIGNMENT),
};
ENET_Init(ENET, &config, netif->hwaddr, refClock);
/* Enable the tx & rx interrupt. */
ENET_EnableInterrupts(ENET, kENET_DmaTx | kENET_DmaRx);
/* Create the handler. */
ENET_CreateHandler(ENET, &g_handle, &config, &buffCfg, ethernet_callback, netif);
/* Initialize Descriptor. */
ENET_DescriptorInit(ENET, &config, &buffCfg);
return ERR_OK;
}
/**
* This function is the ethernet IPv4 packet send function. It calls
* etharp_output after checking link status.
*
* \param[in] netif the lwip network interface structure for this lpc_enetif
* \param[in] q Pointer to pbug to send
* \param[in] ipaddr IP address
* \return ERR_OK or error code
*/
#if LWIP_IPV4
err_t lpc546xx_etharp_output_ipv4(struct netif *netif, struct pbuf *q,
const ip4_addr_t *ipaddr)
{
/* Only send packet is link is up */
if (netif->flags & NETIF_FLAG_LINK_UP)
return etharp_output(netif, q, ipaddr);
return ERR_CONN;
}
#endif
/**
* This function is the ethernet IPv6 packet send function. It calls
* etharp_output after checking link status.
*
* \param[in] netif the lwip network interface structure for this lpc_enetif
* \param[in] q Pointer to pbug to send
* \param[in] ipaddr IP address
* \return ERR_OK or error code
*/
#if LWIP_IPV6
err_t lpc546xx_etharp_output_ipv6(struct netif *netif, struct pbuf *q,
const ip6_addr_t *ipaddr)
{
/* Only send packet is link is up */s
if (netif->flags & NETIF_FLAG_LINK_UP)
return ethip6_output(netif, q, ipaddr);
return ERR_CONN;
}
#endif
/*******************************************************************************
* PHY task: monitor link
*******************************************************************************/
#define STATE_UNKNOWN (-1)
typedef struct {
int connected;
phy_speed_t speed;
phy_duplex_t duplex;
} PHY_STATE;
int phy_link_status(void) {
bool connection_status;
uint32_t phyAddr = 0;
PHY_GetLinkStatus(ENET, phyAddr, &connection_status);
return (int)connection_status;
}
static void lpc546xx_phy_task(void *data) {
struct netif *netif = (struct netif*)data;
static PHY_STATE prev_state = {STATE_UNKNOWN, (phy_speed_t)STATE_UNKNOWN, (phy_duplex_t)STATE_UNKNOWN};
uint32_t phyAddr = 0;
// Get current status
PHY_STATE crt_state;
bool connection_status;
PHY_GetLinkStatus(ENET, phyAddr, &connection_status);
crt_state.connected = connection_status;
// Get the actual PHY link speed
PHY_GetLinkSpeedDuplex(ENET, phyAddr, &crt_state.speed, &crt_state.duplex);
// Compare with previous state
if (crt_state.connected != prev_state.connected) {
// We're called from lwIP's tcpip thread, so can call link functions directly
if (crt_state.connected) {
netif_set_link_up(netif);
} else {
netif_set_link_down(netif);
}
}
if (crt_state.speed != prev_state.speed) {
uint32_t fes = ENET->MAC_CONFIG;
fes &= ~ENET_MAC_CONFIG_FES_MASK;
if (prev_state.speed != (phy_speed_t)STATE_UNKNOWN) {
fes |= ENET_MAC_CONFIG_FES(!crt_state.speed);
} else {
fes |= ENET_MAC_CONFIG_FES(crt_state.speed);
}
ENET->MAC_CONFIG = fes;
}
prev_state = crt_state;
}
/**
* Should be called at the beginning of the program to set up the
* network interface.
*
* This function should be passed as a parameter to netif_add().
*
* @param[in] netif the lwip network interface structure for this lpc_enetif
* @return ERR_OK if the loopif is initialized
* ERR_MEM if private data couldn't be allocated
* any other err_t on error
*/
err_t eth_arch_enetif_init(struct netif *netif)
{
err_t err;
LWIP_ASSERT("netif != NULL", (netif != NULL));
lpc_enetdata.netif = netif;
/* set MAC hardware address */
#if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
netif->hwaddr[0] = MBED_MAC_ADDR_0;
netif->hwaddr[1] = MBED_MAC_ADDR_1;
netif->hwaddr[2] = MBED_MAC_ADDR_2;
netif->hwaddr[3] = MBED_MAC_ADDR_3;
netif->hwaddr[4] = MBED_MAC_ADDR_4;
netif->hwaddr[5] = MBED_MAC_ADDR_5;
#else
mbed_mac_address((char *)netif->hwaddr);
#endif
netif->hwaddr_len = ETH_HWADDR_LEN;
/* maximum transfer unit */
netif->mtu = 1500;
/* device capabilities */
netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET;
#ifdef LWIP_IGMP
netif->flags |= NETIF_FLAG_IGMP;
#endif
#if LWIP_IPV6_MLD
netif->flags |= NETIF_FLAG_MLD6;
#endif
/* Initialize the hardware */
netif->state = &lpc_enetdata;
err = low_level_init(netif);
if (err != ERR_OK)
return err;
#if LWIP_NETIF_HOSTNAME
/* Initialize interface hostname */
netif->hostname = "lwiplpc546xx";
#endif /* LWIP_NETIF_HOSTNAME */
netif->name[0] = 'e';
netif->name[1] = 'n';
#if LWIP_IPV4
netif->output = lpc546xx_etharp_output_ipv4;
#endif
#if LWIP_IPV6
netif->output_ip6 = lpc546xx_etharp_output_ipv6;
#endif
netif->linkoutput = lpc546xx_low_level_output;
/* CMSIS-RTOS, start tasks */
#if NO_SYS == 0
memset(&lpc_enetdata.xTXDCountSem.data, 0, sizeof(lpc_enetdata.xTXDCountSem.data));
lpc_enetdata.xTXDCountSem.attr.cb_mem = &lpc_enetdata.xTXDCountSem.data;
lpc_enetdata.xTXDCountSem.attr.cb_size = sizeof(lpc_enetdata.xTXDCountSem.data);
lpc_enetdata.xTXDCountSem.id = osSemaphoreNew(ENET_TX_RING_LEN, ENET_TX_RING_LEN, &lpc_enetdata.xTXDCountSem.attr);
LWIP_ASSERT("xTXDCountSem creation error", (lpc_enetdata.xTXDCountSem.id != NULL));
err = sys_mutex_new(&lpc_enetdata.TXLockMutex);
LWIP_ASSERT("TXLockMutex creation error", (err == ERR_OK));
/* Allow the PHY task to detect the initial link state and set up the proper flags */
tcpip_callback_with_block(lpc546xx_phy_task, netif, 1);
osDelay(10);
/* Worker thread */
lpc_enetdata.thread = sys_thread_new("lpc546xx_emac_thread", lpc546xx_emac_thread, netif->state, THREAD_STACKSIZE, THREAD_PRIORITY)->id;
#endif
/* Active TX/RX. */
ENET_StartRxTx(ENET, 1, 1);
return ERR_OK;
}
void eth_arch_enable_interrupts(void) {
}
void eth_arch_disable_interrupts(void) {
}
#endif /* LWIP_ARP || LWIP_ETHERNET */

37
features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/lpc546xx_emac_config.h Normal file
View File

@ -0,0 +1,37 @@
/* mbed Microcontroller Library
* Copyright (c) 2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef LPC546XX_EMAC_CONFIG_H__
#define LPC546XX_EMAC_CONFIG_H__
#include "fsl_enet.h"
#define ENET_RX_RING_LEN (16)
#define ENET_TX_RING_LEN (8)
#define ENET_ETH_MAX_FLEN (ENET_FRAME_MAX_FRAMELEN)
#if defined(__cplusplus)
extern "C" {
#endif
int phy_link_status(void);
#if defined(__cplusplus)
}
#endif
#endif // #define LPC546XX_EMAC_CONFIG_H__

29
features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/lwipopts_conf.h Normal file
View File

@ -0,0 +1,29 @@
/* Copyright (C) 2012 mbed.org, MIT License
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge, publish, distribute,
* sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef LWIPOPTS_CONF_H
#define LWIPOPTS_CONF_H
#include "lpc546xx_emac_config.h"
#define LWIP_TRANSPORT_ETHERNET 1
#define ETH_PAD_SIZE 0
#define MEM_SIZE (ENET_RX_RING_LEN * (ENET_ETH_MAX_FLEN + ENET_BUFF_ALIGNMENT) + ENET_TX_RING_LEN * ENET_ETH_MAX_FLEN)
#endif

0
features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/lpc17_emac.c → features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPCTarget/lpc17_emac.c
View File

0
features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/lpc17xx_emac.h → features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPCTarget/lpc17xx_emac.h
View File

0
features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/lpc_emac_config.h → features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPCTarget/lpc_emac_config.h
View File

0
features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/lpc_phy.h → features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPCTarget/lpc_phy.h
View File

0
features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/lpc_phy_dp83848.c → features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPCTarget/lpc_phy_dp83848.c
View File

0
features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/lwipopts_conf.h → features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPCTarget/lwipopts_conf.h
View File

21
features/filesystem/fat/FATFileSystem.cpp
View File

@ -660,7 +660,24 @@ void FATFileSystem::dir_seek(fs_dir_t dir, off_t offset) {
FATFS_DIR *dh = static_cast<FATFS_DIR*>(dir);
lock();
dh->index = offset;
if (offset < dh->index) {
f_rewinddir(dh);
}
while (dh->index < offset) {
FILINFO finfo;
FRESULT res;
#if _USE_LFN
char lfname[NAME_MAX];
finfo.lfname = lfname;
finfo.lfsize = NAME_MAX;
#endif // _USE_LFN
res = f_readdir(dh, &finfo);
if (res != FR_OK) {
break;
} else if (finfo.fname[0] == 0) {
break;
}
}
unlock();
}
@ -678,7 +695,7 @@ void FATFileSystem::dir_rewind(fs_dir_t dir) {
FATFS_DIR *dh = static_cast<FATFS_DIR*>(dir);
lock();
dh->index = 0;
f_rewinddir(dh);
unlock();
}

938
features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp
View File

File diff suppressed because it is too large Load Diff

24
features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h
View File

@ -18,16 +18,16 @@
#ifndef USBHAL_IP_OTGFSHS_H
#define USBHAL_IP_OTGFSHS_H
//==================================================================
// This board has both USB OTG FS and HS connectors.
// Select one line only.
//==================================================================
#if defined(TARGET_DISCO_F746NG)
//#define TARGET_DISCO_F746NG_OTG_FS
#if (MBED_CONF_TARGET_USB_SPEED == 1) // Defined in json configuration file
#define TARGET_DISCO_F746NG_OTG_HS
#else
#define TARGET_DISCO_F746NG_OTG_FS
#endif
#endif
#if defined(TARGET_DISCO_F769NI) || \
#if defined(TARGET_DISCO_F429ZI) || \
defined(TARGET_DISCO_F769NI) || \
defined(TARGET_DISCO_F746NG_OTG_HS)
#define USBHAL_IRQn OTG_HS_IRQn
#else
@ -101,6 +101,11 @@ USBHAL::USBHAL(void) {
hpcd.Init.phy_itface = PCD_PHY_ULPI;
hpcd.Init.Sof_enable = 0;
hpcd.Init.speed = PCD_SPEED_HIGH;
#elif defined(TARGET_DISCO_F429ZI)
hpcd.Instance = USB_OTG_HS;
hpcd.Init.phy_itface = PCD_PHY_EMBEDDED;
hpcd.Init.Sof_enable = 0;
hpcd.Init.speed = PCD_SPEED_HIGH;
#else
hpcd.Instance = USB_OTG_FS;
hpcd.Init.phy_itface = PCD_PHY_EMBEDDED;
@ -151,6 +156,13 @@ USBHAL::USBHAL(void) {
pin_function(PA_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // SOF
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
#elif defined(TARGET_DISCO_F429ZI)
__HAL_RCC_GPIOB_CLK_ENABLE();
pin_function(PB_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_OTG_HS_FS)); // DM
pin_function(PB_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_OTG_HS_FS)); // DP
pin_function(PB_13, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); // VBUS
__HAL_RCC_USB_OTG_HS_CLK_ENABLE();
#elif defined(TARGET_DISCO_L475VG_IOT01A) || \
defined(TARGET_DISCO_L476VG)
__HAL_RCC_GPIOA_CLK_ENABLE();

1
features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h
View File

@ -28,6 +28,7 @@
defined(TARGET_NUCLEO_F767ZI) || \
defined(TARGET_NUCLEO_F746ZG) || \
defined(TARGET_DISCO_F407VG) || \
defined(TARGET_DISCO_F429ZI) || \
defined(TARGET_DISCO_F469NI) || \
defined(TARGET_DISCO_F746NG) || \
defined(TARGET_DISCO_F769NI) || \

2
features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/inc/em_usb.h
View File

@ -45,8 +45,6 @@
#define EFM32_WEAK SL_WEAK
#define EFM32_ATTRIBUTE_SECTION(X) SL_ATTRIBUTE_SECTION(X)
#include "em_int.h"
#if defined( USB_USE_PRINTF )
#include <stdio.h>
#endif

87
features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/src/em_usbd.c
View File

@ -27,6 +27,7 @@
#if defined( USB_DEVICE )
#include "em_cmu.h"
#include "em_core.h"
#include "em_usbtypes.h"
#include "em_usbhal.h"
#include "em_usbd.h"
@ -69,9 +70,10 @@ static const char *stateNames[] =
******************************************************************************/
void USBD_AbortAllTransfers( void )
{
INT_Disable();
CORE_DECLARE_IRQ_STATE;
CORE_ENTER_CRITICAL();
USBDHAL_AbortAllTransfers( USB_STATUS_EP_ABORTED );
INT_Enable();
CORE_EXIT_CRITICAL();
}
/***************************************************************************//**
@ -85,6 +87,7 @@ int USBD_AbortTransfer( int epAddr )
{
USB_XferCompleteCb_TypeDef callback;
USBD_Ep_TypeDef *ep = USBD_GetEpFromAddr( epAddr );
CORE_DECLARE_IRQ_STATE;
if ( ep == NULL )
{
@ -100,10 +103,10 @@ int USBD_AbortTransfer( int epAddr )
return USB_STATUS_ILLEGAL;
}
INT_Disable();
CORE_ENTER_CRITICAL();
if ( ep->state == D_EP_IDLE )
{
INT_Enable();
CORE_EXIT_CRITICAL();
return USB_STATUS_OK;
}
@ -125,7 +128,7 @@ int USBD_AbortTransfer( int epAddr )
callback( USB_STATUS_EP_ABORTED, ep->xferred, ep->remaining );
}
INT_Enable();
CORE_EXIT_CRITICAL();
return USB_STATUS_OK;
}
@ -139,9 +142,10 @@ int USBD_AbortTransfer( int epAddr )
******************************************************************************/
void USBD_Connect( void )
{
INT_Disable();
CORE_DECLARE_IRQ_STATE;
CORE_ENTER_CRITICAL();
USBDHAL_Connect();
INT_Enable();
CORE_EXIT_CRITICAL();
}
/***************************************************************************//**
@ -154,9 +158,10 @@ void USBD_Connect( void )
******************************************************************************/
void USBD_Disconnect( void )
{
INT_Disable();
CORE_DECLARE_IRQ_STATE;
CORE_ENTER_CRITICAL();
USBDHAL_Disconnect();
INT_Enable();
CORE_EXIT_CRITICAL();
}
/***************************************************************************//**
@ -239,6 +244,7 @@ const char *USBD_GetUsbStateName( USBD_State_TypeDef state )
int USBD_Init( const USBD_Init_TypeDef *p )
{
USBD_Ep_TypeDef *ep;
CORE_DECLARE_IRQ_STATE;
#if !defined( USB_CORECLK_HFRCO ) || !defined( CMU_OSCENCMD_USHFRCOEN )
/* Devices supporting crystal-less USB can use HFRCO or HFXO as core clock. */
@ -308,7 +314,7 @@ int USBD_Init( const USBD_Init_TypeDef *p )
*/
totalRxFifoSize += 10 + 1 + ( 2 * (MAX_NUM_OUT_EPS + 1) );
INT_Disable();
CORE_ENTER_CRITICAL();
/* Enable USB clock */
CMU->HFCORECLKEN0 |= CMU_HFCORECLKEN0_USB | CMU_HFCORECLKEN0_USBC;
@ -339,7 +345,7 @@ int USBD_Init( const USBD_Init_TypeDef *p )
}
else
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_Init(), FIFO setup error" );
EFM_ASSERT( false );
return USB_STATUS_ILLEGAL;
@ -356,7 +362,7 @@ int USBD_Init( const USBD_Init_TypeDef *p )
USBD_SetUsbState( USBD_STATE_NONE );
}
INT_Enable();
CORE_EXIT_CRITICAL();
return USB_STATUS_OK;
}
@ -389,6 +395,7 @@ int USBD_Init( const USBD_Init_TypeDef *p )
int USBD_Read( int epAddr, void *data, int byteCount,
USB_XferCompleteCb_TypeDef callback )
{
CORE_DECLARE_IRQ_STATE;
USBD_Ep_TypeDef *ep = USBD_GetEpFromAddr( epAddr );
USB_PRINTF("USBD: Read addr %x, data %p, size %d, cb 0x%lx\n",
@ -416,24 +423,25 @@ int USBD_Read( int epAddr, void *data, int byteCount,
return USB_STATUS_ILLEGAL;
}
INT_Disable();
CORE_ENTER_CRITICAL();
if ( USBDHAL_EpIsStalled( ep ) )
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_Read(), Endpoint is halted" );
return USB_STATUS_EP_STALLED;
}
if ( ep->state != D_EP_IDLE )
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_Read(), Endpoint is busy" );
return USB_STATUS_EP_BUSY;
}
if ( ( ep->num > 0 ) && ( USBD_GetUsbState() != USBD_STATE_CONFIGURED ) )
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_Read(), Device not configured" );
return USB_STATUS_DEVICE_UNCONFIGURED;
}
@ -448,7 +456,7 @@ int USBD_Read( int epAddr, void *data, int byteCount,
}
else if ( ep->in != false )
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_Read(), Illegal EP direction" );
EFM_ASSERT( false );
return USB_STATUS_ILLEGAL;
@ -458,7 +466,7 @@ int USBD_Read( int epAddr, void *data, int byteCount,
ep->xferCompleteCb = callback;
USBD_ArmEp( ep );
INT_Enable();
CORE_EXIT_CRITICAL();
return USB_STATUS_OK;
}
@ -477,22 +485,26 @@ int USBD_Read( int epAddr, void *data, int byteCount,
******************************************************************************/
int USBD_RemoteWakeup( void )
{
INT_Disable();
CORE_DECLARE_IRQ_STATE;
CORE_ENTER_CRITICAL();
if ( ( dev->state != USBD_STATE_SUSPENDED ) ||
( dev->remoteWakeupEnabled == false ) )
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_RemoteWakeup(), Illegal remote wakeup" );
return USB_STATUS_ILLEGAL;
}
USBDHAL_SetRemoteWakeup();
INT_Enable();
CORE_EXIT_CRITICAL();
USBTIMER_DelayMs( 10 );
INT_Disable();
CORE_ENTER_CRITICAL();
USBDHAL_ClearRemoteWakeup();
INT_Enable();
CORE_EXIT_CRITICAL();
return USB_STATUS_OK;
}
@ -565,6 +577,7 @@ void USBD_SetUsbState( USBD_State_TypeDef newState )
int USBD_StallEp( int epAddr )
{
USB_Status_TypeDef retVal;
CORE_DECLARE_IRQ_STATE;
USBD_Ep_TypeDef *ep = USBD_GetEpFromAddr( epAddr );
if ( ep == NULL )
@ -581,9 +594,9 @@ int USBD_StallEp( int epAddr )
return USB_STATUS_ILLEGAL;
}
INT_Disable();
CORE_ENTER_CRITICAL();
retVal = USBDHAL_StallEp( ep );
INT_Enable();
CORE_EXIT_CRITICAL();
if ( retVal != USB_STATUS_OK )
{
@ -626,6 +639,7 @@ void USBD_Stop( void )
int USBD_UnStallEp( int epAddr )
{
USB_Status_TypeDef retVal;
CORE_DECLARE_IRQ_STATE;
USBD_Ep_TypeDef *ep = USBD_GetEpFromAddr( epAddr );
if ( ep == NULL )
@ -642,9 +656,9 @@ int USBD_UnStallEp( int epAddr )
return USB_STATUS_ILLEGAL;
}
INT_Disable();
CORE_ENTER_CRITICAL();
retVal = USBDHAL_UnStallEp( ep );
INT_Enable();
CORE_EXIT_CRITICAL();
if ( retVal != USB_STATUS_OK )
{
@ -678,6 +692,7 @@ int USBD_Write( int epAddr, void *data, int byteCount,
USB_XferCompleteCb_TypeDef callback )
{
USBD_Ep_TypeDef *ep = USBD_GetEpFromAddr( epAddr );
CORE_DECLARE_IRQ_STATE;
USB_PRINTF("USBD: Write addr %x, data %p, size %d, cb 0x%lx\n",
epAddr, data, byteCount, (uint32_t)callback);
@ -704,24 +719,25 @@ int USBD_Write( int epAddr, void *data, int byteCount,
return USB_STATUS_ILLEGAL;
}
INT_Disable();
CORE_ENTER_CRITICAL();
if ( USBDHAL_EpIsStalled( ep ) )
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_Write(), Endpoint is halted" );
return USB_STATUS_EP_STALLED;
}
if ( ep->state != D_EP_IDLE )
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_Write(), Endpoint is busy" );
return USB_STATUS_EP_BUSY;
}
if ( ( ep->num > 0 ) && ( USBD_GetUsbState() != USBD_STATE_CONFIGURED ) )
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_Write(), Device not configured" );
return USB_STATUS_DEVICE_UNCONFIGURED;
}
@ -736,7 +752,7 @@ int USBD_Write( int epAddr, void *data, int byteCount,
}
else if ( ep->in != true )
{
INT_Enable();
CORE_EXIT_CRITICAL();
DEBUG_USB_API_PUTS( "\nUSBD_Write(), Illegal EP direction" );
EFM_ASSERT( false );
return USB_STATUS_ILLEGAL;
@ -746,7 +762,7 @@ int USBD_Write( int epAddr, void *data, int byteCount,
ep->xferCompleteCb = callback;
USBD_ArmEp( ep );
INT_Enable();
CORE_EXIT_CRITICAL();
return USB_STATUS_OK;
}
@ -841,6 +857,7 @@ static void USBD_ResetEndpoints(void)
int USBD_AddEndpoint(int epAddr, int transferType,
int maxPacketSize, int bufferMult)
{
CORE_DECLARE_IRQ_STATE;
USBD_Ep_TypeDef *ep;
numEps++;
@ -890,7 +907,7 @@ int USBD_AddEndpoint(int epAddr, int transferType,
ep->num, numEps, ep->in, ep->addr, ep->type, ep->packetSize, ep->fifoSize,
totalTxFifoSize, totalRxFifoSize);
INT_Disable();
CORE_ENTER_CRITICAL();
#if defined( CMU_OSCENCMD_USHFRCOEN )
/* Happy Gecko workaround: disable LEM GATE mode if using ISOC endpoints. */
if ( transferType == USB_EPTYPE_ISOC )
@ -900,7 +917,7 @@ int USBD_AddEndpoint(int epAddr, int transferType,
#endif
int ret = USBDHAL_ReconfigureFifos(totalRxFifoSize, totalTxFifoSize);
INT_Enable();
CORE_EXIT_CRITICAL();
if( ret != USB_STATUS_OK ) {
return ret;

8
features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/src/em_usbdint.c
View File

@ -27,6 +27,7 @@
#if defined( USB_DEVICE )
#include "em_cmu.h"
#include "em_core.h"
#include "em_usbtypes.h"
#include "em_usbhal.h"
#include "em_usbd.h"
@ -106,8 +107,9 @@ void USB_IRQHandler( void )
{
uint32_t status;
bool servedVbusInterrupt = false;
CORE_DECLARE_IRQ_STATE;
INT_Disable();
CORE_ENTER_CRITICAL();
#if ( USB_PWRSAVE_MODE )
if ( USBD_poweredDown )
@ -192,7 +194,7 @@ void USB_IRQHandler( void )
status = USBHAL_GetCoreInts();
if ( status == 0 )
{
INT_Enable();
CORE_EXIT_CRITICAL();
if ( !servedVbusInterrupt )
{
DEBUG_USB_INT_LO_PUTS( "\nSinT" );
@ -209,7 +211,7 @@ void USB_IRQHandler( void )
HANDLE_INT( USB_GINTSTS_IEPINT )
HANDLE_INT( USB_GINTSTS_OEPINT )
INT_Enable();
CORE_EXIT_CRITICAL();
if ( status != 0 )
{

4
features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/src/em_usbhal.c
View File

@ -199,9 +199,7 @@ USB_Status_TypeDef USBDHAL_CoreInit( uint32_t totalRxFifoSize,
USB_GUSBCFG_FORCEDEVMODE;
#endif
INT_Enable();
USBTIMER_DelayMs( 50 );
INT_Disable();
/* Set device speed */
USB->DCFG = ( USB->DCFG & ~_USB_DCFG_DEVSPD_MASK ) | 3; /* Full speed PHY */
@ -649,9 +647,7 @@ USB_Status_TypeDef USBHHAL_CoreInit( uint32_t rxFifoSize,
~(GUSBCFG_WO_BITMASK | USB_GUSBCFG_FORCEDEVMODE ) ) |
USB_GUSBCFG_FORCEHSTMODE;
INT_Enable();
USBTIMER_DelayMs( 100 );
INT_Disable();
/* Set 48 MHz PHY clock, FS/LS mode */
USB->HCFG = ( USB->HCFG & ~_USB_HCFG_FSLSPCLKSEL_MASK ) |

18
features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/src/em_usbtimer.c
View File

@ -25,6 +25,7 @@
#include "em_usb.h"
#if defined( USB_DEVICE ) || defined( USB_HOST )
#include "em_cmu.h"
#include "em_core.h"
#include "em_timer.h"
#include "em_usbtypes.h"
#include "em_usbhal.h"
@ -244,8 +245,9 @@ void USBTIMER_Start( uint32_t id, uint32_t timeout,
{
uint32_t accumulated;
USBTIMER_Timer_TypeDef *this, **last;
CORE_DECLARE_IRQ_STATE;
INT_Disable();
CORE_ENTER_CRITICAL();
if ( timers[ id ].running )
{
@ -255,7 +257,7 @@ void USBTIMER_Start( uint32_t id, uint32_t timeout,
if ( timeout == 0 )
{
callback();
INT_Enable();
CORE_EXIT_CRITICAL();
return;
}
@ -297,7 +299,7 @@ void USBTIMER_Start( uint32_t id, uint32_t timeout,
}
}
INT_Enable();
CORE_EXIT_CRITICAL();
}
/***************************************************************************//**
@ -310,8 +312,9 @@ void USBTIMER_Start( uint32_t id, uint32_t timeout,
void USBTIMER_Stop( uint32_t id )
{
USBTIMER_Timer_TypeDef *this, **last;
CORE_DECLARE_IRQ_STATE;
INT_Disable();
CORE_ENTER_CRITICAL();
if ( head ) /* Queue empty ? */
{
@ -335,7 +338,7 @@ void USBTIMER_Stop( uint32_t id )
}
}
INT_Enable();
CORE_EXIT_CRITICAL();
}
#endif /* ( NUM_QTIMERS > 0 ) */
@ -347,8 +350,9 @@ void USBTIMER_Stop( uint32_t id )
static void TimerTick( void )
{
USBTIMER_Callback_TypeDef cb;
CORE_DECLARE_IRQ_STATE;
INT_Disable();
CORE_ENTER_CRITICAL();
if ( head )
{
@ -372,7 +376,7 @@ static void TimerTick( void )
}
}
INT_Enable();
CORE_EXIT_CRITICAL();
}
/** @endcond */
#endif /* ( NUM_QTIMERS > 0 ) */

4
mbed.h
View File

@ -16,13 +16,13 @@
#ifndef MBED_H
#define MBED_H
#define MBED_LIBRARY_VERSION 156
#define MBED_LIBRARY_VERSION 157
#if MBED_CONF_RTOS_PRESENT
// RTOS present, this is valid only for mbed OS 5
#define MBED_MAJOR_VERSION 5
#define MBED_MINOR_VERSION 6
#define MBED_PATCH_VERSION 5
#define MBED_PATCH_VERSION 6
#else
// mbed 2

6
platform/mbed_retarget.cpp
View File

@ -940,7 +940,11 @@ extern "C" WEAK void __iar_file_Mtxdst(__iar_Rmtx *mutex) {}
extern "C" WEAK void __iar_file_Mtxlock(__iar_Rmtx *mutex) {}
extern "C" WEAK void __iar_file_Mtxunlock(__iar_Rmtx *mutex) {}
#if defined(__IAR_SYSTEMS_ICC__ ) && (__VER__ >= 8000000)
extern "C" WEAK void *__aeabi_read_tp (void) { return NULL ;}
#pragma section="__iar_tls$$DATA"
extern "C" WEAK void *__aeabi_read_tp (void) {
// Thread Local storage is not supported, using main thread memory for errno
return __section_begin("__iar_tls$$DATA");
}
#endif
#elif defined(__CC_ARM)
// Do nothing

38
rtos/TARGET_CORTEX/mbed_boot.c
View File

@ -168,6 +168,7 @@
#include "cmsis_os2.h"
#include "mbed_toolchain.h"
#include "mbed_error.h"
#include "mbed_critical.h"
#if defined(__IAR_SYSTEMS_ICC__ ) && (__VER__ >= 8000000)
#include <DLib_Threads.h>
#endif
@ -423,6 +424,7 @@ void __rt_entry (void) {
}
typedef void *mutex;
mutex _static_mutexes[OS_MUTEX_NUM] = {NULL};
/* ARM toolchain requires dynamically created mutexes to enforce thread safety. There's
up to 8 static mutexes, protecting atexit, signalinit, stdin, stdout, stderr, stream_list,
@ -441,10 +443,24 @@ int _mutex_initialize(mutex *m)
attr.name = "ARM toolchain mutex";
attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust;
mutex *slot = NULL;
core_util_critical_section_enter();
for (int i = 0; i < OS_MUTEX_NUM; i++) {
if (_static_mutexes[i] == NULL) {
_static_mutexes[i] = (mutex)-1; // dummy value to reserve slot
slot = &_static_mutexes[i];
break;
}
}
core_util_critical_section_exit();
if (slot != NULL) {
*m = osMutexNew(&attr);
*slot = *m;
if (*m != NULL) {
return 1;
}
}
/* Mutex pool exhausted, try using HEAP */
attr.cb_size = sizeof(mbed_rtos_storage_mutex_t);
@ -463,6 +479,28 @@ int _mutex_initialize(mutex *m)
return 1;
}
void _mutex_free(mutex *m) {
mutex *slot = NULL;
core_util_critical_section_enter();
for (int i = 0; i < OS_MUTEX_NUM; i++) {
if (_static_mutexes[i] == *m) {
slot = &_static_mutexes[i];
break;
}
}
core_util_critical_section_exit();
osMutexDelete(*m);
// if no slot reserved for mutex, must have been dynamically allocated
if (!slot) {
free(m);
} else {
*slot = NULL;
}
}
#endif /* ARMC */
#elif defined (__GNUC__) /******************** GCC ********************/

1
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/trng_api.c
View File

@ -50,6 +50,7 @@ void trng_free(trng_t *obj)
*/
static void trng_get_byte(unsigned char *byte)
{
*byte = 0;
size_t bit;
/* 34.5 Steps 3-4-5: poll SR and read from OR when ready */

12
targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c
View File

@ -103,8 +103,6 @@ void lp_ticker_init(void)
// Schedule wakeup to match semantics of lp_ticker_get_compare_match()
lp_ticker_set_interrupt(wakeup_tick);
}
timestamp_t lp_ticker_read()
@ -144,21 +142,13 @@ timestamp_t lp_ticker_read()
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
uint32_t now = lp_ticker_read();
uint32_t delta = timestamp - lp_ticker_read();
wakeup_tick = timestamp;
TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
int delta = (int) (timestamp - now);
if (delta > 0) {
cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
lp_ticker_arm_cd();
} else {
// NOTE: With lp_ticker_fire_interrupt() introduced, upper layer would handle past event case.
// This code fragment gets redundant, but it is still kept here for backward-compatible.
void lp_ticker_fire_interrupt(void);
lp_ticker_fire_interrupt();
}
}
void lp_ticker_fire_interrupt(void)

31
targets/TARGET_NUVOTON/TARGET_M480/trng_api.c
View File

@ -25,9 +25,17 @@
/*
* Get Random number generator.
*/
#define PRNG_KEY_SIZE (0x20UL)
static volatile int g_PRNG_done;
volatile int g_AES_done;
/* Implementation that should never be optimized out by the compiler */
static void trng_zeroize( void *v, size_t n ) {
volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
}
void CRYPTO_IRQHandler()
{
if (PRNG_GET_INT_FLAG()) {
@ -77,21 +85,22 @@ void trng_free(trng_t *obj)
int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
{
(void)obj;
unsigned char tmpBuff[PRNG_KEY_SIZE];
size_t cur_length = 0;
*output_length = 0;
if (length < 32) {
unsigned char tmpBuff[32];
trng_get(tmpBuff);
memcpy(output, &tmpBuff, length);
*output_length = length;
} else {
for (unsigned i = 0; i < (length/32); i++) {
while (length >= sizeof(tmpBuff)) {
trng_get(output);
*output_length += 32;
output += 32;
output += sizeof(tmpBuff);
cur_length += sizeof(tmpBuff);
length -= sizeof(tmpBuff);
}
if (length > 0) {
trng_get(tmpBuff);
memcpy(output, tmpBuff, length);
cur_length += length;
trng_zeroize(tmpBuff, sizeof(tmpBuff));
}
*output_length = cur_length;
return 0;
}

9
targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c
View File

@ -147,16 +147,9 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
{
TIMER_Stop((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
int delta = (int) (timestamp - us_ticker_read());
if (delta > 0) {
uint32_t delta = timestamp - us_ticker_read();
cd_major_minor_us = delta * US_PER_TICK;
us_ticker_arm_cd();
} else {
// NOTE: With us_ticker_fire_interrupt() introduced, upper layer would handle past event case.
// This code fragment gets redundant, but it is still kept here for backward-compatible.
void us_ticker_fire_interrupt(void);
us_ticker_fire_interrupt();
}
}
void us_ticker_fire_interrupt(void)

31
targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c
View File

@ -30,9 +30,17 @@
/*
* Get Random number generator.
*/
#define PRNG_KEY_SIZE (0x20UL)
static volatile int g_PRNG_done;
volatile int g_AES_done;
/* Implementation that should never be optimized out by the compiler */
static void trng_zeroize( void *v, size_t n ) {
volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
}
void CRYPTO_IRQHandler()
{
if (PRNG_GET_INT_FLAG()) {
@ -82,21 +90,22 @@ void trng_free(trng_t *obj)
int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
{
(void)obj;
unsigned char tmpBuff[PRNG_KEY_SIZE];
size_t cur_length = 0;
*output_length = 0;
if (length < 32) {
unsigned char tmpBuff[32];
trng_get(tmpBuff);
memcpy(output, &tmpBuff, length);
*output_length = length;
} else {
for (int i = 0; i < (length/32); i++) {
while (length >= sizeof(tmpBuff)) {
trng_get(output);
*output_length += 32;
output += 32;
output += sizeof(tmpBuff);
cur_length += sizeof(tmpBuff);
length -= sizeof(tmpBuff);
}
if (length > 0) {
trng_get(tmpBuff);
memcpy(output, tmpBuff, length);
cur_length += length;
trng_zeroize(tmpBuff, sizeof(tmpBuff));
}
*output_length = cur_length;
return 0;
}

234
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/crc.c Normal file
View File

@ -0,0 +1,234 @@
/**********************************************************************
*
* Filename: crc.c
*
* Description: Slow and fast implementations of the CRC standards.
*
* Notes: The parameters for each supported CRC standard are
* defined in the header file crc.h. The implementations
* here should stand up to further additions to that list.
*
*
* Copyright (c) 2000 by Michael Barr. This software is placed into
* the public domain and may be used for any purpose. However, this
* notice must not be changed or removed and no warranty is either
* expressed or implied by its publication or distribution.
**********************************************************************/
#include "crc.h"
/*
* Derive parameters from the standard-specific parameters in crc.h.
*/
#define WIDTH (8 * sizeof(crc))
#define TOPBIT (1 << (WIDTH - 1))
#if (REFLECT_DATA == TRUE)
#undef REFLECT_DATA
#define REFLECT_DATA(X) ((unsigned char) reflect((X), 8))
#else
#undef REFLECT_DATA
#define REFLECT_DATA(X) (X)
#endif
#if (REFLECT_REMAINDER == TRUE)
#undef REFLECT_REMAINDER
#define REFLECT_REMAINDER(X) ((crc) reflect((X), WIDTH))
#else
#undef REFLECT_REMAINDER
#define REFLECT_REMAINDER(X) (X)
#endif
/*********************************************************************
*
* Function: reflect()
*
* Description: Reorder the bits of a binary sequence, by reflecting
* them about the middle position.
*
* Notes: No checking is done that nBits <= 32.
*
* Returns: The reflection of the original data.
*
*********************************************************************/
static unsigned long
reflect(unsigned long data, unsigned char nBits)
{
unsigned long reflection = 0x00000000;
unsigned char bit;
/*
* Reflect the data about the center bit.
*/
for (bit = 0; bit < nBits; ++bit)
{
/*
* If the LSB bit is set, set the reflection of it.
*/
if (data & 0x01)
{
reflection |= (1 << ((nBits - 1) - bit));
}
data = (data >> 1);
}
return (reflection);
} /* reflect() */
/*********************************************************************
*
* Function: crcSlow()
*
* Description: Compute the CRC of a given message.
*
* Notes:
*
* Returns: The CRC of the message.
*
*********************************************************************/
crc
crcSlow(unsigned char const message[], int nBytes)
{
crc remainder = INITIAL_REMAINDER;
int byte;
unsigned char bit;
/*
* Perform modulo-2 division, a byte at a time.
*/
for (byte = 0; byte < nBytes; ++byte)
{
/*
* Bring the next byte into the remainder.
*/
remainder ^= (REFLECT_DATA(message[byte]) << (WIDTH - 8));
/*
* Perform modulo-2 division, a bit at a time.
*/
for (bit = 8; bit > 0; --bit)
{
/*
* Try to divide the current data bit.
*/
if (remainder & TOPBIT)
{
remainder = (remainder << 1) ^ POLYNOMIAL;
}
else
{
remainder = (remainder << 1);
}
}
}
/*
* The final remainder is the CRC result.
*/
return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
} /* crcSlow() */
crc crcTable[256];
/*********************************************************************
*
* Function: crcInit()
*
* Description: Populate the partial CRC lookup table.
*
* Notes: This function must be rerun any time the CRC standard
* is changed. If desired, it can be run "offline" and
* the table results stored in an embedded system's ROM.
*
* Returns: None defined.
*
*********************************************************************/
void
crcInit(void)
{
crc remainder;
int dividend;
unsigned char bit;
/*
* Compute the remainder of each possible dividend.
*/
for (dividend = 0; dividend < 256; ++dividend)
{
/*
* Start with the dividend followed by zeros.
*/
remainder = dividend << (WIDTH - 8);
/*
* Perform modulo-2 division, a bit at a time.
*/
for (bit = 8; bit > 0; --bit)
{
/*
* Try to divide the current data bit.
*/
if (remainder & TOPBIT)
{
remainder = (remainder << 1) ^ POLYNOMIAL;
}
else
{
remainder = (remainder << 1);
}
}
/*
* Store the result into the table.
*/
crcTable[dividend] = remainder;
}
} /* crcInit() */
/*********************************************************************
*
* Function: crcFast()
*
* Description: Compute the CRC of a given message.
*
* Notes: crcInit() must be called first.
*
* Returns: The CRC of the message.
*
*********************************************************************/
crc
crcFast(unsigned char const message[], int nBytes)
{
crc remainder = INITIAL_REMAINDER;
unsigned char data;
int byte;
/*
* Divide the message by the polynomial, a byte at a time.
*/
for (byte = 0; byte < nBytes; ++byte)
{
data = REFLECT_DATA(message[byte]) ^ (remainder >> (WIDTH - 8));
remainder = crcTable[data] ^ (remainder << 8);
}
/*
* The final remainder is the CRC.
*/
return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
} /* crcFast() */

77
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/crc.h Normal file
View File

@ -0,0 +1,77 @@
/**********************************************************************
*
* Filename: crc.h
*
* Description: A header file describing the various CRC standards.
*
* Notes:
*
*
* Copyright (c) 2000 by Michael Barr. This software is placed into
* the public domain and may be used for any purpose. However, this
* notice must not be changed or removed and no warranty is either
* expressed or implied by its publication or distribution.
**********************************************************************/
#ifndef _crc_h
#define _crc_h
#define FALSE 0
#define TRUE !FALSE
/*
* Select the CRC standard from the list that follows.
*/
#define CRC16
#if defined(CRC_CCITT)
typedef unsigned short crc;
#define CRC_NAME "CRC-CCITT"
#define POLYNOMIAL 0x1021
#define INITIAL_REMAINDER 0xFFFF
#define FINAL_XOR_VALUE 0x0000
#define REFLECT_DATA FALSE
#define REFLECT_REMAINDER FALSE
#define CHECK_VALUE 0x29B1
#elif defined(CRC16)
typedef unsigned short crc;
#define CRC_NAME "CRC-16"
#define POLYNOMIAL 0x8005
#define INITIAL_REMAINDER 0x0000
#define FINAL_XOR_VALUE 0x0000
#define REFLECT_DATA TRUE
#define REFLECT_REMAINDER TRUE
#define CHECK_VALUE 0xBB3D
#elif defined(CRC32)
typedef unsigned long crc;
#define CRC_NAME "CRC-32"
#define POLYNOMIAL 0x04C11DB7
#define INITIAL_REMAINDER 0xFFFFFFFF
#define FINAL_XOR_VALUE 0xFFFFFFFF
#define REFLECT_DATA TRUE
#define REFLECT_REMAINDER TRUE
#define CHECK_VALUE 0xCBF43926
#else
#error "One of CRC_CCITT, CRC16, or CRC32 must be #define'd."
#endif
void crcInit(void);
crc crcSlow(unsigned char const message[], int nBytes);
crc crcFast(unsigned char const message[], int nBytes);
#endif /* _crc_h */

278
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/fsl_phy.c Normal file
View File

@ -0,0 +1,278 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_phy.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Defines the timeout macro. */
#define PHY_TIMEOUT_COUNT 0xFFFFFFU
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get the ENET instance from peripheral base address.
*
* @param base ENET peripheral base address.
* @return ENET instance.
*/
extern uint32_t ENET_GetInstance(ENET_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to enet clocks for each instance. */
#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_LPC_ENET_COUNT];
#endif
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
******************************************************************************/
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
{
uint32_t reg;
uint32_t idReg = 0;
uint32_t delay = PHY_TIMEOUT_COUNT;
uint32_t instance = ENET_GetInstance(base);
bool status = false;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Set SMI first. */
CLOCK_EnableClock(s_enetClock[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
ENET_SetSMI(base, srcClock_Hz, false);
#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
ENET_SetSMI(base);
#endif
/* Initialization after PHY stars to work. */
while ((idReg != PHY_CONTROL_ID1) && (delay != 0))
{
PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
delay --;
}
if (!delay)
{
return kStatus_Fail;
}
delay = PHY_TIMEOUT_COUNT;
/* Reset PHY and wait until completion. */
PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
do
{
PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &reg);
} while (delay-- && reg & PHY_BCTL_RESET_MASK);
if (!delay)
{
return kStatus_Fail;
}
/* Set the ability. */
PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, (PHY_ALL_CAPABLE_MASK | 0x1U));
/* Start Auto negotiation and wait until auto negotiation completion */
PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
delay = PHY_TIMEOUT_COUNT;
do
{
PHY_Read(base, phyAddr, PHY_SEPCIAL_CONTROL_REG, &reg);
delay --;
} while (delay && ((reg & PHY_SPECIALCTL_AUTONEGDONE_MASK) == 0));
if (!delay)
{
return kStatus_Fail;
}
/* Waiting a moment for phy stable. */
for (delay = 0; delay < PHY_TIMEOUT_COUNT; delay++)
{
__ASM("nop");
PHY_GetLinkStatus(base, phyAddr, &status);
if (status)
{
break;
}
}
return kStatus_Success;
}
status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
{
#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
uint32_t counter;
/* Clear the SMI interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
/* Starts a SMI write command. */
ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data);
/* Wait for SMI complete. */
for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
{
if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
{
break;
}
}
/* Check for timeout. */
if (!counter)
{
return kStatus_PHY_SMIVisitTimeout;
}
/* Clear MII interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
ENET_StartSMIWrite(base, phyAddr, phyReg, data);
while (ENET_IsSMIBusy(base))
;
#endif
return kStatus_Success;
}
status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr)
{
#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
assert(dataPtr);
uint32_t counter;
/* Clear the MII interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
/* Starts a SMI read command operation. */
ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame);
/* Wait for MII complete. */
for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
{
if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
{
break;
}
}
/* Check for timeout. */
if (!counter)
{
return kStatus_PHY_SMIVisitTimeout;
}
/* Get data from MII register. */
*dataPtr = ENET_ReadSMIData(base);
/* Clear MII interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
ENET_StartSMIRead(base, phyAddr, phyReg);
while (ENET_IsSMIBusy(base))
;
*dataPtr = ENET_ReadSMIData(base);
#endif
return kStatus_Success;
}
status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status)
{
uint32_t reg;
status_t result = kStatus_Success;
/* Read the basic status register. */
result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &reg);
if (result == kStatus_Success)
{
if (reg & PHY_BSTATUS_LINKSTATUS_MASK)
{
/* link up. */
*status = true;
}
else
{
*status = false;
}
}
return result;
}
status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex)
{
assert(duplex);
assert(speed);
uint32_t reg;
status_t result = kStatus_Success;
/* Read the control two register. */
result = PHY_Read(base, phyAddr, PHY_SEPCIAL_CONTROL_REG, &reg);
if (result == kStatus_Success)
{
if (reg & PHY_SPECIALCTL_DUPLEX_MASK)
{
/* Full duplex. */
*duplex = kPHY_FullDuplex;
}
else
{
/* Half duplex. */
*duplex = kPHY_HalfDuplex;
}
if (reg & PHY_SPECIALCTL_100SPEED_MASK)
{
/* 100M speed. */
*speed = kPHY_Speed100M;
}
else
{ /* 10M speed. */
*speed = kPHY_Speed10M;
}
}
return result;
}

183
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/fsl_phy.h Normal file
View File

@ -0,0 +1,183 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _FSL_PHY_H_
#define _FSL_PHY_H_
#include "fsl_enet.h"
/*!
* @addtogroup phy_driver
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief PHY driver version */
#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
/*! @brief Defines the PHY registers. */
#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */
#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */
#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */
#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */
#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
#define PHY_SEPCIAL_CONTROL_REG 0x1FU /*!< The PHY control two register. */
#define PHY_CONTROL_ID1 0x07U /*!< The PHY ID1*/
/*! @brief Defines the mask flag in basic control register. */
#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */
#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */
#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */
#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */
#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */
/*!@brief Defines the mask flag of operation mode in special control register*/
#define PHY_SPECIALCTL_AUTONEGDONE_MASK 0x1000U /*!< The PHY auto-negotiation complete mask. */
#define PHY_SPECIALCTL_DUPLEX_MASK 0x0010U /*!< The PHY duplex mask. */
#define PHY_SPECIALCTL_100SPEED_MASK 0x0008U /*!< The PHY speed mask. */
#define PHY_SPECIALCTL_10SPEED_MASK 0x0004U /*!< The PHY speed mask. */
#define PHY_SPECIALCTL_SPEEDUPLX_MASK 0x001cU /*!< The PHY speed and duplex mask. */
/*! @brief Defines the mask flag in basic status register. */
#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */
/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
#define PHY_ALL_CAPABLE_MASK 0x1e0U
/*! @brief Defines the PHY status. */
enum _phy_status
{
kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 0), /*!< ENET PHY SMI visit timeout. */
};
/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */
typedef enum _phy_speed {
kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */
kPHY_Speed100M /*!< ENET PHY 100M speed. */
} phy_speed_t;
/*! @brief Defines the PHY link duplex. */
typedef enum _phy_duplex {
kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */
kPHY_FullDuplex /*!< ENET PHY full duplex. */
} phy_duplex_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name PHY Driver
* @{
*/
/*!
* @brief Initializes PHY.
*
* This function initialize the SMI interface and initialize PHY.
* The SMI is the MII management interface between PHY and MAC, which should be
* firstly initialized before any other operation for PHY.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI.
* @retval kStatus_Success PHY initialize success
* @retval kStatus_Fail PHY initialize fail
*/
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz);
/*!
* @brief PHY Write function. This function write data over the SMI to
* the specified PHY register. This function is called by all PHY interfaces.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param phyReg The PHY register.
* @param data The data written to the PHY register.
* @retval kStatus_Success PHY write success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
/*!
* @brief PHY Read function. This interface read data over the SMI from the
* specified PHY register. This function is called by all PHY interfaces.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param phyReg The PHY register.
* @param dataPtr The address to store the data read from the PHY register.
* @retval kStatus_Success PHY read success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);
/*!
* @brief Gets the PHY link status.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param status The link up or down status of the PHY.
* - true the link is up.
* - false the link is down.
* @retval kStatus_Success PHY get link status success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status);
/*!
* @brief Gets the PHY link speed and duplex.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param speed The address of PHY link speed.
* @param duplex The link duplex of PHY.
* @retval kStatus_Success PHY get link speed and duplex success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex);
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* _FSL_PHY_H_ */

48
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c
View File

@ -17,6 +17,10 @@
#include "clock_config.h"
#include "fsl_emc.h"
#include "fsl_power.h"
#include "fsl_flashiap.h"
#define CRC16
#include "crc.h"
/*******************************************************************************
* Definitions
@ -37,6 +41,18 @@
#define SDRAM_MODEREG_VALUE (0x23u)
#define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/
uint32_t FLASHIAP_ReadUid(uint32_t *addr)
{
uint32_t command[5], result[5];
command[0] = kIapCmd_FLASHIAP_ReadUid;
iap_entry(command, result);
memcpy(addr, &result[1], (sizeof(uint32_t) * 4));
return result[0];
}
// called before main
void mbed_sdk_init()
{
@ -59,6 +75,38 @@ void rtc_setup_oscillator(void)
SYSCON->RTCOSCCTRL |= SYSCON_RTCOSCCTRL_EN_MASK;
}
// Provide ethernet devices with a semi-unique MAC address from the UUID
void mbed_mac_address(char *mac)
{
uint16_t MAC[3]; // 3 16 bits words for the MAC
uint32_t UID[4];
// get UID via ISP commands
FLASHIAP_ReadUid(UID);
// generate three CRC16's using different slices of the UUID
MAC[0] = crcSlow((const uint8_t *)UID, 8); // most significant half-word
MAC[1] = crcSlow((const uint8_t *)UID, 12);
MAC[2] = crcSlow((const uint8_t *)UID, 16); // least significant half word
// The network stack expects an array of 6 bytes
// so we copy, and shift and copy from the half-word array to the byte array
mac[0] = MAC[0] >> 8;
mac[1] = MAC[0];
mac[2] = MAC[1] >> 8;
mac[3] = MAC[1];
mac[4] = MAC[2] >> 8;
mac[5] = MAC[2];
// We want to force bits [1:0] of the most significant byte [0]
// to be "10"
// http://en.wikipedia.org/wiki/MAC_address
mac[0] |= 0x02; // force bit 1 to a "1" = "Locally Administered"
mac[0] &= 0xFE; // force bit 0 to a "0" = Unicast
}
void ADC_ClockPower_Configuration(void)
{
/* SYSCON power. */

117
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.h
View File

@ -194,6 +194,123 @@ typedef int32_t status_t;
#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
/* @} */
/*! @name Alignment variable definition macros */
/* @{ */
#if (defined(__ICCARM__))
/**
* Workaround to disable MISRA C message suppress warnings for IAR compiler.
* http://supp.iar.com/Support/?note=24725
*/
_Pragma("diag_suppress=Pm120")
#define SDK_PRAGMA(x) _Pragma(#x)
_Pragma("diag_error=Pm120")
/*! Macro to define a variable with alignbytes alignment */
#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
/*! Macro to define a variable with L1 d-cache line size alignment */
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
#endif
/*! Macro to define a variable with L2 cache line size alignment */
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
#endif
#elif defined(__ARMCC_VERSION)
/*! Macro to define a variable with alignbytes alignment */
#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var
/*! Macro to define a variable with L1 d-cache line size alignment */
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
#endif
/*! Macro to define a variable with L2 cache line size alignment */
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
#endif
#elif defined(__GNUC__)
/*! Macro to define a variable with alignbytes alignment */
#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
/*! Macro to define a variable with L1 d-cache line size alignment */
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
#endif
/*! Macro to define a variable with L2 cache line size alignment */
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
#endif
#else
#error Toolchain not supported
#define SDK_ALIGN(var, alignbytes) var
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
#define SDK_L1DCACHE_ALIGN(var) var
#endif
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
#define SDK_L2CACHE_ALIGN(var) var
#endif
#endif
/*! Macro to change a value to a given size aligned value */
#define SDK_SIZEALIGN(var, alignbytes) \
((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
/* @} */
/*! @name Non-cacheable region definition macros */
/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
* "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
* please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
* will be initialized to zero in system startup.
*/
/* @{ */
#if (defined(__ICCARM__))
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
#else
#define AT_NONCACHEABLE_SECTION(var) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
#define AT_NONCACHEABLE_SECTION_INIT(var) var
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
#endif
#elif(defined(__ARMCC_VERSION))
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
__attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
__attribute__((section("NonCacheable.init"))) __align(alignbytes) var
#else
#define AT_NONCACHEABLE_SECTION(var) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var
#define AT_NONCACHEABLE_SECTION_INIT(var) var
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var
#endif
#elif(defined(__GNUC__))
/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
* in your projects to make sure the non-cacheable section variables will be initialized in system startup.
*/
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
__attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
__attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
#else
#define AT_NONCACHEABLE_SECTION(var) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
#define AT_NONCACHEABLE_SECTION_INIT(var) var
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))
#endif
#else
#error Toolchain not supported.
#define AT_NONCACHEABLE_SECTION(var) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
#define AT_NONCACHEABLE_SECTION_INIT(var) var
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var
#endif
/* @} */
/*******************************************************************************
* API
******************************************************************************/

8
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/analogin_api.c
View File

@ -38,6 +38,13 @@ void analogin_init(analogin_t *obj, PinName pin)
uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT;
adc_config_t adc_config;
uint32_t reg;
uint32_t pin_number = pin & 0x1F;
uint8_t port_number = pin / 32;
/* Clear the DIGIMODE bit */
reg = IOCON->PIO[port_number][pin_number] & ~IOCON_PIO_DIGIMODE_MASK;
IOCON->PIO[port_number][pin_number] = reg;
ADC_ClockPower_Configuration();
@ -69,6 +76,7 @@ uint16_t analogin_read_u16(analogin_t *obj)
adcConvSeqConfigStruct.interruptMode = kADC_InterruptForEachSequence;
ADC_SetConvSeqAConfig(adc_addrs[instance], &adcConvSeqConfigStruct);
ADC_EnableConvSeqA(adc_addrs[instance], true);
ADC_DoSoftwareTriggerConvSeqA(adc_addrs[instance]);
/* Wait for the converter to be done. */

61
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/PinNames.h
View File

@ -50,6 +50,7 @@ typedef enum {
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = (PORT_A<<4|0),
PA_1 = (PORT_A<<4|1),
@ -167,33 +168,8 @@ typedef enum {
DA_0 = (PORT_U<<4|0),
DA_1 = (PORT_U<<4|1),
// Arduino connector namings
A0 = AD_2,//A0 and A1 are connected
A1 = AD_2,
A2 = AD_3,
D0 = PA_6,
D1 = PA_7,
D2 = PA_5,
D3 = PD_4,
D4 = PD_5,
D5 = PA_4,
D6 = PA_3,
D7 = PA_2,
D8 = PB_4,
D9 = PB_5,
D10 = PC_0,
D11 = PC_2,
D12 = PC_3,
D13 = PC_1,
D14 = PB_3,
D15 = PB_2,
D16 = PA_1,
D17 = PA_0,
D18 = PE_5,
// Not connected
NC = (uint32_t)0xFFFFFFFF,
// Generic signals namings
/* LED1~4 are defined as alias of GPIO pins, they are not the LEDs on board*/
@ -213,8 +189,35 @@ typedef enum {
SPI_CS = PC_0,
PWM_OUT = PD_4,
// Not connected
NC = (uint32_t)0xFFFFFFFF
// Arduino connector namings
A0 = AD_2,//A0 and A1 are connected
A1 = AD_2,
A2 = AD_3,
A3 = NC,
A4 = NC,
A5 = NC,
D0 = PA_6,
D1 = PA_7,
D2 = PA_5,
D3 = PD_4,
D4 = PD_5,
D5 = PA_4,
D6 = PA_3,
D7 = PA_2,
D8 = PB_4,
D9 = PB_5,
D10 = PC_0,
D11 = PC_2,
D12 = PC_3,
D13 = PC_1,
D14 = PB_3,
D15 = PB_2,
D16 = PA_1,
D17 = PA_0,
D18 = PE_5
} PinName;
typedef enum {

3
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a.h
View File

@ -43,8 +43,7 @@
#include "rtl8195a_compiler.h"
#include "rtl8195a_platform.h"
#include "rtl8195a_crypto.h"
#define REG32(reg) (*(volatile uint32_t *)(reg))
#define REG16(reg) (*(volatile uint16_t *)(reg))

24
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_crypto.h Normal file
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@ -0,0 +1,24 @@
/* mbed Microcontroller Library
* Copyright (c) 2013-2017 Realtek Semiconductor Corp.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_RTL8195A_CRYPTO_H
#define MBED_RTL8195A_CRYPTO_H
extern _LONG_CALL_ uint32_t crc32_get(uint8_t *buf, int len);
#endif

141
targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c
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@ -13,7 +13,6 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdio.h>
#include <string.h>
#include "mbed_wait_api.h"
@ -24,61 +23,105 @@
static flash_t flash_obj;
void OTA_GetImageInfo(imginfo_t *info)
void OTA_ReadHeader(uint32_t base, imginfo_t *img)
{
uint32_t ver_hi, ver_lo;
uint32_t epoch_hi, epoch_lo;
flash_ext_read_word(&flash_obj, info->base + TAG_OFS, &info->tag);
flash_ext_read_word(&flash_obj, info->base + VER_OFS, &ver_lo);
flash_ext_read_word(&flash_obj, info->base + VER_OFS + 4, &ver_hi);
if (base != OTA_REGION1_BASE || base != OTA_REGION2_BASE) {
return;
}
if (info->tag == TAG_DOWNLOAD) {
info->ver = ((uint64_t)ver_hi << 32) | (uint64_t) ver_lo;
flash_ext_read_word(&flash_obj, base + OTA_TAG_OFS, &img->tag);
flash_ext_read_word(&flash_obj, base + OTA_VER_OFS, &img->ver);
flash_ext_read_word(&flash_obj, base + OTA_EPOCH_OFS, &epoch_hi);
flash_ext_read_word(&flash_obj, base + OTA_EPOCH_OFS + 4, &epoch_lo);
img->timestamp = ((uint64_t)epoch_hi << 32) | (uint64_t) epoch_lo;
flash_ext_read_word(&flash_obj, base + OTA_SIZE_OFS, &img->size);
flash_ext_stream_read(&flash_obj, base + OTA_HASH_OFS, 32, img->hash);
flash_ext_stream_read(&flash_obj, base + OTA_CAMPAIGN_OFS, 16, img->campaign);
flash_ext_read_word(&flash_obj, base + OTA_CRC32_OFS, &img->crc32);
}
bool OTA_CheckHeader(imginfo_t *img)
{
uint8_t *msg;
uint32_t crc;
msg = (uint8_t *)img;
crc = crc32_get(msg, OTA_CRC32_LEN);
if (crc != img->crc32) {
return false;
}
if ((img->tag & OTA_TAG_CHIP_MSK) != (OTA_TAG_ID & OTA_TAG_CHIP_MSK)) {
return false;
}
return true;
}
void OTA_GetImageInfo(uint32_t base, imginfo_t *img)
{
OTA_ReadHeader(base, img);
if (!OTA_CheckHeader(img)) {
img->timestamp = 0;
img->valid = false;
}
img->valid = true;
}
uint32_t OTA_GetUpdateBase(void)
{
imginfo_t img1, img2;
OTA_GetImageInfo(OTA_REGION1_BASE, &img1);
OTA_GetImageInfo(OTA_REGION2_BASE, &img2);
if (img1.valid && img2.valid) {
if (img1.timestamp < img2.timestamp) {
return OTA_REGION1_BASE;
} else {
info->ver = 0;
return OTA_REGION2_BASE;
}
}
uint32_t OTA_GetBase(void)
if (img1.valid) {
return OTA_REGION2_BASE;
}
return OTA_REGION1_BASE;
}
uint32_t OTA_UpateHeader(uint32_t base, imginfo_t *img)
{
static uint32_t ota_base = 0;
imginfo_t region1, region2;
flash_ext_write_word(&flash_obj, base + OTA_TAG_OFS, img->tag);
flash_ext_write_word(&flash_obj, base + OTA_VER_OFS, img->ver);
flash_ext_write_word(&flash_obj, base + OTA_EPOCH_OFS, img->timestamp >> 32);
flash_ext_write_word(&flash_obj, base + OTA_EPOCH_OFS + 4, (img->timestamp << 32) >> 32);
if (ota_base == OTA_REGION1 || ota_base == OTA_REGION2) {
return ota_base;
flash_ext_write_word(&flash_obj, base + OTA_SIZE_OFS, img->size);
flash_ext_stream_write(&flash_obj, base + OTA_HASH_OFS, 32, img->hash);
flash_ext_stream_write(&flash_obj, base + OTA_CAMPAIGN_OFS, 16, img->campaign);
flash_ext_write_word(&flash_obj, base + OTA_CRC32_OFS, img->crc32);
return 0;
}
region1.base = OTA_REGION1;
region2.base = OTA_REGION2;
OTA_GetImageInfo(&region1);
OTA_GetImageInfo(&region2);
if (region1.ver >= region2.ver) {
ota_base = region2.base;
} else {
ota_base = region1.base;
}
return ota_base;
}
uint32_t OTA_MarkUpdateDone(void)
{
uint32_t addr = OTA_GetBase() + TAG_OFS;
return flash_ext_write_word(&flash_obj, addr, TAG_DOWNLOAD);
}
uint32_t OTA_UpdateImage(uint32_t offset, uint32_t len, uint8_t *data)
uint32_t OTA_UpdateImage(uint32_t base, uint32_t offset, uint32_t len, uint8_t *data)
{
uint32_t addr, start, end, count, shift;
uint8_t *pdata = data;
uint8_t buf[FLASH_SECTOR_SIZE];
start = OTA_GetBase() + offset;
start = base + offset;
end = start + len;
if (data == NULL || start > FLASH_TOP || end > FLASH_TOP) {
if (data == NULL ||
base != OTA_REGION1_BASE || base != OTA_REGION2_BASE ||
start > FLASH_TOP || end > FLASH_TOP) {
return 0;
}
@ -96,7 +139,6 @@ uint32_t OTA_UpdateImage(uint32_t offset, uint32_t len, uint8_t *data)
}
while (addr < end) {
printf("OTA: update addr=0x%lx, len=%ld\r\n", addr, len);
count = MIN(FLASH_SECTOR_SIZE, end - addr);
flash_ext_erase_sector(&flash_obj, addr);
flash_ext_stream_write(&flash_obj, addr, count, pdata);
@ -106,19 +148,20 @@ uint32_t OTA_UpdateImage(uint32_t offset, uint32_t len, uint8_t *data)
return len;
}
uint32_t OTA_ReadImage(uint32_t offset, uint32_t len, uint8_t *data)
uint32_t OTA_ReadImage(uint32_t base, uint32_t offset, uint32_t len, uint8_t *data)
{
uint32_t addr, endaddr;
uint32_t start, end;
addr = OTA_GetBase() + offset;
endaddr = addr + len;
start = base + offset;
end = start + len;
if (data == NULL || addr > FLASH_TOP || endaddr > FLASH_TOP) {
if (data == NULL ||
base != OTA_REGION1_BASE || base != OTA_REGION2_BASE ||
start > FLASH_TOP || end > FLASH_TOP) {
return 0;
}
printf("OTA: read addr=0x%lx\r\n", addr);
return flash_ext_stream_read(&flash_obj, addr, len, data);
return flash_ext_stream_read(&flash_obj, start, len, data);
}
void OTA_ResetTarget(void)
@ -126,11 +169,7 @@ void OTA_ResetTarget(void)
__RTK_CTRL_WRITE32(0x14, 0x00000021);
wait(1);
// write SCB->AIRCR
HAL_WRITE32(0xE000ED00, 0x0C,
(0x5FA << 16) | // VECTKEY
(HAL_READ32(0xE000ED00, 0x0C) & (7 << 8)) | // PRIGROUP
(1 << 2)); // SYSRESETREQ
NVIC_SystemReset();
// not reached
while (1);

69
targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h
View File

@ -1,33 +1,75 @@
/* mbed Microcontroller Library
* Copyright (c) 2013-2017 Realtek Semiconductor Corp.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OTA_API_H
#define MBED_OTA_API_H
#define FLASH_TOP 0x200000
#define FLASH_SECTOR_SIZE 0x1000
#define FLASH_SECTOR_MASK ~(FLASH_SECTOR_SIZE - 1)
#define OTA_REGION1 0x0b000
#define OTA_REGION2 0xc0000
#define TAG_OFS 0xc
#define VER_OFS 0x10
#define TAG_DOWNLOAD 0x81950001
#define TAG_VERIFIED 0x81950003
#define OTA_REGION1_BASE 0x40000
#define OTA_REGION2_BASE 0x120000
#define OTA_REGION1_SIZE 0xe0000
#define OTA_REGION2_SIZE 0xe0000
#define OTA_REGION_SIZE 0xe0000
#define OTA_MBED_FS_BASE 0xb000
#define OTA_CRC32_LEN 0x44
#define OTA_HEADER_LEN 0x48
#define OTA_HEADER_OFS 0x0
#define OTA_TAG_OFS 0x0
#define OTA_VER_OFS 0x4
#define OTA_EPOCH_OFS 0x8
#define OTA_SIZE_OFS 0x10
#define OTA_HASH_OFS 0x14
#define OTA_CAMPAIGN_OFS 0x34
#define OTA_CRC32_OFS 0x44
#define OTA_IMAGE_OFS 0x48
#define OTA_TAG_ID 0x81950001
#define OTA_VER_ID 0x81950001
#define OTA_TAG_CHIP_MSK 0xFFFF0000
#define OTA_TAG_INFO_MSK 0x0000FFFF
typedef struct imginfo_s {
uint32_t base;
uint32_t tag;
uint64_t ver;
uint32_t ver;
uint64_t timestamp;
uint32_t size;
uint8_t hash[32];
uint8_t campaign[16];
uint32_t crc32;
bool valid;
} imginfo_t;
#ifdef __cplusplus
extern "C" {
#endif
extern void OTA_GetImageInfo(imginfo_t *info);
extern uint32_t OTA_GetBase(void);
extern void OTA_GetImageInfo(uint32_t base, imginfo_t *info);
extern uint32_t OTA_GetUpdateBase(void);
extern uint32_t OTA_UpdateImage(uint32_t offset, uint32_t len, uint8_t *data);
extern uint32_t OTA_ReadImage(uint32_t offset, uint32_t len, uint8_t *data);
extern uint32_t OTA_MarkUpdateDone(void);
extern uint32_t OTA_UpdateHeader(uint32_t base, imginfo_t *img);
extern uint32_t OTA_UpdateImage(uint32_t base, uint32_t offset, uint32_t len, uint8_t *data);
extern void OTA_ReadHeader(uint32_t base, imginfo_t *img);
extern uint32_t OTA_ReadImage(uint32_t base, uint32_t offset, uint32_t len, uint8_t *data);
extern void OTA_ResetTarget(void);
#ifdef __cplusplus
@ -35,4 +77,3 @@ extern void OTA_ResetTarget(void);
#endif
#endif /* MBED_OTA_API_H */

82
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PeripheralNames.h Normal file
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@ -0,0 +1,82 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ADC_1 = (int)ADC1_BASE
} ADCName;
typedef enum {
UART_1 = (int)USART1_BASE,
UART_2 = (int)USART2_BASE,
UART_6 = (int)USART6_BASE
} UARTName;
#define STDIO_UART_TX PB_6
#define STDIO_UART_RX PB_7
#define STDIO_UART UART_1
typedef enum {
SPI_1 = (int)SPI1_BASE,
SPI_2 = (int)SPI2_BASE,
SPI_3 = (int)SPI3_BASE,
SPI_4 = (int)SPI4_BASE,
SPI_5 = (int)SPI5_BASE
} SPIName;
typedef enum {
I2C_1 = (int)I2C1_BASE,
I2C_2 = (int)I2C2_BASE,
I2C_3 = (int)I2C3_BASE
} I2CName;
typedef enum {
PWM_1 = (int)TIM1_BASE,
PWM_2 = (int)TIM2_BASE,
PWM_3 = (int)TIM3_BASE,
PWM_4 = (int)TIM4_BASE,
PWM_5 = (int)TIM5_BASE,
PWM_9 = (int)TIM9_BASE,
PWM_10 = (int)TIM10_BASE,
PWM_11 = (int)TIM11_BASE
} PWMName;
#ifdef __cplusplus
}
#endif
#endif

224
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PeripheralPins.c Normal file
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@ -0,0 +1,224 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "PeripheralPins.h"
// =====
// Note: Commented lines are alternative possibilities which are not used per default.
// If you change them, you will have also to modify the corresponding xxx_api.c file
// for pwmout, analogin, analogout, ...
// =====
//*** ADC ***
const PinMap PinMap_ADC[] = {
{PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
{PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // SERIAL_TX
// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // SERIAL_RX
// {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // SPI_CS
// {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // SPI_CLK
// {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 // SPI_MISO
// {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // SPI_MOSI
// {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // SPI_CLK
// {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 // SPI_CS
// {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // Push SW 3
// {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // Push SW 4
// {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 // Slide SW 1
// {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 // Slide SW 2
// {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 // LED-4
// {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 // Display LED
{NC, NC, 0}
};
const PinMap PinMap_ADC_Internal[] = {
{ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
{ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
{ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
{NC, NC, 0}
};
//*** I2C ***
const PinMap PinMap_I2C_SDA[] = {
{PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
// {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
// {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
// {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, // Warning: also on SCL
{PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
// {PB_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
{PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
{NC, NC, 0}
};
const PinMap PinMap_I2C_SCL[] = {
{PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
// {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
{NC, NC, 0}
};
//*** PWM ***
// TIM5 cannot be used because already used by the us_ticker
const PinMap PinMap_PWM[] = {
{PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
{PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
{PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // SERIAL_TX
// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // SERIAL_TX
// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // SERIAL_TX
{PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // SERIAL_RX
// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // SERIAL_RX
// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 // SERIAL_RX
{PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
{PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
{PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO
// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO
// {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
// {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
// {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
// {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
// {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
// {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
{PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO
// {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO
// {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
// {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO
// {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
// {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 1, 0)}, // TIM10_CH1
// {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1
{PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO
// {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
// {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
// {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
// {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
// {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO
// {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
// {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
{NC, NC, 0}
};
//*** SERIAL ***
const PinMap PinMap_UART_TX[] = {
{PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_TX
// {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // WAKE_OUT
// {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // GPS_EN
// {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // GPS module SPI
{PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
{NC, NC, 0}
};
const PinMap PinMap_UART_RX[] = {
{PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_RX
// {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // MPU9250 SPI MOSI
// {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // MPU9250 SPI MISO
// {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // GROVE SDA
{PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
{NC, NC, 0}
};
const PinMap PinMap_UART_RTS[] = {
// {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
// {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{NC, NC, 0}
};
const PinMap PinMap_UART_CTS[] = {
// {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
// {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{NC, NC, 0}
};
//*** SPI ***
const PinMap PinMap_SPI_MOSI[] = {
// {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
{PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
{PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
// {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
// {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
{PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
// {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
{NC, NC, 0}
};
const PinMap PinMap_SPI_MISO[] = {
{PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
// {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
{PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
// {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
// {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
{PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
// {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
{NC, NC, 0}
};
const PinMap PinMap_SPI_SCLK[] = {
{PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
{PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
// {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
// {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
// {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Warning: also on NSS
{PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
// {PB_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
// {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
{NC, NC, 0}
};
const PinMap PinMap_SPI_SSEL[] = {
// {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
{PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
{PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
// {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Warning: also on SCLK
// {PB_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, // Warning: also on SCLK
{NC, NC, 0}
};

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targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PinNames.h Normal file
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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
PA_2 = 0x02,
PA_3 = 0x03,
PA_4 = 0x04,
PA_5 = 0x05,
PA_6 = 0x06,
PA_7 = 0x07,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_12 = 0x0C,
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PB_0 = 0x10,
PB_1 = 0x11,
PB_2 = 0x12,
PB_3 = 0x13,
PB_4 = 0x14,
PB_5 = 0x15,
PB_6 = 0x16,
PB_7 = 0x17,
PB_8 = 0x18,
PB_9 = 0x19,
PB_10 = 0x1A,
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_15 = 0x1F,
PC_0 = 0x20,
PC_1 = 0x21,
PC_2 = 0x22,
PC_3 = 0x23,
PC_4 = 0x24,
PC_5 = 0x25,
PC_6 = 0x26,
PC_7 = 0x27,
PC_8 = 0x28,
PC_9 = 0x29,
PC_10 = 0x2A,
PC_11 = 0x2B,
PC_12 = 0x2C,
PC_13 = 0x2D,
PC_14 = 0x2E,
PC_15 = 0x2F,
PD_2 = 0x32,
PH_0 = 0x70,
PH_1 = 0x71,
// ADC internal channels
ADC_TEMP = 0xF0,
ADC_VREF = 0xF1,
ADC_VBAT = 0xF2,
// External IO connector namings
A0 = PA_0,
A1 = PA_1,
VBAT_AD_IN = A0,
VBAT_AD_EN = A1,
I2C_SCL = PB_10,
I2C_SDA = PB_3,
SPI_MOSI = PA_7,
SPI_MISO = PA_6,
SPI_SCK = PA_5,
SPI_CS = PA_4,
EXT_PIN_3 = PA_7,
EXT_PIN_4 = PA_6,
EXT_PIN_5 = PA_5,
EXT_PIN_6 = PA_4,
EXT_PIN_7 = PA_3,
EXT_PIN_8 = PA_2,
EXT_PIN_9 = PB_10,
EXT_PIN_10 = PB_3,
EXT_PIN_13 = PA_0,
EXT_PIN_14 = PA_1,
EXT_I2C_SCL = I2C_SCL,
EXT_I2C_SDA = I2C_SDA,
EXT_SPI_MOSI = SPI_MOSI,
EXT_SPI_MISO = SPI_MISO,
EXT_SPI_SCK = SPI_SCK,
EXT_SPI_CS = SPI_CS,
EXT_SERIAL_TX = PA_2,
EXT_SERIAL_RX = PA_3,
SCM_I2C_SCL = PA_8,
SCM_I2C_SDA = PC_9,
SCM_SPI_MOSI = PB_15,
SCM_SPI_MISO = PB_14,
SCM_SPI_SCK = PB_13,
SCM_SPI_CS = PB_12,
SCM_WAKE_IN = PC_8,
SCM_WAKE_OUT = PA_9,
GPS_INT = PB_5,
GPS_1PPS = PB_4,
GPS_WAKEUP = PD_2,
GPS_EN = PA_11,
GPS_SERIAL_TX = PC_6,
GPS_SERIAL_RX = PC_7,
GPS_SPI_MOSI = PC_12,
GPS_SPI_MISO = PC_11,
GPS_SPI_SCK = PC_10,
GPS_SPI_CS = PA_15,
LCD_LED = PC_5,
LCD_I2C_SCL = PB_8,
LCD_I2C_SDA = PB_9,
BME280_I2C_SCL = PB_8,
BME280_I2C_SDA = PB_9,
MPU9250_SPI_MOSI = PA_10,
MPU9250_SPI_MISO = PA_12,
MPU9250_SPI_SCK = PB_0,
MPU9250_SPI_CS = PB_1,
// Generic signals namings
LED1 = PC_13,
LED2 = PC_15,
LED3 = PH_1,
LED4 = PC_4,
LED_RED = LED1,
// Standardized button names
SW1 = PC_14,
SW2 = PH_0,
SW3 = PC_0,
SW4 = PC_1,
SW5 = PC_2,
SW6 = PC_3,
USER_BUTTON = SW1,
BUTTON1 = SW1,
BUTTON2 = SW2,
BUTTON3 = SW3,
BUTTON4 = SW4,
SLIDE_SW1 = SW5,
SLIDE_SW2 = SW6,
// Serial port pins
SERIAL_TX = PB_6,
SERIAL_RX = PB_7,
USBTX = PB_6,
USBRX = PB_7,
// USB pins
// USB_OTG_FS_SOF = PA_8,
// USB_OTG_FS_VBUS = PA_9,
// USB_OTG_FS_ID = PA_10,
// USB_OTG_FS_DM = PA_11,
// USB_OTG_FS_DP = PA_12,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* This file configures the system clock as follows:
*-----------------------------------------------------------------------------
* System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) | CLOCK_SOURCE_USB=1
* | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) |
* | 3- USE_PLL_HSI (internal 16 MHz) |
*-----------------------------------------------------------------------------
* SYSCLK(MHz) | 100 | 96
* AHBCLK (MHz) | 100 | 96
* APB1CLK (MHz) | 50 | 48
* APB2CLK (MHz) | 100 | 96
* USB capable | NO | YES
*-----------------------------------------------------------------------------
**/
#include "stm32f4xx.h"
#include "mbed_assert.h"
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
// clock source is selected with CLOCK_SOURCE in json config
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
#define USE_PLL_HSI 0x2 // Use HSI internal clock
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
uint8_t SetSysClock_PLL_HSI(void);
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting, vector table location and External memory
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings
* @note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
void SetSysClock(void)
{
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
/* 1- Try to start with HSE and external clock */
if (SetSysClock_PLL_HSE(1) == 0)
#endif
{
#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
/* 2- If fail try to start with HSE and external xtal */
if (SetSysClock_PLL_HSE(0) == 0)
#endif
{
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
/* 3- If fail start with HSI clock */
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
MBED_ASSERT(1);
}
}
}
}
/* Output clock on MCO2 pin(PC9) for debugging purpose */
//HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
}
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
// Enable HSE oscillator and activate PLL with HSE as source
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
if (bypass == 0) {
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
} else {
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
}
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
#if (CLOCK_SOURCE_USB)
RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
#else /* CLOCK_SOURCE_USB */
RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
#endif /* CLOCK_SOURCE_USB */
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz or 96 MHz (depending on CLOCK_SOURCE_USB)
RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (CLOCK_SOURCE_USB=1)
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100/96 MHz
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100/96 MHz
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50/48 MHz
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100/96 MHz
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
return 0; // FAIL
}
/* Output clock on MCO1 pin(PA8) for debugging purpose */
//if (bypass == 0)
// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
//else
// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
return 1; // OK
}
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
/******************************************************************************/
/* PLL (clocked by HSI) used as System clock source */
/******************************************************************************/
uint8_t SetSysClock_PLL_HSI(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
// Enable HSI oscillator and activate PLL with HSI as source
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
RCC_OscInitStruct.HSICalibrationValue = 16;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
#if (CLOCK_SOURCE_USB)
RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
#else /* CLOCK_SOURCE_USB */
RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
#endif /* CLOCK_SOURCE_USB */
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz or 96 MHz (depending on CLOCK_SOURCE_USB)
RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (CLOCK_SOURCE_USB=1)
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
return 0; // FAIL
}
/* Output clock on MCO1 pin(PA8) for debugging purpose */
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
return 1; // OK
}
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

2
targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/stm32l073xz.sct → targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/stm32l072xz.sct
View File

@ -27,7 +27,7 @@
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; STM32L073RZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000)
; STM32L072CZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000)
LR_IROM1 0x08000000 0x30000 { ; load region size_region
ER_IROM1 0x08000000 0x30000 { ; load address = execution address

2
targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/stm32l073xz.sct → targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/stm32l072xz.sct
View File

@ -27,7 +27,7 @@
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; STM32L073RZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000)
; STM32L072CZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000)
LR_IROM1 0x08000000 0x30000 { ; load region size_region
ER_IROM1 0x08000000 0x30000 { ; load address = execution address

2
targets/TARGET_STM/TARGET_STM32L4/serial_device.c
View File

@ -491,9 +491,11 @@ static IRQn_Type serial_get_irq_n(serial_t *obj)
irq_n = USART2_IRQn;
break;
#if defined(UART3_BASE)
case 2:
irq_n = USART3_IRQn;
break;
#endif
#if defined(UART4_BASE)
case 3:
irq_n = UART4_IRQn;

11
targets/TARGET_STM/stm_spi_api.c
View File

@ -29,6 +29,7 @@
*/
#include "mbed_assert.h"
#include "mbed_error.h"
#include "mbed_debug.h"
#include "spi_api.h"
#if DEVICE_SPI
@ -286,6 +287,16 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
handle->Init.Mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
if (slave && (handle->Init.Direction == SPI_DIRECTION_1LINE)) {
/* SPI slave implemtation in MBED does not support the 3 wires SPI.
* (e.g. when MISO is not connected). So we're forcing slave in
* 2LINES mode. As MISO is not connected, slave will only read
* from master, and cannot write to it. Inform user.
*/
debug("3 wires SPI slave not supported - slave will only read\r\n");
handle->Init.Direction = SPI_DIRECTION_2LINES;
}
init_spi(obj);
}

4
targets/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c
View File

@ -40,10 +40,10 @@ void analogin_init(analogin_t *obj, PinName pin)
/* Init structure */
obj->adc = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT((int) obj->adc != NC);
MBED_ASSERT((unsigned int) obj->adc != NC);
obj->channel = pin_location(pin, PinMap_ADC);
MBED_ASSERT((int) obj->channel != NC);
MBED_ASSERT((unsigned int) obj->channel != NC);
/* Only initialize the ADC once */
if (!adc_initialized) {

4
targets/TARGET_Silicon_Labs/TARGET_EFM32/analogout_api.c
View File

@ -41,10 +41,10 @@ void analogout_init(dac_t *obj, PinName pin)
{
/* init in-memory structure */
obj->dac = (DAC_TypeDef *) pinmap_peripheral(pin, PinMap_DAC);
MBED_ASSERT((int) obj->dac != NC);
MBED_ASSERT((unsigned int) obj->dac != NC);
obj->channel = pin_location(pin, PinMap_DAC);
MBED_ASSERT((int) obj->channel != NC);
MBED_ASSERT((unsigned int) obj->channel != NC);
pin_mode(pin, Disabled);

2
targets/TARGET_Silicon_Labs/TARGET_EFM32/common/CommonPinNames.h
View File

@ -41,7 +41,7 @@
PI0 = 8 << 4, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, \
PJ0 = 9 << 4, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, \
PK0 = 10 << 4, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, \
NC = (int) 0xFFFFFFFF
NC = (unsigned int) 0xFFFFFFFFUL
#ifdef __cplusplus
extern "C" {

2
targets/TARGET_Silicon_Labs/TARGET_EFM32/dma_api_HAL.h
View File

@ -45,6 +45,7 @@ extern "C" {
#define DMA_CAP_2DCOPY (1 << 0)
#define DMA_CAP_NONE (0 << 0)
#ifdef DMA_PRESENT
#if ( DMA_CHAN_COUNT <= 4 )
#define DMACTRL_CH_CNT 4
#define DMACTRL_ALIGNMENT 256
@ -60,6 +61,7 @@ extern "C" {
#else
#error "Unsupported DMA channel count (dma_api.c)."
#endif
#endif
#ifdef LDMA_PRESENT
typedef void (*LDMAx_CBFunc_t)(unsigned int channel, bool primary, void *user);

63
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt
View File

@ -1,4 +1,67 @@
================ Revision history ============================================
5.3.3
- em_cmu: 48 MHz HFRCO band selectable for devices that support it.
- em_emu: Added macro guards for BU mode functionality for series 0 devices.
5.3.2
- No changes.
5.3.1
- em_opamp: Corrected reload of default calibration trims in OPAMP_Enable()
for Series 0.
- em_core: Fixed invalid parameter in CORE_YIELD_CRITICAL and
CORE_YIELD_ATOMIC macros.
5.3.0
- em_chip: Updated PLFRCO tuning values.
- em_can: Fixed ID filter mask bug.
- em_gpio: Doc updates.
- em_gpio: Fixed bug in GPIO pin validation to enable PD9 on BGM121 modules.
- em_ldma: Added missing signals for EFM32GG11.
5.2.2:
- em_emu: Fixed bug in EMU_EM4Init(), The BUBODRSTDIS field was not initialized
as specified in function input parameters.
5.2.1:
- em_emu: Fixed a problem with handling of DCDC bypass current limiter
that may cause brownout reset.
- em_chip: Added workaround for errata DCDC-E206 for EFR32xG1x devices.
- em_cmu: Fixed handling of HFCLKLE prescaling at frequencies above 64 MHz.
5.2.0:
- em_cmu: Added flash wait state handling for all devices that can scale down
the voltage.
- em_adc: Fixed bug where ADC SINGLECTRLX register fields VREFSEL, PRSSEL and
FIFOOFACT was not cleared when calling ADC_InitSingle().
- em_msc: Removed call to SystemCoreClockGet() in MSC_Init.
- em_msc: MSC_WriteWordFast() can now only be used when executing code from
RAM on parts that include a flash write buffer.
- em_emu: Using VMON calibration values to set voltage thresholds when
calling EMU_VmonInit() and EMU_VmonHystInit(). The DI page contains
calibration values for 1.86 V and 2.98 V for each VMON channel. Updated
VMON supported voltage range to 1.62V-3.4V.
- em_emu: Added EMU_Save() and changed EMU_EnterEM2() and EMU_EnterEM3()
to only save the state if the restore parameter is true.
- em_usart: Fixed USART async baudrate calculation for EFM32HG devices.
The extra fractional bits in the CLKDIV register was not used.
- Added support for EFM32GG11B devices. This includes new modules for
Quad SPI (em_qspi) and CAN (em_can). This also includes
changes to other emlib modules in order to support the changes in the
register interface of the new device.
- em_cmu: Added DPLL support. Added support for asynchronous clocks for
ADC, reference clocks for QSPI and SDIO and USB rate clock. Added
functions to support the USHFRCO and clock select for HFXOX2.
- em_gpio: Using single cycle set and clear of DOUT on platforms
where this is supported.
- em_lesense: Added configuration of DACCHnEN and DACSTARTUP bits in
LESENSE->PERCTRL in LESENSE_Init() and init struct. Also changed
default values for LESENSE_AltExDesc_TypeDef and
LESENSE_ChDesc_TypeDef to be disabled by default.
5.1.3:
- No changes.
5.1.2:
Misc. bugfixes and improvements.

57
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_acmp.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_acmp.h
* @brief Analog Comparator (ACMP) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -95,8 +95,7 @@ extern "C" {
/** Resistor values used for the internal capacative sense resistor. See the
* datasheet for your device for details on each resistor value. */
typedef enum
{
typedef enum {
acmpResistor0 = _ACMP_INPUTSEL_CSRESSEL_RES0, /**< Resistor value 0 */
acmpResistor1 = _ACMP_INPUTSEL_CSRESSEL_RES1, /**< Resistor value 1 */
acmpResistor2 = _ACMP_INPUTSEL_CSRESSEL_RES2, /**< Resistor value 2 */
@ -111,8 +110,7 @@ typedef enum
/** Hysteresis level. See datasheet for your device for details on each
* level. */
typedef enum
{
typedef enum {
#if defined(_ACMP_CTRL_HYSTSEL_MASK)
acmpHysteresisLevel0 = _ACMP_CTRL_HYSTSEL_HYST0, /**< Hysteresis level 0 */
acmpHysteresisLevel1 = _ACMP_CTRL_HYSTSEL_HYST1, /**< Hysteresis level 1 */
@ -146,8 +144,7 @@ typedef enum
#if defined(_ACMP_CTRL_WARMTIME_MASK)
/** ACMP warmup time. The delay is measured in HFPERCLK cycles and should
* be at least 10 us. */
typedef enum
{
typedef enum {
/** 4 HFPERCLK cycles warmup */
acmpWarmTime4 = _ACMP_CTRL_WARMTIME_4CYCLES,
/** 8 HFPERCLK cycles warmup */
@ -171,8 +168,7 @@ typedef enum
/**
* Adjust performance of the ACMP for a given input voltage range
*/
typedef enum
{
typedef enum {
acmpInputRangeFull = _ACMP_CTRL_INPUTRANGE_FULL, /**< Input can be from 0 to Vdd */
acmpInputRangeHigh = _ACMP_CTRL_INPUTRANGE_GTVDDDIV2, /**< Input will always be greater than Vdd/2 */
acmpInputRangeLow = _ACMP_CTRL_INPUTRANGE_LTVDDDIV2 /**< Input will always be less than Vdd/2 */
@ -183,8 +179,7 @@ typedef enum
/**
* ACMP Power source.
*/
typedef enum
{
typedef enum {
acmpPowerSourceAvdd = _ACMP_CTRL_PWRSEL_AVDD, /**< Power the ACMP using the AVDD supply */
acmpPowerSourceVddVreg = _ACMP_CTRL_PWRSEL_VREGVDD, /**< Power the ACMP using the VREGVDD supply */
acmpPowerSourceIOVdd0 = _ACMP_CTRL_PWRSEL_IOVDD0, /**< Power the ACMP using the IOVDD/IOVDD0 supply */
@ -196,8 +191,7 @@ typedef enum
/**
* ACMP accuracy mode.
*/
typedef enum
{
typedef enum {
acmpAccuracyLow = _ACMP_CTRL_ACCURACY_LOW, /**< Low-accuracy mode but consume less current */
acmpAccuracyHigh = _ACMP_CTRL_ACCURACY_HIGH /**< High-accuracy mode but consume more current */
} ACMP_Accuracy_TypeDef;
@ -206,8 +200,7 @@ typedef enum
#if defined(_ACMP_INPUTSEL_VASEL_MASK)
/** ACMP Input to the VA divider. This enum is used to select the input for
* the VA Divider */
typedef enum
{
typedef enum {
acmpVAInputVDD = _ACMP_INPUTSEL_VASEL_VDD,
acmpVAInputAPORT2YCH0 = _ACMP_INPUTSEL_VASEL_APORT2YCH0,
acmpVAInputAPORT2YCH2 = _ACMP_INPUTSEL_VASEL_APORT2YCH2,
@ -265,8 +258,7 @@ typedef enum
* ACMP Input to the VB divider. This enum is used to select the input for
* the VB divider.
*/
typedef enum
{
typedef enum {
acmpVBInput1V25 = _ACMP_INPUTSEL_VBSEL_1V25,
acmpVBInput2V5 = _ACMP_INPUTSEL_VBSEL_2V5
} ACMP_VBInput_TypeDef;
@ -276,8 +268,7 @@ typedef enum
/**
* ACMP Low-Power Input Selection.
*/
typedef enum
{
typedef enum {
acmpVLPInputVADIV = _ACMP_INPUTSEL_VLPSEL_VADIV,
acmpVLPInputVBDIV = _ACMP_INPUTSEL_VLPSEL_VBDIV
} ACMP_VLPInput_Typedef;
@ -285,8 +276,7 @@ typedef enum
#if defined(_ACMP_INPUTSEL_POSSEL_APORT0XCH0)
/** ACMP Input Selection */
typedef enum
{
typedef enum {
acmpInputAPORT0XCH0 = _ACMP_INPUTSEL_POSSEL_APORT0XCH0,
acmpInputAPORT0XCH1 = _ACMP_INPUTSEL_POSSEL_APORT0XCH1,
acmpInputAPORT0XCH2 = _ACMP_INPUTSEL_POSSEL_APORT0XCH2,
@ -462,8 +452,7 @@ typedef enum
#else
/** ACMP inputs. Note that scaled VDD and bandgap references can only be used
* as negative inputs. */
typedef enum
{
typedef enum {
/** Channel 0 */
acmpChannel0 = _ACMP_INPUTSEL_NEGSEL_CH0,
/** Channel 1 */
@ -510,8 +499,7 @@ typedef enum
* used by an external module like LESENSE when it's taking control over
* the ACMP input.
*/
typedef enum
{
typedef enum {
acmpExternalInputAPORT0X = _ACMP_EXTIFCTRL_APORTSEL_APORT0X,
acmpExternalInputAPORT0Y = _ACMP_EXTIFCTRL_APORTSEL_APORT0Y,
acmpExternalInputAPORT1X = _ACMP_EXTIFCTRL_APORTSEL_APORT1X,
@ -534,8 +522,7 @@ typedef enum
******************************************************************************/
/** Capsense initialization structure. */
typedef struct
{
typedef struct {
/** Full bias current. See the ACMP chapter about bias and response time in
* the reference manual for details. */
bool fullBias;
@ -646,8 +633,7 @@ typedef struct
#endif
/** ACMP initialization structure. */
typedef struct
{
typedef struct {
/** Full bias current. See the ACMP chapter about bias and response time in
* the reference manual for details. */
bool fullBias;
@ -779,8 +765,7 @@ typedef struct
#if defined(_ACMP_INPUTSEL_VASEL_MASK)
/** VA Configuration structure. This struct is used to configure the
* VA voltage input source and it's dividers. */
typedef struct
{
typedef struct {
ACMP_VAInput_TypeDef input; /**< VA voltage input source */
/**
@ -813,8 +798,7 @@ typedef struct
#if defined(_ACMP_INPUTSEL_VBSEL_MASK)
/** VB Configuration structure. This struct is used to configure the
* VB voltage input source and it's dividers. */
typedef struct
{
typedef struct {
ACMP_VBInput_TypeDef input; /**< VB Voltage input source */
/**
@ -883,7 +867,6 @@ __STATIC_INLINE void ACMP_IntClear(ACMP_TypeDef *acmp, uint32_t flags)
acmp->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more ACMP interrupts.
@ -901,7 +884,6 @@ __STATIC_INLINE void ACMP_IntDisable(ACMP_TypeDef *acmp, uint32_t flags)
acmp->IEN &= ~(flags);
}
/***************************************************************************//**
* @brief
* Enable one or more ACMP interrupts.
@ -924,7 +906,6 @@ __STATIC_INLINE void ACMP_IntEnable(ACMP_TypeDef *acmp, uint32_t flags)
acmp->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending ACMP interrupt flags.
@ -945,7 +926,6 @@ __STATIC_INLINE uint32_t ACMP_IntGet(ACMP_TypeDef *acmp)
return acmp->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending ACMP interrupt flags.
@ -977,7 +957,6 @@ __STATIC_INLINE uint32_t ACMP_IntGetEnabled(ACMP_TypeDef *acmp)
return acmp->IF & tmp;
}
/***************************************************************************//**
* @brief
* Set one or more pending ACMP interrupts from SW.

97
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_adc.h
* @brief Analog to Digital Converter (ADC) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -57,8 +57,7 @@ extern "C" {
******************************************************************************/
/** Acquisition time (in ADC clock cycles). */
typedef enum
{
typedef enum {
adcAcqTime1 = _ADC_SINGLECTRL_AT_1CYCLE, /**< 1 clock cycle. */
adcAcqTime2 = _ADC_SINGLECTRL_AT_2CYCLES, /**< 2 clock cycles. */
adcAcqTime4 = _ADC_SINGLECTRL_AT_4CYCLES, /**< 4 clock cycles. */
@ -72,8 +71,7 @@ typedef enum
#if defined(_ADC_CTRL_LPFMODE_MASK)
/** Lowpass filter mode. */
typedef enum
{
typedef enum {
/** No filter or decoupling capacitor. */
adcLPFilterBypass = _ADC_CTRL_LPFMODE_BYPASS,
@ -86,8 +84,7 @@ typedef enum
#endif
/** Oversample rate select. */
typedef enum
{
typedef enum {
/** 2 samples per conversion result. */
adcOvsRateSel2 = _ADC_CTRL_OVSRSEL_X2,
@ -125,10 +122,8 @@ typedef enum
adcOvsRateSel4096 = _ADC_CTRL_OVSRSEL_X4096
} ADC_OvsRateSel_TypeDef;
/** Peripheral Reflex System signal used to trigger single sample. */
typedef enum
{
typedef enum {
#if defined(_ADC_SINGLECTRL_PRSSEL_MASK)
adcPRSSELCh0 = _ADC_SINGLECTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */
adcPRSSELCh1 = _ADC_SINGLECTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */
@ -167,10 +162,18 @@ typedef enum
adcPRSSELCh5 = _ADC_SINGLECTRLX_PRSSEL_PRSCH5, /**< PRS channel 5. */
adcPRSSELCh6 = _ADC_SINGLECTRLX_PRSSEL_PRSCH6, /**< PRS channel 6. */
adcPRSSELCh7 = _ADC_SINGLECTRLX_PRSSEL_PRSCH7, /**< PRS channel 7. */
#if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH8)
adcPRSSELCh8 = _ADC_SINGLECTRLX_PRSSEL_PRSCH8, /**< PRS channel 8. */
#endif
#if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH9)
adcPRSSELCh9 = _ADC_SINGLECTRLX_PRSSEL_PRSCH9, /**< PRS channel 9. */
#endif
#if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH10)
adcPRSSELCh10 = _ADC_SINGLECTRLX_PRSSEL_PRSCH10, /**< PRS channel 10. */
#endif
#if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH11)
adcPRSSELCh11 = _ADC_SINGLECTRLX_PRSSEL_PRSCH11, /**< PRS channel 11. */
#endif
#if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH12)
adcPRSSELCh12 = _ADC_SINGLECTRLX_PRSSEL_PRSCH12, /**< PRS channel 12. */
adcPRSSELCh13 = _ADC_SINGLECTRLX_PRSSEL_PRSCH13, /**< PRS channel 13. */
@ -180,14 +183,12 @@ typedef enum
#endif
} ADC_PRSSEL_TypeDef;
/** Single and scan mode voltage references. Using unshifted enums and or
in ADC_CTRLX_VREFSEL_REG to select the extension register CTRLX_VREFSEL. */
#if defined(_ADC_SCANCTRLX_VREFSEL_MASK)
#define ADC_CTRLX_VREFSEL_REG 0x80
#endif
typedef enum
{
typedef enum {
/** Internal 1.25V reference. */
adcRef1V25 = _ADC_SINGLECTRL_REF_1V25,
@ -262,21 +263,17 @@ typedef enum
#endif
/** @endcond */
/** Sample resolution. */
typedef enum
{
typedef enum {
adcRes12Bit = _ADC_SINGLECTRL_RES_12BIT, /**< 12 bit sampling. */
adcRes8Bit = _ADC_SINGLECTRL_RES_8BIT, /**< 8 bit sampling. */
adcRes6Bit = _ADC_SINGLECTRL_RES_6BIT, /**< 6 bit sampling. */
adcResOVS = _ADC_SINGLECTRL_RES_OVS /**< Oversampling. */
} ADC_Res_TypeDef;
#if defined(_ADC_SINGLECTRL_INPUTSEL_MASK)
/** Single sample input selection. */
typedef enum
{
typedef enum {
/* Differential mode disabled */
adcSingleInputCh0 = _ADC_SINGLECTRL_INPUTSEL_CH0, /**< Channel 0. */
adcSingleInputCh1 = _ADC_SINGLECTRL_INPUTSEL_CH1, /**< Channel 1. */
@ -331,8 +328,7 @@ typedef enum
#if defined(_ADC_SINGLECTRL_POSSEL_MASK)
/** Positive input selection for single and scan coversion. */
typedef enum
{
typedef enum {
adcPosSelAPORT0XCH0 = _ADC_SINGLECTRL_POSSEL_APORT0XCH0,
adcPosSelAPORT0XCH1 = _ADC_SINGLECTRL_POSSEL_APORT0XCH1,
adcPosSelAPORT0XCH2 = _ADC_SINGLECTRL_POSSEL_APORT0XCH2,
@ -494,6 +490,9 @@ typedef enum
adcPosSelAPORT4YCH30 = _ADC_SINGLECTRL_POSSEL_APORT4YCH30,
adcPosSelAPORT4XCH31 = _ADC_SINGLECTRL_POSSEL_APORT4XCH31,
adcPosSelAVDD = _ADC_SINGLECTRL_POSSEL_AVDD,
#if defined(_ADC_SINGLECTRL_POSSEL_BU)
adcPosSelBUVDD = _ADC_SINGLECTRL_POSSEL_BU,
#endif
adcPosSelDVDD = _ADC_SINGLECTRL_POSSEL_AREG,
adcPosSelPAVDD = _ADC_SINGLECTRL_POSSEL_VREGOUTPA,
adcPosSelDECOUPLE = _ADC_SINGLECTRL_POSSEL_PDBU,
@ -513,14 +512,11 @@ typedef enum
#define adcPosSelVREGOUTPA adcPosSelPAVDD
#define adcPosSelAREG adcPosSelDVDD
#define adcPosSelPDBU adcPosSelDECOUPLE
#endif
#if defined(_ADC_SINGLECTRL_NEGSEL_MASK)
/** Negative input selection for single and scan coversion. */
typedef enum
{
typedef enum {
adcNegSelAPORT0XCH0 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH0,
adcNegSelAPORT0XCH1 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH1,
adcNegSelAPORT0XCH2 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH2,
@ -687,11 +683,9 @@ typedef enum
} ADC_NegSel_TypeDef;
#endif
#if defined(_ADC_SCANINPUTSEL_MASK)
/* ADC scan input groups */
typedef enum
{
typedef enum {
adcScanInputGroup0 = 0,
adcScanInputGroup1 = 1,
adcScanInputGroup2 = 2,
@ -710,8 +704,7 @@ typedef enum
<< _ADC_SCANINPUTSEL_INPUT24TO31SEL_SHIFT))
/* ADC scan alternative negative inputs */
typedef enum
{
typedef enum {
adcScanNegInput1 = 1,
adcScanNegInput3 = 3,
adcScanNegInput5 = 5,
@ -724,10 +717,8 @@ typedef enum
} ADC_ScanNegInput_TypeDef;
#endif
/** ADC Start command. */
typedef enum
{
typedef enum {
/** Start single conversion. */
adcStartSingle = ADC_CMD_SINGLESTART,
@ -741,10 +732,8 @@ typedef enum
adcStartScanAndSingle = ADC_CMD_SCANSTART | ADC_CMD_SINGLESTART
} ADC_Start_TypeDef;
/** Warm-up mode. */
typedef enum
{
typedef enum {
/** ADC shutdown after each conversion. */
adcWarmupNormal = _ADC_CTRL_WARMUPMODE_NORMAL,
@ -773,28 +762,23 @@ typedef enum
/** ADC and reference selected for scan mode kept warmup, allowing
continuous conversion. */
adcWarmupKeepADCWarm = _ADC_CTRL_WARMUPMODE_KEEPADCWARM,
} ADC_Warmup_TypeDef;
#if defined(_ADC_CTRL_ADCCLKMODE_MASK)
/** ADC EM2 clock configuration */
typedef enum
{
typedef enum {
adcEm2Disabled = 0,
adcEm2ClockOnDemand = ADC_CTRL_ADCCLKMODE_ASYNC | ADC_CTRL_ASYNCCLKEN_ASNEEDED,
adcEm2ClockAlwaysOn = ADC_CTRL_ADCCLKMODE_ASYNC | ADC_CTRL_ASYNCCLKEN_ALWAYSON,
} ADC_EM2ClockConfig_TypeDef;
#endif
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** ADC init structure, common for single conversion and scan sequence. */
typedef struct
{
typedef struct {
/**
* Oversampling rate select. In order to have any effect, oversampling must
* be enabled for single/scan mode.
@ -830,7 +814,6 @@ typedef struct
#endif
} ADC_Init_TypeDef;
/** Default config for ADC init structure. */
#if defined(_ADC_CTRL_LPFMODE_MASK) && (!defined(_ADC_CTRL_ADCCLKMODE_MASK))
#define ADC_INIT_DEFAULT \
@ -863,10 +846,8 @@ typedef struct
}
#endif
/** Scan input configuration */
typedef struct
{
typedef struct {
/** Input range select to be applied to ADC_SCANINPUTSEL. */
uint32_t scanInputSel;
@ -877,10 +858,8 @@ typedef struct
uint32_t scanNegSel;
} ADC_InitScanInput_TypeDef;
/** Scan sequence init structure. */
typedef struct
{
typedef struct {
/**
* Peripheral reflex system trigger selection. Only applicable if @p prsEnable
* is enabled.
@ -979,10 +958,8 @@ typedef struct
}
#endif
/** Single conversion init structure. */
typedef struct
{
typedef struct {
/**
* Peripheral reflex system trigger selection. Only applicable if @p prsEnable
* is enabled.
@ -1098,7 +1075,6 @@ __STATIC_INLINE uint32_t ADC_DataSingleGet(ADC_TypeDef *adc)
return adc->SINGLEDATA;
}
/***************************************************************************//**
* @brief
* Peek single conversion result.
@ -1117,7 +1093,6 @@ __STATIC_INLINE uint32_t ADC_DataSinglePeek(ADC_TypeDef *adc)
return adc->SINGLEDATAP;
}
/***************************************************************************//**
* @brief
* Get scan result.
@ -1136,7 +1111,6 @@ __STATIC_INLINE uint32_t ADC_DataScanGet(ADC_TypeDef *adc)
return adc->SCANDATA;
}
/***************************************************************************//**
* @brief
* Peek scan result.
@ -1155,7 +1129,6 @@ __STATIC_INLINE uint32_t ADC_DataScanPeek(ADC_TypeDef *adc)
return adc->SCANDATAP;
}
#if defined(_ADC_SCANDATAX_MASK)
uint32_t ADC_DataIdScanGet(ADC_TypeDef *adc, uint32_t *scanId);
#endif
@ -1179,7 +1152,6 @@ void ADC_InitSingle(ADC_TypeDef *adc, const ADC_InitSingle_TypeDef *init);
uint8_t ADC_TimebaseCalc(uint32_t hfperFreq);
uint8_t ADC_PrescaleCalc(uint32_t adcFreq, uint32_t hfperFreq);
/***************************************************************************//**
* @brief
* Clear one or more pending ADC interrupts.
@ -1196,7 +1168,6 @@ __STATIC_INLINE void ADC_IntClear(ADC_TypeDef *adc, uint32_t flags)
adc->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more ADC interrupts.
@ -1213,7 +1184,6 @@ __STATIC_INLINE void ADC_IntDisable(ADC_TypeDef *adc, uint32_t flags)
adc->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more ADC interrupts.
@ -1235,7 +1205,6 @@ __STATIC_INLINE void ADC_IntEnable(ADC_TypeDef *adc, uint32_t flags)
adc->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending ADC interrupt flags.
@ -1255,7 +1224,6 @@ __STATIC_INLINE uint32_t ADC_IntGet(ADC_TypeDef *adc)
return adc->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending ADC interrupt flags.
@ -1287,7 +1255,6 @@ __STATIC_INLINE uint32_t ADC_IntGetEnabled(ADC_TypeDef *adc)
return adc->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending ADC interrupts from SW.
@ -1304,7 +1271,6 @@ __STATIC_INLINE void ADC_IntSet(ADC_TypeDef *adc, uint32_t flags)
adc->IFS = flags;
}
/***************************************************************************//**
* @brief
* Start scan sequence and/or single conversion.
@ -1320,7 +1286,6 @@ __STATIC_INLINE void ADC_Start(ADC_TypeDef *adc, ADC_Start_TypeDef cmd)
adc->CMD = (uint32_t)cmd;
}
/** @} (end addtogroup ADC) */
/** @} (end addtogroup emlib) */

13
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_aes.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_aes.h
* @brief Advanced encryption standard (AES) accelerator peripheral API.
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -202,7 +202,6 @@ __STATIC_INLINE void AES_IntClear(uint32_t flags)
AES->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more AES interrupts.
@ -216,7 +215,6 @@ __STATIC_INLINE void AES_IntDisable(uint32_t flags)
AES->IEN &= ~(flags);
}
/***************************************************************************//**
* @brief
* Enable one or more AES interrupts.
@ -235,7 +233,6 @@ __STATIC_INLINE void AES_IntEnable(uint32_t flags)
AES->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending AES interrupt flags.
@ -252,7 +249,6 @@ __STATIC_INLINE uint32_t AES_IntGet(void)
return AES->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending AES interrupt flags.
@ -275,7 +271,6 @@ __STATIC_INLINE uint32_t AES_IntGetEnabled(void)
return AES->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending AES interrupts from SW.
@ -289,7 +284,6 @@ __STATIC_INLINE void AES_IntSet(uint32_t flags)
AES->IFS = flags;
}
void AES_OFB128(uint8_t *out,
const uint8_t *in,
unsigned int len,
@ -304,7 +298,6 @@ void AES_OFB256(uint8_t *out,
const uint8_t *iv);
#endif
/** @} (end addtogroup AES) */
/** @} (end addtogroup emlib) */
@ -314,5 +307,3 @@ void AES_OFB256(uint8_t *out,
#endif /* defined(AES_COUNT) && (AES_COUNT > 0) */
#endif /* EM_AES_H */

4
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_assert.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_assert.h
* @brief Emlib peripheral API "assert" implementation.
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*

42
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_burtc.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_burtc.h
* @brief Backup Real Time Counter (BURTC) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -73,8 +73,7 @@ extern "C" {
******************************************************************************/
/** BURTC clock selection */
typedef enum
{
typedef enum {
/** Ultra low frequency (1 kHz) clock */
burtcClkSelULFRCO = BURTC_CTRL_CLKSEL_ULFRCO,
/** Low frequency RC oscillator */
@ -83,10 +82,8 @@ typedef enum
burtcClkSelLFXO = BURTC_CTRL_CLKSEL_LFXO
} BURTC_ClkSel_TypeDef;
/** BURTC mode of operation */
typedef enum
{
typedef enum {
/** Disable BURTC */
burtcModeDisable = BURTC_CTRL_MODE_DISABLE,
/** Enable and start BURTC counter in EM0 to EM2 */
@ -98,8 +95,7 @@ typedef enum
} BURTC_Mode_TypeDef;
/** BURTC low power mode */
typedef enum
{
typedef enum {
/** Low Power Mode is disabled */
burtcLPDisable = BURTC_LPMODE_LPMODE_DISABLE,
/** Low Power Mode is always enabled */
@ -113,8 +109,7 @@ typedef enum
******************************************************************************/
/** BURTC initialization structure. */
typedef struct
{
typedef struct {
bool enable; /**< Enable BURTC after initialization (starts counter) */
BURTC_Mode_TypeDef mode; /**< Configure energy mode operation */
@ -162,7 +157,6 @@ __STATIC_INLINE void BURTC_IntClear(uint32_t flags)
BURTC->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more BURTC interrupts.
@ -177,7 +171,6 @@ __STATIC_INLINE void BURTC_IntDisable(uint32_t flags)
BURTC->IEN &= ~(flags);
}
/***************************************************************************//**
* @brief
* Enable one or more BURTC interrupts.
@ -197,7 +190,6 @@ __STATIC_INLINE void BURTC_IntEnable(uint32_t flags)
BURTC->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending BURTC interrupt flags.
@ -214,7 +206,6 @@ __STATIC_INLINE uint32_t BURTC_IntGet(void)
return(BURTC->IF);
}
/***************************************************************************//**
* @brief
* Get enabled and pending BURTC interrupt flags.
@ -238,7 +229,6 @@ __STATIC_INLINE uint32_t BURTC_IntGetEnabled(void)
return BURTC->IF & tmp;
}
/***************************************************************************//**
* @brief
* Set one or more pending BURTC interrupts from SW.
@ -253,7 +243,6 @@ __STATIC_INLINE void BURTC_IntSet(uint32_t flags)
BURTC->IFS = flags;
}
/***************************************************************************//**
* @brief
* Status of BURTC RAM, timestamp and LP Mode
@ -265,7 +254,6 @@ __STATIC_INLINE uint32_t BURTC_Status(void)
return BURTC->STATUS;
}
/***************************************************************************//**
* @brief
* Clear and reset BURTC status register
@ -275,7 +263,6 @@ __STATIC_INLINE void BURTC_StatusClear(void)
BURTC->CMD = BURTC_CMD_CLRSTATUS;
}
/***************************************************************************//**
* @brief
* Enable or Disable BURTC peripheral reset and start counter
@ -289,17 +276,13 @@ __STATIC_INLINE void BURTC_Enable(bool enable)
&& ((BURTC->CTRL & _BURTC_CTRL_MODE_MASK)
!= BURTC_CTRL_MODE_DISABLE))
|| (enable == false));
if (enable)
{
if (enable) {
BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0);
}
else
{
} else {
BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1);
}
}
/***************************************************************************//**
* @brief Get BURTC counter
*
@ -311,7 +294,6 @@ __STATIC_INLINE uint32_t BURTC_CounterGet(void)
return BURTC->CNT;
}
/***************************************************************************//**
* @brief Get BURTC timestamp for entering BU
*
@ -323,7 +305,6 @@ __STATIC_INLINE uint32_t BURTC_TimestampGet(void)
return BURTC->TIMESTAMP;
}
/***************************************************************************//**
* @brief Freeze register updates until enabled
* @param[in] enable If true, registers are not updated until enabled again.
@ -333,7 +314,6 @@ __STATIC_INLINE void BURTC_FreezeEnable(bool enable)
BUS_RegBitWrite(&BURTC->FREEZE, _BURTC_FREEZE_REGFREEZE_SHIFT, enable);
}
/***************************************************************************//**
* @brief Shut down power to rentention register bank.
* @param[in] enable
@ -347,7 +327,6 @@ __STATIC_INLINE void BURTC_Powerdown(bool enable)
BUS_RegBitWrite(&BURTC->POWERDOWN, _BURTC_POWERDOWN_RAM_SHIFT, enable);
}
/***************************************************************************//**
* @brief
* Set a value in one of the retention registers
@ -364,7 +343,6 @@ __STATIC_INLINE void BURTC_RetRegSet(uint32_t num, uint32_t data)
BURTC->RET[num].REG = data;
}
/***************************************************************************//**
* @brief
* Read a value from one of the retention registers
@ -379,7 +357,6 @@ __STATIC_INLINE uint32_t BURTC_RetRegGet(uint32_t num)
return BURTC->RET[num].REG;
}
/***************************************************************************//**
* @brief
* Lock BURTC registers, will protect from writing new config settings
@ -389,7 +366,6 @@ __STATIC_INLINE void BURTC_Lock(void)
BURTC->LOCK = BURTC_LOCK_LOCKKEY_LOCK;
}
/***************************************************************************//**
* @brief
* Unlock BURTC registers, enable write access to change configuration
@ -399,7 +375,6 @@ __STATIC_INLINE void BURTC_Unlock(void)
BURTC->LOCK = BURTC_LOCK_LOCKKEY_UNLOCK;
}
void BURTC_Reset(void);
void BURTC_Init(const BURTC_Init_TypeDef *burtcInit);
void BURTC_CounterReset(void);
@ -407,7 +382,6 @@ void BURTC_CompareSet(unsigned int comp, uint32_t value);
uint32_t BURTC_CompareGet(unsigned int comp);
uint32_t BURTC_ClockFreqGet(void);
/** @} (end addtogroup BURTC) */
/** @} (end addtogroup emlib) */

12
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bus.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_bus.h
* @brief RAM and peripheral bit-field set and clear API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -89,7 +89,6 @@ __STATIC_INLINE void BUS_RamBitWrite(volatile uint32_t *addr,
#endif
}
/***************************************************************************//**
* @brief
* Perform a single-bit read operation on a 32-bit word in RAM
@ -124,7 +123,6 @@ __STATIC_INLINE unsigned int BUS_RamBitRead(volatile const uint32_t *addr,
#endif
}
/***************************************************************************//**
* @brief
* Perform a single-bit write operation on a peripheral register
@ -162,7 +160,6 @@ __STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr,
#endif
}
/***************************************************************************//**
* @brief
* Perform a single-bit read operation on a peripheral register
@ -197,7 +194,6 @@ __STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr,
#endif
}
/***************************************************************************//**
* @brief
* Perform a masked set operation on peripheral register address.
@ -229,7 +225,6 @@ __STATIC_INLINE void BUS_RegMaskedSet(volatile uint32_t *addr,
#endif
}
/***************************************************************************//**
* @brief
* Perform a masked clear operation on peripheral register address.
@ -261,7 +256,6 @@ __STATIC_INLINE void BUS_RegMaskedClear(volatile uint32_t *addr,
#endif
}
/***************************************************************************//**
* @brief
* Perform peripheral register masked clear and value write.
@ -297,7 +291,6 @@ __STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr,
#endif
}
/***************************************************************************//**
* @brief
* Perform a peripheral register masked read
@ -321,7 +314,6 @@ __STATIC_INLINE uint32_t BUS_RegMaskedRead(volatile const uint32_t *addr,
return *addr & mask;
}
/** @} (end addtogroup BUS) */
/** @} (end addtogroup emlib) */

596
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_can.h Normal file
View File

@ -0,0 +1,596 @@
/***************************************************************************//**
* @file em_can.h
* @brief Controller Area Network API
* @version 5.3.3
*******************************************************************************
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
* obligation to support this Software. Silicon Labs is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Silicon Labs will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
******************************************************************************/
#ifndef EM_CAN_H
#define EM_CAN_H
#include "em_bus.h"
#include "em_device.h"
#include <stdbool.h>
#if defined(CAN_COUNT) && (CAN_COUNT > 0)
#ifdef __cplusplus
extern "C" {
#endif
/***************************************************************************//**
* @addtogroup emlib
* @{
******************************************************************************/
/***************************************************************************//**
* @addtogroup CAN
* @{
******************************************************************************/
/*******************************************************************************
******************************* DEFINES ***********************************
******************************************************************************/
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
/** CAN Status codes */
typedef enum {
/** No error occurred during last CAN bus event. */
canErrorNoError = CAN_STATUS_LEC_NONE,
/**
* More than 5 equal bits in a sequence have occurred in a part of a received
* message where this is not allowed.
*/
canErrorStuff = CAN_STATUS_LEC_STUFF,
/** A fixed format part of a received frame has the wrong format. */
canErrorForm = CAN_STATUS_LEC_FORM,
/** The message this CAN Core transmitted was not acknowledged by another node. */
canErrorAck = CAN_STATUS_LEC_ACK,
/** Wrong monitored bus value : dominant when the module wanted to send a recessive. */
canErrorBit1 = CAN_STATUS_LEC_BIT1,
/** Wrong monitored bus value : recessive when the module intended to send a dominant. */
canErrorBit0 = CAN_STATUS_LEC_BIT0,
/** CRC check sum incorrect. */
canErrorCrc = CAN_STATUS_LEC_CRC,
/** Unused. No new error since the cpu wrote this value */
canErrorUnused = CAN_STATUS_LEC_UNUSED
} CAN_ErrorCode_TypeDef;
/** CAN peripheral mode */
typedef enum {
/** CAN peripheral in Normal mode : ready to send and receive messages */
canModeNormal,
/** CAN peripheral in Basic mode : no use of the RAM */
canModeBasic,
/**
* CAN peripheral in Loopback mode : input from the CAN bus is disregarded
* and comes from TX instead
*/
canModeLoopBack,
/**
* CAN peripheral in SilentLoopback mode : input from the CAN bus is
* disregarded and comes from TX instead ; no output on the CAN bus
*/
canModeSilentLoopBack,
/** CAN peripheral in Silent mode : no output on the CAN bus. If required to
* send a dominant bit, it's rerouted internally so that the CAN module
* monitors it but the CAN bus stays recessive.
*/
canModeSilent
} CAN_Mode_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** CAN Message Object TypeDef structure. LSBs is used */
typedef struct {
/** Message number of this Message Object, [1 - 32] */
uint8_t msgNum;
/** Id extended if true, standard if false */
bool extended;
/**
* Id of the message, with 11 bits (standard) or 28 bits (extended).
* LSBs are used for both of them
*/
uint32_t id;
/** Data Length Code [0 - 8] */
uint8_t dlc;
/** Pointer to the data, [0 - 8] bytes */
uint8_t data[8];
/** Mask for id filtering */
uint32_t mask;
/** Enable the use of 'extended' value for filtering */
bool extendedMask;
/** Enable the use of 'direction' value for filtering */
bool directionMask;
} CAN_MessageObject_TypeDef;
/** CAN initialization structure. */
typedef struct {
/** true to set the CAN Device in normal mode after init */
bool enable;
/** True to reset messages during initialization */
bool resetMessages;
/** Default bitrate */
uint32_t bitrate;
/** Default Propagation Time Segment */
uint8_t propagationTimeSegment;
/** Default Phase Buffer Segment 1 */
uint8_t phaseBufferSegment1;
/** Default Phase Buffer Segment 2 */
uint8_t phaseBufferSegment2;
/** Default Synchronisation Jump Width */
uint8_t synchronisationJumpWidth;
} CAN_Init_TypeDef;
/**
* Default initialization of CAN_Init_TypeDef. The total duration of a bit with
* these default parameters is 10 tq (time quantum : tq = brp/fsys, brp being
* the baudrate prescaler and being set according to the wanted bitrate, fsys
* beeing the CAN Device frequency).
*/
#define CAN_INIT_DEFAULT \
{ \
true, /** Set the CAN Device in normal mode after init */ \
true, /** Reset messages during initialization */ \
100000, /** Set bitrate to 100 000 */ \
1, /** Set the Propagation Time Segment to 1 */ \
4, /** Set the Phase Buffer Segment 1 to 4 */ \
4, /** Set the Phase Buffer Segment 2 to 4 */ \
1 /** Set the Synchronization Jump Width to 1 */ \
}
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
void CAN_Init(CAN_TypeDef *can, const CAN_Init_TypeDef *init);
uint32_t CAN_GetClockFrequency(CAN_TypeDef *can);
bool CAN_MessageLost(CAN_TypeDef *can, uint8_t interface, uint8_t msgNum);
void CAN_SetRoute(CAN_TypeDef *can,
bool active,
uint16_t pinRxLoc,
uint16_t pinTxLoc);
void CAN_SetBitTiming(CAN_TypeDef *can,
uint32_t bitrate,
uint16_t propagationTimeSegment,
uint16_t phaseBufferSegment1,
uint16_t phaseBufferSegment2,
uint16_t synchronisationJumpWidth);
void CAN_SetMode(CAN_TypeDef *can, CAN_Mode_TypeDef mode);
void CAN_SetIdAndFilter(CAN_TypeDef *can,
uint8_t interface,
bool useMask,
const CAN_MessageObject_TypeDef *message,
bool wait);
void CAN_ConfigureMessageObject(CAN_TypeDef *can,
uint8_t interface,
uint8_t msgNum,
bool valid,
bool tx,
bool remoteTransfer,
bool endOfBuffer,
bool wait);
void CAN_SendMessage(CAN_TypeDef *can,
uint8_t interface,
const CAN_MessageObject_TypeDef *message,
bool wait);
void CAN_ReadMessage(CAN_TypeDef *can,
uint8_t interface,
CAN_MessageObject_TypeDef *message);
void CAN_AbortSendMessage(CAN_TypeDef *can,
uint8_t interface,
uint8_t msgNum,
bool wait);
void CAN_ResetMessages(CAN_TypeDef *can, uint8_t interface);
void CAN_Reset(CAN_TypeDef *can);
void CAN_WriteData(CAN_TypeDef *can,
uint8_t interface,
const CAN_MessageObject_TypeDef *message);
void CAN_SendRequest(CAN_TypeDef *can,
uint8_t interface,
uint8_t msgNum,
bool wait);
/***************************************************************************//**
* @brief
* Enable the Host Controller to send messages.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] enable
* true to enable CAN device, false to disable it. If the CAN device is
* enabled, it goes in normal mode (the default working mode).
******************************************************************************/
__STATIC_INLINE void CAN_Enable(CAN_TypeDef *can, bool enable)
{
BUS_RegBitWrite(&can->CTRL, _CAN_CTRL_INIT_SHIFT, (enable ? 0 : 1));
}
/***************************************************************************//**
* @brief
* Gives the communication capabilities state.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @return
* true if the Host Controller can send messages, false otherwise.
******************************************************************************/
__STATIC_INLINE bool CAN_IsEnabled(CAN_TypeDef *can)
{
return (can->CTRL & _CAN_CTRL_INIT_MASK) == 0;
}
/***************************************************************************//**
* @brief
* Waiting function.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] interface
* Indicate which Message Interface Register to use.
*
******************************************************************************/
__STATIC_INLINE void CAN_ReadyWait(CAN_TypeDef *can,
uint8_t interface)
{
while ((_CAN_MIR_CMDREQ_BUSY_MASK & can->MIR[interface].CMDREQ) != 0) {
}
}
/***************************************************************************//**
* @brief
* Get the last error code and clear its register.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @return
* return Last error code.
******************************************************************************/
__STATIC_INLINE CAN_ErrorCode_TypeDef CAN_GetLastErrorCode(CAN_TypeDef *can)
{
CAN_ErrorCode_TypeDef errorCode = (CAN_ErrorCode_TypeDef)
(can->STATUS & _CAN_STATUS_LEC_MASK);
can->STATUS |= ~_CAN_STATUS_LEC_MASK;
return errorCode;
}
/***************************************************************************//**
* @brief
* Indicates which messages objects have received new data.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @return
* State of MESSAGEDATA register indicating which messages objects have received
* new data.
******************************************************************************/
__STATIC_INLINE uint32_t CAN_HasNewdata(CAN_TypeDef *can)
{
return can->MESSAGEDATA;
}
/***************************************************************************//**
* @brief
* Clear one or more pending CAN status interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] flags
* Pending CAN status interrupt source(s) to clear.
******************************************************************************/
__STATIC_INLINE void CAN_StatusIntClear(CAN_TypeDef *can, uint32_t flags)
{
can->IF1IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable CAN status interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] flags
* CAN status interrupt source(s) to disable.
******************************************************************************/
__STATIC_INLINE void CAN_StatusIntDisable(CAN_TypeDef *can, uint32_t flags)
{
can->IF1IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable CAN status interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] flags
* CAN status interrupt source(s) to enable.
******************************************************************************/
__STATIC_INLINE void CAN_StatusIntEnable(CAN_TypeDef *can, uint32_t flags)
{
can->IF1IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending CAN status interrupt flags.
*
* @note
* The event bits are not cleared by the use of this function.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @return
* CAN interrupt source(s) pending.
******************************************************************************/
__STATIC_INLINE uint32_t CAN_StatusIntGet(CAN_TypeDef *can)
{
return can->IF1IF;
}
/***************************************************************************//**
* @brief
* Get pending and enabled CAN status interrupt flags.
*
* @note
* The event bits are not cleared by the use of this function.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @return
* CAN interrupt source(s) pending and enabled.
******************************************************************************/
__STATIC_INLINE uint32_t CAN_StatusIntGetEnabled(CAN_TypeDef *can)
{
uint32_t ien;
ien = can->IF1IEN;
return can->IF1IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more CAN status interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] flags
* CAN status interrupt source(s) to set to pending.
******************************************************************************/
__STATIC_INLINE void CAN_StatusIntSet(CAN_TypeDef *can, uint32_t flags)
{
can->IF1IFS = flags;
}
/***************************************************************************//**
* @brief
* Get CAN status.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @return
* Value of CAN register STATUS.
******************************************************************************/
__STATIC_INLINE uint32_t CAN_StatusGet(CAN_TypeDef *can)
{
return can->STATUS & ~_CAN_STATUS_LEC_MASK;
}
/***************************************************************************//**
* @brief
* Clear CAN status.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] flags
* CAN status bits to clear.
******************************************************************************/
__STATIC_INLINE void CAN_StatusClear(CAN_TypeDef *can, uint32_t flags)
{
can->STATUS &= ~flags;
}
/***************************************************************************//**
* @brief
* Get the error count.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @return
* Error count.
******************************************************************************/
__STATIC_INLINE uint32_t CAN_GetErrorCount(CAN_TypeDef *can)
{
return can->ERRCNT;
}
/***************************************************************************//**
* @brief
* Clear one or more pending CAN message interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] flags
* Pending CAN message interrupt source(s) to clear.
******************************************************************************/
__STATIC_INLINE void CAN_MessageIntClear(CAN_TypeDef *can, uint32_t flags)
{
can->IF0IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable CAN message interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] flags
* CAN message interrupt source(s) to disable.
******************************************************************************/
__STATIC_INLINE void CAN_MessageIntDisable(CAN_TypeDef *can, uint32_t flags)
{
can->IF0IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable CAN message interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] flags
* CAN message interrupt source(s) to enable.
******************************************************************************/
__STATIC_INLINE void CAN_MessageIntEnable(CAN_TypeDef *can, uint32_t flags)
{
can->IF0IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending CAN message interrupt flags.
*
* @note
* The event bits are not cleared by the use of this function.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @return
* CAN message interrupt source(s) pending.
******************************************************************************/
__STATIC_INLINE uint32_t CAN_MessageIntGet(CAN_TypeDef *can)
{
return can->IF0IF;
}
/***************************************************************************//**
* @brief
* Get CAN message interrupt flags that are pending and enabled.
*
* @note
* The event bits are not cleared by the use of this function.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @return
* CAN message interrupt source(s) pending and enabled.
******************************************************************************/
__STATIC_INLINE uint32_t CAN_MessageIntGetEnabled(CAN_TypeDef *can)
{
uint32_t ien;
ien = can->IF0IEN;
return can->IF0IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more CAN message interrupts.
*
* @param[in] can
* Pointer to CAN peripheral register block.
*
* @param[in] flags
* CAN message interrupt source(s) to set to pending.
******************************************************************************/
__STATIC_INLINE void CAN_MessageIntSet(CAN_TypeDef *can, uint32_t flags)
{
can->IF0IFS = flags;
}
/** @} (end addtogroup CAN) */
/** @} (end addtogroup emlib) */
#ifdef __cplusplus
}
#endif
#endif /* defined(CAN_COUNT) && (CAN_COUNT > 0) */
#endif /* EM_CAN_H */

79
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_chip.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_chip.h
* @brief Chip Initialization API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -76,8 +76,7 @@ __STATIC_INLINE void CHIP_Init(void)
rev = *(volatile uint32_t *)(0x0FE081FC);
/* Engineering Sample calibration setup */
if ((rev >> 24) == 0)
{
if ((rev >> 24) == 0) {
reg = (volatile uint32_t *)0x400CA00C;
*reg &= ~(0x70UL);
/* DREG */
@ -85,8 +84,7 @@ __STATIC_INLINE void CHIP_Init(void)
*reg &= ~(0xE0000000UL);
*reg |= ~(7UL << 25);
}
if ((rev >> 24) <= 3)
{
if ((rev >> 24) <= 3) {
/* DREG */
reg = (volatile uint32_t *)0x400C6020;
*reg &= ~(0x00001F80UL);
@ -104,12 +102,10 @@ __STATIC_INLINE void CHIP_Init(void)
}
SYSTEM_ChipRevisionGet(&chipRev);
if (chipRev.major == 0x01)
{
if (chipRev.major == 0x01) {
/* Rev A errata handling for EM2/3. Must enable DMA clock in order for EM2/3 */
/* to work. This will be fixed in later chip revisions, so only do for rev A. */
if (chipRev.minor == 00)
{
if (chipRev.minor == 00) {
reg = (volatile uint32_t *)0x400C8040;
*reg |= 0x2;
}
@ -117,16 +113,14 @@ __STATIC_INLINE void CHIP_Init(void)
/* Rev A+B errata handling for I2C when using EM2/3. USART0 clock must be enabled */
/* after waking up from EM2/EM3 in order for I2C to work. This will be fixed in */
/* later chip revisions, so only do for rev A+B. */
if (chipRev.minor <= 0x01)
{
if (chipRev.minor <= 0x01) {
reg = (volatile uint32_t *)0x400C8044;
*reg |= 0x1;
}
}
/* Ensure correct ADC/DAC calibration value */
rev = *(volatile uint32_t *)0x0FE081F0;
if (rev < 0x4C8ABA00)
{
if (rev < 0x4C8ABA00) {
uint32_t cal;
/* Enable ADC/DAC clocks */
@ -134,17 +128,17 @@ __STATIC_INLINE void CHIP_Init(void)
*reg |= (1 << 14 | 1 << 11);
/* Retrive calibration values */
cal = ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) >>
8) << 24;
cal = ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL)
>> 8) << 24;
cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) >>
0) << 16;
cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL)
>> 0) << 16;
cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) >>
8) << 8;
cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL)
>> 8) << 8;
cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) >>
0) << 0;
cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL)
>> 0) << 0;
/* ADC0->CAL = 1.25 reference */
reg = (volatile uint32_t *)0x40002034UL;
@ -172,8 +166,7 @@ __STATIC_INLINE void CHIP_Init(void)
prodRev = SYSTEM_GetProdRev();
SYSTEM_ChipRevisionGet(&chipRev);
if ((prodRev >= 16) && (chipRev.minor >= 3))
{
if ((prodRev >= 16) && (chipRev.minor >= 3)) {
/* This fixes an issue with the LFXO on high temperatures. */
*(volatile uint32_t*)0x400C80C0 =
(*(volatile uint32_t*)0x400C80C0 & ~(1 << 6) ) | (1 << 4);
@ -185,8 +178,7 @@ __STATIC_INLINE void CHIP_Init(void)
uint8_t prodRev;
prodRev = SYSTEM_GetProdRev();
if (prodRev <= 129)
{
if (prodRev <= 129) {
/* This fixes a mistaken internal connection between PC0 and PC4 */
/* This disables an internal pulldown on PC4 */
*(volatile uint32_t*)(0x400C6018) = (1 << 26) | (5 << 0);
@ -215,8 +207,7 @@ __STATIC_INLINE void CHIP_Init(void)
SYSTEM_ChipRevisionGet(&chipRev);
/* This errata is fixed in hardware from PRODREV 0x8F. */
if (prodRev < 0x8F)
{
if (prodRev < 0x8F) {
/* Fixes for errata GPIO_E201 (slewrate) */
/* Save HFBUSCLK enable state and enable GPIO clock. */
@ -224,8 +215,7 @@ __STATIC_INLINE void CHIP_Init(void)
CMU->HFBUSCLKEN0 = clkEn | CMU_HFBUSCLKEN0_GPIO;
/* Update slewrate */
for(port = 0; port <= GPIO_PORT_MAX; port++)
{
for (port = 0; port <= GPIO_PORT_MAX; port++) {
GPIO->P[port].CTRL = setVal | resetVal;
}
@ -234,19 +224,25 @@ __STATIC_INLINE void CHIP_Init(void)
}
/* This errata is fixed in hardware from PRODREV 0x90. */
if (prodRev < 0x90)
{
if (prodRev < 0x90) {
/* HFXO high temperature oscillator startup robustness fix */
CMU->HFXOSTARTUPCTRL =
(CMU->HFXOSTARTUPCTRL & ~_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK)
| (0x20 << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT);
}
if (chipRev.major == 0x01)
{
if (chipRev.major == 0x01) {
/* Fix for errata EMU_E210 - Potential Power-Down When Entering EM2 */
*(volatile uint32_t *)(EMU_BASE + 0x164) |= 0x4;
}
#if defined(_EFR_DEVICE)
/****************************
* Fix for errata DCDC_E206
* Disable bypass limit enabled temporarily in SystemInit() errata
* workaround. */
BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0);
#endif
#endif
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
@ -254,14 +250,12 @@ __STATIC_INLINE void CHIP_Init(void)
uint8_t prodRev = SYSTEM_GetProdRev();
/* EM2 current fixes for early samples */
if (prodRev == 0)
{
if (prodRev == 0) {
*(volatile uint32_t *)(EMU_BASE + 0x190) = 0x0000ADE8UL;
*(volatile uint32_t *)(EMU_BASE + 0x198) |= (0x1 << 2);
*(volatile uint32_t *)(EMU_BASE + 0x190) = 0x0;
}
if (prodRev < 2)
{
if (prodRev < 2) {
*(volatile uint32_t *)(EMU_BASE + 0x164) |= (0x1 << 13);
}
@ -275,7 +269,14 @@ __STATIC_INLINE void CHIP_Init(void)
MSC->CTRL |= 0x1 << 8;
#endif
/* Set validated PLFRCO trims for production revision < 5. Overwriting registers
for all production revisions is safe. */
#if defined(_SILICON_LABS_32B_SERIES_1) && defined(_CMU_STATUS_PLFRCOENS_MASK)
*(volatile uint32_t *)(CMU_BASE + 0x28C) = 0x258;
*(volatile uint32_t *)(CMU_BASE + 0x290) = 0x55D4A;
*(volatile uint32_t *)(CMU_BASE + 0x2FC) = 0x16E228;
*(volatile uint32_t *)(CMU_BASE + 0x294) = 0x1E0;
#endif
}
/** @} (end addtogroup CHIP) */

519
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_cmu.h
* @brief Clock management unit (CMU) API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -64,6 +64,11 @@ extern "C" {
#define CMU_LFECLKSEL_REG 5
#define CMU_DBGCLKSEL_REG 6
#define CMU_USBCCLKSEL_REG 7
#define CMU_ADC0ASYNCSEL_REG 8
#define CMU_ADC1ASYNCSEL_REG 9
#define CMU_SDIOREFSEL_REG 10
#define CMU_QSPI0REFSEL_REG 11
#define CMU_USBRCLKSEL_REG 12
#define CMU_SEL_REG_POS 0
#define CMU_SEL_REG_MASK 0xf
@ -82,6 +87,7 @@ extern "C" {
#define CMU_LFAPRESC0_REG 6
#define CMU_LFBPRESC0_REG 7
#define CMU_LFEPRESC0_REG 8
#define CMU_ADCASYNCDIV_REG 9
#define CMU_PRESC_REG_POS 4
#define CMU_DIV_REG_POS CMU_PRESC_REG_POS
@ -100,6 +106,11 @@ extern "C" {
#define CMU_LFCCLKEN0_EN_REG 8
#define CMU_LFECLKEN0_EN_REG 9
#define CMU_PCNT_EN_REG 10
#define CMU_SDIOREF_EN_REG 11
#define CMU_QSPI0REF_EN_REG 12
#define CMU_QSPI1REF_EN_REG 13
#define CMU_HFPERCLKEN1_EN_REG 14
#define CMU_USBRCLK_EN_REG 15
#define CMU_EN_REG_POS 8
#define CMU_EN_REG_MASK 0xf
@ -131,6 +142,11 @@ extern "C" {
#define CMU_LCD_CLK_BRANCH 20
#define CMU_LESENSE_CLK_BRANCH 21
#define CMU_CSEN_LF_CLK_BRANCH 22
#define CMU_ADC0ASYNC_CLK_BRANCH 23
#define CMU_ADC1ASYNC_CLK_BRANCH 24
#define CMU_SDIOREF_CLK_BRANCH 25
#define CMU_QSPI0REF_CLK_BRANCH 26
#define CMU_USBR_CLK_BRANCH 27
#define CMU_CLK_BRANCH_POS 17
#define CMU_CLK_BRANCH_MASK 0x1f
@ -139,6 +155,14 @@ extern "C" {
/* Max clock frequency for VSCALE voltages */
#define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 20000000
#endif
#if defined(USB_PRESENT) && defined(_CMU_HFCORECLKEN0_USBC_MASK)
#define USBC_CLOCK_PRESENT
#endif
#if defined(USB_PRESENT) && defined(_CMU_USBCTRL_MASK)
#define USBR_CLOCK_PRESENT
#endif
/** @endcond */
/*******************************************************************************
@ -173,8 +197,7 @@ typedef uint32_t CMU_ClkPresc_TypeDef;
#if defined(_CMU_HFRCOCTRL_BAND_MASK)
/** High frequency system RCO bands */
typedef enum
{
typedef enum {
cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ, /**< 1MHz HFRCO band */
cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ, /**< 7MHz HFRCO band */
cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ, /**< 11MHz HFRCO band */
@ -188,8 +211,7 @@ typedef enum
#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK)
/** AUX High frequency RCO bands */
typedef enum
{
typedef enum {
cmuAUXHFRCOBand_1MHz = _CMU_AUXHFRCOCTRL_BAND_1MHZ, /**< 1MHz RC band */
cmuAUXHFRCOBand_7MHz = _CMU_AUXHFRCOCTRL_BAND_7MHZ, /**< 7MHz RC band */
cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ, /**< 11MHz RC band */
@ -203,8 +225,7 @@ typedef enum
#if defined(_CMU_USHFRCOCONF_BAND_MASK)
/** USB High frequency RC bands. */
typedef enum
{
typedef enum {
/** 24MHz RC band. */
cmuUSHFRCOBand_24MHz = _CMU_USHFRCOCONF_BAND_24MHZ,
/** 48MHz RC band. */
@ -212,10 +233,22 @@ typedef enum
} CMU_USHFRCOBand_TypeDef;
#endif
#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK)
/** High USHFRCO bands */
typedef enum {
cmuUSHFRCOFreq_16M0Hz = 16000000U, /**< 16MHz RC band */
cmuUSHFRCOFreq_32M0Hz = 32000000U, /**< 32MHz RC band */
cmuUSHFRCOFreq_48M0Hz = 48000000U, /**< 48MHz RC band */
cmuUSHFRCOFreq_50M0Hz = 50000000U, /**< 50MHz RC band */
cmuUSHFRCOFreq_UserDefined = 0,
} CMU_USHFRCOFreq_TypeDef;
#define CMU_USHFRCO_MIN cmuUSHFRCOFreq_16M0Hz
#define CMU_USHFRCO_MAX cmuUSHFRCOFreq_50M0Hz
#endif
#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK)
/** High frequency system RCO bands */
typedef enum
{
typedef enum {
cmuHFRCOFreq_1M0Hz = 1000000U, /**< 1MHz RC band */
cmuHFRCOFreq_2M0Hz = 2000000U, /**< 2MHz RC band */
cmuHFRCOFreq_4M0Hz = 4000000U, /**< 4MHz RC band */
@ -226,16 +259,37 @@ typedef enum
cmuHFRCOFreq_26M0Hz = 26000000U, /**< 26MHz RC band */
cmuHFRCOFreq_32M0Hz = 32000000U, /**< 32MHz RC band */
cmuHFRCOFreq_38M0Hz = 38000000U, /**< 38MHz RC band */
#if defined(_DEVINFO_HFRCOCAL13_MASK)
cmuHFRCOFreq_48M0Hz = 48000000U, /**< 48MHz RC band */
#endif
#if defined(_DEVINFO_HFRCOCAL14_MASK)
cmuHFRCOFreq_56M0Hz = 56000000U, /**< 56MHz RC band */
#endif
#if defined(_DEVINFO_HFRCOCAL15_MASK)
cmuHFRCOFreq_64M0Hz = 64000000U, /**< 64MHz RC band */
#endif
#if defined(_DEVINFO_HFRCOCAL16_MASK)
cmuHFRCOFreq_72M0Hz = 72000000U, /**< 72MHz RC band */
#endif
cmuHFRCOFreq_UserDefined = 0,
} CMU_HFRCOFreq_TypeDef;
#define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz
#if defined(_DEVINFO_HFRCOCAL16_MASK)
#define CMU_HFRCO_MAX cmuHFRCOFreq_72M0Hz
#elif defined(_DEVINFO_HFRCOCAL15_MASK)
#define CMU_HFRCO_MAX cmuHFRCOFreq_64M0Hz
#elif defined(_DEVINFO_HFRCOCAL14_MASK)
#define CMU_HFRCO_MAX cmuHFRCOFreq_56M0Hz
#elif defined(_DEVINFO_HFRCOCAL13_MASK)
#define CMU_HFRCO_MAX cmuHFRCOFreq_48M0Hz
#else
#define CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz
#endif
#endif
#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK)
/** AUX High frequency RCO bands */
typedef enum
{
typedef enum {
cmuAUXHFRCOFreq_1M0Hz = 1000000U, /**< 1MHz RC band */
cmuAUXHFRCOFreq_2M0Hz = 2000000U, /**< 2MHz RC band */
cmuAUXHFRCOFreq_4M0Hz = 4000000U, /**< 4MHz RC band */
@ -246,16 +300,22 @@ typedef enum
cmuAUXHFRCOFreq_26M0Hz = 26000000U, /**< 26MHz RC band */
cmuAUXHFRCOFreq_32M0Hz = 32000000U, /**< 32MHz RC band */
cmuAUXHFRCOFreq_38M0Hz = 38000000U, /**< 38MHz RC band */
#if defined(_DEVINFO_AUXHFRCOCAL14_MASK)
cmuAUXHFRCOFreq_48M0Hz = 48000000U, /**< 48MHz RC band */
cmuAUXHFRCOFreq_50M0Hz = 50000000U, /**< 50MHz RC band */
#endif
cmuAUXHFRCOFreq_UserDefined = 0,
} CMU_AUXHFRCOFreq_TypeDef;
#define CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz
#if defined(_DEVINFO_AUXHFRCOCAL14_MASK)
#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_50M0Hz
#else
#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz
#endif
#endif
/** Clock points in CMU. Please refer to CMU overview in reference manual. */
typedef enum
{
typedef enum {
/*******************/
/* HF clock branch */
/*******************/
@ -351,6 +411,15 @@ typedef enum
| (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFBUSCLKEN0_QSPI0)
/** Quad SPI clock. */
cmuClock_QSPI0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFBUSCLKEN0_QSPI0_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFBUSCLKEN0_GPCRC)
/** General purpose cyclic redundancy checksum clock. */
cmuClock_GPCRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
@ -477,7 +546,6 @@ typedef enum
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFPERCLKEN0_UART0)
/** Universal async receiver/transmitter 0 clock. */
cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
@ -485,6 +553,13 @@ typedef enum
| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#elif defined(_CMU_HFPERCLKEN1_UART0_MASK)
/** Universal async receiver/transmitter 0 clock. */
cmuClock_UART0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN1_UART0_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFPERCLKEN0_UART1)
@ -494,6 +569,13 @@ typedef enum
| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#elif defined(_CMU_HFPERCLKEN1_UART1_MASK)
/** Universal async receiver/transmitter 1 clock. */
cmuClock_UART1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN1_UART1_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFPERCLKEN0_TIMER0)
@ -532,6 +614,33 @@ typedef enum
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFPERCLKEN0_TIMER4)
/** Timer 4 clock. */
cmuClock_TIMER4 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN0_TIMER4_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFPERCLKEN0_TIMER5)
/** Timer 5 clock. */
cmuClock_TIMER5 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN0_TIMER5_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFPERCLKEN0_TIMER6)
/** Timer 6 clock. */
cmuClock_TIMER6 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN0_TIMER6_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFPERCLKEN0_WTIMER0)
/** Wide Timer 0 clock. */
cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
@ -539,6 +648,13 @@ typedef enum
| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN0_WTIMER0_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#elif defined(CMU_HFPERCLKEN1_WTIMER0)
/** Wide Timer 0 clock. */
cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN1_WTIMER0_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFPERCLKEN0_WTIMER1)
@ -548,6 +664,31 @@ typedef enum
| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN0_WTIMER1_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#elif defined(CMU_HFPERCLKEN1_WTIMER1)
/** Wide Timer 1 clock. */
cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN1_WTIMER1_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFPERCLKEN1_WTIMER2)
/** Wide Timer 2 clock. */
cmuClock_WTIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN1_WTIMER2_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFPERCLKEN1_WTIMER3)
/** Wide Timer 3 clock. */
cmuClock_WTIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN1_WTIMER3_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFPERCLKEN0_CRYOTIMER)
@ -577,6 +718,24 @@ typedef enum
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFPERCLKEN0_ACMP2)
/** Analog comparator 2 clock. */
cmuClock_ACMP2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN0_ACMP2_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFPERCLKEN0_ACMP3)
/** Analog comparator 3 clock. */
cmuClock_ACMP3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN0_ACMP3_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFPERCLKEN0_PRS)
/** Peripheral reflex system clock. */
cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS)
@ -602,6 +761,13 @@ typedef enum
| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN0_VDAC0_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#elif defined(CMU_HFPERCLKEN1_VDAC0)
/** Voltage digital to analog converter 0 clock. */
cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN1_VDAC0_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFPERCLKEN0_IDAC0)
@ -640,6 +806,15 @@ typedef enum
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFPERCLKEN0_ADC1)
/** Analog to digital converter 1 clock. */
cmuClock_ADC1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN0_ADC1_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFPERCLKEN0_I2C0)
/** I2C 0 clock. */
cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
@ -674,6 +849,13 @@ typedef enum
| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#elif defined(CMU_HFPERCLKEN1_CSEN)
/** Capacitive Sense HF clock */
cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN1_CSEN_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFPERCLKEN0_TRNG0)
@ -685,6 +867,24 @@ typedef enum
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(_CMU_HFPERCLKEN1_CAN0_MASK)
/** Controller Area Network 0 clock. */
cmuClock_CAN0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN1_CAN0_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(_CMU_HFPERCLKEN1_CAN1_MASK)
/** Controller Area Network 1 clock. */
cmuClock_CAN1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN1_CAN1_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
/**********************/
/* HF core sub-branch */
/**********************/
@ -730,16 +930,48 @@ typedef enum
| (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#elif defined(_CMU_HFBUSCLKEN0_EBI_MASK)
/** External bus interface clock. */
cmuClock_EBI = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFBUSCLKEN0_EBI_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined( CMU_HFCORECLKEN0_USBC )
#if defined(_CMU_HFBUSCLKEN0_ETH_MASK)
/** Ethernet clock. */
cmuClock_ETH = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFBUSCLKEN0_ETH_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(_CMU_HFBUSCLKEN0_SDIO_MASK)
/** SDIO clock. */
cmuClock_SDIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFBUSCLKEN0_SDIO_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(USBC_CLOCK_PRESENT)
/** USB Core clock. */
cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS)
| (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined (USBR_CLOCK_PRESENT)
/** USB Rate clock. */
cmuClock_USBR = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_USBRCLKSEL_REG << CMU_SEL_REG_POS)
| (CMU_USBRCLK_EN_REG << CMU_EN_REG_POS)
| (_CMU_USBCTRL_USBCLKEN_SHIFT << CMU_EN_BIT_POS)
| (CMU_USBR_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_HFCORECLKEN0_USB)
@ -749,6 +981,13 @@ typedef enum
| (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#elif defined(CMU_HFBUSCLKEN0_USB)
/** USB clock. */
cmuClock_USB = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFBUSCLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
/***************/
@ -780,6 +1019,15 @@ typedef enum
| (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_LFACLKEN0_LETIMER1)
/** Low energy timer 1 clock. */
cmuClock_LETIMER1 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_LFACLKEN0_LETIMER1_SHIFT << CMU_EN_BIT_POS)
| (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(CMU_LFACLKEN0_LCD)
/** Liquid crystal display, pre FDIV clock. */
cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
@ -898,6 +1146,13 @@ typedef enum
| (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS)
| (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#elif defined(CMU_LFCCLKEN0_USB)
/** USB LE clock. */
cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
| (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_LFCCLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
| (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#endif
@ -906,14 +1161,14 @@ typedef enum
/* LF E branch */
/***************/
/** Low frequency A clock */
/** Low frequency E clock */
cmuClock_LFE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_LFECLKSEL_REG << CMU_SEL_REG_POS)
| (CMU_NO_EN_REG << CMU_EN_REG_POS)
| (0 << CMU_EN_BIT_POS)
| (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
/** Real time counter and calendar clock. */
/** Real-time counter and calendar clock. */
#if defined (CMU_LFECLKEN0_RTCC)
cmuClock_RTCC = (CMU_LFEPRESC0_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@ -923,6 +1178,45 @@ typedef enum
#endif
#endif
/**********************************/
/* Asynchronous peripheral clocks */
/**********************************/
#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK)
/** ADC0 asynchronous clock. */
cmuClock_ADC0ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS)
| (CMU_ADC0ASYNCSEL_REG << CMU_SEL_REG_POS)
| (CMU_NO_EN_REG << CMU_EN_REG_POS)
| (0 << CMU_EN_BIT_POS)
| (CMU_ADC0ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK)
/** ADC1 asynchronous clock. */
cmuClock_ADC1ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS)
| (CMU_ADC1ASYNCSEL_REG << CMU_SEL_REG_POS)
| (CMU_NO_EN_REG << CMU_EN_REG_POS)
| (0 << CMU_EN_BIT_POS)
| (CMU_ADC1ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(_CMU_SDIOCTRL_SDIOCLKDIS_MASK)
/** SDIO reference clock. */
cmuClock_SDIOREF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_SDIOREFSEL_REG << CMU_SEL_REG_POS)
| (CMU_SDIOREF_EN_REG << CMU_EN_REG_POS)
| (_CMU_SDIOCTRL_SDIOCLKDIS_SHIFT << CMU_EN_BIT_POS)
| (CMU_SDIOREF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#if defined(_CMU_QSPICTRL_QSPI0CLKDIS_MASK)
/** QSPI0 reference clock. */
cmuClock_QSPI0REF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_QSPI0REFSEL_REG << CMU_SEL_REG_POS)
| (CMU_QSPI0REF_EN_REG << CMU_EN_REG_POS)
| (_CMU_QSPICTRL_QSPI0CLKDIS_SHIFT << CMU_EN_BIT_POS)
| (CMU_QSPI0REF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
} CMU_Clock_TypeDef;
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
@ -930,10 +1224,8 @@ typedef enum
#define cmuClock_CORELE cmuClock_HFLE
/** @endcond */
/** Oscillator types. */
typedef enum
{
typedef enum {
cmuOsc_LFXO, /**< Low frequency crystal oscillator. */
cmuOsc_LFRCO, /**< Low frequency RC oscillator. */
cmuOsc_HFXO, /**< High frequency crystal oscillator. */
@ -951,16 +1243,14 @@ typedef enum
} CMU_Osc_TypeDef;
/** Oscillator modes. */
typedef enum
{
typedef enum {
cmuOscMode_Crystal, /**< Crystal oscillator. */
cmuOscMode_AcCoupled, /**< AC coupled buffer. */
cmuOscMode_External, /**< External digital clock. */
} CMU_OscMode_TypeDef;
/** Selectable clock sources. */
typedef enum
{
typedef enum {
cmuSelect_Error, /**< Usage error. */
cmuSelect_Disabled, /**< Clock selector disabled. */
cmuSelect_LFXO, /**< Low frequency crystal oscillator. */
@ -969,13 +1259,17 @@ typedef enum
cmuSelect_HFRCO, /**< High frequency RC oscillator. */
cmuSelect_HFCLKLE, /**< High frequency LE clock divided by 2 or 4. */
cmuSelect_AUXHFRCO, /**< Auxilliary clock source can be used for debug clock */
cmuSelect_HFSRCCLK, /**< High frequency source clock */
cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on
Tiny Gecko and for USBC (not used on Gecko) */
#if defined(CMU_STATUS_USHFRCOENS)
cmuSelect_USHFRCO, /**< USB high frequency RC oscillator */
#endif
#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2)
cmuSelect_USHFRCODIV2, /**< USB high frequency RC oscillator */
cmuSelect_USHFRCODIV2, /**< USB high frequency RC oscillator / 2 */
#endif
#if defined(CMU_HFXOCTRL_HFXOX2EN)
cmuSelect_HFXOX2, /**< High frequency crystal oscillator x 2. */
#endif
#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO)
cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */
@ -992,21 +1286,22 @@ typedef enum
/** @endcond */
#endif
#if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK)
/** HFXO tuning modes */
typedef enum
{
typedef enum {
cmuHFXOTuningMode_Auto = 0,
cmuHFXOTuningMode_PeakDetectCommand = CMU_CMD_HFXOPEAKDETSTART, /**< Run peak detect optimization only */
#if defined(CMU_CMD_HFXOSHUNTOPTSTART)
cmuHFXOTuningMode_ShuntCommand = CMU_CMD_HFXOSHUNTOPTSTART, /**< Run shunt current optimization only */
cmuHFXOTuningMode_PeakShuntCommand = CMU_CMD_HFXOPEAKDETSTART /**< Run peak and shunt current optimization */
| CMU_CMD_HFXOSHUNTOPTSTART,
#endif
} CMU_HFXOTuningMode_TypeDef;
#endif
#if defined(_CMU_CTRL_LFXOBOOST_MASK)
/** LFXO Boost values. */
typedef enum
{
typedef enum {
cmuLfxoBoost70 = 0x0,
cmuLfxoBoost100 = 0x2,
#if defined(_EMU_AUXCTRL_REDLFXOBOOST_MASK)
@ -1016,14 +1311,34 @@ typedef enum
} CMU_LFXOBoost_TypeDef;
#endif
#if defined(CMU_OSCENCMD_DPLLEN)
/** DPLL reference clock selector. */
typedef enum {
cmuDPLLClkSel_Hfxo = _CMU_DPLLCTRL_REFSEL_HFXO, /**< HFXO is DPLL reference clock. */
cmuDPLLClkSel_Lfxo = _CMU_DPLLCTRL_REFSEL_LFXO, /**< LFXO is DPLL reference clock. */
cmuDPLLClkSel_Clkin0 = _CMU_DPLLCTRL_REFSEL_CLKIN0 /**< CLKIN0 is DPLL reference clock. */
} CMU_DPLLClkSel_TypeDef;
/** DPLL reference clock edge detect selector. */
typedef enum {
cmuDPLLEdgeSel_Fall = _CMU_DPLLCTRL_EDGESEL_FALL, /**< Detect falling edge of reference clock. */
cmuDPLLEdgeSel_Rise = _CMU_DPLLCTRL_EDGESEL_RISE /**< Detect rising edge of reference clock. */
} CMU_DPLLEdgeSel_TypeDef;
/** DPLL lock mode selector. */
typedef enum {
cmuDPLLLockMode_Freq = _CMU_DPLLCTRL_MODE_FREQLL, /**< Frequency lock mode. */
cmuDPLLLockMode_Phase = _CMU_DPLLCTRL_MODE_PHASELL /**< Phase lock mode. */
} CMU_DPLLLockMode_TypeDef;
#endif // CMU_OSCENCMD_DPLLEN
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** LFXO initialization structure. Init values should be obtained from a configuration tool,
app note or xtal datasheet */
typedef struct
{
typedef struct {
#if defined(_CMU_LFXOCTRL_MASK)
uint8_t ctune; /**< CTUNE (load capacitance) value */
uint8_t gain; /**< Gain / max startup margin */
@ -1069,9 +1384,16 @@ typedef struct
/** HFXO initialization structure. Init values should be obtained from a configuration tool,
app note or xtal datasheet */
typedef struct
{
#if defined( _CMU_HFXOCTRL_MASK )
typedef struct {
#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100)
uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */
uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */
uint16_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */
uint16_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */
uint8_t timeoutPeakDetect; /**< Timeout - peak detection */
uint8_t timeoutSteady; /**< Timeout - steady-state */
uint8_t timeoutStartup; /**< Timeout - startup */
#elif defined(_CMU_HFXOCTRL_MASK)
bool lowPowerMode; /**< Enable low-power mode */
bool autoStartEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */
bool autoSelEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */
@ -1094,7 +1416,30 @@ typedef struct
CMU_OscMode_TypeDef mode; /**< Oscillator mode */
} CMU_HFXOInit_TypeDef;
#if defined( _CMU_HFXOCTRL_MASK )
#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100)
#define CMU_HFXOINIT_DEFAULT \
{ \
_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \
_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
cmuOscMode_Crystal, \
}
#define CMU_HFXOINIT_EXTERNAL_CLOCK \
{ \
_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \
_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
cmuOscMode_External, \
}
#elif defined(_CMU_HFXOCTRL_MASK)
/**
* Default HFXO initialization values for Platform 2 devices which contain a
* separate HFXOCTRL register.
@ -1108,11 +1453,11 @@ typedef struct
false, /* @deprecated no longer in use */ \
_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
0x20, /* Matching errata fix in CHIP_Init() */ \
0xA, /* Default Shunt steady-state current */ \
0x20, /* Matching errata fix in @ref CHIP_Init() */ \
0x7, /* Recommended steady-state XO core bias current */ \
0x6, /* Recommended peak detection threshold */ \
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
0x2, /* Recommended shunt optimization timeout */ \
0xA, /* Recommended peak detection timeout */ \
0x4, /* Recommended steady timeout */ \
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
@ -1127,11 +1472,11 @@ typedef struct
false, /* @deprecated no longer in use */ \
_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
0x20, /* Matching errata fix in CHIP_Init() */ \
0xA, /* Default shunt steady-state current */ \
0x20, /* Matching errata fix in @ref CHIP_Init() */ \
0x7, /* Recommended steady-state osc core bias current */ \
0x6, /* Recommended peak detection threshold */ \
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
0x2, /* Recommended shunt optimization timeout */ \
0xA, /* Recommended peak detection timeout */ \
0x4, /* Recommended steady timeout */ \
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
@ -1146,11 +1491,11 @@ typedef struct
false, /* @deprecated no longer in use */ \
0, /* Startup CTUNE=0 recommended for external clock */ \
0, /* Steady CTUNE=0 recommended for external clock */ \
_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
0xA, /* Default shunt steady-state current */ \
0, /* Startup IBTRIMXOCORE=0 recommended for external clock */ \
0, /* Steady IBTRIMXOCORE=0 recommended for external clock */ \
0x6, /* Recommended peak detection threshold */ \
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
0x2, /* Recommended shunt optimization timeout */ \
0x0, /* Peak-detect not recommended for external clock usage */ \
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES, /* Minimal steady timeout */ \
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES, /* Minimal startup timeout */ \
@ -1176,6 +1521,37 @@ typedef struct
}
#endif /* _CMU_HFXOCTRL_MASK */
#if defined(CMU_OSCENCMD_DPLLEN)
/** DPLL initialization structure. Frequency will be Fref*(N+1)/(M+1). */
typedef struct {
uint32_t frequency; /**< PLL frequency value, max 40 MHz. */
uint16_t n; /**< Factor N. 32 <= N <= 4095 */
uint16_t m; /**< Factor M. M <= 4095 */
uint8_t ssInterval; /**< Spread spectrum update interval. */
uint8_t ssAmplitude; /**< Spread spectrum amplitude. */
CMU_DPLLClkSel_TypeDef refClk; /**< Reference clock selector. */
CMU_DPLLEdgeSel_TypeDef edgeSel; /**< Reference clock edge detect selector. */
CMU_DPLLLockMode_TypeDef lockMode; /**< DPLL lock mode selector. */
bool autoRecover; /**< Enable automatic lock recovery. */
} CMU_DPLLInit_TypeDef;
/**
* DPLL initialization values for 39,998,805 Hz using LFXO as reference
* clock, M=2 and N=3661.
*/
#define CMU_DPLL_LFXO_TO_40MHZ \
{ \
39998805, /* Target frequency. */ \
3661, /* Factor N. */ \
2, /* Factor M. */ \
0, /* No spread spectrum clocking. */ \
0, /* No spread spectrum clocking. */ \
cmuDPLLClkSel_Lfxo, /* Select LFXO as reference clock. */ \
cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
true /* Enable automatic lock recovery. */ \
}
#endif // CMU_OSCENCMD_DPLLEN
/*******************************************************************************
***************************** PROTOTYPES **********************************
@ -1210,6 +1586,10 @@ uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock);
void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);
CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
#if defined(CMU_OSCENCMD_DPLLEN)
bool CMU_DPLLLock(CMU_DPLLInit_TypeDef *init);
#endif
void CMU_FreezeEnable(bool enable);
#if defined(_CMU_HFRCOCTRL_BAND_MASK)
@ -1224,6 +1604,11 @@ void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq);
uint32_t CMU_HFRCOStartupDelayGet(void);
void CMU_HFRCOStartupDelaySet(uint32_t delay);
#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK)
CMU_USHFRCOFreq_TypeDef CMU_USHFRCOBandGet(void);
void CMU_USHFRCOBandSet(CMU_USHFRCOFreq_TypeDef setFreq);
#endif
#if defined(_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK)
void CMU_HFXOAutostartEnable(uint32_t userSel,
bool enEM0EM1Start,
@ -1232,7 +1617,6 @@ void CMU_HFXOAutostartEnable(uint32_t userSel,
void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit);
uint32_t CMU_LCDClkFDIVGet(void);
void CMU_LCDClkFDIVSet(uint32_t div);
void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit);
@ -1241,12 +1625,13 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, boo
uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);
#if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK)
bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode);
bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc,
CMU_HFXOTuningMode_TypeDef mode,
bool wait);
#endif
void CMU_UpdateWaitStates(uint32_t freq, int vscale);
bool CMU_PCNTClockExternalGet(unsigned int instance);
void CMU_PCNTClockExternalSet(unsigned int instance, bool external);
@ -1255,7 +1640,7 @@ void CMU_PCNTClockExternalSet(unsigned int instance, bool exter
CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void);
void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band);
#endif
void CMU_UpdateWaitStates(uint32_t freq, int vscale);
#if defined(CMU_CALCTRL_CONT)
/***************************************************************************//**
@ -1271,20 +1656,18 @@ __STATIC_INLINE void CMU_CalibrateCont(bool enable)
}
#endif
/***************************************************************************//**
* @brief
* Starts calibration
* @note
* This call is usually invoked after CMU_CalibrateConfig() and possibly
* CMU_CalibrateCont()
* This call is usually invoked after @ref CMU_CalibrateConfig() and possibly
* @ref CMU_CalibrateCont()
******************************************************************************/
__STATIC_INLINE void CMU_CalibrateStart(void)
{
CMU->CMD = CMU_CMD_CALSTART;
}
#if defined(CMU_CMD_CALSTOP)
/***************************************************************************//**
* @brief
@ -1296,7 +1679,6 @@ __STATIC_INLINE void CMU_CalibrateStop(void)
}
#endif
/***************************************************************************//**
* @brief
* Convert dividend to logarithmic value. Only works for even
@ -1321,6 +1703,18 @@ __STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)
return log2;
}
#if defined(CMU_OSCENCMD_DPLLEN)
/***************************************************************************//**
* @brief
* Unlock the DPLL.
* @note
* The HFRCO is not turned off.
******************************************************************************/
__STATIC_INLINE void CMU_DPLLUnlock(void)
{
CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS;
}
#endif
/***************************************************************************//**
* @brief
@ -1334,7 +1728,6 @@ __STATIC_INLINE void CMU_IntClear(uint32_t flags)
CMU->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more CMU interrupts.
@ -1347,14 +1740,13 @@ __STATIC_INLINE void CMU_IntDisable(uint32_t flags)
CMU->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more CMU interrupts.
*
* @note
* Depending on the use, a pending interrupt may already be set prior to
* enabling the interrupt. Consider using CMU_IntClear() prior to enabling
* enabling the interrupt. Consider using @ref CMU_IntClear() prior to enabling
* if such a pending interrupt should be ignored.
*
* @param[in] flags
@ -1365,7 +1757,6 @@ __STATIC_INLINE void CMU_IntEnable(uint32_t flags)
CMU->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending CMU interrupts.
@ -1378,7 +1769,6 @@ __STATIC_INLINE uint32_t CMU_IntGet(void)
return CMU->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending CMU interrupt flags.
@ -1403,7 +1793,6 @@ __STATIC_INLINE uint32_t CMU_IntGetEnabled(void)
return CMU->IF & ien;
}
/**************************************************************************//**
* @brief
* Set one or more pending CMU interrupts.
@ -1416,7 +1805,6 @@ __STATIC_INLINE void CMU_IntSet(uint32_t flags)
CMU->IFS = flags;
}
/***************************************************************************//**
* @brief
* Lock the CMU in order to protect some of its registers against unintended
@ -1435,7 +1823,6 @@ __STATIC_INLINE void CMU_Lock(void)
CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
}
/***************************************************************************//**
* @brief
* Convert logarithm of 2 prescaler to division factor.
@ -1451,7 +1838,6 @@ __STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2)
return 1 << log2;
}
#if defined(_SILICON_LABS_32B_SERIES_1)
/***************************************************************************//**
* @brief
@ -1481,7 +1867,6 @@ __STATIC_INLINE uint32_t CMU_PrescToLog2(CMU_ClkPresc_TypeDef presc)
}
#endif
/***************************************************************************//**
* @brief
* Unlock the CMU so that writing to locked registers again is possible.
@ -1491,7 +1876,6 @@ __STATIC_INLINE void CMU_Unlock(void)
CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
}
#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK)
/***************************************************************************//**
* @brief
@ -1508,7 +1892,6 @@ __STATIC_INLINE CMU_HFRCOFreq_TypeDef CMU_HFRCOFreqGet(void)
return CMU_HFRCOBandGet();
}
/***************************************************************************//**
* @brief
* Set HFRCO calibration for the selected target frequency
@ -1525,7 +1908,6 @@ __STATIC_INLINE void CMU_HFRCOFreqSet(CMU_HFRCOFreq_TypeDef setFreq)
}
#endif
#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK)
/***************************************************************************//**
* @brief
@ -1542,7 +1924,6 @@ __STATIC_INLINE CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOFreqGet(void)
return CMU_AUXHFRCOBandGet();
}
/***************************************************************************//**
* @brief
* Set AUXHFRCO calibration for the selected target frequency

55
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_common.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_common.h
* @brief General purpose utilities.
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -124,9 +124,11 @@ extern "C" {
/** @brief IAR Embedded Workbench: Macro for handling non-returning functions. */
#define SL_NORETURN __noreturn
/* *INDENT-OFF* */
/** IAR Embedded Workbench: Macro for handling section placement */
#define SL_ATTRIBUTE_SECTION(X) @ X
#endif
/* *INDENT-ON* */
#define SL_ATTRIBUTE_ALIGN(X)
@ -198,18 +200,63 @@ __STATIC_INLINE uint32_t SL_CTZ(uint32_t value)
#else
uint32_t zeros;
for(zeros=0; (zeros<32) && ((value&0x1) == 0); zeros++, value>>=1);
for (zeros = 0; (zeros < 32) && ((value & 0x1) == 0); zeros++, value >>= 1) {
;
}
return zeros;
#endif
}
/* Deprecated function. New code should use @ref SL_CTZ. */
__STATIC_INLINE uint32_t EFM32_CTZ(uint32_t value)
{
return SL_CTZ(value);
}
/***************************************************************************//**
* @brief
* Reverse the bits. Use the RBIT instruction if available, else process.
*
* @param[in] value
* Data value to reverse.
*
* @return
* Reversed value.
******************************************************************************/
__STATIC_INLINE uint32_t SL_RBIT(uint32_t value)
{
uint32_t result;
#if (__CORTEX_M >= 0x03U)
result = __RBIT(value);
#else
int32_t s = 4 * 8 - 1;
result = value;
for (value >>= 1U; value; value >>= 1U) {
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s;
#endif
return result;
}
/***************************************************************************//**
* @brief
* Reverse the bits. Use the RBIT instruction if available, else process.
*
* @param[in] value
* 16-bit data value to reverse.
*
* @return
* 16-bit reversed value.
******************************************************************************/
__STATIC_INLINE uint32_t SL_RBIT16(uint32_t value)
{
return SL_RBIT(value) >> 16;
}
/** @} (end addtogroup COMMON) */
/** @} (end addtogroup emlib) */

8
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_core.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_core.h
* @brief Core interrupt handling API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -110,7 +110,7 @@ extern "C" {
#define CORE_EXIT_CRITICAL() CORE_ExitCritical(irqState)
/** CRITICAL style yield. */
#define CORE_YIELD_CRITICAL() CORE_YieldCritical(void)
#define CORE_YIELD_CRITICAL() CORE_YieldCritical()
//
// ATOMIC section macro API.
@ -142,7 +142,7 @@ extern "C" {
#define CORE_EXIT_ATOMIC() CORE_ExitAtomic(irqState)
/** ATOMIC style yield. */
#define CORE_YIELD_ATOMIC() CORE_YieldAtomic(void)
#define CORE_YIELD_ATOMIC() CORE_YieldAtomic()
//
// NVIC mask section macro API.

16
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cryotimer.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_cryotimer.h
* @brief Ultra Low Energy Timer/Counter (CRYOTIMER) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -116,8 +116,7 @@ extern "C" {
******************************************************************************/
/** Prescaler selection. */
typedef enum
{
typedef enum {
cryotimerPresc_1 = _CRYOTIMER_CTRL_PRESC_DIV1, /**< Divide clock by 1. */
cryotimerPresc_2 = _CRYOTIMER_CTRL_PRESC_DIV2, /**< Divide clock by 2. */
cryotimerPresc_4 = _CRYOTIMER_CTRL_PRESC_DIV4, /**< Divide clock by 4. */
@ -129,16 +128,14 @@ typedef enum
} CRYOTIMER_Presc_TypeDef;
/** Low frequency oscillator selection. */
typedef enum
{
typedef enum {
cryotimerOscLFRCO = _CRYOTIMER_CTRL_OSCSEL_LFRCO, /**< Select Low Frequency RC Oscillator. */
cryotimerOscLFXO = _CRYOTIMER_CTRL_OSCSEL_LFXO, /**< Select Low Frequency Crystal Oscillator. */
cryotimerOscULFRCO = _CRYOTIMER_CTRL_OSCSEL_ULFRCO, /**< Select Ultra Low Frequency RC Oscillator. */
} CRYOTIMER_Osc_TypeDef;
/** Period selection value */
typedef enum
{
typedef enum {
cryotimerPeriod_1 = 0, /**< Wakeup event after every Pre-scaled clock cycle. */
cryotimerPeriod_2 = 1, /**< Wakeup event after 2 Pre-scaled clock cycles. */
cryotimerPeriod_4 = 2, /**< Wakeup event after 4 Pre-scaled clock cycles. */
@ -179,8 +176,7 @@ typedef enum
******************************************************************************/
/** CRYOTIMER initialization structure. */
typedef struct
{
typedef struct {
/** Enable/disable counting when initialization is completed. */
bool enable;

59
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_crypto.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_crypto.h
* @brief Cryptography accelerator peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -192,6 +192,15 @@ extern "C" {
******************************************************************************/
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** Default CRYPTO instance for deprecated AES functions. */
#if !defined(DEFAULT_CRYPTO)
#if defined(CRYPTO)
#define DEFAULT_CRYPTO CRYPTO
#elif defined(CRYPTO0)
#define DEFAULT_CRYPTO CRYPTO0
#endif
#endif
/** Data sizes used by CRYPTO operations. */
#define CRYPTO_DATA_SIZE_IN_BITS (128)
#define CRYPTO_DATA_SIZE_IN_BYTES (CRYPTO_DATA_SIZE_IN_BITS / 8)
@ -478,8 +487,7 @@ typedef volatile uint32_t* CRYPTO_DDataReg_TypeDef;
typedef volatile uint32_t* CRYPTO_QDataReg_TypeDef;
/** CRYPTO modulus identifiers. */
typedef enum
{
typedef enum {
cryptoModulusBin256 = CRYPTO_WAC_MODULUS_BIN256, /**< Generic 256 bit modulus 2^256 */
cryptoModulusBin128 = CRYPTO_WAC_MODULUS_BIN128, /**< Generic 128 bit modulus 2^128 */
cryptoModulusGcmBin128 = CRYPTO_WAC_MODULUS_GCMBIN128, /**< GCM 128 bit modulus = 2^128 + 2^7 + 2^2 + 2 + 1 */
@ -498,8 +506,7 @@ typedef enum
} CRYPTO_ModulusId_TypeDef;
/** CRYPTO multiplication widths for wide arithmetic operations. */
typedef enum
{
typedef enum {
cryptoMulOperand256Bits = CRYPTO_WAC_MULWIDTH_MUL256, /**< 256 bits operands */
cryptoMulOperand128Bits = CRYPTO_WAC_MULWIDTH_MUL128, /**< 128 bits operands */
cryptoMulOperandModulusBits = CRYPTO_WAC_MULWIDTH_MULMOD /**< MUL operand width
@ -508,16 +515,14 @@ typedef enum
} CRYPTO_MulOperandWidth_TypeDef;
/** CRYPTO result widths for MUL operations. */
typedef enum
{
typedef enum {
cryptoResult128Bits = CRYPTO_WAC_RESULTWIDTH_128BIT, /**< Multiplication result width is 128 bits*/
cryptoResult256Bits = CRYPTO_WAC_RESULTWIDTH_256BIT, /**< Multiplication result width is 256 bits*/
cryptoResult260Bits = CRYPTO_WAC_RESULTWIDTH_260BIT /**< Multiplication result width is 260 bits*/
} CRYPTO_ResultWidth_TypeDef;
/** CRYPTO result widths for MUL operations. */
typedef enum
{
typedef enum {
cryptoInc1byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH1, /**< inc width is 1 byte*/
cryptoInc2byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH2, /**< inc width is 2 byte*/
cryptoInc3byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH3, /**< inc width is 3 byte*/
@ -525,8 +530,7 @@ typedef enum
} CRYPTO_IncWidth_TypeDef;
/** CRYPTO key width. */
typedef enum
{
typedef enum {
cryptoKey128Bits = 8, /**< Key width is 128 bits*/
cryptoKey256Bits = 16, /**< Key width is 256 bits*/
} CRYPTO_KeyWidth_TypeDef;
@ -861,15 +865,12 @@ __STATIC_INLINE void CRYPTO_KeyBufWrite(CRYPTO_TypeDef *crypto,
CRYPTO_KeyBuf_TypeDef val,
CRYPTO_KeyWidth_TypeDef keyWidth)
{
if (keyWidth == cryptoKey256Bits)
{
if (keyWidth == cryptoKey256Bits) {
/* Set AES-256 mode */
BUS_RegBitWrite(&crypto->CTRL, _CRYPTO_CTRL_AES_SHIFT, _CRYPTO_CTRL_AES_AES256);
/* Load key in KEYBUF register (= DDATA4) */
CRYPTO_DDataWrite(&crypto->DDATA4, (uint32_t *)val);
}
else
{
} else {
/* Set AES-128 mode */
BUS_RegBitWrite(&crypto->CTRL, _CRYPTO_CTRL_AES_SHIFT, _CRYPTO_CTRL_AES_AES128);
CRYPTO_BurstToCrypto(&crypto->KEYBUF, &val[0]);
@ -1342,7 +1343,7 @@ __STATIC_INLINE void AES_CBC128(uint8_t * out,
const uint8_t * iv,
bool encrypt)
{
CRYPTO_AES_CBC128(CRYPTO, out, in, len, key, iv, encrypt);
CRYPTO_AES_CBC128(DEFAULT_CRYPTO, out, in, len, key, iv, encrypt);
}
/***************************************************************************//**
@ -1361,7 +1362,7 @@ __STATIC_INLINE void AES_CBC256(uint8_t * out,
const uint8_t * iv,
bool encrypt)
{
CRYPTO_AES_CBC256(CRYPTO, out, in, len, key, iv, encrypt);
CRYPTO_AES_CBC256(DEFAULT_CRYPTO, out, in, len, key, iv, encrypt);
}
/***************************************************************************//**
@ -1379,7 +1380,7 @@ __STATIC_INLINE void AES_CFB128(uint8_t * out,
const uint8_t * iv,
bool encrypt)
{
CRYPTO_AES_CFB128(CRYPTO, out, in, len, key, iv, encrypt);
CRYPTO_AES_CFB128(DEFAULT_CRYPTO, out, in, len, key, iv, encrypt);
}
/***************************************************************************//**
@ -1397,7 +1398,7 @@ __STATIC_INLINE void AES_CFB256(uint8_t * out,
const uint8_t * iv,
bool encrypt)
{
CRYPTO_AES_CFB256(CRYPTO, out, in, len, key, iv, encrypt);
CRYPTO_AES_CFB256(DEFAULT_CRYPTO, out, in, len, key, iv, encrypt);
}
/***************************************************************************//**
@ -1415,7 +1416,7 @@ __STATIC_INLINE void AES_CTR128(uint8_t * out,
uint8_t * ctr,
CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc)
{
CRYPTO_AES_CTR128(CRYPTO, out, in, len, key, ctr, ctrFunc);
CRYPTO_AES_CTR128(DEFAULT_CRYPTO, out, in, len, key, ctr, ctrFunc);
}
/***************************************************************************//**
@ -1433,7 +1434,7 @@ __STATIC_INLINE void AES_CTR256(uint8_t * out,
uint8_t * ctr,
CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc)
{
CRYPTO_AES_CTR256(CRYPTO, out, in, len, key, ctr, ctrFunc);
CRYPTO_AES_CTR256(DEFAULT_CRYPTO, out, in, len, key, ctr, ctrFunc);
}
/***************************************************************************//**
@ -1460,7 +1461,7 @@ __STATIC_INLINE void AES_CTRUpdate32Bit(uint8_t * ctr)
******************************************************************************/
__STATIC_INLINE void AES_DecryptKey128(uint8_t * out, const uint8_t * in)
{
CRYPTO_AES_DecryptKey128(CRYPTO, out, in);
CRYPTO_AES_DecryptKey128(DEFAULT_CRYPTO, out, in);
}
/***************************************************************************//**
@ -1474,7 +1475,7 @@ __STATIC_INLINE void AES_DecryptKey128(uint8_t * out, const uint8_t * in)
******************************************************************************/
__STATIC_INLINE void AES_DecryptKey256(uint8_t * out, const uint8_t * in)
{
CRYPTO_AES_DecryptKey256(CRYPTO, out, in);
CRYPTO_AES_DecryptKey256(DEFAULT_CRYPTO, out, in);
}
/***************************************************************************//**
@ -1492,7 +1493,7 @@ __STATIC_INLINE void AES_ECB128(uint8_t * out,
const uint8_t * key,
bool encrypt)
{
CRYPTO_AES_ECB128(CRYPTO, out, in, len, key, encrypt);
CRYPTO_AES_ECB128(DEFAULT_CRYPTO, out, in, len, key, encrypt);
}
/***************************************************************************//**
@ -1510,7 +1511,7 @@ __STATIC_INLINE void AES_ECB256(uint8_t * out,
const uint8_t * key,
bool encrypt)
{
CRYPTO_AES_ECB256(CRYPTO, out, in, len, key, encrypt);
CRYPTO_AES_ECB256(DEFAULT_CRYPTO, out, in, len, key, encrypt);
}
/***************************************************************************//**
@ -1527,7 +1528,7 @@ __STATIC_INLINE void AES_OFB128(uint8_t * out,
const uint8_t * key,
const uint8_t * iv)
{
CRYPTO_AES_OFB128(CRYPTO, out, in, len, key, iv);
CRYPTO_AES_OFB128(DEFAULT_CRYPTO, out, in, len, key, iv);
}
/***************************************************************************//**
@ -1544,7 +1545,7 @@ __STATIC_INLINE void AES_OFB256(uint8_t * out,
const uint8_t * key,
const uint8_t * iv)
{
CRYPTO_AES_OFB256(CRYPTO, out, in, len, key, iv);
CRYPTO_AES_OFB256(DEFAULT_CRYPTO, out, in, len, key, iv);
}
#ifdef __cplusplus

89
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_csen.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_csen.h
* @brief Capacitive Sense Module (CSEN) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -83,8 +83,7 @@ extern "C" {
******************************************************************************/
/** Comparator Mode. Selects the operation of the digital comparator. */
typedef enum
{
typedef enum {
/** Comparator is disabled. */
csenCmpModeDisabled = 0,
@ -98,10 +97,8 @@ typedef enum
csenCmpModeEMAWindow = CSEN_CTRL_EMACMPEN,
} CSEN_CmpMode_TypeDef;
/** Converter Select. Determines the converter operational mode. */
typedef enum
{
typedef enum {
/** Successive Approximation (SAR) converter. */
csenConvSelSAR = CSEN_CTRL_CONVSEL_SAR,
@ -115,10 +112,8 @@ typedef enum
csenConvSelDMChop = CSEN_CTRL_CONVSEL_DM | CSEN_CTRL_CHOPEN_ENABLE,
} CSEN_ConvSel_TypeDef;
/** Sample Mode. Determines how inputs are sampled for a conversion. */
typedef enum
{
typedef enum {
/** Convert multiple inputs shorted together and stop. */
csenSampleModeBonded = CSEN_CTRL_CM_SGL | CSEN_CTRL_MCEN_ENABLE,
@ -138,19 +133,15 @@ typedef enum
csenSampleModeContScan = CSEN_CTRL_CM_CONTSCAN,
} CSEN_SampleMode_TypeDef;
/** Start Trigger Select. */
typedef enum
{
typedef enum {
csenTrigSelPRS = _CSEN_CTRL_STM_PRS, /**< PRS system. */
csenTrigSelTimer = _CSEN_CTRL_STM_TIMER, /**< CSEN PC timer. */
csenTrigSelStart = _CSEN_CTRL_STM_START, /**< Start bit. */
} CSEN_TrigSel_TypeDef;
/** Accumulator Mode Select. */
typedef enum
{
typedef enum {
csenAccMode1 = _CSEN_CTRL_ACU_ACC1, /**< Accumulate 1 sample. */
csenAccMode2 = _CSEN_CTRL_ACU_ACC2, /**< Accumulate 2 samples. */
csenAccMode4 = _CSEN_CTRL_ACU_ACC4, /**< Accumulate 4 samples. */
@ -160,31 +151,25 @@ typedef enum
csenAccMode64 = _CSEN_CTRL_ACU_ACC64, /**< Accumulate 64 samples. */
} CSEN_AccMode_TypeDef;
/** Successive Approximation (SAR) Conversion Resolution. */
typedef enum
{
typedef enum {
csenSARRes10 = _CSEN_CTRL_SARCR_CLK10, /**< 10-bit resolution. */
csenSARRes12 = _CSEN_CTRL_SARCR_CLK12, /**< 12-bit resolution. */
csenSARRes14 = _CSEN_CTRL_SARCR_CLK14, /**< 14-bit resolution. */
csenSARRes16 = _CSEN_CTRL_SARCR_CLK16, /**< 16-bit resolution. */
} CSEN_SARRes_TypeDef;
/** Delta Modulator (DM) Conversion Resolution. */
typedef enum
{
typedef enum {
csenDMRes10 = _CSEN_DMCFG_CRMODE_DM10, /**< 10-bit resolution. */
csenDMRes12 = _CSEN_DMCFG_CRMODE_DM12, /**< 12-bit resolution. */
csenDMRes14 = _CSEN_DMCFG_CRMODE_DM14, /**< 14-bit resolution. */
csenDMRes16 = _CSEN_DMCFG_CRMODE_DM16, /**< 16-bit resolution. */
} CSEN_DMRes_TypeDef;
/** Period counter clock pre-scaler. See the reference manual for source clock
* information. */
typedef enum
{
typedef enum {
csenPCPrescaleDiv1 = _CSEN_TIMCTRL_PCPRESC_DIV1, /**< Divide by 1. */
csenPCPrescaleDiv2 = _CSEN_TIMCTRL_PCPRESC_DIV2, /**< Divide by 2. */
csenPCPrescaleDiv4 = _CSEN_TIMCTRL_PCPRESC_DIV4, /**< Divide by 4. */
@ -195,10 +180,8 @@ typedef enum
csenPCPrescaleDiv128 = _CSEN_TIMCTRL_PCPRESC_DIV128, /**< Divide by 128. */
} CSEN_PCPrescale_TypeDef;
/** Exponential Moving Average sample weight. */
typedef enum
{
typedef enum {
csenEMASampleW1 = _CSEN_EMACTRL_EMASAMPLE_W1, /**< Weight 1. */
csenEMASampleW2 = _CSEN_EMACTRL_EMASAMPLE_W2, /**< Weight 2. */
csenEMASampleW4 = _CSEN_EMACTRL_EMASAMPLE_W4, /**< Weight 4. */
@ -208,10 +191,8 @@ typedef enum
csenEMASampleW64 = _CSEN_EMACTRL_EMASAMPLE_W64, /**< Weight 64. */
} CSEN_EMASample_TypeDef;
/** Reset Phase Timing Select (units are microseconds). */
typedef enum
{
typedef enum {
csenResetPhaseSel0 = 0, /**< Reset phase time = 0.75 usec. */
csenResetPhaseSel1 = 1, /**< Reset phase time = 1.00 usec. */
csenResetPhaseSel2 = 2, /**< Reset phase time = 1.20 usec. */
@ -222,10 +203,8 @@ typedef enum
csenResetPhaseSel7 = 7, /**< Reset phase time = 12.0 usec. */
} CSEN_ResetPhaseSel_TypeDef;
/** Drive Strength Select. Scales the output current. */
typedef enum
{
typedef enum {
csenDriveSelFull = 0, /**< Drive strength = fully on. */
csenDriveSel1 = 1, /**< Drive strength = 1/8 full scale. */
csenDriveSel2 = 2, /**< Drive strength = 1/4 full scale. */
@ -236,10 +215,8 @@ typedef enum
csenDriveSel7 = 7, /**< Drive strength = 7/8 full scale. */
} CSEN_DriveSel_TypeDef;
/** Gain Select. See reference manual for information on each setting. */
typedef enum
{
typedef enum {
csenGainSel1X = 0, /**< Gain = 1x. */
csenGainSel2X = 1, /**< Gain = 2x. */
csenGainSel3X = 2, /**< Gain = 3x. */
@ -250,10 +227,8 @@ typedef enum
csenGainSel8X = 7, /**< Gain = 8x. */
} CSEN_GainSel_TypeDef;
/** Peripheral Reflex System signal used to trigger conversion. */
typedef enum
{
typedef enum {
csenPRSSELCh0 = _CSEN_PRSSEL_PRSSEL_PRSCH0, /**< PRS channel 0. */
csenPRSSELCh1 = _CSEN_PRSSEL_PRSSEL_PRSCH1, /**< PRS channel 1. */
csenPRSSELCh2 = _CSEN_PRSSEL_PRSSEL_PRSCH2, /**< PRS channel 2. */
@ -262,16 +237,22 @@ typedef enum
csenPRSSELCh5 = _CSEN_PRSSEL_PRSSEL_PRSCH5, /**< PRS channel 5. */
csenPRSSELCh6 = _CSEN_PRSSEL_PRSSEL_PRSCH6, /**< PRS channel 6. */
csenPRSSELCh7 = _CSEN_PRSSEL_PRSSEL_PRSCH7, /**< PRS channel 7. */
#if defined(_CSEN_PRSSEL_PRSSEL_PRSCH8)
csenPRSSELCh8 = _CSEN_PRSSEL_PRSSEL_PRSCH8, /**< PRS channel 8. */
#endif
#if defined(_CSEN_PRSSEL_PRSSEL_PRSCH9)
csenPRSSELCh9 = _CSEN_PRSSEL_PRSSEL_PRSCH9, /**< PRS channel 9. */
#endif
#if defined(_CSEN_PRSSEL_PRSSEL_PRSCH10)
csenPRSSELCh10 = _CSEN_PRSSEL_PRSSEL_PRSCH10, /**< PRS channel 10. */
#endif
#if defined(_CSEN_PRSSEL_PRSSEL_PRSCH11)
csenPRSSELCh11 = _CSEN_PRSSEL_PRSSEL_PRSCH11, /**< PRS channel 11. */
#endif
} CSEN_PRSSel_TypeDef;
/** APORT channel to CSEN input selection. */
typedef enum
{
typedef enum {
csenInputSelDefault = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT,
csenInputSelAPORT1CH0TO7 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7,
csenInputSelAPORT1CH8TO15 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15,
@ -283,10 +264,8 @@ typedef enum
csenInputSelAPORT3CH24TO31 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31,
} CSEN_InputSel_TypeDef;
/** APORT channel to CSEN single input selection. */
typedef enum
{
typedef enum {
csenSingleSelDefault = _CSEN_SINGLECTRL_SINGLESEL_DEFAULT,
csenSingleSelAPORT1XCH0 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0,
csenSingleSelAPORT1YCH1 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1,
@ -354,14 +333,12 @@ typedef enum
csenSingleSelAPORT3YCH31 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31,
} CSEN_SingleSel_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** CSEN init structure, common for all measurement modes. */
typedef struct
{
typedef struct {
/** Requests system charge pump high accuracy mode. */
bool cpAccuracyHi;
@ -413,10 +390,8 @@ typedef struct
csenInputSelAPORT3CH24TO31, /* input56To63 -> aport3ch24to31 */ \
}
/** Measurement mode init structure. */
typedef struct
{
typedef struct {
/** Selects the conversion sample mode. */
CSEN_SampleMode_TypeDef sampleMode;
@ -522,7 +497,6 @@ typedef struct
csenGainSel8X, /* Use highest converter gain. */ \
}
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
@ -612,7 +586,6 @@ void CSEN_Init(CSEN_TypeDef *csen, const CSEN_Init_TypeDef *init);
void CSEN_InitMode(CSEN_TypeDef *csen, const CSEN_InitMode_TypeDef *init);
void CSEN_Reset(CSEN_TypeDef *csen);
/***************************************************************************//**
* @brief
* Clear one or more pending CSEN interrupts.
@ -629,7 +602,6 @@ __STATIC_INLINE void CSEN_IntClear(CSEN_TypeDef *csen, uint32_t flags)
csen->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more CSEN interrupts.
@ -646,7 +618,6 @@ __STATIC_INLINE void CSEN_IntDisable(CSEN_TypeDef *csen, uint32_t flags)
csen->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more CSEN interrupts.
@ -668,7 +639,6 @@ __STATIC_INLINE void CSEN_IntEnable(CSEN_TypeDef *csen, uint32_t flags)
csen->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending CSEN interrupt flags.
@ -688,7 +658,6 @@ __STATIC_INLINE uint32_t CSEN_IntGet(CSEN_TypeDef *csen)
return csen->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending CSEN interrupt flags.
@ -720,7 +689,6 @@ __STATIC_INLINE uint32_t CSEN_IntGetEnabled(CSEN_TypeDef *csen)
return csen->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending CSEN interrupts from SW.
@ -737,7 +705,6 @@ __STATIC_INLINE void CSEN_IntSet(CSEN_TypeDef *csen, uint32_t flags)
csen->IFS = flags;
}
/***************************************************************************//**
* @brief
* Return CSEN conversion busy status.
@ -753,7 +720,6 @@ __STATIC_INLINE bool CSEN_IsBusy(CSEN_TypeDef *csen)
return (bool)(csen->STATUS & _CSEN_STATUS_CSENBUSY_MASK);
}
/***************************************************************************//**
* @brief
* Start scan sequence and/or single conversion.
@ -766,7 +732,6 @@ __STATIC_INLINE void CSEN_Start(CSEN_TypeDef *csen)
csen->CMD = CSEN_CMD_START;
}
/** @} (end addtogroup CSEN) */
/** @} (end addtogroup emlib) */

39
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dac.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_dac.h
* @brief Digital to Analog Converter (DAC) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -44,7 +44,6 @@
extern "C" {
#endif
/***************************************************************************//**
* @addtogroup emlib
* @{
@ -67,26 +66,22 @@ extern "C" {
******************************************************************************/
/** Conversion mode. */
typedef enum
{
typedef enum {
dacConvModeContinuous = _DAC_CTRL_CONVMODE_CONTINUOUS, /**< Continuous mode. */
dacConvModeSampleHold = _DAC_CTRL_CONVMODE_SAMPLEHOLD, /**< Sample/hold mode. */
dacConvModeSampleOff = _DAC_CTRL_CONVMODE_SAMPLEOFF /**< Sample/shut off mode. */
} DAC_ConvMode_TypeDef;
/** Output mode. */
typedef enum
{
typedef enum {
dacOutputDisable = _DAC_CTRL_OUTMODE_DISABLE, /**< Output to pin and ADC disabled. */
dacOutputPin = _DAC_CTRL_OUTMODE_PIN, /**< Output to pin only. */
dacOutputADC = _DAC_CTRL_OUTMODE_ADC, /**< Output to ADC only */
dacOutputPinADC = _DAC_CTRL_OUTMODE_PINADC /**< Output to pin and ADC. */
} DAC_Output_TypeDef;
/** Peripheral Reflex System signal used to trigger single sample. */
typedef enum
{
typedef enum {
dacPRSSELCh0 = _DAC_CH0CTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */
dacPRSSELCh1 = _DAC_CH0CTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */
dacPRSSELCh2 = _DAC_CH0CTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */
@ -117,33 +112,27 @@ typedef enum
#endif
} DAC_PRSSEL_TypeDef;
/** Reference voltage for DAC. */
typedef enum
{
typedef enum {
dacRef1V25 = _DAC_CTRL_REFSEL_1V25, /**< Internal 1.25V bandgap reference. */
dacRef2V5 = _DAC_CTRL_REFSEL_2V5, /**< Internal 2.5V bandgap reference. */
dacRefVDD = _DAC_CTRL_REFSEL_VDD /**< VDD reference. */
} DAC_Ref_TypeDef;
/** Refresh interval. */
typedef enum
{
typedef enum {
dacRefresh8 = _DAC_CTRL_REFRSEL_8CYCLES, /**< Refresh every 8 prescaled cycles. */
dacRefresh16 = _DAC_CTRL_REFRSEL_16CYCLES, /**< Refresh every 16 prescaled cycles. */
dacRefresh32 = _DAC_CTRL_REFRSEL_32CYCLES, /**< Refresh every 32 prescaled cycles. */
dacRefresh64 = _DAC_CTRL_REFRSEL_64CYCLES /**< Refresh every 64 prescaled cycles. */
} DAC_Refresh_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** DAC init structure, common for both channels. */
typedef struct
{
typedef struct {
/** Refresh interval. Only used if REFREN bit set for a DAC channel. */
DAC_Refresh_TypeDef refresh;
@ -193,10 +182,8 @@ typedef struct
false /* Single ended mode. */ \
}
/** DAC channel init structure. */
typedef struct
{
typedef struct {
/** Enable channel. */
bool enable;
@ -228,7 +215,6 @@ typedef struct
dacPRSSELCh0 /* Select PRS ch0 (if PRS triggering enabled). */ \
}
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
@ -263,7 +249,6 @@ __STATIC_INLINE void DAC_Channel0OutputSet( DAC_TypeDef *dac,
dac->CH0DATA = value;
}
/***************************************************************************//**
* @brief
* Set the output signal of DAC channel 1 to a given value.
@ -285,7 +270,6 @@ __STATIC_INLINE void DAC_Channel1OutputSet( DAC_TypeDef *dac,
dac->CH1DATA = value;
}
/***************************************************************************//**
* @brief
* Clear one or more pending DAC interrupts.
@ -302,7 +286,6 @@ __STATIC_INLINE void DAC_IntClear(DAC_TypeDef *dac, uint32_t flags)
dac->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more DAC interrupts.
@ -319,7 +302,6 @@ __STATIC_INLINE void DAC_IntDisable(DAC_TypeDef *dac, uint32_t flags)
dac->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more DAC interrupts.
@ -341,7 +323,6 @@ __STATIC_INLINE void DAC_IntEnable(DAC_TypeDef *dac, uint32_t flags)
dac->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending DAC interrupt flags.
@ -361,7 +342,6 @@ __STATIC_INLINE uint32_t DAC_IntGet(DAC_TypeDef *dac)
return dac->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending DAC interrupt flags.
@ -393,7 +373,6 @@ __STATIC_INLINE uint32_t DAC_IntGetEnabled(DAC_TypeDef *dac)
return dac->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending DAC interrupts from SW.

6
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dbg.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_dbg.h
* @brief Debug (DBG) API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -30,7 +30,6 @@
*
******************************************************************************/
#ifndef EM_DBG_H
#define EM_DBG_H
@ -76,7 +75,6 @@ __STATIC_INLINE bool DBG_Connected(void)
}
#endif
#if defined(GPIO_ROUTE_SWOPEN) || defined(GPIO_ROUTEPEN_SWVPEN)
void DBG_SWOEnable(unsigned int location);
#endif

58
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dma.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_dma.h
* @brief Direct memory access (DMA) API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -61,27 +61,22 @@ extern "C" {
* Amount source/destination address should be incremented for each data
* transfer.
*/
typedef enum
{
typedef enum {
dmaDataInc1 = _DMA_CTRL_SRC_INC_BYTE, /**< Increment address 1 byte. */
dmaDataInc2 = _DMA_CTRL_SRC_INC_HALFWORD, /**< Increment address 2 bytes. */
dmaDataInc4 = _DMA_CTRL_SRC_INC_WORD, /**< Increment address 4 bytes. */
dmaDataIncNone = _DMA_CTRL_SRC_INC_NONE /**< Do not increment address. */
} DMA_DataInc_TypeDef;
/** Data sizes (in number of bytes) to be read/written by DMA transfer. */
typedef enum
{
typedef enum {
dmaDataSize1 = _DMA_CTRL_SRC_SIZE_BYTE, /**< 1 byte DMA transfer size. */
dmaDataSize2 = _DMA_CTRL_SRC_SIZE_HALFWORD, /**< 2 byte DMA transfer size. */
dmaDataSize4 = _DMA_CTRL_SRC_SIZE_WORD /**< 4 byte DMA transfer size. */
} DMA_DataSize_TypeDef;
/** Type of DMA transfer. */
typedef enum
{
typedef enum {
/** Basic DMA cycle. */
dmaCycleCtrlBasic = _DMA_CTRL_CYCLE_CTRL_BASIC,
/** Auto-request DMA cycle. */
@ -94,10 +89,8 @@ typedef enum
dmaCycleCtrlPerScatterGather = _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER
} DMA_CycleCtrl_TypeDef;
/** Number of transfers before controller does new arbitration. */
typedef enum
{
typedef enum {
dmaArbitrate1 = _DMA_CTRL_R_POWER_1, /**< Arbitrate after 1 DMA transfer. */
dmaArbitrate2 = _DMA_CTRL_R_POWER_2, /**< Arbitrate after 2 DMA transfers. */
dmaArbitrate4 = _DMA_CTRL_R_POWER_4, /**< Arbitrate after 4 DMA transfers. */
@ -111,7 +104,6 @@ typedef enum
dmaArbitrate1024 = _DMA_CTRL_R_POWER_1024 /**< Arbitrate after 1024 DMA transfers. */
} DMA_ArbiterConfig_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
@ -134,7 +126,6 @@ typedef enum
*/
typedef void (*DMA_FuncPtr_TypeDef)(unsigned int channel, bool primary, void *user);
/**
* @brief
* Callback structure that can be used to define DMA complete actions.
@ -145,8 +136,7 @@ typedef void (*DMA_FuncPtr_TypeDef)(unsigned int channel, bool primary, void *us
* handled by one common callback, using the provided 'primary' parameter
* with the callback function.
*/
typedef struct
{
typedef struct {
/**
* Pointer to callback function to invoke when DMA transfer cycle done.
* Notice that this function is invoked in interrupt context, and therefore
@ -165,10 +155,8 @@ typedef struct
uint8_t primary;
} DMA_CB_TypeDef;
/** Configuration structure for a channel. */
typedef struct
{
typedef struct {
/**
* Select if channel priority is in the high or default priority group
* with respect to arbitration. Within a priority group, lower numbered
@ -208,13 +196,11 @@ typedef struct
DMA_CB_TypeDef *cb;
} DMA_CfgChannel_TypeDef;
/**
* Configuration structure for primary or alternate descriptor
* (not used for scatter-gather DMA cycles).
*/
typedef struct
{
typedef struct {
/** Destination increment size for each DMA transfer */
DMA_DataInc_TypeDef dstInc;
@ -242,13 +228,11 @@ typedef struct
uint8_t hprot;
} DMA_CfgDescr_TypeDef;
#if defined(_DMA_LOOP0_MASK) && defined(_DMA_LOOP1_MASK)
/**
* Configuration structure for loop mode
*/
typedef struct
{
typedef struct {
/** Enable repeated loop */
bool enable;
/** Width of transfer, reload value for nMinus1 */
@ -256,13 +240,11 @@ typedef struct
} DMA_CfgLoop_TypeDef;
#endif
#if defined(_DMA_RECT0_MASK)
/**
* Configuration structure for rectangular copy
*/
typedef struct
{
typedef struct {
/** DMA channel destination stride (width of destination image, distance between lines) */
uint16_t dstStride;
/** DMA channel source stride (width of source image, distance between lines) */
@ -272,10 +254,8 @@ typedef struct
} DMA_CfgRect_TypeDef;
#endif
/** Configuration structure for alternate scatter-gather descriptor. */
typedef struct
{
typedef struct {
/** Pointer to location to transfer data from. */
void *src;
@ -320,10 +300,8 @@ typedef struct
bool peripheral;
} DMA_CfgDescrSGAlt_TypeDef;
/** DMA init structure */
typedef struct
{
typedef struct {
/**
* HPROT signal state when accessing the primary/alternate
* descriptors. Normally set to 0 if protection is not an issue.
@ -352,7 +330,6 @@ typedef struct
DMA_DESCRIPTOR_TypeDef *controlBlock;
} DMA_Init_TypeDef;
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
@ -403,8 +380,7 @@ void DMA_CfgRect(unsigned int channel, DMA_CfgRect_TypeDef *cfg);
__STATIC_INLINE void DMA_ResetLoop(unsigned int channel)
{
/* Clean loop copy operation */
switch(channel)
{
switch (channel) {
case 0:
DMA->LOOP0 = _DMA_LOOP0_RESETVALUE;
break;
@ -417,7 +393,6 @@ __STATIC_INLINE void DMA_ResetLoop(unsigned int channel)
}
#endif
#if defined(_DMA_RECT0_MASK)
/***************************************************************************//**
* @brief
@ -464,7 +439,6 @@ __STATIC_INLINE void DMA_IntClear(uint32_t flags)
DMA->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more DMA interrupts.
@ -478,7 +452,6 @@ __STATIC_INLINE void DMA_IntDisable(uint32_t flags)
DMA->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more DMA interrupts.
@ -497,7 +470,6 @@ __STATIC_INLINE void DMA_IntEnable(uint32_t flags)
DMA->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending DMA interrupt flags.
@ -514,7 +486,6 @@ __STATIC_INLINE uint32_t DMA_IntGet(void)
return DMA->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending DMA interrupt flags.
@ -537,7 +508,6 @@ __STATIC_INLINE uint32_t DMA_IntGetEnabled(void)
return DMA->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending DMA interrupts

285
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_ebi.h
* @brief External Bus Iterface (EBI) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -82,28 +82,88 @@ extern "C" {
#define EBI_CS2 (uint32_t)(1 << 3) /**< EBI chip select line 2 */
#define EBI_CS3 (uint32_t)(1 << 4) /**< EBI chip select line 3 */
#if defined(_EBI_ROUTE_MASK) && defined(_EBI_ROUTE_APEN_MASK)
#define EBI_GENERIC_ALB_A0 EBI_ROUTE_ALB_A0
#define EBI_GENERIC_ALB_A8 EBI_ROUTE_ALB_A8
#define EBI_GENERIC_ALB_A16 EBI_ROUTE_ALB_A16
#define EBI_GENERIC_ALB_A24 EBI_ROUTE_ALB_A24
#define EBI_GENERIC_APEN_A0 EBI_ROUTE_APEN_A0
#define EBI_GENERIC_APEN_A5 EBI_ROUTE_APEN_A5
#define EBI_GENERIC_APEN_A6 EBI_ROUTE_APEN_A6
#define EBI_GENERIC_APEN_A7 EBI_ROUTE_APEN_A7
#define EBI_GENERIC_APEN_A8 EBI_ROUTE_APEN_A8
#define EBI_GENERIC_APEN_A9 EBI_ROUTE_APEN_A9
#define EBI_GENERIC_APEN_A10 EBI_ROUTE_APEN_A10
#define EBI_GENERIC_APEN_A11 EBI_ROUTE_APEN_A11
#define EBI_GENERIC_APEN_A12 EBI_ROUTE_APEN_A12
#define EBI_GENERIC_APEN_A13 EBI_ROUTE_APEN_A13
#define EBI_GENERIC_APEN_A14 EBI_ROUTE_APEN_A14
#define EBI_GENERIC_APEN_A15 EBI_ROUTE_APEN_A15
#define EBI_GENERIC_APEN_A16 EBI_ROUTE_APEN_A16
#define EBI_GENERIC_APEN_A17 EBI_ROUTE_APEN_A17
#define EBI_GENERIC_APEN_A18 EBI_ROUTE_APEN_A18
#define EBI_GENERIC_APEN_A19 EBI_ROUTE_APEN_A19
#define EBI_GENERIC_APEN_A20 EBI_ROUTE_APEN_A20
#define EBI_GENERIC_APEN_A21 EBI_ROUTE_APEN_A21
#define EBI_GENERIC_APEN_A22 EBI_ROUTE_APEN_A22
#define EBI_GENERIC_APEN_A23 EBI_ROUTE_APEN_A23
#define EBI_GENERIC_APEN_A24 EBI_ROUTE_APEN_A24
#define EBI_GENERIC_APEN_A25 EBI_ROUTE_APEN_A25
#define EBI_GENERIC_APEN_A26 EBI_ROUTE_APEN_A26
#define EBI_GENERIC_APEN_A27 EBI_ROUTE_APEN_A27
#define EBI_GENERIC_APEN_A28 EBI_ROUTE_APEN_A28
#elif defined(_EBI_ROUTEPEN_MASK)
#define EBI_GENERIC_ALB_A0 EBI_ROUTEPEN_ALB_A0
#define EBI_GENERIC_ALB_A8 EBI_ROUTEPEN_ALB_A8
#define EBI_GENERIC_ALB_A16 EBI_ROUTEPEN_ALB_A16
#define EBI_GENERIC_ALB_A24 EBI_ROUTEPEN_ALB_A24
#define EBI_GENERIC_APEN_A0 EBI_ROUTEPEN_APEN_A0
#define EBI_GENERIC_APEN_A5 EBI_ROUTEPEN_APEN_A5
#define EBI_GENERIC_APEN_A6 EBI_ROUTEPEN_APEN_A6
#define EBI_GENERIC_APEN_A7 EBI_ROUTEPEN_APEN_A7
#define EBI_GENERIC_APEN_A8 EBI_ROUTEPEN_APEN_A8
#define EBI_GENERIC_APEN_A9 EBI_ROUTEPEN_APEN_A9
#define EBI_GENERIC_APEN_A10 EBI_ROUTEPEN_APEN_A10
#define EBI_GENERIC_APEN_A11 EBI_ROUTEPEN_APEN_A11
#define EBI_GENERIC_APEN_A12 EBI_ROUTEPEN_APEN_A12
#define EBI_GENERIC_APEN_A13 EBI_ROUTEPEN_APEN_A13
#define EBI_GENERIC_APEN_A14 EBI_ROUTEPEN_APEN_A14
#define EBI_GENERIC_APEN_A15 EBI_ROUTEPEN_APEN_A15
#define EBI_GENERIC_APEN_A16 EBI_ROUTEPEN_APEN_A16
#define EBI_GENERIC_APEN_A17 EBI_ROUTEPEN_APEN_A17
#define EBI_GENERIC_APEN_A18 EBI_ROUTEPEN_APEN_A18
#define EBI_GENERIC_APEN_A19 EBI_ROUTEPEN_APEN_A19
#define EBI_GENERIC_APEN_A20 EBI_ROUTEPEN_APEN_A20
#define EBI_GENERIC_APEN_A21 EBI_ROUTEPEN_APEN_A21
#define EBI_GENERIC_APEN_A22 EBI_ROUTEPEN_APEN_A22
#define EBI_GENERIC_APEN_A23 EBI_ROUTEPEN_APEN_A23
#define EBI_GENERIC_APEN_A24 EBI_ROUTEPEN_APEN_A24
#define EBI_GENERIC_APEN_A25 EBI_ROUTEPEN_APEN_A25
#define EBI_GENERIC_APEN_A26 EBI_ROUTEPEN_APEN_A26
#define EBI_GENERIC_APEN_A27 EBI_ROUTEPEN_APEN_A27
#define EBI_GENERIC_APEN_A28 EBI_ROUTEPEN_APEN_A28
#endif
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
/** EBI Mode of operation */
typedef enum
{
typedef enum {
/** 8 data bits, 8 address bits */
ebiModeD8A8 = EBI_CTRL_MODE_D8A8,
/** 16 data bits, 16 address bits, using address latch enable */
ebiModeD16A16ALE = EBI_CTRL_MODE_D16A16ALE,
/** 8 data bits, 24 address bits, using address latch enable */
ebiModeD8A24ALE = EBI_CTRL_MODE_D8A24ALE,
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if defined(EBI_CTRL_MODE_D16)
/** Mode D16 */
ebiModeD16 = EBI_CTRL_MODE_D16,
#endif
} EBI_Mode_TypeDef;
/** EBI Polarity configuration */
typedef enum
{
typedef enum {
/** Active Low */
ebiActiveLow = 0,
/** Active High */
@ -111,8 +171,7 @@ typedef enum
} EBI_Polarity_TypeDef;
/** EBI Pin Line types */
typedef enum
{
typedef enum {
/** Address Ready line */
ebiLineARDY,
/** Address Latch Enable line */
@ -123,11 +182,11 @@ typedef enum
ebiLineRE,
/** Chip Select line */
ebiLineCS,
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if defined(_EBI_POLARITY_BLPOL_MASK)
/** BL line */
ebiLineBL,
#endif
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if defined(_EBI_TFTPOLARITY_MASK)
/** TFT VSYNC line */
ebiLineTFTVSync,
/** TFT HSYNC line */
@ -141,75 +200,75 @@ typedef enum
#endif
} EBI_Line_TypeDef;
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if !defined(_EFM32_GECKO_FAMILY)
/** Address Pin Enable, lower limit - lower range of pins to enable */
typedef enum
{
typedef enum {
/** Adress lines EBI_A[0] and upwards are enabled by APEN */
ebiALowA0 = EBI_ROUTE_ALB_A0,
ebiALowA0 = EBI_GENERIC_ALB_A0,
/** Adress lines EBI_A[8] and upwards are enabled by APEN */
ebiALowA8 = EBI_ROUTE_ALB_A8,
ebiALowA8 = EBI_GENERIC_ALB_A8,
/** Adress lines EBI_A[16] and upwards are enabled by APEN */
ebiALowA16 = EBI_ROUTE_ALB_A16,
ebiALowA16 = EBI_GENERIC_ALB_A16,
/** Adress lines EBI_A[24] and upwards are enabled by APEN */
ebiALowA24 = EBI_ROUTE_ALB_A24,
ebiALowA24 = EBI_GENERIC_ALB_A24,
} EBI_ALow_TypeDef;
/** Adress Pin Enable, high limit - higher limit of pins to enable */
typedef enum
{
typedef enum {
/** All EBI_A pins are disabled */
ebiAHighA0 = EBI_ROUTE_APEN_A0,
ebiAHighA0 = EBI_GENERIC_APEN_A0,
/** All EBI_A[4:ALow] are enabled */
ebiAHighA5 = EBI_ROUTE_APEN_A5,
ebiAHighA5 = EBI_GENERIC_APEN_A5,
/** All EBI_A[5:ALow] are enabled */
ebiAHighA6 = EBI_ROUTE_APEN_A6,
ebiAHighA6 = EBI_GENERIC_APEN_A6,
/** All EBI_A[6:ALow] are enabled */
ebiAHighA7 = EBI_ROUTE_APEN_A7,
ebiAHighA7 = EBI_GENERIC_APEN_A7,
/** All EBI_A[7:ALow] are enabled */
ebiAHighA8 = EBI_ROUTE_APEN_A8,
ebiAHighA8 = EBI_GENERIC_APEN_A8,
/** All EBI_A[8:ALow] are enabled */
ebiAHighA9 = EBI_ROUTE_APEN_A9,
ebiAHighA9 = EBI_GENERIC_APEN_A9,
/** All EBI_A[9:ALow] are enabled */
ebiAHighA10 = EBI_ROUTE_APEN_A10,
ebiAHighA10 = EBI_GENERIC_APEN_A10,
/** All EBI_A[10:ALow] are enabled */
ebiAHighA11 = EBI_ROUTE_APEN_A11,
ebiAHighA11 = EBI_GENERIC_APEN_A11,
/** All EBI_A[11:ALow] are enabled */
ebiAHighA12 = EBI_ROUTE_APEN_A12,
ebiAHighA12 = EBI_GENERIC_APEN_A12,
/** All EBI_A[12:ALow] are enabled */
ebiAHighA13 = EBI_ROUTE_APEN_A13,
ebiAHighA13 = EBI_GENERIC_APEN_A13,
/** All EBI_A[13:ALow] are enabled */
ebiAHighA14 = EBI_ROUTE_APEN_A14,
ebiAHighA14 = EBI_GENERIC_APEN_A14,
/** All EBI_A[14:ALow] are enabled */
ebiAHighA15 = EBI_ROUTE_APEN_A15,
ebiAHighA15 = EBI_GENERIC_APEN_A15,
/** All EBI_A[15:ALow] are enabled */
ebiAHighA16 = EBI_ROUTE_APEN_A16,
ebiAHighA16 = EBI_GENERIC_APEN_A16,
/** All EBI_A[16:ALow] are enabled */
ebiAHighA17 = EBI_ROUTE_APEN_A17,
ebiAHighA17 = EBI_GENERIC_APEN_A17,
/** All EBI_A[17:ALow] are enabled */
ebiAHighA18 = EBI_ROUTE_APEN_A18,
ebiAHighA18 = EBI_GENERIC_APEN_A18,
/** All EBI_A[18:ALow] are enabled */
ebiAHighA19 = EBI_ROUTE_APEN_A19,
ebiAHighA19 = EBI_GENERIC_APEN_A19,
/** All EBI_A[19:ALow] are enabled */
ebiAHighA20 = EBI_ROUTE_APEN_A20,
ebiAHighA20 = EBI_GENERIC_APEN_A20,
/** All EBI_A[20:ALow] are enabled */
ebiAHighA21 = EBI_ROUTE_APEN_A21,
ebiAHighA21 = EBI_GENERIC_APEN_A21,
/** All EBI_A[21:ALow] are enabled */
ebiAHighA22 = EBI_ROUTE_APEN_A22,
ebiAHighA22 = EBI_GENERIC_APEN_A22,
/** All EBI_A[22:ALow] are enabled */
ebiAHighA23 = EBI_ROUTE_APEN_A23,
ebiAHighA23 = EBI_GENERIC_APEN_A23,
/** All EBI_A[23:ALow] are enabled */
ebiAHighA24 = EBI_ROUTE_APEN_A24,
ebiAHighA24 = EBI_GENERIC_APEN_A24,
/** All EBI_A[24:ALow] are enabled */
ebiAHighA25 = EBI_ROUTE_APEN_A25,
ebiAHighA25 = EBI_GENERIC_APEN_A25,
/** All EBI_A[25:ALow] are enabled */
ebiAHighA26 = EBI_ROUTE_APEN_A26,
ebiAHighA26 = EBI_GENERIC_APEN_A26,
/** All EBI_A[26:ALow] are enabled */
ebiAHighA27 = EBI_ROUTE_APEN_A27,
ebiAHighA27 = EBI_GENERIC_APEN_A27,
/** All EBI_A[27:ALow] are enabled */
ebiAHighA28 = EBI_ROUTE_APEN_A28,
ebiAHighA28 = EBI_GENERIC_APEN_A28,
} EBI_AHigh_TypeDef;
#endif
#if defined(_EBI_ROUTE_LOCATION_MASK)
/** EBI I/O Alternate Pin Location */
typedef enum {
/** EBI PIN I/O Location 0 */
@ -221,11 +280,11 @@ typedef enum {
} EBI_Location_TypeDef;
#endif
#if defined(_EBI_TFTCTRL_MASK)
/* TFT support */
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
/** EBI TFT Graphics Bank Select */
typedef enum
{
typedef enum {
/** Memory BANK0 contains frame buffer */
ebiTFTBank0 = EBI_TFTCTRL_BANKSEL_BANK0,
/** Memory BANK1 contains frame buffer */
@ -237,8 +296,7 @@ typedef enum
} EBI_TFTBank_TypeDef;
/** Masking and Alpha blending source color*/
typedef enum
{
typedef enum {
/** Use memory as source color for masking/alpha blending */
ebiTFTColorSrcMem = EBI_TFTCTRL_COLOR1SRC_MEM,
/** Use PIXEL1 register as source color for masking/alpha blending */
@ -246,8 +304,7 @@ typedef enum
} EBI_TFTColorSrc_TypeDef;
/** Bus Data Interleave Mode */
typedef enum
{
typedef enum {
/** Unlimited interleaved accesses per EBI_DCLK period. Can cause jitter */
ebiTFTInterleaveUnlimited = EBI_TFTCTRL_INTERLEAVE_UNLIMITED,
/** Allow 1 interleaved access per EBI_DCLK period */
@ -257,8 +314,7 @@ typedef enum
} EBI_TFTInterleave_TypeDef;
/** Control frame base pointer copy */
typedef enum
{
typedef enum {
/** Trigger update of frame buffer pointer on vertical sync */
ebiTFTFrameBufTriggerVSync = EBI_TFTCTRL_FBCTRIG_VSYNC,
/** Trigger update of frame buffer pointer on horizontal sync */
@ -266,8 +322,7 @@ typedef enum
} EBI_TFTFrameBufTrigger_TypeDef;
/** Control of mask and alpha blending mode */
typedef enum
{
typedef enum {
/** Masking and blending are disabled */
ebiTFTMBDisabled = EBI_TFTCTRL_MASKBLEND_DISABLED,
/** Internal masking */
@ -275,18 +330,30 @@ typedef enum
/** Internal alpha blending */
ebiTFTMBIAlpha = EBI_TFTCTRL_MASKBLEND_IALPHA,
/** Internal masking and alpha blending are enabled */
#if defined(EBI_TFTCTRL_MASKBLEND_IMASKIALPHA)
ebiTFTMBIMaskAlpha = EBI_TFTCTRL_MASKBLEND_IMASKIALPHA,
#else
ebiTFTMBIMaskAlpha = EBI_TFTCTRL_MASKBLEND_IMASKALPHA,
#endif
#if defined(EBI_TFTCTRL_MASKBLEND_EMASK)
/** External masking */
ebiTFTMBEMask = EBI_TFTCTRL_MASKBLEND_EMASK,
/** External alpha blending */
ebiTFTMBEAlpha = EBI_TFTCTRL_MASKBLEND_EALPHA,
/** External masking and alpha blending */
ebiTFTMBEMaskAlpha = EBI_TFTCTRL_MASKBLEND_EMASKEALPHA,
#else
/** External masking */
ebiTFTMBEMask = EBI_TFTCTRL_MASKBLEND_EFBMASK,
/** External alpha blending */
ebiTFTMBEAlpha = EBI_TFTCTRL_MASKBLEND_EFBALPHA,
/** External masking and alpha blending */
ebiTFTMBEMaskAlpha = EBI_TFTCTRL_MASKBLEND_EFBMASKALPHA,
#endif
} EBI_TFTMaskBlend_TypeDef;
/** TFT Direct Drive mode */
typedef enum
{
typedef enum {
/** Disabled */
ebiTFTDDModeDisabled = EBI_TFTCTRL_DD_DISABLED,
/** Direct Drive from internal memory */
@ -296,23 +363,21 @@ typedef enum
} EBI_TFTDDMode_TypeDef;
/** TFT Data Increment Width */
typedef enum
{
typedef enum {
/** Pixel increments are 1 byte at a time */
ebiTFTWidthByte = EBI_TFTCTRL_WIDTH_BYTE,
/** Pixel increments are 2 bytes (half word) */
ebiTFTWidthHalfWord = EBI_TFTCTRL_WIDTH_HALFWORD,
} EBI_TFTWidth_TypeDef;
#endif
#endif // _EBI_TFTCTRL_MASK
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** EBI Initialization structure */
typedef struct
{
typedef struct {
/** EBI operation mode, data and address limits */
EBI_Mode_TypeDef mode;
/** Address Ready pin polarity, active high or low */
@ -325,8 +390,8 @@ typedef struct
EBI_Polarity_TypeDef rePolarity;
/** Chip Select pin polarity, active high or low */
EBI_Polarity_TypeDef csPolarity;
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
/** Byte Lane pin polaritym, active high or low */
#if !defined(_EFM32_GECKO_FAMILY)
/** Byte Lane pin polarity, active high or low */
EBI_Polarity_TypeDef blPolarity;
/** Flag to enable or disable Byte Lane support */
bool blEnable;
@ -345,7 +410,7 @@ typedef struct
int addrSetupCycles;
/** Number of cycles address is driven onto the ADDRDAT bus before ALE is asserted */
int addrHoldCycles;
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if !defined(_EFM32_GECKO_FAMILY)
/** Enable or disables half cycle duration of the ALE strobe in the last address setup cycle */
bool addrHalfALE;
#endif
@ -355,7 +420,7 @@ typedef struct
int readStrobeCycles;
/** Number of cycles CSn is held active after REn is deasserted */
int readHoldCycles;
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if !defined(_EFM32_GECKO_FAMILY)
/** Enable or disable page mode reads */
bool readPageMode;
/** Enables or disable prefetching from sequential addresses */
@ -369,7 +434,7 @@ typedef struct
int writeStrobeCycles;
/** Number of cycles CSn is held active after WEn is deasserted */
int writeHoldCycles;
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if !defined(_EFM32_GECKO_FAMILY)
/** Enable or disable the write buffer */
bool writeBufferDisable;
/** Enables or disables half cycle duration of the WEn signal in the last strobe cycle */
@ -378,6 +443,8 @@ typedef struct
EBI_ALow_TypeDef aLow;
/** High address pin limit to enable */
EBI_AHigh_TypeDef aHigh;
#endif
#if defined(_EBI_ROUTE_LOCATION_MASK)
/** Pin Location */
EBI_Location_TypeDef location;
#endif
@ -386,7 +453,41 @@ typedef struct
} EBI_Init_TypeDef;
/** Default config for EBI init structures */
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if defined(_SILICON_LABS_32B_SERIES_1)
#define EBI_INIT_DEFAULT \
{ \
ebiModeD8A8, /* 8 bit address, 8 bit data */ \
ebiActiveLow, /* ARDY polarity */ \
ebiActiveLow, /* ALE polarity */ \
ebiActiveLow, /* WE polarity */ \
ebiActiveLow, /* RE polarity */ \
ebiActiveLow, /* CS polarity */ \
ebiActiveLow, /* BL polarity */ \
false, /* enable BL */ \
false, /* enable NOIDLE */ \
false, /* enable ARDY */ \
false, /* don't disable ARDY timeout */ \
EBI_BANK0, /* enable bank 0 */ \
EBI_CS0, /* enable chip select 0 */ \
0, /* addr setup cycles */ \
1, /* addr hold cycles */ \
false, /* do not enable half cycle ALE strobe */ \
0, /* read setup cycles */ \
0, /* read strobe cycles */ \
0, /* read hold cycles */ \
false, /* disable page mode */ \
false, /* disable prefetch */ \
false, /* do not enable half cycle REn strobe */ \
0, /* write setup cycles */ \
0, /* write strobe cycles */ \
1, /* write hold cycles */ \
false, /* do not disable the write buffer */ \
false, /* do not enable halc cycle WEn strobe */ \
ebiALowA0, /* ALB - Low bound, address lines */ \
ebiAHighA0, /* APEN - High bound, address lines */ \
true, /* enable EBI */ \
}
#elif !defined(_EFM32_GECKO_FAMILY)
#define EBI_INIT_DEFAULT \
{ \
ebiModeD8A8, /* 8 bit address, 8 bit data */ \
@ -446,11 +547,10 @@ typedef struct
}
#endif
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if defined(_EBI_TFTCTRL_MASK)
/** TFT Initialization structure */
typedef struct
{
typedef struct {
/** External memory bank for driving display */
EBI_TFTBank_TypeDef bank;
/** Width */
@ -535,8 +635,8 @@ typedef struct
1, /* DCLK Setup cycles */ \
1, /* DCLK Hold cycles */ \
}
#endif
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
@ -546,7 +646,7 @@ void EBI_Disable(void);
uint32_t EBI_BankAddress(uint32_t bank);
void EBI_BankEnable(uint32_t banks, bool enable);
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if defined(_EBI_TFTCTRL_MASK)
void EBI_TFTInit(const EBI_TFTInit_TypeDef *ebiTFTInit);
void EBI_TFTSizeSet(uint32_t horizontal, uint32_t vertical);
void EBI_TFTHPorchSet(int front, int back, int pulseWidth);
@ -554,7 +654,7 @@ void EBI_TFTVPorchSet(int front, int back, int pulseWidth);
void EBI_TFTTimingSet(int dclkPeriod, int start, int setup, int hold);
#endif
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#if !defined(_EFM32_GECKO_FAMILY)
/* This functionality is only available on devices with independent timing support */
void EBI_BankReadTimingSet(uint32_t bank, int setupCycles, int strobeCycles, int holdCycles);
void EBI_BankReadTimingConfig(uint32_t bank, bool pageMode, bool prefetch, bool halfRE);
@ -568,7 +668,9 @@ void EBI_BankAddressTimingConfig(uint32_t bank, bool halfALE);
void EBI_BankPolaritySet(uint32_t bank, EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity);
void EBI_BankByteLaneEnable(uint32_t bank, bool enable);
void EBI_AltMapEnable(bool enable);
#endif
#if defined(_EBI_TFTCTRL_MASK)
/***************************************************************************//**
* @brief
* Enable or disable TFT Direct Drive
@ -581,7 +683,6 @@ __STATIC_INLINE void EBI_TFTEnable(EBI_TFTDDMode_TypeDef mode)
EBI->TFTCTRL = (EBI->TFTCTRL & ~(_EBI_TFTCTRL_DD_MASK)) | (uint32_t) mode;
}
/***************************************************************************//**
* @brief
* Configure frame buffer pointer
@ -594,7 +695,6 @@ __STATIC_INLINE void EBI_TFTFrameBaseSet(uint32_t address)
EBI->TFTFRAMEBASE = (uint32_t) address;
}
/***************************************************************************//**
* @brief Set TFT Pixel Color 0 or 1
*
@ -607,17 +707,14 @@ __STATIC_INLINE void EBI_TFTPixelSet(int pixel, uint32_t color)
{
EFM_ASSERT(pixel == 0 || pixel == 1);
if (pixel == 0)
{
if (pixel == 0) {
EBI->TFTPIXEL0 = color;
}
if (pixel == 1)
{
if (pixel == 1) {
EBI->TFTPIXEL1 = color;
}
}
/***************************************************************************//**
* @brief Masking and Blending Mode Set
*
@ -629,7 +726,6 @@ __STATIC_INLINE void EBI_TFTMaskBlendMode(EBI_TFTMaskBlend_TypeDef maskBlend)
EBI->TFTCTRL = (EBI->TFTCTRL & (~_EBI_TFTCTRL_MASKBLEND_MASK)) | maskBlend;
}
/***************************************************************************//**
* @brief Set TFT Alpha Blending Factor
*
@ -641,7 +737,6 @@ __STATIC_INLINE void EBI_TFTAlphaBlendSet(uint8_t alpha)
EBI->TFTALPHA = alpha;
}
/***************************************************************************//**
* @brief Set TFT mask value
* Data accesses that matches this value are suppressed
@ -652,7 +747,6 @@ __STATIC_INLINE void EBI_TFTMaskSet(uint32_t mask)
EBI->TFTMASK = mask;
}
/***************************************************************************//**
* @brief Get current vertical position counter
* @return
@ -663,7 +757,6 @@ __STATIC_INLINE uint32_t EBI_TFTVCount(void)
return((EBI->TFTSTATUS & _EBI_TFTSTATUS_VCNT_MASK) >> _EBI_TFTSTATUS_VCNT_SHIFT);
}
/***************************************************************************//**
* @brief Get current horizontal position counter
* @return
@ -674,7 +767,6 @@ __STATIC_INLINE uint32_t EBI_TFTHCount(void)
return((EBI->TFTSTATUS & _EBI_TFTSTATUS_HCNT_MASK) >> _EBI_TFTSTATUS_HCNT_SHIFT);
}
/***************************************************************************//**
* @brief Set Frame Buffer Trigger
*
@ -690,7 +782,6 @@ __STATIC_INLINE void EBI_TFTFBTriggerSet(EBI_TFTFrameBufTrigger_TypeDef sync)
EBI->TFTCTRL = ((EBI->TFTCTRL & ~_EBI_TFTCTRL_FBCTRIG_MASK) | sync);
}
/***************************************************************************//**
* @brief Set horizontal TFT stride value in number of bytes
*
@ -702,11 +793,12 @@ __STATIC_INLINE void EBI_TFTHStrideSet(uint32_t nbytes)
{
EFM_ASSERT(nbytes < 0x1000);
EBI->TFTSTRIDE = (EBI->TFTSTRIDE & ~(_EBI_TFTSTRIDE_HSTRIDE_MASK))|
(nbytes<<_EBI_TFTSTRIDE_HSTRIDE_SHIFT);
EBI->TFTSTRIDE = (EBI->TFTSTRIDE & ~(_EBI_TFTSTRIDE_HSTRIDE_MASK))
| (nbytes << _EBI_TFTSTRIDE_HSTRIDE_SHIFT);
}
#endif // _EBI_TFTCTRL_MASK
#if defined(_EBI_IF_MASK)
/***************************************************************************//**
* @brief
* Clear one or more pending EBI interrupts.
@ -719,7 +811,6 @@ __STATIC_INLINE void EBI_IntClear(uint32_t flags)
EBI->IFC = flags;
}
/***************************************************************************//**
* @brief
* Set one or more pending EBI interrupts.
@ -733,7 +824,6 @@ __STATIC_INLINE void EBI_IntSet(uint32_t flags)
EBI->IFS = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more EBI interrupts.
@ -747,7 +837,6 @@ __STATIC_INLINE void EBI_IntDisable(uint32_t flags)
EBI->IEN &= ~(flags);
}
/***************************************************************************//**
* @brief
* Enable one or more EBI interrupts.
@ -761,7 +850,6 @@ __STATIC_INLINE void EBI_IntEnable(uint32_t flags)
EBI->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending EBI interrupt flags.
@ -778,7 +866,6 @@ __STATIC_INLINE uint32_t EBI_IntGet(void)
return EBI->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending EBI interrupt flags.
@ -800,8 +887,9 @@ __STATIC_INLINE uint32_t EBI_IntGetEnabled(void)
ien = EBI->IEN;
return EBI->IF & ien;
}
#endif // _EBI_IF_MASK
#if defined(_EBI_CMD_MASK)
/***************************************************************************//**
* @brief
* Start ECC generator on NAND flash transfers.
@ -811,7 +899,6 @@ __STATIC_INLINE void EBI_StartNandEccGen(void)
EBI->CMD = EBI_CMD_ECCSTART | EBI_CMD_ECCCLEAR;
}
/***************************************************************************//**
* @brief
* Stop NAND flash ECC generator and return generated ECC.
@ -824,7 +911,7 @@ __STATIC_INLINE uint32_t EBI_StopNandEccGen( void )
EBI->CMD = EBI_CMD_ECCSTOP;
return EBI->ECCPARITY;
}
#endif
#endif // _EBI_CMD_MASK
void EBI_ChipSelectEnable(uint32_t banks, bool enable);
void EBI_ReadTimingSet(int setupCycles, int strobeCycles, int holdCycles);

205
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_emu.h
* @brief Energy management unit (EMU) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -59,8 +59,7 @@ extern "C" {
#if defined(_EMU_EM4CONF_OSC_MASK)
/** EM4 duty oscillator */
typedef enum
{
typedef enum {
/** Select ULFRCO as duty oscillator in EM4 */
emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO,
/** Select LFXO as duty oscillator in EM4 */
@ -72,8 +71,7 @@ typedef enum
#if defined(_EMU_BUCTRL_PROBE_MASK)
/** Backup Power Voltage Probe types */
typedef enum
{
typedef enum {
/** Disable voltage probe */
emuProbe_Disable = EMU_BUCTRL_PROBE_DISABLE,
/** Connect probe to VDD_DREG */
@ -87,8 +85,7 @@ typedef enum
#if defined(_EMU_PWRCONF_PWRRES_MASK)
/** Backup Power Domain resistor selection */
typedef enum
{
typedef enum {
/** Main power and backup power connected with RES0 series resistance */
emuRes_Res0 = EMU_PWRCONF_PWRRES_RES0,
/** Main power and backup power connected with RES1 series resistance */
@ -100,10 +97,9 @@ typedef enum
} EMU_Resistor_TypeDef;
#endif
#if defined( BU_PRESENT )
#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0)
/** Backup Power Domain power connection */
typedef enum
{
typedef enum {
/** No connection between main and backup power */
emuPower_None = EMU_BUINACT_PWRCON_NONE,
/** Main power and backup power connected through diode,
@ -118,8 +114,7 @@ typedef enum
#endif
/** BOD threshold setting selector, active or inactive mode */
typedef enum
{
typedef enum {
/** Configure BOD threshold for active mode */
emuBODMode_Active,
/** Configure BOD threshold for inactive mode */
@ -128,8 +123,7 @@ typedef enum
#if defined(_EMU_EM4CTRL_EM4STATE_MASK)
/** EM4 modes */
typedef enum
{
typedef enum {
/** EM4 Hibernate */
emuEM4Hibernate = EMU_EM4CTRL_EM4STATE_EM4H,
/** EM4 Shutoff */
@ -137,32 +131,27 @@ typedef enum
} EMU_EM4State_TypeDef;
#endif
#if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK)
typedef enum
{
typedef enum {
/** No Retention: Pads enter reset state when entering EM4 */
emuPinRetentionDisable = EMU_EM4CTRL_EM4IORETMODE_DISABLE,
/** Retention through EM4: Pads enter reset state when exiting EM4 */
emuPinRetentionEm4Exit = EMU_EM4CTRL_EM4IORETMODE_EM4EXIT,
/** Retention through EM4 and wakeup: call EMU_UnlatchPinRetention() to
/** Retention through EM4 and wakeup: call @ref EMU_UnlatchPinRetention() to
release pins from retention after EM4 wakeup */
emuPinRetentionLatch = EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH,
} EMU_EM4PinRetention_TypeDef;
#endif
/** Power configurations. DCDC-to-DVDD is currently the only supported mode. */
typedef enum
{
typedef enum {
/** DCDC is connected to DVDD */
emuPowerConfig_DcdcToDvdd,
} EMU_PowerConfig_TypeDef;
#if defined(_EMU_DCDCCTRL_MASK)
/** DCDC operating modes */
typedef enum
{
typedef enum {
/** DCDC regulator bypass */
emuDcdcMode_Bypass = EMU_DCDCCTRL_DCDCMODE_BYPASS,
/** DCDC low-noise mode */
@ -176,8 +165,7 @@ typedef enum
#if defined(_EMU_DCDCCTRL_MASK)
/** DCDC conduction modes */
typedef enum
{
typedef enum {
/** DCDC Low-Noise Continuous Conduction Mode (CCM). EFR32 interference minimization
features are available in this mode. */
emuDcdcConductionMode_ContinuousLN,
@ -189,8 +177,7 @@ typedef enum
#if defined(_EMU_PWRCTRL_MASK)
/** DCDC to DVDD mode analog peripheral power supply select */
typedef enum
{
typedef enum {
/** Select AVDD as analog power supply. Typically lower noise, but less energy efficient. */
emuDcdcAnaPeripheralPower_AVDD = EMU_PWRCTRL_ANASW_AVDD,
/** Select DCDC (DVDD) as analog power supply. Typically more energy efficient, but more noise. */
@ -209,11 +196,9 @@ typedef int16_t EMU_DcdcLnReverseCurrentControl_TypeDef;
#define emuDcdcLnFastTransient 160
#endif
#if defined(_EMU_DCDCCTRL_MASK)
/** DCDC Low-noise RCO band select */
typedef enum
{
typedef enum {
/** Set RCO to 3MHz */
emuDcdcLnRcoBand_3MHz = 0,
/** Set RCO to 4MHz */
@ -245,11 +230,9 @@ typedef enum
/** @endcond */
#endif
#if defined(_EMU_DCDCCTRL_MASK)
/** DCDC Low Noise Compensator Control register. */
typedef enum
{
typedef enum {
/** DCDC capacitor is 1uF. */
emuDcdcLnCompCtrl_1u0F,
/** DCDC capacitor is 4.7uF. */
@ -257,22 +240,25 @@ typedef enum
} EMU_DcdcLnCompCtrl_TypeDef;
#endif
#if defined(EMU_STATUS_VMONRDY)
/** VMON channels */
typedef enum
{
typedef enum {
emuVmonChannel_AVDD,
emuVmonChannel_ALTAVDD,
emuVmonChannel_DVDD,
emuVmonChannel_IOVDD0
emuVmonChannel_IOVDD0,
#if defined(_EMU_VMONIO1CTRL_EN_MASK)
emuVmonChannel_IOVDD1,
#endif
#if defined(_EMU_VMONBUVDDCTRL_EN_MASK)
emuVmonChannel_BUVDD,
#endif
} EMU_VmonChannel_TypeDef;
#endif /* EMU_STATUS_VMONRDY */
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
/** Bias mode configurations */
typedef enum
{
typedef enum {
emuBiasMode_1KHz,
emuBiasMode_4KHz,
emuBiasMode_Continuous
@ -281,8 +267,7 @@ typedef enum
#if defined(_EMU_CMD_EM01VSCALE0_MASK)
/** Supported EM0/1 Voltage Scaling Levels */
typedef enum
{
typedef enum {
/** High-performance voltage level. HF clock can be set to any frequency. */
emuVScaleEM01_HighPerformance = _EMU_STATUS_VSCALE_VSCALE2,
/** Low-power optimized voltage level. The HF clock must be limited
@ -296,12 +281,11 @@ typedef enum
#if defined(_EMU_CTRL_EM23VSCALE_MASK)
/** Supported EM2/3 Voltage Scaling Levels */
typedef enum
{
typedef enum {
/** Fast-wakeup voltage level. */
emuVScaleEM23_FastWakeup = _EMU_CTRL_EM23VSCALE_VSCALE2,
/** Low-power optimized voltage level. Using this voltage level in EM2 and 3
adds 20-25us to wakeup time if the EM0 and 1 voltage must be scaled
adds approximately 30us to wakeup time if the EM0 and 1 voltage must be scaled
up to @ref emuVScaleEM01_HighPerformance on EM2 or 3 exit. */
emuVScaleEM23_LowPower = _EMU_CTRL_EM23VSCALE_VSCALE0,
} EMU_VScaleEM23_TypeDef;
@ -309,12 +293,11 @@ typedef enum
#if defined(_EMU_CTRL_EM4HVSCALE_MASK)
/** Supported EM4H Voltage Scaling Levels */
typedef enum
{
typedef enum {
/** Fast-wakeup voltage level. */
emuVScaleEM4H_FastWakeup = _EMU_CTRL_EM4HVSCALE_VSCALE2,
/** Low-power optimized voltage level. Using this voltage level in EM4H
adds 20-25us to wakeup time if the EM0 and 1 voltage must be scaled
adds approximately 30us to wakeup time if the EM0 and 1 voltage must be scaled
up to @ref emuVScaleEM01_HighPerformance on EM4H exit. */
emuVScaleEM4H_LowPower = _EMU_CTRL_EM4HVSCALE_VSCALE0,
} EMU_VScaleEM4H_TypeDef;
@ -322,16 +305,52 @@ typedef enum
#if defined(_EMU_EM23PERNORETAINCTRL_MASK)
/** Peripheral EM2 and 3 retention control */
typedef enum
{
typedef enum {
#if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK)
emuPeripheralRetention_USB = _EMU_EM23PERNORETAINCTRL_USBDIS_MASK, /* Select USB retention control */
#endif
#if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK)
emuPeripheralRetention_RTC = _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK, /* Select RTC retention control */
#endif
#if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK)
emuPeripheralRetention_ACMP3 = _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK, /* Select ACMP3 retention control */
#endif
#if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK)
emuPeripheralRetention_ACMP2 = _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK, /* Select ACMP2 retention control */
#endif
#if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK)
emuPeripheralRetention_ADC1 = _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK, /* Select ADC1 retention control */
#endif
#if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK)
emuPeripheralRetention_I2C2 = _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK, /* Select I2C2 retention control */
#endif
#if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK)
emuPeripheralRetention_LETIMER1 = _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK, /* Select LETIMER1 retention control */
#endif
#if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK)
emuPeripheralRetention_LCD = _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK, /* Select LCD retention control */
#endif
#if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK)
emuPeripheralRetention_LEUART1 = _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK, /* Select LEUART1 retention control */
#endif
emuPeripheralRetention_LEUART0 = _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK, /* Select LEUART0 retention control */
#if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK)
emuPeripheralRetention_CSEN = _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK, /* Select CSEN retention control */
#endif
emuPeripheralRetention_LESENSE0 = _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK, /* Select LESENSE0 retention control */
#if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK)
emuPeripheralRetention_WDOG1 = _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK, /* Select WDOG1 retention control */
#endif
emuPeripheralRetention_WDOG0 = _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK, /* Select WDOG0 retention control */
emuPeripheralRetention_LETIMER0 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK, /* Select LETIMER0 retention control */
emuPeripheralRetention_ADC0 = _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK, /* Select ADC0 retention control */
#if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK)
emuPeripheralRetention_IDAC0 = _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK, /* Select IDAC0 retention control */
#endif
emuPeripheralRetention_VDAC0 = _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK, /* Select DAC0 retention control */
#if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK)
emuPeripheralRetention_I2C1 = _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /* Select I2C1 retention control */
#endif
emuPeripheralRetention_I2C0 = _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, /* Select I2C0 retention control */
emuPeripheralRetention_ACMP1 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK, /* Select ACMP1 retention control */
emuPeripheralRetention_ACMP0 = _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK, /* Select ACMP0 retention control */
@ -347,18 +366,55 @@ typedef enum
| _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK
| _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,/* Select all peripherals in domain 1 */
emuPeripheralRetention_D2 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK
#if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK)
| _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK
#endif
| _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK
#if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK)
| _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK
#endif
| _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK
#if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK)
| _EMU_EM23PERNORETAINCTRL_USBDIS_MASK
#endif
#if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK)
| _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK
#endif
#if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK)
| _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK
#endif
#if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK)
| _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK
#endif
#if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK)
| _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK
#endif
#if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK)
| _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK
#endif
#if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK)
| _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK
#endif
#if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK)
| _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK
#endif
#if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK)
| _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK
#endif
#if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK)
| _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK
| _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK
#endif
| _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK
| _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /* Select all peripherals in domain 2 */
#if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK)
| _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK /* Select all peripherals in domain 2 */
#endif
| _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK,
emuPeripheralRetention_ALL = emuPeripheralRetention_D1
| emuPeripheralRetention_D2, /* Select all peripherals with retention control */
| emuPeripheralRetention_D2
#if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK)
| emuPeripheralRetention_WDOG1
#endif
| emuPeripheralRetention_WDOG0, /* Select all peripherals with retention control */
} EMU_PeripheralRetention_TypeDef;
#endif
@ -370,8 +426,7 @@ typedef enum
/** EM0 and 1 initialization structure. Voltage scaling is applied when
the core clock frequency is changed from @ref CMU. EM0 an 1 emuVScaleEM01_HighPerformance
is always enabled. */
typedef struct
{
typedef struct {
bool vScaleEM01LowPowerVoltageEnable; /**< EM0/1 low power voltage status */
} EMU_EM01Init_TypeDef;
#endif
@ -385,8 +440,7 @@ typedef struct
#endif
/** EM2 and 3 initialization structure */
typedef struct
{
typedef struct {
bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3 */
#if defined(_EMU_CTRL_EM23VSCALE_MASK)
EMU_VScaleEM23_TypeDef vScaleEM23Voltage; /**< EM2/3 voltage scaling level */
@ -409,8 +463,7 @@ typedef struct
#if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK)
/** EM4 initialization structure */
typedef struct
{
typedef struct {
#if defined(_EMU_EM4CONF_MASK)
/* Init parameters for platforms with EMU->EM4CONF register (Series 0) */
bool lockConfig; /**< Lock configuration of regulator, BOD and oscillator */
@ -467,10 +520,9 @@ typedef struct
}
#endif
#if defined( BU_PRESENT )
#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0)
/** Backup Power Domain Initialization structure */
typedef struct
{
typedef struct {
/* Backup Power Domain power configuration */
/** Voltage probe select, selects ADC voltage */
@ -517,8 +569,7 @@ typedef struct
#if defined(_EMU_DCDCCTRL_MASK)
/** DCDC initialization structure */
typedef struct
{
typedef struct {
EMU_PowerConfig_TypeDef powerConfig; /**< Device external power configuration.
@ref emuPowerConfig_DcdcToDvdd is currently the only supported mode. */
EMU_DcdcMode_TypeDef dcdcMode; /**< DCDC regulator operating mode in EM0/1 */
@ -571,7 +622,7 @@ typedef struct
10, /* Nominal EM2/3/4 load current less than 10uA */ \
200, /* Maximum average current of 200mA
(assume strong battery or other power source) */ \
emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \
emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply) */ \
emuDcdcLnHighEfficiency, /* Use high-efficiency mode */ \
emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \
}
@ -612,10 +663,9 @@ typedef struct
#if defined(EMU_STATUS_VMONRDY)
/** VMON initialization structure */
typedef struct
{
typedef struct {
EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure */
int threshold; /**< Trigger threshold (mV) */
int threshold; /**< Trigger threshold (mV). Supported range is 1620 mV to 3400 mV */
bool riseWakeup; /**< Wake up from EM4H on rising edge */
bool fallWakeup; /**< Wake up from EM4H on falling edge */
bool enable; /**< Enable VMON channel */
@ -634,8 +684,7 @@ typedef struct
}
/** VMON Hysteresis initialization structure */
typedef struct
{
typedef struct {
EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure */
int riseThreshold; /**< Rising threshold (mV) */
int fallThreshold; /**< Falling threshold (mV) */
@ -669,6 +718,7 @@ void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init);
#endif
void EMU_EnterEM2(bool restore);
void EMU_EnterEM3(bool restore);
void EMU_Save(void);
void EMU_Restore(void);
void EMU_EnterEM4(void);
#if defined(_EMU_EM4CTRL_MASK)
@ -685,7 +735,7 @@ void EMU_UpdateOscConfig(void);
void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait);
void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait);
#endif
#if defined( BU_PRESENT )
#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0)
void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit);
void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value);
void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value);
@ -717,7 +767,6 @@ __STATIC_INLINE void EMU_EnterEM1(void)
__WFI();
}
#if defined(_EMU_STATUS_VSCALE_MASK)
/***************************************************************************//**
* @brief
@ -774,7 +823,6 @@ __STATIC_INLINE void EMU_IntClear(uint32_t flags)
EMU->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more EMU interrupts.
@ -788,14 +836,13 @@ __STATIC_INLINE void EMU_IntDisable(uint32_t flags)
EMU->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more EMU interrupts.
*
* @note
* Depending on the use, a pending interrupt may already be set prior to
* enabling the interrupt. Consider using EMU_IntClear() prior to enabling
* enabling the interrupt. Consider using @ref EMU_IntClear() prior to enabling
* if such a pending interrupt should be ignored.
*
* @param[in] flags
@ -807,7 +854,6 @@ __STATIC_INLINE void EMU_IntEnable(uint32_t flags)
EMU->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending EMU interrupt flags.
@ -824,7 +870,6 @@ __STATIC_INLINE uint32_t EMU_IntGet(void)
return EMU->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending EMU interrupt flags.
@ -847,7 +892,6 @@ __STATIC_INLINE uint32_t EMU_IntGetEnabled(void)
return EMU->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending EMU interrupts
@ -862,7 +906,6 @@ __STATIC_INLINE void EMU_IntSet(uint32_t flags)
}
#endif /* _EMU_IF_MASK */
#if defined(_EMU_EM4CONF_LOCKCONF_MASK)
/***************************************************************************//**
* @brief
@ -918,7 +961,6 @@ __STATIC_INLINE void EMU_Lock(void)
EMU->LOCK = EMU_LOCK_LOCKKEY_LOCK;
}
/***************************************************************************//**
* @brief
* Unlock the EMU so that writing to locked registers again is possible.
@ -928,7 +970,6 @@ __STATIC_INLINE void EMU_Unlock(void)
EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK;
}
#if defined(_EMU_PWRLOCK_MASK)
/***************************************************************************//**
* @brief
@ -940,7 +981,6 @@ __STATIC_INLINE void EMU_PowerLock(void)
EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK;
}
/***************************************************************************//**
* @brief
* Unlock the EMU power control registers so that writing to
@ -952,7 +992,6 @@ __STATIC_INLINE void EMU_PowerUnlock(void)
}
#endif
/***************************************************************************//**
* @brief
* Block entering EM2 or higher number energy modes.

7
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpcrc.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file
* @brief General Purpose Cyclic Redundancy Check (GPCRC) API.
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -99,8 +99,7 @@ extern "C" {
******************************************************************************/
/** CRC initialization structure. */
typedef struct
{
typedef struct {
/**
* CRC polynomial value. The GPCRC support either a fixed 32-bit polynomial
* or a user configurable 16 bit polynomial. The fixed 32-bit polynomial

175
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpio.h
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@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_gpio.h
* @brief General Purpose IO (GPIO) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -30,7 +30,6 @@
*
******************************************************************************/
#ifndef EM_GPIO_H
#define EM_GPIO_H
@ -60,7 +59,8 @@ extern "C" {
******************************************************************************/
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
#if defined( _EFM32_TINY_FAMILY ) || defined( _EFM32_ZERO_FAMILY )
#if defined(_SILICON_LABS_32B_SERIES_0) \
&& defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY)
#define _GPIO_PORT_A_PIN_COUNT 14
#define _GPIO_PORT_B_PIN_COUNT 10
@ -112,8 +112,8 @@ extern "C" {
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
#elif defined( _EFM32_GIANT_FAMILY ) \
|| defined( _EFM32_WONDER_FAMILY )
#elif defined(_SILICON_LABS_32B_SERIES_0) \
&& (defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY))
#define _GPIO_PORT_A_PIN_COUNT 16
#define _GPIO_PORT_B_PIN_COUNT 16
@ -170,7 +170,7 @@ extern "C" {
#define _GPIO_PORT_A_PIN_COUNT 6
#define _GPIO_PORT_B_PIN_COUNT 5
#define _GPIO_PORT_C_PIN_COUNT 6
#define _GPIO_PORT_D_PIN_COUNT 6
#define _GPIO_PORT_D_PIN_COUNT 7
#define _GPIO_PORT_E_PIN_COUNT 0
#define _GPIO_PORT_F_PIN_COUNT 8
#define _GPIO_PORT_G_PIN_COUNT 0
@ -182,7 +182,7 @@ extern "C" {
#define _GPIO_PORT_A_PIN_MASK 0x003F
#define _GPIO_PORT_B_PIN_MASK 0xF800
#define _GPIO_PORT_C_PIN_MASK 0x0FC0
#define _GPIO_PORT_D_PIN_MASK 0xFC00
#define _GPIO_PORT_D_PIN_MASK 0xFE00
#define _GPIO_PORT_E_PIN_MASK 0x0000
#define _GPIO_PORT_F_PIN_MASK 0x00FF
#define _GPIO_PORT_G_PIN_MASK 0x0000
@ -269,37 +269,115 @@ extern "C" {
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
#elif defined(_SILICON_LABS_32B_SERIES_1) && defined(_EFM32_GIANT_FAMILY)
#define _GPIO_PORT_A_PIN_COUNT 16
#define _GPIO_PORT_B_PIN_COUNT 16
#define _GPIO_PORT_C_PIN_COUNT 16
#define _GPIO_PORT_D_PIN_COUNT 16
#define _GPIO_PORT_E_PIN_COUNT 16
#define _GPIO_PORT_F_PIN_COUNT 16
#define _GPIO_PORT_G_PIN_COUNT 16
#define _GPIO_PORT_H_PIN_COUNT 16
#define _GPIO_PORT_I_PIN_COUNT 16
#define _GPIO_PORT_J_PIN_COUNT 0
#define _GPIO_PORT_K_PIN_COUNT 0
#define _GPIO_PORT_A_PIN_MASK 0xFFFF
#define _GPIO_PORT_B_PIN_MASK 0xFFFF
#define _GPIO_PORT_C_PIN_MASK 0xFFFF
#define _GPIO_PORT_D_PIN_MASK 0xFFFF
#define _GPIO_PORT_E_PIN_MASK 0xFFFF
#define _GPIO_PORT_F_PIN_MASK 0xFFFF
#define _GPIO_PORT_G_PIN_MASK 0xFFFF
#define _GPIO_PORT_H_PIN_MASK 0xFFFF
#define _GPIO_PORT_I_PIN_MASK 0xFFFF
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
#define _GPIO_PORT_A_PIN_COUNT 6
#define _GPIO_PORT_B_PIN_COUNT 5
#define _GPIO_PORT_C_PIN_COUNT 6
#define _GPIO_PORT_D_PIN_COUNT 6
#define _GPIO_PORT_E_PIN_COUNT 0
#define _GPIO_PORT_F_PIN_COUNT 8
#define _GPIO_PORT_G_PIN_COUNT 0
#define _GPIO_PORT_H_PIN_COUNT 0
#define _GPIO_PORT_I_PIN_COUNT 0
#define _GPIO_PORT_J_PIN_COUNT 0
#define _GPIO_PORT_K_PIN_COUNT 0
#define _GPIO_PORT_A_PIN_MASK 0x003F
#define _GPIO_PORT_B_PIN_MASK 0xF800
#define _GPIO_PORT_C_PIN_MASK 0x0FC0
#define _GPIO_PORT_D_PIN_MASK 0xFC00
#define _GPIO_PORT_E_PIN_MASK 0x0000
#define _GPIO_PORT_F_PIN_MASK 0x00FF
#define _GPIO_PORT_G_PIN_MASK 0x0000
#define _GPIO_PORT_H_PIN_MASK 0x0000
#define _GPIO_PORT_I_PIN_MASK 0x0000
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
#define _GPIO_PORT_A_PIN_COUNT 14
#define _GPIO_PORT_B_PIN_COUNT 10
#define _GPIO_PORT_C_PIN_COUNT 16
#define _GPIO_PORT_D_PIN_COUNT 9
#define _GPIO_PORT_E_PIN_COUNT 12
#define _GPIO_PORT_F_PIN_COUNT 6
#define _GPIO_PORT_G_PIN_COUNT 0
#define _GPIO_PORT_H_PIN_COUNT 0
#define _GPIO_PORT_I_PIN_COUNT 0
#define _GPIO_PORT_J_PIN_COUNT 0
#define _GPIO_PORT_K_PIN_COUNT 0
#define _GPIO_PORT_A_PIN_MASK 0xF77F
#define _GPIO_PORT_B_PIN_MASK 0x79F8
#define _GPIO_PORT_C_PIN_MASK 0xFFFF
#define _GPIO_PORT_D_PIN_MASK 0x01FF
#define _GPIO_PORT_E_PIN_MASK 0xFFF0
#define _GPIO_PORT_F_PIN_MASK 0x003F
#define _GPIO_PORT_G_PIN_MASK 0x0000
#define _GPIO_PORT_H_PIN_MASK 0x0000
#define _GPIO_PORT_I_PIN_MASK 0x0000
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
#else
#warning "Port and pin masks are not defined for this family."
#endif
#define _GPIO_PORT_SIZE(port) ( \
(port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \
(port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \
(port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \
(port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \
(port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \
(port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \
(port) == 6 ? _GPIO_PORT_G_PIN_COUNT : \
(port) == 7 ? _GPIO_PORT_H_PIN_COUNT : \
(port) == 8 ? _GPIO_PORT_I_PIN_COUNT : \
(port) == 9 ? _GPIO_PORT_J_PIN_COUNT : \
(port) == 10 ? _GPIO_PORT_K_PIN_COUNT : \
0)
(port) == 0 ? _GPIO_PORT_A_PIN_COUNT \
: (port) == 1 ? _GPIO_PORT_B_PIN_COUNT \
: (port) == 2 ? _GPIO_PORT_C_PIN_COUNT \
: (port) == 3 ? _GPIO_PORT_D_PIN_COUNT \
: (port) == 4 ? _GPIO_PORT_E_PIN_COUNT \
: (port) == 5 ? _GPIO_PORT_F_PIN_COUNT \
: (port) == 6 ? _GPIO_PORT_G_PIN_COUNT \
: (port) == 7 ? _GPIO_PORT_H_PIN_COUNT \
: (port) == 8 ? _GPIO_PORT_I_PIN_COUNT \
: (port) == 9 ? _GPIO_PORT_J_PIN_COUNT \
: (port) == 10 ? _GPIO_PORT_K_PIN_COUNT \
: 0)
#define _GPIO_PORT_MASK(port) ( \
(port) == 0 ? _GPIO_PORT_A_PIN_MASK : \
(port) == 1 ? _GPIO_PORT_B_PIN_MASK : \
(port) == 2 ? _GPIO_PORT_C_PIN_MASK : \
(port) == 3 ? _GPIO_PORT_D_PIN_MASK : \
(port) == 4 ? _GPIO_PORT_E_PIN_MASK : \
(port) == 5 ? _GPIO_PORT_F_PIN_MASK : \
(port) == 6 ? _GPIO_PORT_G_PIN_MASK : \
(port) == 7 ? _GPIO_PORT_H_PIN_MASK : \
(port) == 8 ? _GPIO_PORT_I_PIN_MASK : \
(port) == 9 ? _GPIO_PORT_J_PIN_MASK : \
(port) == 10 ? _GPIO_PORT_K_PIN_MASK : \
0)
(port) == 0 ? _GPIO_PORT_A_PIN_MASK \
: (port) == 1 ? _GPIO_PORT_B_PIN_MASK \
: (port) == 2 ? _GPIO_PORT_C_PIN_MASK \
: (port) == 3 ? _GPIO_PORT_D_PIN_MASK \
: (port) == 4 ? _GPIO_PORT_E_PIN_MASK \
: (port) == 5 ? _GPIO_PORT_F_PIN_MASK \
: (port) == 6 ? _GPIO_PORT_G_PIN_MASK \
: (port) == 7 ? _GPIO_PORT_H_PIN_MASK \
: (port) == 8 ? _GPIO_PORT_I_PIN_MASK \
: (port) == 9 ? _GPIO_PORT_J_PIN_MASK \
: (port) == 10 ? _GPIO_PORT_K_PIN_MASK \
: 0)
/** Validation of port and pin */
#define GPIO_PORT_VALID(port) (_GPIO_PORT_MASK(port) )
@ -342,8 +420,7 @@ extern "C" {
******************************************************************************/
/** GPIO ports ids. */
typedef enum
{
typedef enum {
#if (_GPIO_PORT_A_PIN_COUNT > 0)
gpioPortA = 0,
#endif
@ -381,8 +458,7 @@ typedef enum
#if defined(_GPIO_P_CTRL_DRIVEMODE_MASK)
/** GPIO drive mode. */
typedef enum
{
typedef enum {
/** Default 6mA */
gpioDriveModeStandard = GPIO_P_CTRL_DRIVEMODE_STANDARD,
/** 0.5 mA */
@ -396,8 +472,7 @@ typedef enum
#if defined(_GPIO_P_CTRL_DRIVESTRENGTH_MASK) && defined(_GPIO_P_CTRL_DRIVESTRENGTHALT_MASK)
/** GPIO drive strength. */
typedef enum
{
typedef enum {
/** GPIO weak 1mA and alternate function weak 1mA */
gpioDriveStrengthWeakAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK,
@ -418,8 +493,7 @@ typedef enum
/** Pin mode. For more details on each mode, please refer to the
* reference manual. */
typedef enum
{
typedef enum {
/** Input disabled. Pullup if DOUT is set. */
gpioModeDisabled = _GPIO_P_MODEL_MODE0_DISABLED,
/** Input enabled. Filter if DOUT is set */
@ -532,7 +606,7 @@ __STATIC_INLINE void GPIO_DbgSWDIOEnable(bool enable)
* @note
* Enabling this pin is not sufficient to fully enable serial wire output
* which is also dependent on issues outside the GPIO module. Please refer to
* DBG_SWOEnable().
* @ref DBG_SWOEnable().
*
* @param[in] enable
* @li false - disable serial wire viewer pin (default after reset).
@ -605,7 +679,7 @@ __STATIC_INLINE uint32_t GPIO_EM4GetPinWakeupCause(void)
* pull direction in EM4.
*
* @note
* For platform 2 parts, EMU_EM4Init() and EMU_UnlatchPinRetention() offers
* For platform 2 parts, @ref EMU_EM4Init() and @ref EMU_UnlatchPinRetention() offers
* more pin retention features. This function implements the EM4EXIT retention
* mode on platform 2.
*
@ -615,17 +689,14 @@ __STATIC_INLINE uint32_t GPIO_EM4GetPinWakeupCause(void)
*****************************************************************************/
__STATIC_INLINE void GPIO_EM4SetPinRetention(bool enable)
{
if (enable)
{
if (enable) {
#if defined(GPIO_CTRL_EM4RET)
GPIO->CTRL |= GPIO_CTRL_EM4RET;
#else
EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK)
| EMU_EM4CTRL_EM4IORETMODE_EM4EXIT;
#endif
}
else
{
} else {
#if defined(GPIO_CTRL_EM4RET)
GPIO->CTRL &= ~GPIO_CTRL_EM4RET;
#else
@ -694,7 +765,7 @@ __STATIC_INLINE void GPIO_IntDisable(uint32_t flags)
*
* @note
* Depending on the use, a pending interrupt may already be set prior to
* enabling the interrupt. Consider using GPIO_IntClear() prior to enabling
* enabling the interrupt. Consider using @ref GPIO_IntClear() prior to enabling
* if such a pending interrupt should be ignored.
*
* @param[in] flags
@ -814,7 +885,7 @@ __STATIC_INLINE void GPIO_PinOutClear(GPIO_Port_TypeDef port, unsigned int pin)
#if defined(_GPIO_P_DOUTCLR_MASK)
GPIO->P[port].DOUTCLR = 1 << pin;
#else
BUS_RegBitWrite(&GPIO->P[port].DOUT, pin, 0);
BUS_RegMaskedClear(&GPIO->P[port].DOUT, 1 << pin);
#endif
}
@ -859,7 +930,7 @@ __STATIC_INLINE void GPIO_PinOutSet(GPIO_Port_TypeDef port, unsigned int pin)
#if defined(_GPIO_P_DOUTSET_MASK)
GPIO->P[port].DOUTSET = 1 << pin;
#else
BUS_RegBitWrite(&GPIO->P[port].DOUT, pin, 1);
BUS_RegMaskedSet(&GPIO->P[port].DOUT, 1 << pin);
#endif
}
@ -1067,7 +1138,7 @@ __STATIC_INLINE void GPIO_Unlock(void)
*
* @details
* If reconfiguring a GPIO interrupt that is already enabled, it is generally
* recommended to disable it first, see GPIO_Disable().
* recommended to disable it first, see @ref GPIO_Disable().
*
* The actual GPIO interrupt handler must be in place before enabling the
* interrupt.
@ -1099,7 +1170,7 @@ __STATIC_INLINE void GPIO_Unlock(void)
*
* @param[in] enable
* Set to true if interrupt shall be enabled after configuration completed,
* false to leave disabled. See GPIO_IntDisable() and GPIO_IntEnable().
* false to leave disabled. See @ref GPIO_IntDisable() and @ref GPIO_IntEnable().
******************************************************************************/
__STATIC_INLINE void GPIO_IntConfig(GPIO_Port_TypeDef port,
unsigned int pin,

35
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_i2c.h
* @brief Inter-intergrated circuit (I2C) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -98,7 +98,6 @@ extern "C" {
*/
#define I2C_FREQ_FAST_MAX 392157
/**
* @brief
* Fast mode+ max frequency assuming using 11:6 ratio for Nlow:Nhigh.
@ -111,7 +110,6 @@ extern "C" {
*/
#define I2C_FREQ_FASTPLUS_MAX 987167
/**
* @brief
* Indicate plain write sequence: S+ADDR(W)+DATA0+P.
@ -161,23 +159,19 @@ extern "C" {
/** Use 10 bit address. */
#define I2C_FLAG_10BIT_ADDR 0x0010
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
/** Clock low to high ratio settings. */
typedef enum
{
typedef enum {
i2cClockHLRStandard = _I2C_CTRL_CLHR_STANDARD, /**< Ratio is 4:4 */
i2cClockHLRAsymetric = _I2C_CTRL_CLHR_ASYMMETRIC, /**< Ratio is 6:3 */
i2cClockHLRFast = _I2C_CTRL_CLHR_FAST /**< Ratio is 11:3 */
} I2C_ClockHLR_TypeDef;
/** Return codes for single master mode transfer function. */
typedef enum
{
typedef enum {
/* In progress code (>0) */
i2cTransferInProgress = 1, /**< Transfer in progress. */
@ -192,14 +186,12 @@ typedef enum
i2cTransferSwFault = -5 /**< SW fault. */
} I2C_TransferReturn_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** I2C initialization structure. */
typedef struct
{
typedef struct {
/** Enable I2C peripheral when init completed. */
bool enable;
@ -234,7 +226,6 @@ typedef struct
i2cClockHLRStandard /* Set to use 4:4 low/high duty cycle */ \
}
/**
* @brief
* Master mode transfer message structure used to define a complete
@ -249,8 +240,7 @@ typedef struct
* @li #I2C_FLAG_WRITE_WRITE - data written from buf[0].data and
* buf[1].data
*/
typedef struct
{
typedef struct {
/**
* @brief
* Address to use after (repeated) start.
@ -268,8 +258,7 @@ typedef struct
* Buffers used to hold data to send from or receive into depending
* on sequence type.
*/
struct
{
struct {
/** Buffer used for data to transmit/receive, must be @p len long. */
uint8_t *data;
@ -284,7 +273,6 @@ typedef struct
} buf[2];
} I2C_TransferSeq_TypeDef;
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
@ -313,7 +301,6 @@ __STATIC_INLINE void I2C_IntClear(I2C_TypeDef *i2c, uint32_t flags)
i2c->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more I2C interrupts.
@ -330,7 +317,6 @@ __STATIC_INLINE void I2C_IntDisable(I2C_TypeDef *i2c, uint32_t flags)
i2c->IEN &= ~(flags);
}
/***************************************************************************//**
* @brief
* Enable one or more I2C interrupts.
@ -352,7 +338,6 @@ __STATIC_INLINE void I2C_IntEnable(I2C_TypeDef *i2c, uint32_t flags)
i2c->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending I2C interrupt flags.
@ -372,7 +357,6 @@ __STATIC_INLINE uint32_t I2C_IntGet(I2C_TypeDef *i2c)
return i2c->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending I2C interrupt flags.
@ -398,7 +382,6 @@ __STATIC_INLINE uint32_t I2C_IntGetEnabled(I2C_TypeDef *i2c)
return i2c->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending I2C interrupts from SW.
@ -439,7 +422,6 @@ __STATIC_INLINE uint8_t I2C_SlaveAddressGet(I2C_TypeDef *i2c)
return ((uint8_t)(i2c->SADDR));
}
/***************************************************************************//**
* @brief
* Set slave address to use for I2C peripheral (when operating in slave mode).
@ -462,7 +444,6 @@ __STATIC_INLINE void I2C_SlaveAddressSet(I2C_TypeDef *i2c, uint8_t addr)
i2c->SADDR = (uint32_t)addr & 0xfe;
}
/***************************************************************************//**
* @brief
* Get slave address mask used for I2C peripheral (when operating in slave
@ -491,7 +472,6 @@ __STATIC_INLINE uint8_t I2C_SlaveAddressMaskGet(I2C_TypeDef *i2c)
return ((uint8_t)(i2c->SADDRMASK));
}
/***************************************************************************//**
* @brief
* Set slave address mask used for I2C peripheral (when operating in slave
@ -520,7 +500,6 @@ __STATIC_INLINE void I2C_SlaveAddressMaskSet(I2C_TypeDef *i2c, uint8_t mask)
i2c->SADDRMASK = (uint32_t)mask & 0xfe;
}
I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c);
I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c,
I2C_TransferSeq_TypeDef *seq);

28
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_idac.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_idac.h
* @brief Current Digital to Analog Converter (IDAC) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -90,8 +90,7 @@ extern "C" {
******************************************************************************/
/** Output mode. */
typedef enum
{
typedef enum {
#if defined(_IDAC_CTRL_OUTMODE_MASK)
idacOutputPin = IDAC_CTRL_OUTMODE_PIN, /**< Output to IDAC OUT pin */
idacOutputADC = IDAC_CTRL_OUTMODE_ADC /**< Output to ADC */
@ -131,11 +130,9 @@ typedef enum
#endif
} IDAC_OutMode_TypeDef;
/** Selects which Peripheral Reflex System (PRS) signal to use when
PRS is set to control the IDAC output. */
typedef enum
{
typedef enum {
idacPRSSELCh0 = IDAC_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */
idacPRSSELCh1 = IDAC_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */
idacPRSSELCh2 = IDAC_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */
@ -154,10 +151,8 @@ typedef enum
#endif
} IDAC_PRSSEL_TypeDef;
/** Selects which current range to use. */
typedef enum
{
typedef enum {
idacCurrentRange0 = IDAC_CURPROG_RANGESEL_RANGE0, /**< current range 0. */
idacCurrentRange1 = IDAC_CURPROG_RANGESEL_RANGE1, /**< current range 1. */
idacCurrentRange2 = IDAC_CURPROG_RANGESEL_RANGE2, /**< current range 2. */
@ -169,8 +164,7 @@ typedef enum
******************************************************************************/
/** IDAC init structure, common for both channels. */
typedef struct
{
typedef struct {
/** Enable IDAC. */
bool enable;
@ -192,7 +186,6 @@ typedef struct
/** Enable/disable current sink mode. */
bool sinkEnable;
} IDAC_Init_TypeDef;
/** Default config for IDAC init structure. */
@ -216,12 +209,10 @@ typedef struct
}
#endif
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
void IDAC_Init(IDAC_TypeDef *idac, const IDAC_Init_TypeDef *init);
void IDAC_Enable(IDAC_TypeDef *idac, bool enable);
void IDAC_Reset(IDAC_TypeDef *idac);
@ -230,7 +221,6 @@ void IDAC_RangeSet(IDAC_TypeDef *idac, const IDAC_Range_TypeDef range);
void IDAC_StepSet(IDAC_TypeDef *idac, const uint32_t step);
void IDAC_OutEnable(IDAC_TypeDef *idac, bool enable);
#if defined(_IDAC_IEN_MASK)
/***************************************************************************//**
* @brief
@ -248,7 +238,6 @@ __STATIC_INLINE void IDAC_IntClear(IDAC_TypeDef *idac, uint32_t flags)
idac->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more IDAC interrupts.
@ -265,7 +254,6 @@ __STATIC_INLINE void IDAC_IntDisable(IDAC_TypeDef *idac, uint32_t flags)
idac->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more IDAC interrupts.
@ -287,7 +275,6 @@ __STATIC_INLINE void IDAC_IntEnable(IDAC_TypeDef *idac, uint32_t flags)
idac->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending IDAC interrupt flags.
@ -307,7 +294,6 @@ __STATIC_INLINE uint32_t IDAC_IntGet(IDAC_TypeDef *idac)
return idac->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending IDAC interrupt flags.
@ -339,7 +325,6 @@ __STATIC_INLINE uint32_t IDAC_IntGetEnabled(IDAC_TypeDef *idac)
return idac->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending IDAC interrupts from SW.
@ -357,7 +342,6 @@ __STATIC_INLINE void IDAC_IntSet(IDAC_TypeDef *idac, uint32_t flags)
}
#endif
/** @} (end addtogroup IDAC) */
/** @} (end addtogroup emlib) */

132
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_int.h
View File

@ -1,132 +0,0 @@
/***************************************************************************//**
* @file em_int.h
* @brief Interrupt enable/disable unit API
* @version 5.1.2
*******************************************************************************
* @section License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
* obligation to support this Software. Silicon Labs is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Silicon Labs will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
******************************************************************************/
#ifndef EM_INT_H
#define EM_INT_H
#include "em_device.h"
extern uint32_t INT_LockCnt;
#ifdef __cplusplus
extern "C" {
#endif
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
#ifndef UINT32_MAX
#define UINT32_MAX ((uint32_t)(0xFFFFFFFF))
#endif
#warning "The INT module is deprecated and marked for removal in a later release. Please use the new CORE module instead. See \"Porting from em_int\" in the CORE documentation for instructions."
/** @endcond */
/***************************************************************************//**
* @addtogroup emlib
* @{
******************************************************************************/
/***************************************************************************//**
* @addtogroup INT
* @{
******************************************************************************/
/***************************************************************************//**
* @brief
* Disable interrupts.
*
* @deprecated
* This function is deprecated and marked for removal in a later release.
* Please use the new CORE module instead.
*
* @details
* Disable interrupts and increment lock level counter.
*
* @return
* The resulting interrupt disable nesting level.
*
******************************************************************************/
__STATIC_INLINE uint32_t INT_Disable(void)
{
__disable_irq();
if (INT_LockCnt < UINT32_MAX)
{
INT_LockCnt++;
}
return INT_LockCnt;
}
/***************************************************************************//**
* @brief
* Enable interrupts.
*
* @deprecated
* This function is deprecated and marked for removal in a later release.
* Please use the new CORE module instead.
*
* @return
* The resulting interrupt disable nesting level.
*
* @details
* Decrement interrupt lock level counter and enable interrupts if counter
* reached zero.
*
******************************************************************************/
__STATIC_INLINE uint32_t INT_Enable(void)
{
uint32_t retVal;
if (INT_LockCnt > 0)
{
INT_LockCnt--;
retVal = INT_LockCnt;
if (retVal == 0)
{
__enable_irq();
}
return retVal;
}
else
{
return 0;
}
}
/** @} (end addtogroup INT) */
/** @} (end addtogroup emlib) */
#ifdef __cplusplus
}
#endif
#endif /* EM_INT_H */

194
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lcd.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_lcd.h
* @brief Liquid Crystal Display (LCD) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -53,13 +53,19 @@ extern "C" {
* @{
******************************************************************************/
/*******************************************************************************
******************************** DEFINES **********************************
******************************************************************************/
#define LCD_DEFAULT_FRAME_RATE_DIV 4
#define LCD_DEFAULT_CONTRAST 15
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
/** MUX setting */
typedef enum
{
typedef enum {
/** Static (segments can be multiplexed with LCD_COM[0]) */
lcdMuxStatic = LCD_DISPCTRL_MUX_STATIC,
/** Duplex / 1/2 Duty cycle (segments can be multiplexed with LCD_COM[0:1]) */
@ -73,12 +79,24 @@ typedef enum
lcdMuxSextaplex = LCD_DISPCTRL_MUXE_MUXE | LCD_DISPCTRL_MUX_DUPLEX,
/** Octaplex / 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]) */
lcdMuxOctaplex = LCD_DISPCTRL_MUXE_MUXE | LCD_DISPCTRL_MUX_QUADRUPLEX
#elif defined(LCD_DISPCTRL_MUX_SEXTAPLEX)
/** Sextaplex / 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]) */
lcdMuxSextaplex = LCD_DISPCTRL_MUX_SEXTAPLEX,
/** Octaplex / 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]) */
lcdMuxOctaplex = LCD_DISPCTRL_MUX_OCTAPLEX,
#endif
} LCD_Mux_TypeDef;
/** Wave type */
typedef enum {
/** Low power optimized waveform output */
lcdWaveLowPower = LCD_DISPCTRL_WAVE_LOWPOWER,
/** Regular waveform output */
lcdWaveNormal = LCD_DISPCTRL_WAVE_NORMAL
} LCD_Wave_TypeDef;
/** Bias setting */
typedef enum
{
typedef enum {
/** Static (2 levels) */
lcdBiasStatic = LCD_DISPCTRL_BIAS_STATIC,
/** 1/2 Bias (3 levels) */
@ -91,36 +109,29 @@ typedef enum
#endif
} LCD_Bias_TypeDef;
/** Wave type */
typedef enum
{
/** Low power optimized waveform output */
lcdWaveLowPower = LCD_DISPCTRL_WAVE_LOWPOWER,
/** Regular waveform output */
lcdWaveNormal = LCD_DISPCTRL_WAVE_NORMAL
} LCD_Wave_TypeDef;
#if defined(_SILICON_LABS_32B_SERIES_0)
/** VLCD Voltage Source */
typedef enum
{
typedef enum {
/** VLCD Powered by VDD */
lcdVLCDSelVDD = LCD_DISPCTRL_VLCDSEL_VDD,
/** VLCD Powered by external VDD / Voltage Boost */
lcdVLCDSelVExtBoost = LCD_DISPCTRL_VLCDSEL_VEXTBOOST
} LCD_VLCDSel_TypeDef;
#endif
/** Contrast Configuration */
typedef enum
{
#if defined(_SILICON_LABS_32B_SERIES_0)
typedef enum {
/** Contrast is adjusted relative to VDD (VLCD) */
lcdConConfVLCD = LCD_DISPCTRL_CONCONF_VLCD,
/** Contrast is adjusted relative to Ground */
lcdConConfGND = LCD_DISPCTRL_CONCONF_GND
} LCD_ConConf_TypeDef;
#endif
#if defined(_SILICON_LABS_32B_SERIES_0)
/** Voltage Boost Level - Datasheets document setting for each part number */
typedef enum
{
typedef enum {
lcdVBoostLevel0 = LCD_DISPCTRL_VBLEV_LEVEL0, /**< Voltage boost LEVEL0 */
lcdVBoostLevel1 = LCD_DISPCTRL_VBLEV_LEVEL1, /**< Voltage boost LEVEL1 */
lcdVBoostLevel2 = LCD_DISPCTRL_VBLEV_LEVEL2, /**< Voltage boost LEVEL2 */
@ -130,10 +141,19 @@ typedef enum
lcdVBoostLevel6 = LCD_DISPCTRL_VBLEV_LEVEL6, /**< Voltage boost LEVEL6 */
lcdVBoostLevel7 = LCD_DISPCTRL_VBLEV_LEVEL7 /**< Voltage boost LEVEL7 */
} LCD_VBoostLevel_TypeDef;
#endif
#if defined(_SILICON_LABS_32B_SERIES_1)
/** Mode */
typedef enum {
lcdModeNoExtCap = LCD_DISPCTRL_MODE_NOEXTCAP, /**< No external capacitor */
lcdModeStepDown = LCD_DISPCTRL_MODE_STEPDOWN, /**< External cap with resistor string */
lcdModeCpIntOsc = LCD_DISPCTRL_MODE_CPINTOSC, /**< External cap and internal oscillator */
} LCD_Mode_Typedef;
#endif
/** Frame Counter Clock Prescaler, FC-CLK = FrameRate (Hz) / this factor */
typedef enum
{
typedef enum {
/** Prescale Div 1 */
lcdFCPrescDiv1 = LCD_BACTRL_FCPRESC_DIV1,
/** Prescale Div 2 */
@ -144,9 +164,9 @@ typedef enum
lcdFCPrescDiv8 = LCD_BACTRL_FCPRESC_DIV8
} LCD_FCPreScale_TypeDef;
#if defined(_SILICON_LABS_32B_SERIES_0)
/** Segment selection */
typedef enum
{
typedef enum {
/** Select segment lines 0 to 3 */
lcdSegment0_3 = (1 << 0),
/** Select segment lines 4 to 7 */
@ -175,10 +195,10 @@ typedef enum
lcdSegmentAll = (0x03ff)
#endif
} LCD_SegmentRange_TypeDef;
#endif
/** Update Data Control */
typedef enum
{
typedef enum {
/** Regular update, data transfer done immediately */
lcdUpdateCtrlRegular = LCD_CTRL_UDCTRL_REGULAR,
/** Data transfer done at Frame Counter event */
@ -188,8 +208,7 @@ typedef enum
} LCD_UpdateCtrl_TypeDef;
/** Animation Shift operation; none, left or right */
typedef enum
{
typedef enum {
/** No shift */
lcdAnimShiftNone = _LCD_BACTRL_AREGASC_NOSHIFT,
/** Shift segment bits left */
@ -199,22 +218,19 @@ typedef enum
} LCD_AnimShift_TypeDef;
/** Animation Logic Control, how AReg and BReg should be combined */
typedef enum
{
typedef enum {
/** Use bitwise logic AND to mix animation register A (AREGA) and B (AREGB) */
lcdAnimLogicAnd = LCD_BACTRL_ALOGSEL_AND,
/** Use bitwise logic OR to mix animation register A (AREGA) and B (AREGB) */
lcdAnimLogicOr = LCD_BACTRL_ALOGSEL_OR
} LCD_AnimLogic_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** LCD Animation Configuration */
typedef struct
{
typedef struct {
/** Enable Animation at end of initialization */
bool enable;
/** Initial Animation Register A Value */
@ -234,8 +250,7 @@ typedef struct
} LCD_AnimInit_TypeDef;
/** LCD Frame Control Initialization */
typedef struct
{
typedef struct {
/** Enable at end */
bool enable;
/** Frame Counter top value */
@ -245,8 +260,7 @@ typedef struct
} LCD_FrameCountInit_TypeDef;
/** LCD Controller Initialization structure */
typedef struct
{
typedef struct {
/** Enable controller at end of initialization */
bool enable;
/** Mux configuration */
@ -255,13 +269,23 @@ typedef struct
LCD_Bias_TypeDef bias;
/** Wave configuration */
LCD_Wave_TypeDef wave;
#if defined(_SILICON_LABS_32B_SERIES_0)
/** VLCD Select */
LCD_VLCDSel_TypeDef vlcd;
/** Contrast Configuration */
LCD_ConConf_TypeDef contrast;
#endif
#if defined(_SILICON_LABS_32B_SERIES_1)
/** Mode */
LCD_Mode_Typedef mode;
uint8_t chgrDst;
uint8_t frameRateDivider;
int contrastLevel;
#endif
} LCD_Init_TypeDef;
/** Default config for LCD init structure, enables 160 segments */
#if defined(_SILICON_LABS_32B_SERIES_0)
#define LCD_INIT_DEFAULT \
{ \
true, \
@ -269,32 +293,57 @@ typedef struct
lcdBiasOneThird, \
lcdWaveLowPower, \
lcdVLCDSelVDD, \
lcdConConfVLCD \
lcdConConfVLCD, \
}
#endif
#if defined(_SILICON_LABS_32B_SERIES_1)
#define LCD_INIT_DEFAULT \
{ \
true, \
lcdMuxQuadruplex, \
lcdBiasOneThird, \
lcdWaveLowPower, \
lcdModeNoExtCap, \
0, \
LCD_DEFAULT_FRAME_RATE_DIV, \
LCD_DEFAULT_CONTRAST \
}
#endif
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
void LCD_Init(const LCD_Init_TypeDef *lcdInit);
#if defined(_SILICON_LABS_32B_SERIES_0)
void LCD_VLCDSelect(LCD_VLCDSel_TypeDef vlcd);
#endif
void LCD_UpdateCtrl(LCD_UpdateCtrl_TypeDef ud);
void LCD_FrameCountInit(const LCD_FrameCountInit_TypeDef *fcInit);
void LCD_AnimInit(const LCD_AnimInit_TypeDef *animInit);
#if defined(_SILICON_LABS_32B_SERIES_0)
void LCD_SegmentRangeEnable(LCD_SegmentRange_TypeDef segment, bool enable);
#endif
void LCD_SegmentSet(int com, int bit, bool enable);
void LCD_SegmentSetLow(int com, uint32_t mask, uint32_t bits);
#if defined(_LCD_SEGD0H_MASK)
void LCD_SegmentSetHigh(int com, uint32_t mask, uint32_t bits);
#endif
void LCD_ContrastSet(int level);
void LCD_BiasSet(LCD_Bias_TypeDef bias);
#if defined(_SILICON_LABS_32B_SERIES_0)
void LCD_VBoostSet(LCD_VBoostLevel_TypeDef vboost);
#endif
#if defined(LCD_CTRL_DSC)
void LCD_BiasSegmentSet(int segment, int biasLevel);
void LCD_BiasComSet(int com, int biasLevel);
#endif
#if defined(_SILICON_LABS_32B_SERIES_1)
void LCD_ModeSet(LCD_Mode_Typedef mode);
void LCD_ChargeRedistributionCyclesSet(uint8_t cycles);
#endif
/***************************************************************************//**
* @brief
@ -307,17 +356,13 @@ void LCD_BiasComSet(int com, int biasLevel);
******************************************************************************/
__STATIC_INLINE void LCD_Enable(bool enable)
{
if (enable)
{
if (enable) {
LCD->CTRL |= LCD_CTRL_EN;
}
else
{
} else {
LCD->CTRL &= ~LCD_CTRL_EN;
}
}
/***************************************************************************//**
* @brief
* Enables or disables LCD Animation feature
@ -327,17 +372,13 @@ __STATIC_INLINE void LCD_Enable(bool enable)
******************************************************************************/
__STATIC_INLINE void LCD_AnimEnable(bool enable)
{
if (enable)
{
if (enable) {
LCD->BACTRL |= LCD_BACTRL_AEN;
}
else
{
} else {
LCD->BACTRL &= ~LCD_BACTRL_AEN;
}
}
/***************************************************************************//**
* @brief
* Enables or disables LCD blink
@ -347,17 +388,13 @@ __STATIC_INLINE void LCD_AnimEnable(bool enable)
******************************************************************************/
__STATIC_INLINE void LCD_BlinkEnable(bool enable)
{
if (enable)
{
if (enable) {
LCD->BACTRL |= LCD_BACTRL_BLINKEN;
}
else
{
} else {
LCD->BACTRL &= ~LCD_BACTRL_BLINKEN;
}
}
/***************************************************************************//**
* @brief
* Disables all segments, while keeping segment state
@ -367,17 +404,13 @@ __STATIC_INLINE void LCD_BlinkEnable(bool enable)
******************************************************************************/
__STATIC_INLINE void LCD_BlankEnable(bool enable)
{
if (enable)
{
if (enable) {
LCD->BACTRL |= LCD_BACTRL_BLANK;
}
else
{
} else {
LCD->BACTRL &= ~LCD_BACTRL_BLANK;
}
}
/***************************************************************************//**
* @brief
* Enables or disables LCD Frame Control
@ -387,17 +420,13 @@ __STATIC_INLINE void LCD_BlankEnable(bool enable)
******************************************************************************/
__STATIC_INLINE void LCD_FrameCountEnable(bool enable)
{
if (enable)
{
if (enable) {
LCD->BACTRL |= LCD_BACTRL_FCEN;
}
else
{
} else {
LCD->BACTRL &= ~LCD_BACTRL_FCEN;
}
}
/***************************************************************************//**
* @brief
* Returns current animation state
@ -410,7 +439,6 @@ __STATIC_INLINE int LCD_AnimState(void)
return (int)(LCD->STATUS & _LCD_STATUS_ASTATE_MASK) >> _LCD_STATUS_ASTATE_SHIFT;
}
/***************************************************************************//**
* @brief
* Returns current blink state
@ -423,7 +451,6 @@ __STATIC_INLINE int LCD_BlinkState(void)
return (int)(LCD->STATUS & _LCD_STATUS_BLINK_MASK) >> _LCD_STATUS_BLINK_SHIFT;
}
/***************************************************************************//**
* @brief
* When set, LCD registers will not be updated until cleared,
@ -434,17 +461,13 @@ __STATIC_INLINE int LCD_BlinkState(void)
******************************************************************************/
__STATIC_INLINE void LCD_FreezeEnable(bool enable)
{
if (enable)
{
if (enable) {
LCD->FREEZE = LCD_FREEZE_REGFREEZE_FREEZE;
}
else
{
} else {
LCD->FREEZE = LCD_FREEZE_REGFREEZE_UPDATE;
}
}
/***************************************************************************//**
* @brief
* Returns SYNCBUSY bits, indicating which registers have pending updates
@ -457,7 +480,6 @@ __STATIC_INLINE uint32_t LCD_SyncBusyGet(void)
return LCD->SYNCBUSY;
}
/***************************************************************************//**
* @brief
* Polls LCD SYNCBUSY flags, until flag has been cleared
@ -471,7 +493,6 @@ __STATIC_INLINE void LCD_SyncBusyDelay(uint32_t flags)
;
}
/***************************************************************************//**
* @brief
* Get pending LCD interrupt flags
@ -485,7 +506,6 @@ __STATIC_INLINE uint32_t LCD_IntGet(void)
return LCD->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending LCD interrupt flags.
@ -516,7 +536,6 @@ __STATIC_INLINE uint32_t LCD_IntGetEnabled(void)
return LCD->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending LCD interrupts from SW.
@ -531,7 +550,6 @@ __STATIC_INLINE void LCD_IntSet(uint32_t flags)
LCD->IFS = flags;
}
/***************************************************************************//**
* @brief
* Enable LCD interrupts
@ -546,7 +564,6 @@ __STATIC_INLINE void LCD_IntEnable(uint32_t flags)
LCD->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Disable LCD interrupts
@ -561,7 +578,6 @@ __STATIC_INLINE void LCD_IntDisable(uint32_t flags)
LCD->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Clear one or more interrupt flags
@ -576,7 +592,6 @@ __STATIC_INLINE void LCD_IntClear(uint32_t flags)
LCD->IFC = flags;
}
#if defined(LCD_CTRL_DSC)
/***************************************************************************//**
* @brief
@ -589,12 +604,9 @@ __STATIC_INLINE void LCD_IntClear(uint32_t flags)
******************************************************************************/
__STATIC_INLINE void LCD_DSCEnable(bool enable)
{
if (enable)
{
if (enable) {
LCD->CTRL |= LCD_CTRL_DSC;
}
else
{
} else {
LCD->CTRL &= ~LCD_CTRL_DSC;
}
}

238
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ldma.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_ldma.h
* @brief Direct memory access (LDMA) API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -43,7 +43,6 @@
extern "C" {
#endif
/***************************************************************************//**
* @addtogroup emlib
* @{
@ -132,8 +131,7 @@ extern "C" {
* This value controls the number of unit data transfers per arbitration
* cycle, providing a means to balance DMA channels' load on the controller.
*/
typedef enum
{
typedef enum {
ldmaCtrlBlockSizeUnit1 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1, /**< One transfer per arbitration. */
ldmaCtrlBlockSizeUnit2 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT2, /**< Two transfers per arbitration. */
ldmaCtrlBlockSizeUnit3 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT3, /**< Three transfers per arbitration. */
@ -151,23 +149,20 @@ typedef enum
} LDMA_CtrlBlockSize_t;
/** DMA structure type. */
typedef enum
{
typedef enum {
ldmaCtrlStructTypeXfer = _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER, /**< TRANSFER transfer type. */
ldmaCtrlStructTypeSync = _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE, /**< SYNCHRONIZE transfer type. */
ldmaCtrlStructTypeWrite = _LDMA_CH_CTRL_STRUCTTYPE_WRITE /**< WRITE transfer type. */
} LDMA_CtrlStructType_t;
/** DMA transfer block or cycle selector. */
typedef enum
{
typedef enum {
ldmaCtrlReqModeBlock = _LDMA_CH_CTRL_REQMODE_BLOCK, /**< Each DMA request trigger transfer of one block. */
ldmaCtrlReqModeAll = _LDMA_CH_CTRL_REQMODE_ALL /**< A DMA request trigger transfer of a complete cycle. */
} LDMA_CtrlReqMode_t;
/** Source address increment unit size. */
typedef enum
{
typedef enum {
ldmaCtrlSrcIncOne = _LDMA_CH_CTRL_SRCINC_ONE, /**< Increment source address by one unit data size. */
ldmaCtrlSrcIncTwo = _LDMA_CH_CTRL_SRCINC_TWO, /**< Increment source address by two unit data sizes. */
ldmaCtrlSrcIncFour = _LDMA_CH_CTRL_SRCINC_FOUR, /**< Increment source address by four unit data sizes. */
@ -175,16 +170,14 @@ typedef enum
} LDMA_CtrlSrcInc_t;
/** DMA transfer unit size. */
typedef enum
{
typedef enum {
ldmaCtrlSizeByte = _LDMA_CH_CTRL_SIZE_BYTE, /**< Each unit transfer is a byte. */
ldmaCtrlSizeHalf = _LDMA_CH_CTRL_SIZE_HALFWORD, /**< Each unit transfer is a half-word. */
ldmaCtrlSizeWord = _LDMA_CH_CTRL_SIZE_WORD /**< Each unit transfer is a word. */
} LDMA_CtrlSize_t;
/** Destination address increment unit size. */
typedef enum
{
typedef enum {
ldmaCtrlDstIncOne = _LDMA_CH_CTRL_DSTINC_ONE, /**< Increment destination address by one unit data size. */
ldmaCtrlDstIncTwo = _LDMA_CH_CTRL_DSTINC_TWO, /**< Increment destination address by two unit data sizes. */
ldmaCtrlDstIncFour = _LDMA_CH_CTRL_DSTINC_FOUR, /**< Increment destination address by four unit data sizes. */
@ -192,29 +185,25 @@ typedef enum
} LDMA_CtrlDstInc_t;
/** Source addressing mode. */
typedef enum
{
typedef enum {
ldmaCtrlSrcAddrModeAbs = _LDMA_CH_CTRL_SRCMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */
ldmaCtrlSrcAddrModeRel = _LDMA_CH_CTRL_SRCMODE_RELATIVE /**< Address fetched from a linked structure is relative. */
} LDMA_CtrlSrcAddrMode_t;
/** Destination addressing mode. */
typedef enum
{
typedef enum {
ldmaCtrlDstAddrModeAbs = _LDMA_CH_CTRL_DSTMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */
ldmaCtrlDstAddrModeRel = _LDMA_CH_CTRL_DSTMODE_RELATIVE /**< Address fetched from a linked structure is relative. */
} LDMA_CtrlDstAddrMode_t;
/** DMA linkload address mode. */
typedef enum
{
typedef enum {
ldmaLinkModeAbs = _LDMA_CH_LINK_LINKMODE_ABSOLUTE, /**< Link address is an absolute address value. */
ldmaLinkModeRel = _LDMA_CH_LINK_LINKMODE_RELATIVE /**< Link address is a two's complement releative address. */
} LDMA_LinkMode_t;
/** Insert extra arbitration slots to increase channel arbitration priority. */
typedef enum
{
typedef enum {
ldmaCfgArbSlotsAs1 = _LDMA_CH_CFG_ARBSLOTS_ONE, /**< One arbitration slot selected. */
ldmaCfgArbSlotsAs2 = _LDMA_CH_CFG_ARBSLOTS_TWO, /**< Two arbitration slots selected. */
ldmaCfgArbSlotsAs4 = _LDMA_CH_CFG_ARBSLOTS_FOUR, /**< Four arbitration slots selected. */
@ -222,22 +211,19 @@ typedef enum
} LDMA_CfgArbSlots_t;
/** Source address increment sign. */
typedef enum
{
typedef enum {
ldmaCfgSrcIncSignPos = _LDMA_CH_CFG_SRCINCSIGN_POSITIVE, /**< Increment source address. */
ldmaCfgSrcIncSignNeg = _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE /**< Decrement source address. */
} LDMA_CfgSrcIncSign_t;
/** Destination address increment sign. */
typedef enum
{
typedef enum {
ldmaCfgDstIncSignPos = _LDMA_CH_CFG_DSTINCSIGN_POSITIVE, /**< Increment destination address. */
ldmaCfgDstIncSignNeg = _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE /**< Decrement destination address. */
} LDMA_CfgDstIncSign_t;
/** Peripherals that can trigger LDMA transfers. */
typedef enum
{
typedef enum {
ldmaPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering.
#if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SCAN)
ldmaPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SCAN.
@ -245,6 +231,12 @@ typedef enum
#if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE)
ldmaPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SINGLE.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SCAN)
ldmaPeripheralSignal_ADC1_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC1SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trig on ADC1_SCAN.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE)
ldmaPeripheralSignal_ADC1_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trig on ADC1_SINGLE.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD)
ldmaPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0RD.
#endif
@ -296,6 +288,24 @@ typedef enum
#if defined(LDMA_CH_REQSEL_SIGSEL_CSENDATA)
ldmaPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trig on CSEN_DATA.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY)
ldmaPeripheralSignal_EBI_PXL0EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXL0EMPTY.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY)
ldmaPeripheralSignal_EBI_PXL1EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXL1EMPTY.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL)
ldmaPeripheralSignal_EBI_PXLFULL = LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXLFULL.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY)
ldmaPeripheralSignal_EBI_DDEMPTY = LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_DDEMPTY.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_EBIVSYNC)
ldmaPeripheralSignal_EBI_VSYNC = LDMA_CH_REQSEL_SIGSEL_EBIVSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_VSYNC.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_EBIHSYNC)
ldmaPeripheralSignal_EBI_HSYNC = LDMA_CH_REQSEL_SIGSEL_EBIHSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_HSYNC.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV)
ldmaPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_RXDATAV.
#endif
@ -308,6 +318,12 @@ typedef enum
#if defined(LDMA_CH_REQSEL_SIGSEL_I2C1TXBL)
ldmaPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trig on I2C1_TXBL.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV)
ldmaPeripheralSignal_I2C2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trig on I2C2_RXDATAV.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_I2C2TXBL)
ldmaPeripheralSignal_I2C2_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C2TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trig on I2C2_TXBL.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV)
ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE, ///< Trig on LESENSE_BUFDATAV.
#endif
@ -320,6 +336,15 @@ typedef enum
#if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY)
ldmaPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXEMPTY.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV)
ldmaPeripheralSignal_LEUART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_RXDATAV.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL)
ldmaPeripheralSignal_LEUART1_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_TXBL.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY)
ldmaPeripheralSignal_LEUART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_TXEMPTY.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_MSCWDATA)
ldmaPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trig on MSC_WDATA.
#endif
@ -356,6 +381,84 @@ typedef enum
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF)
ldmaPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_UFOF.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC0)
ldmaPeripheralSignal_TIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC0.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC1)
ldmaPeripheralSignal_TIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC1.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC2)
ldmaPeripheralSignal_TIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC2.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF)
ldmaPeripheralSignal_TIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_UFOF.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC0)
ldmaPeripheralSignal_TIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC0.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC1)
ldmaPeripheralSignal_TIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC1.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC2)
ldmaPeripheralSignal_TIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC2.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF)
ldmaPeripheralSignal_TIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_UFOF.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC0)
ldmaPeripheralSignal_TIMER4_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC0.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC1)
ldmaPeripheralSignal_TIMER4_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC1.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC2)
ldmaPeripheralSignal_TIMER4_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC2.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF)
ldmaPeripheralSignal_TIMER4_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_UFOF.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC0)
ldmaPeripheralSignal_TIMER5_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC0.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC1)
ldmaPeripheralSignal_TIMER5_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC1.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC2)
ldmaPeripheralSignal_TIMER5_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC2.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF)
ldmaPeripheralSignal_TIMER5_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_UFOF.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC0)
ldmaPeripheralSignal_TIMER6_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC0.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC1)
ldmaPeripheralSignal_TIMER6_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC1.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC2)
ldmaPeripheralSignal_TIMER6_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC2.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF)
ldmaPeripheralSignal_TIMER6_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_UFOF.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV)
ldmaPeripheralSignal_UART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_RXDATAV.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXBL)
ldmaPeripheralSignal_UART0_TXBL = LDMA_CH_REQSEL_SIGSEL_UART0TXBL | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_TXBL.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY)
ldmaPeripheralSignal_UART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_TXEMPTY.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV)
ldmaPeripheralSignal_UART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trig on UART1_RXDATAV.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXBL)
ldmaPeripheralSignal_UART1_TXBL = LDMA_CH_REQSEL_SIGSEL_UART1TXBL | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trig on UART1_TXBL.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY)
ldmaPeripheralSignal_UART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trig on UART1_TXEMPTY.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV)
ldmaPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_RXDATAV.
#endif
@ -404,6 +507,30 @@ typedef enum
#if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY)
ldmaPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXEMPTY.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV)
ldmaPeripheralSignal_USART4_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_RXDATAV.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT)
ldmaPeripheralSignal_USART4_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_RXDATAVRIGHT.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBL)
ldmaPeripheralSignal_USART4_TXBL = LDMA_CH_REQSEL_SIGSEL_USART4TXBL | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXBL.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT)
ldmaPeripheralSignal_USART4_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXBLRIGHT.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY)
ldmaPeripheralSignal_USART4_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXEMPTY.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV)
ldmaPeripheralSignal_USART5_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_RXDATAV.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBL)
ldmaPeripheralSignal_USART5_TXBL = LDMA_CH_REQSEL_SIGSEL_USART5TXBL | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_TXBL.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY)
ldmaPeripheralSignal_USART5_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_TXEMPTY.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH0)
ldmaPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trig on VDAC0_CH0.
#endif
@ -435,11 +562,34 @@ typedef enum
ldmaPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC3.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF)
ldmaPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1 ///< Trig on WTIMER1_UFOF.
ldmaPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_UFOF.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0)
ldmaPeripheralSignal_WTIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC0.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1)
ldmaPeripheralSignal_WTIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC1.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2)
ldmaPeripheralSignal_WTIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC2.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF)
ldmaPeripheralSignal_WTIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_UFOF.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0)
ldmaPeripheralSignal_WTIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC0.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1)
ldmaPeripheralSignal_WTIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC1.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2)
ldmaPeripheralSignal_WTIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC2.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF)
ldmaPeripheralSignal_WTIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_UFOF.
#endif
} LDMA_PeripheralSignal_t;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
@ -453,14 +603,12 @@ typedef enum
* given DMA channel. The three descriptor types are XFER, SYNC and WRI.
* Refer to the reference manual for further information.
*/
typedef union
{
typedef union {
/**
* TRANSFER DMA descriptor, this is the only descriptor type which can be
* used to start a DMA transfer.
*/
struct
{
struct {
uint32_t structType : 2; /**< Set to 0 to select XFER descriptor type. */
uint32_t reserved0 : 1;
uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */
@ -488,8 +636,7 @@ typedef union
/** SYNCHRONIZE DMA descriptor, used for intra channel transfer
* syncronization.
*/
struct
{
struct {
uint32_t structType : 2; /**< Set to 1 to select SYNC descriptor type. */
uint32_t reserved0 : 1;
uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */
@ -519,8 +666,7 @@ typedef union
} sync;
/** WRITE DMA descriptor, used for write immediate operations. */
struct
{
struct {
uint32_t structType : 2; /**< Set to 2 to select WRITE descriptor type.*/
uint32_t reserved0 : 1;
uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */
@ -547,8 +693,7 @@ typedef union
} LDMA_Descriptor_t;
/** @brief LDMA initialization configuration structure. */
typedef struct
{
typedef struct {
uint8_t ldmaInitCtrlNumFixed; /**< Arbitration mode separator.*/
uint8_t ldmaInitCtrlSyncPrsClrEn; /**< PRS Synctrig clear enable. */
uint8_t ldmaInitCtrlSyncPrsSetEn; /**< PRS Synctrig set enable. */
@ -561,8 +706,7 @@ typedef struct
* @details
* This struct configures all aspects of a DMA transfer.
*/
typedef struct
{
typedef struct {
uint32_t ldmaReqSel; /**< Selects DMA trigger source. */
uint8_t ldmaCtrlSyncPrsClrOff; /**< PRS Synctrig clear enables to clear. */
uint8_t ldmaCtrlSyncPrsClrOn; /**< PRS Synctrig clear enables to set. */
@ -576,12 +720,10 @@ typedef struct
uint8_t ldmaLoopCnt; /**< Counter for looped transfers. */
} LDMA_TransferCfg_t;
/*******************************************************************************
************************** STRUCT INITIALIZERS ****************************
******************************************************************************/
/** @brief Default DMA initialization structure. */
#define LDMA_INIT_DEFAULT \
{ \
@ -1394,7 +1536,6 @@ void LDMA_StopTransfer(int ch);
bool LDMA_TransferDone(int ch);
uint32_t LDMA_TransferRemainingCount(int ch);
/***************************************************************************//**
* @brief
* Clear one or more pending LDMA interrupts.
@ -1409,7 +1550,6 @@ __STATIC_INLINE void LDMA_IntClear(uint32_t flags)
LDMA->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more LDMA interrupts.
@ -1424,7 +1564,6 @@ __STATIC_INLINE void LDMA_IntDisable(uint32_t flags)
LDMA->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more LDMA interrupts.
@ -1444,7 +1583,6 @@ __STATIC_INLINE void LDMA_IntEnable(uint32_t flags)
LDMA->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending LDMA interrupt flags.
@ -1462,7 +1600,6 @@ __STATIC_INLINE uint32_t LDMA_IntGet(void)
return LDMA->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending LDMA interrupt flags.
@ -1485,7 +1622,6 @@ __STATIC_INLINE uint32_t LDMA_IntGetEnabled(void)
return LDMA->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending LDMA interrupts

229
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lesense.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_lesense.h
* @brief Low Energy Sensor (LESENSE) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -43,7 +43,6 @@
extern "C" {
#endif
/***************************************************************************//**
* @addtogroup emlib
* @{
@ -68,8 +67,7 @@ extern "C" {
* counter.
* Note: these enumeration values are being used for different clock division
* related configuration parameters (hfPresc, lfPresc, pcPresc). */
typedef enum
{
typedef enum {
lesenseClkDiv_1 = 0, /**< Divide clock by 1. */
lesenseClkDiv_2 = 1, /**< Divide clock by 2. */
lesenseClkDiv_4 = 2, /**< Divide clock by 4. */
@ -80,10 +78,8 @@ typedef enum
lesenseClkDiv_128 = 7 /**< Divide clock by 128. */
} LESENSE_ClkPresc_TypeDef;
/** Scan modes. */
typedef enum
{
typedef enum {
/** New scan is started each time the period counter overflows. */
lesenseScanStartPeriodic = LESENSE_CTRL_SCANMODE_PERIODIC,
@ -94,12 +90,10 @@ typedef enum
lesenseScanStartPRS = LESENSE_CTRL_SCANMODE_PRS
} LESENSE_ScanMode_TypeDef;
/** PRS sources.
* Note: these enumeration values are being used for different PRS related
* configuration parameters. */
typedef enum
{
typedef enum {
lesensePRSCh0 = 0, /**< PRS channel 0. */
lesensePRSCh1 = 1, /**< PRS channel 1. */
lesensePRSCh2 = 2, /**< PRS channel 2. */
@ -130,10 +124,8 @@ typedef enum
#endif
} LESENSE_PRSSel_TypeDef;
/** Locations of the alternate excitation function. */
typedef enum
{
typedef enum {
/** Alternate excitation is mapped to the LES_ALTEX pins. */
lesenseAltExMapALTEX = _LESENSE_CTRL_ALTEXMAP_ALTEX,
@ -149,10 +141,8 @@ typedef enum
#endif
} LESENSE_AltExMap_TypeDef;
/** Result buffer interrupt and DMA trigger levels. */
typedef enum
{
typedef enum {
/** DMA and interrupt flags are set when result buffer is halffull. */
lesenseBufTrigHalf = LESENSE_CTRL_BUFIDL_HALFFULL,
@ -160,10 +150,8 @@ typedef enum
lesenseBufTrigFull = LESENSE_CTRL_BUFIDL_FULL
} LESENSE_BufTrigLevel_TypeDef;
/** Modes of operation for DMA wakeup from EM2. */
typedef enum
{
typedef enum {
/** No DMA wakeup from EM2. */
lesenseDMAWakeUpDisable = LESENSE_CTRL_DMAWU_DISABLE,
@ -176,10 +164,8 @@ typedef enum
lesenseDMAWakeUpBufLevel = LESENSE_CTRL_DMAWU_BUFLEVEL
} LESENSE_DMAWakeUp_TypeDef;
/** Bias modes. */
typedef enum
{
typedef enum {
/** Duty cycle bias module between low power and high accuracy mode. */
lesenseBiasModeDutyCycle = LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE,
@ -190,10 +176,8 @@ typedef enum
lesenseBiasModeDontTouch = LESENSE_BIASCTRL_BIASMODE_DONTTOUCH
} LESENSE_BiasMode_TypeDef;
/** Scan configuration. */
typedef enum
{
typedef enum {
/** The channel configuration registers (CHx_CONF) used are directly mapped to
* the channel number. */
lesenseScanConfDirMap = LESENSE_CTRL_SCANCONF_DIRMAP,
@ -211,10 +195,8 @@ typedef enum
lesenseScanConfDecDef = LESENSE_CTRL_SCANCONF_DECDEF
} LESENSE_ScanConfSel_TypeDef;
/** DAC CHx data control configuration. */
typedef enum
{
typedef enum {
/** DAC channel x data is defined by DAC_CHxDATA register.
* Note: this value could be used for both DAC Ch0 and Ch1. */
lesenseDACIfData = _LESENSE_PERCTRL_DACCH0DATA_DACDATA,
@ -234,8 +216,7 @@ typedef enum
#if defined(_LESENSE_PERCTRL_DACCH0CONV_MASK)
/** DAC channel x conversion mode configuration. */
typedef enum
{
typedef enum {
/** LESENSE doesn't control DAC channel x.
* Note: this value could be used for both DAC Ch0 and Ch1. */
lesenseDACConvModeDisable = _LESENSE_PERCTRL_DACCH0CONV_DISABLE,
@ -256,8 +237,7 @@ typedef enum
#if defined(_LESENSE_PERCTRL_DACCH0OUT_MASK)
/** DAC channel x output mode configuration. */
typedef enum
{
typedef enum {
/** DAC CHx output to pin and ACMP/ADC disabled.
* Note: this value could be used for both DAC Ch0 and Ch1. */
lesenseDACOutModeDisable = _LESENSE_PERCTRL_DACCH0OUT_DISABLE,
@ -276,11 +256,9 @@ typedef enum
} LESENSE_ControlDACOut_TypeDef;
#endif
#if defined(_LESENSE_PERCTRL_DACREF_MASK)
/** DAC reference configuration. */
typedef enum
{
typedef enum {
/** DAC uses VDD reference. */
lesenseDACRefVdd = LESENSE_PERCTRL_DACREF_VDD,
@ -289,10 +267,8 @@ typedef enum
} LESENSE_DACRef_TypeDef;
#endif
/** ACMPx control configuration. */
typedef enum
{
typedef enum {
/** LESENSE does not control the ACMPx.
* Note: this value could be used for both ACMP0 and ACMP1. */
lesenseACMPModeDisable = _LESENSE_PERCTRL_ACMP0MODE_DISABLE,
@ -306,10 +282,8 @@ typedef enum
lesenseACMPModeMuxThres = _LESENSE_PERCTRL_ACMP0MODE_MUXTHRES
} LESENSE_ControlACMP_TypeDef;
/** Warm up modes. ACMP and DAC duty cycle mode configuration. */
typedef enum
{
typedef enum {
/** ACMPs and DACs are shut down when LESENSE is idle. */
lesenseWarmupModeNormal = LESENSE_PERCTRL_WARMUPMODE_NORMAL,
@ -323,10 +297,8 @@ typedef enum
lesenseWarmupModeKeepWarm = LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM
} LESENSE_WarmupMode_TypeDef;
/** Decoder input source configuration. */
typedef enum
{
typedef enum {
/** The SENSORSTATE register is used as input to the decoder. */
lesenseDecInputSensorSt = LESENSE_DECCTRL_INPUT_SENSORSTATE,
@ -334,10 +306,8 @@ typedef enum
lesenseDecInputPRS = LESENSE_DECCTRL_INPUT_PRS
} LESENSE_DecInput_TypeDef;
/** Compare source selection for sensor sampling. */
typedef enum
{
typedef enum {
/** Counter output will be used in comparison. */
lesenseSampleModeCounter = 0x0 << _LESENSE_CH_INTERACT_SAMPLE_SHIFT,
@ -353,10 +323,8 @@ typedef enum
#endif
} LESENSE_ChSampleMode_TypeDef;
/** Interrupt generation setup for CHx interrupt flag. */
typedef enum
{
typedef enum {
/** No interrupt is generated. */
lesenseSetIntNone = LESENSE_CH_INTERACT_SETIF_NONE,
@ -370,10 +338,8 @@ typedef enum
lesenseSetIntNegEdge = LESENSE_CH_INTERACT_SETIF_NEGEDGE
} LESENSE_ChIntMode_TypeDef;
/** Channel pin mode for the excitation phase of the scan sequence. */
typedef enum
{
typedef enum {
/** Channel pin is disabled. */
lesenseChPinExDis = LESENSE_CH_INTERACT_EXMODE_DISABLE,
@ -387,10 +353,8 @@ typedef enum
lesenseChPinExDACOut = LESENSE_CH_INTERACT_EXMODE_DACOUT
} LESENSE_ChPinExMode_TypeDef;
/** Channel pin mode for the idle phase of the scan sequence. */
typedef enum
{
typedef enum {
/** Channel pin is disabled in idle phase.
* Note: this value could be used for all channels. */
lesenseChPinIdleDis = _LESENSE_IDLECONF_CH0_DISABLE,
@ -418,10 +382,8 @@ typedef enum
#endif
} LESENSE_ChPinIdleMode_TypeDef;
/** Clock used for excitation and sample delay timing. */
typedef enum
{
typedef enum {
/** LFACLK (LF clock) is used. */
lesenseClkLF = _LESENSE_CH_INTERACT_EXCLK_LFACLK,
@ -429,10 +391,8 @@ typedef enum
lesenseClkHF = _LESENSE_CH_INTERACT_EXCLK_AUXHFRCO
} LESENSE_ChClk_TypeDef;
/** Compare modes for counter comparison. */
typedef enum
{
typedef enum {
/** Comparison evaluates to 1 if the sensor data is less than the counter
* threshold, or if the ACMP output is 0. */
lesenseCompModeLess = LESENSE_CH_EVAL_COMP_LESS,
@ -442,11 +402,9 @@ typedef enum
lesenseCompModeGreaterOrEq = LESENSE_CH_EVAL_COMP_GE
} LESENSE_ChCompMode_TypeDef;
#if defined(_LESENSE_CH_EVAL_MODE_MASK)
/** Sensor evaluation modes. */
typedef enum
{
typedef enum {
/** Threshold comparison evaluation mode. In this mode the sensor data
* is compared to the configured threshold value. Two possible comparison
* operators can be used on the sensor data, either >= (GE) or < (LT).
@ -469,10 +427,8 @@ typedef enum
} LESENSE_ChEvalMode_TypeDef;
#endif
/** Idle phase configuration of alternate excitation channels. */
typedef enum
{
typedef enum {
/** ALTEX output is disabled in idle phase.
* Note: this value could be used for all alternate excitation channels. */
lesenseAltExPinIdleDis = _LESENSE_ALTEXCONF_IDLECONF0_DISABLE,
@ -486,10 +442,8 @@ typedef enum
lesenseAltExPinIdleLow = _LESENSE_ALTEXCONF_IDLECONF0_LOW
} LESENSE_AltExPinIdle_TypeDef;
/** Transition action modes. */
typedef enum
{
typedef enum {
/** No PRS pulses generated (if PRSCOUNT == 0).
* Do not count (if PRSCOUNT == 1). */
lesenseTransActNone = LESENSE_ST_TCONFA_PRSACT_NONE,
@ -528,14 +482,12 @@ typedef enum
lesenseTransActDownAndPRS2 = LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2
} LESENSE_StTransAct_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** Core control (LESENSE_CTRL) descriptor structure. */
typedef struct
{
typedef struct {
/** Select scan start mode to control how the scan start is being triggered.*/
LESENSE_ScanMode_TypeDef scanStart;
@ -593,8 +545,7 @@ typedef struct
}
/** LESENSE timing control descriptor structure. */
typedef struct
{
typedef struct {
/** Set the number of LFACLK cycles to delay sensor interaction on
* each channel. Valid range: 0-3 (2 bit). */
uint8_t startDelay;
@ -613,17 +564,17 @@ typedef struct
false /* Don't delay the AUXHFRCO startup. */ \
}
/** LESENSE peripheral control descriptor structure. */
typedef struct
{
typedef struct {
/** Configure DAC channel 0 data control. */
LESENSE_ControlDACData_TypeDef dacCh0Data;
#if defined(_LESENSE_PERCTRL_DACCH0CONV_MASK)
/** Configure how LESENSE controls conversion on DAC channel 0. */
LESENSE_ControlDACConv_TypeDef dacCh0ConvMode;
#endif
#if defined(_LESENSE_PERCTRL_DACCH0OUT_MASK)
/** Configure how LESENSE controls output on DAC channel 0. */
LESENSE_ControlDACOut_TypeDef dacCh0OutMode;
#endif
@ -634,7 +585,9 @@ typedef struct
#if defined(_LESENSE_PERCTRL_DACCH1CONV_MASK)
/** Configure how LESENSE controls conversion on DAC channel 1. */
LESENSE_ControlDACConv_TypeDef dacCh1ConvMode;
#endif
#if defined(_LESENSE_PERCTRL_DACCH1OUT_MASK)
/** Configure how LESENSE controls output on DAC channel 1. */
LESENSE_ControlDACOut_TypeDef dacCh1OutMode;
#endif
@ -665,6 +618,22 @@ typedef struct
* set to false the DAC is enabled before every channel measurement. */
bool dacScan;
#endif
#if defined(_LESENSE_PERCTRL_DACSTARTUP_MASK)
/** When set to true the DAC is started a half clock cycle before sensor
* interaction starts. When set to false, a full clock cycle is used. */
bool dacStartupHalf;
#endif
#if defined(_LESENSE_PERCTRL_DACCH0EN_MASK)
/** When set to true, LESENSE controls DAC channel 0. */
bool dacCh0En;
#endif
#if defined(_LESENSE_PERCTRL_DACCH1EN_MASK)
/** When set to true, LESENSE controls DAC channel 1. */
bool dacCh1En;
#endif
} LESENSE_PerCtrlDesc_TypeDef;
/** Default configuration for LESENSE_PerCtrl_TypeDef structure. */
@ -681,7 +650,7 @@ typedef struct
lesenseDACRefVdd, /* DAC uses VDD reference. */ \
lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP0. */ \
lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP1. */ \
lesenseWarmupModeKeepWarm, /* Keep both ACMPs and the DAC powered up when LESENSE is idle. */ \
lesenseWarmupModeKeepWarm /* Keep both ACMPs and the DAC powered up when LESENSE is idle. */ \
}
#else
#define LESENSE_PERCTRL_DESC_DEFAULT \
@ -691,13 +660,15 @@ typedef struct
lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP0. */ \
lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP1. */ \
lesenseWarmupModeKeepWarm,/* Keep both ACMPs and the DAC powered up when LESENSE is idle. */ \
false, /* DAC is enable for before every channel measurement. */ \
false, /* DAC is enabled for before every channel measurement. */ \
false, /* DAC is enabled a full clock cycle before sensor interaction */ \
false, /* LESENSE does not control DAC channel 0. */ \
false /* LESENSE does not control DAC channel 1. */ \
}
#endif
/** LESENSE decoder control descriptor structure. */
typedef struct
{
typedef struct {
/** Select the input to the LESENSE decoder. */
LESENSE_DecInput_TypeDef decInput;
@ -763,10 +734,8 @@ typedef struct
lesensePRSCh3, /* PRS Channel 3 as input for bit 3 of the LESENSE decoder. */ \
}
/** LESENSE module initialization structure. */
typedef struct
{
typedef struct {
/** LESENSE core configuration parameters. */
LESENSE_CoreCtrlDesc_TypeDef coreCtrl;
@ -789,10 +758,8 @@ typedef struct
.decCtrl = LESENSE_DECCTRL_DESC_DEFAULT /* Default decoder control parameters. */ \
}
/** Channel descriptor structure. */
typedef struct
{
typedef struct {
/** Set to enable scan channel CHx. */
bool enaScanCh;
@ -873,13 +840,10 @@ typedef struct
/** Select sensor evaluation mode. */
LESENSE_ChEvalMode_TypeDef evalMode;
#endif
} LESENSE_ChDesc_TypeDef;
/** Configuration structure for all scan channels. */
typedef struct
{
typedef struct {
/** Channel descriptor for all LESENSE channels. */
LESENSE_ChDesc_TypeDef Ch[LESENSE_NUM_CHANNELS];
} LESENSE_ChAll_TypeDef;
@ -888,53 +852,52 @@ typedef struct
#if defined(_LESENSE_CH_EVAL_MODE_MASK)
#define LESENSE_CH_CONF_DEFAULT \
{ \
true, /* Enable scan channel. */ \
true, /* Enable the assigned pin on scan channel. */ \
true, /* Enable interrupts on channel. */ \
lesenseChPinExHigh, /* Channel pin is high during the excitation period. */ \
lesenseChPinIdleLow, /* Channel pin is low during the idle period. */ \
false, /* Disable scan channel. */ \
false, /* Disable the assigned pin on scan channel. */ \
false, /* Disable interrupts on channel. */ \
lesenseChPinExDis, /* Channel pin is disabled during the excitation period. */ \
lesenseChPinIdleDis, /* Channel pin is disabled during the idle period. */ \
false, /* Don't use alternate excitation pins for excitation. */ \
false, /* Disabled to shift results from this channel to the decoder register. */ \
false, /* Disabled to invert the scan result bit. */ \
false, /* Disabled to store counter value in the result buffer. */ \
lesenseClkLF, /* Use the LF clock for excitation timing. */ \
lesenseClkLF, /* Use the LF clock for sample timing. */ \
0x03U, /* Excitation time is set to 3(+1) excitation clock cycles. */ \
0x09U, /* Sample delay is set to 9(+1) sample clock cycles. */ \
0x06U, /* Measure delay is set to 6 excitation clock cycles.*/ \
0x00U, /* Excitation time is set to 0(+1) excitation clock cycles. */ \
0x00U, /* Sample delay is set to 0(+1) sample clock cycles. */ \
0x00U, /* Measure delay is set to 0 excitation clock cycles.*/ \
0x00U, /* ACMP threshold has been set to 0. */ \
lesenseSampleModeACMP, /* ACMP output will be used in comparison. */ \
lesenseSetIntNone, /* No interrupt is generated by the channel. */ \
0xFFU, /* Counter threshold has bee set to 0xFF. */ \
0x00U, /* Counter threshold has bee set to 0x00. */ \
lesenseCompModeLess, /* Compare mode has been set to trigger interrupt on "less". */ \
lesenseEvalModeThreshold /* Compare mode has been set to trigger interrupt on "less". */ \
lesenseEvalModeThreshold /* Eval mode has been set to trigger interrupt on threshold. */ \
}
#else
#define LESENSE_CH_CONF_DEFAULT \
{ \
true, /* Enable scan channel. */ \
true, /* Enable the assigned pin on scan channel. */ \
true, /* Enable interrupts on channel. */ \
lesenseChPinExHigh, /* Channel pin is high during the excitation period. */ \
lesenseChPinIdleLow, /* Channel pin is low during the idle period. */ \
false, /* Disable scan channel. */ \
false, /* Disable the assigned pin on scan channel. */ \
false, /* Disable interrupts on channel. */ \
lesenseChPinExDis, /* Channel pin is disabled during the excitation period. */ \
lesenseChPinIdleDis, /* Channel pin is disabled during the idle period. */ \
false, /* Don't use alternate excitation pins for excitation. */ \
false, /* Disabled to shift results from this channel to the decoder register. */ \
false, /* Disabled to invert the scan result bit. */ \
false, /* Disabled to store counter value in the result buffer. */ \
lesenseClkLF, /* Use the LF clock for excitation timing. */ \
lesenseClkLF, /* Use the LF clock for sample timing. */ \
0x03U, /* Excitation time is set to 3(+1) excitation clock cycles. */ \
0x09U, /* Sample delay is set to 9(+1) sample clock cycles. */ \
0x06U, /* Measure delay is set to 6 excitation clock cycles.*/ \
0x00U, /* Excitation time is set to 0(+1) excitation clock cycles. */ \
0x00U, /* Sample delay is set to 0(+1) sample clock cycles. */ \
0x00U, /* Measure delay is set to 0 excitation clock cycles.*/ \
0x00U, /* ACMP threshold has been set to 0. */ \
lesenseSampleModeACMP, /* ACMP output will be used in comparison. */ \
lesenseSetIntNone, /* No interrupt is generated by the channel. */ \
0xFFU, /* Counter threshold has bee set to 0xFF. */ \
0x00U, /* Counter threshold has bee set to 0x00. */ \
lesenseCompModeLess /* Compare mode has been set to trigger interrupt on "less". */ \
}
#endif
/** Default configuration for all sensor channels. */
#define LESENSE_SCAN_CONF_DEFAULT \
{ \
@ -958,10 +921,8 @@ typedef struct
} \
}
/** Alternate excitation descriptor structure. */
typedef struct
{
typedef struct {
/** Configure alternate excitation pins. If set, the corresponding alternate
* excitation pin/signal is enabled. */
bool enablePin;
@ -980,10 +941,8 @@ typedef struct
bool alwaysEx;
} LESENSE_AltExDesc_TypeDef;
/** Configuration structure for alternate excitation. */
typedef struct
{
typedef struct {
/** Select alternate excitation mapping. */
LESENSE_AltExMap_TypeDef altExMap;
@ -1000,14 +959,12 @@ typedef struct
* LESENSE_AltExDesc_TypeDef structure for details regarding which parameters
* are valid. */
LESENSE_AltExDesc_TypeDef AltEx[16];
} LESENSE_ConfAltEx_TypeDef;
/** Default configuration for alternate excitation channel. */
#define LESENSE_ALTEX_CH_CONF_DEFAULT \
{ \
true, /* Alternate excitation enabled.*/ \
false, /* Alternate excitation disabled.*/ \
lesenseAltExPinIdleDis,/* Alternate excitation pin is disabled in idle. */ \
false /* Excite only for corresponding channel. */ \
}
@ -1062,8 +1019,7 @@ typedef struct
#endif
/** Decoder state condition descriptor structure. */
typedef struct
{
typedef struct {
/** Configure compare value. State transition is triggered when sensor state
* equals to this value. Valid range: 0-15 (4 bits). */
uint8_t compVal;
@ -1095,10 +1051,8 @@ typedef struct
false /* No interrupt triggered on compare match. */ \
}
/** Decoder state x configuration structure. */
typedef struct
{
typedef struct {
/** If enabled, the state descriptor pair in the next location will also be
* evaluated. */
bool chainDesc;
@ -1112,10 +1066,8 @@ typedef struct
LESENSE_DecStCond_TypeDef confB;
} LESENSE_DecStDesc_TypeDef;
/** Configuration structure for the decoder. */
typedef struct
{
typedef struct {
/** Descriptor of the 16 or 32 decoder states depending on the device. */
LESENSE_DecStDesc_TypeDef St[LESENSE_NUM_DECODER_STATES];
} LESENSE_DecStAll_TypeDef;
@ -1236,7 +1188,6 @@ void LESENSE_ScanStop(void);
void LESENSE_DecoderStart(void);
void LESENSE_ResultBufferClear(void);
/***************************************************************************//**
* @brief
* Stop LESENSE decoder.
@ -1251,7 +1202,6 @@ __STATIC_INLINE void LESENSE_DecoderStop(void)
LESENSE->DECCTRL |= LESENSE_DECCTRL_DISABLE;
}
/***************************************************************************//**
* @brief
* Get the current status of LESENSE.
@ -1271,7 +1221,6 @@ __STATIC_INLINE uint32_t LESENSE_StatusGet(void)
return LESENSE->STATUS;
}
/***************************************************************************//**
* @brief
* Wait until the status of LESENSE is equal to what requested.
@ -1298,7 +1247,6 @@ __STATIC_INLINE void LESENSE_StatusWait(uint32_t flag)
;
}
/***************************************************************************//**
* @brief
* Get the currently active channel index.
@ -1312,7 +1260,6 @@ __STATIC_INLINE uint32_t LESENSE_ChannelActiveGet(void)
return LESENSE->CURCH;
}
/***************************************************************************//**
* @brief
* Get the latest scan comparison result (1 bit / channel).
@ -1329,7 +1276,6 @@ __STATIC_INLINE uint32_t LESENSE_ScanResultGet(void)
return LESENSE->SCANRES & _LESENSE_SCANRES_SCANRES_MASK;
}
/***************************************************************************//**
* @brief
* Get the oldest unread data from the result buffer.
@ -1348,7 +1294,6 @@ __STATIC_INLINE uint32_t LESENSE_ScanResultDataGet(void)
return LESENSE->BUFDATA;
}
/***************************************************************************//**
* @brief
* Get data from the result data buffer.
@ -1383,7 +1328,6 @@ __STATIC_INLINE uint32_t LESENSE_SensorStateGet(void)
return LESENSE->SENSORSTATE;
}
#if defined(LESENSE_POWERDOWN_RAM)
/***************************************************************************//**
* @brief
@ -1404,7 +1348,6 @@ __STATIC_INLINE void LESENSE_RAMPowerDown(void)
}
#endif
/***************************************************************************//**
* @brief
* Clear one or more pending LESENSE interrupts.
@ -1419,7 +1362,6 @@ __STATIC_INLINE void LESENSE_IntClear(uint32_t flags)
LESENSE->IFC = flags;
}
/***************************************************************************//**
* @brief
* Enable one or more LESENSE interrupts.
@ -1434,7 +1376,6 @@ __STATIC_INLINE void LESENSE_IntEnable(uint32_t flags)
LESENSE->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Disable one or more LESENSE interrupts.
@ -1449,7 +1390,6 @@ __STATIC_INLINE void LESENSE_IntDisable(uint32_t flags)
LESENSE->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Set one or more pending LESENSE interrupts from SW.
@ -1464,7 +1404,6 @@ __STATIC_INLINE void LESENSE_IntSet(uint32_t flags)
LESENSE->IFS = flags;
}
/***************************************************************************//**
* @brief
* Get pending LESENSE interrupt flags.
@ -1481,7 +1420,6 @@ __STATIC_INLINE uint32_t LESENSE_IntGet(void)
return LESENSE->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending LESENSE interrupt flags.
@ -1512,7 +1450,6 @@ __STATIC_INLINE uint32_t LESENSE_IntGetEnabled(void)
return LESENSE->IF & tmp;
}
/** @} (end addtogroup LESENSE) */
/** @} (end addtogroup emlib) */

25
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_letimer.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_letimer.h
* @brief Low Energy Timer (LETIMER) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -56,8 +56,7 @@ extern "C" {
******************************************************************************/
/** Repeat mode. */
typedef enum
{
typedef enum {
/** Count until stopped by SW. */
letimerRepeatFree = _LETIMER_CTRL_REPMODE_FREE,
/** Count REP0 times. */
@ -74,10 +73,8 @@ typedef enum
letimerRepeatDouble = _LETIMER_CTRL_REPMODE_DOUBLE
} LETIMER_RepeatMode_TypeDef;
/** Underflow action on output. */
typedef enum
{
typedef enum {
/** No output action. */
letimerUFOANone = _LETIMER_CTRL_UFOA0_NONE,
/** Toggle output when counter underflows. */
@ -93,8 +90,7 @@ typedef enum
******************************************************************************/
/** LETIMER initialization structure. */
typedef struct
{
typedef struct {
bool enable; /**< Start counting when init completed. */
bool debugRun; /**< Counter shall keep running during debug halt. */
#if defined(LETIMER_CTRL_RTCC0TEN)
@ -150,7 +146,6 @@ void LETIMER_CompareSet(LETIMER_TypeDef *letimer,
unsigned int comp,
uint32_t value);
/***************************************************************************//**
* @brief
* Get LETIMER counter value.
@ -166,14 +161,12 @@ __STATIC_INLINE uint32_t LETIMER_CounterGet(LETIMER_TypeDef *letimer)
return(letimer->CNT);
}
void LETIMER_Enable(LETIMER_TypeDef *letimer, bool enable);
#if defined(_LETIMER_FREEZE_MASK)
void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable);
#endif
void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init);
/***************************************************************************//**
* @brief
* Clear one or more pending LETIMER interrupts.
@ -191,7 +184,6 @@ __STATIC_INLINE void LETIMER_IntClear(LETIMER_TypeDef *letimer, uint32_t flags)
letimer->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more LETIMER interrupts.
@ -208,7 +200,6 @@ __STATIC_INLINE void LETIMER_IntDisable(LETIMER_TypeDef *letimer, uint32_t flags
letimer->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more LETIMER interrupts.
@ -230,7 +221,6 @@ __STATIC_INLINE void LETIMER_IntEnable(LETIMER_TypeDef *letimer, uint32_t flags)
letimer->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending LETIMER interrupt flags.
@ -250,7 +240,6 @@ __STATIC_INLINE uint32_t LETIMER_IntGet(LETIMER_TypeDef *letimer)
return letimer->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending LETIMER interrupt flags.
@ -276,7 +265,6 @@ __STATIC_INLINE uint32_t LETIMER_IntGetEnabled(LETIMER_TypeDef *letimer)
{
uint32_t ien;
/* Store flags in temporary variable in order to define explicit order
* of volatile accesses. */
ien = letimer->IEN;
@ -285,7 +273,6 @@ __STATIC_INLINE uint32_t LETIMER_IntGetEnabled(LETIMER_TypeDef *letimer)
return letimer->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending LETIMER interrupts from SW.
@ -302,14 +289,12 @@ __STATIC_INLINE void LETIMER_IntSet(LETIMER_TypeDef *letimer, uint32_t flags)
letimer->IFS = flags;
}
uint32_t LETIMER_RepeatGet(LETIMER_TypeDef *letimer, unsigned int rep);
void LETIMER_RepeatSet(LETIMER_TypeDef *letimer,
unsigned int rep,
uint32_t value);
void LETIMER_Reset(LETIMER_TypeDef *letimer);
/** @} (end addtogroup LETIMER) */
/** @} (end addtogroup emlib) */

33
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_leuart.h
View File

@ -2,9 +2,9 @@
* @file em_leuart.h
* @brief Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
* peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -58,16 +58,13 @@ extern "C" {
******************************************************************************/
/** Databit selection. */
typedef enum
{
typedef enum {
leuartDatabits8 = LEUART_CTRL_DATABITS_EIGHT, /**< 8 databits. */
leuartDatabits9 = LEUART_CTRL_DATABITS_NINE /**< 9 databits. */
} LEUART_Databits_TypeDef;
/** Enable selection. */
typedef enum
{
typedef enum {
/** Disable both receiver and transmitter. */
leuartDisable = 0x0,
@ -81,31 +78,25 @@ typedef enum
leuartEnable = (LEUART_CMD_RXEN | LEUART_CMD_TXEN)
} LEUART_Enable_TypeDef;
/** Parity selection. */
typedef enum
{
typedef enum {
leuartNoParity = LEUART_CTRL_PARITY_NONE, /**< No parity. */
leuartEvenParity = LEUART_CTRL_PARITY_EVEN, /**< Even parity. */
leuartOddParity = LEUART_CTRL_PARITY_ODD /**< Odd parity. */
} LEUART_Parity_TypeDef;
/** Stopbits selection. */
typedef enum
{
typedef enum {
leuartStopbits1 = LEUART_CTRL_STOPBITS_ONE, /**< 1 stopbits. */
leuartStopbits2 = LEUART_CTRL_STOPBITS_TWO /**< 2 stopbits. */
} LEUART_Stopbits_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** Init structure. */
typedef struct
{
typedef struct {
/** Specifies whether TX and/or RX shall be enabled when init completed. */
LEUART_Enable_TypeDef enable;
@ -139,7 +130,6 @@ typedef struct
leuartStopbits1 /* 1 stopbit. */ \
}
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
@ -171,7 +161,6 @@ __STATIC_INLINE void LEUART_IntClear(LEUART_TypeDef *leuart, uint32_t flags)
leuart->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more LEUART interrupts.
@ -188,7 +177,6 @@ __STATIC_INLINE void LEUART_IntDisable(LEUART_TypeDef *leuart, uint32_t flags)
leuart->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more LEUART interrupts.
@ -210,7 +198,6 @@ __STATIC_INLINE void LEUART_IntEnable(LEUART_TypeDef *leuart, uint32_t flags)
leuart->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending LEUART interrupt flags.
@ -230,7 +217,6 @@ __STATIC_INLINE uint32_t LEUART_IntGet(LEUART_TypeDef *leuart)
return leuart->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending LEUART interrupt flags.
@ -262,7 +248,6 @@ __STATIC_INLINE uint32_t LEUART_IntGetEnabled(LEUART_TypeDef *leuart)
return leuart->IF & tmp;
}
/***************************************************************************//**
* @brief
* Set one or more pending LEUART interrupts from SW.
@ -279,7 +264,6 @@ __STATIC_INLINE void LEUART_IntSet(LEUART_TypeDef *leuart, uint32_t flags)
leuart->IFS = flags;
}
/***************************************************************************//**
* @brief
* Get LEUART STATUS register.
@ -302,7 +286,6 @@ uint16_t LEUART_RxExt(LEUART_TypeDef *leuart);
void LEUART_Tx(LEUART_TypeDef *leuart, uint8_t data);
void LEUART_TxExt(LEUART_TypeDef *leuart, uint16_t data);
/***************************************************************************//**
* @brief
* Receive one 8 bit frame, (or part of a 9 bit frame).
@ -336,7 +319,6 @@ __STATIC_INLINE uint8_t LEUART_RxDataGet(LEUART_TypeDef *leuart)
return (uint8_t)leuart->RXDATA;
}
/***************************************************************************//**
* @brief
* Receive one 8-9 bit frame, with extended information.
@ -370,7 +352,6 @@ __STATIC_INLINE uint16_t LEUART_RxDataXGet(LEUART_TypeDef *leuart)
return (uint16_t)leuart->RXDATAX;
}
/** @} (end addtogroup LEUART) */
/** @} (end addtogroup emlib) */

25
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_mpu.h
* @brief Memory protection unit (MPU) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -71,8 +71,7 @@ extern "C" {
/**
* Size of an MPU region.
*/
typedef enum
{
typedef enum {
mpuRegionSize32b = 4, /**< 32 byte region size. */
mpuRegionSize64b = 5, /**< 64 byte region size. */
mpuRegionSize128b = 6, /**< 128 byte region size. */
@ -106,8 +105,7 @@ typedef enum
/**
* MPU region access permission attributes.
*/
typedef enum
{
typedef enum {
mpuRegionNoAccess = 0, /**< No access what so ever. */
mpuRegionApPRw = 1, /**< Priviledged state R/W only. */
mpuRegionApPRwURo = 2, /**< Priviledged state R/W, User state R only. */
@ -116,14 +114,12 @@ typedef enum
mpuRegionApPRo_URo = 6 /**< R only in Priviledged and User state. */
} MPU_RegionAp_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** MPU Region init structure. */
typedef struct
{
typedef struct {
bool regionEnable; /**< MPU region enable. */
uint8_t regionNo; /**< MPU region number. */
uint32_t baseAddress; /**< Region baseaddress. */
@ -153,7 +149,6 @@ typedef struct
0 /* No TEX attributes. */ \
}
/** Default configuration of MPU region init structure for sram memory. */
#define MPU_INIT_SRAM_DEFAULT \
{ \
@ -170,7 +165,6 @@ typedef struct
0 /* No TEX attributes. */ \
}
/** Default configuration of MPU region init structure for onchip peripherals.*/
#define MPU_INIT_PERIPHERAL_DEFAULT \
{ \
@ -187,15 +181,12 @@ typedef struct
0 /* No TEX attributes. */ \
}
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
void MPU_ConfigureRegion(const MPU_RegionInit_TypeDef *init);
/***************************************************************************//**
* @brief
* Disable the MPU
@ -204,11 +195,12 @@ void MPU_ConfigureRegion(const MPU_RegionInit_TypeDef *init);
******************************************************************************/
__STATIC_INLINE void MPU_Disable(void)
{
#if defined(SCB_SHCSR_MEMFAULTENA_Msk)
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; /* Disable fault exceptions */
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; /* Disable the MPU */
}
/***************************************************************************//**
* @brief
* Enable the MPU
@ -225,10 +217,11 @@ __STATIC_INLINE void MPU_Enable(uint32_t flags)
| MPU_CTRL_ENABLE_Msk)));
MPU->CTRL = flags | MPU_CTRL_ENABLE_Msk; /* Enable the MPU */
#if defined(SCB_SHCSR_MEMFAULTENA_Msk)
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; /* Enable fault exceptions */
#endif
}
/** @} (end addtogroup MPU) */
/** @} (end addtogroup emlib) */

42
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_msc.h
* @brief Flash controller (MSC) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -130,8 +130,7 @@ extern "C" {
******************************************************************************/
/** Return codes for writing/erasing the flash */
typedef enum
{
typedef enum {
mscReturnOk = 0, /**< Flash write/erase successful. */
mscReturnInvalidAddr = -1, /**< Invalid address. Write to an address that is not flash. */
mscReturnLocked = -2, /**< Flash address is locked. */
@ -139,11 +138,9 @@ typedef enum
mscReturnUnaligned = -4 /**< Unaligned access to flash. */
} MSC_Status_TypeDef;
#if defined(_MSC_READCTRL_BUSSTRATEGY_MASK)
/** Strategy for prioritized bus access */
typedef enum
{
typedef enum {
mscBusStrategyCPU = MSC_READCTRL_BUSSTRATEGY_CPU, /**< Prioritize CPU bus accesses */
mscBusStrategyDMA = MSC_READCTRL_BUSSTRATEGY_DMA, /**< Prioritize DMA bus accesses */
mscBusStrategyDMAEM1 = MSC_READCTRL_BUSSTRATEGY_DMAEM1, /**< Prioritize DMAEM1 for bus accesses */
@ -152,8 +149,7 @@ typedef enum
#endif
/** Code execution configuration */
typedef struct
{
typedef struct {
bool scbtEn; /**< Enable Suppressed Conditional Branch Target Prefetch */
bool prefetchEn; /**< Enable MSC prefetching */
bool ifcDis; /**< Disable instruction cache */
@ -179,7 +175,6 @@ typedef struct
#define msc_Return_TypeDef MSC_Status_TypeDef
/** @endcond */
/***************************************************************************//**
* @brief
* Clear one or more pending MSC interrupts.
@ -206,7 +201,6 @@ __STATIC_INLINE void MSC_IntDisable(uint32_t flags)
MSC->IEN &= ~(flags);
}
/***************************************************************************//**
* @brief
* Enable one or more MSC interrupts.
@ -225,7 +219,6 @@ __STATIC_INLINE void MSC_IntEnable(uint32_t flags)
MSC->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending MSC interrupt flags.
@ -242,7 +235,6 @@ __STATIC_INLINE uint32_t MSC_IntGet(void)
return(MSC->IF);
}
/***************************************************************************//**
* @brief
* Get enabled and pending MSC interrupt flags.
@ -265,7 +257,6 @@ __STATIC_INLINE uint32_t MSC_IntGetEnabled(void)
return MSC->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending MSC interrupts from SW.
@ -279,7 +270,6 @@ __STATIC_INLINE void MSC_IntSet(uint32_t flags)
MSC->IFS = flags;
}
#if defined(MSC_IF_CHOF) && defined(MSC_IF_CMOF)
/***************************************************************************//**
* @brief
@ -301,7 +291,6 @@ __STATIC_INLINE void MSC_StartCacheMeasurement(void)
#endif
}
/***************************************************************************//**
* @brief
* Stops measuring the hit rate.
@ -321,13 +310,11 @@ __STATIC_INLINE void MSC_StartCacheMeasurement(void)
* {
* uint32_t flags;
* flags = MSC->IF;
* if (flags & MSC_IF_CHOF)
* {
* if (flags & MSC_IF_CHOF) {
* MSC->IFC = MSC_IF_CHOF;
* hitOverflows++;
* }
* if (flags & MSC_IF_CMOF)
* {
* if (flags & MSC_IF_CMOF) {
* MSC->IFC = MSC_IF_CMOF;
* missOverflows++;
* }
@ -361,8 +348,7 @@ __STATIC_INLINE int32_t MSC_GetCacheMeasurement(void)
#endif
/* Check for overflows in performance counters */
if (MSC->IF & (MSC_IF_CHOF | MSC_IF_CMOF))
{
if (MSC->IF & (MSC_IF_CHOF | MSC_IF_CMOF)) {
return -2;
}
@ -370,15 +356,13 @@ __STATIC_INLINE int32_t MSC_GetCacheMeasurement(void)
total = MSC->CACHEMISSES + hits;
/* To avoid a division by zero. */
if (total == 0)
{
if (total == 0) {
return -1;
}
return (hits * 100) / total;
}
/***************************************************************************//**
* @brief
* Flush the contents of the instruction cache.
@ -392,7 +376,6 @@ __STATIC_INLINE void MSC_FlushCache(void)
#endif
}
/***************************************************************************//**
* @brief
* Enable or disable instruction cache functionality
@ -404,7 +387,6 @@ __STATIC_INLINE void MSC_EnableCache(bool enable)
BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_IFCDIS_SHIFT, !enable);
}
#if defined(MSC_READCTRL_ICCDIS)
/***************************************************************************//**
* @brief
@ -418,7 +400,6 @@ __STATIC_INLINE void MSC_EnableCacheIRQs(bool enable)
}
#endif
/***************************************************************************//**
* @brief
* Enable or disable instruction cache flushing when writing to flash
@ -431,7 +412,6 @@ __STATIC_INLINE void MSC_EnableAutoCacheFlush(bool enable)
}
#endif /* defined( MSC_IF_CHOF ) && defined( MSC_IF_CMOF ) */
#if defined(_MSC_READCTRL_BUSSTRATEGY_MASK)
/***************************************************************************//**
* @brief
@ -445,7 +425,6 @@ __STATIC_INLINE void MSC_BusStrategy(mscBusStrategy_Typedef mode)
}
#endif
/*******************************************************************************
************************* PROTOTYPES **************************************
******************************************************************************/
@ -473,11 +452,12 @@ MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef
uint32_t numBytes);
#if !defined(_EFM32_GECKO_FAMILY)
#if !defined (EM_MSC_RUN_FROM_FLASH) || (_SILICON_LABS_GECKO_INTERNAL_SDID < 84)
MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef
MSC_WriteWordFast(uint32_t *address,
void const *data,
uint32_t numBytes);
#endif
#endif
MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef

54
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h
View File

@ -1,9 +1,9 @@
/**************************************************************************//**
* @file em_opamp.h
* @brief Operational Amplifier (OPAMP) peripheral API
* @version 5.1.2
* @version 5.3.3
******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -66,7 +66,13 @@ extern "C" {
#if defined(_SILICON_LABS_32B_SERIES_0)
#define DAC_OPA_VALID(opa) ((opa) <= OPA2)
#elif defined(_SILICON_LABS_32B_SERIES_1)
#if defined(VDAC_STATUS_OPA2ENS)
#define VDAC_OPA_VALID(opa) ((opa) <= OPA2)
#elif defined(VDAC_STATUS_OPA1ENS)
#define VDAC_OPA_VALID(opa) ((opa) <= OPA1)
#else
#define VDAC_OPA_VALID(opa) ((opa) = OPA0)
#endif
#endif
/** @endcond */
@ -76,16 +82,20 @@ extern "C" {
******************************************************************************/
/** OPAMP selector values. */
typedef enum
{
typedef enum {
#if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA0ENS)
OPA0 = 0, /**< Select OPA0. */
#endif
#if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA1ENS)
OPA1 = 1, /**< Select OPA1. */
#endif
#if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA2ENS)
OPA2 = 2 /**< Select OPA2. */
#endif
} OPAMP_TypeDef;
/** OPAMP negative terminal input selection values. */
typedef enum
{
typedef enum {
#if defined(_SILICON_LABS_32B_SERIES_0)
opaNegSelDisable = DAC_OPA0MUX_NEGSEL_DISABLE, /**< Input disabled. */
opaNegSelUnityGain = DAC_OPA0MUX_NEGSEL_UG, /**< Unity gain feedback path. */
@ -164,8 +174,7 @@ typedef enum
} OPAMP_NegSel_TypeDef;
/** OPAMP positive terminal input selection values. */
typedef enum
{
typedef enum {
#if defined(_SILICON_LABS_32B_SERIES_0)
opaPosSelDisable = DAC_OPA0MUX_POSSEL_DISABLE, /**< Input disabled. */
opaPosSelDac = DAC_OPA0MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */
@ -246,8 +255,7 @@ typedef enum
} OPAMP_PosSel_TypeDef;
/** OPAMP output terminal selection values. */
typedef enum
{
typedef enum {
#if defined(_SILICON_LABS_32B_SERIES_0)
opaOutModeDisable = DAC_OPA0MUX_OUTMODE_DISABLE, /**< OPA output disabled. */
opaOutModeMain = DAC_OPA0MUX_OUTMODE_MAIN, /**< Main output to pin enabled. */
@ -326,8 +334,7 @@ typedef enum
} OPAMP_OutMode_TypeDef;
/** OPAMP gain values. */
typedef enum
{
typedef enum {
#if defined(_SILICON_LABS_32B_SERIES_0)
opaResSelDefault = DAC_OPA0MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */
opaResSelR2eq0_33R1 = DAC_OPA0MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */
@ -352,8 +359,7 @@ typedef enum
} OPAMP_ResSel_TypeDef;
/** OPAMP resistor ladder input selector values. */
typedef enum
{
typedef enum {
#if defined(_SILICON_LABS_32B_SERIES_0)
opaResInMuxDisable = DAC_OPA0MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */
opaResInMuxOpaIn = DAC_OPA0MUX_RESINMUX_OPA0INP, /**< Input from OPAx. */
@ -374,8 +380,7 @@ typedef enum
} OPAMP_ResInMux_TypeDef;
#if defined(_SILICON_LABS_32B_SERIES_1)
typedef enum
{
typedef enum {
opaPrsModeDefault = VDAC_OPA_CTRL_PRSMODE_DEFAULT, /**< Default value when PRS is not the trigger. */
opaPrsModePulsed = VDAC_OPA_CTRL_PRSMODE_PULSED, /**< PRS trigger is a pulse that starts the OPAMP
warmup sequence. The end of the warmup sequence
@ -385,8 +390,7 @@ typedef enum
sequence is controlled by the edge of the pulse. */
} OPAMP_PrsMode_TypeDef;
typedef enum
{
typedef enum {
opaPrsSelDefault = VDAC_OPA_CTRL_PRSSEL_DEFAULT, /**< Default value when PRS is not the trigger. */
opaPrsSelCh0 = VDAC_OPA_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0 triggers OPAMP. */
opaPrsSelCh1 = VDAC_OPA_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1 triggers OPAMP. */
@ -396,28 +400,27 @@ typedef enum
opaPrsSelCh5 = VDAC_OPA_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5 triggers OPAMP. */
opaPrsSelCh6 = VDAC_OPA_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6 triggers OPAMP. */
opaPrsSelCh7 = VDAC_OPA_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7 triggers OPAMP. */
#if defined(VDAC_OPA_CTRL_PRSSEL_PRSCH8)
opaPrsSelCh8 = VDAC_OPA_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8 triggers OPAMP. */
opaPrsSelCh9 = VDAC_OPA_CTRL_PRSSEL_PRSCH9, /**< PRS channel 9 triggers OPAMP. */
opaPrsSelCh10 = VDAC_OPA_CTRL_PRSSEL_PRSCH10, /**< PRS channel 10 triggers OPAMP. */
opaPrsSelCh11 = VDAC_OPA_CTRL_PRSSEL_PRSCH11, /**< PRS channel 11 triggers OPAMP. */
#endif
} OPAMP_PrsSel_TypeDef;
typedef enum
{
typedef enum {
opaPrsOutDefault = VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT, /**< Default value. */
opaPrsOutWarm = VDAC_OPA_CTRL_PRSOUTMODE_WARM, /**< Warm status available on PRS. */
opaPrsOutOutValid = VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID, /**< Outvalid status available on PRS. */
} OPAMP_PrsOut_TypeDef;
typedef enum
{
typedef enum {
opaOutScaleDefault = VDAC_OPA_CTRL_OUTSCALE_DEFAULT, /**< Default OPAM output drive strength. */
opaOutScaleFull = VDAC_OPA_CTRL_OUTSCALE_FULL, /**< OPAMP uses full output drive strength. */
opaOutSacleHalf = VDAC_OPA_CTRL_OUTSCALE_HALF, /**< OPAMP uses half output drive strength. */
} OPAMP_OutScale_Typedef;
typedef enum
{
typedef enum {
opaDrvStrDefault = VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT, /**< Default value. */
opaDrvStrLowerAccLowStr = (0 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Lower accuracy with low drive stregth. */
opaDrvStrLowAccLowStr = (1 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Low accuracy with low drive stregth. */
@ -431,8 +434,7 @@ typedef enum
******************************************************************************/
/** OPAMP init structure. */
typedef struct
{
typedef struct {
OPAMP_NegSel_TypeDef negSel; /**< Select input source for negative terminal. */
OPAMP_PosSel_TypeDef posSel; /**< Select input source for positive terminal. */
OPAMP_OutMode_TypeDef outMode; /**< Output terminal connection. */

40
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_pcnt.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_pcnt.h
* @brief Pulse Counter (PCNT) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -72,14 +72,12 @@ extern "C" {
#define PCNT2_CNT_SIZE (8) /* PCNT2 counter is 8 bits. */
#endif
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
/** Mode selection. */
typedef enum
{
typedef enum {
/** Disable pulse counter. */
pcntModeDisable = _PCNT_CTRL_MODE_DISABLE,
@ -104,13 +102,11 @@ typedef enum
#endif
} PCNT_Mode_TypeDef;
#if defined(_PCNT_CTRL_CNTEV_MASK)
/** Counter event selection.
* Note: unshifted values are being used for enumeration because multiple
* configuration structure members use this type definition. */
typedef enum
{
typedef enum {
/** Counts up on up-count and down on down-count events. */
pcntCntEventBoth = _PCNT_CTRL_CNTEV_BOTH,
@ -125,11 +121,9 @@ typedef enum
} PCNT_CntEvent_TypeDef;
#endif
#if defined(_PCNT_INPUT_MASK)
/** PRS sources for @p s0PRS and @p s1PRS. */
typedef enum
{
typedef enum {
pcntPRSCh0 = 0, /**< PRS channel 0. */
pcntPRSCh1 = 1, /**< PRS channel 1. */
pcntPRSCh2 = 2, /**< PRS channel 2. */
@ -160,23 +154,19 @@ typedef enum
#endif
} PCNT_PRSSel_TypeDef;
/** PRS inputs of PCNT. */
typedef enum
{
typedef enum {
pcntPRSInputS0 = 0, /** PRS input 0. */
pcntPRSInputS1 = 1 /** PRS input 1. */
} PCNT_PRSInput_TypeDef;
#endif
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** Init structure. */
typedef struct
{
typedef struct {
/** Mode to operate in. */
PCNT_Mode_TypeDef mode;
@ -264,8 +254,7 @@ typedef struct
#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT)
/** Filter initialization structure */
typedef struct
{
typedef struct {
/** Used only in OVSINGLE and OVSQUAD1X-4X modes. To use this, enable the filter through
* setting filter to true during PCNT_Init(). Filter length = (filtLen + 5) LFACLK cycles. */
uint8_t filtLen;
@ -288,8 +277,7 @@ typedef struct
#if defined(PCNT_CTRL_TCCMODE_DEFAULT)
/** Modes for Triggered Compare and Clear module */
typedef enum
{
typedef enum {
/** Triggered compare and clear not enabled. */
tccModeDisabled = _PCNT_CTRL_TCCMODE_DISABLED,
@ -301,8 +289,7 @@ typedef enum
} PCNT_TCCMode_TypeDef;
/** Prescaler values for LFA compare and clear events. Only has effect when TCC mode is LFA. */
typedef enum
{
typedef enum {
/** Compare and clear event each LFA cycle. */
tccPrescDiv1 = _PCNT_CTRL_TCCPRESC_DIV1,
@ -317,8 +304,7 @@ typedef enum
} PCNT_TCCPresc_Typedef;
/** Compare modes for TCC module */
typedef enum
{
typedef enum {
/** Compare match if PCNT_CNT is less than, or equal to PCNT_TOP. */
tccCompLTOE = _PCNT_CTRL_TCCCOMP_LTOE,
@ -331,8 +317,7 @@ typedef enum
} PCNT_TCCComp_Typedef;
/** TCC initialization structure */
typedef struct
{
typedef struct {
/** Mode to operate in. */
PCNT_TCCMode_TypeDef mode;
@ -547,7 +532,6 @@ __STATIC_INLINE uint32_t PCNT_IntGetEnabled(PCNT_TypeDef *pcnt)
{
uint32_t ien;
/* Store pcnt->IEN in temporary variable in order to define explicit order
* of volatile accesses. */
ien = pcnt->IEN;

8
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_prs.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_prs.h
* @brief Peripheral Reflex System (PRS) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -55,8 +55,7 @@ extern "C" {
******************************************************************************/
/** Edge detection type. */
typedef enum
{
typedef enum {
prsEdgeOff = PRS_CH_CTRL_EDSEL_OFF, /**< Leave signal as is. */
prsEdgePos = PRS_CH_CTRL_EDSEL_POSEDGE, /**< Generate pules on positive edge. */
prsEdgeNeg = PRS_CH_CTRL_EDSEL_NEGEDGE, /**< Generate pules on negative edge. */
@ -88,7 +87,6 @@ __STATIC_INLINE void PRS_LevelSet(uint32_t level, uint32_t mask)
PRS->SWLEVEL = (PRS->SWLEVEL & ~mask) | (level & mask);
}
/***************************************************************************//**
* @brief
* Trigger a high pulse (one HFPERCLK) for one or more channels.

345
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_qspi.h Normal file
View File

@ -0,0 +1,345 @@
/***************************************************************************//**
* @file em_qspi.h
* @brief QSPI Octal-SPI Flash Controller API
* @version 5.3.3
*******************************************************************************
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
* obligation to support this Software. Silicon Labs is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Silicon Labs will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
******************************************************************************/
#ifndef EM_QSPI_H
#define EM_QSPI_H
#include "em_device.h"
#if defined(QSPI_COUNT) && (QSPI_COUNT > 0)
#ifdef __cplusplus
extern "C" {
#endif
#include "em_bus.h"
#include <stdbool.h>
/***************************************************************************//**
* @addtogroup emlib
* @{
******************************************************************************/
/***************************************************************************//**
* @addtogroup QSPI
* @{
******************************************************************************/
/*******************************************************************************
******************************* DEFINES ***********************************
******************************************************************************/
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
/** Transfer type. */
typedef enum {
/** Single IO mode. DQ0 used for output and DQ1 as input. */
qspiTransferSingle = 0,
/** Dual I/O transfer. DQ0 and DQ1 are used as both inputs and outputs. */
qspiTransferDual = 1,
/** Quad I/O transfer. DQ0, DQ1, DQ2 and DQ3 are used as both inputs and outputs. */
qspiTransferQuad = 2,
/** Octal I/O transfer. DQ[7:0] are used as both inputs and outputs. */
qspiTransferOctal = 3
} QSPI_TransferType_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** QSPI Device Read Instruction Configuration structure. */
typedef struct {
/** Read opcode in non-xip mode. */
uint8_t opCode;
/** Number of dummy read clock cycles. */
uint8_t dummyCycles;
/** Transfer type used for address. */
QSPI_TransferType_TypeDef addrTransfer;
/** Transfer type used for data. */
QSPI_TransferType_TypeDef dataTransfer;
/** Transfer type used for instruction. */
QSPI_TransferType_TypeDef instTransfer;
} QSPI_ReadConfig_TypeDef;
/** Default read configuration structure. */
#define QSPI_READCONFIG_DEFAULT \
{ \
0x03, /* 0x03 is the standard read opcode. */ \
0, /* 0 dummy cycles. */ \
qspiTransferSingle, /* Single I/O mode. */ \
qspiTransferSingle, /* Single I/O mode. */ \
qspiTransferSingle, /* Single I/O mode. */ \
}
/** QSPI Device Write Instruction Configuration structure. */
typedef struct {
/** Write opcode. */
uint8_t opCode;
/** Number of dummy read clock cycles. */
uint8_t dummyCycles;
/** Transfer type used for address. */
QSPI_TransferType_TypeDef addrTransfer;
/** Transfer type used for data. */
QSPI_TransferType_TypeDef dataTransfer;
/**
* @brief
* Enable/disable automatic issuing of WEL (Write Enable Latch)
* command before a write operation.
*
* @details
* When writing to a flash device the write enable latch (WEL)
* within the flash device itself must be high before a write sequence can be
* issued. The QSPI peripheral can automatically issue the write enable latch
* command before triggering a write sequence. The command used for enabling
* the write enable latch is WREN (0x06) and is common between devices. */
bool autoWEL;
} QSPI_WriteConfig_TypeDef;
/** Default write configuration structure. */
#define QSPI_WRITECONFIG_DEFAULT \
{ \
0x02, /* 0x02 is the standard write opcode. */ \
0, /* 0 dummy cycles. */ \
qspiTransferSingle, /* Single I/O mode. */ \
qspiTransferSingle, /* Single I/O mode. */ \
true, /* Send WEL command automatically. */ \
}
/** QSPI Device Delay Configuration structure. */
typedef struct {
/** The minimal delay to keep the chip select line de-asserted between
* two transactions. */
uint8_t deassert;
/** Delay between one chip select being de-activated and the
* activation of another. */
uint8_t deviceSwitch;
/** Delay between last bit and chip select de-assert. */
uint8_t lastBit;
/** Delay chip select assert and first bit in a transaction. */
uint8_t firstBit;
} QSPI_DelayConfig_TypeDef;
/** Defines command to be executed using STIG mechanism. */
typedef struct {
/** command op-code */
uint8_t cmdOpcode;
/** Number of Read Data Bytes */
uint16_t readDataSize;
/** Number of Address Bytes */
uint8_t addrSize;
/** Number of Write Data Bytes */
uint8_t writeDataSize;
/** Number of dummy cycles */
uint8_t dummyCycles;
/** Mode Bit Configuration register are sent following the address bytes. */
bool modeBitEnable;
/** flash command address */
uint32_t address;
/** buffer for read data */
void * readBuffer;
/** buffer with data to write */
void * writeBuffer;
} QSPI_StigCmd_TypeDef;
/** QSPI initialization structure. */
typedef struct {
/** Enable/disable Quad SPI when initialization is completed. */
bool enable;
/**
* Master mode baude rate divisor. Values can be even numbers in the range
* [2-32] inclusive. */
uint8_t divisor;
} QSPI_Init_TypeDef;
/** Default configuration for QSPI_Init_TypeDef structure. */
#define QSPI_INIT_DEFAULT \
{ \
true, /* Enable Quad SPI. */ \
32, /* Divide QSPI clock by 32. */ \
}
/*******************************************************************************
****************************** PROTOTYPES *********************************
******************************************************************************/
void QSPI_Init(QSPI_TypeDef * qspi, const QSPI_Init_TypeDef * init);
void QSPI_ReadConfig(QSPI_TypeDef * qspi, const QSPI_ReadConfig_TypeDef * config);
void QSPI_WriteConfig(QSPI_TypeDef * qspi, const QSPI_WriteConfig_TypeDef * config);
void QSPI_ExecStigCmd(QSPI_TypeDef * qspi, const QSPI_StigCmd_TypeDef * stigCmd);
/***************************************************************************//**
* @brief
* Wait for the QSPI to go into idle state.
*
* @param[in] qspi
* Pointer to QSPI peripheral register block.
******************************************************************************/
__STATIC_INLINE void QSPI_WaitForIdle(QSPI_TypeDef * qspi)
{
while ((qspi->CONFIG & _QSPI_CONFIG_IDLE_MASK) == 0)
;
}
/***************************************************************************//**
* @brief
* Get the fill level of the write partition of the QSPI internal SRAM.
*
* @param[in] qspi
* Pointer to QSPI peripheral register block.
*
* @return
* SRAM fill level of the write partition. The value is the number of 4 byte
* words in the write partition.
******************************************************************************/
__STATIC_INLINE uint16_t QSPI_GetWriteLevel(QSPI_TypeDef * qspi)
{
return (qspi->SRAMFILL & _QSPI_SRAMFILL_SRAMFILLINDACWRITE_MASK)
>> _QSPI_SRAMFILL_SRAMFILLINDACWRITE_SHIFT;
}
/***************************************************************************//**
* @brief
* Get the fill level of the read partition of the QSPI internal SRAM.
*
* @param[in] qspi
* Pointer to QSPI peripheral register block.
*
* @return
* SRAM fill level of the read partition. The value is the number of 4 byte
* words in the read partition.
******************************************************************************/
__STATIC_INLINE uint16_t QSPI_GetReadLevel(QSPI_TypeDef * qspi)
{
return (qspi->SRAMFILL & _QSPI_SRAMFILL_SRAMFILLINDACREAD_MASK)
>> _QSPI_SRAMFILL_SRAMFILLINDACREAD_SHIFT;
}
/***************************************************************************//**
* @brief
* Enable/disable Quad SPI.
*
* @param[in] qspi
* Pointer to QSPI peripheral register block.
*
* @param[in] enable
* true to enable quad spi, false to disable quad spi.
******************************************************************************/
__STATIC_INLINE void QSPI_Enable(QSPI_TypeDef * qspi, bool enable)
{
BUS_RegBitWrite(&qspi->CONFIG, _QSPI_CONFIG_ENBSPI_SHIFT, enable ? 1 : 0);
}
/***************************************************************************//**
* @brief
* Get the current interrupt flags.
*
* @param[in] qspi
* Pointer to QSPI peripheral register block.
*
* @return
* This functions returns the current interrupt flags that are set.
******************************************************************************/
__STATIC_INLINE uint32_t QSPI_IntGet(QSPI_TypeDef * qspi)
{
return qspi->IRQSTATUS;
}
/***************************************************************************//**
* @brief
* Clear interrupt flags
*
* @param[in] qspi
* Pointer to QSPI peripheral register block.
*
* @param[in] flags
* The interrupt flags to clear.
******************************************************************************/
__STATIC_INLINE void QSPI_IntClear(QSPI_TypeDef * qspi, uint32_t flags)
{
qspi->IRQSTATUS = flags;
}
/***************************************************************************//**
* @brief
* Enable interrupts.
*
* @param[in] qspi
* Pointer to QSPI peripheral register block.
*
* @param[in] flags
* The interrupt flags to enable.
******************************************************************************/
__STATIC_INLINE void QSPI_IntEnable(QSPI_TypeDef * qspi, uint32_t flags)
{
qspi->IRQMASK = flags & (~_QSPI_IRQMASK_MASK);
}
/***************************************************************************//**
* @brief
* Disable interrupts.
*
* @param[in] qspi
* Pointer to QSPI peripheral register block.
*
* @param[in] flags
* The interrupt flags to disable.
******************************************************************************/
__STATIC_INLINE void QSPI_IntDisable(QSPI_TypeDef * qspi, uint32_t flags)
{
qspi->IRQMASK = ~flags & (~_QSPI_IRQMASK_MASK);
}
/** @} (end addtogroup QSPI) */
/** @} (end addtogroup emlib) */
#ifdef __cplusplus
}
#endif
#endif /* defined(QSPI_COUNT) && (QSPI_COUNT > 0) */
#endif /* EM_QSPI_H */

12
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ramfunc.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_ramfunc.h
* @brief RAM code support.
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -37,6 +37,7 @@
extern "C" {
#endif
/* *INDENT-OFF* */
/***************************************************************************//**
* @addtogroup emlib
* @{
@ -61,6 +62,11 @@ extern "C" {
guarantee no calls to standard libraries with GCC.
Read more at https://gcc.gnu.org/onlinedocs/gcc-5.3.0/gcc/Standards.html
@warning
Keil/ARM uVision users must add a section named "ram_code" in their linker
scatter file. This section must be in RAM memory. Look in the MCU SDK for
example scatter files (ram_code.sct).
@n @section ramfunc_usage Usage
In your .h file:
@ -87,8 +93,8 @@ extern "C" {
SL_RAMFUNC_DEFINITION_END
@endverbatim
******************************************************************************/
/* *INDENT-ON* */
/*******************************************************************************
****************************** DEFINES ***********************************

10
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rmu.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_rmu.h
* @brief Reset Management Unit (RMU) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -58,8 +58,7 @@ extern "C" {
******************************************************************************/
/** RMU reset modes */
typedef enum
{
typedef enum {
#if defined(_RMU_CTRL_PINRMODE_MASK)
rmuResetModeDisabled = _RMU_CTRL_PINRMODE_DISABLED,
rmuResetModeLimited = _RMU_CTRL_PINRMODE_LIMITED,
@ -72,8 +71,7 @@ typedef enum
} RMU_ResetMode_TypeDef;
/** RMU controlled peripheral reset control and reset source control */
typedef enum
{
typedef enum {
#if defined(RMU_CTRL_BURSTEN)
rmuResetBU = _RMU_CTRL_BURSTEN_MASK, /**< Reset control over Backup Power domain select */
#endif

15
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtc.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_rtc.h
* @brief Real Time Counter (RTC) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -57,8 +57,7 @@ extern "C" {
******************************************************************************/
/** RTC initialization structure. */
typedef struct
{
typedef struct {
bool enable; /**< Start counting when init completed. */
bool debugRun; /**< Counter shall keep running during debug halt. */
bool comp0Top; /**< Use compare register 0 as max count value. */
@ -72,7 +71,6 @@ typedef struct
true /* Restart counting from 0 when reaching COMP0 */ \
}
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
@ -108,7 +106,9 @@ __STATIC_INLINE void RTC_CounterSet(uint32_t value)
void RTC_CounterReset(void);
void RTC_Enable(bool enable);
#if defined(_RTC_FREEZE_MASK)
void RTC_FreezeEnable(bool enable);
#endif
void RTC_Init(const RTC_Init_TypeDef *init);
/***************************************************************************//**
@ -125,7 +125,6 @@ __STATIC_INLINE void RTC_IntClear(uint32_t flags)
RTC->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more RTC interrupts.
@ -140,7 +139,6 @@ __STATIC_INLINE void RTC_IntDisable(uint32_t flags)
RTC->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more RTC interrupts.
@ -160,7 +158,6 @@ __STATIC_INLINE void RTC_IntEnable(uint32_t flags)
RTC->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending RTC interrupt flags.
@ -177,7 +174,6 @@ __STATIC_INLINE uint32_t RTC_IntGet(void)
return RTC->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending RTC interrupt flags.
@ -200,7 +196,6 @@ __STATIC_INLINE uint32_t RTC_IntGetEnabled(void)
return RTC->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending RTC interrupts from SW.

78
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtcc.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file
* @brief Real Time Counter (RTCC) peripheral API.
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -73,19 +73,17 @@ extern "C" {
******************************************************************************/
/** Operational mode of the counter. */
typedef enum
{
typedef enum {
/** Normal counter mode. The counter is incremented by 1 for each tick. */
rtccCntModeNormal = _RTCC_CTRL_CNTTICK_PRESC,
rtccCntModeNormal = _RTCC_CTRL_CNTMODE_NORMAL,
/** Calendar mode. Refer to the RTCC chapter of the Reference Manual for more
* details on the calendar mode. */
rtccCntModeCalendar = _RTCC_CTRL_CNTTICK_CCV0MATCH
rtccCntModeCalendar = _RTCC_CTRL_CNTMODE_CALENDAR
} RTCC_CntMode_TypeDef;
/** Counter prescaler selection. */
typedef enum
{
typedef enum {
rtccCntPresc_1 = _RTCC_CTRL_CNTPRESC_DIV1, /**< Divide clock by 1. */
rtccCntPresc_2 = _RTCC_CTRL_CNTPRESC_DIV2, /**< Divide clock by 2. */
rtccCntPresc_4 = _RTCC_CTRL_CNTPRESC_DIV4, /**< Divide clock by 4. */
@ -104,10 +102,8 @@ typedef enum
rtccCntPresc_32768 = _RTCC_CTRL_CNTPRESC_DIV32768 /**< Divide clock by 32768. */
} RTCC_CntPresc_TypeDef;
/** Prescaler mode of the RTCC counter. */
typedef enum
{
typedef enum {
/** CNT register ticks according to the prescaler value. */
rtccCntTickPresc = _RTCC_CTRL_CNTTICK_PRESC,
@ -116,28 +112,23 @@ typedef enum
rtccCntTickCCV0Match = _RTCC_CTRL_CNTTICK_CCV0MATCH
} RTCC_PrescMode_TypeDef;
/** Capture/Compare channel mode. */
typedef enum
{
typedef enum {
rtccCapComChModeOff = _RTCC_CC_CTRL_MODE_OFF, /**< Capture/Compare channel turned off. */
rtccCapComChModeCapture = _RTCC_CC_CTRL_MODE_INPUTCAPTURE, /**< Capture mode. */
rtccCapComChModeCompare = _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE, /**< Compare mode. */
} RTCC_CapComChMode_TypeDef;
/** Compare match output action mode. */
typedef enum
{
typedef enum {
rtccCompMatchOutActionPulse = _RTCC_CC_CTRL_CMOA_PULSE, /**< Generate a pulse. */
rtccCompMatchOutActionToggle = _RTCC_CC_CTRL_CMOA_TOGGLE, /**< Toggle output. */
rtccCompMatchOutActionClear = _RTCC_CC_CTRL_CMOA_CLEAR, /**< Clear output. */
rtccCompMatchOutActionSet = _RTCC_CC_CTRL_CMOA_SET /**< Set output. */
} RTCC_CompMatchOutAction_TypeDef;
/** PRS input sources. */
typedef enum
{
typedef enum {
rtccPRSCh0 = _RTCC_CC_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */
rtccPRSCh1 = _RTCC_CC_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */
rtccPRSCh2 = _RTCC_CC_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */
@ -146,26 +137,30 @@ typedef enum
rtccPRSCh5 = _RTCC_CC_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5. */
rtccPRSCh6 = _RTCC_CC_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6. */
rtccPRSCh7 = _RTCC_CC_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7. */
#if defined(_RTCC_CC_CTRL_PRSSEL_PRSCH8)
rtccPRSCh8 = _RTCC_CC_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8. */
#endif
#if defined(_RTCC_CC_CTRL_PRSSEL_PRSCH9)
rtccPRSCh9 = _RTCC_CC_CTRL_PRSSEL_PRSCH9, /**< PRS channel 9. */
#endif
#if defined(_RTCC_CC_CTRL_PRSSEL_PRSCH10)
rtccPRSCh10 = _RTCC_CC_CTRL_PRSSEL_PRSCH10, /**< PRS channel 10. */
#endif
#if defined(_RTCC_CC_CTRL_PRSSEL_PRSCH11)
rtccPRSCh11 = _RTCC_CC_CTRL_PRSSEL_PRSCH11 /**< PRS channel 11. */
#endif
} RTCC_PRSSel_TypeDef;
/** Input edge select. */
typedef enum
{
typedef enum {
rtccInEdgeRising = _RTCC_CC_CTRL_ICEDGE_RISING, /**< Rising edges detected. */
rtccInEdgeFalling = _RTCC_CC_CTRL_ICEDGE_FALLING, /**< Falling edges detected. */
rtccInEdgeBoth = _RTCC_CC_CTRL_ICEDGE_BOTH, /**< Both edges detected. */
rtccInEdgeNone = _RTCC_CC_CTRL_ICEDGE_NONE /**< No edge detection, signal is left as is. */
} RTCC_InEdgeSel_TypeDef;
/** Capture/Compare channel compare mode. */
typedef enum
{
typedef enum {
/** CCVx is compared with the CNT register. */
rtccCompBaseCnt = _RTCC_CC_CTRL_COMPBASE_CNT,
@ -174,8 +169,7 @@ typedef enum
} RTCC_CompBase_TypeDef;
/** Day compare mode. */
typedef enum
{
typedef enum {
rtccDayCompareModeMonth = _RTCC_CC_CTRL_DAYCC_MONTH, /**< Day of month is selected for Capture/Compare. */
rtccDayCompareModeWeek = _RTCC_CC_CTRL_DAYCC_WEEK /**< Day of week is selected for Capture/Compare. */
} RTCC_DayCompareMode_TypeDef;
@ -185,8 +179,7 @@ typedef enum
******************************************************************************/
/** RTCC initialization structure. */
typedef struct
{
typedef struct {
/** Enable/disable counting when initialization is completed. */
bool enable;
@ -224,10 +217,8 @@ typedef struct
bool disLeapYearCorr;
} RTCC_Init_TypeDef;
/** RTCC capture/compare channel configuration structure. */
typedef struct
{
typedef struct {
/** Select the mode of the Capture/Compare channel. */
RTCC_CapComChMode_TypeDef chMode;
@ -251,7 +242,6 @@ typedef struct
RTCC_DayCompareMode_TypeDef dayCompMode;
} RTCC_CCChConf_TypeDef;
/*******************************************************************************
******************************* DEFINES ***********************************
******************************************************************************/
@ -484,12 +474,9 @@ __STATIC_INLINE void RTCC_DateSet( uint32_t date )
******************************************************************************/
__STATIC_INLINE void RTCC_EM4WakeupEnable(bool enable)
{
if ( enable )
{
if ( enable ) {
RTCC->EM4WUEN = RTCC_EM4WUEN_EM4WU;
}
else
{
} else {
RTCC->EM4WUEN = 0;
}
}
@ -608,8 +595,7 @@ __STATIC_INLINE void RTCC_Lock( void )
* RTCC_LOCK register must be modified while RTCC clock is disabled. */
uint32_t lfeReg = CMU->LFECLKEN0;
bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED);
if (cmuLocked)
{
if (cmuLocked) {
CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
}
CMU->LFECLKEN0 = 0x0;
@ -618,8 +604,7 @@ __STATIC_INLINE void RTCC_Lock( void )
#if defined(ERRATA_FIX_RTCC_E203)
/* Restore clock state after RTCC_E203 fix. */
CMU->LFECLKEN0 = lfeReg;
if (cmuLocked)
{
if (cmuLocked) {
CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
}
#endif
@ -678,8 +663,7 @@ void RTCC_StatusClear( void );
******************************************************************************/
__STATIC_INLINE uint32_t RTCC_StatusGet(void)
{
while ( RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD )
{
while ( RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD ) {
// Wait for syncronization.
}
return RTCC->STATUS;
@ -725,8 +709,7 @@ __STATIC_INLINE void RTCC_Unlock( void )
* RTCC_LOCK register must be modified while RTCC clock is disabled. */
uint32_t lfeReg = CMU->LFECLKEN0;
bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED);
if (cmuLocked)
{
if (cmuLocked) {
CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
}
CMU->LFECLKEN0 = 0x0;
@ -735,8 +718,7 @@ __STATIC_INLINE void RTCC_Unlock( void )
#if defined(ERRATA_FIX_RTCC_E203)
/* Restore clock state after RTCC_E203 fix. */
CMU->LFECLKEN0 = lfeReg;
if (cmuLocked)
{
if (cmuLocked) {
CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
}
#endif

323
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_smu.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_smu.h
* @brief Security Management Unit (SMU) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -77,7 +77,6 @@ extern "C" {
/** SMU peripheral identifiers. */
typedef enum {
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
@ -127,8 +126,12 @@ typedef enum {
smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1 */
#if defined(_SMU_PPUPATD0_CSEN_SHIFT)
smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */
#endif
#if defined(_SMU_PPUPATD0_VDAC0_SHIFT)
smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
#endif
smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */
@ -136,7 +139,9 @@ typedef enum {
smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
#if defined(_SMU_PPUPATD0_IDAC0_SHIFT)
smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */
#endif
smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */
smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
@ -156,6 +161,167 @@ typedef enum {
smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
#if defined(_SMU_PPUPATD0_ACMP0_SHIFT)
smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
#endif
#if defined(_SMU_PPUPATD0_ACMP1_SHIFT)
smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
#endif
smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */
smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
smuPeripheralCRYPTO = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
#if defined(_SMU_PPUPATD0_VDAC0_SHIFT)
smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
#endif
smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */
smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
#if defined(_SMU_PPUPATD0_IDAC0_SHIFT)
smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */
#endif
smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */
smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
#if defined(_SMU_PPUPATD0_LESENSE_SHIFT)
smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
#endif
smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */
smuPeripheralLEUART = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */
#if defined(_SMU_PPUPATD0_PCNT0_SHIFT)
smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */
#endif
smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU */
smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */
smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */
smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100)
smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, /**< SMU peripheral identifier for ACMP2 */
smuPeripheralACMP3 = _SMU_PPUPATD0_ACMP3_SHIFT, /**< SMU peripheral identifier for ACMP3 */
smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */
smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, /**< SMU peripheral identifier for ADC1 */
smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0 */
smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, /**< SMU peripheral identifier for CAN1 */
smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */
smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, /**< SMU peripheral identifier for EBI */
smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
#if defined(_SMU_PPUPATD0_ETH_SHIFT)
smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, /**< SMU peripheral identifier for ETH */
#endif
smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */
smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
smuPeripheralI2C2 = _SMU_PPUPATD0_I2C2_SHIFT, /**< SMU peripheral identifier for I2C2 */
smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */
smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC */
#if defined(_SMU_PPUPATD0_LCD_SHIFT)
smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD */
#endif
smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */
smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, /**< SMU peripheral identifier for LETIMER1 */
smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */
smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, /**< SMU peripheral identifier for LEUART1 */
smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */
smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1 */
smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2 */
#if defined(_SMU_PPUPATD1_QSPI0_SHIFT)
smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, /**< SMU peripheral identifier for QSPI0 */
#endif
smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU */
smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, /**< SMU peripheral identifier for RTC */
smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
#if defined(_SMU_PPUPATD1_SDIO_SHIFT)
smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, /**< SMU peripheral identifier for SDIO */
#endif
smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */
smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2 */
smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3 */
smuPeripheralTIMER4 = 32 + _SMU_PPUPATD1_TIMER4_SHIFT, /**< SMU peripheral identifier for TIMER4 */
smuPeripheralTIMER5 = 32 + _SMU_PPUPATD1_TIMER5_SHIFT, /**< SMU peripheral identifier for TIMER5 */
smuPeripheralTIMER6 = 32 + _SMU_PPUPATD1_TIMER6_SHIFT, /**< SMU peripheral identifier for TIMER6 */
smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */
smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, /**< SMU peripheral identifier for UART0 */
smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, /**< SMU peripheral identifier for UART1 */
smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */
smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3 */
smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, /**< SMU peripheral identifier for USART4 */
smuPeripheralUSART5 = 32 + _SMU_PPUPATD1_USART5_SHIFT, /**< SMU peripheral identifier for USART5 */
#if defined(_SMU_PPUPATD1_USB_SHIFT)
smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, /**< SMU peripheral identifier for USB */
#endif
smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1 */
smuPeripheralWTIMER2 = 32 + _SMU_PPUPATD1_WTIMER2_SHIFT, /**< SMU peripheral identifier for WTIMER2 */
smuPeripheralWTIMER3 = 32 + _SMU_PPUPATD1_WTIMER3_SHIFT, /**< SMU peripheral identifier for WTIMER3 */
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */
smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0 */
smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */
smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC */
#if defined(_SMU_PPUPATD0_LCD_SHIFT)
smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD */
#endif
smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */
smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */
smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */
smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU */
smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER0 */
smuPeripheralTRNG0 = _SMU_PPUPATD0_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */
smuPeripheralUART0 = _SMU_PPUPATD0_UART0_SHIFT, /**< SMU peripheral identifier for UART0 */
smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
smuPeripheralUSART2 = _SMU_PPUPATD0_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */
smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3 */
smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1 */
#else
#error "No peripherals defined for SMU for this device configuration."
#endif
@ -164,7 +330,6 @@ typedef enum {
/** SMU peripheral privileged access enablers. */
typedef struct {
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
@ -262,6 +427,154 @@ typedef struct {
bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
bool privilegedACMP0 : 1; /**< Privileged access enabler for */
bool privilegedACMP1 : 1; /**< Privileged access enabler for */
bool privilegedADC0 : 1; /**< Privileged access enabler for */
bool privilegedReserved0 : 1;
bool privilegedReserved1 : 1;
bool privilegedCMU : 1; /**< Privileged access enabler for */
bool privilegedReserved2 : 1;
bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for */
bool privilegedCRYPTO : 1; /**< Privileged access enabler for */
bool privilegedVDAC0 : 1; /**< Privileged access enabler for */
bool privilegedPRS : 1; /**< Privileged access enabler for */
bool privilegedEMU : 1; /**< Privileged access enabler for */
bool privilegedFPUEH : 1; /**< Privileged access enabler for */
bool privilegedReserved3 : 1;
bool privilegedGPCRC : 1; /**< Privileged access enabler for */
bool privilegedGPIO : 1; /**< Privileged access enabler for */
bool privilegedI2C0 : 1; /**< Privileged access enabler for */
bool privilegedIDAC0 : 1; /**< Privileged access enabler for */
bool privilegedMSC : 1; /**< Privileged access enabler for */
bool privilegedLDMA : 1; /**< Privileged access enabler for */
bool privilegedLESENSE : 1; /**< Privileged access enabler for */
bool privilegedLETIMER0 : 1; /**< Privileged access enabler for */
bool privilegedLEUART : 1; /**< Privileged access enabler for */
bool privilegedReserved4 : 1;
bool privilegedPCNT0 : 1; /**< Privileged access enabler for */
bool privilegedReserved5 : 1;
bool privilegedReserved6 : 1;
bool privilegedReserved7 : 1;
bool privilegedReserved8 : 1;
bool privilegedRMU : 1; /**< Privileged access enabler for */
bool privilegedRTCC : 1; /**< Privileged access enabler for */
bool privilegedSMU : 1; /**< Privileged access enabler for */
bool privilegedReserved9 : 1;
bool privilegedTIMER0 : 1; /**< Privileged access enabler for */
bool privilegedTIMER1 : 1; /**< Privileged access enabler for */
bool privilegedTRNG0 : 1; /**< Privileged access enabler for */
bool privilegedUSART0 : 1; /**< Privileged access enabler for */
bool privilegedUSART1 : 1; /**< Privileged access enabler for */
bool privilegedWDOG0 : 1; /**< Privileged access enabler for */
bool privilegedWDOG1 : 1; /**< Privileged access enabler for */
bool privilegedWTIMER0 : 1; /**< Privileged access enabler for */
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100)
bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
bool privilegedACMP2 : 1; /**< Privileged access enabler for ACMP2 */
bool privilegedACMP3 : 1; /**< Privileged access enabler for ACMP3 */
bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */
bool privilegedADC1 : 1; /**< Privileged access enabler for ADC1 */
bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0 */
bool privilegedCAN1 : 1; /**< Privileged access enabler for CAN1 */
bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */
bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */
bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */
bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
bool privilegedPRS : 1; /**< Privileged access enabler for PRS */
bool privilegedEBI : 1; /**< Privileged access enabler for EBI */
bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
bool privilegedETH : 1; /**< Privileged access enabler for ETH */
bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH */
bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
bool privilegedI2C2 : 1; /**< Privileged access enabler for I2C2 */
bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0 */
bool privilegedMSC : 1; /**< Privileged access enabler for MAC */
bool privilegedLCD : 1; /**< Privileged access enabler for LCD */
bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */
bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
bool privilegedLETIMER1 : 1; /**< Privileged access enabler for LETIMER1 */
bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */
bool privilegedLEUART1 : 1; /**< Privileged access enabler for LEUART1 */
bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */
bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1 */
bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2 */
bool privilegedQSPI0 : 1; /**< Privileged access enabler for QSPI0 */
bool privilegedRMU : 1; /**< Privileged access enabler for RMU */
bool privilegedRTC : 1; /**< Privileged access enabler for RTC */
bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */
bool privilegedSDIO : 1; /**< Privileged access enabler for SDIO */
bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */
bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */
bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */
bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5 */
bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6 */
bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */
bool privilegedUART0 : 1; /**< Privileged access enabler for UART0 */
bool privilegedUART1 : 1; /**< Privileged access enabler for UART1 */
bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */
bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3 */
bool privilegedUSART4 : 1; /**< Privileged access enabler for USART4 */
bool privilegedUSART5 : 1; /**< Privileged access enabler for USART5 */
bool privilegedUSB : 1; /**< Privileged access enabler for USB */
bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */
bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1 */
bool privilegedWTIMER2 : 1; /**< Privileged access enabler for WTIMER2 */
bool privilegedWTIMER3 : 1; /**< Privileged access enabler for WTIMER3 */
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */
bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0 */
bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */
bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */
bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */
bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
bool privilegedPRS : 1; /**< Privileged access enabler for PRS */
bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
bool privilegedMSC : 1; /**< Privileged access enabler for MAC */
bool privilegedLCD : 1; /**< Privileged access enabler for LCD */
bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */
bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */
bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */
bool privilegedRMU : 1; /**< Privileged access enabler for RMU */
bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */
bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */
bool privilegedUART0 : 1; /**< Privileged access enabler for UART0 */
bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */
bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3 */
bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */
bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1 */
#else
#error "No peripherals defined for SMU for this device configuration"
#endif
@ -280,13 +593,11 @@ typedef struct {
bool enable; /**< SMU enable flag, when set SMU_Init() will enable SMU.*/
} SMU_Init_TypeDef;
#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID > 80)
/** Default SMU initialization struct settings. */
#define SMU_INIT_DEFAULT { \
{ { 0 } }, /* No peripherals acsess protected. */ \
true /* Enable SMU.*/ \
}
#endif
/*******************************************************************************
***************************** PROTOTYPES **********************************

72
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_system.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_system.h
* @brief System API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -61,18 +61,23 @@ extern "C" {
******************************************************************************/
/** Family identifiers. */
typedef enum
{
typedef enum {
/* New style family #defines */
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32G)
systemPartFamilyEfm32Gecko = _DEVINFO_PART_DEVICE_FAMILY_EFM32G, /**< EFM32 Gecko Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG)
systemPartFamilyEfm32Giant = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG, /**< EFM32 Giant Gecko Device Family */
systemPartFamilyEfm32Giant = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG, /**< EFM32 Giant Gecko Series 0 Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B)
systemPartFamilyEfm32Giant11B = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B, /**< EFM32 Giant Gecko Series 1 Config 1 Basic Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG)
systemPartFamilyEfm32Tiny = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG, /**< EFM32 Tiny Gecko Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B)
systemPartFamilyEfm32Tiny11B = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B, /**< EFM32 Tiny Gecko 11 Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32LG)
systemPartFamilyEfm32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EFM32LG, /**< EFM32 Leopard Gecko Device Family */
#endif
@ -196,8 +201,33 @@ typedef enum
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V)
systemPartFamilyFlex13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V, /**< EFR32 Flex Gecko Series 1 Config 3 Value Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P)
systemPartFamilyMighty14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P, /**< EFR32 Mighty Gecko Series 1 Config 4 Premium Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B)
systemPartFamilyMighty14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B, /**< EFR32 Mighty Gecko Series 1 Config 4 Basic Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V)
systemPartFamilyMighty14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V, /**< EFR32 Mighty Gecko Series 1 Config 4 Value Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P)
systemPartFamilyBlue14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P, /**< EFR32 Blue Gecko Series 1 Config 4 Premium Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B)
systemPartFamilyBlue14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B, /**< EFR32 Blue Gecko Series 1 Config 4 Basic Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V)
systemPartFamilyBlue14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V, /**< EFR32 Blue Gecko Series 1 Config 4 Value Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P)
systemPartFamilyFlex14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P, /**< EFR32 Flex Gecko Series 1 Config 4 Premium Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B)
systemPartFamilyFlex14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B, /**< EFR32 Flex Gecko Series 1 Config 4 Basic Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V)
systemPartFamilyFlex14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V, /**< EFR32 Flex Gecko Series 1 Config 4 Value Device Family */
#endif
/* Deprecated family #defines */
#if defined(_DEVINFO_PART_DEVICE_FAMILY_G)
@ -226,14 +256,12 @@ typedef enum
on unprogrammed parts. */
} SYSTEM_PartFamily_TypeDef;
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** Chip revision details */
typedef struct
{
typedef struct {
uint8_t minor; /**< Minor revision number */
uint8_t major; /**< Major revision number */
uint8_t family;/**< Device family number */
@ -241,8 +269,7 @@ typedef struct
#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1)
/** Floating point coprocessor access modes. */
typedef enum
{
typedef enum {
fpuAccessDenied = (0x0 << 20), /**< Access denied, any attempted access generates a NOCP UsageFault. */
fpuAccessPrivilegedOnly = (0x5 << 20), /**< Privileged access only, an unprivileged access generates a NOCP UsageFault. */
fpuAccessReserved = (0xA << 20), /**< Reserved. */
@ -251,8 +278,7 @@ typedef enum
#endif
/** DEVINFO calibration address/value pair */
typedef struct
{
typedef struct {
uint32_t address; /**< Peripheral calibration register address */
uint32_t calValue; /**< Calibration value for register at address */
}
@ -324,8 +350,7 @@ __STATIC_INLINE uint16_t SYSTEM_GetSRAMSize(void)
#if defined(_EFM32_GECKO_FAMILY)
/* Early Gecko devices had a bug where SRAM and Flash size were swapped. */
if (SYSTEM_GetProdRev() < 5)
{
if (SYSTEM_GetProdRev() < 5) {
sizekb = (DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK)
>> _DEVINFO_MSIZE_FLASH_SHIFT;
}
@ -357,8 +382,7 @@ __STATIC_INLINE uint16_t SYSTEM_GetFlashSize(void)
{
#if defined(_EFM32_GECKO_FAMILY)
/* Early Gecko devices had a bug where SRAM and Flash size were swapped. */
if (SYSTEM_GetProdRev() < 5)
{
if (SYSTEM_GetProdRev() < 5) {
return (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK)
>> _DEVINFO_MSIZE_SRAM_SHIFT;
}
@ -367,7 +391,6 @@ __STATIC_INLINE uint16_t SYSTEM_GetFlashSize(void)
>> _DEVINFO_MSIZE_FLASH_SHIFT;
}
/***************************************************************************//**
* @brief
* Get the flash page size in bytes.
@ -384,18 +407,18 @@ __STATIC_INLINE uint32_t SYSTEM_GetFlashPageSize(void)
{
uint32_t tmp;
#if defined(_SILICON_LABS_32B_SERIES_0)
#if defined(_EFM32_GIANT_FAMILY)
if (SYSTEM_GetProdRev() < 18)
{
if (SYSTEM_GetProdRev() < 18) {
/* Early Giant/Leopard devices did not have MEMINFO in DEVINFO. */
return FLASH_PAGE_SIZE;
}
#elif defined(_EFM32_ZERO_FAMILY)
if (SYSTEM_GetProdRev() < 24)
{
if (SYSTEM_GetProdRev() < 24) {
/* Early Zero devices have an incorrect DEVINFO flash page size */
return FLASH_PAGE_SIZE;
}
#endif
#endif
tmp = (DEVINFO->MEMINFO & _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK)
@ -404,7 +427,6 @@ __STATIC_INLINE uint32_t SYSTEM_GetFlashPageSize(void)
return 1 << ((tmp + 10) & 0xFF);
}
#if defined(_DEVINFO_DEVINFOREV_DEVINFOREV_MASK)
/***************************************************************************//**
* @brief
@ -420,7 +442,6 @@ __STATIC_INLINE uint8_t SYSTEM_GetDevinfoRev(void)
}
#endif
/***************************************************************************//**
* @brief
* Get part number of the MCU.
@ -455,7 +476,6 @@ __STATIC_INLINE SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void)
>> _DEVINFO_PART_DEVICE_FAMILY_SHIFT);
}
/***************************************************************************//**
* @brief
* Get the calibration temperature (in degrees Celsius).

110
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_timer.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_timer.h
* @brief Timer/counter (TIMER) peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -78,18 +78,15 @@ extern "C" {
******************************************************************************/
/** Timer compare/capture mode. */
typedef enum
{
typedef enum {
timerCCModeOff = _TIMER_CC_CTRL_MODE_OFF, /**< Channel turned off. */
timerCCModeCapture = _TIMER_CC_CTRL_MODE_INPUTCAPTURE, /**< Input capture. */
timerCCModeCompare = _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE, /**< Output compare. */
timerCCModePWM = _TIMER_CC_CTRL_MODE_PWM /**< Pulse-Width modulation. */
} TIMER_CCMode_TypeDef;
/** Clock select. */
typedef enum
{
typedef enum {
/** Prescaled HFPER clock. */
timerClkSelHFPerClk = _TIMER_CTRL_CLKSEL_PRESCHFPERCLK,
@ -103,10 +100,8 @@ typedef enum
timerClkSelCascade = _TIMER_CTRL_CLKSEL_TIMEROUF
} TIMER_ClkSel_TypeDef;
/** Input capture edge select. */
typedef enum
{
typedef enum {
/** Rising edges detected. */
timerEdgeRising = _TIMER_CC_CTRL_ICEDGE_RISING,
@ -120,10 +115,8 @@ typedef enum
timerEdgeNone = _TIMER_CC_CTRL_ICEDGE_NONE
} TIMER_Edge_TypeDef;
/** Input capture event control. */
typedef enum
{
typedef enum {
/** PRS output pulse, interrupt flag and DMA request set on every capture. */
timerEventEveryEdge = _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE,
/** PRS output pulse, interrupt flag and DMA request set on every second capture. */
@ -140,10 +133,8 @@ typedef enum
timerEventFalling = _TIMER_CC_CTRL_ICEVCTRL_FALLING
} TIMER_Event_TypeDef;
/** Input edge action. */
typedef enum
{
typedef enum {
/** No action taken. */
timerInputActionNone = _TIMER_CTRL_FALLA_NONE,
@ -157,20 +148,16 @@ typedef enum
timerInputActionReloadStart = _TIMER_CTRL_FALLA_RELOADSTART
} TIMER_InputAction_TypeDef;
/** Timer mode. */
typedef enum
{
typedef enum {
timerModeUp = _TIMER_CTRL_MODE_UP, /**< Up-counting. */
timerModeDown = _TIMER_CTRL_MODE_DOWN, /**< Down-counting. */
timerModeUpDown = _TIMER_CTRL_MODE_UPDOWN, /**< Up/down-counting. */
timerModeQDec = _TIMER_CTRL_MODE_QDEC /**< Quadrature decoder. */
} TIMER_Mode_TypeDef;
/** Compare/capture output action. */
typedef enum
{
typedef enum {
/** No action. */
timerOutputActionNone = _TIMER_CC_CTRL_CUFOA_NONE,
@ -184,10 +171,8 @@ typedef enum
timerOutputActionSet = _TIMER_CC_CTRL_CUFOA_SET
} TIMER_OutputAction_TypeDef;
/** Prescaler. */
typedef enum
{
typedef enum {
timerPrescale1 = _TIMER_CTRL_PRESC_DIV1, /**< Divide by 1. */
timerPrescale2 = _TIMER_CTRL_PRESC_DIV2, /**< Divide by 2. */
timerPrescale4 = _TIMER_CTRL_PRESC_DIV4, /**< Divide by 4. */
@ -201,10 +186,8 @@ typedef enum
timerPrescale1024 = _TIMER_CTRL_PRESC_DIV1024 /**< Divide by 1024. */
} TIMER_Prescale_TypeDef;
/** Peripheral Reflex System signal. */
typedef enum
{
typedef enum {
timerPRSSELCh0 = _TIMER_CC_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */
timerPRSSELCh1 = _TIMER_CC_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */
timerPRSSELCh2 = _TIMER_CC_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */
@ -237,8 +220,7 @@ typedef enum
#if defined(_TIMER_DTFC_DTFA_NONE)
/** DT (Dead Time) Fault Actions. */
typedef enum
{
typedef enum {
timerDtiFaultActionNone = _TIMER_DTFC_DTFA_NONE, /**< No action on fault. */
timerDtiFaultActionInactive = _TIMER_DTFC_DTFA_INACTIVE, /**< Set outputs inactive. */
timerDtiFaultActionClear = _TIMER_DTFC_DTFA_CLEAR, /**< Clear outputs. */
@ -251,8 +233,7 @@ typedef enum
******************************************************************************/
/** TIMER initialization structure. */
typedef struct
{
typedef struct {
/** Start counting when init completed. */
bool enable;
@ -332,8 +313,7 @@ typedef struct
#endif
/** TIMER compare/capture initialization structure. */
typedef struct
{
typedef struct {
/** Input capture event control. */
TIMER_Event_TypeDef eventCtrl;
@ -395,8 +375,7 @@ typedef struct
#if defined(_TIMER_DTCTRL_MASK)
/** TIMER Dead Time Insertion (DTI) initialization structure. */
typedef struct
{
typedef struct {
/** Enable DTI or leave it disabled until @ref TIMER_EnableDTI() is called */
bool enable;
@ -451,10 +430,8 @@ typedef struct
/** Fault Action */
TIMER_DtiFaultAction_TypeDef faultAction;
} TIMER_InitDTI_TypeDef;
/** Default config for TIMER DTI init structure. */
#define TIMER_INITDTI_DEFAULT \
{ \
@ -478,12 +455,10 @@ typedef struct
}
#endif /* _TIMER_DTCTRL_MASK */
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
/***************************************************************************//**
* @brief
* Validate the TIMER register block pointer
@ -506,11 +481,26 @@ __STATIC_INLINE bool TIMER_Valid(const TIMER_TypeDef *ref)
#if defined(TIMER3)
|| (ref == TIMER3)
#endif
#if defined(TIMER4)
|| (ref == TIMER4)
#endif
#if defined(TIMER5)
|| (ref == TIMER5)
#endif
#if defined(TIMER6)
|| (ref == TIMER6)
#endif
#if defined(WTIMER0)
|| (ref == WTIMER0)
#endif
#if defined(WTIMER1)
|| (ref == WTIMER1)
#endif
#if defined(WTIMER2)
|| (ref == WTIMER2)
#endif
#if defined(WTIMER3)
|| (ref == WTIMER3)
#endif
;
}
@ -533,8 +523,13 @@ __STATIC_INLINE uint32_t TIMER_MaxCount(const TIMER_TypeDef *ref)
#if defined(WTIMER1)
|| (ref == WTIMER1)
#endif
)
{
#if defined(WTIMER2)
|| (ref == WTIMER2)
#endif
#if defined(WTIMER3)
|| (ref == WTIMER3)
#endif
) {
return 0xFFFFFFFFUL;
}
#else
@ -562,7 +557,6 @@ __STATIC_INLINE uint32_t TIMER_CaptureGet(TIMER_TypeDef *timer, unsigned int ch)
return timer->CC[ch].CCV;
}
/***************************************************************************//**
* @brief
* Set compare value buffer for compare/capture channel when operating in
@ -590,7 +584,6 @@ __STATIC_INLINE void TIMER_CompareBufSet(TIMER_TypeDef *timer,
timer->CC[ch].CCVB = val;
}
/***************************************************************************//**
* @brief
* Set compare value for compare/capture channel when operating in compare
@ -613,7 +606,6 @@ __STATIC_INLINE void TIMER_CompareSet(TIMER_TypeDef *timer,
timer->CC[ch].CCV = val;
}
/***************************************************************************//**
* @brief
* Get TIMER counter value.
@ -629,7 +621,6 @@ __STATIC_INLINE uint32_t TIMER_CounterGet(TIMER_TypeDef *timer)
return timer->CNT;
}
/***************************************************************************//**
* @brief
* Set TIMER counter value.
@ -646,7 +637,6 @@ __STATIC_INLINE void TIMER_CounterSet(TIMER_TypeDef *timer, uint32_t val)
timer->CNT = val;
}
/***************************************************************************//**
* @brief
* Start/stop TIMER.
@ -661,17 +651,13 @@ __STATIC_INLINE void TIMER_Enable(TIMER_TypeDef *timer, bool enable)
{
EFM_ASSERT(TIMER_REF_VALID(timer));
if (enable)
{
if (enable) {
timer->CMD = TIMER_CMD_START;
}
else
{
} else {
timer->CMD = TIMER_CMD_STOP;
}
}
void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init);
void TIMER_InitCC(TIMER_TypeDef *timer,
unsigned int ch,
@ -694,17 +680,13 @@ __STATIC_INLINE void TIMER_EnableDTI(TIMER_TypeDef *timer, bool enable)
{
EFM_ASSERT(TIMER0 == timer);
if (enable)
{
if (enable) {
timer->DTCTRL |= TIMER_DTCTRL_DTEN;
}
else
{
} else {
timer->DTCTRL &= ~TIMER_DTCTRL_DTEN;
}
}
/***************************************************************************//**
* @brief
* Get DTI fault source flags status.
@ -725,7 +707,6 @@ __STATIC_INLINE uint32_t TIMER_GetDTIFault(TIMER_TypeDef *timer)
return timer->DTFAULT;
}
/***************************************************************************//**
* @brief
* Clear DTI fault source flags.
@ -745,7 +726,6 @@ __STATIC_INLINE void TIMER_ClearDTIFault(TIMER_TypeDef *timer, uint32_t flags)
}
#endif /* _TIMER_DTCTRL_MASK */
/***************************************************************************//**
* @brief
* Clear one or more pending TIMER interrupts.
@ -762,7 +742,6 @@ __STATIC_INLINE void TIMER_IntClear(TIMER_TypeDef *timer, uint32_t flags)
timer->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more TIMER interrupts.
@ -779,7 +758,6 @@ __STATIC_INLINE void TIMER_IntDisable(TIMER_TypeDef *timer, uint32_t flags)
timer->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more TIMER interrupts.
@ -801,7 +779,6 @@ __STATIC_INLINE void TIMER_IntEnable(TIMER_TypeDef *timer, uint32_t flags)
timer->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending TIMER interrupt flags.
@ -821,7 +798,6 @@ __STATIC_INLINE uint32_t TIMER_IntGet(TIMER_TypeDef *timer)
return timer->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending TIMER interrupt flags.
@ -853,7 +829,6 @@ __STATIC_INLINE uint32_t TIMER_IntGetEnabled(TIMER_TypeDef *timer)
return timer->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending TIMER interrupts from SW.
@ -918,7 +893,6 @@ __STATIC_INLINE void TIMER_TopBufSet(TIMER_TypeDef *timer, uint32_t val)
timer->TOPB = val;
}
/***************************************************************************//**
* @brief
* Get top value setting for timer.
@ -934,7 +908,6 @@ __STATIC_INLINE uint32_t TIMER_TopGet(TIMER_TypeDef *timer)
return timer->TOP;
}
/***************************************************************************//**
* @brief
* Set top value for timer.
@ -951,7 +924,6 @@ __STATIC_INLINE void TIMER_TopSet(TIMER_TypeDef *timer, uint32_t val)
timer->TOP = val;
}
#if defined(TIMER_DTLOCK_LOCKKEY_UNLOCK)
/***************************************************************************//**
* @brief

206
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h
View File

@ -2,9 +2,9 @@
* @file em_usart.h
* @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART)
* peripheral API
* @version 5.1.2
* @version 5.3.3
*******************************************************************************
* @section License
* # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@ -31,7 +31,6 @@
*
******************************************************************************/
#ifndef EM_USART_H
#define EM_USART_H
@ -102,8 +101,7 @@ extern "C" {
******************************************************************************/
/** Databit selection. */
typedef enum
{
typedef enum {
usartDatabits4 = USART_FRAME_DATABITS_FOUR, /**< 4 databits (not available for UART). */
usartDatabits5 = USART_FRAME_DATABITS_FIVE, /**< 5 databits (not available for UART). */
usartDatabits6 = USART_FRAME_DATABITS_SIX, /**< 6 databits (not available for UART). */
@ -119,10 +117,8 @@ typedef enum
usartDatabits16 = USART_FRAME_DATABITS_SIXTEEN /**< 16 databits (not available for UART). */
} USART_Databits_TypeDef;
/** Enable selection. */
typedef enum
{
typedef enum {
/** Disable both receiver and transmitter. */
usartDisable = 0x0,
@ -136,39 +132,40 @@ typedef enum
usartEnable = (USART_CMD_RXEN | USART_CMD_TXEN)
} USART_Enable_TypeDef;
/** Oversampling selection, used for asynchronous operation. */
typedef enum
{
typedef enum {
usartOVS16 = USART_CTRL_OVS_X16, /**< 16x oversampling (normal). */
usartOVS8 = USART_CTRL_OVS_X8, /**< 8x oversampling. */
usartOVS6 = USART_CTRL_OVS_X6, /**< 6x oversampling. */
usartOVS4 = USART_CTRL_OVS_X4 /**< 4x oversampling. */
} USART_OVS_TypeDef;
/** Parity selection, mainly used for asynchronous operation. */
typedef enum
{
typedef enum {
usartNoParity = USART_FRAME_PARITY_NONE, /**< No parity. */
usartEvenParity = USART_FRAME_PARITY_EVEN, /**< Even parity. */
usartOddParity = USART_FRAME_PARITY_ODD /**< Odd parity. */
} USART_Parity_TypeDef;
/** Stopbits selection, used for asynchronous operation. */
typedef enum
{
typedef enum {
usartStopbits0p5 = USART_FRAME_STOPBITS_HALF, /**< 0.5 stopbits. */
usartStopbits1 = USART_FRAME_STOPBITS_ONE, /**< 1 stopbits. */
usartStopbits1p5 = USART_FRAME_STOPBITS_ONEANDAHALF, /**< 1.5 stopbits. */
usartStopbits2 = USART_FRAME_STOPBITS_TWO /**< 2 stopbits. */
} USART_Stopbits_TypeDef;
#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK)
typedef enum {
usartHwFlowControlNone = 0,
usartHwFlowControlCts = USART_ROUTEPEN_CTSPEN,
usartHwFlowControlRts = USART_ROUTEPEN_RTSPEN,
usartHwFlowControlCtsAndRts = USART_ROUTEPEN_CTSPEN | USART_ROUTEPEN_RTSPEN,
} USART_HwFlowControl_TypeDef;
#endif
/** Clock polarity/phase mode. */
typedef enum
{
typedef enum {
/** Clock idle low, sample on rising edge. */
usartClockMode0 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLELEADING,
@ -182,10 +179,8 @@ typedef enum
usartClockMode3 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLETRAILING
} USART_ClockMode_TypeDef;
/** Pulse width selection for IrDA mode. */
typedef enum
{
typedef enum {
/** IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 */
usartIrDAPwONE = USART_IRCTRL_IRPW_ONE,
@ -199,10 +194,8 @@ typedef enum
usartIrDAPwFOUR = USART_IRCTRL_IRPW_FOUR
} USART_IrDAPw_Typedef;
/** PRS channel selection for IrDA mode. */
typedef enum
{
typedef enum {
usartIrDAPrsCh0 = USART_IRCTRL_IRPRSSEL_PRSCH0, /**< PRS channel 0 */
usartIrDAPrsCh1 = USART_IRCTRL_IRPRSSEL_PRSCH1, /**< PRS channel 1 */
usartIrDAPrsCh2 = USART_IRCTRL_IRPRSSEL_PRSCH2, /**< PRS channel 2 */
@ -223,8 +216,7 @@ typedef enum
#if defined(_USART_I2SCTRL_MASK)
/** I2S format selection. */
typedef enum
{
typedef enum {
usartI2sFormatW32D32 = USART_I2SCTRL_FORMAT_W32D32, /**< 32-bit word, 32-bit data */
usartI2sFormatW32D24M = USART_I2SCTRL_FORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked */
usartI2sFormatW32D24 = USART_I2SCTRL_FORMAT_W32D24, /**< 32-bit word, 24-bit data */
@ -236,8 +228,7 @@ typedef enum
} USART_I2sFormat_TypeDef;
/** I2S frame data justify. */
typedef enum
{
typedef enum {
usartI2sJustifyLeft = USART_I2SCTRL_JUSTIFY_LEFT, /**< Data is left-justified within the frame */
usartI2sJustifyRight = USART_I2SCTRL_JUSTIFY_RIGHT /**< Data is right-justified within the frame */
} USART_I2sJustify_TypeDef;
@ -245,8 +236,7 @@ typedef enum
#if defined(_USART_INPUT_MASK)
/** USART Rx input PRS selection. */
typedef enum
{
typedef enum {
usartPrsRxCh0 = USART_INPUT_RXPRSSEL_PRSCH0, /**< PRSCH0 selected as USART_INPUT */
usartPrsRxCh1 = USART_INPUT_RXPRSSEL_PRSCH1, /**< PRSCH1 selected as USART_INPUT */
usartPrsRxCh2 = USART_INPUT_RXPRSSEL_PRSCH2, /**< PRSCH2 selected as USART_INPUT */
@ -269,8 +259,7 @@ typedef enum
#endif
/** USART PRS Transmit Trigger Channels */
typedef enum
{
typedef enum {
usartPrsTriggerCh0 = USART_TRIGCTRL_TSEL_PRSCH0, /**< PRSCH0 selected as USART Trigger */
usartPrsTriggerCh1 = USART_TRIGCTRL_TSEL_PRSCH1, /**< PRSCH0 selected as USART Trigger */
usartPrsTriggerCh2 = USART_TRIGCTRL_TSEL_PRSCH2, /**< PRSCH0 selected as USART Trigger */
@ -289,8 +278,7 @@ typedef enum
******************************************************************************/
/** Asynchronous mode init structure. */
typedef struct
{
typedef struct {
/** Specifies whether TX and/or RX shall be enabled when init completed. */
USART_Enable_TypeDef enable;
@ -334,11 +322,13 @@ typedef struct
/** Auto CS setup time in baud cycles */
uint8_t autoCsSetup;
#endif
#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK)
USART_HwFlowControl_TypeDef hwFlowControl;
#endif
} USART_InitAsync_TypeDef;
/** USART PRS trigger enable */
typedef struct
{
typedef struct {
#if defined(USART_TRIGCTRL_AUTOTXTEN)
/** Enable AUTOTX */
bool autoTxTriggerEnable;
@ -352,6 +342,54 @@ typedef struct
} USART_PrsTriggerInit_TypeDef;
/** Default config for USART async init structure. */
#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK)
#if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
#define USART_INITASYNC_DEFAULT \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartNoParity, /* No parity. */ \
usartStopbits1, /* 1 stopbit. */ \
false, /* Do not disable majority vote. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0, /* PRS channel 0. */ \
false, /* Auto CS functionality enable/disable switch */ \
0, /* Auto CS Hold cycles */ \
0, /* Auto CS Setup cycles */ \
usartHwFlowControlNone /* No HW flow control */ \
}
#elif defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
#define USART_INITASYNC_DEFAULT \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartNoParity, /* No parity. */ \
usartStopbits1, /* 1 stopbit. */ \
false, /* Do not disable majority vote. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0, /* PRS channel 0. */ \
usartHwFlowControlNone /* No HW flow control */ \
}
#else
#define USART_INITASYNC_DEFAULT \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartNoParity, /* No parity. */ \
usartStopbits1, /* 1 stopbit. */ \
usartHwFlowControlNone /* No HW flow control */ \
}
#endif
#else
#if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
#define USART_INITASYNC_DEFAULT \
{ \
@ -395,6 +433,7 @@ typedef struct
usartStopbits1 /* 1 stopbit. */ \
}
#endif
#endif
/** Default config for USART PRS triggering structure. */
#if defined(USART_TRIGCTRL_AUTOTXTEN)
@ -415,8 +454,7 @@ typedef struct
#endif
/** Synchronous mode init structure. */
typedef struct
{
typedef struct {
/** Specifies whether TX and/or RX shall be enabled when init completed. */
USART_Enable_TypeDef enable;
@ -507,10 +545,8 @@ typedef struct
}
#endif
/** IrDA mode init structure. Inherited from asynchronous mode init structure */
typedef struct
{
typedef struct {
/** General Async initialization structure. */
USART_InitAsync_TypeDef async;
@ -533,8 +569,76 @@ typedef struct
USART_IrDAPrsSel_Typedef irPrsSel;
} USART_InitIrDA_TypeDef;
/** Default config for IrDA mode init structure. */
#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK)
#if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
#define USART_INITIRDA_DEFAULT \
{ \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartEvenParity,/* Even parity. */ \
usartStopbits1, /* 1 stopbit. */ \
false, /* Do not disable majority vote. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0, /* PRS channel 0. */ \
false, /* Auto CS functionality enable/disable switch */ \
0, /* Auto CS Hold cycles */ \
0, /* Auto CS Setup cycles */ \
usartHwFlowControlNone /* No HW flow control */ \
}, \
false, /* Rx invert disabled. */ \
false, /* Filtering disabled. */ \
usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
false, /* Routing to PRS is disabled. */ \
usartIrDAPrsCh0 /* PRS channel 0. */ \
}
#elif defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
#define USART_INITIRDA_DEFAULT \
{ \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartEvenParity,/* Even parity. */ \
usartStopbits1, /* 1 stopbit. */ \
false, /* Do not disable majority vote. */ \
false, /* Not USART PRS input mode. */ \
usartPrsRxCh0, /* PRS channel 0. */ \
usartHwFlowControlNone /* No HW flow control */ \
}, \
false, /* Rx invert disabled. */ \
false, /* Filtering disabled. */ \
usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
false, /* Routing to PRS is disabled. */ \
usartIrDAPrsCh0 /* PRS channel 0. */ \
}
#else
#define USART_INITIRDA_DEFAULT \
{ \
{ \
usartEnable, /* Enable RX/TX when init completed. */ \
0, /* Use current configured reference clock for configuring baudrate. */ \
115200, /* 115200 bits/s. */ \
usartOVS16, /* 16x oversampling. */ \
usartDatabits8, /* 8 databits. */ \
usartEvenParity,/* Even parity. */ \
usartStopbits1, /* 1 stopbit. */ \
usartHwFlowControlNone /* No HW flow control */ \
}, \
false, /* Rx invert disabled. */ \
false, /* Filtering disabled. */ \
usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
false, /* Routing to PRS is disabled. */ \
usartIrDAPrsCh0 /* PRS channel 0. */ \
}
#endif
#else
#if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
#define USART_INITIRDA_DEFAULT \
{ \
@ -599,11 +703,11 @@ typedef struct
usartIrDAPrsCh0 /* PRS channel 0. */ \
}
#endif
#endif
#if defined(_USART_I2SCTRL_MASK)
/** I2S mode init structure. Inherited from synchronous mode init structure */
typedef struct
{
typedef struct {
/** General Sync initialization structure. */
USART_InitSync_TypeDef sync;
@ -625,7 +729,6 @@ typedef struct
bool mono;
} USART_InitI2s_TypeDef;
/** Default config for I2S mode init structure. */
#if defined(_USART_TIMING_CSHOLD_MASK)
#define USART_INITI2S_DEFAULT \
@ -759,7 +862,6 @@ __STATIC_INLINE void USART_IntClear(USART_TypeDef *usart, uint32_t flags)
usart->IFC = flags;
}
/***************************************************************************//**
* @brief
* Disable one or more USART interrupts.
@ -776,7 +878,6 @@ __STATIC_INLINE void USART_IntDisable(USART_TypeDef *usart, uint32_t flags)
usart->IEN &= ~flags;
}
/***************************************************************************//**
* @brief
* Enable one or more USART interrupts.
@ -798,7 +899,6 @@ __STATIC_INLINE void USART_IntEnable(USART_TypeDef *usart, uint32_t flags)
usart->IEN |= flags;
}
/***************************************************************************//**
* @brief
* Get pending USART interrupt flags.
@ -818,7 +918,6 @@ __STATIC_INLINE uint32_t USART_IntGet(USART_TypeDef *usart)
return usart->IF;
}
/***************************************************************************//**
* @brief
* Get enabled and pending USART interrupt flags.
@ -850,7 +949,6 @@ __STATIC_INLINE uint32_t USART_IntGetEnabled(USART_TypeDef *usart)
return usart->IF & ien;
}
/***************************************************************************//**
* @brief
* Set one or more pending USART interrupts from SW.
@ -867,7 +965,6 @@ __STATIC_INLINE void USART_IntSet(USART_TypeDef *usart, uint32_t flags)
usart->IFS = flags;
}
/***************************************************************************//**
* @brief
* Get USART STATUS register.
@ -890,7 +987,6 @@ uint16_t USART_RxDouble(USART_TypeDef *usart);
uint32_t USART_RxDoubleExt(USART_TypeDef *usart);
uint16_t USART_RxExt(USART_TypeDef *usart);
/***************************************************************************//**
* @brief
* Receive one 4-8 bit frame, (or part of 10-16 bit frame).
@ -924,7 +1020,6 @@ __STATIC_INLINE uint8_t USART_RxDataGet(USART_TypeDef *usart)
return (uint8_t)usart->RXDATA;
}
/***************************************************************************//**
* @brief
* Receive two 4-8 bit frames, or one 10-16 bit frame.
@ -962,7 +1057,6 @@ __STATIC_INLINE uint16_t USART_RxDoubleGet(USART_TypeDef *usart)
return (uint16_t)usart->RXDOUBLE;
}
/***************************************************************************//**
* @brief
* Receive two 4-9 bit frames, or one 10-16 bit frame with extended
@ -998,7 +1092,6 @@ __STATIC_INLINE uint32_t USART_RxDoubleXGet(USART_TypeDef *usart)
return usart->RXDOUBLEX;
}
/***************************************************************************//**
* @brief
* Receive one 4-9 bit frame, (or part of 10-16 bit frame) with extended
@ -1039,7 +1132,6 @@ void USART_TxDouble(USART_TypeDef *usart, uint16_t data);
void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data);
void USART_TxExt(USART_TypeDef *usart, uint16_t data);
/** @} (end addtogroup USART) */
/** @} (end addtogroup emlib) */

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