diff --git a/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S b/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S
deleted file mode 100644
index d37f889191..0000000000
--- a/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S
+++ /dev/null
@@ -1,94 +0,0 @@
-/* Copyright (c) 2009 - 2012 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------
- * Functions
- *---------------------------------------------------------------------------*/
- .text
- .global __v7_all_cache
-/*
- * __STATIC_ASM void __v7_all_cache(uint32_t op) {
- */
-__v7_all_cache:
- .arm
-
- PUSH {R4-R11}
-
- MRC p15, 1, R6, c0, c0, 1 /* Read CLIDR */
- ANDS R3, R6, #0x07000000 /* Extract coherency level */
- MOV R3, R3, LSR #23 /* Total cache levels << 1 */
- BEQ Finished /* If 0, no need to clean */
-
- MOV R10, #0 /* R10 holds current cache level << 1 */
-Loop1: ADD R2, R10, R10, LSR #1 /* R2 holds cache "Set" position */
- MOV R1, R6, LSR R2 /* Bottom 3 bits are the Cache-type for this level */
- AND R1, R1, #7 /* Isolate those lower 3 bits */
- CMP R1, #2
- BLT Skip /* No cache or only instruction cache at this level */
-
- MCR p15, 2, R10, c0, c0, 0 /* Write the Cache Size selection register */
- ISB /* ISB to sync the change to the CacheSizeID reg */
- MRC p15, 1, R1, c0, c0, 0 /* Reads current Cache Size ID register */
- AND R2, R1, #7 /* Extract the line length field */
- ADD R2, R2, #4 /* Add 4 for the line length offset (log2 16 bytes) */
- LDR R4, =0x3FF
- ANDS R4, R4, R1, LSR #3 /* R4 is the max number on the way size (right aligned) */
- CLZ R5, R4 /* R5 is the bit position of the way size increment */
- LDR R7, =0x7FFF
- ANDS R7, R7, R1, LSR #13 /* R7 is the max number of the index size (right aligned) */
-
-Loop2: MOV R9, R4 /* R9 working copy of the max way size (right aligned) */
-
-Loop3: ORR R11, R10, R9, LSL R5 /* Factor in the Way number and cache number into R11 */
- ORR R11, R11, R7, LSL R2 /* Factor in the Set number */
- CMP R0, #0
- BNE Dccsw
- MCR p15, 0, R11, c7, c6, 2 /* DCISW. Invalidate by Set/Way */
- B cont
-Dccsw: CMP R0, #1
- BNE Dccisw
- MCR p15, 0, R11, c7, c10, 2 /* DCCSW. Clean by Set/Way */
- B cont
-Dccisw: MCR p15, 0, R11, c7, c14, 2 /* DCCISW, Clean and Invalidate by Set/Way */
-cont: SUBS R9, R9, #1 /* Decrement the Way number */
- BGE Loop3
- SUBS R7, R7, #1 /* Decrement the Set number */
- BGE Loop2
-Skip: ADD R10, R10, #2 /* increment the cache number */
- CMP R3, R10
- BGT Loop1
-
-Finished:
- DSB
- POP {R4-R11}
- BX lr
-
-
- .END
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.s b/cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.s
deleted file mode 100644
index 00352787a2..0000000000
--- a/cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.s
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Copyright (c) 2009 - 2012 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------
- * Functions
- *---------------------------------------------------------------------------*/
- SECTION `.text`:CODE:NOROOT(2)
- arm
- PUBLIC __v7_all_cache
-/*
- * __STATIC_ASM void __v7_all_cache(uint32_t op) {
- */
-
-__v7_all_cache:
-
-
- PUSH {R4-R11}
-
- MRC p15, 1, R6, c0, c0, 1 /* Read CLIDR */
- ANDS R3, R6, #0x07000000 /* Extract coherency level */
- MOV R3, R3, LSR #23 /* Total cache levels << 1 */
- BEQ Finished /* If 0, no need to clean */
-
- MOV R10, #0 /* R10 holds current cache level << 1 */
-Loop1: ADD R2, R10, R10, LSR #1 /* R2 holds cache "Set" position */
- MOV R1, R6, LSR R2 /* Bottom 3 bits are the Cache-type for this level */
- AND R1, R1, #7 /* Isolate those lower 3 bits */
- CMP R1, #2
- BLT Skip /* No cache or only instruction cache at this level */
-
- MCR p15, 2, R10, c0, c0, 0 /* Write the Cache Size selection register */
- ISB /* ISB to sync the change to the CacheSizeID reg */
- MRC p15, 1, R1, c0, c0, 0 /* Reads current Cache Size ID register */
- AND R2, R1, #7 /* Extract the line length field */
- ADD R2, R2, #4 /* Add 4 for the line length offset (log2 16 bytes) */
- LDR R4, =0x3FF
- ANDS R4, R4, R1, LSR #3 /* R4 is the max number on the way size (right aligned) */
- CLZ R5, R4 /* R5 is the bit position of the way size increment */
- LDR R7, =0x7FFF
- ANDS R7, R7, R1, LSR #13 /* R7 is the max number of the index size (right aligned) */
-
-Loop2: MOV R9, R4 /* R9 working copy of the max way size (right aligned) */
-
-Loop3: ORR R11, R10, R9, LSL R5 /* Factor in the Way number and cache number into R11 */
- ORR R11, R11, R7, LSL R2 /* Factor in the Set number */
- CMP R0, #0
- BNE Dccsw
- MCR p15, 0, R11, c7, c6, 2 /* DCISW. Invalidate by Set/Way */
- B cont
-Dccsw: CMP R0, #1
- BNE Dccisw
- MCR p15, 0, R11, c7, c10, 2 /* DCCSW. Clean by Set/Way */
- B cont
-Dccisw: MCR p15, 0, R11, c7, c14, 2 /* DCCISW, Clean and Invalidate by Set/Way */
-cont: SUBS R9, R9, #1 /* Decrement the Way number */
- BGE Loop3
- SUBS R7, R7, #1 /* Decrement the Set number */
- BGE Loop2
-Skip: ADD R10, R10, #2 /* increment the cache number */
- CMP R3, R10
- BGT Loop1
-
-Finished:
- DSB
- POP {R4-R11}
- BX lr
-
-
- END
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
-
diff --git a/cmsis/TOOLCHAIN_IAR/cmain.S b/cmsis/TOOLCHAIN_IAR/cmain.S
deleted file mode 100644
index 7395d3fa57..0000000000
--- a/cmsis/TOOLCHAIN_IAR/cmain.S
+++ /dev/null
@@ -1,81 +0,0 @@
-/**************************************************
- *
- * Part two of the system initialization code, contains C-level
- * initialization, thumb-2 only variant.
- *
- * Copyright 2006 IAR Systems. All rights reserved.
- *
- * $Revision: 59783 $
- *
- **************************************************/
-
-
-; --------------------------------------------------
-; Module ?cmain, C-level initialization.
-;
-
-
- SECTION SHT$$PREINIT_ARRAY:CONST:NOROOT(2)
- SECTION SHT$$INIT_ARRAY:CONST:NOROOT(2)
-
- SECTION .text:CODE:NOROOT(2)
-
- PUBLIC __cmain
- ;; Keep ?main for legacy reasons, it is accessed in countless instances of cstartup.s around the world...
- PUBLIC ?main
- EXTWEAK __iar_data_init3
- EXTWEAK __iar_argc_argv
- EXTERN __low_level_init
- EXTERN __call_ctors
- EXTERN main
- EXTERN exit
- EXTERN __iar_dynamic_initialization
- EXTERN mbed_sdk_init
- EXTERN SystemInit
-
- THUMB
-__cmain:
-?main:
-
-; Initialize segments.
-; __segment_init and __low_level_init are assumed to use the same
-; instruction set and to be reachable by BL from the ICODE segment
-; (it is safest to link them in segment ICODE).
-
- FUNCALL __cmain, __low_level_init
- bl __low_level_init
- cmp r0,#0
- beq ?l1
- FUNCALL __cmain, __iar_data_init3
- bl __iar_data_init3
- MOVS r0,#0 ; No parameters
- FUNCALL __cmain, mbed_sdk_init
- BL mbed_sdk_init
- MOVS r0,#0 ; No parameters
- FUNCALL __cmain, __iar_dynamic_initialization
- BL __iar_dynamic_initialization ; C++ dynamic initialization
-
-?l1:
- REQUIRE ?l3
-
- SECTION .text:CODE:NOROOT(2)
-
- PUBLIC _main
- PUBLIC _call_main
- THUMB
-
-__iar_init$$done: ; Copy initialization is done
-
-?l3:
-_call_main:
- MOVS r0,#0 ; No parameters
- FUNCALL __cmain, __iar_argc_argv
- BL __iar_argc_argv ; Maybe setup command line
-
- FUNCALL __cmain, main
- BL main
-_main:
- FUNCALL __cmain, exit
- BL exit
-
- END
diff --git a/cmsis/arm_common_tables.h b/cmsis/arm_common_tables.h
deleted file mode 100644
index 039cc3d66b..0000000000
--- a/cmsis/arm_common_tables.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
-*
-* $Date: 19. March 2015
-* $Revision: V.1.4.5
-*
-* Project: CMSIS DSP Library
-* Title: arm_common_tables.h
-*
-* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
-*
-* Target Processor: Cortex-M4/Cortex-M3
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-* - Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* - Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in
-* the documentation and/or other materials provided with the
-* distribution.
-* - Neither the name of ARM LIMITED nor the names of its contributors
-* may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-#ifndef _ARM_COMMON_TABLES_H
-#define _ARM_COMMON_TABLES_H
-
-#include "arm_math.h"
-
-extern const uint16_t armBitRevTable[1024];
-extern const q15_t armRecipTableQ15[64];
-extern const q31_t armRecipTableQ31[64];
-//extern const q31_t realCoefAQ31[1024];
-//extern const q31_t realCoefBQ31[1024];
-extern const float32_t twiddleCoef_16[32];
-extern const float32_t twiddleCoef_32[64];
-extern const float32_t twiddleCoef_64[128];
-extern const float32_t twiddleCoef_128[256];
-extern const float32_t twiddleCoef_256[512];
-extern const float32_t twiddleCoef_512[1024];
-extern const float32_t twiddleCoef_1024[2048];
-extern const float32_t twiddleCoef_2048[4096];
-extern const float32_t twiddleCoef_4096[8192];
-#define twiddleCoef twiddleCoef_4096
-extern const q31_t twiddleCoef_16_q31[24];
-extern const q31_t twiddleCoef_32_q31[48];
-extern const q31_t twiddleCoef_64_q31[96];
-extern const q31_t twiddleCoef_128_q31[192];
-extern const q31_t twiddleCoef_256_q31[384];
-extern const q31_t twiddleCoef_512_q31[768];
-extern const q31_t twiddleCoef_1024_q31[1536];
-extern const q31_t twiddleCoef_2048_q31[3072];
-extern const q31_t twiddleCoef_4096_q31[6144];
-extern const q15_t twiddleCoef_16_q15[24];
-extern const q15_t twiddleCoef_32_q15[48];
-extern const q15_t twiddleCoef_64_q15[96];
-extern const q15_t twiddleCoef_128_q15[192];
-extern const q15_t twiddleCoef_256_q15[384];
-extern const q15_t twiddleCoef_512_q15[768];
-extern const q15_t twiddleCoef_1024_q15[1536];
-extern const q15_t twiddleCoef_2048_q15[3072];
-extern const q15_t twiddleCoef_4096_q15[6144];
-extern const float32_t twiddleCoef_rfft_32[32];
-extern const float32_t twiddleCoef_rfft_64[64];
-extern const float32_t twiddleCoef_rfft_128[128];
-extern const float32_t twiddleCoef_rfft_256[256];
-extern const float32_t twiddleCoef_rfft_512[512];
-extern const float32_t twiddleCoef_rfft_1024[1024];
-extern const float32_t twiddleCoef_rfft_2048[2048];
-extern const float32_t twiddleCoef_rfft_4096[4096];
-
-
-/* floating-point bit reversal tables */
-#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
-#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
-#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
-#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
-#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
-#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
-#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
-#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
-#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
-
-/* fixed-point bit reversal tables */
-#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
-#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
-#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
-#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
-#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
-#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
-#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
-#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
-#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
-
-/* Tables for Fast Math Sine and Cosine */
-extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
-extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
-extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
-
-#endif /* ARM_COMMON_TABLES_H */
diff --git a/cmsis/arm_const_structs.h b/cmsis/arm_const_structs.h
deleted file mode 100644
index 726d06eb69..0000000000
--- a/cmsis/arm_const_structs.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
-*
-* $Date: 19. March 2015
-* $Revision: V.1.4.5
-*
-* Project: CMSIS DSP Library
-* Title: arm_const_structs.h
-*
-* Description: This file has constant structs that are initialized for
-* user convenience. For example, some can be given as
-* arguments to the arm_cfft_f32() function.
-*
-* Target Processor: Cortex-M4/Cortex-M3
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-* - Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* - Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in
-* the documentation and/or other materials provided with the
-* distribution.
-* - Neither the name of ARM LIMITED nor the names of its contributors
-* may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-#ifndef _ARM_CONST_STRUCTS_H
-#define _ARM_CONST_STRUCTS_H
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
-
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
-
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
-
-#endif
diff --git a/cmsis/core_ca9.h b/cmsis/core_ca9.h
deleted file mode 100644
index c7c402d750..0000000000
--- a/cmsis/core_ca9.h
+++ /dev/null
@@ -1,276 +0,0 @@
-/**************************************************************************//**
- * @file core_ca9.h
- * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
- * @version
- * @date 25 March 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2012 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CA9_H_GENERIC
-#define __CORE_CA9_H_GENERIC
-
-
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_A9
- @{
- */
-
-/* CMSIS CA9 definitions */
-#define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
-#define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
- __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_A (0x09) /*!< Cortex-A Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
- #define __STATIC_ASM static __asm
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
- #define __STATIC_ASM static __asm
-
-#include
-inline uint32_t __get_PSR(void) {
- __ASM("mrs r0, cpsr");
-}
-
-#elif defined ( __TMS470__ )
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
- #define __STATIC_INLINE static inline
- #define __STATIC_ASM static __asm
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
- #define __STATIC_ASM static __asm
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
- #define __STATIC_ASM static __asm
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __TMS470__ )
- #if defined __TI_VFP_SUPPORT__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-#endif
-
-#include /*!< standard types definitions */
-#include "core_caInstr.h" /*!< Core Instruction Access */
-#include "core_caFunc.h" /*!< Core Function Access */
-#include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
-
-#endif /* __CORE_CA9_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CA9_H_DEPENDANT
-#define __CORE_CA9_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CA9_REV
- #define __CA9_REV 0x0000
- #warning "__CA9_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 1
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 1
- #endif
-
- #if __Vendor_SysTickConfig == 0
- #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- IO Type Qualifiers are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/*@} end of group Cortex_A9 */
-
-
-/*******************************************************************************
- * Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-A processor based devices.
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-
-/*@} end of group CMSIS_CORE */
-
-/*@} end of CMSIS_Core_FPUFunctions */
-
-
-#endif /* __CORE_CA9_H_GENERIC */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-
-
-#endif
diff --git a/cmsis/core_caFunc.h b/cmsis/core_caFunc.h
deleted file mode 100644
index 6e473214b6..0000000000
--- a/cmsis/core_caFunc.h
+++ /dev/null
@@ -1,1444 +0,0 @@
-/**************************************************************************//**
- * @file core_caFunc.h
- * @brief CMSIS Cortex-A Core Function Access Header File
- * @version V3.10
- * @date 30 Oct 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CAFUNC_H__
-#define __CORE_CAFUNC_H__
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-#define MODE_USR 0x10
-#define MODE_FIQ 0x11
-#define MODE_IRQ 0x12
-#define MODE_SVC 0x13
-#define MODE_MON 0x16
-#define MODE_ABT 0x17
-#define MODE_HYP 0x1A
-#define MODE_UND 0x1B
-#define MODE_SYS 0x1F
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
- register uint32_t __regAPSR __ASM("apsr");
- return(__regAPSR);
-}
-
-
-/** \brief Get CPSR Register
-
- This function returns the content of the CPSR Register.
-
- \return CPSR Register value
- */
-__STATIC_INLINE uint32_t __get_CPSR(void)
-{
- register uint32_t __regCPSR __ASM("cpsr");
- return(__regCPSR);
-}
-
-/** \brief Set Stack Pointer
-
- This function assigns the given value to the current stack pointer.
-
- \param [in] topOfStack Stack Pointer value to set
- */
-register uint32_t __regSP __ASM("sp");
-__STATIC_INLINE void __set_SP(uint32_t topOfStack)
-{
- __regSP = topOfStack;
-}
-
-
-/** \brief Get link register
-
- This function returns the value of the link register
-
- \return Value of link register
- */
-register uint32_t __reglr __ASM("lr");
-__STATIC_INLINE uint32_t __get_LR(void)
-{
- return(__reglr);
-}
-
-/** \brief Set link register
-
- This function sets the value of the link register
-
- \param [in] lr LR value to set
- */
-__STATIC_INLINE void __set_LR(uint32_t lr)
-{
- __reglr = lr;
-}
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the USR/SYS Stack Pointer (PSP).
-
- \param [in] topOfProcStack USR/SYS Stack Pointer value to set
- */
-__STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
-{
- ARM
- PRESERVE8
-
- BIC R0, R0, #7 ;ensure stack is 8-byte aligned
- MRS R1, CPSR
- CPS #MODE_SYS ;no effect in USR mode
- MOV SP, R0
- MSR CPSR_c, R1 ;no effect in USR mode
- ISB
- BX LR
-
-}
-
-/** \brief Set User Mode
-
- This function changes the processor state to User Mode
- */
-__STATIC_ASM void __set_CPS_USR(void)
-{
- ARM
-
- CPS #MODE_USR
- BX LR
-}
-
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq
-
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- return(__regfpscr);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- __regfpscr = (fpscr);
-#endif
-}
-
-/** \brief Get FPEXC
-
- This function returns the current value of the Floating Point Exception Control register.
-
- \return Floating Point Exception Control register value
- */
-__STATIC_INLINE uint32_t __get_FPEXC(void)
-{
-#if (__FPU_PRESENT == 1)
- register uint32_t __regfpexc __ASM("fpexc");
- return(__regfpexc);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPEXC
-
- This function assigns the given value to the Floating Point Exception Control register.
-
- \param [in] fpscr Floating Point Exception Control value to set
- */
-__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
-{
-#if (__FPU_PRESENT == 1)
- register uint32_t __regfpexc __ASM("fpexc");
- __regfpexc = (fpexc);
-#endif
-}
-
-/** \brief Get CPACR
-
- This function returns the current value of the Coprocessor Access Control register.
-
- \return Coprocessor Access Control register value
- */
-__STATIC_INLINE uint32_t __get_CPACR(void)
-{
- register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
- return __regCPACR;
-}
-
-/** \brief Set CPACR
-
- This function assigns the given value to the Coprocessor Access Control register.
-
- \param [in] cpacr Coprocessor Acccess Control value to set
- */
-__STATIC_INLINE void __set_CPACR(uint32_t cpacr)
-{
- register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
- __regCPACR = cpacr;
- __ISB();
-}
-
-/** \brief Get CBAR
-
- This function returns the value of the Configuration Base Address register.
-
- \return Configuration Base Address register value
- */
-__STATIC_INLINE uint32_t __get_CBAR() {
- register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
- return(__regCBAR);
-}
-
-/** \brief Get TTBR0
-
- This function returns the value of the Translation Table Base Register 0.
-
- \return Translation Table Base Register 0 value
- */
-__STATIC_INLINE uint32_t __get_TTBR0() {
- register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
- return(__regTTBR0);
-}
-
-/** \brief Set TTBR0
-
- This function assigns the given value to the Translation Table Base Register 0.
-
- \param [in] ttbr0 Translation Table Base Register 0 value to set
- */
-__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
- register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
- __regTTBR0 = ttbr0;
- __ISB();
-}
-
-/** \brief Get DACR
-
- This function returns the value of the Domain Access Control Register.
-
- \return Domain Access Control Register value
- */
-__STATIC_INLINE uint32_t __get_DACR() {
- register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
- return(__regDACR);
-}
-
-/** \brief Set DACR
-
- This function assigns the given value to the Domain Access Control Register.
-
- \param [in] dacr Domain Access Control Register value to set
- */
-__STATIC_INLINE void __set_DACR(uint32_t dacr) {
- register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
- __regDACR = dacr;
- __ISB();
-}
-
-/******************************** Cache and BTAC enable ****************************************************/
-
-/** \brief Set SCTLR
-
- This function assigns the given value to the System Control Register.
-
- \param [in] sctlr System Control Register value to set
- */
-__STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
-{
- register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
- __regSCTLR = sctlr;
-}
-
-/** \brief Get SCTLR
-
- This function returns the value of the System Control Register.
-
- \return System Control Register value
- */
-__STATIC_INLINE uint32_t __get_SCTLR() {
- register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
- return(__regSCTLR);
-}
-
-/** \brief Enable Caches
-
- Enable Caches
- */
-__STATIC_INLINE void __enable_caches(void) {
- // Set I bit 12 to enable I Cache
- // Set C bit 2 to enable D Cache
- __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
-}
-
-/** \brief Disable Caches
-
- Disable Caches
- */
-__STATIC_INLINE void __disable_caches(void) {
- // Clear I bit 12 to disable I Cache
- // Clear C bit 2 to disable D Cache
- __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
- __ISB();
-}
-
-/** \brief Enable BTAC
-
- Enable BTAC
- */
-__STATIC_INLINE void __enable_btac(void) {
- // Set Z bit 11 to enable branch prediction
- __set_SCTLR( __get_SCTLR() | (1 << 11));
- __ISB();
-}
-
-/** \brief Disable BTAC
-
- Disable BTAC
- */
-__STATIC_INLINE void __disable_btac(void) {
- // Clear Z bit 11 to disable branch prediction
- __set_SCTLR( __get_SCTLR() & ~(1 << 11));
-}
-
-
-/** \brief Enable MMU
-
- Enable MMU
- */
-__STATIC_INLINE void __enable_mmu(void) {
- // Set M bit 0 to enable the MMU
- // Set AFE bit to enable simplified access permissions model
- // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
- __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
- __ISB();
-}
-
-/** \brief Disable MMU
-
- Disable MMU
- */
-__STATIC_INLINE void __disable_mmu(void) {
- // Clear M bit 0 to disable the MMU
- __set_SCTLR( __get_SCTLR() & ~1);
- __ISB();
-}
-
-/******************************** TLB maintenance operations ************************************************/
-/** \brief Invalidate the whole tlb
-
- TLBIALL. Invalidate the whole tlb
- */
-
-__STATIC_INLINE void __ca9u_inv_tlb_all(void) {
- register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
- __TLBIALL = 0;
- __DSB();
- __ISB();
-}
-
-/******************************** BTB maintenance operations ************************************************/
-/** \brief Invalidate entire branch predictor array
-
- BPIALL. Branch Predictor Invalidate All.
- */
-
-__STATIC_INLINE void __v7_inv_btac(void) {
- register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
- __BPIALL = 0;
- __DSB(); //ensure completion of the invalidation
- __ISB(); //ensure instruction fetch path sees new state
-}
-
-
-/******************************** L1 cache operations ******************************************************/
-
-/** \brief Invalidate the whole I$
-
- ICIALLU. Instruction Cache Invalidate All to PoU
- */
-__STATIC_INLINE void __v7_inv_icache_all(void) {
- register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
- __ICIALLU = 0;
- __DSB(); //ensure completion of the invalidation
- __ISB(); //ensure instruction fetch path sees new I cache state
-}
-
-/** \brief Clean D$ by MVA
-
- DCCMVAC. Data cache clean by MVA to PoC
- */
-__STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
- register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
- __DCCMVAC = (uint32_t)va;
- __DMB(); //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief Invalidate D$ by MVA
-
- DCIMVAC. Data cache invalidate by MVA to PoC
- */
-__STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
- register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
- __DCIMVAC = (uint32_t)va;
- __DMB(); //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief Clean and Invalidate D$ by MVA
-
- DCCIMVAC. Data cache clean and invalidate by MVA to PoC
- */
-__STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
- register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
- __DCCIMVAC = (uint32_t)va;
- __DMB(); //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief Clean and Invalidate the entire data or unified cache
-
- Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
- */
-#pragma push
-#pragma arm
-__STATIC_ASM void __v7_all_cache(uint32_t op) {
- ARM
-
- PUSH {R4-R11}
-
- MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
- ANDS R3, R6, #0x07000000 // Extract coherency level
- MOV R3, R3, LSR #23 // Total cache levels << 1
- BEQ Finished // If 0, no need to clean
-
- MOV R10, #0 // R10 holds current cache level << 1
-Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
- MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
- AND R1, R1, #7 // Isolate those lower 3 bits
- CMP R1, #2
- BLT Skip // No cache or only instruction cache at this level
-
- MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
- ISB // ISB to sync the change to the CacheSizeID reg
- MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
- AND R2, R1, #7 // Extract the line length field
- ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
- LDR R4, =0x3FF
- ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
- CLZ R5, R4 // R5 is the bit position of the way size increment
- LDR R7, =0x7FFF
- ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
-
-Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
-
-Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
- ORR R11, R11, R7, LSL R2 // Factor in the Set number
- CMP R0, #0
- BNE Dccsw
- MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
- B cont
-Dccsw CMP R0, #1
- BNE Dccisw
- MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
- B cont
-Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
-cont SUBS R9, R9, #1 // Decrement the Way number
- BGE Loop3
- SUBS R7, R7, #1 // Decrement the Set number
- BGE Loop2
-Skip ADD R10, R10, #2 // Increment the cache number
- CMP R3, R10
- BGT Loop1
-
-Finished
- DSB
- POP {R4-R11}
- BX lr
-
-}
-#pragma pop
-
-
-/** \brief Invalidate the whole D$
-
- DCISW. Invalidate by Set/Way
- */
-
-__STATIC_INLINE void __v7_inv_dcache_all(void) {
- __v7_all_cache(0);
-}
-
-/** \brief Clean the whole D$
-
- DCCSW. Clean by Set/Way
- */
-
-__STATIC_INLINE void __v7_clean_dcache_all(void) {
- __v7_all_cache(1);
-}
-
-/** \brief Clean and invalidate the whole D$
-
- DCCISW. Clean and Invalidate by Set/Way
- */
-
-__STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
- __v7_all_cache(2);
-}
-
-#include "core_ca_mmu.h"
-
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-
-#define __inline inline
-
-inline static uint32_t __disable_irq_iar() {
- int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
- __disable_irq();
- return irq_dis;
-}
-
-#define MODE_USR 0x10
-#define MODE_FIQ 0x11
-#define MODE_IRQ 0x12
-#define MODE_SVC 0x13
-#define MODE_MON 0x16
-#define MODE_ABT 0x17
-#define MODE_HYP 0x1A
-#define MODE_UND 0x1B
-#define MODE_SYS 0x1F
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the USR/SYS Stack Pointer (PSP).
-
- \param [in] topOfProcStack USR/SYS Stack Pointer value to set
- */
-// from rt_CMSIS.c
-__arm static inline void __set_PSP(uint32_t topOfProcStack) {
-__asm(
- " ARM\n"
-// " PRESERVE8\n"
-
- " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
- " MRS R1, CPSR \n"
- " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
- " MOV SP, R0 \n"
- " MSR CPSR_c, R1 ;no effect in USR mode \n"
- " ISB \n"
- " BX LR \n");
-}
-
-/** \brief Set User Mode
-
- This function changes the processor state to User Mode
- */
-// from rt_CMSIS.c
-__arm static inline void __set_CPS_USR(void) {
-__asm(
- " ARM \n"
-
- " CPS #0x10 \n" // MODE_USR
- " BX LR\n");
-}
-
-/** \brief Set TTBR0
-
- This function assigns the given value to the Translation Table Base Register 0.
-
- \param [in] ttbr0 Translation Table Base Register 0 value to set
- */
-// from mmu_Renesas_RZ_A1.c
-__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
- __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
- __ISB();
-}
-
-/** \brief Set DACR
-
- This function assigns the given value to the Domain Access Control Register.
-
- \param [in] dacr Domain Access Control Register value to set
- */
-// from mmu_Renesas_RZ_A1.c
-__STATIC_INLINE void __set_DACR(uint32_t dacr) {
- __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
- __ISB();
-}
-
-
-/******************************** Cache and BTAC enable ****************************************************/
-/** \brief Set SCTLR
-
- This function assigns the given value to the System Control Register.
-
- \param [in] sctlr System Control Register value to set
- */
-// from __enable_mmu()
-__STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
- __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
-}
-
-/** \brief Get SCTLR
-
- This function returns the value of the System Control Register.
-
- \return System Control Register value
- */
-// from __enable_mmu()
-__STATIC_INLINE uint32_t __get_SCTLR() {
- uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
- return __regSCTLR;
-}
-
-/** \brief Enable Caches
-
- Enable Caches
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __enable_caches(void) {
- __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
-}
-
-/** \brief Enable BTAC
-
- Enable BTAC
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __enable_btac(void) {
- __set_SCTLR( __get_SCTLR() | (1 << 11));
- __ISB();
-}
-
-/** \brief Enable MMU
-
- Enable MMU
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __enable_mmu(void) {
- // Set M bit 0 to enable the MMU
- // Set AFE bit to enable simplified access permissions model
- // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
- __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
- __ISB();
-}
-
-/******************************** TLB maintenance operations ************************************************/
-/** \brief Invalidate the whole tlb
-
- TLBIALL. Invalidate the whole tlb
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __ca9u_inv_tlb_all(void) {
- uint32_t val = 0;
- __MCR(15, 0, val, 8, 7, 0); // reg to cp15
- __MCR(15, 0, val, 8, 6, 0); // reg to cp15
- __MCR(15, 0, val, 8, 5, 0); // reg to cp15
- __DSB();
- __ISB();
-}
-
-/******************************** BTB maintenance operations ************************************************/
-/** \brief Invalidate entire branch predictor array
-
- BPIALL. Branch Predictor Invalidate All.
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __v7_inv_btac(void) {
- uint32_t val = 0;
- __MCR(15, 0, val, 7, 5, 6); // reg to cp15
- __DSB(); //ensure completion of the invalidation
- __ISB(); //ensure instruction fetch path sees new state
-}
-
-
-/******************************** L1 cache operations ******************************************************/
-
-/** \brief Invalidate the whole I$
-
- ICIALLU. Instruction Cache Invalidate All to PoU
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __v7_inv_icache_all(void) {
- uint32_t val = 0;
- __MCR(15, 0, val, 7, 5, 0); // reg to cp15
- __DSB(); //ensure completion of the invalidation
- __ISB(); //ensure instruction fetch path sees new I cache state
-}
-
-// from __v7_inv_dcache_all()
-__arm static inline void __v7_all_cache(uint32_t op) {
-__asm(
- " ARM \n"
-
- " PUSH {R4-R11} \n"
-
- " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
- " ANDS R3, R6, #0x07000000\n" // Extract coherency level
- " MOV R3, R3, LSR #23\n" // Total cache levels << 1
- " BEQ Finished\n" // If 0, no need to clean
-
- " MOV R10, #0\n" // R10 holds current cache level << 1
- "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
- " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
- " AND R1, R1, #7 \n" // Isolate those lower 3 bits
- " CMP R1, #2 \n"
- " BLT Skip \n" // No cache or only instruction cache at this level
-
- " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
- " ISB \n" // ISB to sync the change to the CacheSizeID reg
- " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
- " AND R2, R1, #7 \n" // Extract the line length field
- " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
- " movw R4, #0x3FF \n"
- " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
- " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
- " movw R7, #0x7FFF \n"
- " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
-
- "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
-
- "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
- " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
- " CMP R0, #0 \n"
- " BNE Dccsw \n"
- " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
- " B cont \n"
- "Dccsw: CMP R0, #1 \n"
- " BNE Dccisw \n"
- " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
- " B cont \n"
- "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
- "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
- " BGE Loop3 \n"
- " SUBS R7, R7, #1 \n" // Decrement the Set number
- " BGE Loop2 \n"
- "Skip: ADD R10, R10, #2 \n" // increment the cache number
- " CMP R3, R10 \n"
- " BGT Loop1 \n"
-
- "Finished: \n"
- " DSB \n"
- " POP {R4-R11} \n"
- " BX lr \n" );
-}
-
-/** \brief Invalidate the whole D$
-
- DCISW. Invalidate by Set/Way
- */
-// from system_Renesas_RZ_A1.c
-__STATIC_INLINE void __v7_inv_dcache_all(void) {
- __v7_all_cache(0);
-}
-/** \brief Clean the whole D$
-
- DCCSW. Clean by Set/Way
- */
-
-__STATIC_INLINE void __v7_clean_dcache_all(void) {
- __v7_all_cache(1);
-}
-
-/** \brief Clean and invalidate the whole D$
-
- DCCISW. Clean and Invalidate by Set/Way
- */
-
-__STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
- __v7_all_cache(2);
-}
-/** \brief Clean and Invalidate D$ by MVA
-
- DCCIMVAC. Data cache clean and invalidate by MVA to PoC
- */
-__STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
- __MCR(15, 0, (uint32_t)va, 7, 14, 1);
- __DMB();
-}
-
-#include "core_ca_mmu.h"
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-#define MODE_USR 0x10
-#define MODE_FIQ 0x11
-#define MODE_IRQ 0x12
-#define MODE_SVC 0x13
-#define MODE_MON 0x16
-#define MODE_ABT 0x17
-#define MODE_HYP 0x1A
-#define MODE_UND 0x1B
-#define MODE_SYS 0x1F
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
- __ASM volatile ("cpsie i");
-}
-
-/** \brief Disable IRQ Interrupts
-
- This function disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
-{
- uint32_t result;
-
- __ASM volatile ("mrs %0, cpsr" : "=r" (result));
- __ASM volatile ("cpsid i");
- return(result & 0x80);
-}
-
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-#if 1
- register uint32_t __regAPSR;
- __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
-#else
- register uint32_t __regAPSR __ASM("apsr");
-#endif
- return(__regAPSR);
-}
-
-
-/** \brief Get CPSR Register
-
- This function returns the content of the CPSR Register.
-
- \return CPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
-{
-#if 1
- register uint32_t __regCPSR;
- __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
-#else
- register uint32_t __regCPSR __ASM("cpsr");
-#endif
- return(__regCPSR);
-}
-
-#if 0
-/** \brief Set Stack Pointer
-
- This function assigns the given value to the current stack pointer.
-
- \param [in] topOfStack Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
-{
- register uint32_t __regSP __ASM("sp");
- __regSP = topOfStack;
-}
-#endif
-
-/** \brief Get link register
-
- This function returns the value of the link register
-
- \return Value of link register
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
-{
- register uint32_t __reglr __ASM("lr");
- return(__reglr);
-}
-
-#if 0
-/** \brief Set link register
-
- This function sets the value of the link register
-
- \param [in] lr LR value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
-{
- register uint32_t __reglr __ASM("lr");
- __reglr = lr;
-}
-#endif
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the USR/SYS Stack Pointer (PSP).
-
- \param [in] topOfProcStack USR/SYS Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __asm__ volatile (
- ".ARM;"
- ".eabi_attribute Tag_ABI_align8_preserved,1;"
-
- "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
- "MRS R1, CPSR;"
- "CPS %0;" /* ;no effect in USR mode */
- "MOV SP, R0;"
- "MSR CPSR_c, R1;" /* ;no effect in USR mode */
- "ISB;"
- //"BX LR;"
- :
- : "i"(MODE_SYS)
- : "r0", "r1");
- return;
-}
-
-/** \brief Set User Mode
-
- This function changes the processor state to User Mode
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
-{
- __asm__ volatile (
- ".ARM;"
-
- "CPS %0;"
- //"BX LR;"
- :
- : "i"(MODE_USR)
- : );
- return;
-}
-
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq() __asm__ volatile ("cpsie f")
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq() __asm__ volatile ("cpsid f")
-
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-#if 1
- uint32_t result;
-
- __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
- return (result);
-#else
- register uint32_t __regfpscr __ASM("fpscr");
- return(__regfpscr);
-#endif
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-#if 1
- __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
-#else
- register uint32_t __regfpscr __ASM("fpscr");
- __regfpscr = (fpscr);
-#endif
-#endif
-}
-
-/** \brief Get FPEXC
-
- This function returns the current value of the Floating Point Exception Control register.
-
- \return Floating Point Exception Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
-{
-#if (__FPU_PRESENT == 1)
-#if 1
- uint32_t result;
-
- __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
- return (result);
-#else
- register uint32_t __regfpexc __ASM("fpexc");
- return(__regfpexc);
-#endif
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPEXC
-
- This function assigns the given value to the Floating Point Exception Control register.
-
- \param [in] fpscr Floating Point Exception Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
-{
-#if (__FPU_PRESENT == 1)
-#if 1
- __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
-#else
- register uint32_t __regfpexc __ASM("fpexc");
- __regfpexc = (fpexc);
-#endif
-#endif
-}
-
-/** \brief Get CPACR
-
- This function returns the current value of the Coprocessor Access Control register.
-
- \return Coprocessor Access Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
-{
-#if 1
- register uint32_t __regCPACR;
- __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
-#else
- register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
-#endif
- return __regCPACR;
-}
-
-/** \brief Set CPACR
-
- This function assigns the given value to the Coprocessor Access Control register.
-
- \param [in] cpacr Coprocessor Acccess Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
-{
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
-#else
- register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
- __regCPACR = cpacr;
-#endif
- __ISB();
-}
-
-/** \brief Get CBAR
-
- This function returns the value of the Configuration Base Address register.
-
- \return Configuration Base Address register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
-#if 1
- register uint32_t __regCBAR;
- __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
-#else
- register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
-#endif
- return(__regCBAR);
-}
-
-/** \brief Get TTBR0
-
- This function returns the value of the Translation Table Base Register 0.
-
- \return Translation Table Base Register 0 value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
-#if 1
- register uint32_t __regTTBR0;
- __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
-#else
- register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
-#endif
- return(__regTTBR0);
-}
-
-/** \brief Set TTBR0
-
- This function assigns the given value to the Translation Table Base Register 0.
-
- \param [in] ttbr0 Translation Table Base Register 0 value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
-#else
- register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
- __regTTBR0 = ttbr0;
-#endif
- __ISB();
-}
-
-/** \brief Get DACR
-
- This function returns the value of the Domain Access Control Register.
-
- \return Domain Access Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
-#if 1
- register uint32_t __regDACR;
- __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
-#else
- register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
-#endif
- return(__regDACR);
-}
-
-/** \brief Set DACR
-
- This function assigns the given value to the Domain Access Control Register.
-
- \param [in] dacr Domain Access Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
-#else
- register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
- __regDACR = dacr;
-#endif
- __ISB();
-}
-
-/******************************** Cache and BTAC enable ****************************************************/
-
-/** \brief Set SCTLR
-
- This function assigns the given value to the System Control Register.
-
- \param [in] sctlr System Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
-{
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
-#else
- register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
- __regSCTLR = sctlr;
-#endif
-}
-
-/** \brief Get SCTLR
-
- This function returns the value of the System Control Register.
-
- \return System Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
-#if 1
- register uint32_t __regSCTLR;
- __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
-#else
- register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
-#endif
- return(__regSCTLR);
-}
-
-/** \brief Enable Caches
-
- Enable Caches
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
- // Set I bit 12 to enable I Cache
- // Set C bit 2 to enable D Cache
- __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
-}
-
-/** \brief Disable Caches
-
- Disable Caches
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
- // Clear I bit 12 to disable I Cache
- // Clear C bit 2 to disable D Cache
- __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
- __ISB();
-}
-
-/** \brief Enable BTAC
-
- Enable BTAC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
- // Set Z bit 11 to enable branch prediction
- __set_SCTLR( __get_SCTLR() | (1 << 11));
- __ISB();
-}
-
-/** \brief Disable BTAC
-
- Disable BTAC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
- // Clear Z bit 11 to disable branch prediction
- __set_SCTLR( __get_SCTLR() & ~(1 << 11));
-}
-
-
-/** \brief Enable MMU
-
- Enable MMU
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
- // Set M bit 0 to enable the MMU
- // Set AFE bit to enable simplified access permissions model
- // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
- __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
- __ISB();
-}
-
-/** \brief Disable MMU
-
- Disable MMU
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
- // Clear M bit 0 to disable the MMU
- __set_SCTLR( __get_SCTLR() & ~1);
- __ISB();
-}
-
-/******************************** TLB maintenance operations ************************************************/
-/** \brief Invalidate the whole tlb
-
- TLBIALL. Invalidate the whole tlb
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
-#else
- register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
- __TLBIALL = 0;
-#endif
- __DSB();
- __ISB();
-}
-
-/******************************** BTB maintenance operations ************************************************/
-/** \brief Invalidate entire branch predictor array
-
- BPIALL. Branch Predictor Invalidate All.
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
-#else
- register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
- __BPIALL = 0;
-#endif
- __DSB(); //ensure completion of the invalidation
- __ISB(); //ensure instruction fetch path sees new state
-}
-
-
-/******************************** L1 cache operations ******************************************************/
-
-/** \brief Invalidate the whole I$
-
- ICIALLU. Instruction Cache Invalidate All to PoU
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
-#else
- register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
- __ICIALLU = 0;
-#endif
- __DSB(); //ensure completion of the invalidation
- __ISB(); //ensure instruction fetch path sees new I cache state
-}
-
-/** \brief Clean D$ by MVA
-
- DCCMVAC. Data cache clean by MVA to PoC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
-#else
- register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
- __DCCMVAC = (uint32_t)va;
-#endif
- __DMB(); //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief Invalidate D$ by MVA
-
- DCIMVAC. Data cache invalidate by MVA to PoC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
-#else
- register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
- __DCIMVAC = (uint32_t)va;
-#endif
- __DMB(); //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief Clean and Invalidate D$ by MVA
-
- DCCIMVAC. Data cache clean and invalidate by MVA to PoC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
-#else
- register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
- __DCCIMVAC = (uint32_t)va;
-#endif
- __DMB(); //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief Clean and Invalidate the entire data or unified cache
-
- Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
- */
-extern void __v7_all_cache(uint32_t op);
-
-
-/** \brief Invalidate the whole D$
-
- DCISW. Invalidate by Set/Way
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
- __v7_all_cache(0);
-}
-
-/** \brief Clean the whole D$
-
- DCCSW. Clean by Set/Way
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
- __v7_all_cache(1);
-}
-
-/** \brief Clean and invalidate the whole D$
-
- DCCISW. Clean and Invalidate by Set/Way
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
- __v7_all_cache(2);
-}
-
-#include "core_ca_mmu.h"
-
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-
-#error TASKING Compiler support not implemented for Cortex-A
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CAFUNC_H__ */
diff --git a/cmsis/core_caInstr.h b/cmsis/core_caInstr.h
deleted file mode 100644
index b1d3435765..0000000000
--- a/cmsis/core_caInstr.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/**************************************************************************//**
- * @file core_caInstr.h
- * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
- * @version
- * @date 04. December 2012
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2012 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-#ifndef __CORE_CAINSTR_H__
-#define __CORE_CAINSTR_H__
-
-#define __CORTEX_M 0x3
-#include "core_cmInstr.h"
-#undef __CORTEX_M
-
-#endif
-
diff --git a/cmsis/core_ca_mmu.h b/cmsis/core_ca_mmu.h
deleted file mode 100644
index 189b073dbc..0000000000
--- a/cmsis/core_ca_mmu.h
+++ /dev/null
@@ -1,847 +0,0 @@
-;/**************************************************************************//**
-; * @file core_ca_mmu.h
-; * @brief MMU Startup File for A9_MP Device Series
-; * @version V1.01
-; * @date 10 Sept 2014
-; *
-; * @note
-; *
-; ******************************************************************************/
-;/* Copyright (c) 2012-2014 ARM LIMITED
-;
-; All rights reserved.
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; - Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; - Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; - Neither the name of ARM nor the names of its contributors may be used
-; to endorse or promote products derived from this software without
-; specific prior written permission.
-; *
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-; POSSIBILITY OF SUCH DAMAGE.
-; ---------------------------------------------------------------------------*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef _MMU_FUNC_H
-#define _MMU_FUNC_H
-
-#define SECTION_DESCRIPTOR (0x2)
-#define SECTION_MASK (0xFFFFFFFC)
-
-#define SECTION_TEXCB_MASK (0xFFFF8FF3)
-#define SECTION_B_SHIFT (2)
-#define SECTION_C_SHIFT (3)
-#define SECTION_TEX0_SHIFT (12)
-#define SECTION_TEX1_SHIFT (13)
-#define SECTION_TEX2_SHIFT (14)
-
-#define SECTION_XN_MASK (0xFFFFFFEF)
-#define SECTION_XN_SHIFT (4)
-
-#define SECTION_DOMAIN_MASK (0xFFFFFE1F)
-#define SECTION_DOMAIN_SHIFT (5)
-
-#define SECTION_P_MASK (0xFFFFFDFF)
-#define SECTION_P_SHIFT (9)
-
-#define SECTION_AP_MASK (0xFFFF73FF)
-#define SECTION_AP_SHIFT (10)
-#define SECTION_AP2_SHIFT (15)
-
-#define SECTION_S_MASK (0xFFFEFFFF)
-#define SECTION_S_SHIFT (16)
-
-#define SECTION_NG_MASK (0xFFFDFFFF)
-#define SECTION_NG_SHIFT (17)
-
-#define SECTION_NS_MASK (0xFFF7FFFF)
-#define SECTION_NS_SHIFT (19)
-
-
-#define PAGE_L1_DESCRIPTOR (0x1)
-#define PAGE_L1_MASK (0xFFFFFFFC)
-
-#define PAGE_L2_4K_DESC (0x2)
-#define PAGE_L2_4K_MASK (0xFFFFFFFD)
-
-#define PAGE_L2_64K_DESC (0x1)
-#define PAGE_L2_64K_MASK (0xFFFFFFFC)
-
-#define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
-#define PAGE_4K_B_SHIFT (2)
-#define PAGE_4K_C_SHIFT (3)
-#define PAGE_4K_TEX0_SHIFT (6)
-#define PAGE_4K_TEX1_SHIFT (7)
-#define PAGE_4K_TEX2_SHIFT (8)
-
-#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
-#define PAGE_64K_B_SHIFT (2)
-#define PAGE_64K_C_SHIFT (3)
-#define PAGE_64K_TEX0_SHIFT (12)
-#define PAGE_64K_TEX1_SHIFT (13)
-#define PAGE_64K_TEX2_SHIFT (14)
-
-#define PAGE_TEXCB_MASK (0xFFFF8FF3)
-#define PAGE_B_SHIFT (2)
-#define PAGE_C_SHIFT (3)
-#define PAGE_TEX_SHIFT (12)
-
-#define PAGE_XN_4K_MASK (0xFFFFFFFE)
-#define PAGE_XN_4K_SHIFT (0)
-#define PAGE_XN_64K_MASK (0xFFFF7FFF)
-#define PAGE_XN_64K_SHIFT (15)
-
-
-#define PAGE_DOMAIN_MASK (0xFFFFFE1F)
-#define PAGE_DOMAIN_SHIFT (5)
-
-#define PAGE_P_MASK (0xFFFFFDFF)
-#define PAGE_P_SHIFT (9)
-
-#define PAGE_AP_MASK (0xFFFFFDCF)
-#define PAGE_AP_SHIFT (4)
-#define PAGE_AP2_SHIFT (9)
-
-#define PAGE_S_MASK (0xFFFFFBFF)
-#define PAGE_S_SHIFT (10)
-
-#define PAGE_NG_MASK (0xFFFFF7FF)
-#define PAGE_NG_SHIFT (11)
-
-#define PAGE_NS_MASK (0xFFFFFFF7)
-#define PAGE_NS_SHIFT (3)
-
-#define OFFSET_1M (0x00100000)
-#define OFFSET_64K (0x00010000)
-#define OFFSET_4K (0x00001000)
-
-#define DESCRIPTOR_FAULT (0x00000000)
-
-/* ########################### MMU Function Access ########################### */
-/** \ingroup MMU_FunctionInterface
- \defgroup MMU_Functions MMU Functions Interface
- @{
- */
-
-/* Attributes enumerations */
-
-/* Region size attributes */
-typedef enum
-{
- SECTION,
- PAGE_4k,
- PAGE_64k,
-} mmu_region_size_Type;
-
-/* Region type attributes */
-typedef enum
-{
- NORMAL,
- DEVICE,
- SHARED_DEVICE,
- NON_SHARED_DEVICE,
- STRONGLY_ORDERED
-} mmu_memory_Type;
-
-/* Region cacheability attributes */
-typedef enum
-{
- NON_CACHEABLE,
- WB_WA,
- WT,
- WB_NO_WA,
-} mmu_cacheability_Type;
-
-/* Region parity check attributes */
-typedef enum
-{
- ECC_DISABLED,
- ECC_ENABLED,
-} mmu_ecc_check_Type;
-
-/* Region execution attributes */
-typedef enum
-{
- EXECUTE,
- NON_EXECUTE,
-} mmu_execute_Type;
-
-/* Region global attributes */
-typedef enum
-{
- GLOBAL,
- NON_GLOBAL,
-} mmu_global_Type;
-
-/* Region shareability attributes */
-typedef enum
-{
- NON_SHARED,
- SHARED,
-} mmu_shared_Type;
-
-/* Region security attributes */
-typedef enum
-{
- SECURE,
- NON_SECURE,
-} mmu_secure_Type;
-
-/* Region access attributes */
-typedef enum
-{
- NO_ACCESS,
- RW,
- READ,
-} mmu_access_Type;
-
-/* Memory Region definition */
-typedef struct RegionStruct {
- mmu_region_size_Type rg_t;
- mmu_memory_Type mem_t;
- uint8_t domain;
- mmu_cacheability_Type inner_norm_t;
- mmu_cacheability_Type outer_norm_t;
- mmu_ecc_check_Type e_t;
- mmu_execute_Type xn_t;
- mmu_global_Type g_t;
- mmu_secure_Type sec_t;
- mmu_access_Type priv_t;
- mmu_access_Type user_t;
- mmu_shared_Type sh_t;
-
-} mmu_region_attributes_Type;
-
-/** \brief Set section execution-never attribute
-
- The function sets section execution-never attribute
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
-
- \return 0
- */
-__STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
-{
- *descriptor_l1 &= SECTION_XN_MASK;
- *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
- return 0;
-}
-
-/** \brief Set section domain
-
- The function sets section domain
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] domain Section domain
-
- \return 0
- */
-__STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
-{
- *descriptor_l1 &= SECTION_DOMAIN_MASK;
- *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
- return 0;
-}
-
-/** \brief Set section parity check
-
- The function sets section parity check
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
-
- \return 0
- */
-__STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
-{
- *descriptor_l1 &= SECTION_P_MASK;
- *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
- return 0;
-}
-
-/** \brief Set section access privileges
-
- The function sets section access privileges
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] user User Level Access: NO_ACCESS, RW, READ
- \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
- \param [in] afe Access flag enable
-
- \return 0
- */
-__STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
-{
- uint32_t ap = 0;
-
- if (afe == 0) { //full access
- if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
- else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
- else if ((priv == RW) && (user == READ)) { ap = 0x2; }
- else if ((priv == RW) && (user == RW)) { ap = 0x3; }
- else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
- else if ((priv == READ) && (user == READ)) { ap = 0x7; }
- }
-
- else { //Simplified access
- if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
- else if ((priv == RW) && (user == RW)) { ap = 0x3; }
- else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
- else if ((priv == READ) && (user == READ)) { ap = 0x7; }
- }
-
- *descriptor_l1 &= SECTION_AP_MASK;
- *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
- *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
-
- return 0;
-}
-
-/** \brief Set section shareability
-
- The function sets section shareability
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] s_bit Section shareability: NON_SHARED, SHARED
-
- \return 0
- */
-__STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
-{
- *descriptor_l1 &= SECTION_S_MASK;
- *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
- return 0;
-}
-
-/** \brief Set section Global attribute
-
- The function sets section Global attribute
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
-
- \return 0
- */
-__STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
-{
- *descriptor_l1 &= SECTION_NG_MASK;
- *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
- return 0;
-}
-
-/** \brief Set section Security attribute
-
- The function sets section Global attribute
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
-
- \return 0
- */
-__STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
-{
- *descriptor_l1 &= SECTION_NS_MASK;
- *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
- return 0;
-}
-
-/* Page 4k or 64k */
-/** \brief Set 4k/64k page execution-never attribute
-
- The function sets 4k/64k page execution-never attribute
-
- \param [out] descriptor_l2 L2 descriptor.
- \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
- \param [in] page Page size: PAGE_4k, PAGE_64k,
-
- \return 0
- */
-__STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
-{
- if (page == PAGE_4k)
- {
- *descriptor_l2 &= PAGE_XN_4K_MASK;
- *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
- }
- else
- {
- *descriptor_l2 &= PAGE_XN_64K_MASK;
- *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
- }
- return 0;
-}
-
-/** \brief Set 4k/64k page domain
-
- The function sets 4k/64k page domain
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] domain Page domain
-
- \return 0
- */
-__STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
-{
- *descriptor_l1 &= PAGE_DOMAIN_MASK;
- *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
- return 0;
-}
-
-/** \brief Set 4k/64k page parity check
-
- The function sets 4k/64k page parity check
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
-
- \return 0
- */
-__STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
-{
- *descriptor_l1 &= SECTION_P_MASK;
- *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
- return 0;
-}
-
-/** \brief Set 4k/64k page access privileges
-
- The function sets 4k/64k page access privileges
-
- \param [out] descriptor_l2 L2 descriptor.
- \param [in] user User Level Access: NO_ACCESS, RW, READ
- \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
- \param [in] afe Access flag enable
-
- \return 0
- */
-__STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
-{
- uint32_t ap = 0;
-
- if (afe == 0) { //full access
- if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
- else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
- else if ((priv == RW) && (user == READ)) { ap = 0x2; }
- else if ((priv == RW) && (user == RW)) { ap = 0x3; }
- else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
- else if ((priv == READ) && (user == READ)) { ap = 0x6; }
- }
-
- else { //Simplified access
- if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
- else if ((priv == RW) && (user == RW)) { ap = 0x3; }
- else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
- else if ((priv == READ) && (user == READ)) { ap = 0x7; }
- }
-
- *descriptor_l2 &= PAGE_AP_MASK;
- *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
- *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
-
- return 0;
-}
-
-/** \brief Set 4k/64k page shareability
-
- The function sets 4k/64k page shareability
-
- \param [out] descriptor_l2 L2 descriptor.
- \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
-
- \return 0
- */
-__STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
-{
- *descriptor_l2 &= PAGE_S_MASK;
- *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
- return 0;
-}
-
-/** \brief Set 4k/64k page Global attribute
-
- The function sets 4k/64k page Global attribute
-
- \param [out] descriptor_l2 L2 descriptor.
- \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
-
- \return 0
- */
-__STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
-{
- *descriptor_l2 &= PAGE_NG_MASK;
- *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
- return 0;
-}
-
-/** \brief Set 4k/64k page Security attribute
-
- The function sets 4k/64k page Global attribute
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
-
- \return 0
- */
-__STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
-{
- *descriptor_l1 &= PAGE_NS_MASK;
- *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
- return 0;
-}
-
-
-/** \brief Set Section memory attributes
-
- The function sets section memory attributes
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
- \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
- \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-
- \return 0
- */
-__STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
-{
- *descriptor_l1 &= SECTION_TEXCB_MASK;
-
- if (STRONGLY_ORDERED == mem)
- {
- return 0;
- }
- else if (SHARED_DEVICE == mem)
- {
- *descriptor_l1 |= (1 << SECTION_B_SHIFT);
- }
- else if (NON_SHARED_DEVICE == mem)
- {
- *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
- }
- else if (NORMAL == mem)
- {
- *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
- switch(inner)
- {
- case NON_CACHEABLE:
- break;
- case WB_WA:
- *descriptor_l1 |= (1 << SECTION_B_SHIFT);
- break;
- case WT:
- *descriptor_l1 |= 1 << SECTION_C_SHIFT;
- break;
- case WB_NO_WA:
- *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
- break;
- }
- switch(outer)
- {
- case NON_CACHEABLE:
- break;
- case WB_WA:
- *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
- break;
- case WT:
- *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
- break;
- case WB_NO_WA:
- *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
- break;
- }
- }
-
- return 0;
-}
-
-/** \brief Set 4k/64k page memory attributes
-
- The function sets 4k/64k page memory attributes
-
- \param [out] descriptor_l2 L2 descriptor.
- \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
- \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
- \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-
- \return 0
- */
-__STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
-{
- *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
-
- if (page == PAGE_64k)
- {
- //same as section
- __memory_section(descriptor_l2, mem, outer, inner);
- }
- else
- {
- if (STRONGLY_ORDERED == mem)
- {
- return 0;
- }
- else if (SHARED_DEVICE == mem)
- {
- *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
- }
- else if (NON_SHARED_DEVICE == mem)
- {
- *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
- }
- else if (NORMAL == mem)
- {
- *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
- switch(inner)
- {
- case NON_CACHEABLE:
- break;
- case WB_WA:
- *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
- break;
- case WT:
- *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
- break;
- case WB_NO_WA:
- *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
- break;
- }
- switch(outer)
- {
- case NON_CACHEABLE:
- break;
- case WB_WA:
- *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
- break;
- case WT:
- *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
- break;
- case WB_NO_WA:
- *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
- break;
- }
- }
- }
-
- return 0;
-}
-
-/** \brief Create a L1 section descriptor
-
- The function creates a section descriptor.
-
- Assumptions:
- - 16MB super sections not supported
- - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
- - Functions always return 0
-
- \param [out] descriptor L1 descriptor
- \param [out] descriptor2 L2 descriptor
- \param [in] reg Section attributes
-
- \return 0
- */
-__STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
-{
- *descriptor = 0;
-
- __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
- __xn_section(descriptor,reg.xn_t);
- __domain_section(descriptor, reg.domain);
- __p_section(descriptor, reg.e_t);
- __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
- __shared_section(descriptor,reg.sh_t);
- __global_section(descriptor,reg.g_t);
- __secure_section(descriptor,reg.sec_t);
- *descriptor &= SECTION_MASK;
- *descriptor |= SECTION_DESCRIPTOR;
-
- return 0;
-
-}
-
-
-/** \brief Create a L1 and L2 4k/64k page descriptor
-
- The function creates a 4k/64k page descriptor.
- Assumptions:
- - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
- - Functions always return 0
-
- \param [out] descriptor L1 descriptor
- \param [out] descriptor2 L2 descriptor
- \param [in] reg 4k/64k page attributes
-
- \return 0
- */
-__STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
-{
- *descriptor = 0;
- *descriptor2 = 0;
-
- switch (reg.rg_t)
- {
- case PAGE_4k:
- __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
- __xn_page(descriptor2, reg.xn_t, PAGE_4k);
- __domain_page(descriptor, reg.domain);
- __p_page(descriptor, reg.e_t);
- __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
- __shared_page(descriptor2,reg.sh_t);
- __global_page(descriptor2,reg.g_t);
- __secure_page(descriptor,reg.sec_t);
- *descriptor &= PAGE_L1_MASK;
- *descriptor |= PAGE_L1_DESCRIPTOR;
- *descriptor2 &= PAGE_L2_4K_MASK;
- *descriptor2 |= PAGE_L2_4K_DESC;
- break;
-
- case PAGE_64k:
- __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
- __xn_page(descriptor2, reg.xn_t, PAGE_64k);
- __domain_page(descriptor, reg.domain);
- __p_page(descriptor, reg.e_t);
- __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
- __shared_page(descriptor2,reg.sh_t);
- __global_page(descriptor2,reg.g_t);
- __secure_page(descriptor,reg.sec_t);
- *descriptor &= PAGE_L1_MASK;
- *descriptor |= PAGE_L1_DESCRIPTOR;
- *descriptor2 &= PAGE_L2_64K_MASK;
- *descriptor2 |= PAGE_L2_64K_DESC;
- break;
-
- case SECTION:
- //error
- break;
-
- }
-
- return 0;
-
-}
-
-/** \brief Create a 1MB Section
-
- \param [in] ttb Translation table base address
- \param [in] base_address Section base address
- \param [in] count Number of sections to create
- \param [in] descriptor_l1 L1 descriptor (region attributes)
-
- */
-__STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
-{
- uint32_t offset;
- uint32_t entry;
- uint32_t i;
-
- offset = base_address >> 20;
- entry = (base_address & 0xFFF00000) | descriptor_l1;
-
- //4 bytes aligned
- ttb = ttb + offset;
-
- for (i = 0; i < count; i++ )
- {
- //4 bytes aligned
- *ttb++ = entry;
- entry += OFFSET_1M;
- }
-}
-
-/** \brief Create a 4k page entry
-
- \param [in] ttb L1 table base address
- \param [in] base_address 4k base address
- \param [in] count Number of 4k pages to create
- \param [in] descriptor_l1 L1 descriptor (region attributes)
- \param [in] ttb_l2 L2 table base address
- \param [in] descriptor_l2 L2 descriptor (region attributes)
-
- */
-__STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
-{
-
- uint32_t offset, offset2;
- uint32_t entry, entry2;
- uint32_t i;
-
-
- offset = base_address >> 20;
- entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
-
- //4 bytes aligned
- ttb += offset;
- //create l1_entry
- *ttb = entry;
-
- offset2 = (base_address & 0xff000) >> 12;
- ttb_l2 += offset2;
- entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
- for (i = 0; i < count; i++ )
- {
- //4 bytes aligned
- *ttb_l2++ = entry2;
- entry2 += OFFSET_4K;
- }
-}
-
-/** \brief Create a 64k page entry
-
- \param [in] ttb L1 table base address
- \param [in] base_address 64k base address
- \param [in] count Number of 64k pages to create
- \param [in] descriptor_l1 L1 descriptor (region attributes)
- \param [in] ttb_l2 L2 table base address
- \param [in] descriptor_l2 L2 descriptor (region attributes)
-
- */
-__STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
-{
- uint32_t offset, offset2;
- uint32_t entry, entry2;
- uint32_t i,j;
-
-
- offset = base_address >> 20;
- entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
-
- //4 bytes aligned
- ttb += offset;
- //create l1_entry
- *ttb = entry;
-
- offset2 = (base_address & 0xff000) >> 12;
- ttb_l2 += offset2;
- entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
- for (i = 0; i < count; i++ )
- {
- //create 16 entries
- for (j = 0; j < 16; j++)
- //4 bytes aligned
- *ttb_l2++ = entry2;
- entry2 += OFFSET_64K;
- }
-}
-
-/*@} end of MMU_Functions */
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/rtos/rtx/TARGET_CORTEX_A/HAL_CA.c b/rtos/rtx/TARGET_CORTEX_A/HAL_CA.c
deleted file mode 100644
index 68852d439a..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/HAL_CA.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: HAL_CA.C
- * Purpose: Hardware Abstraction Layer for Cortex-A
- * Rev.: V4.77 plus changes for RTX-Ax
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH, 2012-2015 ARM Limited
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-#include "rt_TypeDef.h"
-#include "RTX_Config.h"
-#include "rt_HAL_CA.h"
-
-/*--------------------------- os_init_context -------------------------------*/
-
-void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
- /* Prepare TCB and saved context for a first time start of a task. */
- U32 *stk,i,size;
-
- /* Prepare a complete interrupt frame for first task start */
- size = p_TCB->priv_stack >> 2;
- if (size == 0U) {
- size = (U16)os_stackinfo >> 2;
- }
- /* Write to the top of stack. */
- stk = &p_TCB->stack[size];
-
- /* Auto correct to 8-byte ARM stack alignment. */
- if ((U32)stk & 0x04U) {
- stk--;
- }
-
- stk -= 16;
-
- /* Initial PC and default CPSR */
- stk[14] = (U32)task_body;
- /* Task run mode is inherited from the startup file. */
- /* (non-privileged USER or privileged SYSTEM mode) */
- stk[15] = (os_flags & 1) ? INIT_CPSR_SYS : INIT_CPSR_USER;
- /* Set T-bit if task function in Thumb mode. */
- if ((U32)task_body & 1) {
- stk[15] |= CPSR_T_BIT;
- }
- /* Assign a void pointer to R0. */
- stk[8] = (U32)p_TCB->msg;
- /* Clear R1-R12,LR registers. */
- for (i = 0U; i < 8U; i++) {
- stk[i] = 0U;
- }
- for (i = 9U; i < 14U; i++) {
- stk[i] = 0;
- }
-
- /* Initial Task stack pointer. */
- p_TCB->tsk_stack = (U32)stk;
-
- /* Task entry point. */
- p_TCB->ptask = task_body;
-
- /* Initialize stack with magic pattern. */
- if (os_stackinfo & 0x10000000U) {
- if (size > (16U+1U)) {
- for (i = ((size - 16U)/2U) - 1U; i; i--) {
- stk -= 2U;
- stk[1] = MAGIC_PATTERN;
- stk[0] = MAGIC_PATTERN;
- }
- if (--stk > p_TCB->stack) {
- *stk = MAGIC_PATTERN;
- }
- }
- }
-
- /* Set a magic word for checking of stack overflow. */
- p_TCB->stack[0] = MAGIC_WORD;
-}
-
-
-/*--------------------------- rt_ret_val ----------------------------------*/
-
-static __inline U32 *rt_ret_regs (P_TCB p_TCB) {
- /* Get pointer to task return value registers (R0..R3) in Stack */
- if (p_TCB->stack_frame & 0x4) {
- /* NEON/D32 Stack Frame: D0-31,FPSCR,Reserved,R4-R11,R0-R3,R12,LR,PC,xPSR */
- return (U32 *)(p_TCB->tsk_stack + (8U*4U) + (2U*4U) + (32U*8U));
- } else if (p_TCB->stack_frame & 0x2) {
- /* VFP/D16 Stack Frame: D0-D15/S0-31,FPSCR,Reserved,R4-R11,R0-R3,R12,LR,PC,xPSR */
- return (U32 *)(p_TCB->tsk_stack + (8U*4U) + (2U*4U) + (32U*4U));
- } else {
- /* Basic Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */
- return (U32 *)(p_TCB->tsk_stack + (8U*4U));
- }
-}
-
-void rt_ret_val (P_TCB p_TCB, U32 v0) {
- U32 *ret;
-
- ret = rt_ret_regs(p_TCB);
- ret[0] = v0;
-}
-
-void rt_ret_val2(P_TCB p_TCB, U32 v0, U32 v1) {
- U32 *ret;
-
- ret = rt_ret_regs(p_TCB);
- ret[0] = v0;
- ret[1] = v1;
-}
-
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h b/rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h
deleted file mode 100644
index ab4017dd11..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h
+++ /dev/null
@@ -1,608 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RTX_CM_LIB.H
- * Purpose: RTX Kernel System Configuration
- * Rev.: V4.79
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-#if defined (__CC_ARM)
-#include
-#pragma O3
-#define __USED __attribute__((used))
-#elif defined (__GNUC__)
-#pragma GCC optimize ("O3")
-#define __USED __attribute__((used))
-#elif defined (__ICCARM__)
-#define __USED __root
-#endif
-
-
-/*----------------------------------------------------------------------------
- * Definitions
- *---------------------------------------------------------------------------*/
-
-#define _declare_box(pool,size,cnt) uint32_t pool[(((size)+3)/4)*(cnt) + 3]
-#define _declare_box8(pool,size,cnt) uint64_t pool[(((size)+7)/8)*(cnt) + 2]
-
-#define OS_TCB_SIZE 64
-#define OS_TMR_SIZE 8
-
-#if defined (__CC_ARM) && !defined (__MICROLIB)
-
-typedef void *OS_ID;
-typedef uint32_t OS_TID;
-typedef uint32_t OS_MUT[4];
-typedef uint32_t OS_RESULT;
-
-#define runtask_id() rt_tsk_self()
-#define mutex_init(m) rt_mut_init(m)
-#define mutex_wait(m) os_mut_wait(m,0xFFFFU)
-#define mutex_rel(m) os_mut_release(m)
-
-extern uint8_t os_running;
-extern OS_TID rt_tsk_self (void);
-extern void rt_mut_init (OS_ID mutex);
-extern OS_RESULT rt_mut_release (OS_ID mutex);
-extern OS_RESULT rt_mut_wait (OS_ID mutex, uint16_t timeout);
-
-#define os_mut_wait(mutex,timeout) _os_mut_wait((uint32_t)rt_mut_wait,mutex,timeout)
-#define os_mut_release(mutex) _os_mut_release((uint32_t)rt_mut_release,mutex)
-
-OS_RESULT _os_mut_release (uint32_t p, OS_ID mutex) __svc_indirect(0);
-OS_RESULT _os_mut_wait (uint32_t p, OS_ID mutex, uint16_t timeout) __svc_indirect(0);
-
-#elif defined (__ICCARM__)
-
-typedef void *OS_ID;
-typedef uint32_t OS_TID;
-typedef uint32_t OS_MUT[4];
-typedef uint32_t OS_RESULT;
-
-#define runtask_id() rt_tsk_self()
-#define mutex_init(m) rt_mut_init(m)
-#define mutex_del(m) os_mut_delete(m)
-#define mutex_wait(m) os_mut_wait(m,0xFFFF)
-#define mutex_rel(m) os_mut_release(m)
-
-extern OS_TID rt_tsk_self (void);
-extern void rt_mut_init (OS_ID mutex);
-extern OS_RESULT rt_mut_delete (OS_ID mutex);
-extern OS_RESULT rt_mut_release (OS_ID mutex);
-extern OS_RESULT rt_mut_wait (OS_ID mutex, uint16_t timeout);
-
-#pragma swi_number=0
-__swi OS_RESULT _os_mut_delete (OS_ID mutex);
-
-static inline OS_RESULT os_mut_delete(OS_ID mutex)
-{
- __asm("mov r12,%0\n" :: "r"(&rt_mut_delete) : "r12" );
- return _os_mut_delete(mutex);
-}
-
-#pragma swi_number=0
-__swi OS_RESULT _os_mut_release (OS_ID mutex);
-
-static inline OS_RESULT os_mut_release(OS_ID mutex)
-{
- __asm("mov r12,%0\n" :: "r"(&rt_mut_release) : "r12" );
- return _os_mut_release(mutex);
-}
-
-#pragma swi_number=0
-__swi OS_RESULT _os_mut_wait (OS_ID mutex, uint16_t timeout);
-
-static inline OS_RESULT os_mut_wait(OS_ID mutex, uint16_t timeout)
-{
- __asm("mov r12,%0\n" :: "r"(&rt_mut_wait) : "r12" );
- return _os_mut_wait(mutex, timeout);
-}
-
-#include /* for include DLib_Thread.h */
-
-void __iar_system_Mtxinit(__iar_Rmtx *);
-void __iar_system_Mtxdst(__iar_Rmtx *);
-void __iar_system_Mtxlock(__iar_Rmtx *);
-void __iar_system_Mtxunlock(__iar_Rmtx *);
-
-
-
-
-#endif
-
-
-/*----------------------------------------------------------------------------
- * Global Variables
- *---------------------------------------------------------------------------*/
-
-#if (OS_TASKCNT == 0)
-#error "Invalid number of concurrent running threads!"
-#endif
-
-#if (OS_PRIVCNT >= OS_TASKCNT)
-#error "Too many threads with user-provided stack size!"
-#endif
-
-#if (OS_TIMERS != 0)
-#define OS_TASK_CNT (OS_TASKCNT + 1)
-#ifndef __MBED_CMSIS_RTOS_CA9
-#define OS_PRIV_CNT (OS_PRIVCNT + 2)
-#define OS_STACK_SZ (4*(OS_PRIVSTKSIZE+OS_MAINSTKSIZE+OS_TIMERSTKSZ))
-#endif
-#else
-#define OS_TASK_CNT OS_TASKCNT
-#ifndef __MBED_CMSIS_RTOS_CA9
-#define OS_PRIV_CNT (OS_PRIVCNT + 1)
-#define OS_STACK_SZ (4*(OS_PRIVSTKSIZE+OS_MAINSTKSIZE))
-#endif
-#endif
-
-#ifndef OS_STKINIT
-#define OS_STKINIT 0
-#endif
-
-uint16_t const os_maxtaskrun = OS_TASK_CNT;
-#ifdef __MBED_CMSIS_RTOS_CA9
-uint32_t const os_stackinfo = (OS_STKINIT<<28) | (OS_STKCHECK<<24) | (OS_IDLESTKSIZE*4);
-#else
-uint32_t const os_stackinfo = (OS_STKINIT<<28) | (OS_STKCHECK<<24) | (OS_PRIV_CNT<<16) | (OS_STKSIZE*4);
-#endif
-uint32_t const os_rrobin = (OS_ROBIN << 16) | OS_ROBINTOUT;
-uint32_t const os_tickfreq = OS_CLOCK;
-uint16_t const os_tickus_i = OS_CLOCK/1000000;
-uint16_t const os_tickus_f = (((uint64_t)(OS_CLOCK-1000000*(OS_CLOCK/1000000)))<<16)/1000000;
-uint32_t const os_trv = OS_TRV;
-#if defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)
-uint8_t const os_flags = 0;
-#else /* defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED) */
-uint8_t const os_flags = OS_RUNPRIV;
-#endif /* defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED) */
-
-/* Export following defines to uVision debugger. */
-__USED uint32_t const CMSIS_RTOS_API_Version = osCMSIS;
-__USED uint32_t const CMSIS_RTOS_RTX_Version = osCMSIS_RTX;
-__USED uint32_t const os_clockrate = OS_TICK;
-__USED uint32_t const os_timernum = 0U;
-
-/* Memory pool for TCB allocation */
-_declare_box (mp_tcb, OS_TCB_SIZE, OS_TASK_CNT);
-uint16_t const mp_tcb_size = sizeof(mp_tcb);
-
-#ifdef __MBED_CMSIS_RTOS_CA9
-/* Memory pool for os_idle_demon stack allocation. */
-_declare_box8 (mp_stk, OS_IDLESTKSIZE*4, 1);
-uint32_t const mp_stk_size = sizeof(mp_stk);
-#else
-/* Memory pool for System stack allocation (+os_idle_demon). */
-_declare_box8 (mp_stk, OS_STKSIZE*4, OS_TASK_CNT-OS_PRIV_CNT+1);
-uint32_t const mp_stk_size = sizeof(mp_stk);
-
-/* Memory pool for user specified stack allocation (+main, +timer) */
-uint64_t os_stack_mem[2+OS_PRIV_CNT+(OS_STACK_SZ/8)];
-uint32_t const os_stack_sz = sizeof(os_stack_mem);
-#endif
-
-#ifndef OS_FIFOSZ
- #define OS_FIFOSZ 16
-#endif
-
-/* Fifo Queue buffer for ISR requests.*/
-uint32_t os_fifo[OS_FIFOSZ*2+1];
-uint8_t const os_fifo_size = OS_FIFOSZ;
-
-/* An array of Active task pointers. */
-void *os_active_TCB[OS_TASK_CNT];
-
-/* User Timers Resources */
-#if (OS_TIMERS != 0)
-extern void osTimerThread (void const *argument);
-#ifdef __MBED_CMSIS_RTOS_CA9
-osThreadDef(osTimerThread, (osPriority)(OS_TIMERPRIO-3), 4*OS_TIMERSTKSZ);
-#else
-osThreadDef(osTimerThread, (osPriority)(OS_TIMERPRIO-3), 1, 4*OS_TIMERSTKSZ);
-#endif
-osThreadId osThreadId_osTimerThread;
-osMessageQDef(osTimerMessageQ, OS_TIMERCBQS, void *);
-osMessageQId osMessageQId_osTimerMessageQ;
-#else
-osThreadDef_t os_thread_def_osTimerThread = { NULL };
-osThreadId osThreadId_osTimerThread;
-osMessageQDef(osTimerMessageQ, 0U, void *);
-osMessageQId osMessageQId_osTimerMessageQ;
-#endif
-
-/* Legacy RTX User Timers not used */
-uint32_t os_tmr = 0U;
-uint32_t const *m_tmr = NULL;
-uint16_t const mp_tmr_size = 0U;
-
-/* singleton mutex */
-osMutexId singleton_mutex_id;
-osMutexDef(singleton_mutex);
-
-#if defined (__CC_ARM) && !defined (__MICROLIB)
- /* A memory space for arm standard library. */
- static uint32_t std_libspace[OS_TASK_CNT][96/4];
- static OS_MUT std_libmutex[OS_MUTEXCNT];
- static uint32_t nr_mutex;
- extern void *__libspace_start;
-#elif defined (__ICCARM__)
-typedef struct os_mut_array {
- OS_MUT mutex;
- uint32_t used;
-} os_mut_array_t;
-
-static os_mut_array_t std_libmutex[OS_MUTEXCNT];/* must be Zero clear */
-static uint32_t nr_mutex = 0;
-#endif
-
-
-/*----------------------------------------------------------------------------
- * RTX Optimizations (empty functions)
- *---------------------------------------------------------------------------*/
-
-#if OS_ROBIN == 0
- void rt_init_robin (void) {;}
- void rt_chk_robin (void) {;}
-#endif
-
-#if OS_STKCHECK == 0
- void rt_stk_check (void) {;}
-#endif
-
-
-/*----------------------------------------------------------------------------
- * Standard Library multithreading interface
- *---------------------------------------------------------------------------*/
-
-#if defined (__CC_ARM) && !defined (__MICROLIB)
-
-/*--------------------------- __user_perthread_libspace ---------------------*/
-
-void *__user_perthread_libspace (void) {
- /* Provide a separate libspace for each task. */
- uint32_t idx;
-
- idx = (os_running != 0U) ? runtask_id () : 0U;
- if (idx == 0U) {
- /* RTX not running yet. */
- return (&__libspace_start);
- }
- return ((void *)&std_libspace[idx-1]);
-}
-
-/*--------------------------- _mutex_initialize -----------------------------*/
-
-int _mutex_initialize (OS_ID *mutex) {
- /* Allocate and initialize a system mutex. */
-
- if (nr_mutex >= OS_MUTEXCNT) {
- /* If you are here, you need to increase the number OS_MUTEXCNT. */
- for (;;);
- }
- *mutex = &std_libmutex[nr_mutex++];
- mutex_init (*mutex);
- return (1);
-}
-
-
-/*--------------------------- _mutex_acquire --------------------------------*/
-
-__attribute__((used)) void _mutex_acquire (OS_ID *mutex) {
- /* Acquire a system mutex, lock stdlib resources. */
- if (os_running) {
- /* RTX running, acquire a mutex. */
- mutex_wait (*mutex);
- }
-}
-
-
-/*--------------------------- _mutex_release --------------------------------*/
-
-__attribute__((used)) void _mutex_release (OS_ID *mutex) {
- /* Release a system mutex, unlock stdlib resources. */
- if (os_running) {
- /* RTX running, release a mutex. */
- mutex_rel (*mutex);
- }
-}
-
-#elif defined (__ICCARM__)
-
-/*--------------------------- __iar_system_Mtxinit --------------------------*/
-
-void __iar_system_Mtxinit(__iar_Rmtx *mutex)
-{
- /* Allocate and initialize a system mutex. */
- int32_t idx;
-
- for (idx = 0; idx < OS_MUTEXCNT; idx++)
- {
- if (std_libmutex[idx].used == 0)
- {
- std_libmutex[idx].used = 1;
- *mutex = &std_libmutex[idx].mutex;
- nr_mutex++;
- break;
- }
- }
- if (nr_mutex >= OS_MUTEXCNT)
- {
- /* If you are here, you need to increase the number OS_MUTEXCNT. */
- for (;;);
- }
-
- mutex_init (*mutex);
-}
-
-/*--------------------------- __iar_system_Mtxdst ---------------------------*/
-
-void __iar_system_Mtxdst(__iar_Rmtx *mutex)
-{
- /* Free a system mutex. */
- int32_t idx;
-
- if (nr_mutex == 0)
- {
- for (;;);
- }
-
- idx = ((((uint32_t)mutex) - ((uint32_t)&std_libmutex[0].mutex))
- / sizeof(os_mut_array_t));
-
- if (idx >= OS_MUTEXCNT)
- {
- for (;;);
- }
-
- mutex_del (*mutex);
- std_libmutex[idx].used = 0;
-}
-
-/*--------------------------- __iar_system_Mtxlock --------------------------*/
-
-void __iar_system_Mtxlock(__iar_Rmtx *mutex)
-{
- /* Acquire a system mutex, lock stdlib resources. */
- if (runtask_id ())
- {
- /* RTX running, acquire a mutex. */
- mutex_wait (*mutex);
- }
-}
-
-/*--------------------------- __iar_system_Mtxunlock ------------------------*/
-
-void __iar_system_Mtxunlock(__iar_Rmtx *mutex)
-{
- /* Release a system mutex, unlock stdlib resources. */
- if (runtask_id ())
- {
- /* RTX running, release a mutex. */
- mutex_rel (*mutex);
- }
-}
-
-#endif
-
-
-/*----------------------------------------------------------------------------
- * RTX Startup
- *---------------------------------------------------------------------------*/
-
-/* Main Thread definition */
-extern void pre_main (void);
-#ifdef __MBED_CMSIS_RTOS_CA9
-uint32_t os_thread_def_stack_main [(4 * OS_MAINSTKSIZE) / sizeof(uint32_t)];
-osThreadDef_t os_thread_def_main = {(os_pthread)pre_main, osPriorityNormal, 1U, 4*OS_MAINSTKSIZE, os_thread_def_stack_main };
-#else
-osThreadDef_t os_thread_def_main = {(os_pthread)pre_main, osPriorityNormal, 1U, 4*OS_MAINSTKSIZE };
-#endif
-
-#if defined (__CC_ARM)
-
-#ifdef __MICROLIB
-
-int main(void);
-void _main_init (void) __attribute__((section(".ARM.Collect$$$$000000FF")));
-void $Super$$__cpp_initialize__aeabi_(void);
-
-#if __TARGET_ARCH_ARM
-#pragma push
-#pragma arm
-#endif
-void _main_init (void) {
- osKernelInitialize();
- osThreadCreate(&os_thread_def_main, NULL);
- osKernelStart();
- for (;;);
-}
-#if __TARGET_ARCH_ARM
-#pragma pop
-#endif
-
-void $Sub$$__cpp_initialize__aeabi_(void)
-{
- // this should invoke C++ initializers prior _main_init, we keep this empty and
- // invoke them after _main_init (=starts RTX kernel)
-}
-
-void pre_main()
-{
- singleton_mutex_id = osMutexCreate(osMutex(singleton_mutex));
- $Super$$__cpp_initialize__aeabi_();
- main();
-}
-
-#else
-
-void * armcc_heap_base;
-void * armcc_heap_top;
-
-int main(void);
-
-void pre_main (void)
-{
- singleton_mutex_id = osMutexCreate(osMutex(singleton_mutex));
- __rt_lib_init((unsigned)armcc_heap_base, (unsigned)armcc_heap_top);
- main();
-}
-
-__asm void __rt_entry (void) {
-
- IMPORT __user_setup_stackheap
- IMPORT os_thread_def_main
- IMPORT armcc_heap_base
- IMPORT armcc_heap_top
- IMPORT osKernelInitialize
- IMPORT osKernelStart
- IMPORT osThreadCreate
-
- BL __user_setup_stackheap
- LDR R3,=armcc_heap_base
- LDR R4,=armcc_heap_top
- STR R0,[R3]
- STR R2,[R4]
- BL osKernelInitialize
- LDR R0,=os_thread_def_main
- MOVS R1,#0
- BL osThreadCreate
- BL osKernelStart
- /* osKernelStart should not return */
- B .
-
- ALIGN
-}
-#endif
-
-#elif defined (__GNUC__)
-
-osMutexDef(malloc_mutex);
-static osMutexId malloc_mutex_id;
-osMutexDef(env_mutex);
-static osMutexId env_mutex_id;
-
-extern int atexit(void (*func)(void));
-extern void __libc_fini_array(void);
-extern void __libc_init_array (void);
-extern int main(int argc, char **argv);
-
-void pre_main(void) {
- singleton_mutex_id = osMutexCreate(osMutex(singleton_mutex));
- malloc_mutex_id = osMutexCreate(osMutex(malloc_mutex));
- env_mutex_id = osMutexCreate(osMutex(env_mutex));
- __libc_init_array();
- main(0, NULL);
-}
-
-__attribute__((naked)) void software_init_hook_rtos (void) {
- __asm (
- ".syntax unified\n"
- ".arm\n"
- "bl osKernelInitialize\n"
- "ldr r0,=os_thread_def_main\n"
- "movs r1,#0\n"
- "bl osThreadCreate\n"
- "bl osKernelStart\n"
- /* osKernelStart should not return */
- "B .\n"
- );
-}
-
-// Opaque declaration of _reent structure
-struct _reent;
-
-void __rtos_malloc_lock( struct _reent *_r )
-{
- osMutexWait(malloc_mutex_id, osWaitForever);
-}
-
-void __rtos_malloc_unlock( struct _reent *_r )
-{
- osMutexRelease(malloc_mutex_id);
-}
-
-void __rtos_env_lock( struct _reent *_r )
-{
- osMutexWait(env_mutex_id, osWaitForever);
-}
-
-void __rtos_env_unlock( struct _reent *_r )
-{
- osMutexRelease(env_mutex_id);
-}
-
-#elif defined (__ICCARM__)
-extern void* __vector_core_a9;
-extern int __low_level_init(void);
-extern void __iar_data_init3(void);
-extern __weak void __iar_init_core( void );
-extern __weak void __iar_init_vfp( void );
-extern void __iar_dynamic_initialization(void);
-extern void mbed_sdk_init(void);
-extern void mbed_main(void);
-extern int main(void);
-static uint8_t low_level_init_needed;
-
-void pre_main(void) {
- singleton_mutex_id = osMutexCreate(osMutex(singleton_mutex));
- if (low_level_init_needed) {
- __iar_dynamic_initialization();
- }
- mbed_main();
- main();
-}
-
-#pragma required=__vector_core_a9
-void __iar_program_start(void)
-{
- __iar_init_core();
- __iar_init_vfp();
-
- uint8_t low_level_init_needed_local;
-
- low_level_init_needed_local = __low_level_init();
- if (low_level_init_needed_local) {
- __iar_data_init3();
- mbed_sdk_init();
- }
- /* Store in a global variable after RAM has been initialized */
- low_level_init_needed = low_level_init_needed_local;
- osKernelInitialize();
- osThreadCreate(&os_thread_def_main, NULL);
- osKernelStart();
- /* osKernelStart should not return */
- while (1);
-}
-
-#endif
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c b/rtos/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c
deleted file mode 100644
index 97b64a5ec5..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c
+++ /dev/null
@@ -1,353 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RTX_Conf_CM.C
- * Purpose: Configuration of CMSIS RTX Kernel
- * Rev.: V4.80
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-#include "cmsis_os.h"
-
-/*----------------------------------------------------------------------------
- * RTX User configuration part BEGIN
- *---------------------------------------------------------------------------*/
-
-#if defined(MBED_RTOS_SINGLE_THREAD)
-#define OS_TASKCNT 1
-#define OS_TIMERS 0
-#endif
-
-// Include per-target RTX config file
-#include "mbed_rtx.h"
-
-//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
-//
-// Thread Configuration
-// =======================
-//
-// Number of concurrent running user threads <1-250>
-// Defines max. number of user threads that will run at the same time.
-// Default: 6
-#ifndef OS_TASKCNT
- #define OS_TASKCNT 25
-#endif
-
-#ifdef __MBED_CMSIS_RTOS_CA9
-// Idle stack size [bytes] <64-4096:8><#/4>
-// Defines default stack size for the Idle thread.
-#ifndef OS_IDLESTKSIZE
- #define OS_IDLESTKSIZE 128
-#endif
-#else // __MBED_CMSIS_RTOS_CA9
-// Default Thread stack size [bytes] <64-4096:8><#/4>
-// Defines default stack size for threads with osThreadDef stacksz = 0
-// Default: 200
-#ifndef OS_STKSIZE
- #define OS_STKSIZE 200 // this stack size value is in words
-#endif
-#endif // __MBED_CMSIS_RTOS_CA9
-
-// Main Thread stack size [bytes] <64-4096:8><#/4>
-// Defines stack size for main thread.
-// Default: 4096
-#ifndef OS_MAINSTKSIZE
- #define OS_MAINSTKSIZE 4096 // this stack size value is in words
-#endif
-
-#ifndef __MBED_CMSIS_RTOS_CA9
-// Number of threads with user-provided stack size <0-250>
-// Defines the number of threads with user-provided stack size.
-// Default: 0
-#ifndef OS_PRIVCNT
- #define OS_PRIVCNT 0
-#endif
-
-// Total stack size [bytes] for threads with user-provided stack size <0-4096:8><#/4>
-// Defines the combined stack size for threads with user-provided stack size.
-// Default: 0
-#ifndef OS_PRIVSTKSIZE
- #define OS_PRIVSTKSIZE 0 // this stack size value is in words
-#endif
-#endif // __MBED_CMSIS_RTOS_CA9
-
-// Stack overflow checking
-// Enable stack overflow checks at thread switch.
-// Enabling this option increases slightly the execution time of a thread switch.
-#ifndef OS_STKCHECK
- #define OS_STKCHECK 1
-#endif
-
-// Stack usage watermark
-// Initialize thread stack with watermark pattern for analyzing stack usage (current/maximum) in System and Thread Viewer.
-// Enabling this option increases significantly the execution time of osThreadCreate.
-#ifndef OS_STKINIT
- #if (defined(MBED_STACK_STATS_ENABLED) && MBED_STACK_STATS_ENABLED)
- #define OS_STKINIT 1
- #else
- #define OS_STKINIT 0
- #endif
-#endif
-
-// Processor mode for thread execution
-// <0=> Unprivileged mode
-// <1=> Privileged mode
-// Default: Privileged mode
-#ifndef OS_RUNPRIV
- #define OS_RUNPRIV 1
-#endif
-
-//
-
-// RTX Kernel Timer Tick Configuration
-// ======================================
-// Use Cortex-M SysTick timer as RTX Kernel Timer
-// Cortex-M processors provide in most cases a SysTick timer that can be used as
-// as time-base for RTX.
-#ifndef OS_SYSTICK
- #define OS_SYSTICK 0
-#endif
-//
-// RTOS Kernel Timer input clock frequency [Hz] <1-1000000000>
-// Defines the input frequency of the RTOS Kernel Timer.
-// Default: 12000000 (12MHz)
-// is on most systems identical with the core clock.
-#ifndef OS_CLOCK
- #error "no target defined"
-#endif
-
-// RTX Timer tick interval value [us] <1-1000000>
-// The RTX Timer tick interval value is used to calculate timeout values.
-// Default: 1000 (1ms)
-#ifndef OS_TICK
- #define OS_TICK 1000
-#endif
-
-//
-
-// System Configuration
-// =======================
-//
-// Round-Robin Thread switching
-// ===============================
-//
-// Enables Round-Robin Thread switching.
-#ifndef OS_ROBIN
- #define OS_ROBIN 1
-#endif
-
-// Round-Robin Timeout [ticks] <1-1000>
-// Defines how long a thread will execute before a thread switch.
-// Default: 5
-#ifndef OS_ROBINTOUT
- #define OS_ROBINTOUT 5
-#endif
-
-//
-
-// User Timers
-// ==============
-// Enables user Timers
-#ifndef OS_TIMERS
- #define OS_TIMERS 1
-#endif
-
-// Timer Thread Priority
-// <1=> Low
-// <2=> Below Normal <3=> Normal <4=> Above Normal
-// <5=> High
-// <6=> Realtime (highest)
-// Defines priority for Timer Thread
-// Default: High
-#ifndef OS_TIMERPRIO
- #define OS_TIMERPRIO 5
-#endif
-
-// Timer Thread stack size [bytes] <64-4096:8><#/4>
-// Defines stack size for Timer thread.
-// Default: 200
-#ifndef OS_TIMERSTKSZ
- #define OS_TIMERSTKSZ WORDS_STACK_SIZE // this stack size value is in words
-#endif
-
-// Timer Callback Queue size <1-32>
-// Number of concurrent active timer callback functions.
-// Default: 4
-#ifndef OS_TIMERCBQS
- #define OS_TIMERCBQS 4
-#endif
-
-//
-
-// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries
-// <12=> 12 entries <16=> 16 entries
-// <24=> 24 entries <32=> 32 entries
-// <48=> 48 entries <64=> 64 entries
-// <96=> 96 entries
-// ISR functions store requests to this buffer,
-// when they are called from the interrupt handler.
-// Default: 16 entries
-#ifndef OS_FIFOSZ
- #define OS_FIFOSZ 16
-#endif
-
-//
-
-//------------- <<< end of configuration section >>> -----------------------
-
-// Standard library system mutexes
-// ===============================
-// Define max. number system mutexes that are used to protect
-// the arm standard runtime library. For microlib they are not used.
-#ifndef OS_MUTEXCNT
- #define OS_MUTEXCNT 12
-#endif
-
-/*----------------------------------------------------------------------------
- * RTX User configuration part END
- *---------------------------------------------------------------------------*/
-
-#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
-
-
-/*----------------------------------------------------------------------------
- * Global Functions
- *---------------------------------------------------------------------------*/
-
-/*--------------------------- os_idle_demon ---------------------------------*/
-extern void rtos_idle_loop(void);
-
-/// \brief The idle demon is running when no other thread is ready to run
-void os_idle_demon (void) {
- rtos_idle_loop();
-}
-
-#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer
-
-/*--------------------------- os_tick_init ----------------------------------*/
-#if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H)
-#define OSTM0 (0xFCFEC000uL) /* OSTM0 */
-#define OSTM1 (0xFCFEC400uL) /* OSTM1 */
-#define CPG (0xFCFE0410uL) /* CPG */
-
-#define CPGSTBCR5 (*((volatile unsigned char*)(CPG + 0x00000018uL)))
-
-#define OSTM0CMP (*((volatile unsigned long*)(OSTM0 + 0x00000000uL)))
-#define OSTM0CNT (*((volatile unsigned long*)(OSTM0 + 0x00000004uL)))
-#define OSTM0TE (*((volatile unsigned char*)(OSTM0 + 0x00000010uL)))
-#define OSTM0TS (*((volatile unsigned char*)(OSTM0 + 0x00000014uL)))
-#define OSTM0TT (*((volatile unsigned char*)(OSTM0 + 0x00000018uL)))
-#define OSTM0CTL (*((volatile unsigned char*)(OSTM0 + 0x00000020uL)))
-
-#define OSTM1CMP (*((volatile unsigned long*)(OSTM1 + 0x00000000uL)))
-#define OSTM1CNT (*((volatile unsigned long*)(OSTM1 + 0x00000004uL)))
-#define OSTM1TE (*((volatile unsigned char*)(OSTM1 + 0x00000010uL)))
-#define OSTM1TS (*((volatile unsigned char*)(OSTM1 + 0x00000014uL)))
-#define OSTM1TT (*((volatile unsigned char*)(OSTM1 + 0x00000018uL)))
-#define OSTM1CTL (*((volatile unsigned char*)(OSTM1 + 0x00000020uL)))
-
-#define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */
-#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
-#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
-
-typedef enum
-{
- IRQ_SGI0 = 0,
- IRQ_OSTMI0TINT = 134
-} IRQn_Type;
-
-typedef void(*IRQHandler)();
-
-extern void PendSV_Handler(uint32_t);
-extern void OS_Tick_Handler(uint32_t);
-extern uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler);
-#endif
-
-/// \brief Initializes an alternative hardware timer as RTX kernel timer
-/// \return IRQ number of the alternative hardware timer
-int os_tick_init (void) {
-#if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H)
- CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP51); /* enable OSTM0 clock */
-
- OSTM0TT = 0x1; /* Stop the counter and clears the OSTM0TE bit. */
- OSTM0CTL = 0x1; /* Interval timer mode. Interrupt enabled */
-
- OSTM0CMP = (uint32_t)(((double)CM0_RENESAS_RZ_A1_P0_CLK*(double)OS_TICK)/1E6);
-
- OSTM0TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */
-
- InterruptHandlerRegister(IRQ_SGI0 , (IRQHandler)PendSV_Handler);
- InterruptHandlerRegister(IRQ_OSTMI0TINT, (IRQHandler)OS_Tick_Handler);
-
-
- return IRQ_OSTMI0TINT; /* Return IRQ number of timer (0..239) */
- /* RTX will set and configure the interrupt */
-#endif
-}
-
-/*--------------------------- os_tick_irqack --------------------------------*/
-
-/// \brief Acknowledge alternative hardware timer interrupt
-void os_tick_irqack (void) {
- /* ... */
-}
-
-#endif // (OS_SYSTICK == 0)
-
-/*--------------------------- os_error --------------------------------------*/
-extern void error(const char* format, ...);
-extern osThreadId svcThreadGetId (void);
-
-void os_error (uint32_t err_code) {
- /* This function is called when a runtime error is detected. Parameter */
- /* 'err_code' holds the runtime error code (defined in RTX_Config.h). */
- osThreadId err_task = svcThreadGetId();
- error("RTX error code: 0x%08X, task ID: 0x%08X\n", err_code, err_task);
-
- /* HERE: include optional code to be executed on runtime error. */
- for (;;);
-}
-
-/*----------------------------------------------------------------------------
- * RTX Hooks
- *---------------------------------------------------------------------------*/
-extern void thread_terminate_hook(osThreadId id);
-
-void sysThreadTerminate(osThreadId id) {
- thread_terminate_hook(id);
-}
-
-/*----------------------------------------------------------------------------
- * RTX Configuration Functions
- *---------------------------------------------------------------------------*/
-
-#include "RTX_CM_lib.h"
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/RTX_Config.h b/rtos/rtx/TARGET_CORTEX_A/RTX_Config.h
deleted file mode 100644
index d6f5161c47..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/RTX_Config.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RTX_CONFIG.H
- * Purpose: Exported functions of RTX_Config.c
- * Rev.: V4.79
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-
-/* Error Codes */
-#define OS_ERR_STK_OVF 1U
-#define OS_ERR_FIFO_OVF 2U
-#define OS_ERR_MBX_OVF 3U
-#define OS_ERR_TIMER_OVF 4U
-
-/* Definitions */
-#define BOX_ALIGN_8 0x80000000U
-#define _declare_box(pool,size,cnt) U32 pool[(((size)+3)/4)*(cnt) + 3]
-#define _declare_box8(pool,size,cnt) U64 pool[(((size)+7)/8)*(cnt) + 2]
-#define _init_box8(pool,size,bsize) _init_box (pool,size,(bsize) | BOX_ALIGN_8)
-
-/* Variables */
-extern U32 mp_tcb[];
-extern U64 mp_stk[];
-extern U32 os_fifo[];
-extern void *os_active_TCB[];
-
-/* Constants */
-extern U16 const os_maxtaskrun;
-extern U32 const os_trv;
-extern U8 const os_flags;
-extern U32 const os_stackinfo;
-extern U32 const os_rrobin;
-extern U32 const os_clockrate;
-extern U32 const os_timernum;
-extern U16 const mp_tcb_size;
-extern U32 const mp_stk_size;
-extern U32 const *m_tmr;
-extern U16 const mp_tmr_size;
-extern U8 const os_fifo_size;
-
-/* Functions */
-extern void os_idle_demon (void);
-extern S32 os_tick_init (void);
-extern U32 os_tick_val (void);
-extern U32 os_tick_ovf (void);
-extern void os_tick_irqack (void);
-extern void os_tmr_call (U16 info);
-extern void os_error (U32 err_code);
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/HAL_CA9.c b/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/HAL_CA9.c
deleted file mode 100644
index fad36ca440..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/HAL_CA9.c
+++ /dev/null
@@ -1,438 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: HAL_CA9.c
- * Purpose: Hardware Abstraction Layer for Cortex-A9 (GICv1)
- * Rev.: 28 April 2016
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 2012 - 2016 ARM Limited
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-#include "rt_TypeDef.h"
-#include "RTX_Config.h"
-#include "rt_System.h"
-#include "rt_Task.h"
-#include "rt_List.h"
-#include "rt_MemBox.h"
-#include "rt_HAL_CA.h"
-
-
-/*----------------------------------------------------------------------------
- * Functions
- *---------------------------------------------------------------------------*/
-
-//For A-class, set USR/SYS stack
-__asm void rt_set_PSP (U32 stack) {
- ARM
-
- MRS R1, CPSR
- CPS #MODE_SYS ;no effect in USR mode
- ISB
- MOV SP, R0
- MSR CPSR_c, R1 ;no effect in USR mode
- ISB
- BX LR
-
-}
-
-//For A-class, get USR/SYS stack
-__asm U32 rt_get_PSP (void) {
- ARM
-
- MRS R1, CPSR
- CPS #MODE_SYS ;no effect in USR mode
- ISB
- MOV R0, SP
- MSR CPSR_c, R1 ;no effect in USR mode
- ISB
- BX LR
-}
-
-/*--------------------------- _alloc_box ------------------------------------*/
-__asm void *_alloc_box (void *box_mem) {
- /* Function wrapper for Unprivileged/Privileged mode. */
- ARM
-
- LDR R12,=__cpp(rt_alloc_box)
- MRS R2, CPSR
- LSLS R2, #28
- BXNE R12
- SVC 0
- BX LR
-}
-
-
-/*--------------------------- _free_box -------------------------------------*/
-__asm U32 _free_box (void *box_mem, void *box) {
- /* Function wrapper for Unprivileged/Privileged mode. */
- ARM
-
- LDR R12,=__cpp(rt_free_box)
- MRS R2, CPSR
- LSLS R2, #28
- BXNE R12
- SVC 0
- BX LR
-
-}
-
-/*-------------------------- SVC_Handler -----------------------------------*/
-
-#pragma push
-#pragma arm
-__asm void SVC_Handler (void) {
- PRESERVE8
- ARM
-
- IMPORT rt_tsk_lock
- IMPORT rt_tsk_unlock
- IMPORT SVC_Count
- IMPORT SVC_Table
- IMPORT rt_stk_check
- IMPORT FPUEnable
- IMPORT scheduler_suspended ; Flag set by rt_suspend, cleared by rt_resume, read by SVC_Handler
-
-Mode_SVC EQU 0x13
-
- SRSFD SP!, #Mode_SVC ; Push LR_SVC and SPRS_SVC onto SVC mode stack
- PUSH {R4} ; Push R4 so we can use it as a temp
-
- MRS R4,SPSR ; Get SPSR
- TST R4,#CPSR_T_BIT ; Check Thumb Bit
- LDRNEH R4,[LR,#-2] ; Thumb: Load Halfword
- BICNE R4,R4,#0xFF00 ; Extract SVC Number
- LDREQ R4,[LR,#-4] ; ARM: Load Word
- BICEQ R4,R4,#0xFF000000 ; Extract SVC Number
-
- /* Lock out systick and re-enable interrupts */
- PUSH {R0-R3,R12,LR}
-
- AND R12, SP, #4 ; Ensure stack is 8-byte aligned
- SUB SP, SP, R12 ; Adjust stack
- PUSH {R12, LR} ; Store stack adjustment and dummy LR to SVC stack
-
- BLX rt_tsk_lock
- CPSIE i
-
- POP {R12, LR} ; Get stack adjustment & discard dummy LR
- ADD SP, SP, R12 ; Unadjust stack
-
- POP {R0-R3,R12,LR}
-
- CMP R4,#0
- BNE SVC_User
-
- MRS R4,SPSR
- PUSH {R4} ; Push R4 so we can use it as a temp
- AND R4, SP, #4 ; Ensure stack is 8-byte aligned
- SUB SP, SP, R4 ; Adjust stack
- PUSH {R4, LR} ; Store stack adjustment and dummy LR
- BLX R12
- POP {R4, LR} ; Get stack adjustment & discard dummy LR
- ADD SP, SP, R4 ; Unadjust stack
- POP {R4} ; Restore R4
- MSR SPSR_CXSF,R4
-
- /* Here we will be in SVC mode (even if coming in from PendSV_Handler or OS_Tick_Handler) */
-Sys_Switch
- LDR LR,=__cpp(&os_tsk)
- LDM LR,{R4,LR} ; os_tsk.run, os_tsk.new_tsk
- CMP R4,LR
- BNE switching
-
- PUSH {R0-R3,R12,LR}
-
- AND R12, SP, #4 ; Ensure stack is 8-byte aligned
- SUB SP, SP, R12 ; Adjust stack
- PUSH {R12, LR} ; Store stack adjustment and dummy LR to SVC stack
-
- CPSID i
- ; Do not unlock scheduler if it has just been suspended by rt_suspend()
- LDR R1,=scheduler_suspended
- LDRB R0, [R1]
- CMP R0, #1
- BEQ dont_unlock
- BLX rt_tsk_unlock
-dont_unlock
-
- POP {R12, LR} ; Get stack adjustment & discard dummy LR
- ADD SP, SP, R12 ; Unadjust stack
-
- POP {R0-R3,R12,LR}
- POP {R4}
- RFEFD SP! ; Return from exception, no task switch
-
-switching
- CLREX
- CMP R4,#0
- ADDEQ SP,SP,#12 ; Original R4, LR & SPSR do not need to be popped when we are paging in a different task
- BEQ SVC_Next ; Runtask deleted?
-
-
- PUSH {R8-R11} //R4 and LR already stacked
- MOV R10,R4 ; Preserve os_tsk.run
- MOV R11,LR ; Preserve os_tsk.new_tsk
-
- ADD R8,SP,#16 ; Unstack R4,LR
- LDMIA R8,{R4,LR}
-
- SUB SP,SP,#4 ; Make space on the stack for the next instn
- STMIA SP,{SP}^ ; Put User SP onto stack
- POP {R8} ; Pop User SP into R8
-
- MRS R9,SPSR
- STMDB R8!,{R9} ; User CPSR
- STMDB R8!,{LR} ; User PC
- STMDB R8,{LR}^ ; User LR
- SUB R8,R8,#4 ; No writeback for store of User LR
- STMDB R8!,{R0-R3,R12} ; User R0-R3,R12
- MOV R3,R10 ; os_tsk.run
- MOV LR,R11 ; os_tsk.new_tsk
- POP {R9-R12}
- ADD SP,SP,#12 ; Fix up SP for unstack of R4, LR & SPSR
- STMDB R8!,{R4-R7,R9-R12} ; User R4-R11
-
- //If applicable, stack VFP/NEON state
- MRC p15,0,R1,c1,c0,2 ; VFP/NEON access enabled? (CPACR)
- AND R2,R1,#0x00F00000
- CMP R2,#0x00F00000
- BNE no_outgoing_vfp
- VMRS R2,FPSCR
- STMDB R8!,{R2,R4} ; Push FPSCR, maintain 8-byte alignment
- VSTMDB R8!,{D0-D15}
- VSTMDB R8!,{D16-D31}
- LDRB R2,[R3,#TCB_STACKF] ; Record in TCB that NEON/D32 state is stacked
- ORR R2,#4
- STRB R2,[R3,#TCB_STACKF]
-
-no_outgoing_vfp
- STR R8,[R3,#TCB_TSTACK]
- MOV R4,LR
-
- PUSH {R4} ; Push R4 so we can use it as a temp
- AND R4, SP, #4 ; Ensure stack is 8-byte aligned
- SUB SP, SP, R4 ; Adjust stack
- PUSH {R4, LR} ; Store stack adjustment and dummy LR to SVC stack
-
- BLX rt_stk_check
-
- POP {R4, LR} ; Get stack adjustment & discard dummy LR
- ADD SP, SP, R4 ; Unadjust stack
- POP {R4} ; Restore R4
-
- MOV LR,R4
-
-SVC_Next //R4 == os_tsk.run, LR == os_tsk.new_tsk, R0-R3, R5-R12 corruptible
- LDR R1,=__cpp(&os_tsk) ; os_tsk.run = os_tsk.new_tsk
- STR LR,[R1]
- LDRB R1,[LR,#TCB_TID] ; os_tsk.run->task_id
- LSL R1,#8 ; Store PROCID
- MCR p15,0,R1,c13,c0,1 ; Write CONTEXTIDR
-
- LDR R0,[LR,#TCB_TSTACK] ; os_tsk.run->tsk_stack
-
- //Does incoming task have VFP/NEON state in stack?
- LDRB R3,[LR,#TCB_STACKF]
- ANDS R3, R3, #0x6
- MRC p15,0,R1,c1,c0,2 ; Read CPACR
- ANDEQ R1,R1,#0xFF0FFFFF ; Disable VFP/NEON access if incoming task does not have stacked VFP/NEON state
- ORRNE R1,R1,#0x00F00000 ; Enable VFP/NEON access if incoming task does have stacked VFP/NEON state
- MCR p15,0,R1,c1,c0,2 ; Write CPACR
- BEQ no_incoming_vfp
- ISB ; We only need the sync if we enabled, otherwise we will context switch before next VFP/NEON instruction anyway
- VLDMIA R0!,{D16-D31}
- VLDMIA R0!,{D0-D15}
- LDR R2,[R0]
- VMSR FPSCR,R2
- ADD R0,R0,#8
-
-no_incoming_vfp
- LDR R1,[R0,#60] ; Restore User CPSR
- MSR SPSR_CXSF,R1
- LDMIA R0!,{R4-R11} ; Restore User R4-R11
- ADD R0,R0,#4 ; Restore User R1-R3,R12
- LDMIA R0!,{R1-R3,R12}
- LDMIA R0,{LR}^ ; Restore User LR
- ADD R0,R0,#4 ; No writeback for load to user LR
- LDMIA R0!,{LR} ; Restore User PC
- ADD R0,R0,#4 ; Correct User SP for unstacked user CPSR
-
- PUSH {R0} ; Push R0 onto stack
- LDMIA SP,{SP}^ ; Get R0 off stack into User SP
- ADD SP,SP,#4 ; Put SP back
-
- LDR R0,[R0,#-32] ; Restore R0
-
- PUSH {R0-R3,R12,LR}
-
- AND R12, SP, #4 ; Ensure stack is 8-byte aligned
- SUB SP, SP, R12 ; Adjust stack
- PUSH {R12, LR} ; Store stack adjustment and dummy LR to SVC stack
-
- CPSID i
- BLX rt_tsk_unlock
-
- POP {R12, LR} ; Get stack adjustment & discard dummy LR
- ADD SP, SP, R12 ; Unadjust stack
-
- POP {R0-R3,R12,LR}
-
- MOVS PC,LR ; Return from exception
-
-
- /*------------------- User SVC -------------------------------*/
-
-SVC_User
- LDR R12,=SVC_Count
- LDR R12,[R12]
- CMP R4,R12 ; Check for overflow
- BHI SVC_Done
-
- LDR R12,=SVC_Table-4
- LDR R12,[R12,R4,LSL #2] ; Load SVC Function Address
- MRS R4,SPSR ; Save SPSR
- PUSH {R4} ; Push R4 so we can use it as a temp
- AND R4, SP, #4 ; Ensure stack is 8-byte aligned
- SUB SP, SP, R4 ; Adjust stack
- PUSH {R4, LR} ; Store stack adjustment and dummy LR
- BLX R12 ; Call SVC Function
- POP {R4, LR} ; Get stack adjustment & discard dummy LR
- ADD SP, SP, R4 ; Unadjust stack
- POP {R4} ; Restore R4
- MSR SPSR_CXSF,R4 ; Restore SPSR
-
-SVC_Done
- PUSH {R0-R3,R12,LR}
-
- PUSH {R4} ; Push R4 so we can use it as a temp
- AND R4, SP, #4 ; Ensure stack is 8-byte aligned
- SUB SP, SP, R4 ; Adjust stack
- PUSH {R4, LR} ; Store stack adjustment and dummy LR
-
- CPSID i
- BLX rt_tsk_unlock
-
- POP {R4, LR} ; Get stack adjustment & discard dummy LR
- ADD SP, SP, R4 ; Unadjust stack
- POP {R4} ; Restore R4
-
- POP {R0-R3,R12,LR}
- POP {R4}
- RFEFD SP! ; Return from exception
-}
-#pragma pop
-
-#pragma push
-#pragma arm
-__asm void PendSV_Handler (U32 IRQn) {
- ARM
-
- IMPORT rt_tsk_lock
- IMPORT IRQNestLevel ; Flag indicates whether inside an ISR, and the depth of nesting. 0 = not in ISR.
- IMPORT seen_id0_active ; Flag used to workaround GIC 390 errata 733075 (set in startup_.s)
-
- ADD SP,SP,#8 //fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment)
-
- //Disable systick interrupts, then write EOIR. We want interrupts disabled before we enter the context switcher.
- PUSH {R0, R1}
- BLX rt_tsk_lock
- POP {R0, R1}
- LDR R1, =__cpp(&GICInterface_BASE)
- LDR R1, [R1, #0]
- STR R0, [R1, #0x10] ; Write End Of Interrupt ID to GICC_EOIR
-
- ; If it was interrupt ID0, clear the seen flag, otherwise return as normal
- CMP R0, #0
- LDREQ R1, =seen_id0_active
- STRBEQ R0, [R1] ; Clear the seen flag, using R0 (which is 0), to save loading another register
-
- LDR R0, =IRQNestLevel ; Get address of nesting counter
- LDR R1, [R0]
- SUB R1, R1, #1 ; Decrement nesting counter
- STR R1, [R0]
-
- BLX __cpp(rt_pop_req)
-
- POP {R1, LR} ; Get stack adjustment & discard dummy LR
- ADD SP, SP, R1 ; Unadjust stack
-
- LDR R0,[SP,#24]
- MSR SPSR_CXSF,R0
- POP {R0-R3,R12} ; Leave SPSR & LR on the stack
- PUSH {R4}
- B Sys_Switch
-}
-#pragma pop
-
-
-#pragma push
-#pragma arm
-__asm void OS_Tick_Handler (U32 IRQn) {
- ARM
-
- IMPORT rt_tsk_lock
- IMPORT IRQNestLevel ; Flag indicates whether inside an ISR, and the depth of nesting. 0 = not in ISR.
- IMPORT seen_id0_active ; Flag used to workaround GIC 390 errata 733075 (set in startup_.s)
-
- ADD SP,SP,#8 //fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment)
-
- //Disable systick interrupts, then write EOIR. We want interrupts disabled before we enter the context switcher.
- PUSH {R0, R1}
- BLX rt_tsk_lock
- POP {R0, R1}
- LDR R1, =__cpp(&GICInterface_BASE)
- LDR R1, [R1, #0]
- STR R0, [R1, #0x10] ; Write End Of Interrupt ID to GICC_EOIR
-
- ; If it was interrupt ID0, clear the seen flag, otherwise return as normal
- CMP R0, #0
- LDREQ R1, =seen_id0_active
- STRBEQ R0, [R1] ; Clear the seen flag, using R0 (which is 0), to save loading another register
-
- LDR R0, =IRQNestLevel ; Get address of nesting counter
- LDR R1, [R0]
- SUB R1, R1, #1 ; Decrement nesting counter
- STR R1, [R0]
-
- BLX __cpp(os_tick_irqack)
- BLX __cpp(rt_systick)
-
- POP {R1, LR} ; Get stack adjustment & discard dummy LR
- ADD SP, SP, R1 ; Unadjust stack
-
- LDR R0,[SP,#24]
- MSR SPSR_CXSF,R0
- POP {R0-R3,R12} ; Leave SPSR & LR on the stack
- PUSH {R4}
- B Sys_Switch
-}
-#pragma pop
-
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/SVC_Table.S b/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/SVC_Table.S
deleted file mode 100644
index 37e8429080..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/SVC_Table.S
+++ /dev/null
@@ -1,57 +0,0 @@
-;/*----------------------------------------------------------------------------
-; * CMSIS-RTOS - RTX
-; *----------------------------------------------------------------------------
-; * Name: SVC_TABLE.S
-; * Purpose: Pre-defined SVC Table
-; * Rev.: V4.70, with additions for Cortex-A
-; *----------------------------------------------------------------------------
-; *
-; * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH, 2014-2015 ARM Ltd
-; * All rights reserved.
-; * Redistribution and use in source and binary forms, with or without
-; * modification, are permitted provided that the following conditions are met:
-; * - Redistributions of source code must retain the above copyright
-; * notice, this list of conditions and the following disclaimer.
-; * - Redistributions in binary form must reproduce the above copyright
-; * notice, this list of conditions and the following disclaimer in the
-; * documentation and/or other materials provided with the distribution.
-; * - Neither the name of ARM nor the names of its contributors may be used
-; * to endorse or promote products derived from this software without
-; * specific prior written permission.
-; *
-; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-; * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-; * POSSIBILITY OF SUCH DAMAGE.
-; *---------------------------------------------------------------------------*/
-
-
- AREA SVC_TABLE, CODE, READONLY
-
- EXPORT SVC_Count
-
-SVC_Cnt EQU (SVC_End-SVC_Table)/4
-SVC_Count DCD SVC_Cnt
-
-; Import user SVC functions here.
-; IMPORT __SVC_1
-
- EXPORT SVC_Table
-SVC_Table
-; Insert user SVC functions here. SVC 0 used by RTX Kernel.
-; DCD __SVC_1 ; EnableCaches
-
-SVC_End
-
- END
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_GCC/HAL_CA9.S b/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_GCC/HAL_CA9.S
deleted file mode 100644
index 17cd8e2897..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_GCC/HAL_CA9.S
+++ /dev/null
@@ -1,473 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: HAL_CA9.c
- * Purpose: Hardware Abstraction Layer for Cortex-A9 (GICv1)
- * Rev.: 28 April 2016
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 2012 - 2016 ARM Limited
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
- .global rt_set_PSP
- .global rt_get_PSP
- .global _alloc_box
- .global _free_box
- .global SVC_Handler
- .global PendSV_Handler
- .global OS_Tick_Handler
-
-/* macro defines form rt_HAL_CA.h */
- .EQU CPSR_T_BIT, 0x20
- .EQU CPSR_I_BIT, 0x80
- .EQU CPSR_F_BIT, 0x40
-
- .EQU MODE_USR, 0x10
- .EQU MODE_FIQ, 0x11
- .EQU MODE_IRQ, 0x12
- .EQU MODE_SVC, 0x13
- .EQU MODE_ABT, 0x17
- .EQU MODE_UND, 0x1B
- .EQU MODE_SYS, 0x1F
-
-/* macro defines form rt_TypeDef.h */
- .EQU TCB_TID, 3 /* 'task id' offset */
- .EQU TCB_STACKF, 37 /* 'stack_frame' offset */
- .EQU TCB_TSTACK, 44 /* 'tsk_stack' offset for LARGE_STACK */
-
-
- .extern rt_alloc_box
- .extern os_tsk
- .extern GICInterface_BASE
- .extern rt_pop_req
- .extern os_tick_irqack
- .extern rt_systick
-
- .text
-
-/*----------------------------------------------------------------------------
- * Functions
- *---------------------------------------------------------------------------*/
-
-@ For A-class, set USR/SYS stack
-@ __asm void rt_set_PSP (U32 stack) {
-rt_set_PSP:
- .ARM
-
- MRS R1, CPSR
- CPS #MODE_SYS @no effect in USR mode
- ISB
- MOV SP, R0
- MSR CPSR_c, R1 @no effect in USR mode
- ISB
- BX LR
-
-@ }
-
-@ For A-class, get USR/SYS stack
-@ __asm U32 rt_get_PSP (void) {
-rt_get_PSP:
- .ARM
-
- MRS R1, CPSR
- CPS #MODE_SYS @no effect in USR mode
- ISB
- MOV R0, SP
- MSR CPSR_c, R1 @no effect in USR mode
- ISB
- BX LR
-@ }
-
-/*--------------------------- _alloc_box ------------------------------------*/
-@ __asm void *_alloc_box (void *box_mem) {
-_alloc_box:
- /* Function wrapper for Unprivileged/Privileged mode. */
- .ARM
-
- LDR R12,=rt_alloc_box
- MRS R2, CPSR
- LSLS R2, #28
- BXNE R12
- SVC 0
- BX LR
-@ }
-
-
-/*--------------------------- _free_box -------------------------------------*/
-@ __asm U32 _free_box (void *box_mem, void *box) {
-_free_box:
- /* Function wrapper for Unprivileged/Privileged mode. */
- .ARM
-
- LDR R12,=rt_free_box
- MRS R2, CPSR
- LSLS R2, #28
- BXNE R12
- SVC 0
- BX LR
-
-@ }
-
-/*-------------------------- SVC_Handler -----------------------------------*/
-
-@ #pragma push
-@ #pragma arm
-@ __asm void SVC_Handler (void) {
-SVC_Handler:
- .eabi_attribute Tag_ABI_align8_preserved,1
- .ARM
-
- .extern rt_tsk_lock
- .extern rt_tsk_unlock
- .extern SVC_Count
- .extern SVC_Table
- .extern rt_stk_check
- .extern FPUEnable
- .extern scheduler_suspended @ flag set by rt_suspend, cleared by rt_resume, read by SVC_Handler
-
- .EQU Mode_SVC, 0x13
-
- SRSDB SP!, #Mode_SVC @ Push LR_SVC and SPRS_SVC onto SVC mode stack @ Use SRSDB because SRSFD isn't supported by GCC-ARM.
- PUSH {R4} @ Push R4 so we can use it as a temp
-
- MRS R4,SPSR @ Get SPSR
- TST R4,#CPSR_T_BIT @ Check Thumb Bit
- LDRNEH R4,[LR,#-2] @ Thumb: Load Halfword
- BICNE R4,R4,#0xFF00 @ Extract SVC Number
- LDREQ R4,[LR,#-4] @ ARM: Load Word
- BICEQ R4,R4,#0xFF000000 @ Extract SVC Number
-
- /* Lock out systick and re-enable interrupts */
- PUSH {R0-R3,R12,LR}
-
- AND R12, SP, #4 @ Ensure stack is 8-byte aligned
- SUB SP, SP, R12 @ Adjust stack
- PUSH {R12, LR} @ Store stack adjustment and dummy LR to SVC stack
-
- BLX rt_tsk_lock
- CPSIE i
-
- POP {R12, LR} @ Get stack adjustment & discard dummy LR
- ADD SP, SP, R12 @ Unadjust stack
-
- POP {R0-R3,R12,LR}
-
- CMP R4,#0
- BNE SVC_User
-
- MRS R4,SPSR
- PUSH {R4} @ Push R4 so we can use it as a temp
- AND R4, SP, #4 @ Ensure stack is 8-byte aligned
- SUB SP, SP, R4 @ Adjust stack
- PUSH {R4, LR} @ Store stack adjustment and dummy LR
- BLX R12
- POP {R4, LR} @ Get stack adjustment & discard dummy LR
- ADD SP, SP, R4 @ Unadjust stack
- POP {R4} @ Restore R4
- MSR SPSR_cxsf,R4
-
- /* Here we will be in SVC mode (even if coming in from PendSV_Handler or OS_Tick_Handler) */
-Sys_Switch:
- LDR LR,=os_tsk
- LDM LR,{R4,LR} @ os_tsk.run, os_tsk.new_tsk
- CMP R4,LR
- BNE switching
-
- PUSH {R0-R3,R12,LR}
-
- AND R12, SP, #4 @ Ensure stack is 8-byte aligned
- SUB SP, SP, R12 @ Adjust stack
- PUSH {R12, LR} @ Store stack adjustment and dummy LR to SVC stack
-
- CPSID i
- @ Do not unlock scheduler if it has just been suspended by rt_suspend()
- LDR R1,=scheduler_suspended
- LDRB R0, [R1]
- CMP R0, #1
- BEQ dont_unlock
- BLX rt_tsk_unlock
-dont_unlock:
-
- POP {R12, LR} @ Get stack adjustment & discard dummy LR
- ADD SP, SP, R12 @ Unadjust stack
-
- POP {R0-R3,R12,LR}
- POP {R4}
- RFEFD SP! @ Return from exception, no task switch
-
-switching:
- CLREX
- CMP R4,#0
- ADDEQ SP,SP,#12 @ Original R4, LR & SPSR do not need to be popped when we are paging in a different task
- BEQ SVC_Next @ Runtask deleted?
-
-
- PUSH {R8-R11} @ R4 and LR already stacked
- MOV R10,R4 @ Preserve os_tsk.run
- MOV R11,LR @ Preserve os_tsk.new_tsk
-
- ADD R8,SP,#16 @ Unstack R4,LR
- LDMIA R8,{R4,LR}
-
- SUB SP,SP,#4 @ Make space on the stack for the next instn
- STMIA SP,{SP}^ @ Put User SP onto stack
- POP {R8} @ Pop User SP into R8
-
- MRS R9,SPSR
- STMDB R8!,{R9} @ User CPSR
- STMDB R8!,{LR} @ User PC
- STMDB R8,{LR}^ @ User LR
- SUB R8,R8,#4 @ No writeback for store of User LR
- STMDB R8!,{R0-R3,R12} @ User R0-R3,R12
- MOV R3,R10 @ os_tsk.run
- MOV LR,R11 @ os_tsk.new_tsk
- POP {R9-R12}
- ADD SP,SP,#12 @ Fix up SP for unstack of R4, LR & SPSR
- STMDB R8!,{R4-R7,R9-R12} @ User R4-R11
-
- @ If applicable, stack VFP/NEON state
- MRC p15,0,R1,c1,c0,2 @ VFP/NEON access enabled? (CPACR)
- AND R2,R1,#0x00F00000
- CMP R2,#0x00F00000
- BNE no_outgoing_vfp
- VMRS R2,FPSCR
- STMDB R8!,{R2,R4} @ Push FPSCR, maintain 8-byte alignment
- VSTMDB R8!,{D0-D15}
- VSTMDB R8!,{D16-D31}
- LDRB R2,[R3,#TCB_STACKF] @ Record in TCB that NEON/D32 state is stacked
- ORR R2,#4
- STRB R2,[R3,#TCB_STACKF]
-
-no_outgoing_vfp:
- STR R8,[R3,#TCB_TSTACK]
- MOV R4,LR
-
- PUSH {R4} @ Push R4 so we can use it as a temp
- AND R4, SP, #4 @ Ensure stack is 8-byte aligned
- SUB SP, SP, R4 @ Adjust stack
- PUSH {R4, LR} @ Store stack adjustment and dummy LR to SVC stack
-
- BLX rt_stk_check
-
- POP {R4, LR} @ Get stack adjustment & discard dummy LR
- ADD SP, SP, R4 @ Unadjust stack
- POP {R4} @ Restore R4
-
- MOV LR,R4
-
-SVC_Next: @ R4 == os_tsk.run, LR == os_tsk.new_tsk, R0-R3, R5-R12 corruptible
- LDR R1,=os_tsk @ os_tsk.run = os_tsk.new_tsk
- STR LR,[R1]
- LDRB R1,[LR,#TCB_TID] @ os_tsk.run->task_id
- LSL R1,#8 @ Store PROCID
- MCR p15,0,R1,c13,c0,1 @ Write CONTEXTIDR
-
- LDR R0,[LR,#TCB_TSTACK] @ os_tsk.run->tsk_stack
-
- @ Does incoming task have VFP/NEON state in stack?
- LDRB R3,[LR,#TCB_STACKF]
- ANDS R3, R3, #0x6
- MRC p15,0,R1,c1,c0,2 @ Read CPACR
- ANDEQ R1,R1,#0xFF0FFFFF @ Disable VFP/NEON access if incoming task does not have stacked VFP/NEON state
- ORRNE R1,R1,#0x00F00000 @ Enable VFP/NEON access if incoming task does have stacked VFP/NEON state
- MCR p15,0,R1,c1,c0,2 @ Write CPACR
- BEQ no_incoming_vfp
- ISB @ We only need the sync if we enabled, otherwise we will context switch before next VFP/NEON instruction anyway
- VLDMIA R0!,{D16-D31}
- VLDMIA R0!,{D0-D15}
- LDR R2,[R0]
- VMSR FPSCR,R2
- ADD R0,R0,#8
-
-no_incoming_vfp:
- LDR R1,[R0,#60] @ Restore User CPSR
- MSR SPSR_cxsf,R1
- LDMIA R0!,{R4-R11} @ Restore User R4-R11
- ADD R0,R0,#4 @ Restore User R1-R3,R12
- LDMIA R0!,{R1-R3,R12}
- LDMIA R0,{LR}^ @ Restore User LR
- ADD R0,R0,#4 @ No writeback for load to user LR
- LDMIA R0!,{LR} @ Restore User PC
- ADD R0,R0,#4 @ Correct User SP for unstacked user CPSR
-
- PUSH {R0} @ Push R0 onto stack
- LDMIA SP,{SP}^ @ Get R0 off stack into User SP
- ADD SP,SP,#4 @ Put SP back
-
- LDR R0,[R0,#-32] @ Restore R0
-
- PUSH {R0-R3,R12,LR}
-
- AND R12, SP, #4 @ Ensure stack is 8-byte aligned
- SUB SP, SP, R12 @ Adjust stack
- PUSH {R12, LR} @ Store stack adjustment and dummy LR to SVC stack
-
- CPSID i
- BLX rt_tsk_unlock
-
- POP {R12, LR} @ Get stack adjustment & discard dummy LR
- ADD SP, SP, R12 @ Unadjust stack
-
- POP {R0-R3,R12,LR}
-
- MOVS PC,LR @ Return from exception
-
-
- /*------------------- User SVC -------------------------------*/
-
-SVC_User:
- LDR R12,=SVC_Count
- LDR R12,[R12]
- CMP R4,R12 @ Check for overflow
- BHI SVC_Done
-
- LDR R12,=SVC_Table-4
- LDR R12,[R12,R4,LSL #2] @ Load SVC Function Address
- MRS R4,SPSR @ Save SPSR
- PUSH {R4} @ Push R4 so we can use it as a temp
- AND R4, SP, #4 @ Ensure stack is 8-byte aligned
- SUB SP, SP, R4 @ Adjust stack
- PUSH {R4, LR} @ Store stack adjustment and dummy LR
- BLX R12 @ Call SVC Function
- POP {R4, LR} @ Get stack adjustment & discard dummy LR
- ADD SP, SP, R4 @ Unadjust stack
- POP {R4} @ Restore R4
- MSR SPSR_cxsf,R4 @ Restore SPSR
-
-SVC_Done:
- PUSH {R0-R3,R12,LR}
-
- PUSH {R4} @ Push R4 so we can use it as a temp
- AND R4, SP, #4 @ Ensure stack is 8-byte aligned
- SUB SP, SP, R4 @ Adjust stack
- PUSH {R4, LR} @ Store stack adjustment and dummy LR
-
- CPSID i
- BLX rt_tsk_unlock
-
- POP {R4, LR} @ Get stack adjustment & discard dummy LR
- ADD SP, SP, R4 @ Unadjust stack
- POP {R4} @ Restore R4
-
- POP {R0-R3,R12,LR}
- POP {R4}
- RFEFD SP! @ Return from exception
-@ }
-@ #pragma pop
-
-@ #pragma push
-@ #pragma arm
-@ __asm void PendSV_Handler (U32 IRQn) {
-PendSV_Handler:
- .ARM
-
- .extern rt_tsk_lock
- .extern IRQNestLevel @ Flag indicates whether inside an ISR, and the depth of nesting. 0 = not in ISR.
- .extern seen_id0_active @ Flag used to workaround GIC 390 errata 733075 (set in startup_.s)
-
- ADD SP,SP,#8 @ fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment)
-
- @ Disable systick interrupts, then write EOIR. We want interrupts disabled before we enter the context switcher.
- PUSH {R0, R1}
- BLX rt_tsk_lock
- POP {R0, R1}
- LDR R1, =GICInterface_BASE
- LDR R1, [R1, #0]
- STR R0, [R1, #0x10] @ Write End Of Interrupt ID to GICC_EOIR
-
- @ If it was interrupt ID0, clear the seen flag, otherwise return as normal
- CMP R0, #0
- LDREQ R1, =seen_id0_active
- STREQB R0, [R1] @ Clear the seen flag, using R0 (which is 0), to save loading another register
-
- LDR R0, =IRQNestLevel @ Get address of nesting counter
- LDR R1, [R0]
- SUB R1, R1, #1 @ Decrement nesting counter
- STR R1, [R0]
-
- BLX rt_pop_req
-
- POP {R1, LR} @ Get stack adjustment & discard dummy LR
- ADD SP, SP, R1 @ Unadjust stack
-
- LDR R0,[SP,#24]
- MSR SPSR_cxsf,R0
- POP {R0-R3,R12} @ Leave SPSR & LR on the stack
- PUSH {R4}
- B Sys_Switch
-@ }
-@ #pragma pop
-
-
-@ #pragma push
-@ #pragma arm
-@ __asm void OS_Tick_Handler (U32 IRQn) {
-OS_Tick_Handler:
- .ARM
-
- .extern rt_tsk_lock
- .extern IRQNestLevel @ Flag indicates whether inside an ISR, and the depth of nesting. 0 = not in ISR.
- .extern seen_id0_active @ Flag used to workaround GIC 390 errata 733075 (set in startup_.s)
-
- ADD SP,SP,#8 @ fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment)
-
- @ Disable systick interrupts, then write EOIR. We want interrupts disabled before we enter the context switcher.
- PUSH {R0, R1}
- BLX rt_tsk_lock
- POP {R0, R1}
- LDR R1, =GICInterface_BASE
- LDR R1, [R1, #0]
- STR R0, [R1, #0x10] @ Write End Of Interrupt ID to GICC_EOIR
-
- @ If it was interrupt ID0, clear the seen flag, otherwise return as normal
- CMP R0, #0
- LDREQ R1, =seen_id0_active
- STREQB R0, [R1] @ Clear the seen flag, using R0 (which is 0), to save loading another register
-
- LDR R0, =IRQNestLevel @ Get address of nesting counter
- LDR R1, [R0]
- SUB R1, R1, #1 @ Decrement nesting counter
- STR R1, [R0]
-
- BLX os_tick_irqack
- BLX rt_systick
-
- POP {R1, LR} @ Get stack adjustment & discard dummy LR
- ADD SP, SP, R1 @ Unadjust stack
-
- LDR R0,[SP,#24]
- MSR SPSR_cxsf,R0
- POP {R0-R3,R12} @ Leave SPSR & LR on the stack
- PUSH {R4}
- B Sys_Switch
-@ }
-@ #pragma pop
-
-
- .END
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_GCC/SVC_Table.S b/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_GCC/SVC_Table.S
deleted file mode 100644
index d6962e16e0..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_GCC/SVC_Table.S
+++ /dev/null
@@ -1,57 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: SVC_TABLE.S
- * Purpose: Pre-defined SVC Table
- * Rev.: V4.70, with additions for Cortex-A
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH, 2014-2015 ARM Ltd
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-
- .section SVC_TABLE @, CODE, READONLY
-
- .global SVC_Count
-
-.EQU SVC_Cnt, (SVC_End-SVC_Table)/4
-SVC_Count: .word SVC_Cnt
-
-@ Import user SVC functions here.
-@ .extern __SVC_1
-
- .global SVC_Table
-SVC_Table:
-@ Insert user SVC functions here. SVC 0 used by RTX Kernel.
-@ .word __SVC_1 @ EnableCaches
-
-SVC_End:
-
- .END
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/HAL_CA9.c b/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/HAL_CA9.c
deleted file mode 100644
index b12326ab23..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/HAL_CA9.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*----------------------------------------------------------------------------
- * RL-ARM - RTX
- *----------------------------------------------------------------------------
- * Name: HAL_CA9.c
- * Purpose: Hardware Abstraction Layer for Cortex-A9
- * Rev.: 23 March 2015
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 2012 - 2015 ARM Limited
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-//unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075
-
-
-/*----------------------------------------------------------------------------
- * Functions
- *---------------------------------------------------------------------------*/
-
-/* Functions move to HAL_CA9_asm.S */
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/HAL_CA9_asm.s b/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/HAL_CA9_asm.s
deleted file mode 100644
index 74b6398fca..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/HAL_CA9_asm.s
+++ /dev/null
@@ -1,480 +0,0 @@
-/*----------------------------------------------------------------------------
- * RL-ARM - RTX
- *----------------------------------------------------------------------------
- * Name: HAL_CA9.c
- * Purpose: Hardware Abstraction Layer for Cortex-A9
- * Rev.: 8 April 2015
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 2012 - 2015 ARM Limited
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
- PUBLIC rt_set_PSP
- PUBLIC rt_get_PSP
- PUBLIC _alloc_box
- PUBLIC _free_box
- PUBLIC SWI_Handler
- PUBLIC PendSV_Handler
- PUBLIC OS_Tick_Handler
-
-/* macro defines form rt_HAL_CA.h */
-#define CPSR_T_BIT 0x20
-#define CPSR_I_BIT 0x80
-#define CPSR_F_BIT 0x40
-
-#define MODE_USR 0x10
-#define MODE_FIQ 0x11
-#define MODE_IRQ 0x12
-#define MODE_SVC 0x13
-#define MODE_ABT 0x17
-#define MODE_UND 0x1B
-#define MODE_SYS 0x1F
-
-/* macro defines form rt_TypeDef.h */
-#define TCB_TID 3 /* 'task id' offset */
-#define TCB_STACKF 37 /* 'stack_frame' offset */
-#ifndef __LARGE_PRIV_STACK
-#define TCB_TSTACK 40 /* 'tsk_stack' offset */
-#else
-#define TCB_TSTACK 44 /* 'tsk_stack' offset for LARGE_STACK */
-#endif
-
-
- IMPORT rt_alloc_box
- IMPORT rt_free_box
- IMPORT os_tsk
- IMPORT GICInterface_BASE
- IMPORT rt_pop_req
- IMPORT os_tick_irqack
- IMPORT rt_systick
-
- SECTION `.text`:CODE:ROOT(2)
-
-/*----------------------------------------------------------------------------
- * Functions
- *---------------------------------------------------------------------------*/
-
-//For A-class, set USR/SYS stack
-//__asm void rt_set_PSP (U32 stack) {
-rt_set_PSP:
- ARM
-
- MRS R1, CPSR
- CPS #MODE_SYS ;no effect in USR mode
- ISB
- MOV SP, R0
- MSR CPSR_c, R1 ;no effect in USR mode
- ISB
- BX LR
-
-//}
-
-//For A-class, get USR/SYS stack
-//__asm U32 rt_get_PSP (void) {
-rt_get_PSP:
- ARM
-
- MRS R1, CPSR
- CPS #MODE_SYS ;no effect in USR mode
- ISB
- MOV R0, SP
- MSR CPSR_c, R1 ;no effect in USR mode
- ISB
- BX LR
-//}
-
-/*--------------------------- _alloc_box ------------------------------------*/
-//__asm void *_alloc_box (void *box_mem) {
-_alloc_box:
- /* Function wrapper for Unprivileged/Privileged mode. */
- ARM
-
- LDR R12,=(rt_alloc_box)
- MRS R2, CPSR
- LSLS R2, R2,#28
- BXNE R12
- SVC 0
- BX LR
-//}
-
-
-/*--------------------------- _free_box -------------------------------------*/
-//__asm U32 _free_box (void *box_mem, void *box) {
-_free_box:
- /* Function wrapper for Unprivileged/Privileged mode. */
-
- LDR R12,=(rt_free_box)
- MRS R2, CPSR
- LSLS R2, R2,#28
- BXNE R12
- SVC 0
- BX LR
-
-//}
-
-/*-------------------------- SWI_Handler -----------------------------------*/
-
-//#pragma push
-//#pragma arm
-//__asm void SWI_Handler (void) {
-SWI_Handler:
- PRESERVE8
- ARM
-
- IMPORT rt_tsk_lock
- IMPORT rt_tsk_unlock
- IMPORT SVC_Count
- IMPORT SVC_Table
- IMPORT rt_stk_check
- IMPORT FPUEnable
- IMPORT scheduler_suspended ; flag set by rt_suspend, cleared by rt_resume, read by SWI_Handler
-
-Mode_SVC EQU 0x13
-
- SRSDB #Mode_SVC! ; Push LR_SVC and SPRS_SVC onto SVC mode stack
- STR R4,[SP,#-0x4]! ; Push R4 so we can use it as a temp
-
- MRS R4,SPSR ; Get SPSR
- TST R4,#CPSR_T_BIT ; Check Thumb Bit
- LDRNEH R4,[LR,#-2] ; Thumb: Load Halfword
- BICNE R4,R4,#0xFF00 ; Extract SVC Number
- LDREQ R4,[LR,#-4] ; ARM: Load Word
- BICEQ R4,R4,#0xFF000000 ; Extract SVC Number
-
- /* Lock out systick and re-enable interrupts */
- STMDB SP!,{R0-R3,R12,LR}
-
- AND R12, SP, #4 ; Ensure stack is 8-byte aligned
- SUB SP, SP, R12 ; Adjust stack
- STMDB SP!,{R12, LR} ; Store stack adjustment and dummy LR to SVC stack
-
- BLX rt_tsk_lock
- CPSIE i
-
- LDMIA SP!,{R12,LR} ; Get stack adjustment & discard dummy LR
- ADD SP, SP, R12 ; Unadjust stack
-
- LDMIA SP!,{R0-R3,R12,LR}
-
- CMP R4,#0
- BNE SVC_User
-
- MRS R4,SPSR
- STR R4,[SP,#-0x4]! ; Push R4 so we can use it as a temp
- AND R4, SP, #4 ; Ensure stack is 8-byte aligned
- SUB SP, SP, R4 ; Adjust stack
- STMDB SP!,{R4, LR} ; Store stack adjustment and dummy LR
- BLX R12
- LDMIA SP!,{R4, LR} ; Get stack adjustment & discard dummy LR
- ADD SP, SP, R4 ; Unadjust stack
- LDR R4,[SP],#0x4 ; Restore R4
- MSR SPSR_CXSF,R4
-
- /* Here we will be in SVC mode (even if coming in from PendSV_Handler or OS_Tick_Handler) */
-Sys_Switch:
- LDR LR,=(os_tsk)
- LDMIA LR,{R4,LR} ; os_tsk.run, os_tsk.new
- CMP R4,LR
- BNE switching
-
- STMDB SP!,{R0-R3,R12,LR}
-
- AND R12, SP, #4 ; Ensure stack is 8-byte aligned
- SUB SP, SP, R12 ; Adjust stack
- STMDB SP!,{R12,LR} ; Store stack adjustment and dummy LR to SVC stack
-
- CPSID i
- ; Do not unlock scheduler if it has just been suspended by rt_suspend()
- LDR R1,=scheduler_suspended
- LDRB R0, [R1]
- CMP R0, #1
- BEQ dont_unlock
- BLX rt_tsk_unlock
-dont_unlock:
-
- LDMIA SP!,{R12,LR} ; Get stack adjustment & discard dummy LR
- ADD SP, SP, R12 ; Unadjust stack
-
- LDMIA SP!,{R0-R3,R12,LR}
- LDR R4,[SP],#0x4
- RFEFD SP! ; Return from exception, no task switch
-
-switching:
- CLREX
- CMP R4,#0
- ADDEQ SP,SP,#12 ; Original R4, LR & SPSR do not need to be popped when we are paging in a different task
- BEQ SVC_Next ; Runtask deleted?
-
-
- STMDB SP!,{R8-R11} //R4 and LR already stacked
- MOV R10,R4 ; Preserve os_tsk.run
- MOV R11,LR ; Preserve os_tsk.new
-
- ADD R8,SP,#16 ; Unstack R4,LR
- LDMIA R8,{R4,LR}
-
- SUB SP,SP,#4 ; Make space on the stack for the next instn
- STMIA SP,{SP}^ ; Put User SP onto stack
- LDR R8,[SP],#0x4 ; Pop User SP into R8
-
- MRS R9,SPSR
- STMDB R8!,{R9} ; User CPSR
- STMDB R8!,{LR} ; User PC
- STMDB R8,{LR}^ ; User LR
- SUB R8,R8,#4 ; No writeback for store of User LR
- STMDB R8!,{R0-R3,R12} ; User R0-R3,R12
- MOV R3,R10 ; os_tsk.run
- MOV LR,R11 ; os_tsk.new
- LDMIA SP!,{R9-R12}
- ADD SP,SP,#12 ; Fix up SP for unstack of R4, LR & SPSR
- STMDB R8!,{R4-R7,R9-R12} ; User R4-R11
-
- //If applicable, stack VFP/NEON state
- MRC p15,0,R1,c1,c0,2 ; VFP/NEON access enabled? (CPACR)
- AND R2,R1,#0x00F00000
- CMP R2,#0x00F00000
- BNE no_outgoing_vfp
- VMRS R2,FPSCR
- STMDB R8!,{R2,R4} ; Push FPSCR, maintain 8-byte alignment
- //IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
- VSTMDB R8!,{D0-D15}
- VSTMDB R8!,{D16-D31}
- LDRB R2,[R3,#TCB_STACKF] ; Record in TCB that NEON/D32 state is stacked
- ORR R2,R2,#4
- STRB R2,[R3,#TCB_STACKF]
- //ENDIF
-
-no_outgoing_vfp:
- STR R8,[R3,#TCB_TSTACK]
- MOV R4,LR
-
- STR R4,[SP,#-0x4]! ; Push R4 so we can use it as a temp
- AND R4, SP, #4 ; Ensure stack is 8-byte aligned
- SUB SP, SP, R4 ; Adjust stack
- STMDB SP!,{R4, LR} ; Store stack adjustment and dummy LR to SVC stack
-
- BLX rt_stk_check
-
- LDMIA SP!,{R4, LR} ; Get stack adjustment & discard dummy LR
- ADD SP, SP, R4 ; Unadjust stack
- LDR R4,[SP],#0x4 ; Restore R4
-
- MOV LR,R4
-
-SVC_Next: //R4 == os_tsk.run, LR == os_tsk.new, R0-R3, R5-R12 corruptible
- LDR R1,=(os_tsk) ; os_tsk.run = os_tsk.new
- STR LR,[R1]
- LDRB R1,[LR,#TCB_TID] ; os_tsk.run->task_id
- LSL R1,R1,#8 ; Store PROCID
- MCR p15,0,R1,c13,c0,1 ; Write CONTEXTIDR
-
- LDR R0,[LR,#TCB_TSTACK] ; os_tsk.run->tsk_stack
-
- //Does incoming task have VFP/NEON state in stack?
- LDRB R3,[LR,#TCB_STACKF]
- ANDS R3, R3, #0x6
- MRC p15,0,R1,c1,c0,2 ; Read CPACR
- BICEQ R1,R1,#0x00F00000 ; Disable VFP/NEON access if incoming task does not have stacked VFP/NEON state
- ORRNE R1,R1,#0x00F00000 ; Enable VFP/NEON access if incoming task does have stacked VFP/NEON state
- MCR p15,0,R1,c1,c0,2 ; Write CPACR
- BEQ no_incoming_vfp
- ISB ; We only need the sync if we enabled, otherwise we will context switch before next VFP/NEON instruction anyway
- //IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
- VLDMIA R0!,{D16-D31}
- //ENDIF
- VLDMIA R0!,{D0-D15}
- LDR R2,[R0]
- VMSR FPSCR,R2
- ADD R0,R0,#8
-
-no_incoming_vfp:
- LDR R1,[R0,#60] ; Restore User CPSR
- MSR SPSR_CXSF,R1
- LDMIA R0!,{R4-R11} ; Restore User R4-R11
- ADD R0,R0,#4 ; Restore User R1-R3,R12
- LDMIA R0!,{R1-R3,R12}
- LDMIA R0,{LR}^ ; Restore User LR
- ADD R0,R0,#4 ; No writeback for load to user LR
- LDMIA R0!,{LR} ; Restore User PC
- ADD R0,R0,#4 ; Correct User SP for unstacked user CPSR
-
- STR R0,[SP,#-0x4]! ; Push R0 onto stack
- LDMIA SP,{SP}^ ; Get R0 off stack into User SP
- ADD SP,SP,#4 ; Put SP back
-
- LDR R0,[R0,#-32] ; Restore R0
-
- STMDB SP!,{R0-R3,R12,LR}
-
- AND R12, SP, #4 ; Ensure stack is 8-byte aligned
- SUB SP, SP, R12 ; Adjust stack
- STMDB sp!,{R12, LR} ; Store stack adjustment and dummy LR to SVC stack
-
- CPSID i
- BLX rt_tsk_unlock
-
- LDMIA sp!,{R12, LR} ; Get stack adjustment & discard dummy LR
- ADD SP, SP, R12 ; Unadjust stack
-
- LDMIA SP!,{R0-R3,R12,LR}
-
- MOVS PC,LR ; Return from exception
-
-
- /*------------------- User SVC -------------------------------*/
-
-SVC_User:
- LDR R12,=SVC_Count
- LDR R12,[R12]
- CMP R4,R12 ; Check for overflow
- BHI SVC_Done
-
- LDR R12,=SVC_Table-4
- LDR R12,[R12,R4,LSL #2] ; Load SVC Function Address
- MRS R4,SPSR ; Save SPSR
- STR R4,[SP,#-0x4]! ; Push R4 so we can use it as a temp
- AND R4, SP, #4 ; Ensure stack is 8-byte aligned
- SUB SP, SP, R4 ; Adjust stack
- STMDB SP!,{R4, LR} ; Store stack adjustment and dummy LR
- BLX R12 ; Call SVC Function
- LDMIA SP!,{R4, LR} ; Get stack adjustment & discard dummy LR
- ADD SP, SP, R4 ; Unadjust stack
- LDR R4,[SP],#0x4 ; Restore R4
- MSR SPSR_CXSF,R4 ; Restore SPSR
-
-SVC_Done:
- STMDB sp!,{R0-R3,R12,LR}
-
- STR R4,[sp,#-0x4]! ; Push R4 so we can use it as a temp
- AND R4, SP, #4 ; Ensure stack is 8-byte aligned
- SUB SP, SP, R4 ; Adjust stack
- STMDB SP!,{R4, LR} ; Store stack adjustment and dummy LR
-
- CPSID i
- BLX rt_tsk_unlock
-
- LDMIA SP!,{R4, LR} ; Get stack adjustment & discard dummy LR
- ADD SP, SP, R4 ; Unadjust stack
- LDR R4,[SP],#0x4 ; Restore R4
-
- LDMIA SP!,{R0-R3,R12,LR}
- LDR R4,[SP],#0x4
- RFEFD SP! ; Return from exception
-//}
-//#pragma pop
-
-//#pragma push
-//#pragma arm
-//__asm void PendSV_Handler (U32 IRQn) {
-PendSV_Handler:
- ARM
-
- IMPORT rt_tsk_lock
- IMPORT IRQNestLevel ; Flag indicates whether inside an ISR, and the depth of nesting. 0 = not in ISR.
- IMPORT seen_id0_active ; Flag used to workaround GIC 390 errata 733075 - set in startup_Renesas_RZ_A1.s
-
- ADD SP,SP,#8 //fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment)
-
- //Disable systick interrupts, then write EOIR. We want interrupts disabled before we enter the context switcher.
- STMDB SP!,{R0, R1}
- BLX rt_tsk_lock
- LDMIA SP!,{R0, R1}
- LDR R1,=(GICInterface_BASE)
- LDR R1, [R1, #0]
- STR R0, [R1, #0x10]
-
- ; If it was interrupt ID0, clear the seen flag, otherwise return as normal
- CMP R0, #0
- LDREQ R1, =seen_id0_active
- STRBEQ R0, [R1] ; Clear the seen flag, using R0 (which is 0), to save loading another register
-
- LDR R0, =IRQNestLevel ; Get address of nesting counter
- LDR R1, [R0]
- SUB R1, R1, #1 ; Decrement nesting counter
- STR R1, [R0]
-
- BLX (rt_pop_req)
-
- LDMIA SP!,{R1, LR} ; Get stack adjustment & discard dummy LR
- ADD SP, SP, R1 ; Unadjust stack
-
- LDR R0,[SP,#24]
- MSR SPSR_CXSF,R0
- LDMIA SP!,{R0-R3,R12} ; Leave SPSR & LR on the stack
- STR R4,[SP,#-0x4]!
- B Sys_Switch
-//}
-//#pragma pop
-
-
-//#pragma push
-//#pragma arm
-//__asm void OS_Tick_Handler (U32 IRQn) {
-OS_Tick_Handler:
- ARM
-
- IMPORT rt_tsk_lock
- IMPORT IRQNestLevel ; Flag indicates whether inside an ISR, and the depth of nesting. 0 = not in ISR.
- IMPORT seen_id0_active ; Flag used to workaround GIC 390 errata 733075 - set in startup_Renesas_RZ_A1.s
-
- ADD SP,SP,#8 //fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment)
-
- STMDB SP!,{R0, R1}
- BLX rt_tsk_lock
- LDMIA SP!,{R0, R1}
- LDR R1, =(GICInterface_BASE)
- LDR R1, [R1, #0]
- STR R0, [R1, #0x10]
-
- ; If it was interrupt ID0, clear the seen flag, otherwise return as normal
- CMP R0, #0
- LDREQ R1, =seen_id0_active
- STRBEQ R0, [R1] ; Clear the seen flag, using R0 (which is 0), to save loading another register
-
- LDR R0, =IRQNestLevel ; Get address of nesting counter
- LDR R1, [R0]
- SUB R1, R1, #1 ; Decrement nesting counter
- STR R1, [R0]
-
- BLX (os_tick_irqack)
- BLX (rt_systick)
-
- LDMIA SP!,{R1, LR} ; Get stack adjustment & discard dummy LR
- ADD SP, SP, R1 ; Unadjust stack
-
- LDR R0,[SP,#24]
- MSR SPSR_CXSF,R0
- LDMIA SP!,{R0-R3,R12} ; Leave SPSR & LR on the stack
- STR R4,[SP,#-0x4]!
- B Sys_Switch
-//}
-//#pragma pop
-
-
- END
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/SVC_Table.S b/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/SVC_Table.S
deleted file mode 100644
index b7f2cc8bdb..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/SVC_Table.S
+++ /dev/null
@@ -1,57 +0,0 @@
-;/*----------------------------------------------------------------------------
-; * RL-ARM - RTX
-; *----------------------------------------------------------------------------
-; * Name: SVC_TABLE.S
-; * Purpose: Pre-defined SVC Table for Cortex-M
-; * Rev.: V4.70
-; *----------------------------------------------------------------------------
-; *
-; * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
-; * All rights reserved.
-; * Redistribution and use in source and binary forms, with or without
-; * modification, are permitted provided that the following conditions are met:
-; * - Redistributions of source code must retain the above copyright
-; * notice, this list of conditions and the following disclaimer.
-; * - Redistributions in binary form must reproduce the above copyright
-; * notice, this list of conditions and the following disclaimer in the
-; * documentation and/or other materials provided with the distribution.
-; * - Neither the name of ARM nor the names of its contributors may be used
-; * to endorse or promote products derived from this software without
-; * specific prior written permission.
-; *
-; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-; * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-; * POSSIBILITY OF SUCH DAMAGE.
-; *---------------------------------------------------------------------------*/
-
-
- SECTION SVC_TABLE:CODE:ROOT(2)
-
- EXPORT SVC_Count
-
-SVC_Cnt EQU (SVC_End-SVC_Table)/4
-SVC_Count DCD SVC_Cnt
-
-; Import user SVC functions here.
-; IMPORT __SVC_1
-
- EXPORT SVC_Table
-SVC_Table
-; Insert user SVC functions here. SVC 0 used by RTL Kernel.
-; DCD __SVC_1 ; InitMemorySubsystem
-
-SVC_End
-
- END
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/cmsis_os.h b/rtos/rtx/TARGET_CORTEX_A/cmsis_os.h
deleted file mode 100644
index f4a4bb3b25..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/cmsis_os.h
+++ /dev/null
@@ -1,716 +0,0 @@
-/* ----------------------------------------------------------------------
- * $Date: 5. February 2013
- * $Revision: V1.02
- *
- * Project: CMSIS-RTOS API
- * Title: cmsis_os.h RTX header file
- *
- * Version 0.02
- * Initial Proposal Phase
- * Version 0.03
- * osKernelStart added, optional feature: main started as thread
- * osSemaphores have standard behavior
- * osTimerCreate does not start the timer, added osTimerStart
- * osThreadPass is renamed to osThreadYield
- * Version 1.01
- * Support for C++ interface
- * - const attribute removed from the osXxxxDef_t typedef's
- * - const attribute added to the osXxxxDef macros
- * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
- * Added: osKernelInitialize
- * Version 1.02
- * Control functions for short timeouts in microsecond resolution:
- * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
- * Removed: osSignalGet
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 2013 ARM LIMITED
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-
-#ifndef _CMSIS_OS_H
-#define _CMSIS_OS_H
-
-#define osCMSIS 0x10002U ///< CMSIS-RTOS API version (main [31:16] .sub [15:0])
-
-#define osCMSIS_RTX ((4<<16)|80) ///< RTOS identification and version (main [31:16] .sub [15:0])
-
-#define osKernelSystemId "RTX V4.80" ///< RTOS identification string
-
-#define CMSIS_OS_RTX
-#define CMSIS_OS_RTX_CA /* new define for Coretex-A */
-
-// The stack space occupied is mainly dependent on the underling C standard library
-#if defined(TOOLCHAIN_GCC) || defined(TOOLCHAIN_ARM_STD) || defined(TOOLCHAIN_IAR)
-# define WORDS_STACK_SIZE 512
-#elif defined(TOOLCHAIN_ARM_MICRO)
-# define WORDS_STACK_SIZE 128
-#endif
-
-#define DEFAULT_STACK_SIZE (WORDS_STACK_SIZE*4)
-
-#define osFeature_MainThread 1 ///< main can be thread
-#define osFeature_Pool 1 ///< Memory Pools available
-#define osFeature_MailQ 1 ///< Mail Queues available
-#define osFeature_MessageQ 1 ///< Message Queues available
-#define osFeature_Signals 16 ///< 16 Signal Flags available per thread
-#define osFeature_Semaphore 65535 ///< Maximum count for \ref osSemaphoreCreate function
-#define osFeature_Wait 0 ///< osWait not available
-#define osFeature_SysTick 1 ///< osKernelSysTick functions available
-#define osFeature_ThreadEnum 1 ///< Thread enumeration available
-
-#if defined (__CC_ARM)
-#define os_InRegs __value_in_regs // Compiler specific: force struct in registers
-#else
-#define os_InRegs
-#endif
-
-#include
-#include
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-// ==== Enumeration, structures, defines ====
-
-/// Priority used for thread control.
-typedef enum {
- osPriorityIdle = -3, ///< priority: idle (lowest)
- osPriorityLow = -2, ///< priority: low
- osPriorityBelowNormal = -1, ///< priority: below normal
- osPriorityNormal = 0, ///< priority: normal (default)
- osPriorityAboveNormal = +1, ///< priority: above normal
- osPriorityHigh = +2, ///< priority: high
- osPriorityRealtime = +3, ///< priority: realtime (highest)
- osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority
-} osPriority;
-
-/// Timeout value.
-#define osWaitForever 0xFFFFFFFFU ///< wait forever timeout value
-
-/// Status code values returned by CMSIS-RTOS functions.
-typedef enum {
- osOK = 0, ///< function completed; no error or event occurred.
- osEventSignal = 0x08, ///< function completed; signal event occurred.
- osEventMessage = 0x10, ///< function completed; message event occurred.
- osEventMail = 0x20, ///< function completed; mail event occurred.
- osEventTimeout = 0x40, ///< function completed; timeout occurred.
- osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object.
- osErrorResource = 0x81, ///< resource not available: a specified resource was not available.
- osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period.
- osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines.
- osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object.
- osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority.
- osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.
- osErrorValue = 0x86, ///< value of a parameter is out of range.
- osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits.
- os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization.
-} osStatus;
-
-
-/// Timer type value for the timer definition.
-typedef enum {
- osTimerOnce = 0, ///< one-shot timer
- osTimerPeriodic = 1 ///< repeating timer
-} os_timer_type;
-
-typedef enum {
- osThreadInfoState,
- osThreadInfoStackSize,
- osThreadInfoStackMax,
- osThreadInfoEntry,
- osThreadInfoArg,
-
- osThreadInfo_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization.
-} osThreadInfo;
-
-/// Entry point of a thread.
-typedef void (*os_pthread) (void const *argument);
-
-/// Entry point of a timer call back function.
-typedef void (*os_ptimer) (void const *argument);
-
-// >>> the following data type definitions may shall adapted towards a specific RTOS
-
-/// Thread ID identifies the thread (pointer to a thread control block).
-typedef struct os_thread_cb *osThreadId;
-
-/// Timer ID identifies the timer (pointer to a timer control block).
-typedef struct os_timer_cb *osTimerId;
-
-/// Mutex ID identifies the mutex (pointer to a mutex control block).
-typedef struct os_mutex_cb *osMutexId;
-
-/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).
-typedef struct os_semaphore_cb *osSemaphoreId;
-
-/// Pool ID identifies the memory pool (pointer to a memory pool control block).
-typedef struct os_pool_cb *osPoolId;
-
-/// Message ID identifies the message queue (pointer to a message queue control block).
-typedef struct os_messageQ_cb *osMessageQId;
-
-/// Mail ID identifies the mail queue (pointer to a mail queue control block).
-typedef struct os_mailQ_cb *osMailQId;
-
-/// Thread enumeration ID identifies the enumeration (pointer to a thread enumeration control block).
-typedef uint32_t *osThreadEnumId;
-
-/// Thread Definition structure contains startup information of a thread.
-typedef struct os_thread_def {
- os_pthread pthread; ///< start address of thread function
- osPriority tpriority; ///< initial thread priority
- uint32_t instances; ///< maximum number of instances of that thread function
- uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size
-#ifdef __MBED_CMSIS_RTOS_CA9
- uint32_t *stack_pointer; ///< pointer to the stack memory block
-#endif
-} osThreadDef_t;
-
-/// Timer Definition structure contains timer parameters.
-typedef struct os_timer_def {
- os_ptimer ptimer; ///< start address of a timer function
- void *timer; ///< pointer to internal data
-} osTimerDef_t;
-
-/// Mutex Definition structure contains setup information for a mutex.
-typedef struct os_mutex_def {
- void *mutex; ///< pointer to internal data
-} osMutexDef_t;
-
-/// Semaphore Definition structure contains setup information for a semaphore.
-typedef struct os_semaphore_def {
- void *semaphore; ///< pointer to internal data
-} osSemaphoreDef_t;
-
-/// Definition structure for memory block allocation.
-typedef struct os_pool_def {
- uint32_t pool_sz; ///< number of items (elements) in the pool
- uint32_t item_sz; ///< size of an item
- void *pool; ///< pointer to memory for pool
-} osPoolDef_t;
-
-/// Definition structure for message queue.
-typedef struct os_messageQ_def {
- uint32_t queue_sz; ///< number of elements in the queue
- void *pool; ///< memory array for messages
-} osMessageQDef_t;
-
-/// Definition structure for mail queue.
-typedef struct os_mailQ_def {
- uint32_t queue_sz; ///< number of elements in the queue
- uint32_t item_sz; ///< size of an item
- void *pool; ///< memory array for mail
-} osMailQDef_t;
-
-/// Event structure contains detailed information about an event.
-typedef struct {
- osStatus status; ///< status code: event or error information
- union {
- uint32_t v; ///< message as 32-bit value
- void *p; ///< message or mail as void pointer
- int32_t signals; ///< signal flags
- } value; ///< event value
- union {
- osMailQId mail_id; ///< mail id obtained by \ref osMailCreate
- osMessageQId message_id; ///< message id obtained by \ref osMessageCreate
- } def; ///< event definition
-} osEvent;
-
-
-// ==== Kernel Control Functions ====
-
-/// Initialize the RTOS Kernel for creating objects.
-/// \return status code that indicates the execution status of the function.
-osStatus osKernelInitialize (void);
-
-/// Start the RTOS Kernel.
-/// \return status code that indicates the execution status of the function.
-osStatus osKernelStart (void);
-
-/// Check if the RTOS kernel is already started.
-/// \return 0 RTOS is not started, 1 RTOS is started.
-int32_t osKernelRunning(void);
-
-#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available
-
-/// \cond INTERNAL_VARIABLES
-extern uint32_t const os_tickfreq;
-extern uint16_t const os_tickus_i;
-extern uint16_t const os_tickus_f;
-/// \endcond
-
-/// Get the RTOS kernel system timer counter.
-/// \return RTOS kernel system timer as 32-bit value
-uint32_t osKernelSysTick (void);
-
-/// The RTOS kernel system timer frequency in Hz.
-/// \note Reflects the system timer setting and is typically defined in a configuration file.
-#define osKernelSysTickFrequency os_tickfreq
-
-/// Convert a microseconds value to a RTOS kernel system timer value.
-/// \param microsec time value in microseconds.
-/// \return time value normalized to the \ref osKernelSysTickFrequency
-/*
-#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
-*/
-#define osKernelSysTickMicroSec(microsec) ((microsec * os_tickus_i) + ((microsec * os_tickus_f) >> 16))
-
-#endif // System Timer available
-
-// ==== Thread Management ====
-
-/// Create a Thread Definition with function, priority, and stack requirements.
-/// \param name name of the thread function.
-/// \param priority initial priority of the thread function.
-/// \param instances number of possible thread instances.
-/// \param stacksz stack size (in bytes) requirements for the thread function.
-/// macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal) // object is external
-#define osThreadDef(name, priority, instances, stacksz) \
-extern const osThreadDef_t os_thread_def_##name
-#else // define the object
-#ifdef __MBED_CMSIS_RTOS_CA9
-#define osThreadDef(name, priority, stacksz) \
-uint32_t os_thread_def_stack_##name [stacksz / sizeof(uint32_t)]; \
-const osThreadDef_t os_thread_def_##name = \
-{ (name), (priority), 1, (stacksz), (os_thread_def_stack_##name) }
-#else
-#define osThreadDef(name, priority, instances, stacksz) \
-const osThreadDef_t os_thread_def_##name = \
-{ (name), (priority), (instances), (stacksz) }
-#endif
-#endif
-
-/// Access a Thread definition.
-/// \param name name of the thread definition object.
-/// macro body is implementation specific in every CMSIS-RTOS.
-#define osThread(name) \
-&os_thread_def_##name
-
-/// Create a thread and add it to Active Threads and set it to state READY.
-/// \param[in] thread_def thread definition referenced with \ref osThread.
-/// \param[in] argument pointer that is passed to the thread function as start argument.
-/// \return thread ID for reference by other functions or NULL in case of error.
-osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
-
-/// Return the thread ID of the current running thread.
-/// \return thread ID for reference by other functions or NULL in case of error.
-osThreadId osThreadGetId (void);
-
-/// Terminate execution of a thread and remove it from Active Threads.
-/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \return status code that indicates the execution status of the function.
-osStatus osThreadTerminate (osThreadId thread_id);
-
-/// Pass control to next thread that is in state \b READY.
-/// \return status code that indicates the execution status of the function.
-osStatus osThreadYield (void);
-
-/// Change priority of an active thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \param[in] priority new priority value for the thread function.
-/// \return status code that indicates the execution status of the function.
-osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
-
-/// Get current priority of an active thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \return current priority value of the thread function.
-osPriority osThreadGetPriority (osThreadId thread_id);
-
-#ifdef __MBED_CMSIS_RTOS_CA9
-/// Get current thread state.
-uint8_t osThreadGetState (osThreadId thread_id);
-#endif
-
-/// Get into from an active thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \param[in] info information to read.
-/// \return current state of the thread function.
-/// \return requested info that includes the status code.
-os_InRegs osEvent _osThreadGetInfo(osThreadId thread_id, osThreadInfo info);
-
-// ==== Generic Wait Functions ====
-
-/// Wait for Timeout (Time Delay).
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "Time delay" value
-/// \return status code that indicates the execution status of the function.
-osStatus osDelay (uint32_t millisec);
-
-#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available
-
-/// Wait for Signal, Message, Mail, or Timeout.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
-/// \return event that contains signal, message, or mail information or error code.
-os_InRegs osEvent osWait (uint32_t millisec);
-
-#endif // Generic Wait available
-
-
-// ==== Timer Management Functions ====
-/// Define a Timer object.
-/// \param name name of the timer object.
-/// \param function name of the timer call back function.
-#if defined (osObjectsExternal) // object is external
-#define osTimerDef(name, function) \
-extern const osTimerDef_t os_timer_def_##name
-#else // define the object
-#define osTimerDef(name, function) \
-uint32_t os_timer_cb_##name[6]; \
-const osTimerDef_t os_timer_def_##name = \
-{ (function), (os_timer_cb_##name) }
-#endif
-
-/// Access a Timer definition.
-/// \param name name of the timer object.
-#define osTimer(name) \
-&os_timer_def_##name
-
-/// Create a timer.
-/// \param[in] timer_def timer object referenced with \ref osTimer.
-/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
-/// \param[in] argument argument to the timer call back function.
-/// \return timer ID for reference by other functions or NULL in case of error.
-osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
-
-/// Start or restart a timer.
-/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "Time delay" value of the timer.
-/// \return status code that indicates the execution status of the function.
-osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
-
-/// Stop the timer.
-/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
-/// \return status code that indicates the execution status of the function.
-osStatus osTimerStop (osTimerId timer_id);
-
-/// Delete a timer that was created by \ref osTimerCreate.
-/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
-/// \return status code that indicates the execution status of the function.
-osStatus osTimerDelete (osTimerId timer_id);
-
-
-// ==== Signal Management ====
-
-/// Set the specified Signal Flags of an active thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \param[in] signals specifies the signal flags of the thread that should be set.
-/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
-int32_t osSignalSet (osThreadId thread_id, int32_t signals);
-
-/// Clear the specified Signal Flags of an active thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \param[in] signals specifies the signal flags of the thread that shall be cleared.
-/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.
-int32_t osSignalClear (osThreadId thread_id, int32_t signals);
-
-/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
-/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return event flag information or error code.
-os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec);
-
-
-// ==== Mutex Management ====
-
-/// Define a Mutex.
-/// \param name name of the mutex object.
-#if defined (osObjectsExternal) // object is external
-#define osMutexDef(name) \
-extern const osMutexDef_t os_mutex_def_##name
-#else // define the object
-#define osMutexDef(name) \
-uint32_t os_mutex_cb_##name[4] = { 0 }; \
-const osMutexDef_t os_mutex_def_##name = { (os_mutex_cb_##name) }
-#endif
-
-/// Access a Mutex definition.
-/// \param name name of the mutex object.
-#define osMutex(name) \
-&os_mutex_def_##name
-
-/// Create and Initialize a Mutex object.
-/// \param[in] mutex_def mutex definition referenced with \ref osMutex.
-/// \return mutex ID for reference by other functions or NULL in case of error.
-osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
-
-/// Wait until a Mutex becomes available.
-/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return status code that indicates the execution status of the function.
-osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
-
-/// Release a Mutex that was obtained by \ref osMutexWait.
-/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
-/// \return status code that indicates the execution status of the function.
-osStatus osMutexRelease (osMutexId mutex_id);
-
-/// Delete a Mutex that was created by \ref osMutexCreate.
-/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
-/// \return status code that indicates the execution status of the function.
-osStatus osMutexDelete (osMutexId mutex_id);
-
-
-// ==== Semaphore Management Functions ====
-
-#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available
-
-/// Define a Semaphore object.
-/// \param name name of the semaphore object.
-#if defined (osObjectsExternal) // object is external
-#define osSemaphoreDef(name) \
-extern const osSemaphoreDef_t os_semaphore_def_##name
-#else // define the object
-#define osSemaphoreDef(name) \
-uint32_t os_semaphore_cb_##name[2] = { 0 }; \
-const osSemaphoreDef_t os_semaphore_def_##name = { (os_semaphore_cb_##name) }
-#endif
-
-/// Access a Semaphore definition.
-/// \param name name of the semaphore object.
-#define osSemaphore(name) \
-&os_semaphore_def_##name
-
-/// Create and Initialize a Semaphore object used for managing resources.
-/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore.
-/// \param[in] count number of available resources.
-/// \return semaphore ID for reference by other functions or NULL in case of error.
-osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
-
-/// Wait until a Semaphore token becomes available.
-/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return number of available tokens, or -1 in case of incorrect parameters.
-int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
-
-/// Release a Semaphore token.
-/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
-/// \return status code that indicates the execution status of the function.
-osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
-
-/// Delete a Semaphore that was created by \ref osSemaphoreCreate.
-/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
-/// \return status code that indicates the execution status of the function.
-osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
-
-#endif // Semaphore available
-
-
-// ==== Memory Pool Management Functions ====
-
-#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available
-
-/// \brief Define a Memory Pool.
-/// \param name name of the memory pool.
-/// \param no maximum number of blocks (objects) in the memory pool.
-/// \param type data type of a single block (object).
-#if defined (osObjectsExternal) // object is external
-#define osPoolDef(name, no, type) \
-extern const osPoolDef_t os_pool_def_##name
-#else // define the object
-#define osPoolDef(name, no, type) \
-uint32_t os_pool_m_##name[3+((sizeof(type)+3)/4)*(no)]; \
-const osPoolDef_t os_pool_def_##name = \
-{ (no), sizeof(type), (os_pool_m_##name) }
-#endif
-
-/// \brief Access a Memory Pool definition.
-/// \param name name of the memory pool
-#define osPool(name) \
-&os_pool_def_##name
-
-/// Create and Initialize a memory pool.
-/// \param[in] pool_def memory pool definition referenced with \ref osPool.
-/// \return memory pool ID for reference by other functions or NULL in case of error.
-osPoolId osPoolCreate (const osPoolDef_t *pool_def);
-
-/// Allocate a memory block from a memory pool.
-/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
-/// \return address of the allocated memory block or NULL in case of no memory available.
-void *osPoolAlloc (osPoolId pool_id);
-
-/// Allocate a memory block from a memory pool and set memory block to zero.
-/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
-/// \return address of the allocated memory block or NULL in case of no memory available.
-void *osPoolCAlloc (osPoolId pool_id);
-
-/// Return an allocated memory block back to a specific memory pool.
-/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
-/// \param[in] block address of the allocated memory block that is returned to the memory pool.
-/// \return status code that indicates the execution status of the function.
-osStatus osPoolFree (osPoolId pool_id, void *block);
-
-#endif // Memory Pool Management available
-
-
-// ==== Message Queue Management Functions ====
-
-#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available
-
-/// \brief Create a Message Queue Definition.
-/// \param name name of the queue.
-/// \param queue_sz maximum number of messages in the queue.
-/// \param type data type of a single message element (for debugger).
-#if defined (osObjectsExternal) // object is external
-#define osMessageQDef(name, queue_sz, type) \
-extern const osMessageQDef_t os_messageQ_def_##name
-#else // define the object
-#define osMessageQDef(name, queue_sz, type) \
-uint32_t os_messageQ_q_##name[4+(queue_sz)] = { 0 }; \
-const osMessageQDef_t os_messageQ_def_##name = \
-{ (queue_sz), (os_messageQ_q_##name) }
-#endif
-
-/// \brief Access a Message Queue Definition.
-/// \param name name of the queue
-#define osMessageQ(name) \
-&os_messageQ_def_##name
-
-/// Create and Initialize a Message Queue.
-/// \param[in] queue_def queue definition referenced with \ref osMessageQ.
-/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
-/// \return message queue ID for reference by other functions or NULL in case of error.
-osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
-
-/// Put a Message to a Queue.
-/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
-/// \param[in] info message information.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return status code that indicates the execution status of the function.
-osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
-
-/// Get a Message or Wait for a Message from a Queue.
-/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return event information that includes status code.
-os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
-
-#endif // Message Queues available
-
-
-// ==== Mail Queue Management Functions ====
-
-#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available
-
-/// \brief Create a Mail Queue Definition.
-/// \param name name of the queue
-/// \param queue_sz maximum number of messages in queue
-/// \param type data type of a single message element
-#if defined (osObjectsExternal) // object is external
-#define osMailQDef(name, queue_sz, type) \
-extern const osMailQDef_t os_mailQ_def_##name
-#else // define the object
-#define osMailQDef(name, queue_sz, type) \
-uint32_t os_mailQ_q_##name[4+(queue_sz)] = { 0 }; \
-uint32_t os_mailQ_m_##name[3+((sizeof(type)+3)/4)*(queue_sz)]; \
-void * os_mailQ_p_##name[2] = { (os_mailQ_q_##name), os_mailQ_m_##name }; \
-const osMailQDef_t os_mailQ_def_##name = \
-{ (queue_sz), sizeof(type), (os_mailQ_p_##name) }
-#endif
-
-/// \brief Access a Mail Queue Definition.
-/// \param name name of the queue
-#define osMailQ(name) \
-&os_mailQ_def_##name
-
-/// Create and Initialize mail queue.
-/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ
-/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
-/// \return mail queue ID for reference by other functions or NULL in case of error.
-osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
-
-/// Allocate a memory block from a mail.
-/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
-/// \return pointer to memory block that can be filled with mail or NULL in case of error.
-void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
-
-/// Allocate a memory block from a mail and set memory block to zero.
-/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
-/// \return pointer to memory block that can be filled with mail or NULL in case of error.
-void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
-
-/// Put a mail to a queue.
-/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
-/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
-/// \return status code that indicates the execution status of the function.
-osStatus osMailPut (osMailQId queue_id, void *mail);
-
-/// Get a mail from a queue.
-/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
-/// \return event that contains mail information or error code.
-os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
-
-/// Free a memory block from a mail.
-/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
-/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet.
-/// \return status code that indicates the execution status of the function.
-osStatus osMailFree (osMailQId queue_id, void *mail);
-
-#endif // Mail Queues available
-
-
-// ==== Thread Enumeration Functions ====
-
-#if (defined (osFeature_ThreadEnum) && (osFeature_ThreadEnum != 0)) // Thread enumeration available
-
-/// Start a thread enumeration.
-/// \return an enumeration ID or NULL on error.
-osThreadEnumId _osThreadsEnumStart(void);
-
-/// Get the next task ID in the enumeration.
-/// \return a thread ID or NULL on if the end of the enumeration has been reached.
-osThreadId _osThreadEnumNext(osThreadEnumId enum_id);
-
-/// Free the enumeration structure.
-/// \param[in] enum_id pointer to the enumeration ID that was obtained with \ref _osThreadsEnumStart.
-/// \return status code that indicates the execution status of the function.
-osStatus _osThreadEnumFree(osThreadEnumId enum_id);
-
-#endif // Thread Enumeration available
-
-
-// ==== RTX Extensions ====
-
-/// Suspend the RTX task scheduler.
-/// \return number of ticks, for how long the system can sleep or power-down.
-uint32_t os_suspend (void);
-
-/// Resume the RTX task scheduler
-/// \param[in] sleep_time specifies how long the system was in sleep or power-down mode.
-void os_resume (uint32_t sleep_time);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // _CMSIS_OS_H
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c b/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c
deleted file mode 100644
index 82c7619dd8..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c
+++ /dev/null
@@ -1,2372 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: rt_CMSIS.c
- * Purpose: CMSIS RTOS API
- * Rev.: V4.80 plus changes for RTX-Ax
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH, 2012-2016 ARM Limited
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-#define __CMSIS_GENERIC
-
-#if defined (__CORTEX_M4) || defined (__CORTEX_M4F)
- #include "core_cm4.h"
-#elif defined (__CORTEX_M3)
- #include "core_cm3.h"
-#elif defined (__CORTEX_M0)
- #include "core_cm0.h"
-#elif defined (__CORTEX_A9)
- #include "core_ca9.h"
-#else
- #error "Missing __CORTEX_xx definition"
-#endif
-
-#include "rt_TypeDef.h"
-#include "RTX_Config.h"
-#include "rt_System.h"
-#include "rt_Task.h"
-#include "rt_Event.h"
-#include "rt_List.h"
-#include "rt_Time.h"
-#include "rt_Mutex.h"
-#include "rt_Semaphore.h"
-#include "rt_Mailbox.h"
-#include "rt_MemBox.h"
-#include "rt_Memory.h"
-#include "rt_HAL_CM.h"
-
-#define os_thread_cb OS_TCB
-
-#include "cmsis_os.h"
-
-#if (osFeature_Signals != 16)
-#error Invalid "osFeature_Signals" value!
-#endif
-#if (osFeature_Semaphore > 65535)
-#error Invalid "osFeature_Semaphore" value!
-#endif
-#if (osFeature_Wait != 0)
-#error osWait not supported!
-#endif
-
-
-// ==== Enumeration, structures, defines ====
-
-// Service Calls defines
-
-#if defined (__CC_ARM) /* ARM Compiler */
-
-#define __NO_RETURN __declspec(noreturn)
-
-#define osEvent_type osEvent
-#define osEvent_ret_status ret
-#define osEvent_ret_value ret
-#define osEvent_ret_msg ret
-#define osEvent_ret_mail ret
-
-#define osCallback_type osCallback
-#define osCallback_ret ret
-
-#define SVC_0_1(f,t,...) \
-__svc_indirect(0) t _##f (t(*)()); \
- t f (void); \
-__attribute__((always_inline)) \
-static __inline t __##f (void) { \
- return _##f(f); \
-}
-
-#define SVC_1_0(f,t,t1,...) \
-__svc_indirect(0) t _##f (t(*)(t1),t1); \
- t f (t1 a1); \
-__attribute__((always_inline)) \
-static __inline t __##f (t1 a1) { \
- _##f(f,a1); \
-}
-
-#define SVC_1_1(f,t,t1,...) \
-__svc_indirect(0) t _##f (t(*)(t1),t1); \
- t f (t1 a1); \
-__attribute__((always_inline)) \
-static __inline t __##f (t1 a1) { \
- return _##f(f,a1); \
-}
-
-#define SVC_2_1(f,t,t1,t2,...) \
-__svc_indirect(0) t _##f (t(*)(t1,t2),t1,t2); \
- t f (t1 a1, t2 a2); \
-__attribute__((always_inline)) \
-static __inline t __##f (t1 a1, t2 a2) { \
- return _##f(f,a1,a2); \
-}
-
-#define SVC_3_1(f,t,t1,t2,t3,...) \
-__svc_indirect(0) t _##f (t(*)(t1,t2,t3),t1,t2,t3); \
- t f (t1 a1, t2 a2, t3 a3); \
-__attribute__((always_inline)) \
-static __inline t __##f (t1 a1, t2 a2, t3 a3) { \
- return _##f(f,a1,a2,a3); \
-}
-
-#define SVC_4_1(f,t,t1,t2,t3,t4,...) \
-__svc_indirect(0) t _##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4); \
- t f (t1 a1, t2 a2, t3 a3, t4 a4); \
-__attribute__((always_inline)) \
-static __inline t __##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
- return _##f(f,a1,a2,a3,a4); \
-}
-
-#define SVC_1_2 SVC_1_1
-#define SVC_1_3 SVC_1_1
-#define SVC_2_3 SVC_2_1
-
-#elif defined (__GNUC__) /* GNU Compiler */
-
-#define __NO_RETURN __attribute__((noreturn))
-
-typedef uint32_t __attribute__((vector_size(8))) ret64;
-typedef uint32_t __attribute__((vector_size(16))) ret128;
-
-#define RET_pointer __r0
-#define RET_int32_t __r0
-#define RET_uint32_t __r0
-#define RET_osStatus __r0
-#define RET_osPriority __r0
-#define RET_osEvent {(osStatus)__r0, {(uint32_t)__r1}, {(void *)__r2}}
-#define RET_osCallback {(void *)__r0, (void *)__r1}
-
-#define osEvent_type __attribute__((pcs("aapcs"))) ret128
-#define osEvent_ret_status (ret128){ret.status}
-#define osEvent_ret_value (ret128){ret.status, ret.value.v}
-#define osEvent_ret_msg (ret128){ret.status, ret.value.v, (uint32_t)ret.def.message_id}
-#define osEvent_ret_mail (ret128){ret.status, ret.value.v, (uint32_t)ret.def.mail_id}
-
-#define osCallback_type __attribute__((pcs("aapcs"))) ret64
-#define osCallback_ret (ret64) {(uint32_t)ret.fp, (uint32_t)ret.arg}
-
-#define SVC_ArgN(n) \
- register int __r##n __asm("r"#n);
-
-#define SVC_ArgR(n,t,a) \
- register t __r##n __asm("r"#n) = a;
-
-#define SVC_Arg0() \
- SVC_ArgN(0) \
- SVC_ArgN(1) \
- SVC_ArgN(2) \
- SVC_ArgN(3)
-
-#define SVC_Arg1(t1) \
- SVC_ArgR(0,t1,a1) \
- SVC_ArgN(1) \
- SVC_ArgN(2) \
- SVC_ArgN(3)
-
-#define SVC_Arg2(t1,t2) \
- SVC_ArgR(0,t1,a1) \
- SVC_ArgR(1,t2,a2) \
- SVC_ArgN(2) \
- SVC_ArgN(3)
-
-#define SVC_Arg3(t1,t2,t3) \
- SVC_ArgR(0,t1,a1) \
- SVC_ArgR(1,t2,a2) \
- SVC_ArgR(2,t3,a3) \
- SVC_ArgN(3)
-
-#define SVC_Arg4(t1,t2,t3,t4) \
- SVC_ArgR(0,t1,a1) \
- SVC_ArgR(1,t2,a2) \
- SVC_ArgR(2,t3,a3) \
- SVC_ArgR(3,t4,a4)
-
-#if (defined (__CORTEX_M0))
-#define SVC_Call(f) \
- __asm volatile \
- ( \
- "ldr r7,="#f"\n\t" \
- "mov r12,r7\n\t" \
- "svc 0" \
- : "=r" (__r0), "=r" (__r1), "=r" (__r2), "=r" (__r3) \
- : "r" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) \
- : "r7", "r12", "lr", "cc" \
- );
-#else
-#define SVC_Call(f) \
- __asm volatile \
- ( \
- "ldr r12,="#f"\n\t" \
- "svc 0" \
- : "=r" (__r0), "=r" (__r1), "=r" (__r2), "=r" (__r3) \
- : "r" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) \
- : "r12", "lr", "cc" \
- );
-#endif
-
-#define SVC_0_1(f,t,rv) \
-__attribute__((always_inline)) \
-static inline t __##f (void) { \
- SVC_Arg0(); \
- SVC_Call(f); \
- return (t) rv; \
-}
-
-#define SVC_1_0(f,t,t1) \
-__attribute__((always_inline)) \
-static inline t __##f (t1 a1) { \
- SVC_Arg1(t1); \
- SVC_Call(f); \
-}
-
-#define SVC_1_1(f,t,t1,rv) \
-__attribute__((always_inline)) \
-static inline t __##f (t1 a1) { \
- SVC_Arg1(t1); \
- SVC_Call(f); \
- return (t) rv; \
-}
-
-#define SVC_2_1(f,t,t1,t2,rv) \
-__attribute__((always_inline)) \
-static inline t __##f (t1 a1, t2 a2) { \
- SVC_Arg2(t1,t2); \
- SVC_Call(f); \
- return (t) rv; \
-}
-
-#define SVC_3_1(f,t,t1,t2,t3,rv) \
-__attribute__((always_inline)) \
-static inline t __##f (t1 a1, t2 a2, t3 a3) { \
- SVC_Arg3(t1,t2,t3); \
- SVC_Call(f); \
- return (t) rv; \
-}
-
-#define SVC_4_1(f,t,t1,t2,t3,t4,rv) \
-__attribute__((always_inline)) \
-static inline t __##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
- SVC_Arg4(t1,t2,t3,t4); \
- SVC_Call(f); \
- return (t) rv; \
-}
-
-#define SVC_1_2 SVC_1_1
-#define SVC_1_3 SVC_1_1
-#define SVC_2_3 SVC_2_1
-
-#elif defined (__ICCARM__) /* IAR Compiler */
-
-#define __NO_RETURN __noreturn
-
-#define RET_osEvent "=r"(ret.status), "=r"(ret.value), "=r"(ret.def)
-#define RET_osCallback "=r"(ret.fp), "=r"(ret.arg)
-
-#define osEvent_type osEvent
-#define osEvent_ret_status ret
-#define osEvent_ret_value ret
-#define osEvent_ret_msg ret
-#define osEvent_ret_mail ret
-
-#define osCallback_type uint64_t
-#define osCallback_ret ((uint64_t)ret.fp | ((uint64_t)ret.arg)<<32)
-
-#define SVC_Setup(f) \
- __asm( \
- "mov r12,%0\n" \
- :: "r"(&f): "r12" \
- );
-
-#define SVC_Ret3() \
- __asm( \
- "ldr r0,[sp,#0]\n" \
- "ldr r1,[sp,#4]\n" \
- "ldr r2,[sp,#8]\n" \
- );
-
-#define SVC_0_1(f,t,...) \
-t f (void); \
-_Pragma("swi_number=0") __swi t _##f (void); \
-static inline t __##f (void) { \
- SVC_Setup(f); \
- return _##f(); \
-}
-
-#define SVC_1_0(f,t,t1,...) \
-t f (t1 a1); \
-_Pragma("swi_number=0") __swi t _##f (t1 a1); \
-static inline t __##f (t1 a1) { \
- SVC_Setup(f); \
- _##f(a1); \
-}
-
-#define SVC_1_1(f,t,t1,...) \
-t f (t1 a1); \
-_Pragma("swi_number=0") __swi t _##f (t1 a1); \
-static inline t __##f (t1 a1) { \
- SVC_Setup(f); \
- return _##f(a1); \
-}
-
-#define SVC_2_1(f,t,t1,t2,...) \
-t f (t1 a1, t2 a2); \
-_Pragma("swi_number=0") __swi t _##f (t1 a1, t2 a2); \
-static inline t __##f (t1 a1, t2 a2) { \
- SVC_Setup(f); \
- return _##f(a1,a2); \
-}
-
-#define SVC_3_1(f,t,t1,t2,t3,...) \
-t f (t1 a1, t2 a2, t3 a3); \
-_Pragma("swi_number=0") __swi t _##f (t1 a1, t2 a2, t3 a3); \
-static inline t __##f (t1 a1, t2 a2, t3 a3) { \
- SVC_Setup(f); \
- return _##f(a1,a2,a3); \
-}
-
-#define SVC_4_1(f,t,t1,t2,t3,t4,...) \
-t f (t1 a1, t2 a2, t3 a3, t4 a4); \
-_Pragma("swi_number=0") __swi t _##f (t1 a1, t2 a2, t3 a3, t4 a4); \
-static inline t __##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
- SVC_Setup(f); \
- return _##f(a1,a2,a3,a4); \
-}
-
-#define SVC_1_2(f,t,t1,rr) \
-uint64_t f (t1 a1); \
-_Pragma("swi_number=0") __swi uint64_t _##f (t1 a1); \
-static inline t __##f (t1 a1) { \
- t ret; \
- SVC_Setup(f); \
- _##f(a1); \
- __asm("" : rr : :); \
- return ret; \
-}
-
-#define SVC_1_3(f,t,t1,rr) \
-t f (t1 a1); \
-void f##_ (t1 a1) { \
- f(a1); \
- SVC_Ret3(); \
-} \
-_Pragma("swi_number=0") __swi void _##f (t1 a1); \
-static inline t __##f (t1 a1) { \
- t ret; \
- SVC_Setup(f##_); \
- _##f(a1); \
- __asm("" : rr : :); \
- return ret; \
-}
-
-#define SVC_2_3(f,t,t1,t2,rr) \
-t f (t1 a1, t2 a2); \
-void f##_ (t1 a1, t2 a2) { \
- f(a1,a2); \
- SVC_Ret3(); \
-} \
-_Pragma("swi_number=0") __swi void _##f (t1 a1, t2 a2); \
-static inline t __##f (t1 a1, t2 a2) { \
- t ret; \
- SVC_Setup(f##_); \
- _##f(a1,a2); \
- __asm("" : rr : :); \
- return ret; \
-}
-
-#endif
-
-
-// Callback structure
-typedef struct {
- void *fp; // Function pointer
- void *arg; // Function argument
-} osCallback;
-
-
-// OS Section definitions
-#ifdef OS_SECTIONS_LINK_INFO
-extern const uint32_t os_section_id$$Base;
-extern const uint32_t os_section_id$$Limit;
-#endif
-
-#ifndef __MBED_CMSIS_RTOS_CA9
-// OS Stack Memory for Threads definitions
-extern uint64_t os_stack_mem[];
-extern const uint32_t os_stack_sz;
-#endif
-
-// OS Timers external resources
-extern const osThreadDef_t os_thread_def_osTimerThread;
-extern osThreadId osThreadId_osTimerThread;
-extern const osMessageQDef_t os_messageQ_def_osTimerMessageQ;
-extern osMessageQId osMessageQId_osTimerMessageQ;
-
-extern U32 IRQNestLevel; /* Indicates whether inside an ISR, and the depth of nesting. 0 = not in ISR. */
-
-// Thread creation and destruction
-osMutexDef(osThreadMutex);
-osMutexId osMutexId_osThreadMutex;
-void sysThreadTerminate(osThreadId id);
-
-// ==== Helper Functions ====
-
-/// Convert timeout in millisec to system ticks
-static uint16_t rt_ms2tick (uint32_t millisec) {
- uint32_t tick;
-
- if (millisec == 0U) { return 0x0U; } // No timeout
- if (millisec == osWaitForever) { return 0xFFFFU; } // Indefinite timeout
- if (millisec > 4000000U) { return 0xFFFEU; } // Max ticks supported
-
- tick = ((1000U * millisec) + os_clockrate - 1U) / os_clockrate;
- if (tick > 0xFFFEU) { return 0xFFFEU; }
-
- return (uint16_t)tick;
-}
-
-/// Convert Thread ID to TCB pointer
-P_TCB rt_tid2ptcb (osThreadId thread_id) {
- P_TCB ptcb;
-
- if (thread_id == NULL) { return NULL; }
-
- if ((uint32_t)thread_id & 3U) { return NULL; }
-
-#ifdef OS_SECTIONS_LINK_INFO
- if ((os_section_id$$Base != 0U) && (os_section_id$$Limit != 0U)) {
- if (thread_id < (osThreadId)os_section_id$$Base) { return NULL; }
- if (thread_id >= (osThreadId)os_section_id$$Limit) { return NULL; }
- }
-#endif
-
- ptcb = thread_id;
-
- if (ptcb->cb_type != TCB) { return NULL; }
-
- return ptcb;
-}
-
-/// Convert ID pointer to Object pointer
-static void *rt_id2obj (void *id) {
-
- if ((uint32_t)id & 3U) { return NULL; }
-
-#ifdef OS_SECTIONS_LINK_INFO
- if ((os_section_id$$Base != 0U) && (os_section_id$$Limit != 0U)) {
- if (id < (void *)os_section_id$$Base) { return NULL; }
- if (id >= (void *)os_section_id$$Limit) { return NULL; }
- }
-#endif
-
- return id;
-}
-
-// === Helper functions for system call interface ===
-
-static __inline char __get_mode(void) {
- return (char)(__get_CPSR() & 0x1FU);
-}
-
-static __inline char __exceptional_mode(void) {
- // Interrupts disabled
- if (__get_CPSR() & 0x80) {
- return 1;
- }
-
- switch(__get_mode()) {
- case MODE_USR:
- case MODE_SYS:
- return 0U;
- case MODE_SVC:
- if (IRQNestLevel == 0U)
- return 0U; /* handling a regular service call */
- else
- return 1U; /* handling an ISR in SVC mode */
- default:
- return 1U;
- }
-}
-
-// ==== Kernel Control ====
-
-uint8_t os_initialized; // Kernel Initialized flag
-uint8_t os_running; // Kernel Running flag
-
-// Kernel Control Service Calls declarations
-SVC_0_1(svcKernelInitialize, osStatus, RET_osStatus)
-SVC_0_1(svcKernelStart, osStatus, RET_osStatus)
-SVC_0_1(svcKernelRunning, int32_t, RET_int32_t)
-SVC_0_1(svcKernelSysTick, uint32_t, RET_uint32_t)
-
-static void sysThreadError (osStatus status);
-osThreadId svcThreadCreate (const osThreadDef_t *thread_def, void *argument);
-osMessageQId svcMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
-
-// Kernel Control Service Calls
-
-/// Initialize the RTOS Kernel for creating objects
-osStatus svcKernelInitialize (void) {
-#ifdef __MBED_CMSIS_RTOS_CA9
- if (!os_initialized) {
- rt_sys_init(); // RTX System Initialization
- }
-#else
- uint32_t ret;
-
- if (os_initialized == 0U) {
-
- // Init Thread Stack Memory (must be 8-byte aligned)
- if (((uint32_t)os_stack_mem & 7U) != 0U) { return osErrorNoMemory; }
- ret = rt_init_mem(os_stack_mem, os_stack_sz);
- if (ret != 0U) { return osErrorNoMemory; }
-
- rt_sys_init(); // RTX System Initialization
- }
-#endif
-
- os_tsk.run->prio = 255U; // Highest priority
-
- if (os_initialized == 0U) {
- // Create OS Timers resources (Message Queue & Thread)
- osMessageQId_osTimerMessageQ = svcMessageCreate (&os_messageQ_def_osTimerMessageQ, NULL);
- osThreadId_osTimerThread = svcThreadCreate(&os_thread_def_osTimerThread, NULL);
- // Initialize thread mutex
- osMutexId_osThreadMutex = osMutexCreate(osMutex(osThreadMutex));
- }
-
- sysThreadError(osOK);
-
- os_initialized = 1U;
- os_running = 0U;
-
- return osOK;
-}
-
-/// Start the RTOS Kernel
-osStatus svcKernelStart (void) {
-
- if (os_running) { return osOK; }
-
- rt_tsk_prio(0U, os_tsk.run->prio_base); // Restore priority
- if (os_tsk.run->task_id == 0xFFU) { // Idle Thread
- __set_PSP(os_tsk.run->tsk_stack + (8U*4U)); // Setup PSP
- }
- os_tsk.run = NULL; // Force context switch
-
- rt_sys_start();
-
- os_running = 1U;
-
- return osOK;
-}
-
-/// Check if the RTOS kernel is already started
-int32_t svcKernelRunning (void) {
- return (int32_t)os_running;
-}
-
-/// Get the RTOS kernel system timer counter
-uint32_t svcKernelSysTick (void) {
- uint32_t tick, tick0;
-
- tick = os_tick_val();
- if (os_tick_ovf()) {
- tick0 = os_tick_val();
- if (tick0 < tick) { tick = tick0; }
- tick += (os_trv + 1U) * (os_time + 1U);
- } else {
- tick += (os_trv + 1U) * os_time;
- }
-
- return tick;
-}
-
-// Kernel Control Public API
-
-/// Initialize the RTOS Kernel for creating objects
-osStatus osKernelInitialize (void) {
- if (__exceptional_mode()) {
- return osErrorISR; // Not allowed in ISR
- }
- if (__get_mode() != MODE_USR) {
- return svcKernelInitialize();
- } else {
- return __svcKernelInitialize();
- }
-}
-
-/// Start the RTOS Kernel
-osStatus osKernelStart (void) {
- char mode = __get_mode();
-
- switch(mode) {
- case MODE_USR:
- if (os_flags & 1U) return osErrorOS; // Privileged Thread mode requested from Unprivileged
- break;
- case MODE_SYS:
- if (!(os_flags & 1U)) {
- __set_CPS_USR();
- }
- break;
- default:
- return osErrorISR; // Not allowed in ISR
- }
- return __svcKernelStart();
-}
-
-/// Check if the RTOS kernel is already started
-int32_t osKernelRunning (void) {
- if(__get_mode() != MODE_USR) {
- return os_running;
- } else {
- return __svcKernelRunning();
- }
-}
-
-/// Get the RTOS kernel system timer counter
-uint32_t osKernelSysTick (void) {
- if (__exceptional_mode()) { return 0U; } // Not allowed in ISR
- return __svcKernelSysTick();
-}
-
-
-// ==== Thread Management ====
-
-/// Set Thread Error (for Create functions which return IDs)
-static void sysThreadError (osStatus status) {
- // To Do
-}
-
-__NO_RETURN void osThreadExit (void);
-
-// Thread Service Calls declarations
-SVC_2_1(svcThreadCreate, osThreadId, const osThreadDef_t *, void *, RET_pointer)
-SVC_0_1(svcThreadGetId, osThreadId, RET_pointer)
-SVC_1_1(svcThreadTerminate, osStatus, osThreadId, RET_osStatus)
-SVC_0_1(svcThreadYield, osStatus, RET_osStatus)
-SVC_2_1(svcThreadSetPriority, osStatus, osThreadId, osPriority, RET_osStatus)
-SVC_1_1(svcThreadGetPriority, osPriority, osThreadId, RET_osPriority)
-SVC_2_3(svcThreadGetInfo, os_InRegs osEvent, osThreadId, osThreadInfo, RET_osEvent)
-
-// Thread Service Calls
-
-/// Create a thread and add it to Active Threads and set it to state READY
-osThreadId svcThreadCreate (const osThreadDef_t *thread_def, void *argument) {
- P_TCB ptcb;
- OS_TID tsk;
- void *stk;
-
- if ((thread_def == NULL) ||
- (thread_def->pthread == NULL) ||
- (thread_def->tpriority < osPriorityIdle) ||
- (thread_def->tpriority > osPriorityRealtime)) {
- sysThreadError(osErrorParameter);
- return NULL;
- }
-
-#ifdef __MBED_CMSIS_RTOS_CA9
- if (thread_def->stacksize != 0U) { // Custom stack size
- stk = (void *)thread_def->stack_pointer;
- } else { // Default stack size
- stk = NULL;
- }
-#else
- if (thread_def->stacksize != 0U) { // Custom stack size
- stk = rt_alloc_mem( // Allocate stack
- os_stack_mem,
- thread_def->stacksize
- );
- if (stk == NULL) {
- sysThreadError(osErrorNoMemory); // Out of memory
- return NULL;
- }
- } else { // Default stack size
- stk = NULL;
- }
-#endif
-
- tsk = rt_tsk_create( // Create task
- (FUNCP)thread_def->pthread, // Task function pointer
- (uint32_t)
- (thread_def->tpriority-osPriorityIdle+1) | // Task priority
- (thread_def->stacksize << 8), // Task stack size in bytes
- stk, // Pointer to task's stack
- argument // Argument to the task
- );
-
- if (tsk == 0U) { // Invalid task ID
-#ifndef __MBED_CMSIS_RTOS_CA9
- if (stk != NULL) {
- rt_free_mem(os_stack_mem, stk); // Free allocated stack
- }
-#endif
- sysThreadError(osErrorNoMemory); // Create task failed (Out of memory)
- return NULL;
- }
-
- ptcb = (P_TCB)os_active_TCB[tsk - 1U]; // TCB pointer
-
- *((uint32_t *)ptcb->tsk_stack + 13) = (uint32_t)osThreadExit;
-
- return ptcb;
-}
-
-/// Return the thread ID of the current running thread
-osThreadId svcThreadGetId (void) {
- OS_TID tsk;
-
- tsk = rt_tsk_self();
- if (tsk == 0U) { return NULL; }
- return (P_TCB)os_active_TCB[tsk - 1U];
-}
-
-/// Terminate execution of a thread and remove it from ActiveThreads
-osStatus svcThreadTerminate (osThreadId thread_id) {
- OS_RESULT res;
- P_TCB ptcb;
-#ifndef __MBED_CMSIS_RTOS_CA9
- void *stk;
-#endif
-
- ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer
- if (ptcb == NULL) {
- return osErrorParameter;
- }
-
-#ifndef __MBED_CMSIS_RTOS_CA9
- stk = ptcb->priv_stack ? ptcb->stack : NULL; // Private stack
-#endif
-
- res = rt_tsk_delete(ptcb->task_id); // Delete task
-
- if (res == OS_R_NOK) {
- return osErrorResource; // Delete task failed
- }
-
-#ifndef __MBED_CMSIS_RTOS_CA9
- if (stk != NULL) {
- rt_free_mem(os_stack_mem, stk); // Free private stack
- }
-#endif
-
- return osOK;
-}
-
-/// Pass control to next thread that is in state READY
-osStatus svcThreadYield (void) {
- rt_tsk_pass(); // Pass control to next task
- return osOK;
-}
-
-/// Change priority of an active thread
-osStatus svcThreadSetPriority (osThreadId thread_id, osPriority priority) {
- OS_RESULT res;
- P_TCB ptcb;
-
- ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer
- if (ptcb == NULL) {
- return osErrorParameter;
- }
-
- if ((priority < osPriorityIdle) || (priority > osPriorityRealtime)) {
- return osErrorValue;
- }
-
- res = rt_tsk_prio( // Change task priority
- ptcb->task_id, // Task ID
- (uint8_t)(priority - osPriorityIdle + 1) // New task priority
- );
-
- if (res == OS_R_NOK) {
- return osErrorResource; // Change task priority failed
- }
-
- return osOK;
-}
-
-/// Get current priority of an active thread
-osPriority svcThreadGetPriority (osThreadId thread_id) {
- P_TCB ptcb;
-
- ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer
- if (ptcb == NULL) {
- return osPriorityError;
- }
-
- return (osPriority)(ptcb->prio - 1 + osPriorityIdle);
-}
-
-/// Get info from an active thread
-os_InRegs osEvent_type svcThreadGetInfo (osThreadId thread_id, osThreadInfo info) {
- P_TCB ptcb;
- osEvent ret;
- ret.status = osOK;
-
- ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer
- if (ptcb == NULL) {
- ret.status = osErrorValue;
- return osEvent_ret_status;
- }
-
- if (osThreadInfoStackSize == info) {
- uint32_t size;
- size = ptcb->priv_stack;
- if (0U == size) {
- // This is an OS task - always a fixed size
- size = os_stackinfo & 0x3FFFFU;
- }
- ret.value.v = size;
- return osEvent_ret_value;
- }
-
- if (osThreadInfoStackMax == info) {
- uint32_t i;
- uint32_t *stack_ptr;
- uint32_t stack_size;
- if (!(os_stackinfo & (1 << 28))) {
- // Stack init must be turned on for max stack usage
- ret.status = osErrorResource;
- return osEvent_ret_status;
- }
- stack_ptr = (uint32_t*)ptcb->stack;
- stack_size = ptcb->priv_stack;
- if (0 == stack_size) {
- // This is an OS task - always a fixed size
- stack_size = os_stackinfo & 0x3FFFF;
- }
- for (i = 1; i ptask;
- return osEvent_ret_value;
- }
-
- if (osThreadInfoArg == info) {
- ret.value.p = (void*)ptcb->argv;
- return osEvent_ret_value;
- }
-
- // Unsupported option so return error
- ret.status = osErrorParameter;
- return osEvent_ret_status;
-}
-
-// Thread Public API
-
-/// Create a thread and add it to Active Threads and set it to state READY
-osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) {
- if (__exceptional_mode()) {
- return NULL; // Not allowed in ISR
- }
- if ((__get_mode() != MODE_USR) && (os_running == 0U)) {
- // Privileged and not running
- return svcThreadCreate(thread_def, argument);
- } else {
- osThreadId id;
- osMutexWait(osMutexId_osThreadMutex, osWaitForever);
- // Thread mutex must be held when a thread is created or terminated
- id = __svcThreadCreate(thread_def, argument);
- osMutexRelease(osMutexId_osThreadMutex);
- return id;
- }
-}
-
-/// Return the thread ID of the current running thread
-osThreadId osThreadGetId (void) {
- if (__exceptional_mode()) {
- return NULL; // Not allowed in ISR
- }
- return __svcThreadGetId();
-}
-
-/// Terminate execution of a thread and remove it from ActiveThreads
-osStatus osThreadTerminate (osThreadId thread_id) {
- osStatus status;
- if (__exceptional_mode()) {
- return osErrorISR; // Not allowed in ISR
- }
- osMutexWait(osMutexId_osThreadMutex, osWaitForever);
- sysThreadTerminate(thread_id);
- // Thread mutex must be held when a thread is created or terminated
- status = __svcThreadTerminate(thread_id);
- osMutexRelease(osMutexId_osThreadMutex);
- return status;
-}
-
-/// Pass control to next thread that is in state READY
-osStatus osThreadYield (void) {
- if (__exceptional_mode()) {
- return osErrorISR; // Not allowed in ISR
- }
- return __svcThreadYield();
-}
-
-/// Change priority of an active thread
-osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority) {
- if (__exceptional_mode()) {
- return osErrorISR; // Not allowed in ISR
- }
- return __svcThreadSetPriority(thread_id, priority);
-}
-
-/// Get current priority of an active thread
-osPriority osThreadGetPriority (osThreadId thread_id) {
- if (__exceptional_mode()) {
- return osPriorityError;// Not allowed in ISR
- }
- return __svcThreadGetPriority(thread_id);
-}
-
-/// INTERNAL - Not Public
-/// Auto Terminate Thread on exit (used implicitly when thread exists)
-__NO_RETURN void osThreadExit (void) {
- osThreadId id;
- // Thread mutex must be held when a thread is created or terminated
- // Note - the mutex will be released automatically by the os when
- // the thread is terminated
- osMutexWait(osMutexId_osThreadMutex, osWaitForever);
- id = __svcThreadGetId();
- sysThreadTerminate(id);
- __svcThreadTerminate(id);
- for (;;); // Should never come here
-}
-
-#ifdef __MBED_CMSIS_RTOS_CA9
-/// Get current thread state
-uint8_t osThreadGetState (osThreadId thread_id) {
- P_TCB ptcb;
-
- if (__exceptional_mode()) {
- return osErrorISR; // Not allowed in ISR
- }
-
- ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer
- if (ptcb == NULL) {
- return INACTIVE;
- }
-
- return ptcb->state;
-}
-#endif
-
-/// Get the requested info from the specified active thread
-os_InRegs osEvent _osThreadGetInfo(osThreadId thread_id, osThreadInfo info) {
- osEvent ret;
- if (__exceptional_mode()) {
- ret.status = osErrorISR;
- return ret; // Not allowed in ISR
- }
- return __svcThreadGetInfo(thread_id, info);
-}
-
-osThreadEnumId _osThreadsEnumStart() {
- static uint32_t thread_enum_index;
- osMutexWait(osMutexId_osThreadMutex, osWaitForever);
- thread_enum_index = 0;
- return &thread_enum_index;
-}
-
-osThreadId _osThreadEnumNext(osThreadEnumId enum_id) {
- uint32_t i;
- osThreadId id = NULL;
- uint32_t *index = (uint32_t*)enum_id;
- for (i = *index; i < os_maxtaskrun; i++) {
- if (os_active_TCB[i] != NULL) {
- id = (osThreadId)os_active_TCB[i];
- break;
- }
- }
- if (i == os_maxtaskrun) {
- // Include the idle task at the end of the enumeration
- id = &os_idle_TCB;
- }
- *index = i + 1U;
- return id;
-}
-
-osStatus _osThreadEnumFree(osThreadEnumId enum_id) {
- uint32_t *index = (uint32_t*)enum_id;
- *index = 0U;
- osMutexRelease(osMutexId_osThreadMutex);
- return osOK;
-}
-
-// ==== Generic Wait Functions ====
-
-// Generic Wait Service Calls declarations
-SVC_1_1(svcDelay, osStatus, uint32_t, RET_osStatus)
-#if osFeature_Wait != 0
-SVC_1_3(svcWait, os_InRegs osEvent, uint32_t, RET_osEvent)
-#endif
-
-// Generic Wait Service Calls
-
-/// Wait for Timeout (Time Delay)
-osStatus svcDelay (uint32_t millisec) {
- if (millisec == 0U) { return osOK; }
- rt_dly_wait(rt_ms2tick(millisec));
- return osEventTimeout;
-}
-
-/// Wait for Signal, Message, Mail, or Timeout
-#if osFeature_Wait != 0
-os_InRegs osEvent_type svcWait (uint32_t millisec) {
- osEvent ret;
-
- if (millisec == 0U) {
- ret.status = osOK;
- return osEvent_ret_status;
- }
-
- /* To Do: osEventSignal, osEventMessage, osEventMail */
- rt_dly_wait(rt_ms2tick(millisec));
- ret.status = osEventTimeout;
-
- return osEvent_ret_status;
-}
-#endif
-
-
-// Generic Wait API
-
-/// Wait for Timeout (Time Delay)
-osStatus osDelay (uint32_t millisec) {
- if (__exceptional_mode()) {
- return osErrorISR; // Not allowed in ISR
- }
- return __svcDelay(millisec);
-}
-
-/// Wait for Signal, Message, Mail, or Timeout
-os_InRegs osEvent osWait (uint32_t millisec) {
- osEvent ret;
-
-#if osFeature_Wait == 0
- ret.status = osErrorOS;
- return ret;
-#else
- if (__exceptional_mode()) { // Not allowed in ISR
- ret.status = osErrorISR;
- return ret;
- }
- return __svcWait(millisec);
-#endif
-}
-
-
-// ==== Timer Management ====
-
-// Timer definitions
-#define osTimerInvalid 0U
-#define osTimerStopped 1U
-#define osTimerRunning 2U
-
-// Timer structures
-
-typedef struct os_timer_cb_ { // Timer Control Block
- struct os_timer_cb_ *next; // Pointer to next active Timer
- uint8_t state; // Timer State
- uint8_t type; // Timer Type (Periodic/One-shot)
- uint16_t reserved; // Reserved
- uint32_t tcnt; // Timer Delay Count
- uint32_t icnt; // Timer Initial Count
- void *arg; // Timer Function Argument
- const osTimerDef_t *timer; // Pointer to Timer definition
-} os_timer_cb;
-
-// Timer variables
-os_timer_cb *os_timer_head; // Pointer to first active Timer
-
-
-// Timer Helper Functions
-
-// Insert Timer into the list sorted by time
-static void rt_timer_insert (os_timer_cb *pt, uint32_t tcnt) {
- os_timer_cb *p, *prev;
-
- prev = NULL;
- p = os_timer_head;
- while (p != NULL) {
- if (tcnt < p->tcnt) { break; }
- tcnt -= p->tcnt;
- prev = p;
- p = p->next;
- }
- pt->next = p;
- pt->tcnt = tcnt;
- if (p != NULL) {
- p->tcnt -= pt->tcnt;
- }
- if (prev != NULL) {
- prev->next = pt;
- } else {
- os_timer_head = pt;
- }
-}
-
-// Remove Timer from the list
-static int32_t rt_timer_remove (os_timer_cb *pt) {
- os_timer_cb *p, *prev;
-
- prev = NULL;
- p = os_timer_head;
- while (p != NULL) {
- if (p == pt) { break; }
- prev = p;
- p = p->next;
- }
- if (p == NULL) { return -1; }
- if (prev != NULL) {
- prev->next = pt->next;
- } else {
- os_timer_head = pt->next;
- }
- if (pt->next != NULL) {
- pt->next->tcnt += pt->tcnt;
- }
-
- return 0;
-}
-
-
-// Timer Service Calls declarations
-SVC_3_1(svcTimerCreate, osTimerId, const osTimerDef_t *, os_timer_type, void *, RET_pointer)
-SVC_2_1(svcTimerStart, osStatus, osTimerId, uint32_t, RET_osStatus)
-SVC_1_1(svcTimerStop, osStatus, osTimerId, RET_osStatus)
-SVC_1_1(svcTimerDelete, osStatus, osTimerId, RET_osStatus)
-SVC_1_2(svcTimerCall, os_InRegs osCallback, osTimerId, RET_osCallback)
-
-// Timer Management Service Calls
-
-/// Create timer
-osTimerId svcTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) {
- os_timer_cb *pt;
-
- if ((timer_def == NULL) || (timer_def->ptimer == NULL)) {
- sysThreadError(osErrorParameter);
- return NULL;
- }
-
- pt = timer_def->timer;
- if (pt == NULL) {
- sysThreadError(osErrorParameter);
- return NULL;
- }
-
- if ((type != osTimerOnce) && (type != osTimerPeriodic)) {
- sysThreadError(osErrorValue);
- return NULL;
- }
-
- if (osThreadId_osTimerThread == NULL) {
- sysThreadError(osErrorResource);
- return NULL;
- }
-
- if (pt->state != osTimerInvalid){
- sysThreadError(osErrorResource);
- return NULL;
- }
-
- pt->next = NULL;
- pt->state = osTimerStopped;
- pt->type = (uint8_t)type;
- pt->arg = argument;
- pt->timer = timer_def;
-
- return (osTimerId)pt;
-}
-
-/// Start or restart timer
-osStatus svcTimerStart (osTimerId timer_id, uint32_t millisec) {
- os_timer_cb *pt;
- uint32_t tcnt;
-
- pt = rt_id2obj(timer_id);
- if (pt == NULL) {
- return osErrorParameter;
- }
-
- if (millisec == 0U) { return osErrorValue; }
-
- tcnt = (uint32_t)(((1000U * (uint64_t)millisec) + os_clockrate - 1U) / os_clockrate);
-
- switch (pt->state) {
- case osTimerRunning:
- if (rt_timer_remove(pt) != 0) {
- return osErrorResource;
- }
- break;
- case osTimerStopped:
- pt->state = osTimerRunning;
- pt->icnt = tcnt;
- break;
- default:
- return osErrorResource;
- }
-
- rt_timer_insert(pt, tcnt);
-
- return osOK;
-}
-
-/// Stop timer
-osStatus svcTimerStop (osTimerId timer_id) {
- os_timer_cb *pt;
-
- pt = rt_id2obj(timer_id);
- if (pt == NULL) {
- return osErrorParameter;
- }
-
- if (pt->state != osTimerRunning) { return osErrorResource; }
-
- pt->state = osTimerStopped;
-
- if (rt_timer_remove(pt) != 0) {
- return osErrorResource;
- }
-
- return osOK;
-}
-
-/// Delete timer
-osStatus svcTimerDelete (osTimerId timer_id) {
- os_timer_cb *pt;
-
- pt = rt_id2obj(timer_id);
- if (pt == NULL) {
- return osErrorParameter;
- }
-
- switch (pt->state) {
- case osTimerRunning:
- rt_timer_remove(pt);
- break;
- case osTimerStopped:
- break;
- default:
- return osErrorResource;
- }
-
- pt->state = osTimerInvalid;
-
- return osOK;
-}
-
-/// Get timer callback parameters
-os_InRegs osCallback_type svcTimerCall (osTimerId timer_id) {
- os_timer_cb *pt;
- osCallback ret;
-
- pt = rt_id2obj(timer_id);
- if (pt == NULL) {
- ret.fp = NULL;
- ret.arg = NULL;
- return osCallback_ret;
- }
-
- ret.fp = (void *)pt->timer->ptimer;
- ret.arg = pt->arg;
-
- return osCallback_ret;
-}
-
-osStatus isrMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
-
-/// Timer Tick (called each SysTick)
-void sysTimerTick (void) {
- os_timer_cb *pt, *p;
- osStatus status;
-
- p = os_timer_head;
- if (p == NULL) { return; }
-
- p->tcnt--;
- while ((p != NULL) && (p->tcnt == 0U)) {
- pt = p;
- p = p->next;
- os_timer_head = p;
- status = isrMessagePut(osMessageQId_osTimerMessageQ, (uint32_t)pt, 0U);
- if (status != osOK) {
- os_error(OS_ERR_TIMER_OVF);
- }
- if (pt->type == (uint8_t)osTimerPeriodic) {
- rt_timer_insert(pt, pt->icnt);
- } else {
- pt->state = osTimerStopped;
- }
- }
-}
-
-/// Get user timers wake-up time
-uint32_t sysUserTimerWakeupTime (void) {
-
- if (os_timer_head) {
- return os_timer_head->tcnt;
- }
- return 0xFFFFFFFFU;
-}
-
-/// Update user timers on resume
-void sysUserTimerUpdate (uint32_t sleep_time) {
-
- while ((os_timer_head != NULL) && (sleep_time != 0U)) {
- if (sleep_time >= os_timer_head->tcnt) {
- sleep_time -= os_timer_head->tcnt;
- os_timer_head->tcnt = 1U;
- sysTimerTick();
- } else {
- os_timer_head->tcnt -= sleep_time;
- break;
- }
- }
-}
-
-
-// Timer Management Public API
-
-/// Create timer
-osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) {
- if (__exceptional_mode()) {
- return NULL; // Not allowed in ISR
- }
- if ((__get_mode() != MODE_USR) && (os_running == 0U)) {
- // Privileged and not running
- return svcTimerCreate(timer_def, type, argument);
- } else {
- return __svcTimerCreate(timer_def, type, argument);
- }
-}
-
-/// Start or restart timer
-osStatus osTimerStart (osTimerId timer_id, uint32_t millisec) {
- if (__exceptional_mode()) {
- return osErrorISR; // Not allowed in ISR
- }
- return __svcTimerStart(timer_id, millisec);
-}
-
-/// Stop timer
-osStatus osTimerStop (osTimerId timer_id) {
- if (__exceptional_mode()) {
- return osErrorISR; // Not allowed in ISR
- }
- return __svcTimerStop(timer_id);
-}
-
-/// Delete timer
-osStatus osTimerDelete (osTimerId timer_id) {
- if (__exceptional_mode()) {
- return osErrorISR; // Not allowed in ISR
- }
- return __svcTimerDelete(timer_id);
-}
-
-/// INTERNAL - Not Public
-/// Get timer callback parameters (used by OS Timer Thread)
-os_InRegs osCallback osTimerCall (osTimerId timer_id) {
- return __svcTimerCall(timer_id);
-}
-
-
-// Timer Thread
-__NO_RETURN void osTimerThread (void const *argument) {
- osCallback cb;
- osEvent evt;
-
- for (;;) {
- evt = osMessageGet(osMessageQId_osTimerMessageQ, osWaitForever);
- if (evt.status == osEventMessage) {
- cb = osTimerCall(evt.value.p);
- if (cb.fp != NULL) {
- (*(os_ptimer)cb.fp)(cb.arg);
- }
- }
- }
-}
-
-
-// ==== Signal Management ====
-
-// Signal Service Calls declarations
-SVC_2_1(svcSignalSet, int32_t, osThreadId, int32_t, RET_int32_t)
-SVC_2_1(svcSignalClear, int32_t, osThreadId, int32_t, RET_int32_t)
-SVC_2_3(svcSignalWait, os_InRegs osEvent, int32_t, uint32_t, RET_osEvent)
-
-// Signal Service Calls
-
-/// Set the specified Signal Flags of an active thread
-int32_t svcSignalSet (osThreadId thread_id, int32_t signals) {
- P_TCB ptcb;
- int32_t sig;
-
- ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer
- if (ptcb == NULL) {
- return (int32_t)0x80000000U;
- }
-
- if ((uint32_t)signals & (0xFFFFFFFFU << osFeature_Signals)) {
- return (int32_t)0x80000000U;
- }
-
- sig = (int32_t)ptcb->events; // Previous signal flags
-
- rt_evt_set((uint16_t)signals, ptcb->task_id); // Set event flags
-
- return sig;
-}
-
-/// Clear the specified Signal Flags of an active thread
-int32_t svcSignalClear (osThreadId thread_id, int32_t signals) {
- P_TCB ptcb;
- int32_t sig;
-
- ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer
- if (ptcb == NULL) {
- return (int32_t)0x80000000U;
- }
-
- if ((uint32_t)signals & (0xFFFFFFFFU << osFeature_Signals)) {
- return (int32_t)0x80000000U;
- }
-
- sig = (int32_t)ptcb->events; // Previous signal flags
-
- rt_evt_clr((uint16_t)signals, ptcb->task_id); // Clear event flags
-
- return sig;
-}
-
-/// Wait for one or more Signal Flags to become signaled for the current RUNNING thread
-os_InRegs osEvent_type svcSignalWait (int32_t signals, uint32_t millisec) {
- OS_RESULT res;
- osEvent ret;
-
- if ((uint32_t)signals & (0xFFFFFFFFU << osFeature_Signals)) {
- ret.status = osErrorValue;
- return osEvent_ret_status;
- }
-
- if (signals != 0) { // Wait for all specified signals
- res = rt_evt_wait((uint16_t)signals, rt_ms2tick(millisec), __TRUE);
- } else { // Wait for any signal
- res = rt_evt_wait(0xFFFFU, rt_ms2tick(millisec), __FALSE);
- }
-
- if (res == OS_R_EVT) {
- ret.status = osEventSignal;
- ret.value.signals = (signals != 0) ? signals : (int32_t)os_tsk.run->waits;
- } else {
- ret.status = (millisec != 0U) ? osEventTimeout : osOK;
- ret.value.signals = 0;
- }
-
- return osEvent_ret_value;
-}
-
-
-// Signal ISR Calls
-
-/// Set the specified Signal Flags of an active thread
-int32_t isrSignalSet (osThreadId thread_id, int32_t signals) {
- P_TCB ptcb;
- int32_t sig;
-
- ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer
- if (ptcb == NULL) {
- return (int32_t)0x80000000U;
- }
-
- if ((uint32_t)signals & (0xFFFFFFFFU << osFeature_Signals)) {
- return (int32_t)0x80000000U;
- }
-
- sig = (int32_t)ptcb->events; // Previous signal flags
-
- isr_evt_set((uint16_t)signals, ptcb->task_id);// Set event flags
-
- return sig;
-}
-
-
-// Signal Public API
-
-/// Set the specified Signal Flags of an active thread
-int32_t osSignalSet (osThreadId thread_id, int32_t signals) {
- if (__exceptional_mode()) { // in ISR
- return isrSignalSet(thread_id, signals);
- } else { // in Thread
- return __svcSignalSet(thread_id, signals);
- }
-}
-
-/// Clear the specified Signal Flags of an active thread
-int32_t osSignalClear (osThreadId thread_id, int32_t signals) {
- if (__exceptional_mode()) {
- return (int32_t)0x80000000U; // Not allowed in ISR
- }
- return __svcSignalClear(thread_id, signals);
-}
-
-/// Wait for one or more Signal Flags to become signaled for the current RUNNING thread
-os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec) {
- osEvent ret;
-
- if (__exceptional_mode()) { // Not allowed in ISR
- ret.status = osErrorISR;
- return ret;
- }
- return __svcSignalWait(signals, millisec);
-}
-
-
-// ==== Mutex Management ====
-
-// Mutex Service Calls declarations
-SVC_1_1(svcMutexCreate, osMutexId, const osMutexDef_t *, RET_pointer)
-SVC_2_1(svcMutexWait, osStatus, osMutexId, uint32_t, RET_osStatus)
-SVC_1_1(svcMutexRelease, osStatus, osMutexId, RET_osStatus)
-SVC_1_1(svcMutexDelete, osStatus, osMutexId, RET_osStatus)
-
-// Mutex Service Calls
-
-/// Create and Initialize a Mutex object
-osMutexId svcMutexCreate (const osMutexDef_t *mutex_def) {
- OS_ID mut;
-
- if (mutex_def == NULL) {
- sysThreadError(osErrorParameter);
- return NULL;
- }
-
- mut = mutex_def->mutex;
- if (mut == NULL) {
- sysThreadError(osErrorParameter);
- return NULL;
- }
-
- if (((P_MUCB)mut)->cb_type != 0U) {
- sysThreadError(osErrorParameter);
- return NULL;
- }
-
- rt_mut_init(mut); // Initialize Mutex
-
- return mut;
-}
-
-/// Wait until a Mutex becomes available
-osStatus svcMutexWait (osMutexId mutex_id, uint32_t millisec) {
- OS_ID mut;
- OS_RESULT res;
-
- mut = rt_id2obj(mutex_id);
- if (mut == NULL) {
- return osErrorParameter;
- }
-
- if (((P_MUCB)mut)->cb_type != MUCB) {
- return osErrorParameter;
- }
-
- res = rt_mut_wait(mut, rt_ms2tick(millisec)); // Wait for Mutex
-
- if (res == OS_R_TMO) {
- return ((millisec != 0U) ? osErrorTimeoutResource : osErrorResource);
- }
-
- return osOK;
-}
-
-/// Release a Mutex that was obtained with osMutexWait
-osStatus svcMutexRelease (osMutexId mutex_id) {
- OS_ID mut;
- OS_RESULT res;
-
- mut = rt_id2obj(mutex_id);
- if (mut == NULL) {
- return osErrorParameter;
- }
-
- if (((P_MUCB)mut)->cb_type != MUCB) {
- return osErrorParameter;
- }
-
- res = rt_mut_release(mut); // Release Mutex
-
- if (res == OS_R_NOK) {
- return osErrorResource; // Thread not owner or Zero Counter
- }
-
- return osOK;
-}
-
-/// Delete a Mutex that was created by osMutexCreate
-osStatus svcMutexDelete (osMutexId mutex_id) {
- OS_ID mut;
-
- mut = rt_id2obj(mutex_id);
- if (mut == NULL) {
- return osErrorParameter;
- }
-
- if (((P_MUCB)mut)->cb_type != MUCB) {
- return osErrorParameter;
- }
-
- rt_mut_delete(mut); // Release Mutex
-
- return osOK;
-}
-
-
-// Mutex Public API
-
-/// Create and Initialize a Mutex object
-osMutexId osMutexCreate (const osMutexDef_t *mutex_def) {
- if (__exceptional_mode()) {
- return NULL; // Not allowed in ISR
- }
- if ((__get_mode() != MODE_USR) && (os_running == 0U)) {
- // Privileged and not running
- return svcMutexCreate(mutex_def);
- } else {
- return __svcMutexCreate(mutex_def);
- }
-}
-
-/// Wait until a Mutex becomes available
-osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec) {
- if (__exceptional_mode()) {
- return osErrorISR; // Not allowed in ISR
- }
- return __svcMutexWait(mutex_id, millisec);
-}
-
-/// Release a Mutex that was obtained with osMutexWait
-osStatus osMutexRelease (osMutexId mutex_id) {
- if (__exceptional_mode()) {
- return osErrorISR; // Not allowed in ISR
- }
- return __svcMutexRelease(mutex_id);
-}
-
-/// Delete a Mutex that was created by osMutexCreate
-osStatus osMutexDelete (osMutexId mutex_id) {
- if (__exceptional_mode()) {
- return osErrorISR; // Not allowed in ISR
- }
- return __svcMutexDelete(mutex_id);
-}
-
-
-// ==== Semaphore Management ====
-
-// Semaphore Service Calls declarations
-SVC_2_1(svcSemaphoreCreate, osSemaphoreId, const osSemaphoreDef_t *, int32_t, RET_pointer)
-SVC_2_1(svcSemaphoreWait, int32_t, osSemaphoreId, uint32_t, RET_int32_t)
-SVC_1_1(svcSemaphoreRelease, osStatus, osSemaphoreId, RET_osStatus)
-SVC_1_1(svcSemaphoreDelete, osStatus, osSemaphoreId, RET_osStatus)
-
-// Semaphore Service Calls
-
-/// Create and Initialize a Semaphore object
-osSemaphoreId svcSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) {
- OS_ID sem;
-
- if (semaphore_def == NULL) {
- sysThreadError(osErrorParameter);
- return NULL;
- }
-
- sem = semaphore_def->semaphore;
- if (sem == NULL) {
- sysThreadError(osErrorParameter);
- return NULL;
- }
-
- if (((P_SCB)sem)->cb_type != 0U) {
- sysThreadError(osErrorParameter);
- return NULL;
- }
-
- if (count > osFeature_Semaphore) {
- sysThreadError(osErrorValue);
- return NULL;
- }
-
- rt_sem_init(sem, (uint16_t)count); // Initialize Semaphore
-
- return sem;
-}
-
-/// Wait until a Semaphore becomes available
-int32_t svcSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) {
- OS_ID sem;
- OS_RESULT res;
-
- sem = rt_id2obj(semaphore_id);
- if (sem == NULL) {
- return -1;
- }
-
- if (((P_SCB)sem)->cb_type != SCB) {
- return -1;
- }
-
- res = rt_sem_wait(sem, rt_ms2tick(millisec)); // Wait for Semaphore
-
- if (res == OS_R_TMO) { return 0; } // Timeout
-
- return (int32_t)(((P_SCB)sem)->tokens + 1U);
-}
-
-/// Release a Semaphore
-osStatus svcSemaphoreRelease (osSemaphoreId semaphore_id) {
- OS_ID sem;
-
- sem = rt_id2obj(semaphore_id);
- if (sem == NULL) {
- return osErrorParameter;
- }
-
- if (((P_SCB)sem)->cb_type != SCB) {
- return osErrorParameter;
- }
-
- if ((int32_t)((P_SCB)sem)->tokens == osFeature_Semaphore) {
- return osErrorResource;
- }
-
- rt_sem_send(sem); // Release Semaphore
-
- return osOK;
-}
-
-/// Delete a Semaphore that was created by osSemaphoreCreate
-osStatus svcSemaphoreDelete (osSemaphoreId semaphore_id) {
- OS_ID sem;
-
- sem = rt_id2obj(semaphore_id);
- if (sem == NULL) {
- return osErrorParameter;
- }
-
- if (((P_SCB)sem)->cb_type != SCB) {
- return osErrorParameter;
- }
-
- rt_sem_delete(sem); // Delete Semaphore
-
- return osOK;
-}
-
-
-// Semaphore ISR Calls
-
-/// Release a Semaphore
-osStatus isrSemaphoreRelease (osSemaphoreId semaphore_id) {
- OS_ID sem;
-
- sem = rt_id2obj(semaphore_id);
- if (sem == NULL) {
- return osErrorParameter;
- }
-
- if (((P_SCB)sem)->cb_type != SCB) {
- return osErrorParameter;
- }
-
- if ((int32_t)((P_SCB)sem)->tokens == osFeature_Semaphore) {
- return osErrorResource;
- }
-
- isr_sem_send(sem); // Release Semaphore
-
- return osOK;
-}
-
-
-// Semaphore Public API
-
-/// Create and Initialize a Semaphore object
-osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) {
- if (__exceptional_mode()) {
- return NULL; // Not allowed in ISR
- }
- if ((__get_mode() != MODE_USR) && (os_running == 0U)) {
- // Privileged and not running
- return svcSemaphoreCreate(semaphore_def, count);
- } else {
- return __svcSemaphoreCreate(semaphore_def, count);
- }
-}
-
-/// Wait until a Semaphore becomes available
-int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) {
- if (__exceptional_mode()) {
- return -1; // Not allowed in ISR
- }
- return __svcSemaphoreWait(semaphore_id, millisec);
-}
-
-/// Release a Semaphore
-osStatus osSemaphoreRelease (osSemaphoreId semaphore_id) {
- if (__exceptional_mode()) { // in ISR
- return isrSemaphoreRelease(semaphore_id);
- } else { // in Thread
- return __svcSemaphoreRelease(semaphore_id);
- }
-}
-
-/// Delete a Semaphore that was created by osSemaphoreCreate
-osStatus osSemaphoreDelete (osSemaphoreId semaphore_id) {
- if (__exceptional_mode()) {
- return osErrorISR; // Not allowed in ISR
- }
- return __svcSemaphoreDelete(semaphore_id);
-}
-
-
-// ==== Memory Management Functions ====
-
-// Memory Management Helper Functions
-
-// Clear Memory Box (Zero init)
-static void rt_clr_box (void *box_mem, void *box) {
- uint32_t *p, n;
-
- if ((box_mem != NULL) && (box != NULL)) {
- p = box;
- for (n = ((P_BM)box_mem)->blk_size; n; n -= 4U) {
- *p++ = 0U;
- }
- }
-}
-
-// Memory Management Service Calls declarations
-SVC_1_1(svcPoolCreate, osPoolId, const osPoolDef_t *, RET_pointer)
-SVC_1_1(sysPoolAlloc, void *, osPoolId, RET_pointer)
-SVC_2_1(sysPoolFree, osStatus, osPoolId, void *, RET_osStatus)
-
-// Memory Management Service & ISR Calls
-
-/// Create and Initialize memory pool
-osPoolId svcPoolCreate (const osPoolDef_t *pool_def) {
- uint32_t blk_sz;
-
- if ((pool_def == NULL) ||
- (pool_def->pool_sz == 0U) ||
- (pool_def->item_sz == 0U) ||
- (pool_def->pool == NULL)) {
- sysThreadError(osErrorParameter);
- return NULL;
- }
-
- blk_sz = (pool_def->item_sz + 3U) & (uint32_t)~3U;
-
- _init_box(pool_def->pool, sizeof(struct OS_BM) + (pool_def->pool_sz * blk_sz), blk_sz);
-
- return pool_def->pool;
-}
-
-/// Allocate a memory block from a memory pool
-void *sysPoolAlloc (osPoolId pool_id) {
- void *mem;
-
- if (pool_id == NULL) {
- return NULL;
- }
-
- mem = rt_alloc_box(pool_id);
-
- return mem;
-}
-
-/// Return an allocated memory block back to a specific memory pool
-osStatus sysPoolFree (osPoolId pool_id, void *block) {
- uint32_t res;
-
- if (pool_id == NULL) {
- return osErrorParameter;
- }
-
- res = rt_free_box(pool_id, block);
- if (res != 0) {
- return osErrorValue;
- }
-
- return osOK;
-}
-
-
-// Memory Management Public API
-
-/// Create and Initialize memory pool
-osPoolId osPoolCreate (const osPoolDef_t *pool_def) {
- if (__exceptional_mode()) {
- return NULL; // Not allowed in ISR
- }
- if ((__get_mode() != MODE_USR) && (os_running == 0U)) {
- // Privileged and not running
- return svcPoolCreate(pool_def);
- } else {
- return __svcPoolCreate(pool_def);
- }
-}
-
-/// Allocate a memory block from a memory pool
-void *osPoolAlloc (osPoolId pool_id) {
- if (__get_mode() != MODE_USR) { // in ISR or Privileged
- return sysPoolAlloc(pool_id);
- } else { // in Thread
- return __sysPoolAlloc(pool_id);
- }
-}
-
-/// Allocate a memory block from a memory pool and set memory block to zero
-void *osPoolCAlloc (osPoolId pool_id) {
- void *mem;
-
- if (__get_mode() != MODE_USR) { // in ISR or Privileged
- mem = sysPoolAlloc(pool_id);
- } else { // in Thread
- mem = __sysPoolAlloc(pool_id);
- }
-
- rt_clr_box(pool_id, mem);
-
- return mem;
-}
-
-/// Return an allocated memory block back to a specific memory pool
-osStatus osPoolFree (osPoolId pool_id, void *block) {
- if (__get_mode() != MODE_USR) { // in ISR or Privileged
- return sysPoolFree(pool_id, block);
- } else { // in Thread
- return __sysPoolFree(pool_id, block);
- }
-}
-
-
-// ==== Message Queue Management Functions ====
-
-// Message Queue Management Service Calls declarations
-SVC_2_1(svcMessageCreate, osMessageQId, const osMessageQDef_t *, osThreadId, RET_pointer)
-SVC_3_1(svcMessagePut, osStatus, osMessageQId, uint32_t, uint32_t, RET_osStatus)
-SVC_2_3(svcMessageGet, os_InRegs osEvent, osMessageQId, uint32_t, RET_osEvent)
-
-// Message Queue Service Calls
-
-/// Create and Initialize Message Queue
-osMessageQId svcMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) {
-
- if ((queue_def == NULL) ||
- (queue_def->queue_sz == 0U) ||
- (queue_def->pool == NULL)) {
- sysThreadError(osErrorParameter);
- return NULL;
- }
-
- if (((P_MCB)queue_def->pool)->cb_type != 0U) {
- sysThreadError(osErrorParameter);
- return NULL;
- }
-
- rt_mbx_init(queue_def->pool, (uint16_t)(4U*(queue_def->queue_sz + 4U)));
-
- return queue_def->pool;
-}
-
-/// Put a Message to a Queue
-osStatus svcMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {
- OS_RESULT res;
-
- if (queue_id == NULL) {
- return osErrorParameter;
- }
-
- if (((P_MCB)queue_id)->cb_type != MCB) {
- return osErrorParameter;
- }
-
- res = rt_mbx_send(queue_id, (void *)info, rt_ms2tick(millisec));
-
- if (res == OS_R_TMO) {
- return ((millisec != 0U) ? osErrorTimeoutResource : osErrorResource);
- }
-
- return osOK;
-}
-
-/// Get a Message or Wait for a Message from a Queue
-os_InRegs osEvent_type svcMessageGet (osMessageQId queue_id, uint32_t millisec) {
- OS_RESULT res;
- osEvent ret;
-
- if (queue_id == NULL) {
- ret.status = osErrorParameter;
- return osEvent_ret_status;
- }
-
- if (((P_MCB)queue_id)->cb_type != MCB) {
- ret.status = osErrorParameter;
- return osEvent_ret_status;
- }
-
- res = rt_mbx_wait(queue_id, &ret.value.p, rt_ms2tick(millisec));
-
- if (res == OS_R_TMO) {
- ret.status = (millisec != 0U) ? osEventTimeout : osOK;
- return osEvent_ret_value;
- }
-
- ret.status = osEventMessage;
-
- return osEvent_ret_value;
-}
-
-
-// Message Queue ISR Calls
-
-/// Put a Message to a Queue
-osStatus isrMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {
-
- if ((queue_id == NULL) || (millisec != 0U)) {
- return osErrorParameter;
- }
-
- if (((P_MCB)queue_id)->cb_type != MCB) {
- return osErrorParameter;
- }
-
- if (rt_mbx_check(queue_id) == 0U) { // Check if Queue is full
- return osErrorResource;
- }
-
- isr_mbx_send(queue_id, (void *)info);
-
- return osOK;
-}
-
-/// Get a Message or Wait for a Message from a Queue
-os_InRegs osEvent isrMessageGet (osMessageQId queue_id, uint32_t millisec) {
- OS_RESULT res;
- osEvent ret;
-
- if ((queue_id == NULL) || (millisec != 0U)) {
- ret.status = osErrorParameter;
- return ret;
- }
-
- if (((P_MCB)queue_id)->cb_type != MCB) {
- ret.status = osErrorParameter;
- return ret;
- }
-
- res = isr_mbx_receive(queue_id, &ret.value.p);
-
- if (res != OS_R_MBX) {
- ret.status = osOK;
- return ret;
- }
-
- ret.status = osEventMessage;
-
- return ret;
-}
-
-
-// Message Queue Management Public API
-
-/// Create and Initialize Message Queue
-osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) {
- if (__exceptional_mode()) {
- return NULL; // Not allowed in ISR
- }
- if ((__get_mode() != MODE_USR) && (os_running == 0U)) {
- // Privileged and not running
- return svcMessageCreate(queue_def, thread_id);
- } else {
- return __svcMessageCreate(queue_def, thread_id);
- }
-}
-
-/// Put a Message to a Queue
-osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {
- if (__exceptional_mode()) { // in ISR
- return isrMessagePut(queue_id, info, millisec);
- } else { // in Thread
- return __svcMessagePut(queue_id, info, millisec);
- }
-}
-
-/// Get a Message or Wait for a Message from a Queue
-os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) {
- if (__exceptional_mode()) { // in ISR
- return isrMessageGet(queue_id, millisec);
- } else { // in Thread
- return __svcMessageGet(queue_id, millisec);
- }
-}
-
-
-// ==== Mail Queue Management Functions ====
-
-// Mail Queue Management Service Calls declarations
-SVC_2_1(svcMailCreate, osMailQId, const osMailQDef_t *, osThreadId, RET_pointer)
-SVC_3_1(sysMailAlloc, void *, osMailQId, uint32_t, uint32_t, RET_pointer)
-SVC_3_1(sysMailFree, osStatus, osMailQId, void *, uint32_t, RET_osStatus)
-
-// Mail Queue Management Service & ISR Calls
-
-/// Create and Initialize mail queue
-osMailQId svcMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) {
- uint32_t blk_sz;
- P_MCB pmcb;
- void *pool;
-
- if ((queue_def == NULL) ||
- (queue_def->queue_sz == 0U) ||
- (queue_def->item_sz == 0U) ||
- (queue_def->pool == NULL)) {
- sysThreadError(osErrorParameter);
- return NULL;
- }
-
- pmcb = *(((void **)queue_def->pool) + 0);
- pool = *(((void **)queue_def->pool) + 1);
-
- if ((pool == NULL) || (pmcb == NULL) || (pmcb->cb_type != 0U)) {
- sysThreadError(osErrorParameter);
- return NULL;
- }
-
- blk_sz = (queue_def->item_sz + 3U) & (uint32_t)~3U;
-
- _init_box(pool, sizeof(struct OS_BM) + (queue_def->queue_sz * blk_sz), blk_sz);
-
- rt_mbx_init(pmcb, (uint16_t)(4U*(queue_def->queue_sz + 4U)));
-
- return queue_def->pool;
-}
-
-/// Allocate a memory block from a mail
-void *sysMailAlloc (osMailQId queue_id, uint32_t millisec, uint32_t isr) {
- P_MCB pmcb;
- void *pool;
- void *mem;
-
- if (queue_id == NULL) {
- return NULL;
- }
-
- pmcb = *(((void **)queue_id) + 0);
- pool = *(((void **)queue_id) + 1);
-
- if ((pool == NULL) || (pmcb == NULL)) {
- return NULL;
- }
-
- if ((isr != 0U) && (millisec != 0U)) {
- return NULL;
- }
-
- mem = rt_alloc_box(pool);
-
- if ((mem == NULL) && (millisec != 0U)) {
- // Put Task to sleep when Memory not available
- if (pmcb->p_lnk != NULL) {
- rt_put_prio((P_XCB)pmcb, os_tsk.run);
- } else {
- pmcb->p_lnk = os_tsk.run;
- os_tsk.run->p_lnk = NULL;
- os_tsk.run->p_rlnk = (P_TCB)pmcb;
- // Task is waiting to allocate a message
- pmcb->state = 3U;
- }
- rt_block(rt_ms2tick(millisec), WAIT_MBX);
- }
-
- return mem;
-}
-
-/// Free a memory block from a mail
-osStatus sysMailFree (osMailQId queue_id, void *mail, uint32_t isr) {
- P_MCB pmcb;
- P_TCB ptcb;
- void *pool;
- void *mem;
- uint32_t res;
-
- if (queue_id == NULL) {
- return osErrorParameter;
- }
-
- pmcb = *(((void **)queue_id) + 0);
- pool = *(((void **)queue_id) + 1);
-
- if ((pmcb == NULL) || (pool == NULL)) {
- return osErrorParameter;
- }
-
- res = rt_free_box(pool, mail);
-
- if (res != 0U) {
- return osErrorValue;
- }
-
- if ((pmcb->p_lnk != NULL) && (pmcb->state == 3U)) {
- // Task is waiting to allocate a message
- if (isr != 0U) {
- rt_psq_enq (pmcb, (U32)pool);
- rt_psh_req ();
- } else {
- mem = rt_alloc_box(pool);
- if (mem != NULL) {
- ptcb = rt_get_first((P_XCB)pmcb);
- rt_ret_val(ptcb, (U32)mem);
- rt_rmv_dly(ptcb);
- rt_dispatch(ptcb);
- }
- }
- }
-
- return osOK;
-}
-
-
-// Mail Queue Management Public API
-
-/// Create and Initialize mail queue
-osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) {
- if (__exceptional_mode()) {
- return NULL; // Not allowed in ISR
- }
- if ((__get_mode() != MODE_USR) && (os_running == 0U)) {
- // Privileged and not running
- return svcMailCreate(queue_def, thread_id);
- } else {
- return __svcMailCreate(queue_def, thread_id);
- }
-}
-
-/// Allocate a memory block from a mail
-void *osMailAlloc (osMailQId queue_id, uint32_t millisec) {
- if (__exceptional_mode()) { // in ISR
- return sysMailAlloc(queue_id, millisec, 1U);
- } else { // in Thread
- return __sysMailAlloc(queue_id, millisec, 0U);
- }
-}
-
-/// Allocate a memory block from a mail and set memory block to zero
-void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) {
- void *pool;
- void *mem;
-
- if (__exceptional_mode()) { // in ISR
- mem = sysMailAlloc(queue_id, millisec, 1U);
- } else { // in Thread
- mem = __sysMailAlloc(queue_id, millisec, 0U);
- }
-
- pool = *(((void **)queue_id) + 1);
-
- rt_clr_box(pool, mem);
-
- return mem;
-}
-
-/// Free a memory block from a mail
-osStatus osMailFree (osMailQId queue_id, void *mail) {
- if (__exceptional_mode()) { // in ISR
- return sysMailFree(queue_id, mail, 1U);
- } else { // in Thread
- return __sysMailFree(queue_id, mail, 0U);
- }
-}
-
-/// Put a mail to a queue
-osStatus osMailPut (osMailQId queue_id, void *mail) {
- if (queue_id == NULL) {
- return osErrorParameter;
- }
- if (mail == NULL) {
- return osErrorValue;
- }
- return osMessagePut(*((void **)queue_id), (uint32_t)mail, 0U);
-}
-
-#ifdef __CC_ARM
-#pragma push
-#pragma Ospace
-#endif // __arm__
-/// Get a mail from a queue
-os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) {
- osEvent ret;
-
- if (queue_id == NULL) {
- ret.status = osErrorParameter;
- return ret;
- }
-
- ret = osMessageGet(*((void **)queue_id), millisec);
- if (ret.status == osEventMessage) ret.status = osEventMail;
-
- return ret;
-}
-#ifdef __CC_ARM
-#pragma pop
-#endif // __arm__
-
-
-// ==== RTX Extensions ====
-
-// Service Calls declarations
-SVC_0_1(rt_suspend, uint32_t, RET_uint32_t)
-SVC_1_0(rt_resume, void, uint32_t)
-
-
-// Public API
-
-/// Suspends the OS task scheduler
-uint32_t os_suspend (void) {
- return __rt_suspend();
-}
-
-/// Resumes the OS task scheduler
-void os_resume (uint32_t sleep_time) {
- __rt_resume(sleep_time);
-}
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_Event.c b/rtos/rtx/TARGET_CORTEX_A/rt_Event.c
deleted file mode 100644
index e1a55410ce..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_Event.c
+++ /dev/null
@@ -1,194 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_EVENT.C
- * Purpose: Implements waits and wake-ups for event flags
- * Rev.: V4.79
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-#include "rt_TypeDef.h"
-#include "RTX_Config.h"
-#include "rt_System.h"
-#include "rt_Event.h"
-#include "rt_List.h"
-#include "rt_Task.h"
-#ifdef __CORTEX_A9
-#include "rt_HAL_CA.h"
-#else
-#include "rt_HAL_CM.h"
-#endif
-
-
-/*----------------------------------------------------------------------------
- * Functions
- *---------------------------------------------------------------------------*/
-
-
-/*--------------------------- rt_evt_wait -----------------------------------*/
-
-OS_RESULT rt_evt_wait (U16 wait_flags, U16 timeout, BOOL and_wait) {
- /* Wait for one or more event flags with optional time-out. */
- /* "wait_flags" identifies the flags to wait for. */
- /* "timeout" is the time-out limit in system ticks (0xffff if no time-out) */
- /* "and_wait" specifies the AND-ing of "wait_flags" as condition to be met */
- /* to complete the wait. (OR-ing if set to 0). */
- U32 block_state;
-
- if (and_wait) {
- /* Check for AND-connected events */
- if ((os_tsk.run->events & wait_flags) == wait_flags) {
- os_tsk.run->events &= ~wait_flags;
- return (OS_R_EVT);
- }
- block_state = WAIT_AND;
- }
- else {
- /* Check for OR-connected events */
- if (os_tsk.run->events & wait_flags) {
- os_tsk.run->waits = os_tsk.run->events & wait_flags;
- os_tsk.run->events &= ~wait_flags;
- return (OS_R_EVT);
- }
- block_state = WAIT_OR;
- }
- /* Task has to wait */
- os_tsk.run->waits = wait_flags;
- rt_block (timeout, (U8)block_state);
- return (OS_R_TMO);
-}
-
-
-/*--------------------------- rt_evt_set ------------------------------------*/
-
-void rt_evt_set (U16 event_flags, OS_TID task_id) {
- /* Set one or more event flags of a selectable task. */
- P_TCB p_tcb;
-
- p_tcb = os_active_TCB[task_id-1U];
- if (p_tcb == NULL) {
- return;
- }
- p_tcb->events |= event_flags;
- event_flags = p_tcb->waits;
- /* If the task is not waiting for an event, it should not be put */
- /* to ready state. */
- if (p_tcb->state == WAIT_AND) {
- /* Check for AND-connected events */
- if ((p_tcb->events & event_flags) == event_flags) {
- goto wkup;
- }
- }
- if (p_tcb->state == WAIT_OR) {
- /* Check for OR-connected events */
- if (p_tcb->events & event_flags) {
- p_tcb->waits &= p_tcb->events;
-wkup: p_tcb->events &= ~event_flags;
- rt_rmv_dly (p_tcb);
- p_tcb->state = READY;
-#ifdef __CMSIS_RTOS
- rt_ret_val2(p_tcb, 0x08U/*osEventSignal*/, p_tcb->waits);
-#else
- rt_ret_val (p_tcb, OS_R_EVT);
-#endif
- rt_dispatch (p_tcb);
- }
- }
-}
-
-
-/*--------------------------- rt_evt_clr ------------------------------------*/
-
-void rt_evt_clr (U16 clear_flags, OS_TID task_id) {
- /* Clear one or more event flags (identified by "clear_flags") of a */
- /* selectable task (identified by "task"). */
- P_TCB task = os_active_TCB[task_id-1U];
-
- if (task == NULL) {
- return;
- }
- task->events &= ~clear_flags;
-}
-
-
-/*--------------------------- isr_evt_set -----------------------------------*/
-
-void isr_evt_set (U16 event_flags, OS_TID task_id) {
- /* Same function as "os_evt_set", but to be called by ISRs. */
- P_TCB p_tcb = os_active_TCB[task_id-1U];
-
- if (p_tcb == NULL) {
- return;
- }
- rt_psq_enq (p_tcb, event_flags);
- rt_psh_req ();
-}
-
-
-/*--------------------------- rt_evt_get ------------------------------------*/
-
-U16 rt_evt_get (void) {
- /* Get events of a running task after waiting for OR connected events. */
- return (os_tsk.run->waits);
-}
-
-
-/*--------------------------- rt_evt_psh ------------------------------------*/
-
-void rt_evt_psh (P_TCB p_CB, U16 set_flags) {
- /* Check if task has to be waken up */
- U16 event_flags;
-
- p_CB->events |= set_flags;
- event_flags = p_CB->waits;
- if (p_CB->state == WAIT_AND) {
- /* Check for AND-connected events */
- if ((p_CB->events & event_flags) == event_flags) {
- goto rdy;
- }
- }
- if (p_CB->state == WAIT_OR) {
- /* Check for OR-connected events */
- if (p_CB->events & event_flags) {
- p_CB->waits &= p_CB->events;
-rdy: p_CB->events &= ~event_flags;
- rt_rmv_dly (p_CB);
- p_CB->state = READY;
-#ifdef __CMSIS_RTOS
- rt_ret_val2(p_CB, 0x08U/*osEventSignal*/, p_CB->waits);
-#else
- rt_ret_val (p_CB, OS_R_EVT);
-#endif
- rt_put_prio (&os_rdy, p_CB);
- }
- }
-}
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_Event.h b/rtos/rtx/TARGET_CORTEX_A/rt_Event.h
deleted file mode 100644
index b3c4e597bd..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_Event.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_EVENT.H
- * Purpose: Implements waits and wake-ups for event flags
- * Rev.: V4.70
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-/* Functions */
-extern OS_RESULT rt_evt_wait (U16 wait_flags, U16 timeout, BOOL and_wait);
-extern void rt_evt_set (U16 event_flags, OS_TID task_id);
-extern void rt_evt_clr (U16 clear_flags, OS_TID task_id);
-extern void isr_evt_set (U16 event_flags, OS_TID task_id);
-extern U16 rt_evt_get (void);
-extern void rt_evt_psh (P_TCB p_CB, U16 set_flags);
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h b/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h
deleted file mode 100644
index a517666262..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h
+++ /dev/null
@@ -1,251 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_HAL_CA.H
- * Purpose: Hardware Abstraction Layer for Cortex-A definitions
- * Rev.: V4.79 plus changes for RTX-Ax
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH, 2012-2016 ARM Limited
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-/* Definitions */
-#define INIT_CPSR_SYS 0x4000001F
-#define INIT_CPSR_USER 0x40000010
-
-#define CPSR_T_BIT 0x20
-#define CPSR_I_BIT 0x80
-#define CPSR_F_BIT 0x40
-
-#define MODE_USR 0x10
-#define MODE_FIQ 0x11
-#define MODE_IRQ 0x12
-#define MODE_SVC 0x13
-#define MODE_ABT 0x17
-#define MODE_UND 0x1B
-#define MODE_SYS 0x1F
-
-#define MAGIC_WORD 0xE25A2EA5
-#define MAGIC_PATTERN 0xCCCCCCCC
-
-#include "core_ca9.h"
-
-#if defined (__CC_ARM) /* ARM Compiler */
-
-#if ((defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M) || defined(__TARGET_ARCH_7_A)) && !defined(NO_EXCLUSIVE_ACCESS))
- #define __USE_EXCLUSIVE_ACCESS
-#else
- #undef __USE_EXCLUSIVE_ACCESS
-#endif
-
-/* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */
-#ifdef __USE_EXCLUSIVE_ACCESS
-#pragma diag_suppress 3731
-#endif
-
-#elif defined (__GNUC__) /* GNU Compiler */
-
-#undef __USE_EXCLUSIVE_ACCESS
-
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#define __TARGET_FPU_VFP 1
-#else
-#define __TARGET_FPU_VFP 0
-#endif
-
-#define __inline inline
-#define __weak __attribute__((weak))
-
-#elif defined (__ICCARM__) /* IAR Compiler */
-
-//#error IAR Compiler support not implemented for Cortex-A
-
-#endif
-
-static U8 priority = 0xffU;
-
-extern const U32 GICDistributor_BASE;
-extern const U32 GICInterface_BASE;
-
-/* GIC registers - Distributor */
-#define GICD_ICDICER0 (*((volatile U32 *)(GICDistributor_BASE + 0x180))) /* - RW - Interrupt Clear-Enable Registers */
-#define GICD_ICDISER0 (*((volatile U32 *)(GICDistributor_BASE + 0x100))) /* - RW - Interrupt Set-Enable Registers */
-#define GICD_ICDIPR0 (*((volatile U32 *)(GICDistributor_BASE + 0x400))) /* - RW - Interrupt Priority Registers */
-#define GICD_ICDSGIR (*((volatile U32 *)(GICDistributor_BASE + 0xf00))) /* - RW - Interrupt Software Interrupt Register */
-#define GICD_ICDICERx(irq) *(volatile U32 *)(&GICD_ICDICER0 + irq/32)
-#define GICD_ICDISERx(irq) *(volatile U32 *)(&GICD_ICDISER0 + irq/32)
-
-/* GIC register - CPU Interface */
-#define GICI_ICCPMR (*((volatile U32 *)(GICInterface_BASE + 0x004))) /* - RW - Interrupt Priority Mask Register */
-
-#define SGI_PENDSV 0U /* SGI0 */
-#define SGI_PENDSV_BIT ((U32)(1U << (SGI_PENDSV & 0xfU)))
-
-//Increase priority filter to prevent timer and PendSV interrupts signaling. Guarantees that interrupts will not be forwarded.
-#if defined (__ICCARM__)
-#define OS_LOCK() int irq_dis = __disable_irq_iar();\
- priority = GICI_ICCPMR; \
- GICI_ICCPMR = 0xff; \
- GICI_ICCPMR = GICI_ICCPMR - 1; \
- __DSB();\
- if(!irq_dis) __enable_irq(); \
-
-#else
-#define OS_LOCK() int irq_dis = __disable_irq();\
- priority = GICI_ICCPMR; \
- GICI_ICCPMR = 0xff; \
- GICI_ICCPMR = GICI_ICCPMR - 1; \
- __DSB();\
- if(!irq_dis) __enable_irq(); \
-
-#endif
-
-//Restore priority filter. Re-enable timer and PendSV signaling
-#define OS_UNLOCK() __DSB(); \
- GICI_ICCPMR = priority; \
-
-#define OS_PEND_IRQ() GICD_ICDSGIR = 0x0010000 | SGI_PENDSV
-#define OS_PEND(fl,p) if(p) OS_PEND_IRQ();
-#define OS_UNPEND(fl)
-
-/* HW initialization needs to be done in os_tick_init() in RTX_Conf_CM.c
- * OS_X_INIT enables the IRQ n in the GIC */
-#define OS_X_INIT(n) volatile char *reg; \
- reg = (char *)(&GICD_ICDIPR0 + n / 4); \
- reg += n % 4; \
- *reg = (char)0xff; \
- *reg = *reg - 1; \
- GICD_ICDISERx(n) = (U32)(1U << n % 32);
-#define OS_X_LOCK(n) OS_LOCK()
-#define OS_X_UNLOCK(n) OS_UNLOCK()
-#define OS_X_PEND_IRQ() OS_PEND_IRQ()
-#define OS_X_PEND(fl,p) if(p) OS_X_PEND_IRQ();
-#define OS_X_UNPEND(fl)
-
-
-/* Functions */
-#ifdef __USE_EXCLUSIVE_ACCESS
- #define rt_inc(p) while(__strex((__ldrex(p)+1U),p))
- #define rt_dec(p) while(__strex((__ldrex(p)-1U),p))
-#else
-#if defined (__ICCARM__)
- #define rt_inc(p) { int irq_dis = __disable_irq_iar();(*p)++;if(!irq_dis) __enable_irq(); }
- #define rt_dec(p) { int irq_dis = __disable_irq_iar();(*p)--;if(!irq_dis) __enable_irq(); }
-#else
- #define rt_inc(p) { int irq_dis = __disable_irq();(*p)++;if(!irq_dis) __enable_irq(); }
- #define rt_dec(p) { int irq_dis = __disable_irq();(*p)--;if(!irq_dis) __enable_irq(); }
-#endif /* __ICCARM__ */
-#endif /* __USE_EXCLUSIVE_ACCESS */
-
-__inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
- U32 cnt,c2;
-#ifdef __USE_EXCLUSIVE_ACCESS
- do {
- if ((cnt = __ldrex(count)) == size) {
- __clrex();
- return (cnt); }
- } while (__strex(cnt+1U, count));
- do {
- c2 = (cnt = __ldrex(first)) + 1U;
- if (c2 == size) { c2 = 0U; }
- } while (__strex(c2, first));
-#else
- int irq_dis;
- #if defined (__ICCARM__)
- irq_dis = __disable_irq_iar();
- #else
- irq_dis = __disable_irq();
- #endif /* __ICCARM__ */
- if ((cnt = *count) < size) {
- *count = (U8)(cnt+1U);
- c2 = (cnt = *first) + 1U;
- if (c2 == size) { c2 = 0U; }
- *first = (U8)c2;
- }
- if(!irq_dis) __enable_irq ();
-#endif
- return (cnt);
-}
-
-__inline static void rt_systick_init (void) {
- /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
- /* HW initialization needs to be done in os_tick_init() in RTX_Conf_CM.c */
-}
-
-__inline static U32 rt_systick_val (void) {
- /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
- /* HW initialization needs to be done in os_tick_init() in RTX_Conf_CM.c */
- return 0U;
-}
-
-__inline static U32 rt_systick_ovf (void) {
- /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
- /* HW initialization needs to be done in os_tick_init() in RTX_Conf_CM.c */
- return 0U;
-}
-
-__inline static void rt_svc_init (void) {
- /* Register pendSV - through SGI */
- volatile char *reg;
-
- reg = (char *)(&GICD_ICDIPR0 + SGI_PENDSV/4);
- reg += SGI_PENDSV % 4U;
- /* Write 0xff to read priority level */
- *reg = (char)0xff;
- /* Read priority level and set the lowest possible*/
- *reg = *reg - 1;
-
- GICD_ICDISERx(SGI_PENDSV) = (U32)SGI_PENDSV_BIT;
-}
-
-extern void rt_set_PSP (U32 stack);
-extern U32 rt_get_PSP (void);
-extern void os_set_env (P_TCB p_TCB);
-extern void *_alloc_box (void *box_mem);
-extern U32 _free_box (void *box_mem, void *box);
-
-extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
-extern void rt_ret_val (P_TCB p_TCB, U32 v0);
-extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
-
-extern void dbg_init (void);
-extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
-extern void dbg_task_switch (U32 task_id);
-
-#ifdef DBG_MSG
-#define DBG_INIT() dbg_init()
-#define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
-#define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new!=os_tsk.run)) \
- dbg_task_switch(task_id)
-#else
-#define DBG_INIT()
-#define DBG_TASK_NOTIFY(p_tcb,create)
-#define DBG_TASK_SWITCH(task_id)
-#endif
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CM.h b/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CM.h
deleted file mode 100644
index e3aefae22d..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CM.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_HAL_CM.H
- * Purpose: Hardware Abstraction Layer for Cortex-M definitions
- * Rev.: V4.79
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-/* Definitions */
-#define INITIAL_xPSR 0x01000000U
-#define DEMCR_TRCENA 0x01000000U
-#define ITM_ITMENA 0x00000001U
-#define MAGIC_WORD 0xE25A2EA5U
-#define MAGIC_PATTERN 0xCCCCCCCCU
-
-#if defined (__CC_ARM) /* ARM Compiler */
-
-#if ((defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) && !defined(NO_EXCLUSIVE_ACCESS))
- #define __USE_EXCLUSIVE_ACCESS
-#else
- #undef __USE_EXCLUSIVE_ACCESS
-#endif
-
-/* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */
-#ifdef __USE_EXCLUSIVE_ACCESS
-#pragma diag_suppress 3731
-#endif
-
-#ifndef __CMSIS_GENERIC
-#define __DMB() do {\
- __schedule_barrier();\
- __dmb(0xF);\
- __schedule_barrier();\
- } while (0)
-#endif
-
-#elif defined (__GNUC__) /* GNU Compiler */
-
-#undef __USE_EXCLUSIVE_ACCESS
-
-#if defined (__CORTEX_M0)
-#define __TARGET_ARCH_6S_M
-#endif
-
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#define __TARGET_FPU_VFP
-#endif
-
-#define __inline inline
-#define __weak __attribute__((weak))
-
-#ifndef __CMSIS_GENERIC
-
-__attribute__((always_inline)) static inline void __enable_irq(void)
-{
- __asm volatile ("cpsie i");
-}
-
-__attribute__((always_inline)) static inline U32 __disable_irq(void)
-{
- U32 result;
-
- __asm volatile ("mrs %0, primask" : "=r" (result));
- __asm volatile ("cpsid i");
- return(result & 1);
-}
-
-__attribute__((always_inline)) static inline void __DMB(void)
-{
- __asm volatile ("dmb 0xF":::"memory");
-}
-
-#endif
-
-__attribute__(( always_inline)) static inline U8 __clz(U32 value)
-{
- U8 result;
-
- __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
- return(result);
-}
-
-#elif defined (__ICCARM__) /* IAR Compiler */
-
-#undef __USE_EXCLUSIVE_ACCESS
-
-#if (__CORE__ == __ARM6M__)
-#define __TARGET_ARCH_6S_M 1
-#endif
-
-#if defined __ARMVFP__
-#define __TARGET_FPU_VFP 1
-#endif
-
-#define __inline inline
-
-#ifndef __CMSIS_GENERIC
-
-static inline void __enable_irq(void)
-{
- __asm volatile ("cpsie i");
-}
-
-static inline U32 __disable_irq(void)
-{
- U32 result;
-
- __asm volatile ("mrs %0, primask" : "=r" (result));
- __asm volatile ("cpsid i");
- return(result & 1);
-}
-
-#endif
-
-static inline U8 __clz(U32 value)
-{
- U8 result;
-
- __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
- return(result);
-}
-
-#endif
-
-/* NVIC registers */
-#define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010U))
-#define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014U))
-#define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018U))
-#define NVIC_ISER ((volatile U32 *)0xE000E100U)
-#define NVIC_ICER ((volatile U32 *)0xE000E180U)
-#if defined(__TARGET_ARCH_6S_M)
-#define NVIC_IP ((volatile U32 *)0xE000E400U)
-#else
-#define NVIC_IP ((volatile U8 *)0xE000E400U)
-#endif
-#define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04U))
-#define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0CU))
-#define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1CU))
-#define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20U))
-
-#define OS_PEND_IRQ() NVIC_INT_CTRL = (1UL<<28)
-#define OS_PENDING ((NVIC_INT_CTRL >> 26) & 5U)
-#define OS_UNPEND(fl) NVIC_INT_CTRL = (U32)(fl = (U8)OS_PENDING) << 25
-#define OS_PEND(fl,p) NVIC_INT_CTRL = (U32)(fl | (U8)(p<<2)) << 26
-#define OS_LOCK() NVIC_ST_CTRL = 0x0005U
-#define OS_UNLOCK() NVIC_ST_CTRL = 0x0007U
-
-#define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1U)
-#define OS_X_UNPEND(fl) NVIC_INT_CTRL = (U32)(fl = (U8)OS_X_PENDING) << 27
-#define OS_X_PEND(fl,p) NVIC_INT_CTRL = (U32)(fl | p) << 28
-#if defined(__TARGET_ARCH_6S_M)
-#define OS_X_INIT(n) NVIC_IP[n>>2] |= (U32)0xFFU << ((n & 0x03U) << 3); \
- NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU)
-#else
-#define OS_X_INIT(n) NVIC_IP[n] = 0xFFU; \
- NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU)
-#endif
-#define OS_X_LOCK(n) NVIC_ICER[n>>5] = (U32)1U << (n & 0x1FU)
-#define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU)
-
-/* Core Debug registers */
-#define DEMCR (*((volatile U32 *)0xE000EDFCU))
-
-/* ITM registers */
-#define ITM_CONTROL (*((volatile U32 *)0xE0000E80U))
-#define ITM_ENABLE (*((volatile U32 *)0xE0000E00U))
-#define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078U))
-#define ITM_PORT31_U32 (*((volatile U32 *)0xE000007CU))
-#define ITM_PORT31_U16 (*((volatile U16 *)0xE000007CU))
-#define ITM_PORT31_U8 (*((volatile U8 *)0xE000007CU))
-
-/* Variables */
-extern BIT dbg_msg;
-
-/* Functions */
-#ifdef __USE_EXCLUSIVE_ACCESS
- #define rt_inc(p) while(__strex((__ldrex(p)+1U),p))
- #define rt_dec(p) while(__strex((__ldrex(p)-1U),p))
-#else
- #define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
- #define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
-#endif
-
-__inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
- U32 cnt,c2;
-#ifdef __USE_EXCLUSIVE_ACCESS
- do {
- if ((cnt = __ldrex(count)) == size) {
- __clrex();
- return (cnt); }
- } while (__strex(cnt+1U, count));
- do {
- c2 = (cnt = __ldrex(first)) + 1U;
- if (c2 == size) { c2 = 0U; }
- } while (__strex(c2, first));
-#else
- __disable_irq();
- if ((cnt = *count) < size) {
- *count = (U8)(cnt+1U);
- c2 = (cnt = *first) + 1U;
- if (c2 == size) { c2 = 0U; }
- *first = (U8)c2;
- }
- __enable_irq ();
-#endif
- return (cnt);
-}
-
-__inline static void rt_systick_init (void) {
- NVIC_ST_RELOAD = os_trv;
- NVIC_ST_CURRENT = 0U;
- NVIC_ST_CTRL = 0x0007U;
- NVIC_SYS_PRI3 |= 0xFF000000U;
-}
-
-__inline static U32 rt_systick_val (void) {
- return (os_trv - NVIC_ST_CURRENT);
-}
-
-__inline static U32 rt_systick_ovf (void) {
- return ((NVIC_INT_CTRL >> 26) & 1U);
-}
-
-__inline static void rt_svc_init (void) {
-#if !defined(__TARGET_ARCH_6S_M)
- U32 sh,prigroup;
-#endif
- NVIC_SYS_PRI3 |= 0x00FF0000U;
-#if defined(__TARGET_ARCH_6S_M)
- NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000U;
-#else
- sh = 8U - __clz(~((NVIC_SYS_PRI3 << 8) & 0xFF000000U));
- prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07U);
- if (prigroup >= sh) {
- sh = prigroup + 1U;
- }
-
-/* Only change the SVCall priority if uVisor is not present. */
-#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
- NVIC_SYS_PRI2 = ((0xFEFFFFFFU << sh) & 0xFF000000U) | (NVIC_SYS_PRI2 & 0x00FFFFFFU);
-#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */
-#endif
-}
-
-extern void rt_set_PSP (U32 stack);
-extern U32 rt_get_PSP (void);
-extern void os_set_env (void);
-extern void *_alloc_box (void *box_mem);
-extern U32 _free_box (void *box_mem, void *box);
-
-extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
-extern void rt_ret_val (P_TCB p_TCB, U32 v0);
-extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
-
-extern void dbg_init (void);
-extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
-extern void dbg_task_switch (U32 task_id);
-
-#ifdef DBG_MSG
-#define DBG_INIT() dbg_init()
-#define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
-#define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk!=os_tsk.run)) \
- dbg_task_switch(task_id)
-#else
-#define DBG_INIT()
-#define DBG_TASK_NOTIFY(p_tcb,create)
-#define DBG_TASK_SWITCH(task_id)
-#endif
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_List.c b/rtos/rtx/TARGET_CORTEX_A/rt_List.c
deleted file mode 100644
index 0868b6cc6b..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_List.c
+++ /dev/null
@@ -1,322 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_LIST.C
- * Purpose: Functions for the management of different lists
- * Rev.: V4.79
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-#include "rt_TypeDef.h"
-#include "RTX_Config.h"
-#include "rt_System.h"
-#include "rt_List.h"
-#include "rt_Task.h"
-#include "rt_Time.h"
-#ifdef __CORTEX_A9
-#include "rt_HAL_CA.h"
-#else
-#include "rt_HAL_CM.h"
-#endif
-
-/*----------------------------------------------------------------------------
- * Global Variables
- *---------------------------------------------------------------------------*/
-
-/* List head of chained ready tasks */
-struct OS_XCB os_rdy;
-/* List head of chained delay tasks */
-struct OS_XCB os_dly;
-
-
-/*----------------------------------------------------------------------------
- * Functions
- *---------------------------------------------------------------------------*/
-
-
-/*--------------------------- rt_put_prio -----------------------------------*/
-
-void rt_put_prio (P_XCB p_CB, P_TCB p_task) {
- /* Put task identified with "p_task" into list ordered by priority. */
- /* "p_CB" points to head of list; list has always an element at end with */
- /* a priority less than "p_task->prio". */
- P_TCB p_CB2;
- U32 prio;
- BOOL sem_mbx = __FALSE;
-
- if ((p_CB->cb_type == SCB) || (p_CB->cb_type == MCB) || (p_CB->cb_type == MUCB)) {
- sem_mbx = __TRUE;
- }
- prio = p_task->prio;
- p_CB2 = p_CB->p_lnk;
- /* Search for an entry in the list */
- while ((p_CB2 != NULL) && (prio <= p_CB2->prio)) {
- p_CB = (P_XCB)p_CB2;
- p_CB2 = p_CB2->p_lnk;
- }
- /* Entry found, insert the task into the list */
- p_task->p_lnk = p_CB2;
- p_CB->p_lnk = p_task;
- if (sem_mbx) {
- if (p_CB2 != NULL) {
- p_CB2->p_rlnk = p_task;
- }
- p_task->p_rlnk = (P_TCB)p_CB;
- }
- else {
- p_task->p_rlnk = NULL;
- }
-}
-
-
-/*--------------------------- rt_get_first ----------------------------------*/
-
-P_TCB rt_get_first (P_XCB p_CB) {
- /* Get task at head of list: it is the task with highest priority. */
- /* "p_CB" points to head of list. */
- P_TCB p_first;
-
- p_first = p_CB->p_lnk;
- p_CB->p_lnk = p_first->p_lnk;
- if ((p_CB->cb_type == SCB) || (p_CB->cb_type == MCB) || (p_CB->cb_type == MUCB)) {
- if (p_first->p_lnk != NULL) {
- p_first->p_lnk->p_rlnk = (P_TCB)p_CB;
- p_first->p_lnk = NULL;
- }
- p_first->p_rlnk = NULL;
- }
- else {
- p_first->p_lnk = NULL;
- }
- return (p_first);
-}
-
-
-/*--------------------------- rt_put_rdy_first ------------------------------*/
-
-void rt_put_rdy_first (P_TCB p_task) {
- /* Put task identified with "p_task" at the head of the ready list. The */
- /* task must have at least a priority equal to highest priority in list. */
- p_task->p_lnk = os_rdy.p_lnk;
- p_task->p_rlnk = NULL;
- os_rdy.p_lnk = p_task;
-}
-
-
-/*--------------------------- rt_get_same_rdy_prio --------------------------*/
-
-P_TCB rt_get_same_rdy_prio (void) {
- /* Remove a task of same priority from ready list if any exists. Other- */
- /* wise return NULL. */
- P_TCB p_first;
-
- p_first = os_rdy.p_lnk;
- if (p_first->prio == os_tsk.run->prio) {
- os_rdy.p_lnk = os_rdy.p_lnk->p_lnk;
- return (p_first);
- }
- return (NULL);
-}
-
-
-/*--------------------------- rt_resort_prio --------------------------------*/
-
-void rt_resort_prio (P_TCB p_task) {
- /* Re-sort ordered lists after the priority of 'p_task' has changed. */
- P_TCB p_CB;
-
- if (p_task->p_rlnk == NULL) {
- if (p_task->state == READY) {
- /* Task is chained into READY list. */
- p_CB = (P_TCB)&os_rdy;
- goto res;
- }
- }
- else {
- p_CB = p_task->p_rlnk;
- while (p_CB->cb_type == TCB) {
- /* Find a header of this task chain list. */
- p_CB = p_CB->p_rlnk;
- }
-res:rt_rmv_list (p_task);
- rt_put_prio ((P_XCB)p_CB, p_task);
- }
-}
-
-
-/*--------------------------- rt_put_dly ------------------------------------*/
-
-void rt_put_dly (P_TCB p_task, U16 delay) {
- /* Put a task identified with "p_task" into chained delay wait list using */
- /* a delay value of "delay". */
- P_TCB p;
- U32 delta,idelay = delay;
-
- p = (P_TCB)&os_dly;
- if (p->p_dlnk == NULL) {
- /* Delay list empty */
- delta = 0U;
- goto last;
- }
- delta = os_dly.delta_time;
- while (delta < idelay) {
- if (p->p_dlnk == NULL) {
- /* End of list found */
-last: p_task->p_dlnk = NULL;
- p->p_dlnk = p_task;
- p_task->p_blnk = p;
- p->delta_time = (U16)(idelay - delta);
- p_task->delta_time = 0U;
- return;
- }
- p = p->p_dlnk;
- delta += p->delta_time;
- }
- /* Right place found */
- p_task->p_dlnk = p->p_dlnk;
- p->p_dlnk = p_task;
- p_task->p_blnk = p;
- if (p_task->p_dlnk != NULL) {
- p_task->p_dlnk->p_blnk = p_task;
- }
- p_task->delta_time = (U16)(delta - idelay);
- p->delta_time -= p_task->delta_time;
-}
-
-
-/*--------------------------- rt_dec_dly ------------------------------------*/
-
-void rt_dec_dly (void) {
- /* Decrement delta time of list head: remove tasks having a value of zero.*/
- P_TCB p_rdy;
-
- if (os_dly.p_dlnk == NULL) {
- return;
- }
- os_dly.delta_time--;
- while ((os_dly.delta_time == 0U) && (os_dly.p_dlnk != NULL)) {
- p_rdy = os_dly.p_dlnk;
- if (p_rdy->p_rlnk != NULL) {
- /* Task is really enqueued, remove task from semaphore/mailbox */
- /* timeout waiting list. */
- p_rdy->p_rlnk->p_lnk = p_rdy->p_lnk;
- if (p_rdy->p_lnk != NULL) {
- p_rdy->p_lnk->p_rlnk = p_rdy->p_rlnk;
- p_rdy->p_lnk = NULL;
- }
- p_rdy->p_rlnk = NULL;
- }
- rt_put_prio (&os_rdy, p_rdy);
- os_dly.delta_time = p_rdy->delta_time;
- if (p_rdy->state == WAIT_ITV) {
- /* Calculate the next time for interval wait. */
- p_rdy->delta_time = p_rdy->interval_time + (U16)os_time;
- }
- p_rdy->state = READY;
- os_dly.p_dlnk = p_rdy->p_dlnk;
- if (p_rdy->p_dlnk != NULL) {
- p_rdy->p_dlnk->p_blnk = (P_TCB)&os_dly;
- p_rdy->p_dlnk = NULL;
- }
- p_rdy->p_blnk = NULL;
- }
-}
-
-
-/*--------------------------- rt_rmv_list -----------------------------------*/
-
-void rt_rmv_list (P_TCB p_task) {
- /* Remove task identified with "p_task" from ready, semaphore or mailbox */
- /* waiting list if enqueued. */
- P_TCB p_b;
-
- if (p_task->p_rlnk != NULL) {
- /* A task is enqueued in semaphore / mailbox waiting list. */
- p_task->p_rlnk->p_lnk = p_task->p_lnk;
- if (p_task->p_lnk != NULL) {
- p_task->p_lnk->p_rlnk = p_task->p_rlnk;
- }
- return;
- }
-
- p_b = (P_TCB)&os_rdy;
- while (p_b != NULL) {
- /* Search the ready list for task "p_task" */
- if (p_b->p_lnk == p_task) {
- p_b->p_lnk = p_task->p_lnk;
- return;
- }
- p_b = p_b->p_lnk;
- }
-}
-
-
-/*--------------------------- rt_rmv_dly ------------------------------------*/
-
-void rt_rmv_dly (P_TCB p_task) {
- /* Remove task identified with "p_task" from delay list if enqueued. */
- P_TCB p_b;
-
- p_b = p_task->p_blnk;
- if (p_b != NULL) {
- /* Task is really enqueued */
- p_b->p_dlnk = p_task->p_dlnk;
- if (p_task->p_dlnk != NULL) {
- /* 'p_task' is in the middle of list */
- p_b->delta_time += p_task->delta_time;
- p_task->p_dlnk->p_blnk = p_b;
- p_task->p_dlnk = NULL;
- }
- else {
- /* 'p_task' is at the end of list */
- p_b->delta_time = 0U;
- }
- p_task->p_blnk = NULL;
- }
-}
-
-
-/*--------------------------- rt_psq_enq ------------------------------------*/
-
-void rt_psq_enq (OS_ID entry, U32 arg) {
- /* Insert post service request "entry" into ps-queue. */
- U32 idx;
-
- idx = rt_inc_qi (os_psq->size, &os_psq->count, &os_psq->first);
- if (idx < os_psq->size) {
- os_psq->q[idx].id = entry;
- os_psq->q[idx].arg = arg;
- }
- else {
- os_error (OS_ERR_FIFO_OVF);
- }
-}
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_List.h b/rtos/rtx/TARGET_CORTEX_A/rt_List.h
deleted file mode 100644
index 4d8b51a9f0..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_List.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_LIST.H
- * Purpose: Functions for the management of different lists
- * Rev.: V4.79
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-/* Definitions */
-
-/* Values for 'cb_type' */
-#define TCB 0U
-#define MCB 1U
-#define SCB 2U
-#define MUCB 3U
-#define HCB 4U
-
-/* Variables */
-extern struct OS_XCB os_rdy;
-extern struct OS_XCB os_dly;
-
-/* Functions */
-extern void rt_put_prio (P_XCB p_CB, P_TCB p_task);
-extern P_TCB rt_get_first (P_XCB p_CB);
-extern void rt_put_rdy_first (P_TCB p_task);
-extern P_TCB rt_get_same_rdy_prio (void);
-extern void rt_resort_prio (P_TCB p_task);
-extern void rt_put_dly (P_TCB p_task, U16 delay);
-extern void rt_dec_dly (void);
-extern void rt_rmv_list (P_TCB p_task);
-extern void rt_rmv_dly (P_TCB p_task);
-extern void rt_psq_enq (OS_ID entry, U32 arg);
-
-/* This is a fast macro generating in-line code */
-#define rt_rdy_prio(void) (os_rdy.p_lnk->prio)
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.c b/rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.c
deleted file mode 100644
index 480b7809d6..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.c
+++ /dev/null
@@ -1,297 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_MAILBOX.C
- * Purpose: Implements waits and wake-ups for mailbox messages
- * Rev.: V4.79
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-#include "rt_TypeDef.h"
-#include "RTX_Config.h"
-#include "rt_System.h"
-#include "rt_List.h"
-#include "rt_Mailbox.h"
-#include "rt_MemBox.h"
-#include "rt_Task.h"
-#ifdef __CORTEX_A9
-#include "rt_HAL_CA.h"
-#else
-#include "rt_HAL_CM.h"
-#endif
-
-
-/*----------------------------------------------------------------------------
- * Functions
- *---------------------------------------------------------------------------*/
-
-
-/*--------------------------- rt_mbx_init -----------------------------------*/
-
-void rt_mbx_init (OS_ID mailbox, U16 mbx_size) {
- /* Initialize a mailbox */
- P_MCB p_MCB = mailbox;
-
- p_MCB->cb_type = MCB;
- p_MCB->state = 0U;
- p_MCB->isr_st = 0U;
- p_MCB->p_lnk = NULL;
- p_MCB->first = 0U;
- p_MCB->last = 0U;
- p_MCB->count = 0U;
- p_MCB->size = (U16)((mbx_size - (sizeof(struct OS_MCB) - (sizeof(void *))))
- / sizeof(void *));
-}
-
-
-/*--------------------------- rt_mbx_send -----------------------------------*/
-
-OS_RESULT rt_mbx_send (OS_ID mailbox, void *p_msg, U16 timeout) {
- /* Send message to a mailbox */
- P_MCB p_MCB = mailbox;
- P_TCB p_TCB;
-
- if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 1U)) {
- /* A task is waiting for message */
- p_TCB = rt_get_first ((P_XCB)p_MCB);
-#ifdef __CMSIS_RTOS
- rt_ret_val2(p_TCB, 0x10U/*osEventMessage*/, (U32)p_msg);
-#else
- *p_TCB->msg = p_msg;
- rt_ret_val (p_TCB, OS_R_MBX);
-#endif
- rt_rmv_dly (p_TCB);
- rt_dispatch (p_TCB);
- }
- else {
- /* Store message in mailbox queue */
- if (p_MCB->count == p_MCB->size) {
- /* No free message entry, wait for one. If message queue is full, */
- /* then no task is waiting for message. The 'p_MCB->p_lnk' list */
- /* pointer can now be reused for send message waits task list. */
- if (timeout == 0U) {
- return (OS_R_TMO);
- }
- if (p_MCB->p_lnk != NULL) {
- rt_put_prio ((P_XCB)p_MCB, os_tsk.run);
- }
- else {
- p_MCB->p_lnk = os_tsk.run;
- os_tsk.run->p_lnk = NULL;
- os_tsk.run->p_rlnk = (P_TCB)p_MCB;
- /* Task is waiting to send a message */
- p_MCB->state = 2U;
- }
- os_tsk.run->msg = p_msg;
- rt_block (timeout, WAIT_MBX);
- return (OS_R_TMO);
- }
- /* Yes, there is a free entry in a mailbox. */
- p_MCB->msg[p_MCB->first] = p_msg;
- rt_inc (&p_MCB->count);
- if (++p_MCB->first == p_MCB->size) {
- p_MCB->first = 0U;
- }
- }
- return (OS_R_OK);
-}
-
-
-/*--------------------------- rt_mbx_wait -----------------------------------*/
-
-OS_RESULT rt_mbx_wait (OS_ID mailbox, void **message, U16 timeout) {
- /* Receive a message; possibly wait for it */
- P_MCB p_MCB = mailbox;
- P_TCB p_TCB;
-
- /* If a message is available in the fifo buffer */
- /* remove it from the fifo buffer and return. */
- if (p_MCB->count) {
- *message = p_MCB->msg[p_MCB->last];
- if (++p_MCB->last == p_MCB->size) {
- p_MCB->last = 0U;
- }
- if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 2U)) {
- /* A task is waiting to send message */
- p_TCB = rt_get_first ((P_XCB)p_MCB);
-#ifdef __CMSIS_RTOS
- rt_ret_val(p_TCB, 0U/*osOK*/);
-#else
- rt_ret_val(p_TCB, OS_R_OK);
-#endif
- p_MCB->msg[p_MCB->first] = p_TCB->msg;
- if (++p_MCB->first == p_MCB->size) {
- p_MCB->first = 0U;
- }
- rt_rmv_dly (p_TCB);
- rt_dispatch (p_TCB);
- }
- else {
- rt_dec (&p_MCB->count);
- }
- return (OS_R_OK);
- }
- /* No message available: wait for one */
- if (timeout == 0U) {
- return (OS_R_TMO);
- }
- if (p_MCB->p_lnk != NULL) {
- rt_put_prio ((P_XCB)p_MCB, os_tsk.run);
- }
- else {
- p_MCB->p_lnk = os_tsk.run;
- os_tsk.run->p_lnk = NULL;
- os_tsk.run->p_rlnk = (P_TCB)p_MCB;
- /* Task is waiting to receive a message */
- p_MCB->state = 1U;
- }
- rt_block(timeout, WAIT_MBX);
-#ifndef __CMSIS_RTOS
- os_tsk.run->msg = message;
-#endif
- return (OS_R_TMO);
-}
-
-
-/*--------------------------- rt_mbx_check ----------------------------------*/
-
-OS_RESULT rt_mbx_check (OS_ID mailbox) {
- /* Check for free space in a mailbox. Returns the number of messages */
- /* that can be stored to a mailbox. It returns 0 when mailbox is full. */
- P_MCB p_MCB = mailbox;
-
- return ((U32)(p_MCB->size - p_MCB->count));
-}
-
-
-/*--------------------------- isr_mbx_send ----------------------------------*/
-
-void isr_mbx_send (OS_ID mailbox, void *p_msg) {
- /* Same function as "os_mbx_send", but to be called by ISRs. */
- P_MCB p_MCB = mailbox;
-
- rt_psq_enq (p_MCB, (U32)p_msg);
- rt_psh_req ();
-}
-
-
-/*--------------------------- isr_mbx_receive -------------------------------*/
-
-OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message) {
- /* Receive a message in the interrupt function. The interrupt function */
- /* should not wait for a message since this would block the rtx os. */
- P_MCB p_MCB = mailbox;
-
- if (p_MCB->count) {
- /* A message is available in the fifo buffer. */
- *message = p_MCB->msg[p_MCB->last];
- if (p_MCB->state == 2U) {
- /* A task is locked waiting to send message */
- rt_psq_enq (p_MCB, 0U);
- rt_psh_req ();
- }
- rt_dec (&p_MCB->count);
- if (++p_MCB->last == p_MCB->size) {
- p_MCB->last = 0U;
- }
- return (OS_R_MBX);
- }
- return (OS_R_OK);
-}
-
-
-/*--------------------------- rt_mbx_psh ------------------------------------*/
-
-void rt_mbx_psh (P_MCB p_CB, void *p_msg) {
- /* Store the message to the mailbox queue or pass it to task directly. */
- P_TCB p_TCB;
- void *mem;
-
- if (p_CB->p_lnk != NULL) switch (p_CB->state) {
-#ifdef __CMSIS_RTOS
- case 3:
- /* Task is waiting to allocate memory, remove it from the waiting list */
- mem = rt_alloc_box(p_msg);
- if (mem == NULL) { break; }
- p_TCB = rt_get_first ((P_XCB)p_CB);
- rt_ret_val(p_TCB, (U32)mem);
- p_TCB->state = READY;
- rt_rmv_dly (p_TCB);
- rt_put_prio (&os_rdy, p_TCB);
- break;
-#endif
- case 2:
- /* Task is waiting to send a message, remove it from the waiting list */
- p_TCB = rt_get_first ((P_XCB)p_CB);
-#ifdef __CMSIS_RTOS
- rt_ret_val(p_TCB, 0U/*osOK*/);
-#else
- rt_ret_val(p_TCB, OS_R_OK);
-#endif
- p_CB->msg[p_CB->first] = p_TCB->msg;
- rt_inc (&p_CB->count);
- if (++p_CB->first == p_CB->size) {
- p_CB->first = 0U;
- }
- p_TCB->state = READY;
- rt_rmv_dly (p_TCB);
- rt_put_prio (&os_rdy, p_TCB);
- break;
- case 1:
- /* Task is waiting for a message, pass the message to the task directly */
- p_TCB = rt_get_first ((P_XCB)p_CB);
-#ifdef __CMSIS_RTOS
- rt_ret_val2(p_TCB, 0x10U/*osEventMessage*/, (U32)p_msg);
-#else
- *p_TCB->msg = p_msg;
- rt_ret_val (p_TCB, OS_R_MBX);
-#endif
- p_TCB->state = READY;
- rt_rmv_dly (p_TCB);
- rt_put_prio (&os_rdy, p_TCB);
- break;
- default:
- break;
- } else {
- /* No task is waiting for a message, store it to the mailbox queue */
- if (p_CB->count < p_CB->size) {
- p_CB->msg[p_CB->first] = p_msg;
- rt_inc (&p_CB->count);
- if (++p_CB->first == p_CB->size) {
- p_CB->first = 0U;
- }
- }
- else {
- os_error (OS_ERR_MBX_OVF);
- }
- }
-}
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.h b/rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.h
deleted file mode 100644
index 4ce48bef35..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_MAILBOX.H
- * Purpose: Implements waits and wake-ups for mailbox messages
- * Rev.: V4.70
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-/* Functions */
-extern void rt_mbx_init (OS_ID mailbox, U16 mbx_size);
-extern OS_RESULT rt_mbx_send (OS_ID mailbox, void *p_msg, U16 timeout);
-extern OS_RESULT rt_mbx_wait (OS_ID mailbox, void **message, U16 timeout);
-extern OS_RESULT rt_mbx_check (OS_ID mailbox);
-extern void isr_mbx_send (OS_ID mailbox, void *p_msg);
-extern OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message);
-extern void rt_mbx_psh (P_MCB p_CB, void *p_msg);
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.c b/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.c
deleted file mode 100644
index 049438e79e..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_MEMBOX.C
- * Purpose: Interface functions for fixed memory block management system
- * Rev.: V4.79 plus changes for RTX-Ax
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH, 2015 ARM Limited
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-#include "rt_TypeDef.h"
-#include "RTX_Config.h"
-#include "rt_System.h"
-#include "rt_MemBox.h"
-#ifdef __CORTEX_A9
-#include "rt_HAL_CA.h"
-#else
-#include "rt_HAL_CM.h"
-#endif
-
-/*----------------------------------------------------------------------------
- * Global Functions
- *---------------------------------------------------------------------------*/
-
-
-/*--------------------------- _init_box -------------------------------------*/
-
-U32 _init_box (void *box_mem, U32 box_size, U32 blk_size) {
- /* Initialize memory block system, returns 0 if OK, 1 if fails. */
- void *end;
- void *blk;
- void *next;
- U32 sizeof_bm;
-
- /* Create memory structure. */
- if (blk_size & BOX_ALIGN_8) {
- /* Memory blocks 8-byte aligned. */
- blk_size = ((blk_size & ~BOX_ALIGN_8) + 7U) & ~(U32)7U;
- sizeof_bm = (sizeof (struct OS_BM) + 7U) & ~(U32)7U;
- }
- else {
- /* Memory blocks 4-byte aligned. */
- blk_size = (blk_size + 3U) & ~(U32)3U;
- sizeof_bm = sizeof (struct OS_BM);
- }
- if (blk_size == 0U) {
- return (1U);
- }
- if ((blk_size + sizeof_bm) > box_size) {
- return (1U);
- }
- /* Create a Memory structure. */
- blk = ((U8 *) box_mem) + sizeof_bm;
- ((P_BM) box_mem)->free = blk;
- end = ((U8 *) box_mem) + box_size;
- ((P_BM) box_mem)->end = end;
- ((P_BM) box_mem)->blk_size = blk_size;
-
- /* Link all free blocks using offsets. */
- end = ((U8 *) end) - blk_size;
- while (1) {
- next = ((U8 *) blk) + blk_size;
- if (next > end) { break; }
- *((void **)blk) = next;
- blk = next;
- }
- /* end marker */
- *((void **)blk) = 0U;
- return (0U);
-}
-
-/*--------------------------- rt_alloc_box ----------------------------------*/
-
-void *rt_alloc_box (void *box_mem) {
- /* Allocate a memory block and return start address. */
- void **free;
-#ifndef __USE_EXCLUSIVE_ACCESS
- U32 irq_mask;
-
-
-#if defined (__ICCARM__)
- irq_mask = (U32)__disable_irq_iar();
-#else
- irq_mask = (U32)__disable_irq ();
-#endif /* __ICCARM__ */
- free = ((P_BM) box_mem)->free;
- if (free) {
- ((P_BM) box_mem)->free = *free;
- }
- if (irq_mask == 0U) { __enable_irq (); }
-#else
- do {
- if ((free = (void **)__ldrex(&((P_BM) box_mem)->free)) == 0U) {
- __clrex();
- break;
- }
- } while (__strex((U32)*free, &((P_BM) box_mem)->free));
-#endif
- return (free);
-}
-
-
-/*--------------------------- _calloc_box -----------------------------------*/
-
-void *_calloc_box (void *box_mem) {
- /* Allocate a 0-initialized memory block and return start address. */
- void *free;
- U32 *p;
- U32 i;
-
- free = _alloc_box (box_mem);
- if (free) {
- p = free;
- for (i = ((P_BM) box_mem)->blk_size; i; i -= 4U) {
- *p = 0U;
- p++;
- }
- }
- return (free);
-}
-
-
-/*--------------------------- rt_free_box -----------------------------------*/
-
-U32 rt_free_box (void *box_mem, void *box) {
- /* Free a memory block, returns 0 if OK, 1 if box does not belong to box_mem */
-#ifndef __USE_EXCLUSIVE_ACCESS
- U32 irq_mask;
-#endif
-
- if ((box < box_mem) || (box >= ((P_BM) box_mem)->end)) {
- return (1U);
- }
-
-#ifndef __USE_EXCLUSIVE_ACCESS
-#if defined (__ICCARM__)
- irq_mask = (U32)__disable_irq_iar();
-#else
- irq_mask = (U32)__disable_irq ();
-#endif /* __ICCARM__ */
- *((void **)box) = ((P_BM) box_mem)->free;
- ((P_BM) box_mem)->free = box;
- if (irq_mask == 0U) { __enable_irq (); }
-#else
- do {
- do {
- *((void **)box) = ((P_BM) box_mem)->free;
- __DMB();
- } while (*(void**)box != (void *)__ldrex(&((P_BM) box_mem)->free));
- } while (__strex ((U32)box, &((P_BM) box_mem)->free));
-#endif
- return (0U);
-}
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.h b/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.h
deleted file mode 100644
index 14e7df6cd9..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_MEMBOX.H
- * Purpose: Interface functions for fixed memory block management system
- * Rev.: V4.79
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-/* Functions */
-#define rt_init_box _init_box
-#define rt_calloc_box _calloc_box
-extern U32 _init_box (void *box_mem, U32 box_size, U32 blk_size);
-extern void *rt_alloc_box (void *box_mem);
-extern void * _calloc_box (void *box_mem);
-extern U32 rt_free_box (void *box_mem, void *box);
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_Memory.c b/rtos/rtx/TARGET_CORTEX_A/rt_Memory.c
deleted file mode 100644
index 7ade9e1c0e..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_Memory.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_MEMORY.C
- * Purpose: Interface functions for Dynamic Memory Management System
- * Rev.: V4.79
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-#include "rt_TypeDef.h"
-#include "rt_Memory.h"
-
-
-/* Functions */
-
-// Initialize Dynamic Memory pool
-// Parameters:
-// pool: Pointer to memory pool
-// size: Size of memory pool in bytes
-// Return: 0 - OK, 1 - Error
-
-U32 rt_init_mem (void *pool, U32 size) {
- MEMP *ptr;
-
- if ((pool == NULL) || (size < sizeof(MEMP))) { return (1U); }
-
- ptr = (MEMP *)pool;
- ptr->next = (MEMP *)((U32)pool + size - sizeof(MEMP *));
- ptr->next->next = NULL;
- ptr->len = 0U;
-
- return (0U);
-}
-
-// Allocate Memory from Memory pool
-// Parameters:
-// pool: Pointer to memory pool
-// size: Size of memory in bytes to allocate
-// Return: Pointer to allocated memory
-
-void *rt_alloc_mem (void *pool, U32 size) {
- MEMP *p, *p_search, *p_new;
- U32 hole_size;
-
- if ((pool == NULL) || (size == 0U)) { return NULL; }
-
- /* Add header offset to 'size' */
- size += sizeof(MEMP);
- /* Make sure that block is 4-byte aligned */
- size = (size + 3U) & ~(U32)3U;
-
- p_search = (MEMP *)pool;
- while (1) {
- hole_size = (U32)p_search->next - (U32)p_search;
- hole_size -= p_search->len;
- /* Check if hole size is big enough */
- if (hole_size >= size) { break; }
- p_search = p_search->next;
- if (p_search->next == NULL) {
- /* Failed, we are at the end of the list */
- return NULL;
- }
- }
-
- if (p_search->len == 0U) {
- /* No block is allocated, set the Length of the first element */
- p_search->len = size;
- p = (MEMP *)(((U32)p_search) + sizeof(MEMP));
- } else {
- /* Insert new list element into the memory list */
- p_new = (MEMP *)((U32)p_search + p_search->len);
- p_new->next = p_search->next;
- p_new->len = size;
- p_search->next = p_new;
- p = (MEMP *)(((U32)p_new) + sizeof(MEMP));
- }
-
- return (p);
-}
-
-// Free Memory and return it to Memory pool
-// Parameters:
-// pool: Pointer to memory pool
-// mem: Pointer to memory to free
-// Return: 0 - OK, 1 - Error
-
-U32 rt_free_mem (void *pool, void *mem) {
- MEMP *p_search, *p_prev, *p_return;
-
- if ((pool == NULL) || (mem == NULL)) { return (1U); }
-
- p_return = (MEMP *)((U32)mem - sizeof(MEMP));
-
- /* Set list header */
- p_prev = NULL;
- p_search = (MEMP *)pool;
- while (p_search != p_return) {
- p_prev = p_search;
- p_search = p_search->next;
- if (p_search == NULL) {
- /* Valid Memory block not found */
- return (1U);
- }
- }
-
- if (p_prev == NULL) {
- /* First block to be released, only set length to 0 */
- p_search->len = 0U;
- } else {
- /* Discard block from chain list */
- p_prev->next = p_search->next;
- }
-
- return (0U);
-}
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_Memory.h b/rtos/rtx/TARGET_CORTEX_A/rt_Memory.h
deleted file mode 100644
index 26780a4ad3..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_Memory.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_MEMORY.H
- * Purpose: Interface functions for Dynamic Memory Management System
- * Rev.: V4.79
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-/* Types */
-typedef struct mem { /* << Memory Pool management struct >> */
- struct mem *next; /* Next Memory Block in the list */
- U32 len; /* Length of data block */
-} MEMP;
-
-/* Functions */
-extern U32 rt_init_mem (void *pool, U32 size);
-extern void *rt_alloc_mem (void *pool, U32 size);
-extern U32 rt_free_mem (void *pool, void *mem);
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_Mutex.c b/rtos/rtx/TARGET_CORTEX_A/rt_Mutex.c
deleted file mode 100644
index e9eec52bc7..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_Mutex.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_MUTEX.C
- * Purpose: Implements mutex synchronization objects
- * Rev.: V4.79 plus changes for RTX-Ax
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH, 2012-2016 ARM Limited
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-#include "rt_TypeDef.h"
-#include "RTX_Config.h"
-#include "rt_List.h"
-#include "rt_Task.h"
-#include "rt_Mutex.h"
-#ifdef __CORTEX_A9
-#include "rt_HAL_CA.h"
-#else
-#include "rt_HAL_CM.h"
-#endif
-
-
-/*----------------------------------------------------------------------------
- * Functions
- *---------------------------------------------------------------------------*/
-
-
-/*--------------------------- rt_mut_init -----------------------------------*/
-
-void rt_mut_init (OS_ID mutex) {
- /* Initialize a mutex object */
- P_MUCB p_MCB = mutex;
-
- p_MCB->cb_type = MUCB;
- p_MCB->level = 0U;
- p_MCB->p_lnk = NULL;
- p_MCB->owner = NULL;
- p_MCB->p_mlnk = NULL;
-}
-
-
-/*--------------------------- rt_mut_delete ---------------------------------*/
-
-#ifdef __CMSIS_RTOS
-OS_RESULT rt_mut_delete (OS_ID mutex) {
- /* Delete a mutex object */
- P_MUCB p_MCB = mutex;
- P_TCB p_TCB;
- P_MUCB p_mlnk;
- U8 prio;
-
- __DMB();
- /* Restore owner task's priority. */
- if (p_MCB->level != 0U) {
-
- p_TCB = p_MCB->owner;
-
- /* Remove mutex from task mutex owner list. */
- p_mlnk = p_TCB->p_mlnk;
- if (p_mlnk == p_MCB) {
- p_TCB->p_mlnk = p_MCB->p_mlnk;
- }
- else {
- while (p_mlnk) {
- if (p_mlnk->p_mlnk == p_MCB) {
- p_mlnk->p_mlnk = p_MCB->p_mlnk;
- break;
- }
- p_mlnk = p_mlnk->p_mlnk;
- }
- }
-
- /* Restore owner task's priority. */
- prio = p_TCB->prio_base;
- p_mlnk = p_TCB->p_mlnk;
- while (p_mlnk) {
- if ((p_mlnk->p_lnk != NULL) && (p_mlnk->p_lnk->prio > prio)) {
- /* A task with higher priority is waiting for mutex. */
- prio = p_mlnk->p_lnk->prio;
- }
- p_mlnk = p_mlnk->p_mlnk;
- }
- if (p_TCB->prio != prio) {
- p_TCB->prio = prio;
- if (p_TCB != os_tsk.run) {
- rt_resort_prio (p_TCB);
- }
- }
-
- }
-
- while (p_MCB->p_lnk != NULL) {
- /* A task is waiting for mutex. */
- p_TCB = rt_get_first ((P_XCB)p_MCB);
- rt_ret_val(p_TCB, 0U/*osOK*/);
- rt_rmv_dly(p_TCB);
- p_TCB->state = READY;
- rt_put_prio (&os_rdy, p_TCB);
- }
-
- if ((os_rdy.p_lnk != NULL) && (os_rdy.p_lnk->prio > os_tsk.run->prio)) {
- /* preempt running task */
- rt_put_prio (&os_rdy, os_tsk.run);
- os_tsk.run->state = READY;
- rt_dispatch (NULL);
- }
-
- p_MCB->cb_type = 0U;
-
- return (OS_R_OK);
-}
-#endif
-
-
-/*--------------------------- rt_mut_release --------------------------------*/
-
-OS_RESULT rt_mut_release (OS_ID mutex) {
- /* Release a mutex object */
- P_MUCB p_MCB = mutex;
- P_TCB p_TCB;
- P_MUCB p_mlnk;
- U8 prio;
-
- if ((p_MCB->level == 0U) || (p_MCB->owner != os_tsk.run)) {
- /* Unbalanced mutex release or task is not the owner */
- return (OS_R_NOK);
- }
- __DMB();
- if (--p_MCB->level != 0U) {
- return (OS_R_OK);
- }
-
- /* Remove mutex from task mutex owner list. */
- p_mlnk = os_tsk.run->p_mlnk;
- if (p_mlnk == p_MCB) {
- os_tsk.run->p_mlnk = p_MCB->p_mlnk;
- }
- else {
- while (p_mlnk) {
- if (p_mlnk->p_mlnk == p_MCB) {
- p_mlnk->p_mlnk = p_MCB->p_mlnk;
- break;
- }
- p_mlnk = p_mlnk->p_mlnk;
- }
- }
-
- /* Restore owner task's priority. */
- prio = os_tsk.run->prio_base;
- p_mlnk = os_tsk.run->p_mlnk;
- while (p_mlnk) {
- if ((p_mlnk->p_lnk != NULL) && (p_mlnk->p_lnk->prio > prio)) {
- /* A task with higher priority is waiting for mutex. */
- prio = p_mlnk->p_lnk->prio;
- }
- p_mlnk = p_mlnk->p_mlnk;
- }
- os_tsk.run->prio = prio;
-
- if (p_MCB->p_lnk != NULL) {
- /* A task is waiting for mutex. */
- p_TCB = rt_get_first ((P_XCB)p_MCB);
-#ifdef __CMSIS_RTOS
- rt_ret_val(p_TCB, 0U/*osOK*/);
-#else
- rt_ret_val(p_TCB, OS_R_MUT);
-#endif
- rt_rmv_dly (p_TCB);
- /* A waiting task becomes the owner of this mutex. */
- p_MCB->level = 1U;
- p_MCB->owner = p_TCB;
- p_MCB->p_mlnk = p_TCB->p_mlnk;
- p_TCB->p_mlnk = p_MCB;
- /* Priority inversion, check which task continues. */
- if (os_tsk.run->prio >= rt_rdy_prio()) {
- rt_dispatch (p_TCB);
- }
- else {
- /* Ready task has higher priority than running task. */
- rt_put_prio (&os_rdy, os_tsk.run);
- rt_put_prio (&os_rdy, p_TCB);
- os_tsk.run->state = READY;
- p_TCB->state = READY;
- rt_dispatch (NULL);
- }
- }
- else {
- /* Check if own priority lowered by priority inversion. */
- if (rt_rdy_prio() > os_tsk.run->prio) {
- rt_put_prio (&os_rdy, os_tsk.run);
- os_tsk.run->state = READY;
- rt_dispatch (NULL);
- }
- }
- return (OS_R_OK);
-}
-
-
-/*--------------------------- rt_mut_wait -----------------------------------*/
-
-OS_RESULT rt_mut_wait (OS_ID mutex, U16 timeout) {
- /* Wait for a mutex, continue when mutex is free. */
- P_MUCB p_MCB = mutex;
-
- if (p_MCB->level == 0U) {
- p_MCB->owner = os_tsk.run;
- p_MCB->p_mlnk = os_tsk.run->p_mlnk;
- os_tsk.run->p_mlnk = p_MCB;
- goto inc;
- }
- if (p_MCB->owner == os_tsk.run) {
- /* OK, running task is the owner of this mutex. */
-inc:p_MCB->level++;
- __DMB();
- return (OS_R_OK);
- }
- /* Mutex owned by another task, wait until released. */
- if (timeout == 0U) {
- return (OS_R_TMO);
- }
- /* Raise the owner task priority if lower than current priority. */
- /* This priority inversion is called priority inheritance. */
- if (p_MCB->owner->prio < os_tsk.run->prio) {
- p_MCB->owner->prio = os_tsk.run->prio;
- rt_resort_prio (p_MCB->owner);
- }
- if (p_MCB->p_lnk != NULL) {
- rt_put_prio ((P_XCB)p_MCB, os_tsk.run);
- }
- else {
- p_MCB->p_lnk = os_tsk.run;
- os_tsk.run->p_lnk = NULL;
- os_tsk.run->p_rlnk = (P_TCB)p_MCB;
- }
- rt_block(timeout, WAIT_MUT);
- return (OS_R_TMO);
-}
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_Mutex.h b/rtos/rtx/TARGET_CORTEX_A/rt_Mutex.h
deleted file mode 100644
index 75a2258420..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_Mutex.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_MUTEX.H
- * Purpose: Implements mutex synchronization objects
- * Rev.: V4.70
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-/* Functions */
-extern void rt_mut_init (OS_ID mutex);
-extern OS_RESULT rt_mut_delete (OS_ID mutex);
-extern OS_RESULT rt_mut_release (OS_ID mutex);
-extern OS_RESULT rt_mut_wait (OS_ID mutex, U16 timeout);
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_Robin.c b/rtos/rtx/TARGET_CORTEX_A/rt_Robin.c
deleted file mode 100644
index 92eb480cfd..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_Robin.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_ROBIN.C
- * Purpose: Round Robin Task switching
- * Rev.: V4.79
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-#include "rt_TypeDef.h"
-#include "RTX_Config.h"
-#include "rt_List.h"
-#include "rt_Task.h"
-#include "rt_Time.h"
-#include "rt_Robin.h"
-#ifdef __CORTEX_A9
-#include "rt_HAL_CA.h"
-#else
-#include "rt_HAL_CM.h"
-#endif
-
-/*----------------------------------------------------------------------------
- * Global Variables
- *---------------------------------------------------------------------------*/
-
-struct OS_ROBIN os_robin;
-
-
-/*----------------------------------------------------------------------------
- * Global Functions
- *---------------------------------------------------------------------------*/
-
-/*--------------------------- rt_init_robin ---------------------------------*/
-
-__weak void rt_init_robin (void) {
- /* Initialize Round Robin variables. */
- os_robin.task = NULL;
- os_robin.tout = (U16)os_rrobin;
-}
-
-/*--------------------------- rt_chk_robin ----------------------------------*/
-
-__weak void rt_chk_robin (void) {
- /* Check if Round Robin timeout expired and switch to the next ready task.*/
- P_TCB p_new;
-
- if (os_robin.task != os_rdy.p_lnk) {
- /* New task was suspended, reset Round Robin timeout. */
- os_robin.task = os_rdy.p_lnk;
- os_robin.time = (U16)os_time + os_robin.tout - 1U;
- }
- if (os_robin.time == (U16)os_time) {
- /* Round Robin timeout has expired, swap Robin tasks. */
- os_robin.task = NULL;
- p_new = rt_get_first (&os_rdy);
- rt_put_prio ((P_XCB)&os_rdy, p_new);
- }
-}
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_Robin.h b/rtos/rtx/TARGET_CORTEX_A/rt_Robin.h
deleted file mode 100644
index 4bdf81a8df..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_Robin.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_ROBIN.H
- * Purpose: Round Robin Task switching definitions
- * Rev.: V4.70
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-/* Variables */
-extern struct OS_ROBIN os_robin;
-
-/* Functions */
-extern void rt_init_robin (void);
-extern void rt_chk_robin (void);
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.c b/rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.c
deleted file mode 100644
index 65ba4c6260..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_SEMAPHORE.C
- * Purpose: Implements binary and counting semaphores
- * Rev.: V4.79 plus changes for RTX-Ax
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH, 2012-2016 ARM Limited
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-#include "rt_TypeDef.h"
-#include "RTX_Config.h"
-#include "rt_System.h"
-#include "rt_List.h"
-#include "rt_Task.h"
-#include "rt_Semaphore.h"
-#ifdef __CORTEX_A9
-#include "rt_HAL_CA.h"
-#else
-#include "rt_HAL_CM.h"
-#endif
-
-
-/*----------------------------------------------------------------------------
- * Functions
- *---------------------------------------------------------------------------*/
-
-
-/*--------------------------- rt_sem_init -----------------------------------*/
-
-void rt_sem_init (OS_ID semaphore, U16 token_count) {
- /* Initialize a semaphore */
- P_SCB p_SCB = semaphore;
-
- p_SCB->cb_type = SCB;
- p_SCB->p_lnk = NULL;
- p_SCB->tokens = token_count;
-}
-
-
-/*--------------------------- rt_sem_delete ---------------------------------*/
-
-#ifdef __CMSIS_RTOS
-OS_RESULT rt_sem_delete (OS_ID semaphore) {
- /* Delete semaphore */
- P_SCB p_SCB = semaphore;
- P_TCB p_TCB;
-
- __DMB();
- while (p_SCB->p_lnk != NULL) {
- /* A task is waiting for token */
- p_TCB = rt_get_first ((P_XCB)p_SCB);
- rt_ret_val(p_TCB, 0U);
- rt_rmv_dly(p_TCB);
- p_TCB->state = READY;
- rt_put_prio (&os_rdy, p_TCB);
- }
-
- if ((os_rdy.p_lnk != NULL) && (os_rdy.p_lnk->prio > os_tsk.run->prio)) {
- /* preempt running task */
- rt_put_prio (&os_rdy, os_tsk.run);
- os_tsk.run->state = READY;
- rt_dispatch (NULL);
- }
-
- p_SCB->cb_type = 0U;
-
- return (OS_R_OK);
-}
-#endif
-
-
-/*--------------------------- rt_sem_send -----------------------------------*/
-
-OS_RESULT rt_sem_send (OS_ID semaphore) {
- /* Return a token to semaphore */
- P_SCB p_SCB = semaphore;
- P_TCB p_TCB;
-
- __DMB();
- if (p_SCB->p_lnk != NULL) {
- /* A task is waiting for token */
- p_TCB = rt_get_first ((P_XCB)p_SCB);
-#ifdef __CMSIS_RTOS
- rt_ret_val(p_TCB, 1U);
-#else
- rt_ret_val(p_TCB, OS_R_SEM);
-#endif
- rt_rmv_dly (p_TCB);
- rt_dispatch (p_TCB);
- }
- else {
- /* Store token. */
- p_SCB->tokens++;
- }
- return (OS_R_OK);
-}
-
-
-/*--------------------------- rt_sem_wait -----------------------------------*/
-
-OS_RESULT rt_sem_wait (OS_ID semaphore, U16 timeout) {
- /* Obtain a token; possibly wait for it */
- P_SCB p_SCB = semaphore;
-
- if (p_SCB->tokens) {
- p_SCB->tokens--;
- __DMB();
- return (OS_R_OK);
- }
- /* No token available: wait for one */
- if (timeout == 0U) {
- return (OS_R_TMO);
- }
- if (p_SCB->p_lnk != NULL) {
- rt_put_prio ((P_XCB)p_SCB, os_tsk.run);
- }
- else {
- p_SCB->p_lnk = os_tsk.run;
- os_tsk.run->p_lnk = NULL;
- os_tsk.run->p_rlnk = (P_TCB)p_SCB;
- }
- rt_block(timeout, WAIT_SEM);
- return (OS_R_TMO);
-}
-
-
-/*--------------------------- isr_sem_send ----------------------------------*/
-
-void isr_sem_send (OS_ID semaphore) {
- /* Same function as "os_sem_send", but to be called by ISRs */
- P_SCB p_SCB = semaphore;
-
- rt_psq_enq (p_SCB, 0U);
- rt_psh_req ();
-}
-
-
-/*--------------------------- rt_sem_psh ------------------------------------*/
-
-void rt_sem_psh (P_SCB p_CB) {
- /* Check if task has to be waken up */
- P_TCB p_TCB;
-
- __DMB();
- if (p_CB->p_lnk != NULL) {
- /* A task is waiting for token */
- p_TCB = rt_get_first ((P_XCB)p_CB);
- rt_rmv_dly (p_TCB);
- p_TCB->state = READY;
-#ifdef __CMSIS_RTOS
- rt_ret_val(p_TCB, 1U);
-#else
- rt_ret_val(p_TCB, OS_R_SEM);
-#endif
- rt_put_prio (&os_rdy, p_TCB);
- }
- else {
- /* Store token */
- p_CB->tokens++;
- }
-}
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.h b/rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.h
deleted file mode 100644
index 00c7de49d6..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_SEMAPHORE.H
- * Purpose: Implements binary and counting semaphores
- * Rev.: V4.70
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-/* Functions */
-extern void rt_sem_init (OS_ID semaphore, U16 token_count);
-extern OS_RESULT rt_sem_delete(OS_ID semaphore);
-extern OS_RESULT rt_sem_send (OS_ID semaphore);
-extern OS_RESULT rt_sem_wait (OS_ID semaphore, U16 timeout);
-extern void isr_sem_send (OS_ID semaphore);
-extern void rt_sem_psh (P_SCB p_CB);
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_System.c b/rtos/rtx/TARGET_CORTEX_A/rt_System.c
deleted file mode 100644
index 60d35fedee..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_System.c
+++ /dev/null
@@ -1,336 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_SYSTEM.C
- * Purpose: System Task Manager
- * Rev.: V4.80 plus changes for RTX-Ax
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH, 2012-2016 ARM Limited
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-#include "rt_TypeDef.h"
-#include "RTX_Config.h"
-#include "rt_Task.h"
-#include "rt_System.h"
-#include "rt_Event.h"
-#include "rt_List.h"
-#include "rt_Mailbox.h"
-#include "rt_Semaphore.h"
-#include "rt_Time.h"
-#include "rt_Timer.h"
-#include "rt_Robin.h"
-#ifdef __CORTEX_A9
-#include "rt_HAL_CA.h"
-#else
-#include "rt_HAL_CM.h"
-#endif
-
-/*----------------------------------------------------------------------------
- * Global Variables
- *---------------------------------------------------------------------------*/
-
-S32 os_tick_irqn;
-U8 scheduler_suspended = 0; // flag set by rt_suspend, cleared by rt_resume, read by SVC_Handler
-
-/*----------------------------------------------------------------------------
- * Local Variables
- *---------------------------------------------------------------------------*/
-
-static volatile BIT os_lock;
-static volatile BIT os_psh_flag;
-#ifndef __CORTEX_A9
-static U8 pend_flags;
-#endif
-/*----------------------------------------------------------------------------
- * Global Functions
- *---------------------------------------------------------------------------*/
-
-#define RL_RTX_VER 0x480
-
-#if defined (__CC_ARM)
-__asm void $$RTX$$version (void) {
- /* Export a version number symbol for a version control. */
-
- EXPORT __RL_RTX_VER
-
-__RL_RTX_VER EQU RL_RTX_VER
-}
-#endif
-
-
-/*--------------------------- rt_suspend ------------------------------------*/
-
-extern U32 sysUserTimerWakeupTime(void);
-
-U32 rt_suspend (void) {
- /* Suspend OS scheduler */
- U32 delta = 0xFFFFU;
-#ifdef __CMSIS_RTOS
- U32 sleep;
-#endif
-
- rt_tsk_lock();
- scheduler_suspended = 1;
-
- if (os_dly.p_dlnk) {
- delta = os_dly.delta_time;
- }
-#ifdef __CMSIS_RTOS
- sleep = sysUserTimerWakeupTime();
- if (sleep < delta) { delta = sleep; }
-#else
- if (os_tmr.next) {
- if (os_tmr.tcnt < delta) delta = os_tmr.tcnt;
- }
-#endif
-
- return (delta);
-}
-
-
-/*--------------------------- rt_resume -------------------------------------*/
-
-extern void sysUserTimerUpdate (U32 sleep_time);
-
-void rt_resume (U32 sleep_time) {
- /* Resume OS scheduler after suspend */
- P_TCB next;
- U32 delta;
-
- os_tsk.run->state = READY;
- rt_put_rdy_first (os_tsk.run);
-
- os_robin.task = NULL;
-
- /* Update delays. */
- if (os_dly.p_dlnk) {
- delta = sleep_time;
- if (delta >= os_dly.delta_time) {
- delta -= os_dly.delta_time;
- os_time += os_dly.delta_time;
- os_dly.delta_time = 1U;
- while (os_dly.p_dlnk) {
- rt_dec_dly();
- if (delta == 0U) { break; }
- delta--;
- os_time++;
- }
- } else {
- os_time += delta;
- os_dly.delta_time -= (U16)delta;
- }
- } else {
- os_time += sleep_time;
- }
-
- /* Check the user timers. */
-#ifdef __CMSIS_RTOS
- sysUserTimerUpdate(sleep_time);
-#else
- if (os_tmr.next) {
- delta = sleep_time;
- if (delta >= os_tmr.tcnt) {
- delta -= os_tmr.tcnt;
- os_tmr.tcnt = 1U;
- while (os_tmr.next) {
- rt_tmr_tick();
- if (delta == 0U) { break; }
- delta--;
- }
- } else {
- os_tmr.tcnt -= delta;
- }
- }
-#endif
-
- /* Switch back to highest ready task */
- next = rt_get_first (&os_rdy);
- rt_switch_req (next);
-
- scheduler_suspended = 0;
- rt_tsk_unlock();
-}
-
-
-/*--------------------------- rt_tsk_lock -----------------------------------*/
-
-void rt_tsk_lock (void) {
- /* Prevent task switching by locking out scheduler */
- if (os_lock == __TRUE) // don't lock again if already locked
- return;
-
- if (os_tick_irqn < 0) {
- OS_LOCK();
- os_lock = __TRUE;
- OS_UNPEND(pend_flags);
- } else {
- OS_X_LOCK((U32)os_tick_irqn);
- os_lock = __TRUE;
- OS_X_UNPEND(pend_flags);
- }
-}
-
-
-/*--------------------------- rt_tsk_unlock ---------------------------------*/
-
-void rt_tsk_unlock (void) {
- /* Unlock scheduler and re-enable task switching */
- if (os_tick_irqn < 0) {
- OS_UNLOCK();
- os_lock = __FALSE;
- OS_PEND(pend_flags, os_psh_flag);
- os_psh_flag = __FALSE;
- } else {
- OS_X_UNLOCK((U32)os_tick_irqn);
- os_lock = __FALSE;
- OS_X_PEND(pend_flags, os_psh_flag);
- os_psh_flag = __FALSE;
- }
-}
-
-
-/*--------------------------- rt_psh_req ------------------------------------*/
-
-void rt_psh_req (void) {
- /* Initiate a post service handling request if required. */
- if (os_lock == __FALSE) {
- OS_PEND_IRQ();
- }
- else {
- os_psh_flag = __TRUE;
- }
-}
-
-
-/*--------------------------- rt_pop_req ------------------------------------*/
-
-void rt_pop_req (void) {
- /* Process an ISR post service requests. */
- struct OS_XCB *p_CB;
- P_TCB next;
- U32 idx;
-
- os_tsk.run->state = READY;
- rt_put_rdy_first (os_tsk.run);
-
- idx = os_psq->last;
- while (os_psq->count) {
- p_CB = os_psq->q[idx].id;
- if (p_CB->cb_type == TCB) {
- /* Is of TCB type */
- rt_evt_psh ((P_TCB)p_CB, (U16)os_psq->q[idx].arg);
- }
- else if (p_CB->cb_type == MCB) {
- /* Is of MCB type */
- rt_mbx_psh ((P_MCB)p_CB, (void *)os_psq->q[idx].arg);
- }
- else {
- /* Must be of SCB type */
- rt_sem_psh ((P_SCB)p_CB);
- }
- if (++idx == os_psq->size) { idx = 0U; }
- rt_dec (&os_psq->count);
- }
- os_psq->last = (U8)idx;
-
- next = rt_get_first (&os_rdy);
- rt_switch_req (next);
-}
-
-
-/*--------------------------- os_tick_init ----------------------------------*/
-
-__weak S32 os_tick_init (void) {
- /* Initialize SysTick timer as system tick timer. */
- rt_systick_init();
- return (-1); /* Return IRQ number of SysTick timer */
-}
-
-/*--------------------------- os_tick_val -----------------------------------*/
-
-__weak U32 os_tick_val (void) {
- /* Get SysTick timer current value (0 .. OS_TRV). */
- return rt_systick_val();
-}
-
-/*--------------------------- os_tick_ovf -----------------------------------*/
-
-__weak U32 os_tick_ovf (void) {
- /* Get SysTick timer overflow flag */
- return rt_systick_ovf();
-}
-
-/*--------------------------- os_tick_irqack --------------------------------*/
-
-__weak void os_tick_irqack (void) {
- /* Acknowledge timer interrupt. */
-}
-
-
-/*--------------------------- rt_systick ------------------------------------*/
-
-extern void sysTimerTick(void);
-
-void rt_systick (void) {
- /* Check for system clock update, suspend running task. */
- P_TCB next;
-
- os_tsk.run->state = READY;
- rt_put_rdy_first (os_tsk.run);
-
- /* Check Round Robin timeout. */
- rt_chk_robin ();
-
- /* Update delays. */
- os_time++;
- rt_dec_dly ();
-
- /* Check the user timers. */
-#ifdef __CMSIS_RTOS
- sysTimerTick();
-#else
- rt_tmr_tick ();
-#endif
-
- /* Switch back to highest ready task */
- next = rt_get_first (&os_rdy);
- rt_switch_req (next);
-}
-
-/*--------------------------- rt_stk_check ----------------------------------*/
-
-__weak void rt_stk_check (void) {
- /* Check for stack overflow. */
- if ((os_tsk.run->tsk_stack < (U32)os_tsk.run->stack) ||
- (os_tsk.run->stack[0] != MAGIC_WORD)) {
- os_error (OS_ERR_STK_OVF);
- }
-}
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_System.h b/rtos/rtx/TARGET_CORTEX_A/rt_System.h
deleted file mode 100644
index fa02d2b905..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_System.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_SYSTEM.H
- * Purpose: System Task Manager definitions
- * Rev.: V4.79
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-/* Variables */
-#define os_psq ((P_PSQ)&os_fifo)
-extern S32 os_tick_irqn;
-
-/* Functions */
-extern U32 rt_suspend (void);
-extern void rt_resume (U32 sleep_time);
-extern void rt_tsk_lock (void);
-extern void rt_tsk_unlock (void);
-extern void rt_psh_req (void);
-extern void rt_pop_req (void);
-extern void rt_systick (void);
-extern void rt_stk_check (void);
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_Task.c b/rtos/rtx/TARGET_CORTEX_A/rt_Task.c
deleted file mode 100644
index 836a88d82c..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_Task.c
+++ /dev/null
@@ -1,452 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_TASK.C
- * Purpose: Task functions and system start up.
- * Rev.: V4.80 plus changes for RTX-Ax
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH, 2012-2016 ARM Limited
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-#include "rt_TypeDef.h"
-#include "RTX_Config.h"
-#include "rt_System.h"
-#include "rt_Task.h"
-#include "rt_List.h"
-#include "rt_MemBox.h"
-#include "rt_Robin.h"
-#ifdef __CORTEX_A9
-#include "rt_HAL_CA.h"
-#else
-#include "rt_HAL_CM.h"
-#endif
-
-/*----------------------------------------------------------------------------
- * Global Variables
- *---------------------------------------------------------------------------*/
-
-/* Running and next task info. */
-struct OS_TSK os_tsk;
-
-/* Task Control Blocks of idle demon */
-struct OS_TCB os_idle_TCB;
-
-
-/*----------------------------------------------------------------------------
- * Local Functions
- *---------------------------------------------------------------------------*/
-
-static OS_TID rt_get_TID (void) {
- U32 tid;
-
- for (tid = 1U; tid <= os_maxtaskrun; tid++) {
- if (os_active_TCB[tid-1U] == NULL) {
- return ((OS_TID)tid);
- }
- }
- return (0U);
-}
-
-
-/*--------------------------- rt_init_context -------------------------------*/
-
-static void rt_init_context (P_TCB p_TCB, U8 priority, FUNCP task_body) {
- /* Initialize general part of the Task Control Block. */
- p_TCB->cb_type = TCB;
- p_TCB->state = READY;
- p_TCB->prio = priority;
- p_TCB->prio_base = priority;
- p_TCB->p_lnk = NULL;
- p_TCB->p_rlnk = NULL;
- p_TCB->p_dlnk = NULL;
- p_TCB->p_blnk = NULL;
- p_TCB->p_mlnk = NULL;
- p_TCB->delta_time = 0U;
- p_TCB->interval_time = 0U;
- p_TCB->events = 0U;
- p_TCB->waits = 0U;
- p_TCB->stack_frame = 0U;
-
- if (p_TCB->priv_stack == 0U) {
- /* Allocate the memory space for the stack. */
- p_TCB->stack = rt_alloc_box (mp_stk);
- }
- rt_init_stack (p_TCB, task_body);
-}
-
-
-/*--------------------------- rt_switch_req ---------------------------------*/
-
-void rt_switch_req (P_TCB p_new) {
- /* Switch to next task (identified by "p_new"). */
- os_tsk.new_tsk = p_new;
- p_new->state = RUNNING;
- DBG_TASK_SWITCH(p_new->task_id);
-}
-
-
-/*--------------------------- rt_dispatch -----------------------------------*/
-
-void rt_dispatch (P_TCB next_TCB) {
- /* Dispatch next task if any identified or dispatch highest ready task */
- /* "next_TCB" identifies a task to run or has value NULL (=no next task) */
- if (next_TCB == NULL) {
- /* Running task was blocked: continue with highest ready task */
- next_TCB = rt_get_first (&os_rdy);
- rt_switch_req (next_TCB);
- }
- else {
- /* Check which task continues */
- if (next_TCB->prio > os_tsk.run->prio) {
- /* preempt running task */
- rt_put_rdy_first (os_tsk.run);
- os_tsk.run->state = READY;
- rt_switch_req (next_TCB);
- }
- else {
- /* put next task into ready list, no task switch takes place */
- next_TCB->state = READY;
- rt_put_prio (&os_rdy, next_TCB);
- }
- }
-}
-
-
-/*--------------------------- rt_block --------------------------------------*/
-
-void rt_block (U16 timeout, U8 block_state) {
- /* Block running task and choose next ready task. */
- /* "timeout" sets a time-out value or is 0xffff (=no time-out). */
- /* "block_state" defines the appropriate task state */
- P_TCB next_TCB;
-
- if (timeout) {
- if (timeout < 0xFFFFU) {
- rt_put_dly (os_tsk.run, timeout);
- }
- os_tsk.run->state = block_state;
- next_TCB = rt_get_first (&os_rdy);
- rt_switch_req (next_TCB);
- }
-}
-
-
-/*--------------------------- rt_tsk_pass -----------------------------------*/
-
-void rt_tsk_pass (void) {
- /* Allow tasks of same priority level to run cooperatively.*/
- P_TCB p_new;
-
- p_new = rt_get_same_rdy_prio();
- if (p_new != NULL) {
- rt_put_prio ((P_XCB)&os_rdy, os_tsk.run);
- os_tsk.run->state = READY;
- rt_switch_req (p_new);
- }
-}
-
-
-/*--------------------------- rt_tsk_self -----------------------------------*/
-
-OS_TID rt_tsk_self (void) {
- /* Return own task identifier value. */
- if (os_tsk.run == NULL) {
- return (0U);
- }
- return ((OS_TID)os_tsk.run->task_id);
-}
-
-
-/*--------------------------- rt_tsk_prio -----------------------------------*/
-
-OS_RESULT rt_tsk_prio (OS_TID task_id, U8 new_prio) {
- /* Change execution priority of a task to "new_prio". */
- P_TCB p_task;
-
- if (task_id == 0U) {
- /* Change execution priority of calling task. */
- os_tsk.run->prio = new_prio;
- os_tsk.run->prio_base = new_prio;
-run:if (rt_rdy_prio() > new_prio) {
- rt_put_prio (&os_rdy, os_tsk.run);
- os_tsk.run->state = READY;
- rt_dispatch (NULL);
- }
- return (OS_R_OK);
- }
-
- /* Find the task in the "os_active_TCB" array. */
- if ((task_id > os_maxtaskrun) || (os_active_TCB[task_id-1U] == NULL)) {
- /* Task with "task_id" not found or not started. */
- return (OS_R_NOK);
- }
- p_task = os_active_TCB[task_id-1U];
- p_task->prio = new_prio;
- p_task->prio_base = new_prio;
- if (p_task == os_tsk.run) {
- goto run;
- }
- rt_resort_prio (p_task);
- if (p_task->state == READY) {
- /* Task enqueued in a ready list. */
- p_task = rt_get_first (&os_rdy);
- rt_dispatch (p_task);
- }
- return (OS_R_OK);
-}
-
-
-/*--------------------------- rt_tsk_create ---------------------------------*/
-
-OS_TID rt_tsk_create (FUNCP task, U32 prio_stksz, void *stk, void *argv) {
- /* Start a new task declared with "task". */
- P_TCB task_context;
- U32 i;
-
- /* Priority 0 is reserved for idle task! */
- if ((prio_stksz & 0xFFU) == 0U) {
- prio_stksz += 1U;
- }
- task_context = rt_alloc_box (mp_tcb);
- if (task_context == NULL) {
- return (0U);
- }
- /* If "size != 0" use a private user provided stack. */
- task_context->stack = stk;
- task_context->priv_stack = (U16)(prio_stksz >> 8);
-
- /* Find a free entry in 'os_active_TCB' table. */
- i = rt_get_TID ();
- if (i == 0U) {
- return (0U);
- }
- task_context->task_id = (U8)i;
- /* Pass parameter 'argv' to 'rt_init_context' */
- task_context->msg = argv;
- task_context->argv = argv;
- /* For 'size == 0' system allocates the user stack from the memory pool. */
- rt_init_context (task_context, (U8)(prio_stksz & 0xFFU), task);
-
- os_active_TCB[i-1U] = task_context;
- DBG_TASK_NOTIFY(task_context, __TRUE);
- rt_dispatch (task_context);
- return ((OS_TID)i);
-}
-
-
-/*--------------------------- rt_tsk_delete ---------------------------------*/
-
-OS_RESULT rt_tsk_delete (OS_TID task_id) {
- /* Terminate the task identified with "task_id". */
- P_TCB task_context;
- P_TCB p_TCB;
- P_MUCB p_MCB, p_MCB0;
-
- if ((task_id == 0U) || (task_id == os_tsk.run->task_id)) {
- /* Terminate itself. */
- os_tsk.run->state = INACTIVE;
- os_tsk.run->tsk_stack = rt_get_PSP ();
- rt_stk_check ();
- p_MCB = os_tsk.run->p_mlnk;
- while (p_MCB) {
- /* Release mutexes owned by this task */
- if (p_MCB->p_lnk) {
- /* A task is waiting for mutex. */
- p_TCB = rt_get_first ((P_XCB)p_MCB);
-#ifdef __CMSIS_RTOS
- rt_ret_val (p_TCB, 0U/*osOK*/);
-#else
- rt_ret_val (p_TCB, OS_R_MUT);
-#endif
- rt_rmv_dly (p_TCB);
- p_TCB->state = READY;
- rt_put_prio (&os_rdy, p_TCB);
- /* A waiting task becomes the owner of this mutex. */
- p_MCB0 = p_MCB->p_mlnk;
- p_MCB->level = 1U;
- p_MCB->owner = p_TCB;
- p_MCB->p_mlnk = p_TCB->p_mlnk;
- p_TCB->p_mlnk = p_MCB;
- p_MCB = p_MCB0;
- }
- else {
- p_MCB0 = p_MCB->p_mlnk;
- p_MCB->level = 0U;
- p_MCB->owner = NULL;
- p_MCB->p_mlnk = NULL;
- p_MCB = p_MCB0;
- }
- }
- os_active_TCB[os_tsk.run->task_id-1U] = NULL;
- rt_free_box (mp_stk, os_tsk.run->stack);
- os_tsk.run->stack = NULL;
- DBG_TASK_NOTIFY(os_tsk.run, __FALSE);
- rt_free_box (mp_tcb, os_tsk.run);
- os_tsk.run = NULL;
- rt_dispatch (NULL);
- /* The program should never come to this point. */
- }
- else {
- /* Find the task in the "os_active_TCB" array. */
- if ((task_id > os_maxtaskrun) || (os_active_TCB[task_id-1U] == NULL)) {
- /* Task with "task_id" not found or not started. */
- return (OS_R_NOK);
- }
- task_context = os_active_TCB[task_id-1U];
- rt_rmv_list (task_context);
- rt_rmv_dly (task_context);
- p_MCB = task_context->p_mlnk;
- while (p_MCB) {
- /* Release mutexes owned by this task */
- if (p_MCB->p_lnk) {
- /* A task is waiting for mutex. */
- p_TCB = rt_get_first ((P_XCB)p_MCB);
-#ifdef __CMSIS_RTOS
- rt_ret_val (p_TCB, 0U/*osOK*/);
-#else
- rt_ret_val (p_TCB, OS_R_MUT);
-#endif
- rt_rmv_dly (p_TCB);
- p_TCB->state = READY;
- rt_put_prio (&os_rdy, p_TCB);
- /* A waiting task becomes the owner of this mutex. */
- p_MCB0 = p_MCB->p_mlnk;
- p_MCB->level = 1U;
- p_MCB->owner = p_TCB;
- p_MCB->p_mlnk = p_TCB->p_mlnk;
- p_TCB->p_mlnk = p_MCB;
- p_MCB = p_MCB0;
- }
- else {
- p_MCB0 = p_MCB->p_mlnk;
- p_MCB->level = 0U;
- p_MCB->owner = NULL;
- p_MCB->p_mlnk = NULL;
- p_MCB = p_MCB0;
- }
- }
- os_active_TCB[task_id-1U] = NULL;
- rt_free_box (mp_stk, task_context->stack);
- task_context->stack = NULL;
- DBG_TASK_NOTIFY(task_context, __FALSE);
- rt_free_box (mp_tcb, task_context);
- if (rt_rdy_prio() > os_tsk.run->prio) {
- /* Ready task has higher priority than running task. */
- os_tsk.run->state = READY;
- rt_put_prio (&os_rdy, os_tsk.run);
- rt_dispatch (NULL);
- }
- }
- return (OS_R_OK);
-}
-
-
-/*--------------------------- rt_sys_init -----------------------------------*/
-
-#ifdef __CMSIS_RTOS
-void rt_sys_init (void) {
-#else
-void rt_sys_init (FUNCP first_task, U32 prio_stksz, void *stk) {
-#endif
- /* Initialize system and start up task declared with "first_task". */
- U32 i;
-
- DBG_INIT();
-
- /* Initialize dynamic memory and task TCB pointers to NULL. */
- for (i = 0U; i < os_maxtaskrun; i++) {
- os_active_TCB[i] = NULL;
- }
- rt_init_box (mp_tcb, (U32)mp_tcb_size, sizeof(struct OS_TCB));
- rt_init_box (mp_stk, mp_stk_size, BOX_ALIGN_8 | (U16)(os_stackinfo));
- rt_init_box ((U32 *)m_tmr, (U32)mp_tmr_size, sizeof(struct OS_TMR));
-
- /* Set up TCB of idle demon */
- os_idle_TCB.task_id = 255U;
- os_idle_TCB.priv_stack = 0U;
- rt_init_context (&os_idle_TCB, 0U, os_idle_demon);
-
- /* Set up ready list: initially empty */
- os_rdy.cb_type = HCB;
- os_rdy.p_lnk = NULL;
- /* Set up delay list: initially empty */
- os_dly.cb_type = HCB;
- os_dly.p_dlnk = NULL;
- os_dly.p_blnk = NULL;
- os_dly.delta_time = 0U;
-
- /* Fix SP and system variables to assume idle task is running */
- /* Transform main program into idle task by assuming idle TCB */
-#ifndef __CMSIS_RTOS
- rt_set_PSP (os_idle_TCB.tsk_stack+32U);
-#endif
- os_tsk.run = &os_idle_TCB;
- os_tsk.run->state = RUNNING;
-
- /* Initialize ps queue */
- os_psq->first = 0U;
- os_psq->last = 0U;
- os_psq->size = os_fifo_size;
-
- rt_init_robin ();
-
-#ifndef __CMSIS_RTOS
- /* Initialize SVC and PendSV */
- rt_svc_init ();
-
- /* Initialize and start system clock timer */
- os_tick_irqn = os_tick_init ();
- if (os_tick_irqn >= 0) {
- OS_X_INIT((U32)os_tick_irqn);
- }
-
- /* Start up first user task before entering the endless loop */
- rt_tsk_create (first_task, prio_stksz, stk, NULL);
-#endif
-}
-
-
-/*--------------------------- rt_sys_start ----------------------------------*/
-
-#ifdef __CMSIS_RTOS
-void rt_sys_start (void) {
- /* Start system */
-
- /* Initialize SVC and PendSV */
- rt_svc_init ();
-
- /* Initialize and start system clock timer */
- os_tick_irqn = os_tick_init ();
- if (os_tick_irqn >= 0) {
- OS_X_INIT((U32)os_tick_irqn);
- }
-}
-#endif
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_Task.h b/rtos/rtx/TARGET_CORTEX_A/rt_Task.h
deleted file mode 100644
index b44ab55c0d..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_Task.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_TASK.H
- * Purpose: Task functions and system start up.
- * Rev.: V4.79
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-/* Definitions */
-
-/* Values for 'state' */
-#define INACTIVE 0U
-#define READY 1U
-#define RUNNING 2U
-#define WAIT_DLY 3U
-#define WAIT_ITV 4U
-#define WAIT_OR 5U
-#define WAIT_AND 6U
-#define WAIT_SEM 7U
-#define WAIT_MBX 8U
-#define WAIT_MUT 9U
-
-/* Return codes */
-#define OS_R_TMO 0x01U
-#define OS_R_EVT 0x02U
-#define OS_R_SEM 0x03U
-#define OS_R_MBX 0x04U
-#define OS_R_MUT 0x05U
-
-#define OS_R_OK 0x00U
-#define OS_R_NOK 0xFFU
-
-/* Variables */
-extern struct OS_TSK os_tsk;
-extern struct OS_TCB os_idle_TCB;
-
-/* Functions */
-extern void rt_switch_req (P_TCB p_new);
-extern void rt_dispatch (P_TCB next_TCB);
-extern void rt_block (U16 timeout, U8 block_state);
-extern void rt_tsk_pass (void);
-extern OS_TID rt_tsk_self (void);
-extern OS_RESULT rt_tsk_prio (OS_TID task_id, U8 new_prio);
-extern OS_TID rt_tsk_create (FUNCP task, U32 prio_stksz, void *stk, void *argv);
-extern OS_RESULT rt_tsk_delete (OS_TID task_id);
-#ifdef __CMSIS_RTOS
-extern void rt_sys_init (void);
-extern void rt_sys_start (void);
-#else
-extern void rt_sys_init (FUNCP first_task, U32 prio_stksz, void *stk);
-#endif
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_Time.c b/rtos/rtx/TARGET_CORTEX_A/rt_Time.c
deleted file mode 100644
index 9b02dd5d26..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_Time.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_TIME.C
- * Purpose: Delay and interval wait functions
- * Rev.: V4.79
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-#include "rt_TypeDef.h"
-#include "RTX_Config.h"
-#include "rt_Task.h"
-#include "rt_Time.h"
-
-/*----------------------------------------------------------------------------
- * Global Variables
- *---------------------------------------------------------------------------*/
-
-/* Free running system tick counter */
-U32 os_time;
-
-
-/*----------------------------------------------------------------------------
- * Functions
- *---------------------------------------------------------------------------*/
-
-
-/*--------------------------- rt_time_get -----------------------------------*/
-
-U32 rt_time_get (void) {
- /* Get system time tick */
- return (os_time);
-}
-
-
-/*--------------------------- rt_dly_wait -----------------------------------*/
-
-void rt_dly_wait (U16 delay_time) {
- /* Delay task by "delay_time" */
- rt_block (delay_time, WAIT_DLY);
-}
-
-
-/*--------------------------- rt_itv_set ------------------------------------*/
-
-void rt_itv_set (U16 interval_time) {
- /* Set interval length and define start of first interval */
- os_tsk.run->interval_time = interval_time;
- os_tsk.run->delta_time = interval_time + (U16)os_time;
-}
-
-
-/*--------------------------- rt_itv_wait -----------------------------------*/
-
-void rt_itv_wait (void) {
- /* Wait for interval end and define start of next one */
- U16 delta;
-
- delta = os_tsk.run->delta_time - (U16)os_time;
- os_tsk.run->delta_time += os_tsk.run->interval_time;
- if ((delta & 0x8000U) == 0U) {
- rt_block (delta, WAIT_ITV);
- }
-}
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_Time.h b/rtos/rtx/TARGET_CORTEX_A/rt_Time.h
deleted file mode 100644
index e02983d3ce..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_Time.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_TIME.H
- * Purpose: Delay and interval wait functions definitions
- * Rev.: V4.70
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-/* Variables */
-extern U32 os_time;
-
-/* Functions */
-extern U32 rt_time_get (void);
-extern void rt_dly_wait (U16 delay_time);
-extern void rt_itv_set (U16 interval_time);
-extern void rt_itv_wait (void);
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_Timer.h b/rtos/rtx/TARGET_CORTEX_A/rt_Timer.h
deleted file mode 100644
index 3db3e0a67f..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_Timer.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_TIMER.H
- * Purpose: User timer functions
- * Rev.: V4.70
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-/* Variables */
-extern struct OS_XTMR os_tmr;
-
-/* Functions */
-extern void rt_tmr_tick (void);
-extern OS_ID rt_tmr_create (U16 tcnt, U16 info);
-extern OS_ID rt_tmr_kill (OS_ID timer);
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
diff --git a/rtos/rtx/TARGET_CORTEX_A/rt_TypeDef.h b/rtos/rtx/TARGET_CORTEX_A/rt_TypeDef.h
deleted file mode 100644
index 09f3e0369c..0000000000
--- a/rtos/rtx/TARGET_CORTEX_A/rt_TypeDef.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*----------------------------------------------------------------------------
- * CMSIS-RTOS - RTX
- *----------------------------------------------------------------------------
- * Name: RT_TYPEDEF.H
- * Purpose: Type Definitions
- * Rev.: V4.79 (plus large stack)
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-/* Types */
-typedef char S8;
-typedef unsigned char U8;
-typedef short S16;
-typedef unsigned short U16;
-typedef int S32;
-typedef unsigned int U32;
-typedef long long S64;
-typedef unsigned long long U64;
-typedef unsigned char BIT;
-typedef unsigned int BOOL;
-typedef void (*FUNCP)(void);
-
-typedef U32 OS_TID;
-typedef void *OS_ID;
-typedef U32 OS_RESULT;
-
-typedef struct OS_TCB {
- /* General part: identical for all implementations. */
- U8 cb_type; /* Control Block Type */
- U8 state; /* Task state */
- U8 prio; /* Execution priority */
- U8 task_id; /* Task ID value for optimized TCB access */
- struct OS_TCB *p_lnk; /* Link pointer for ready/sem. wait list */
- struct OS_TCB *p_rlnk; /* Link pointer for sem./mbx lst backwards */
- struct OS_TCB *p_dlnk; /* Link pointer for delay list */
- struct OS_TCB *p_blnk; /* Link pointer for delay list backwards */
- U16 delta_time; /* Time until time out */
- U16 interval_time; /* Time interval for periodic waits */
- U16 events; /* Event flags */
- U16 waits; /* Wait flags */
- void **msg; /* Direct message passing when task waits */
- struct OS_MUCB *p_mlnk; /* Link pointer for mutex owner list */
- U8 prio_base; /* Base priority */
-
- /* Hardware dependant part: specific for Cortex processor */
- U8 stack_frame; /* Stack frame: 0x0 Basic, 0x1 Extended, 0x2 VFP/D16 stacked, 0x4 NEON/D32 stacked */
-#if defined (__ICCARM__)
-#ifndef __LARGE_PRIV_STACK
- U16 priv_stack; /* Private stack size, 0= system assigned */
-#else
- U16 reserved; /* Reserved (padding) */
- U32 priv_stack; /* Private stack size for LARGE_STACK, 0= system assigned */
-#endif /* __LARGE_PRIV_STACK */
-#else
- U16 reserved; /* Reserved (padding) */
- U32 priv_stack; /* Private stack size for LARGE_STACK, 0= system assigned */
-#endif
- U32 tsk_stack; /* Current task Stack pointer (R13) */
- U32 *stack; /* Pointer to Task Stack memory block */
-
- /* Task entry point used for uVision debugger */
- FUNCP ptask; /* Task entry address */
- void *argv; /* Task argument */
-} *P_TCB;
-#define TCB_TID 3 /* 'task id' offset */
-#define TCB_STACKF 37 /* 'stack_frame' offset */
-#if defined (__ICCARM__)
-#ifndef __LARGE_PRIV_STACK
-#define TCB_TSTACK 40 /* 'tsk_stack' offset */
-#else
-#define TCB_TSTACK 44 /* 'tsk_stack' offset for LARGE_STACK */
-#endif /* __LARGE_PRIV_STACK */
-#else
-#define TCB_TSTACK 44 /* 'tsk_stack' offset for LARGE_STACK */
-#endif
-
-typedef struct OS_PSFE { /* Post Service Fifo Entry */
- void *id; /* Object Identification */
- U32 arg; /* Object Argument */
-} *P_PSFE;
-
-typedef struct OS_PSQ { /* Post Service Queue */
- U8 first; /* FIFO Head Index */
- U8 last; /* FIFO Tail Index */
- U8 count; /* Number of stored items in FIFO */
- U8 size; /* FIFO Size */
- struct OS_PSFE q[1]; /* FIFO Content */
-} *P_PSQ;
-
-typedef struct OS_TSK {
- P_TCB run; /* Current running task */
- P_TCB new_tsk; /* Scheduled task to run */
-} *P_TSK;
-
-typedef struct OS_ROBIN { /* Round Robin Control */
- P_TCB task; /* Round Robin task */
- U16 time; /* Round Robin switch time */
- U16 tout; /* Round Robin timeout */
-} *P_ROBIN;
-
-typedef struct OS_XCB {
- U8 cb_type; /* Control Block Type */
- struct OS_TCB *p_lnk; /* Link pointer for ready/sem. wait list */
- struct OS_TCB *p_rlnk; /* Link pointer for sem./mbx lst backwards */
- struct OS_TCB *p_dlnk; /* Link pointer for delay list */
- struct OS_TCB *p_blnk; /* Link pointer for delay list backwards */
- U16 delta_time; /* Time until time out */
-} *P_XCB;
-
-typedef struct OS_MCB {
- U8 cb_type; /* Control Block Type */
- U8 state; /* State flag variable */
- U8 isr_st; /* State flag variable for isr functions */
- struct OS_TCB *p_lnk; /* Chain of tasks waiting for message */
- U16 first; /* Index of the message list begin */
- U16 last; /* Index of the message list end */
- U16 count; /* Actual number of stored messages */
- U16 size; /* Maximum number of stored messages */
- void *msg[1]; /* FIFO for Message pointers 1st element */
-} *P_MCB;
-
-typedef struct OS_SCB {
- U8 cb_type; /* Control Block Type */
- U8 mask; /* Semaphore token mask */
- U16 tokens; /* Semaphore tokens */
- struct OS_TCB *p_lnk; /* Chain of tasks waiting for tokens */
-} *P_SCB;
-
-typedef struct OS_MUCB {
- U8 cb_type; /* Control Block Type */
- U16 level; /* Call nesting level */
- struct OS_TCB *p_lnk; /* Chain of tasks waiting for mutex */
- struct OS_TCB *owner; /* Mutex owner task */
- struct OS_MUCB *p_mlnk; /* Chain of mutexes by owner task */
-} *P_MUCB;
-
-typedef struct OS_XTMR {
- struct OS_TMR *next;
- U16 tcnt;
-} *P_XTMR;
-
-typedef struct OS_TMR {
- struct OS_TMR *next; /* Link pointer to Next timer */
- U16 tcnt; /* Timer delay count */
- U16 info; /* User defined call info */
-} *P_TMR;
-
-typedef struct OS_BM {
- void *free; /* Pointer to first free memory block */
- void *end; /* Pointer to memory block end */
- U32 blk_size; /* Memory block size */
-} *P_BM;
-
-/* Definitions */
-#define __TRUE 1U
-#define __FALSE 0U
-#define NULL ((void *) 0)
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/