mirror of https://github.com/ARMmbed/mbed-os.git
[LPC1549] put PINASSIGN0-15 to PINASSIGN[] on LPC15xx.h
and fixed typo on system_LPC15xx.cpull/182/head
parent
741bfc22b1
commit
5f1f6c7417
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@ -12,6 +12,7 @@
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* from CMSIS SVD File 'H2_v0.3.svd' Version 0.3,
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*
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* modified by Keil
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* modified by ytsuboi
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*******************************************************************************************************/
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@ -1029,6 +1030,9 @@ typedef struct { /*!< WWDT Structure
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*/
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typedef struct { /*!< SWM Structure */
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union {
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__IO uint32_t PINASSIGN[16];
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struct {
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__IO uint32_t PINASSIGN0; /*!< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD,
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U0_RTS, U0_CTS. */
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__IO uint32_t PINASSIGN1; /*!< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD,
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@ -1048,6 +1052,8 @@ typedef struct { /*!< SWM Structure
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__IO uint32_t PINASSIGN13; /*!< Pin assign register 13. Assign movable functions */
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__IO uint32_t PINASSIGN14; /*!< Pin assign register 14. Assign movable functions */
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__IO uint32_t PINASSIGN15; /*!< Pin assign register 15. Assign movable functions */
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};
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};
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__I uint32_t RESERVED0[96];
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__IO uint32_t PINENABLE0; /*!< Pin enable register 0. Enables fixed-pin functions */
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__IO uint32_t PINENABLE1; /*!< Pin enable register 0. Enables fixed-pin functions */
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@ -141,7 +141,7 @@
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// </e>
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//
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// <e> SCT Clock Configuration
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#define SCT_CLOCK_SETUP 0
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#define SCT_CLOCK_SETUP 1
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// <h> SCT PLL Control (SCTPLLCTRL)
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// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
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// <i> F_clkin must be in the range of 10 MHz to 25 MHz
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@ -503,7 +503,7 @@ void SystemInit (void) {
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LPC_SYSCON->PDRUNCFG &= ~(1 << 24); /* Power-up SCT PLL */
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LPC_SYSCON->SCTPLLCLKSEL = SCTPLLCLKSEL_Val; /* Select PLL Input */
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LPC_SYSCON->USBPLLCTRL = SCTPLLCTRL_Val;
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LPC_SYSCON->SCTPLLCTRL = SCTPLLCTRL_Val;
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while (!(LPC_SYSCON->SCTPLLSTAT & 0x01)); /* Wait Until PLL Locked */
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#else /* SCT clock is not used */
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LPC_SYSCON->PDRUNCFG |= (1 << 24); /* Power-down SCT PLL */
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