mirror of https://github.com/ARMmbed/mbed-os.git
Modify to support NEON for RTOS. (mbed common codes)
We modified to support NEON of CMSIS-RTOS RTX for Cortex-A9 and fixed some bugs of it.pull/1326/head
tomoyuki yamanaka
parent
7ea62c20b3
commit
5d7099994a
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@ -2,12 +2,12 @@
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* @file core_caFunc.h
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* @brief CMSIS Cortex-A Core Function Access Header File
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* @version V3.10
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* @date 9 May 2013
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* @date 30 Oct 2013
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*
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* @note
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*
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******************************************************************************/
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/* Copyright (c) 2009 - 2012 ARM LIMITED
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/* Copyright (c) 2009 - 2013 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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@ -147,8 +147,6 @@ __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
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/** \brief Set User Mode
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This function changes the processor state to User Mode
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\param [in] topOfProcStack USR/SYS Stack Pointer value to set
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*/
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__STATIC_ASM void __set_CPS_USR(void)
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{
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@ -253,7 +251,7 @@ __STATIC_INLINE uint32_t __get_CPACR(void)
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This function assigns the given value to the Coprocessor Access Control register.
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\param [in] cpacr Coporcessor Acccess Control value to set
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\param [in] cpacr Coprocessor Acccess Control value to set
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*/
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__STATIC_INLINE void __set_CPACR(uint32_t cpacr)
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{
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@ -275,7 +273,7 @@ __STATIC_INLINE uint32_t __get_CBAR() {
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/** \brief Get TTBR0
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This function returns the value of the Configuration Base Address register.
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This function returns the value of the Translation Table Base Register 0.
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\return Translation Table Base Register 0 value
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*/
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@ -286,7 +284,7 @@ __STATIC_INLINE uint32_t __get_TTBR0() {
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/** \brief Set TTBR0
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This function assigns the given value to the Coprocessor Access Control register.
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This function assigns the given value to the Translation Table Base Register 0.
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\param [in] ttbr0 Translation Table Base Register 0 value to set
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*/
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@ -309,7 +307,7 @@ __STATIC_INLINE uint32_t __get_DACR() {
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/** \brief Set DACR
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This function assigns the given value to the Coprocessor Access Control register.
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This function assigns the given value to the Domain Access Control Register.
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\param [in] dacr Domain Access Control Register value to set
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*/
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@ -325,7 +323,7 @@ __STATIC_INLINE void __set_DACR(uint32_t dacr) {
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This function assigns the given value to the System Control Register.
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\param [in] sctlr System Control Register, value to set
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\param [in] sctlr System Control Register value to set
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*/
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__STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
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{
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@ -397,9 +395,9 @@ __STATIC_INLINE void __enable_mmu(void) {
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__ISB();
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}
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/** \brief Enable MMU
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/** \brief Disable MMU
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Enable MMU
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Disable MMU
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*/
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__STATIC_INLINE void __disable_mmu(void) {
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// Clear M bit 0 to disable the MMU
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@ -477,8 +475,9 @@ __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
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__DMB(); //ensure the ordering of data cache maintenance operations and their effects
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}
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/** \brief
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* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
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/** \brief Clean and Invalidate the entire data or unified cache
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Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
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*/
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#pragma push
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#pragma arm
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@ -522,12 +521,12 @@ Dccsw CMP R0, #1
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BNE Dccisw
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MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
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B cont
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Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
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Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
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cont SUBS R9, R9, #1 // Decrement the Way number
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BGE Loop3
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SUBS R7, R7, #1 // Decrement the Set number
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BGE Loop2
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Skip ADD R10, R10, #2 // increment the cache number
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Skip ADD R10, R10, #2 // Increment the cache number
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CMP R3, R10
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BGT Loop1
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@ -539,9 +538,6 @@ Finished
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}
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#pragma pop
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/** \brief __v7_all_cache - helper function
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*/
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/** \brief Invalidate the whole D$
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@ -577,7 +573,6 @@ __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
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#error IAR Compiler support not implemented for Cortex-A
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#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
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/* GNU gcc specific functions */
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#define MODE_USR 0x10
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@ -620,14 +615,12 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
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{
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#if 1
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uint32_t result;
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__ASM volatile ("mrs %0, apsr" : "=r" (result) );
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return (result);
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register uint32_t __regAPSR;
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__ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
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#else
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register uint32_t __regAPSR __ASM("apsr");
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return(__regAPSR);
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#endif
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return(__regAPSR);
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}
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@ -694,22 +687,49 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
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\param [in] topOfProcStack USR/SYS Stack Pointer value to set
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*/
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extern void __set_PSP(uint32_t topOfProcStack);
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
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{
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__asm__ volatile (
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".ARM;"
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".eabi_attribute Tag_ABI_align8_preserved,1;"
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"BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
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"MRS R1, CPSR;"
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"CPS %0;" /* ;no effect in USR mode */
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"MOV SP, R0;"
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"MSR CPSR_c, R1;" /* ;no effect in USR mode */
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"ISB;"
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//"BX LR;"
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:
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: "i"(MODE_SYS)
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: "r0", "r1");
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return;
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}
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/** \brief Set User Mode
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This function changes the processor state to User Mode
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\param [in] topOfProcStack USR/SYS Stack Pointer value to set
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*/
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extern void __set_CPS_USR(void);
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
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{
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__asm__ volatile (
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".ARM;"
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"CPS %0;"
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//"BX LR;"
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:
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: "i"(MODE_USR)
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: );
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return;
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}
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/** \brief Enable FIQ
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This function enables FIQ interrupts by clearing the F-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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#define __enable_fault_irq __enable_fiq
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#define __enable_fault_irq() __asm__ volatile ("cpsie f")
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/** \brief Disable FIQ
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@ -717,7 +737,7 @@ extern void __set_CPS_USR(void);
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This function disables FIQ interrupts by setting the F-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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#define __disable_fault_irq __disable_fiq
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#define __disable_fault_irq() __asm__ volatile ("cpsid f")
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/** \brief Get FPSCR
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@ -825,7 +845,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
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This function assigns the given value to the Coprocessor Access Control register.
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\param [in] cpacr Coporcessor Acccess Control value to set
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\param [in] cpacr Coprocessor Acccess Control value to set
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
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{
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@ -856,7 +876,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
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/** \brief Get TTBR0
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This function returns the value of the Configuration Base Address register.
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This function returns the value of the Translation Table Base Register 0.
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\return Translation Table Base Register 0 value
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*/
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@ -872,7 +892,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
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/** \brief Set TTBR0
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This function assigns the given value to the Coprocessor Access Control register.
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This function assigns the given value to the Translation Table Base Register 0.
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\param [in] ttbr0 Translation Table Base Register 0 value to set
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*/
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@ -904,7 +924,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
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/** \brief Set DACR
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This function assigns the given value to the Coprocessor Access Control register.
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This function assigns the given value to the Domain Access Control Register.
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\param [in] dacr Domain Access Control Register value to set
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*/
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@ -924,7 +944,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr
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This function assigns the given value to the System Control Register.
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\param [in] sctlr System Control Register, value to set
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\param [in] sctlr System Control Register value to set
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
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{
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@ -1005,9 +1025,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
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__ISB();
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}
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/** \brief Enable MMU
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/** \brief Disable MMU
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Enable MMU
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Disable MMU
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
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// Clear M bit 0 to disable the MMU
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@ -1109,14 +1129,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mv
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__DMB(); //ensure the ordering of data cache maintenance operations and their effects
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}
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/** \brief
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* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
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/** \brief Clean and Invalidate the entire data or unified cache
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Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
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*/
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/** \brief __v7_all_cache - helper function
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*/
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extern void __v7_all_cache(uint32_t op);
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@ -1,14 +1,13 @@
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;/**************************************************************************//**
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; * @file core_ca_mmu.h
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; * @brief MMU Startup File for
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; * VE_A9_MP Device Series
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; * @brief MMU Startup File for A9_MP Device Series
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; * @version V1.01
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; * @date 25 March 2013
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; * @date 10 Sept 2014
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; *
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; * @note
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; *
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; ******************************************************************************/
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;/* Copyright (c) 2012 ARM LIMITED
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;/* Copyright (c) 2012-2014 ARM LIMITED
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;
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; All rights reserved.
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; Redistribution and use in source and binary forms, with or without
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@ -298,7 +297,7 @@ __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user,
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else if ((priv == RW) && (user == READ)) { ap = 0x2; }
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else if ((priv == RW) && (user == RW)) { ap = 0x3; }
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else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
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else if ((priv == READ) && (user == READ)) { ap = 0x6; }
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else if ((priv == READ) && (user == READ)) { ap = 0x7; }
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}
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else { //Simplified access
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@ -647,7 +646,7 @@ __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem,
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The function creates a section descriptor.
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Assumptions:
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- 16MB super sections not suported
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- 16MB super sections not supported
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- TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
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- Functions always return 0
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