diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/stm32l5xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/stm32l5xx_hal_conf.h
index cd47676670..3725c0ca74 100644
--- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/stm32l5xx_hal_conf.h
+++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/stm32l5xx_hal_conf.h
@@ -414,17 +414,7 @@
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t *file, uint32_t line);
+#include "stm32_assert.h" // MBED patch
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/system_stm32l5xx.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/system_stm32l5xx.c
index 9c70c55b01..97a1a8117a 100644
--- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/system_stm32l5xx.c
+++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/system_stm32l5xx.c
@@ -197,6 +197,9 @@ void SystemInit(void)
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+#include "nvic_addr.h" // MBED
+ SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; // MBED
#endif
}
diff --git a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/TOOLCHAIN_ARM_STD/startup_stm32l552xx.S b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/TOOLCHAIN_ARM_STD/startup_stm32l552xx.S
index 90682f13ea..4f4ae36e35 100644
--- a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/TOOLCHAIN_ARM_STD/startup_stm32l552xx.S
+++ b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/TOOLCHAIN_ARM_STD/startup_stm32l552xx.S
@@ -23,31 +23,6 @@
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
-
PRESERVE8
THUMB
@@ -59,7 +34,8 @@ __heap_limit
EXPORT __Vectors_End
EXPORT __Vectors_Size
-__Vectors DCD __initial_sp ; Top of Stack
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
@@ -480,28 +456,6 @@ ICACHE_IRQHandler
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap PROC
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDP
-
- ALIGN
-
- ENDIF
END
diff --git a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/TOOLCHAIN_ARM_STD/stm32l552xx.sct b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/TOOLCHAIN_ARM_STD/stm32l552xx.sct
new file mode 100644
index 0000000000..50f930c713
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/TOOLCHAIN_ARM_STD/stm32l552xx.sct
@@ -0,0 +1,53 @@
+#! armcc -E
+; Scatter-Loading Description File
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2016-2020 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+#include "../cmsis_nvic.h"
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE {
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
+ }
+
+ ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; Stack region growing down
+ }
+}
diff --git a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/TOOLCHAIN_GCC_ARM/startup_stm32l552xx.S b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/TOOLCHAIN_GCC_ARM/startup_stm32l552xx.S
index d060895297..1f58d8f934 100644
--- a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/TOOLCHAIN_GCC_ARM/startup_stm32l552xx.S
+++ b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/TOOLCHAIN_GCC_ARM/startup_stm32l552xx.S
@@ -92,10 +92,8 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl main
+ bl _start
+ bx lr
LoopForever:
b LoopForever
diff --git a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/TOOLCHAIN_GCC_ARM/stm32l552xx.ld b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/TOOLCHAIN_GCC_ARM/stm32l552xx.ld
new file mode 100644
index 0000000000..fd05c82aaf
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/TOOLCHAIN_GCC_ARM/stm32l552xx.ld
@@ -0,0 +1,206 @@
+/* Linker script to configure memory regions. */
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#include "../cmsis_nvic.h"
+
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* Location counter can end up 2byte aligned with narrow Thumb code but
+ __etext is assumed by startup code to be the LMA of a section in RAM
+ which must be 8-byte aligned */
+ __etext = ALIGN (8);
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(8);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(8);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(8);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(8);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ /* Uninitialized data section
+ * This region is not initialized by the C/C++ library and can be used to
+ * store state across soft reboots. */
+ .uninitialized (NOLOAD):
+ {
+ . = ALIGN(32);
+ __uninitialized_start = .;
+ *(.uninitialized)
+ KEEP(*(.keep.uninitialized))
+ . = ALIGN(32);
+ __uninitialized_end = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(8);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ *(.heap*)
+ . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE;
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/TOOLCHAIN_IAR/stm32l552xx.icf b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/TOOLCHAIN_IAR/stm32l552xx.icf
new file mode 100644
index 0000000000..b269939227
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/TOOLCHAIN_IAR/stm32l552xx.icf
@@ -0,0 +1,59 @@
+/* Linker script to configure memory regions.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+/* Device specific values */
+
+/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */
+
+define symbol VECTORS = 124; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
+define symbol HEAP_SIZE = 0x10000;
+
+/* Common - Do not change */
+
+if (!isdefinedsymbol(MBED_APP_START)) {
+ define symbol MBED_APP_START = MBED_ROM_START;
+}
+
+if (!isdefinedsymbol(MBED_APP_SIZE)) {
+ define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
+}
+
+if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ define symbol MBED_BOOT_STACK_SIZE = 0x400;
+}
+
+/* Round up VECTORS_SIZE to 8 bytes */
+define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7;
+define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE;
+define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE];
+define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE];
+
+define block CSTACK with alignment = 8, size = MBED_BOOT_STACK_SIZE { };
+define block HEAP with alignment = 8, size = HEAP_SIZE { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem: MBED_APP_START { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
diff --git a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/cmsis_nvic.h
new file mode 100644
index 0000000000..5678ba435b
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L552xx/cmsis_nvic.h
@@ -0,0 +1,41 @@
+/* mbed Microcontroller Library
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#if !defined(MBED_ROM_START)
+#define MBED_ROM_START 0x8000000
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+#define MBED_ROM_SIZE 0x80000 // 512 KB
+ // 0x40000 STM32L552CCTx STM32L552RCTx STM32L552QCIxQ STM32L552ZCTxQ STM32L552CCUx STM32L552VCTxQ
+ // 0x80000 STM32L552CEUx STM32L552MEYxP STM32L552MEYxQ STM32L552RETx STM32L552ZETx STM32L552QEIxQ STM32L552VETxQ STM32L552QEIxP STM32L552CETx STM32L552CETxP STM32L552QEIx STM32L552ZETxQ STM32L552VETx STM32L552RETxP STM32L552RETxQ STM32L552CEUxP
+#endif
+
+#if !defined(MBED_RAM_START)
+#define MBED_RAM_START 0x20000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+#define MBED_RAM_SIZE 0x40000 // 256 KB
+#endif
+
+#define NVIC_NUM_VECTORS 124
+#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/TOOLCHAIN_ARM_STD/startup_stm32l562xx.S b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/TOOLCHAIN_ARM_STD/startup_stm32l562xx.S
index 19744ffec1..6bcaa4cad2 100644
--- a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/TOOLCHAIN_ARM_STD/startup_stm32l562xx.S
+++ b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/TOOLCHAIN_ARM_STD/startup_stm32l562xx.S
@@ -23,31 +23,6 @@
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
-
PRESERVE8
THUMB
@@ -59,7 +34,8 @@ __heap_limit
EXPORT __Vectors_End
EXPORT __Vectors_Size
-__Vectors DCD __initial_sp ; Top of Stack
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
@@ -486,28 +462,6 @@ OTFDEC1_IRQHandler
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap PROC
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDP
-
- ALIGN
-
- ENDIF
END
diff --git a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/TOOLCHAIN_ARM_STD/stm32l562xx.sct b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/TOOLCHAIN_ARM_STD/stm32l562xx.sct
new file mode 100644
index 0000000000..50f930c713
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/TOOLCHAIN_ARM_STD/stm32l562xx.sct
@@ -0,0 +1,53 @@
+#! armcc -E
+; Scatter-Loading Description File
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2016-2020 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+#include "../cmsis_nvic.h"
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE {
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
+ }
+
+ ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; Stack region growing down
+ }
+}
diff --git a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/TOOLCHAIN_GCC_ARM/startup_stm32l562xx.S b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/TOOLCHAIN_GCC_ARM/startup_stm32l562xx.S
index ffc08ebdc0..8cf9f0728a 100644
--- a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/TOOLCHAIN_GCC_ARM/startup_stm32l562xx.S
+++ b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/TOOLCHAIN_GCC_ARM/startup_stm32l562xx.S
@@ -92,10 +92,8 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl main
+ bl _start
+ bx lr
LoopForever:
b LoopForever
diff --git a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/TOOLCHAIN_GCC_ARM/stm32l562xx.ld b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/TOOLCHAIN_GCC_ARM/stm32l562xx.ld
new file mode 100644
index 0000000000..fd05c82aaf
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/TOOLCHAIN_GCC_ARM/stm32l562xx.ld
@@ -0,0 +1,206 @@
+/* Linker script to configure memory regions. */
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#include "../cmsis_nvic.h"
+
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* Location counter can end up 2byte aligned with narrow Thumb code but
+ __etext is assumed by startup code to be the LMA of a section in RAM
+ which must be 8-byte aligned */
+ __etext = ALIGN (8);
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(8);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(8);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(8);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(8);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ /* Uninitialized data section
+ * This region is not initialized by the C/C++ library and can be used to
+ * store state across soft reboots. */
+ .uninitialized (NOLOAD):
+ {
+ . = ALIGN(32);
+ __uninitialized_start = .;
+ *(.uninitialized)
+ KEEP(*(.keep.uninitialized))
+ . = ALIGN(32);
+ __uninitialized_end = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(8);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ *(.heap*)
+ . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE;
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/TOOLCHAIN_IAR/stm32l562xx.icf b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/TOOLCHAIN_IAR/stm32l562xx.icf
new file mode 100644
index 0000000000..cd58e042d5
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/TOOLCHAIN_IAR/stm32l562xx.icf
@@ -0,0 +1,59 @@
+/* Linker script to configure memory regions.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+/* Device specific values */
+
+/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */
+
+define symbol VECTORS = 125; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
+define symbol HEAP_SIZE = 0x10000;
+
+/* Common - Do not change */
+
+if (!isdefinedsymbol(MBED_APP_START)) {
+ define symbol MBED_APP_START = MBED_ROM_START;
+}
+
+if (!isdefinedsymbol(MBED_APP_SIZE)) {
+ define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
+}
+
+if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ define symbol MBED_BOOT_STACK_SIZE = 0x400;
+}
+
+/* Round up VECTORS_SIZE to 8 bytes */
+define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7;
+define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE;
+define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE];
+define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE];
+
+define block CSTACK with alignment = 8, size = MBED_BOOT_STACK_SIZE { };
+define block HEAP with alignment = 8, size = HEAP_SIZE { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem: MBED_APP_START { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
diff --git a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/cmsis_nvic.h
new file mode 100644
index 0000000000..5e4c782071
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xx/cmsis_nvic.h
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#if !defined(MBED_ROM_START)
+#define MBED_ROM_START 0x8000000
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+#define MBED_ROM_SIZE 0x80000 // 512 KB
+#endif
+
+#if !defined(MBED_RAM_START)
+#define MBED_RAM_START 0x20000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+#define MBED_RAM_SIZE 0x40000 // 256 KB
+#endif
+
+#define NVIC_NUM_VECTORS 125
+#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
+
+#endif