ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #206 from dreschpe/master 

Fix SPI 16 Bit for ST Nucleo
pull/207/head
Bogdan Marinescu 2014-03-11 11:56:20 +00:00
parent 8055bca0d6 ad09a83642
commit 5d2d302526
7 changed files with 103 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h
View File

@ -678,15 +678,15 @@ USB_OTG_HostChannelTypeDef;
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(96 KB) base address in the alias region */
//#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
//#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(96 KB) base address in the bit-band region */
//#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
//#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h
View File

@ -99,7 +99,7 @@
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External crystal in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)

22
libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/spi_api.c
View File

@ -215,13 +215,19 @@ static inline int ssp_writeable(spi_t *obj) {
static inline void ssp_write(spi_t *obj, int value) {
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
while (!ssp_writeable(obj));
SPI_SendData8(spi, (uint8_t)value);
if(obj->bits == SPI_DATASIZE_8BIT) // 8 bit mode
SPI_SendData8(spi, (uint8_t)value);
else
SPI_I2S_SendData16(spi, (uint16_t)value);
}
static inline int ssp_read(spi_t *obj) {
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
while (!ssp_readable(obj));
return (int)SPI_ReceiveData8(spi);
if(obj->bits == SPI_DATASIZE_8BIT) // 8 bit mode
return (int)SPI_ReceiveData8(spi);
else // 16 bit mode
return (int)SPI_I2S_ReceiveData16(spi);
}
static inline int ssp_busy(spi_t *obj) {
@ -242,13 +248,19 @@ int spi_slave_receive(spi_t *obj) {
int spi_slave_read(spi_t *obj) {
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
return (int)SPI_ReceiveData8(spi);
if(obj->bits == SPI_DATASIZE_8BIT) // 8 bit mode
return (int)SPI_ReceiveData8(spi);
else
return (int)SPI_I2S_ReceiveData16(spi);
}
void spi_slave_write(spi_t *obj, int value) {
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
while (!ssp_writeable(obj));
SPI_SendData8(spi, (uint8_t)value);
while (!ssp_writeable(obj));
if(obj->bits == SPI_DATASIZE_8BIT) // 8 bit mode
SPI_SendData8(spi, (uint8_t)value);
else
SPI_I2S_SendData16(spi, (uint16_t)value);
}
int spi_busy(spi_t *obj) {

7
libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h
View File

@ -44,6 +44,7 @@ typedef enum {
typedef enum {
UART_1 = (int)USART1_BASE,
UART_2 = (int)USART2_BASE
UART_3 = (int)USART6_BASE,
} UARTName;
#define STDIO_UART_TX PA_2
@ -52,12 +53,14 @@ typedef enum {
typedef enum {
SPI_1 = (int)SPI1_BASE,
SPI_2 = (int)SPI2_BASE
SPI_2 = (int)SPI2_BASE,
SPI_3 = (int)SPI3_BASE
} SPIName;
typedef enum {
I2C_1 = (int)I2C1_BASE,
I2C_2 = (int)I2C2_BASE
I2C_2 = (int)I2C2_BASE,
I2C_3 = (int)I2C3_BASE
} I2CName;
typedef enum {

19
libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/i2c_api.c
View File

@ -44,11 +44,15 @@
static const PinMap PinMap_I2C_SDA[] = {
{PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
{PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
{NC, NC, 0}
};
static const PinMap PinMap_I2C_SCL[] = {
{PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
{PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
{NC, NC, 0}
};
@ -69,6 +73,13 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
if (obj->i2c == I2C_1) {
__I2C1_CLK_ENABLE();
}
if (obj->i2c == I2C_2) {
__I2C2_CLK_ENABLE();
}
if (obj->i2c == I2C_3) {
__I2C3_CLK_ENABLE();
}
// Configure I2C pins
pinmap_pinout(sda, PinMap_I2C_SDA);
@ -207,6 +218,14 @@ void i2c_reset(i2c_t *obj) {
__I2C1_FORCE_RESET();
__I2C1_RELEASE_RESET();
}
if (obj->i2c == I2C_2) {
__I2C2_FORCE_RESET();
__I2C2_RELEASE_RESET();
}
if (obj->i2c == I2C_3) {
__I2C3_FORCE_RESET();
__I2C3_RELEASE_RESET();
}
}
#if DEVICE_I2CSLAVE

14
libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/serial_api.c
View File

@ -37,16 +37,18 @@
static const PinMap PinMap_UART_TX[] = {
{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
{PC_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
{NC, NC, 0}
};
static const PinMap PinMap_UART_RX[] = {
{PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
{PC_7, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
{NC, NC, 0}
};
#define UART_NUM (2)
#define UART_NUM (3)
static uint32_t serial_irq_ids[UART_NUM] = {0};
@ -89,6 +91,9 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
if (obj->uart == UART_2) {
__USART2_CLK_ENABLE();
}
if (obj->uart == UART_3) {
__USART6_CLK_ENABLE();
}
// Configure the UART pins
pinmap_pinout(tx, PinMap_UART_TX);
@ -107,6 +112,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
// The index is used by irq
if (obj->uart == UART_1) obj->index = 0;
if (obj->uart == UART_2) obj->index = 1;
if (obj->uart == UART_3) obj->index = 2;
// For stdio management
if (obj->uart == STDIO_UART) {
@ -180,6 +186,7 @@ static void uart_irq(UARTName name, int id) {
// Not part of mbed api
static void uart1_irq(void) {uart_irq(UART_1, 0);}
static void uart2_irq(void) {uart_irq(UART_2, 1);}
static void uart3_irq(void) {uart_irq(UART_3, 2);}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
irq_handler = handler;
@ -202,6 +209,11 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
vector = (uint32_t)&uart2_irq;
}
if (obj->uart == UART_3) {
irq_n = USART6_IRQn;
vector = (uint32_t)&uart3_irq;
}
if (enable) {
if (irq == RxIrq) {

46
libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/spi_api.c
View File

@ -39,22 +39,42 @@
static const PinMap PinMap_SPI_MOSI[] = {
{PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
{PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
{PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
{PB_5 , SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_MISO[] = {
{PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
{PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
{PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
{PB_4 , SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_SCLK[] = {
{PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
{PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
{PB_3 , SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
{NC, NC, 0}
};
// Only used in Slave mode
static const PinMap PinMap_SPI_SSEL[] = {
{PB_6, SPI_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)}, // Generic IO, not real H/W NSS pin
{PA_4, SPI_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PA_15, SPI_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PB_9 , SPI_2, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PB_12, SPI_2, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PA_4 , SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF6_SPI3)},
{PA_15, SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF6_SPI3)},
{NC, NC, 0}
};
@ -102,11 +122,20 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
if (obj->spi == SPI_1) {
__SPI1_CLK_ENABLE();
}
if (obj->spi == SPI_2) {
__SPI2_CLK_ENABLE();
}
if (obj->spi == SPI_3) {
__SPI3_CLK_ENABLE();
}
// Configure the SPI pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) { // slave mode
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
// Save new values
obj->bits = SPI_DATASIZE_8BIT;
@ -114,7 +143,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
obj->cpha = SPI_PHASE_1EDGE;
obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 1MHz (with HSI=16MHz and APB2CLKDivider=2)
if (ssel == NC) { // Master
if (ssel == NC) { // SW NSS Master mode
obj->mode = SPI_MODE_MASTER;
obj->nss = SPI_NSS_SOFT;
}
@ -174,8 +203,15 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
void spi_frequency(spi_t *obj, int hz) {
// Get SPI clock frequency
uint32_t PCLK = SystemCoreClock >> 1;
// SPI1 runs from PCLK2, which runs at SystemCoreClock / 2. SPI2 and SPI3
// run from PCLK1, which runs at SystemCoreClock / 4.
uint32_t PCLK = SystemCoreClock;
switch ((int)obj->spi) {
case SPI_1: PCLK = PCLK >> 1; break;
case SPI_2: PCLK = PCLK >> 2; break;
case SPI_3: PCLK = PCLK >> 2; break;
}
// Choose the baud rate divisor (between 2 and 256)
uint32_t divisor = PCLK / hz;
@ -215,7 +251,9 @@ static inline int ssp_writeable(spi_t *obj) {
static inline void ssp_write(spi_t *obj, int value) {
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
while (!ssp_writeable(obj));
spi->DR = (uint8_t)value;
if(obj->bits == SPI_DATASIZE_8BIT)
spi->DR = (uint8_t)value; // 8 bit mode
else spi->DR = (uint16_t)value; // 16 bit mode
}
static inline int ssp_read(spi_t *obj) {