From 5c47eb4b20091aa290d94b710a427b12179253d8 Mon Sep 17 00:00:00 2001 From: Volodymyr Medvid Date: Fri, 25 Jan 2019 19:03:57 -0800 Subject: [PATCH] PSOC6: add BSP generated sources for Cypress kits Code generated for pioneer kits: * CY8CKIT-062-4343W * CY8CKIT-062-BLE * CY8CKIT-WIFI-BT Prototyping boards: * CY8CPROTO-062-4343W The source is generated with ModusToolbox Device Configurator. The origin design.modus files used to produce the GeneratedSource will be submitted in the consequent pull requests. --- .../GeneratedSource/cycfg.c | 34 + .../GeneratedSource/cycfg.h | 47 + .../GeneratedSource/cycfg_clocks.c | 49 + .../GeneratedSource/cycfg_clocks.h | 53 + .../GeneratedSource/cycfg_connectivity.c | 39 + .../GeneratedSource/cycfg_connectivity.h | 76 ++ .../GeneratedSource/cycfg_notices.h | 30 + .../GeneratedSource/cycfg_peripherals.c | 219 ++++ .../GeneratedSource/cycfg_peripherals.h | 148 +++ .../GeneratedSource/cycfg_pins.c | 883 ++++++++++++++ .../GeneratedSource/cycfg_pins.h | 571 +++++++++ .../GeneratedSource/cycfg_platform.c | 567 +++++++++ .../GeneratedSource/cycfg_platform.h | 53 + .../GeneratedSource/cycfg.c | 34 + .../GeneratedSource/cycfg.h | 47 + .../GeneratedSource/cycfg_clocks.c | 45 + .../GeneratedSource/cycfg_clocks.h | 51 + .../GeneratedSource/cycfg_connectivity.c | 39 + .../GeneratedSource/cycfg_connectivity.h | 64 + .../GeneratedSource/cycfg_notices.h | 30 + .../GeneratedSource/cycfg_peripherals.c | 108 ++ .../GeneratedSource/cycfg_peripherals.h | 128 ++ .../GeneratedSource/cycfg_pins.c | 595 ++++++++++ .../GeneratedSource/cycfg_pins.h | 396 +++++++ .../GeneratedSource/cycfg_platform.c | 506 ++++++++ .../GeneratedSource/cycfg_platform.h | 53 + .../GeneratedSource/cycfg.c | 34 + .../GeneratedSource/cycfg.h | 48 + .../GeneratedSource/cycfg_clocks.c | 53 + .../GeneratedSource/cycfg_clocks.h | 55 + .../GeneratedSource/cycfg_connectivity.c | 51 + .../GeneratedSource/cycfg_connectivity.h | 89 ++ .../GeneratedSource/cycfg_dmas.c | 179 +++ .../GeneratedSource/cycfg_dmas.h | 67 ++ .../GeneratedSource/cycfg_notices.h | 30 + .../GeneratedSource/cycfg_peripherals.c | 204 ++++ .../GeneratedSource/cycfg_peripherals.h | 140 +++ .../GeneratedSource/cycfg_pins.c | 883 ++++++++++++++ .../GeneratedSource/cycfg_pins.h | 571 +++++++++ .../GeneratedSource/cycfg_platform.c | 557 +++++++++ .../GeneratedSource/cycfg_platform.h | 53 + .../GeneratedSource/cycfg.c | 34 + .../GeneratedSource/cycfg.h | 47 + .../GeneratedSource/cycfg_clocks.c | 45 + .../GeneratedSource/cycfg_clocks.h | 51 + .../GeneratedSource/cycfg_connectivity.c | 39 + .../GeneratedSource/cycfg_connectivity.h | 75 ++ .../GeneratedSource/cycfg_notices.h | 30 + .../GeneratedSource/cycfg_peripherals.c | 187 +++ .../GeneratedSource/cycfg_peripherals.h | 138 +++ .../GeneratedSource/cycfg_pins.c | 811 +++++++++++++ .../GeneratedSource/cycfg_pins.h | 529 +++++++++ .../GeneratedSource/cycfg_platform.c | 516 ++++++++ .../GeneratedSource/cycfg_platform.h | 52 + .../GeneratedSource/cycfg.c | 34 + .../GeneratedSource/cycfg.h | 48 + .../GeneratedSource/cycfg_clocks.c | 53 + .../GeneratedSource/cycfg_clocks.h | 55 + .../GeneratedSource/cycfg_connectivity.c | 51 + .../GeneratedSource/cycfg_connectivity.h | 93 ++ .../GeneratedSource/cycfg_dmas.c | 179 +++ .../GeneratedSource/cycfg_dmas.h | 67 ++ .../GeneratedSource/cycfg_notices.h | 30 + .../GeneratedSource/cycfg_peripherals.c | 204 ++++ .../GeneratedSource/cycfg_peripherals.h | 140 +++ .../GeneratedSource/cycfg_pins.c | 1045 +++++++++++++++++ .../GeneratedSource/cycfg_pins.h | 663 +++++++++++ .../GeneratedSource/cycfg_platform.c | 571 +++++++++ .../GeneratedSource/cycfg_platform.h | 53 + 69 files changed, 13719 insertions(+) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_clocks.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_clocks.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_connectivity.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_connectivity.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_notices.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_peripherals.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_peripherals.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_pins.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_pins.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_platform.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_platform.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_connectivity.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_connectivity.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_notices.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_connectivity.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_connectivity.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_notices.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_connectivity.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_connectivity.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_notices.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_connectivity.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_connectivity.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_dmas.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_dmas.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_notices.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg.c new file mode 100644 index 0000000000..cf7ac0229a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg.c @@ -0,0 +1,34 @@ +/******************************************************************************* +* File Name: cycfg.c +* +* Description: +* Wrapper function to initialize all generated code. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg.h" + +void init_cycfg_all(void) +{ + init_cycfg_clocks(); + init_cycfg_peripherals(); + init_cycfg_pins(); + init_cycfg_platform(); + init_cycfg_connectivity(); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg.h new file mode 100644 index 0000000000..68bb40bf09 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg.h @@ -0,0 +1,47 @@ +/******************************************************************************* +* File Name: cycfg.h +* +* Description: +* Simple wrapper header containing all generated files. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_H) +#define CYCFG_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +#include "cycfg_clocks.h" +#include "cycfg_peripherals.h" +#include "cycfg_pins.h" +#include "cycfg_platform.h" +#include "cycfg_connectivity.h" + +void init_cycfg_all(void); + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_clocks.c new file mode 100644 index 0000000000..e14461b9aa --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_clocks.c @@ -0,0 +1,49 @@ +/******************************************************************************* +* File Name: cycfg_clocks.c +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_clocks.h" + + +void init_cycfg_clocks(void) +{ + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 108U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 1U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 255U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_clocks.h new file mode 100644 index 0000000000..aeee9061aa --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_clocks.h @@ -0,0 +1,53 @@ +/******************************************************************************* +* File Name: cycfg_clocks.h +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_CLOCKS_H) +#define CYCFG_CLOCKS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define peri_0_div_16_0_HW CY_SYSCLK_DIV_16_BIT +#define peri_0_div_16_0_NUM 0U +#define peri_0_div_8_1_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_1_NUM 1U +#define peri_0_div_8_2_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_2_NUM 2U +#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_3_NUM 3U +#define peri_0_div_8_4_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_4_NUM 4U + +void init_cycfg_clocks(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_CLOCKS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_connectivity.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_connectivity.c new file mode 100644 index 0000000000..c389562da2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_connectivity.c @@ -0,0 +1,39 @@ +/******************************************************************************* +* File Name: cycfg_connectivity.c +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_connectivity.h" + +#include "cy_device_headers.h" + +void init_cycfg_connectivity(void) +{ + HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; + HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_connectivity.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_connectivity.h new file mode 100644 index 0000000000..a8554f2843 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_connectivity.h @@ -0,0 +1,76 @@ +/******************************************************************************* +* File Name: cycfg_connectivity.h +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_CONNECTIVITY_H) +#define CYCFG_CONNECTIVITY_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +void init_cycfg_connectivity(void); + +#define ioss_0_port_11_pin_1_HSIOM P11_1_TCPWM1_LINE_COMPL1 +#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 +#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 +#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 +#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 +#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 +#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK +#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_2_pin_0_HSIOM P2_0_SDHC0_CARD_DAT_3TO00 +#define ioss_0_port_2_pin_1_HSIOM P2_1_SDHC0_CARD_DAT_3TO01 +#define ioss_0_port_2_pin_2_HSIOM P2_2_SDHC0_CARD_DAT_3TO02 +#define ioss_0_port_2_pin_3_HSIOM P2_3_SDHC0_CARD_DAT_3TO03 +#define ioss_0_port_2_pin_4_HSIOM P2_4_SDHC0_CARD_CMD +#define ioss_0_port_2_pin_5_HSIOM P2_5_SDHC0_CLK_CARD +#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX +#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX +#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS +#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS +#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX +#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX +#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL +#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA +#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO +#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS +#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK +#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_CONNECTIVITY_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_notices.h new file mode 100644 index 0000000000..90f1013f8a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_notices.h @@ -0,0 +1,30 @@ +/******************************************************************************* +* File Name: cycfg_notices.h +* +* Description: +* Contains warnings and errors that occurred while generating code for the +* design. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_NOTICES_H) +#define CYCFG_NOTICES_H + + +#endif /* CYCFG_NOTICES_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_peripherals.c new file mode 100644 index 0000000000..74b7f028c4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_peripherals.c @@ -0,0 +1,219 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.c +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_peripherals.h" + +#define PWM_INPUT_DISABLED 0x7U +#define USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \ + CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \ + CY_USBFS_DEV_DRV_SET_EP1_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_EP2_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U)) + +cy_stc_csd_context_t cy_csd_0_context = +{ + .lockKey = CY_CSD_NONE_KEY, +}; +const cy_stc_scb_uart_config_t BT_UART_config = +{ + .uartMode = CY_SCB_UART_STANDARD, + .enableMutliProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + .oversample = 8, + .enableMsbFirst = false, + .dataWidth = 8UL, + .parity = CY_SCB_UART_PARITY_NONE, + .stopBits = CY_SCB_UART_STOP_BITS_1, + .enableInputFilter = false, + .breakWidth = 11UL, + .dropOnFrameError = false, + .dropOnParityError = false, + .receiverAddress = 0x0UL, + .receiverAddressMask = 0x0UL, + .acceptAddrInFifo = false, + .enableCts = true, + .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rtsRxFifoLevel = 63, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rxFifoTriggerLevel = 63UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, +}; +const cy_stc_scb_ezi2c_config_t CSD_COMM_config = +{ + .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS, + .slaveAddress1 = 8U, + .slaveAddress2 = 0U, + .subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS, + .enableWakeFromSleep = false, +}; +const cy_stc_scb_uart_config_t KITPROG_UART_config = +{ + .uartMode = CY_SCB_UART_STANDARD, + .enableMutliProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + .oversample = 8, + .enableMsbFirst = false, + .dataWidth = 8UL, + .parity = CY_SCB_UART_PARITY_NONE, + .stopBits = CY_SCB_UART_STOP_BITS_1, + .enableInputFilter = false, + .breakWidth = 11UL, + .dropOnFrameError = false, + .dropOnParityError = false, + .receiverAddress = 0x0UL, + .receiverAddressMask = 0x0UL, + .acceptAddrInFifo = false, + .enableCts = false, + .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rtsRxFifoLevel = 0UL, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rxFifoTriggerLevel = 63UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, +}; +cy_en_sd_host_card_capacity_t SDIO_cardCapacity = CY_SD_HOST_SDSC; +cy_en_sd_host_card_type_t SDIO_cardType = CY_SD_HOST_EMMC; +uint32_t SDIO_rca = 0u; +const cy_stc_sd_host_init_config_t SDIO_config = +{ + .emmc = true, + .dmaType = CY_SD_HOST_DMA_SDMA, + .enableLedControl = false, +}; +cy_stc_sd_host_sd_card_config_t SDIO_card_cfg = +{ + .lowVoltageSignaling = false, + .busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT, + .cardType = &SDIO_cardType, + .rca = &SDIO_rca, + .cardCapacity = &SDIO_cardCapacity, +}; +const cy_stc_smif_config_t QSPI_config = +{ + .mode = (uint32_t)CY_SMIF_NORMAL, + .deselectDelay = QSPI_DESELECT_DELAY, + .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK, + .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, +}; +const cy_stc_mcwdt_config_t MCWDT0_config = +{ + .c0Match = 32768U, + .c1Match = 32768U, + .c0Mode = CY_MCWDT_MODE_NONE, + .c1Mode = CY_MCWDT_MODE_NONE, + .c2ToggleBit = 16U, + .c2Mode = CY_MCWDT_MODE_NONE, + .c0ClearOnMatch = false, + .c1ClearOnMatch = false, + .c0c1Cascade = true, + .c1c2Cascade = false, +}; +const cy_stc_rtc_config_t RTC_config = +{ + .sec = 0U, + .min = 0U, + .hour = 12U, + .amPm = CY_RTC_AM, + .hrFormat = CY_RTC_24_HOURS, + .dayOfWeek = CY_RTC_SUNDAY, + .date = 1U, + .month = CY_RTC_JANUARY, + .year = 0U, +}; +const cy_stc_tcpwm_pwm_config_t PWM_config = +{ + .pwmMode = CY_TCPWM_PWM_MODE_PWM, + .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, + .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, + .deadTimeClocks = 0, + .runMode = CY_TCPWM_PWM_CONTINUOUS, + .period0 = 32000, + .period1 = 32768, + .enablePeriodSwap = false, + .compare0 = 16384, + .compare1 = 16384, + .enableCompareSwap = false, + .interruptSources = CY_TCPWM_INT_NONE, + .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE, + .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE, + .killMode = CY_TCPWM_PWM_STOP_ON_KILL, + .swapInputMode = PWM_INPUT_DISABLED & 0x3U, + .swapInput = CY_TCPWM_INPUT_0, + .reloadInputMode = PWM_INPUT_DISABLED & 0x3U, + .reloadInput = CY_TCPWM_INPUT_0, + .startInputMode = PWM_INPUT_DISABLED & 0x3U, + .startInput = CY_TCPWM_INPUT_0, + .killInputMode = PWM_INPUT_DISABLED & 0x3U, + .killInput = CY_TCPWM_INPUT_0, + .countInputMode = PWM_INPUT_DISABLED & 0x3U, + .countInput = CY_TCPWM_INPUT_1, +}; +const cy_stc_usbfs_dev_drv_config_t USBUART_config = +{ + .mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU, + .epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR, + .epBuffer = NULL, + .epBufferSize = 0U, + .dmaConfig[0] = NULL, + .dmaConfig[1] = NULL, + .dmaConfig[2] = NULL, + .dmaConfig[3] = NULL, + .dmaConfig[4] = NULL, + .dmaConfig[5] = NULL, + .dmaConfig[6] = NULL, + .dmaConfig[7] = NULL, + .enableLpm = false, + .intrLevelSel = USBUART_INTR_LVL_SEL, +}; + + +void init_cycfg_peripherals(void) +{ + Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U); + + Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM1_CLOCKS1, CY_SYSCLK_DIV_8_BIT, 3U); + + Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_peripherals.h new file mode 100644 index 0000000000..558a12aade --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_peripherals.h @@ -0,0 +1,148 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.h +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PERIPHERALS_H) +#define CYCFG_PERIPHERALS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_csd.h" +#include "cy_scb_uart.h" +#include "cy_scb_ezi2c.h" +#include "cy_sd_host.h" +#include "cy_smif.h" +#include "cy_mcwdt.h" +#include "cy_rtc.h" +#include "cy_tcpwm_pwm.h" +#include "cycfg_connectivity.h" +#include "cy_usbfs_dev_drv.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CY_CAPSENSE_CORE 4u +#define CY_CAPSENSE_CPU_CLK 100000000u +#define CY_CAPSENSE_PERI_CLK 100000000u +#define CY_CAPSENSE_VDDA_MV 3300u +#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT +#define CY_CAPSENSE_PERI_DIV_INDEX 4u +#define Cmod_PORT GPIO_PRT7 +#define CintA_PORT GPIO_PRT7 +#define CintB_PORT GPIO_PRT7 +#define Button0_Rx0_PORT GPIO_PRT8 +#define Button0_Tx_PORT GPIO_PRT1 +#define Button1_Rx0_PORT GPIO_PRT8 +#define Button1_Tx_PORT GPIO_PRT1 +#define LinearSlider0_Sns0_PORT GPIO_PRT8 +#define LinearSlider0_Sns1_PORT GPIO_PRT8 +#define LinearSlider0_Sns2_PORT GPIO_PRT8 +#define LinearSlider0_Sns3_PORT GPIO_PRT8 +#define LinearSlider0_Sns4_PORT GPIO_PRT8 +#define Cmod_PIN 7u +#define CintA_PIN 1u +#define CintB_PIN 2u +#define Button0_Rx0_PIN 1u +#define Button0_Tx_PIN 0u +#define Button1_Rx0_PIN 2u +#define Button1_Tx_PIN 0u +#define LinearSlider0_Sns0_PIN 3u +#define LinearSlider0_Sns1_PIN 4u +#define LinearSlider0_Sns2_PIN 5u +#define LinearSlider0_Sns3_PIN 6u +#define LinearSlider0_Sns4_PIN 7u +#define Cmod_PORT_NUM 7u +#define CintA_PORT_NUM 7u +#define CintB_PORT_NUM 7u +#define CapSense_HW CSD0 +#define CapSense_IRQ csd_interrupt_IRQn +#define BT_UART_HW SCB2 +#define BT_UART_IRQ scb_2_interrupt_IRQn +#define CSD_COMM_HW SCB3 +#define CSD_COMM_IRQ scb_3_interrupt_IRQn +#define KITPROG_UART_HW SCB5 +#define KITPROG_UART_IRQ scb_5_interrupt_IRQn +#define SDIO_HW SDHC0 +#define SDIO_IRQ sdhc_0_interrupt_general_IRQn +#define QSPI_HW SMIF0 +#define QSPI_IRQ smif_interrupt_IRQn +#define QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL) +#define QSPI_RX_DATA_FIFO_UNDERFLOW (0UL) +#define QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL) +#define QSPI_TX_DATA_FIFO_OVERFLOW (0UL) +#define QSPI_RX_FIFO_TRIGEER_LEVEL (0UL) +#define QSPI_TX_FIFO_TRIGEER_LEVEL (0UL) +#define QSPI_DATALINES0_1 (1UL) +#define QSPI_DATALINES2_3 (1UL) +#define QSPI_DATALINES4_5 (0UL) +#define QSPI_DATALINES6_7 (0UL) +#define QSPI_SS0 (1UL) +#define QSPI_SS1 (0UL) +#define QSPI_SS2 (0UL) +#define QSPI_SS3 (0UL) +#define QSPI_DESELECT_DELAY 7 +#define MCWDT0_HW MCWDT_STRUCT0 +#define RTC_10_MONTH_OFFSET (28U) +#define RTC_MONTH_OFFSET (24U) +#define RTC_10_DAY_OFFSET (20U) +#define RTC_DAY_OFFSET (16U) +#define RTC_1000_YEAR_OFFSET (12U) +#define RTC_100_YEAR_OFFSET (8U) +#define RTC_10_YEAR_OFFSET (4U) +#define RTC_YEAR_OFFSET (0U) +#define PWM_HW TCPWM1 +#define PWM_NUM 1UL +#define PWM_MASK (1UL << 1) +#define USBUART_ACTIVE_ENDPOINTS_MASK 7U +#define USBUART_ENDPOINTS_BUFFER_SIZE 140U +#define USBUART_ENDPOINTS_ACCESS_TYPE 0U +#define USBUART_USB_CORE 4U +#define USBUART_HW USBFS0 +#define USBUART_HI_IRQ usb_interrupt_hi_IRQn +#define USBUART_MED_IRQ usb_interrupt_med_IRQn +#define USBUART_LO_IRQ usb_interrupt_lo_IRQn + +extern cy_stc_csd_context_t cy_csd_0_context; +extern const cy_stc_scb_uart_config_t BT_UART_config; +extern const cy_stc_scb_ezi2c_config_t CSD_COMM_config; +extern const cy_stc_scb_uart_config_t KITPROG_UART_config; +extern cy_en_sd_host_card_capacity_t SDIO_cardCapacity; +extern cy_en_sd_host_card_type_t SDIO_cardType; +extern uint32_t SDIO_rca; +extern const cy_stc_sd_host_init_config_t SDIO_config; +extern cy_stc_sd_host_sd_card_config_t SDIO_card_cfg; +extern const cy_stc_smif_config_t QSPI_config; +extern const cy_stc_mcwdt_config_t MCWDT0_config; +extern const cy_stc_rtc_config_t RTC_config; +extern const cy_stc_tcpwm_pwm_config_t PWM_config; +extern const cy_stc_usbfs_dev_drv_config_t USBUART_config; + +void init_cycfg_peripherals(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PERIPHERALS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_pins.c new file mode 100644 index 0000000000..e8cc28fd9e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_pins.c @@ -0,0 +1,883 @@ +/******************************************************************************* +* File Name: cycfg_pins.c +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_pins.h" + +const cy_stc_gpio_pin_config_t WCO_IN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = WCO_IN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t WCO_OUT_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = WCO_OUT_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED_RED_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED_RED_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SW2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = SW2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED_BLUE_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED_BLUE_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_SS0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = QSPI_SS0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = QSPI_SPI_CLOCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED9_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED9_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = ioss_0_port_14_pin_0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = ioss_0_port_14_pin_1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED_GREEN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED_GREEN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED8_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED8_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_DAT0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_DAT0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_DAT1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_DAT1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_DAT2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_DAT2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_DAT3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_DAT3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_CMD_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_CMD_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_CLK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_CLK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t ENABLE_WIFI_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = ENABLE_WIFI_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_UART_RX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = BT_UART_RX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_UART_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = BT_UART_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_UART_RTS_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = BT_UART_RTS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_UART_CTS_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = BT_UART_CTS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_POWER_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF, + .hsiom = BT_POWER_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = BT_HOST_WAKE_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = BT_DEVICE_WAKE_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t UART_RX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = UART_RX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t UART_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = UART_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t EZI2C_SCL_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = EZI2C_SCL_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t EZI2C_SDA_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = EZI2C_SDA_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SWO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = SWO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SWDIO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = SWDIO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SWDCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLDOWN, + .hsiom = SWDCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CINA_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CINA_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CINB_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CINB_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CMOD_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CMOD_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_BTN0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_BTN0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_BTN1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_BTN1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD4_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD4_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; + + +void init_cycfg_pins(void) +{ + Cy_GPIO_Pin_Init(WCO_IN_PORT, WCO_IN_PIN, &WCO_IN_config); + + Cy_GPIO_Pin_Init(WCO_OUT_PORT, WCO_OUT_PIN, &WCO_OUT_config); + + Cy_GPIO_Pin_Init(LED_RED_PORT, LED_RED_PIN, &LED_RED_config); + + Cy_GPIO_Pin_Init(SW2_PORT, SW2_PIN, &SW2_config); + + Cy_GPIO_Pin_Init(LED_BLUE_PORT, LED_BLUE_PIN, &LED_BLUE_config); + + Cy_GPIO_Pin_Init(QSPI_SS0_PORT, QSPI_SS0_PIN, &QSPI_SS0_config); + + Cy_GPIO_Pin_Init(QSPI_DATA3_PORT, QSPI_DATA3_PIN, &QSPI_DATA3_config); + + Cy_GPIO_Pin_Init(QSPI_DATA2_PORT, QSPI_DATA2_PIN, &QSPI_DATA2_config); + + Cy_GPIO_Pin_Init(QSPI_DATA1_PORT, QSPI_DATA1_PIN, &QSPI_DATA1_config); + + Cy_GPIO_Pin_Init(QSPI_DATA0_PORT, QSPI_DATA0_PIN, &QSPI_DATA0_config); + + Cy_GPIO_Pin_Init(QSPI_SPI_CLOCK_PORT, QSPI_SPI_CLOCK_PIN, &QSPI_SPI_CLOCK_config); + + Cy_GPIO_Pin_Init(LED9_PORT, LED9_PIN, &LED9_config); + + Cy_GPIO_Pin_Init(ioss_0_port_14_pin_0_PORT, ioss_0_port_14_pin_0_PIN, &ioss_0_port_14_pin_0_config); + + Cy_GPIO_Pin_Init(ioss_0_port_14_pin_1_PORT, ioss_0_port_14_pin_1_PIN, &ioss_0_port_14_pin_1_config); + + + Cy_GPIO_Pin_Init(LED_GREEN_PORT, LED_GREEN_PIN, &LED_GREEN_config); + + Cy_GPIO_Pin_Init(LED8_PORT, LED8_PIN, &LED8_config); + + Cy_GPIO_Pin_Init(SDHC0_DAT0_PORT, SDHC0_DAT0_PIN, &SDHC0_DAT0_config); + + Cy_GPIO_Pin_Init(SDHC0_DAT1_PORT, SDHC0_DAT1_PIN, &SDHC0_DAT1_config); + + Cy_GPIO_Pin_Init(SDHC0_DAT2_PORT, SDHC0_DAT2_PIN, &SDHC0_DAT2_config); + + Cy_GPIO_Pin_Init(SDHC0_DAT3_PORT, SDHC0_DAT3_PIN, &SDHC0_DAT3_config); + + Cy_GPIO_Pin_Init(SDHC0_CMD_PORT, SDHC0_CMD_PIN, &SDHC0_CMD_config); + + Cy_GPIO_Pin_Init(SDHC0_CLK_PORT, SDHC0_CLK_PIN, &SDHC0_CLK_config); + + Cy_GPIO_Pin_Init(ENABLE_WIFI_PORT, ENABLE_WIFI_PIN, &ENABLE_WIFI_config); + + Cy_GPIO_Pin_Init(BT_UART_RX_PORT, BT_UART_RX_PIN, &BT_UART_RX_config); + + Cy_GPIO_Pin_Init(BT_UART_TX_PORT, BT_UART_TX_PIN, &BT_UART_TX_config); + + Cy_GPIO_Pin_Init(BT_UART_RTS_PORT, BT_UART_RTS_PIN, &BT_UART_RTS_config); + + Cy_GPIO_Pin_Init(BT_UART_CTS_PORT, BT_UART_CTS_PIN, &BT_UART_CTS_config); + + Cy_GPIO_Pin_Init(BT_POWER_PORT, BT_POWER_PIN, &BT_POWER_config); + + Cy_GPIO_Pin_Init(BT_HOST_WAKE_PORT, BT_HOST_WAKE_PIN, &BT_HOST_WAKE_config); + + Cy_GPIO_Pin_Init(BT_DEVICE_WAKE_PORT, BT_DEVICE_WAKE_PIN, &BT_DEVICE_WAKE_config); + + Cy_GPIO_Pin_Init(UART_RX_PORT, UART_RX_PIN, &UART_RX_config); + + Cy_GPIO_Pin_Init(UART_TX_PORT, UART_TX_PIN, &UART_TX_config); + + Cy_GPIO_Pin_Init(EZI2C_SCL_PORT, EZI2C_SCL_PIN, &EZI2C_SCL_config); + + Cy_GPIO_Pin_Init(EZI2C_SDA_PORT, EZI2C_SDA_PIN, &EZI2C_SDA_config); + + Cy_GPIO_Pin_Init(SWO_PORT, SWO_PIN, &SWO_config); + + Cy_GPIO_Pin_Init(SWDIO_PORT, SWDIO_PIN, &SWDIO_config); + + Cy_GPIO_Pin_Init(SWDCK_PORT, SWDCK_PIN, &SWDCK_config); + + + + + + + + + + +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_pins.h new file mode 100644 index 0000000000..c2f019c59e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_pins.h @@ -0,0 +1,571 @@ +/******************************************************************************* +* File Name: cycfg_pins.h +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PINS_H) +#define CYCFG_PINS_H + +#include "cycfg_notices.h" +#include "cy_gpio.h" +#include "cycfg_connectivity.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define WCO_IN_PORT GPIO_PRT0 +#define WCO_IN_PIN 0U +#define WCO_IN_NUM 0U +#define WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG +#define WCO_IN_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_0_HSIOM + #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM +#define WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn +#define WCO_OUT_PORT GPIO_PRT0 +#define WCO_OUT_PIN 1U +#define WCO_OUT_NUM 1U +#define WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG +#define WCO_OUT_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_1_HSIOM + #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM +#define WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn +#define LED_RED_PORT GPIO_PRT0 +#define LED_RED_PIN 3U +#define LED_RED_NUM 3U +#define LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED_RED_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_3_HSIOM + #define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM +#define LED_RED_IRQ ioss_interrupts_gpio_0_IRQn +#define SW2_PORT GPIO_PRT0 +#define SW2_PIN 4U +#define SW2_NUM 4U +#define SW2_DRIVEMODE CY_GPIO_DM_PULLUP +#define SW2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_4_HSIOM + #define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define SW2_HSIOM ioss_0_port_0_pin_4_HSIOM +#define SW2_IRQ ioss_interrupts_gpio_0_IRQn +#define LED_BLUE_PORT GPIO_PRT11 +#define LED_BLUE_PIN 1U +#define LED_BLUE_NUM 1U +#define LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED_BLUE_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_1_HSIOM + #define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM +#define LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_SS0_PORT GPIO_PRT11 +#define QSPI_SS0_PIN 2U +#define QSPI_SS0_NUM 2U +#define QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define QSPI_SS0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_2_HSIOM + #define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM +#define QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA3_PORT GPIO_PRT11 +#define QSPI_DATA3_PIN 3U +#define QSPI_DATA3_NUM 3U +#define QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_3_HSIOM + #define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM +#define QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA2_PORT GPIO_PRT11 +#define QSPI_DATA2_PIN 4U +#define QSPI_DATA2_NUM 4U +#define QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_4_HSIOM + #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM +#define QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA1_PORT GPIO_PRT11 +#define QSPI_DATA1_PIN 5U +#define QSPI_DATA1_NUM 5U +#define QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_5_HSIOM + #define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM +#define QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA0_PORT GPIO_PRT11 +#define QSPI_DATA0_PIN 6U +#define QSPI_DATA0_NUM 6U +#define QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_6_HSIOM + #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM +#define QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_SPI_CLOCK_PORT GPIO_PRT11 +#define QSPI_SPI_CLOCK_PIN 7U +#define QSPI_SPI_CLOCK_NUM 7U +#define QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define QSPI_SPI_CLOCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_7_HSIOM + #define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM +#define QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn +#define LED9_PORT GPIO_PRT13 +#define LED9_PIN 7U +#define LED9_NUM 7U +#define LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED9_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_13_pin_7_HSIOM + #define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define LED9_HSIOM ioss_0_port_13_pin_7_HSIOM +#define LED9_IRQ ioss_interrupts_gpio_13_IRQn +#define ioss_0_port_14_pin_0_PORT GPIO_PRT14 +#define ioss_0_port_14_pin_0_PIN 0U +#define ioss_0_port_14_pin_0_NUM 0U +#define ioss_0_port_14_pin_0_DRIVEMODE CY_GPIO_DM_ANALOG +#define ioss_0_port_14_pin_0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_14_pin_0_HSIOM + #define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define ioss_0_port_14_pin_0_IRQ ioss_interrupts_gpio_14_IRQn +#define ioss_0_port_14_pin_1_PORT GPIO_PRT14 +#define ioss_0_port_14_pin_1_PIN 1U +#define ioss_0_port_14_pin_1_NUM 1U +#define ioss_0_port_14_pin_1_DRIVEMODE CY_GPIO_DM_ANALOG +#define ioss_0_port_14_pin_1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_14_pin_1_HSIOM + #define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define ioss_0_port_14_pin_1_IRQ ioss_interrupts_gpio_14_IRQn +#define CSD_TX_PORT GPIO_PRT1 +#define CSD_TX_PIN 0U +#define CSD_TX_NUM 0U +#define CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_0_HSIOM + #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM +#define CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn +#define LED_GREEN_PORT GPIO_PRT1 +#define LED_GREEN_PIN 1U +#define LED_GREEN_NUM 1U +#define LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED_GREEN_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_1_HSIOM + #define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM +#define LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn +#define LED8_PORT GPIO_PRT1 +#define LED8_PIN 5U +#define LED8_NUM 5U +#define LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED8_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_5_HSIOM + #define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define LED8_HSIOM ioss_0_port_1_pin_5_HSIOM +#define LED8_IRQ ioss_interrupts_gpio_1_IRQn +#define SDHC0_DAT0_PORT GPIO_PRT2 +#define SDHC0_DAT0_PIN 0U +#define SDHC0_DAT0_NUM 0U +#define SDHC0_DAT0_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_DAT0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_0_HSIOM + #define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_DAT0_HSIOM ioss_0_port_2_pin_0_HSIOM +#define SDHC0_DAT0_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_DAT1_PORT GPIO_PRT2 +#define SDHC0_DAT1_PIN 1U +#define SDHC0_DAT1_NUM 1U +#define SDHC0_DAT1_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_DAT1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_1_HSIOM + #define ioss_0_port_2_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_DAT1_HSIOM ioss_0_port_2_pin_1_HSIOM +#define SDHC0_DAT1_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_DAT2_PORT GPIO_PRT2 +#define SDHC0_DAT2_PIN 2U +#define SDHC0_DAT2_NUM 2U +#define SDHC0_DAT2_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_DAT2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_2_HSIOM + #define ioss_0_port_2_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_DAT2_HSIOM ioss_0_port_2_pin_2_HSIOM +#define SDHC0_DAT2_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_DAT3_PORT GPIO_PRT2 +#define SDHC0_DAT3_PIN 3U +#define SDHC0_DAT3_NUM 3U +#define SDHC0_DAT3_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_DAT3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_3_HSIOM + #define ioss_0_port_2_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_DAT3_HSIOM ioss_0_port_2_pin_3_HSIOM +#define SDHC0_DAT3_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_CMD_PORT GPIO_PRT2 +#define SDHC0_CMD_PIN 4U +#define SDHC0_CMD_NUM 4U +#define SDHC0_CMD_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_CMD_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_4_HSIOM + #define ioss_0_port_2_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM +#define SDHC0_CMD_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_CLK_PORT GPIO_PRT2 +#define SDHC0_CLK_PIN 5U +#define SDHC0_CLK_NUM 5U +#define SDHC0_CLK_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_CLK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_5_HSIOM + #define ioss_0_port_2_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM +#define SDHC0_CLK_IRQ ioss_interrupts_gpio_2_IRQn +#define ENABLE_WIFI_PORT GPIO_PRT2 +#define ENABLE_WIFI_PIN 6U +#define ENABLE_WIFI_NUM 6U +#define ENABLE_WIFI_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define ENABLE_WIFI_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_2_pin_6_HSIOM + #define ioss_0_port_2_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define ENABLE_WIFI_HSIOM ioss_0_port_2_pin_6_HSIOM +#define ENABLE_WIFI_IRQ ioss_interrupts_gpio_2_IRQn +#define BT_UART_RX_PORT GPIO_PRT3 +#define BT_UART_RX_PIN 0U +#define BT_UART_RX_NUM 0U +#define BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ +#define BT_UART_RX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_0_HSIOM + #define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM +#define BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_UART_TX_PORT GPIO_PRT3 +#define BT_UART_TX_PIN 1U +#define BT_UART_TX_NUM 1U +#define BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define BT_UART_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_1_HSIOM + #define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM +#define BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_UART_RTS_PORT GPIO_PRT3 +#define BT_UART_RTS_PIN 2U +#define BT_UART_RTS_NUM 2U +#define BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define BT_UART_RTS_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_2_HSIOM + #define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM +#define BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_UART_CTS_PORT GPIO_PRT3 +#define BT_UART_CTS_PIN 3U +#define BT_UART_CTS_NUM 3U +#define BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ +#define BT_UART_CTS_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_3_HSIOM + #define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM +#define BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_POWER_PORT GPIO_PRT3 +#define BT_POWER_PIN 4U +#define BT_POWER_NUM 4U +#define BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF +#define BT_POWER_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_4_HSIOM + #define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM +#define BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_HOST_WAKE_PORT GPIO_PRT3 +#define BT_HOST_WAKE_PIN 5U +#define BT_HOST_WAKE_NUM 5U +#define BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG +#define BT_HOST_WAKE_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_3_pin_5_HSIOM + #define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM +#define BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_DEVICE_WAKE_PORT GPIO_PRT4 +#define BT_DEVICE_WAKE_PIN 0U +#define BT_DEVICE_WAKE_NUM 0U +#define BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define BT_DEVICE_WAKE_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_4_pin_0_HSIOM + #define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM +#define BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn +#define UART_RX_PORT GPIO_PRT5 +#define UART_RX_PIN 0U +#define UART_RX_NUM 0U +#define UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ +#define UART_RX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_5_pin_0_HSIOM + #define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM +#define UART_RX_IRQ ioss_interrupts_gpio_5_IRQn +#define UART_TX_PORT GPIO_PRT5 +#define UART_TX_PIN 1U +#define UART_TX_NUM 1U +#define UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define UART_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_5_pin_1_HSIOM + #define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM +#define UART_TX_IRQ ioss_interrupts_gpio_5_IRQn +#define EZI2C_SCL_PORT GPIO_PRT6 +#define EZI2C_SCL_PIN 0U +#define EZI2C_SCL_NUM 0U +#define EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define EZI2C_SCL_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_0_HSIOM + #define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM +#define EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn +#define EZI2C_SDA_PORT GPIO_PRT6 +#define EZI2C_SDA_PIN 1U +#define EZI2C_SDA_NUM 1U +#define EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define EZI2C_SDA_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_1_HSIOM + #define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM +#define EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn +#define SWO_PORT GPIO_PRT6 +#define SWO_PIN 4U +#define SWO_NUM 4U +#define SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define SWO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_4_HSIOM + #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define SWO_HSIOM ioss_0_port_6_pin_4_HSIOM +#define SWO_IRQ ioss_interrupts_gpio_6_IRQn +#define SWDIO_PORT GPIO_PRT6 +#define SWDIO_PIN 6U +#define SWDIO_NUM 6U +#define SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP +#define SWDIO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_6_HSIOM + #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM +#define SWDIO_IRQ ioss_interrupts_gpio_6_IRQn +#define SWDCK_PORT GPIO_PRT6 +#define SWDCK_PIN 7U +#define SWDCK_NUM 7U +#define SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN +#define SWDCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_7_HSIOM + #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM +#define SWDCK_IRQ ioss_interrupts_gpio_6_IRQn +#define CINA_PORT GPIO_PRT7 +#define CINA_PIN 1U +#define CINA_NUM 1U +#define CINA_DRIVEMODE CY_GPIO_DM_ANALOG +#define CINA_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_1_HSIOM + #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CINA_HSIOM ioss_0_port_7_pin_1_HSIOM +#define CINA_IRQ ioss_interrupts_gpio_7_IRQn +#define CINB_PORT GPIO_PRT7 +#define CINB_PIN 2U +#define CINB_NUM 2U +#define CINB_DRIVEMODE CY_GPIO_DM_ANALOG +#define CINB_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_2_HSIOM + #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CINB_HSIOM ioss_0_port_7_pin_2_HSIOM +#define CINB_IRQ ioss_interrupts_gpio_7_IRQn +#define CMOD_PORT GPIO_PRT7 +#define CMOD_PIN 7U +#define CMOD_NUM 7U +#define CMOD_DRIVEMODE CY_GPIO_DM_ANALOG +#define CMOD_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_7_HSIOM + #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM +#define CMOD_IRQ ioss_interrupts_gpio_7_IRQn +#define CSD_BTN0_PORT GPIO_PRT8 +#define CSD_BTN0_PIN 1U +#define CSD_BTN0_NUM 1U +#define CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_BTN0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_1_HSIOM + #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM +#define CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_BTN1_PORT GPIO_PRT8 +#define CSD_BTN1_PIN 2U +#define CSD_BTN1_NUM 2U +#define CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_BTN1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_2_HSIOM + #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM +#define CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD0_PORT GPIO_PRT8 +#define CSD_SLD0_PIN 3U +#define CSD_SLD0_NUM 3U +#define CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_3_HSIOM + #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM +#define CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD1_PORT GPIO_PRT8 +#define CSD_SLD1_PIN 4U +#define CSD_SLD1_NUM 4U +#define CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_4_HSIOM + #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM +#define CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD2_PORT GPIO_PRT8 +#define CSD_SLD2_PIN 5U +#define CSD_SLD2_NUM 5U +#define CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_5_HSIOM + #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM +#define CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD3_PORT GPIO_PRT8 +#define CSD_SLD3_PIN 6U +#define CSD_SLD3_NUM 6U +#define CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_6_HSIOM + #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM +#define CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD4_PORT GPIO_PRT8 +#define CSD_SLD4_PIN 7U +#define CSD_SLD4_NUM 7U +#define CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD4_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_7_HSIOM + #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM +#define CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn + +extern const cy_stc_gpio_pin_config_t WCO_IN_config; +extern const cy_stc_gpio_pin_config_t WCO_OUT_config; +extern const cy_stc_gpio_pin_config_t LED_RED_config; +extern const cy_stc_gpio_pin_config_t SW2_config; +extern const cy_stc_gpio_pin_config_t LED_BLUE_config; +extern const cy_stc_gpio_pin_config_t QSPI_SS0_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA3_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA2_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA1_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA0_config; +extern const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config; +extern const cy_stc_gpio_pin_config_t LED9_config; +extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config; +extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config; +extern const cy_stc_gpio_pin_config_t CSD_TX_config; +extern const cy_stc_gpio_pin_config_t LED_GREEN_config; +extern const cy_stc_gpio_pin_config_t LED8_config; +extern const cy_stc_gpio_pin_config_t SDHC0_DAT0_config; +extern const cy_stc_gpio_pin_config_t SDHC0_DAT1_config; +extern const cy_stc_gpio_pin_config_t SDHC0_DAT2_config; +extern const cy_stc_gpio_pin_config_t SDHC0_DAT3_config; +extern const cy_stc_gpio_pin_config_t SDHC0_CMD_config; +extern const cy_stc_gpio_pin_config_t SDHC0_CLK_config; +extern const cy_stc_gpio_pin_config_t ENABLE_WIFI_config; +extern const cy_stc_gpio_pin_config_t BT_UART_RX_config; +extern const cy_stc_gpio_pin_config_t BT_UART_TX_config; +extern const cy_stc_gpio_pin_config_t BT_UART_RTS_config; +extern const cy_stc_gpio_pin_config_t BT_UART_CTS_config; +extern const cy_stc_gpio_pin_config_t BT_POWER_config; +extern const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config; +extern const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config; +extern const cy_stc_gpio_pin_config_t UART_RX_config; +extern const cy_stc_gpio_pin_config_t UART_TX_config; +extern const cy_stc_gpio_pin_config_t EZI2C_SCL_config; +extern const cy_stc_gpio_pin_config_t EZI2C_SDA_config; +extern const cy_stc_gpio_pin_config_t SWO_config; +extern const cy_stc_gpio_pin_config_t SWDIO_config; +extern const cy_stc_gpio_pin_config_t SWDCK_config; +extern const cy_stc_gpio_pin_config_t CINA_config; +extern const cy_stc_gpio_pin_config_t CINB_config; +extern const cy_stc_gpio_pin_config_t CMOD_config; +extern const cy_stc_gpio_pin_config_t CSD_BTN0_config; +extern const cy_stc_gpio_pin_config_t CSD_BTN1_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD0_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD1_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD2_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD3_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD4_config; + +void init_cycfg_pins(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PINS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_platform.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_platform.c new file mode 100644 index 0000000000..02ba12d7e9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_platform.c @@ -0,0 +1,567 @@ +/******************************************************************************* +* File Name: cycfg_platform.c +* +* Description: +* Platform configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_platform.h" + +#define CY_CFG_SYSCLK_ECO_ERROR 1 +#define CY_CFG_SYSCLK_ALTHF_ERROR 2 +#define CY_CFG_SYSCLK_PLL_ERROR 3 +#define CY_CFG_SYSCLK_FLL_ERROR 4 +#define CY_CFG_SYSCLK_WCO_ERROR 5 +#define CY_CFG_SYSCLK_PLL1_AVAILABLE 1 +#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 +#define CY_CFG_SYSCLK_FLL_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 48UL +#define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1 +#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL +#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL +#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1 +#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_ILO_ENABLED 1 +#define CY_CFG_SYSCLK_IMO_ENABLED 1 +#define CY_CFG_SYSCLK_CLKLF_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 +#define CY_CFG_SYSCLK_PLL0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 +#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1 +#define CY_CFG_SYSCLK_WCO_ENABLED 1 +#define CY_CFG_PWR_ENABLED 1 +#define CY_CFG_PWR_USING_LDO 1 +#define CY_CFG_PWR_USING_PMIC 0 +#define CY_CFG_PWR_VBAC_SUPPLY CY_CFG_PWR_VBAC_SUPPLY_VDD +#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_1_1V +#define CY_CFG_PWR_USING_ULP 0 + +static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = +{ + .fllMult = 500U, + .refDiv = 20U, + .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, + .enableOutputDiv = true, + .lockTolerance = 4U, + .igain = 9U, + .pgain = 5U, + .settlingCount = 8U, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, + .cco_Freq = 355U, +}; +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = +{ + .feedbackDiv = 30, + .referenceDiv = 1, + .outputDiv = 5, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, +}; + +__WEAK void cycfg_ClockStartupError(uint32_t error) +{ + (void)error; /* Suppress the compiler warning */ + while(1); +} +__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit() +{ + Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF); +} +__STATIC_INLINE void Cy_SysClk_ClkBakInit() +{ + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); +} +__STATIC_INLINE void Cy_SysClk_ClkFastInit() +{ + Cy_SysClk_ClkFastSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_FllInit() +{ + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } +} +__STATIC_INLINE void Cy_SysClk_ClkHf0Init() +{ + Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); +} +__STATIC_INLINE void Cy_SysClk_ClkHf1Init() +{ + Cy_SysClk_ClkHfSetSource(1U, CY_CFG_SYSCLK_CLKHF1_CLKPATH); + Cy_SysClk_ClkHfSetDivider(1U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfEnable(1U); +} +__STATIC_INLINE void Cy_SysClk_ClkHf2Init() +{ + Cy_SysClk_ClkHfSetSource(2U, CY_CFG_SYSCLK_CLKHF2_CLKPATH); + Cy_SysClk_ClkHfSetDivider(2U, CY_SYSCLK_CLKHF_DIVIDE_BY_2); + Cy_SysClk_ClkHfEnable(2U); +} +__STATIC_INLINE void Cy_SysClk_ClkHf3Init() +{ + Cy_SysClk_ClkHfSetSource(3U, CY_CFG_SYSCLK_CLKHF3_CLKPATH); + Cy_SysClk_ClkHfSetDivider(3U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfEnable(3U); +} +__STATIC_INLINE void Cy_SysClk_ClkHf4Init() +{ + Cy_SysClk_ClkHfSetSource(4U, CY_CFG_SYSCLK_CLKHF4_CLKPATH); + Cy_SysClk_ClkHfSetDivider(4U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfEnable(4U); +} +__STATIC_INLINE void Cy_SysClk_IloInit() +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_IloEnable(); + Cy_SysClk_IloHibernateOn(true); +} +__STATIC_INLINE void Cy_SysClk_ClkLfInit() +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); +} +__STATIC_INLINE void Cy_SysClk_ClkPath0Init() +{ + Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath1Init() +{ + Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath2Init() +{ + Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath3Init() +{ + Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath4Init() +{ + Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPeriInit() +{ + Cy_SysClk_ClkPeriSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_Pll0Init() +{ + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } +} +__STATIC_INLINE void Cy_SysClk_ClkSlowInit() +{ + Cy_SysClk_ClkSlowSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_ClkTimerInit() +{ + Cy_SysClk_ClkTimerDisable(); + Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO); + Cy_SysClk_ClkTimerSetDivider(0U); + Cy_SysClk_ClkTimerEnable(); +} +__STATIC_INLINE void Cy_SysClk_WcoInit() +{ + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); + } +} + + +void init_cycfg_platform(void) +{ + /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ + Cy_SysLib_SetWaitStates(false, 150UL); + #if (CY_CFG_PWR_VBAC_SUPPLY == CY_CFG_PWR_VBAC_SUPPLY_VDD) + if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) + { + Cy_SysLib_ResetBackupDomain(); + Cy_SysClk_IloDisable(); + Cy_SysClk_IloInit(); + } + #endif + #ifdef CY_CFG_PWR_ENABLED + /* Configure power mode */ + #if CY_CFG_PWR_USING_LDO + Cy_SysPm_LdoSetVoltage(CY_CFG_PWR_LDO_VOLTAGE); + #else + Cy_SysPm_BuckEnable(CY_CFG_PWR_BUCK_VOLTAGE); + #endif + /* Configure PMIC */ + Cy_SysPm_UnlockPmic(); + #if CY_CFG_PWR_USING_PMIC + Cy_SysPm_PmicEnableOutput(); + #else + Cy_SysPm_PmicDisableOutput(); + #endif + #endif + + /* Reset the core clock path to default and disable all the FLLs/PLLs */ + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkFastSetDivider(0U); + Cy_SysClk_ClkPeriSetDivider(1U); + Cy_SysClk_ClkSlowSetDivider(0U); + Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH1); + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); + + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && + (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) + { + Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); + } + + Cy_SysClk_FllDisable(); + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); + #ifdef CY_IP_MXBLESS + (void)Cy_BLE_EcoReset(); + #endif + + #ifdef CY_CFG_SYSCLK_PLL1_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2); + #endif + + #ifdef CY_CFG_SYSCLK_PLL2_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH3); + #endif + + #ifdef CY_CFG_SYSCLK_PLL3_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH4); + #endif + + #ifdef CY_CFG_SYSCLK_PLL4_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH5); + #endif + + #ifdef CY_CFG_SYSCLK_PLL5_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH6); + #endif + + #ifdef CY_CFG_SYSCLK_PLL6_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH7); + #endif + + #ifdef CY_CFG_SYSCLK_PLL7_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH8); + #endif + + #ifdef CY_CFG_SYSCLK_PLL8_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH9); + #endif + + #ifdef CY_CFG_SYSCLK_PLL9_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH10); + #endif + + #ifdef CY_CFG_SYSCLK_PLL10_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH11); + #endif + + #ifdef CY_CFG_SYSCLK_PLL11_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH12); + #endif + + #ifdef CY_CFG_SYSCLK_PLL12_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH13); + #endif + + #ifdef CY_CFG_SYSCLK_PLL13_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH14); + #endif + + #ifdef CY_CFG_SYSCLK_PLL14_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH15); + #endif + + /* Enable all source clocks */ + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + Cy_SysClk_PiloInit(); + #endif + + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + Cy_SysClk_WcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + Cy_SysClk_ClkLfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED + Cy_SysClk_AltHfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + Cy_SysClk_EcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + Cy_SysClk_ExtClkInit(); + #endif + + /* Configure CPU clock dividers */ + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED + Cy_SysClk_ClkFastInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + Cy_SysClk_ClkPeriInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + Cy_SysClk_ClkSlowInit(); + #endif + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ + Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); + #else + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure Path Clocks */ + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + Cy_SysClk_ClkPath0Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + Cy_SysClk_ClkPath2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + Cy_SysClk_ClkPath3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + Cy_SysClk_ClkPath4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + Cy_SysClk_ClkPath5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED + Cy_SysClk_ClkPath6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED + Cy_SysClk_ClkPath7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED + Cy_SysClk_ClkPath8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED + Cy_SysClk_ClkPath9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED + Cy_SysClk_ClkPath10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED + Cy_SysClk_ClkPath11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED + Cy_SysClk_ClkPath12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED + Cy_SysClk_ClkPath13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED + Cy_SysClk_ClkPath14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED + Cy_SysClk_ClkPath15Init(); + #endif + + /* Configure and enable FLL */ + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + Cy_SysClk_FllInit(); + #endif + + Cy_SysClk_ClkHf0Init(); + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + /* Apply the ClkPath1 user setting */ + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure and enable PLLs */ + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + Cy_SysClk_Pll0Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + Cy_SysClk_Pll1Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL2_ENABLED + Cy_SysClk_Pll2Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL3_ENABLED + Cy_SysClk_Pll3Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL4_ENABLED + Cy_SysClk_Pll4Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL5_ENABLED + Cy_SysClk_Pll5Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL6_ENABLED + Cy_SysClk_Pll6Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL7_ENABLED + Cy_SysClk_Pll7Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL8_ENABLED + Cy_SysClk_Pll8Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL9_ENABLED + Cy_SysClk_Pll9Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL10_ENABLED + Cy_SysClk_Pll10Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL11_ENABLED + Cy_SysClk_Pll11Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL12_ENABLED + Cy_SysClk_Pll12Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL13_ENABLED + Cy_SysClk_Pll13Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL14_ENABLED + Cy_SysClk_Pll14Init(); + #endif + + /* Configure HF clocks */ + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + Cy_SysClk_ClkHf1Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + Cy_SysClk_ClkHf2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + Cy_SysClk_ClkHf3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + Cy_SysClk_ClkHf4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + Cy_SysClk_ClkHf5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED + Cy_SysClk_ClkHf6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED + Cy_SysClk_ClkHf7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED + Cy_SysClk_ClkHf8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED + Cy_SysClk_ClkHf9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED + Cy_SysClk_ClkHf10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED + Cy_SysClk_ClkHf11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED + Cy_SysClk_ClkHf12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED + Cy_SysClk_ClkHf13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED + Cy_SysClk_ClkHf14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED + Cy_SysClk_ClkHf15Init(); + #endif + + /* Configure miscellaneous clocks */ + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED + Cy_SysClk_ClkTimerInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + Cy_SysClk_ClkAltSysTickInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + Cy_SysClk_ClkPumpInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + Cy_SysClk_ClkBakInit(); + #endif + + /* Configure default enabled clocks */ + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + Cy_SysClk_IloInit(); + #else + Cy_SysClk_IloDisable(); + #endif + + #ifndef CY_CFG_SYSCLK_IMO_ENABLED + #error the IMO must be enabled for proper chip operation + #endif + + /* Set accurate flash wait states */ + #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) + Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); + #endif + + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ + SystemCoreClockUpdate(); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_platform.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_platform.h new file mode 100644 index 0000000000..76dfbef7bc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_platform.h @@ -0,0 +1,53 @@ +/******************************************************************************* +* File Name: cycfg_platform.h +* +* Description: +* Platform configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PLATFORM_H) +#define CYCFG_PLATFORM_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_systick.h" +#include "cy_gpio.h" +#include "cy_syspm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 +#define CY_CFG_PWR_VDDA_MV 3300 +#define CY_CFG_PWR_VDDD_MV 3300 +#define CY_CFG_PWR_VBACKUP_MV 3300 +#define CY_CFG_PWR_VDD_NS_MV 3300 +#define CY_CFG_PWR_VDDIO0_MV 3300 +#define CY_CFG_PWR_VDDIO1_MV 3300 + +void init_cycfg_platform(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PLATFORM_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.c new file mode 100644 index 0000000000..cf7ac0229a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.c @@ -0,0 +1,34 @@ +/******************************************************************************* +* File Name: cycfg.c +* +* Description: +* Wrapper function to initialize all generated code. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg.h" + +void init_cycfg_all(void) +{ + init_cycfg_clocks(); + init_cycfg_peripherals(); + init_cycfg_pins(); + init_cycfg_platform(); + init_cycfg_connectivity(); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.h new file mode 100644 index 0000000000..68bb40bf09 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.h @@ -0,0 +1,47 @@ +/******************************************************************************* +* File Name: cycfg.h +* +* Description: +* Simple wrapper header containing all generated files. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_H) +#define CYCFG_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +#include "cycfg_clocks.h" +#include "cycfg_peripherals.h" +#include "cycfg_pins.h" +#include "cycfg_platform.h" +#include "cycfg_connectivity.h" + +void init_cycfg_all(void); + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.c new file mode 100644 index 0000000000..9a6a4e3cf9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.c @@ -0,0 +1,45 @@ +/******************************************************************************* +* File Name: cycfg_clocks.c +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_clocks.h" + + +void init_cycfg_clocks(void) +{ + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 35U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 0U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.h new file mode 100644 index 0000000000..ce944e4bd0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.h @@ -0,0 +1,51 @@ +/******************************************************************************* +* File Name: cycfg_clocks.h +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_CLOCKS_H) +#define CYCFG_CLOCKS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define peri_0_div_8_0_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_0_NUM 0U +#define peri_0_div_8_1_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_1_NUM 1U +#define peri_0_div_8_2_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_2_NUM 2U +#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_3_NUM 3U + +void init_cycfg_clocks(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_CLOCKS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_connectivity.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_connectivity.c new file mode 100644 index 0000000000..d4beee5fd1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_connectivity.c @@ -0,0 +1,39 @@ +/******************************************************************************* +* File Name: cycfg_connectivity.c +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_connectivity.h" + +#include "cy_device_headers.h" + +void init_cycfg_connectivity(void) +{ + HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; + HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_connectivity.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_connectivity.h new file mode 100644 index 0000000000..ad5cb15c79 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_connectivity.h @@ -0,0 +1,64 @@ +/******************************************************************************* +* File Name: cycfg_connectivity.h +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_CONNECTIVITY_H) +#define CYCFG_CONNECTIVITY_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +void init_cycfg_connectivity(void); + +#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 +#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 +#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 +#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 +#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 +#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK +#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX +#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL +#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA +#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO +#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS +#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK +#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_CONNECTIVITY_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_notices.h new file mode 100644 index 0000000000..90f1013f8a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_notices.h @@ -0,0 +1,30 @@ +/******************************************************************************* +* File Name: cycfg_notices.h +* +* Description: +* Contains warnings and errors that occurred while generating code for the +* design. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_NOTICES_H) +#define CYCFG_NOTICES_H + + +#endif /* CYCFG_NOTICES_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.c new file mode 100644 index 0000000000..211f24a113 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.c @@ -0,0 +1,108 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.c +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_peripherals.h" + +cy_stc_csd_context_t cy_csd_0_context = +{ + .lockKey = CY_CSD_NONE_KEY, +}; +const cy_stc_scb_ezi2c_config_t CSD_COMM_config = +{ + .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS, + .slaveAddress1 = 8U, + .slaveAddress2 = 0U, + .subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS, + .enableWakeFromSleep = false, +}; +const cy_stc_scb_uart_config_t KITPROG_UART_config = +{ + .uartMode = CY_SCB_UART_STANDARD, + .enableMutliProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + .oversample = 12, + .enableMsbFirst = false, + .dataWidth = 9UL, + .parity = CY_SCB_UART_PARITY_NONE, + .stopBits = CY_SCB_UART_STOP_BITS_1, + .enableInputFilter = false, + .breakWidth = 11UL, + .dropOnFrameError = false, + .dropOnParityError = false, + .receiverAddress = 0x0UL, + .receiverAddressMask = 0x0UL, + .acceptAddrInFifo = false, + .enableCts = false, + .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rtsRxFifoLevel = 0UL, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rxFifoTriggerLevel = 63UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, +}; +const cy_stc_smif_config_t QSPI_config = +{ + .mode = (uint32_t)CY_SMIF_NORMAL, + .deselectDelay = QSPI_DESELECT_DELAY, + .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK, + .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, +}; +const cy_stc_mcwdt_config_t MCWDT0_config = +{ + .c0Match = 32768U, + .c1Match = 32768U, + .c0Mode = CY_MCWDT_MODE_NONE, + .c1Mode = CY_MCWDT_MODE_NONE, + .c2ToggleBit = 16U, + .c2Mode = CY_MCWDT_MODE_NONE, + .c0ClearOnMatch = false, + .c1ClearOnMatch = false, + .c0c1Cascade = true, + .c1c2Cascade = false, +}; +const cy_stc_rtc_config_t RTC_config = +{ + .sec = 0U, + .min = 0U, + .hour = 12U, + .amPm = CY_RTC_AM, + .hrFormat = CY_RTC_24_HOURS, + .dayOfWeek = CY_RTC_SUNDAY, + .date = 1U, + .month = CY_RTC_JANUARY, + .year = 0U, +}; + + +void init_cycfg_peripherals(void) +{ + Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.h new file mode 100644 index 0000000000..230df68ef5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.h @@ -0,0 +1,128 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.h +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PERIPHERALS_H) +#define CYCFG_PERIPHERALS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_csd.h" +#include "cy_scb_ezi2c.h" +#include "cy_scb_uart.h" +#include "cy_smif.h" +#include "cy_mcwdt.h" +#include "cy_rtc.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CY_BLE_CORE_CORTEX_M4 4U +#define CY_BLE_CORE_CORTEX_M0P 0U +#define CY_BLE_CORE_DUAL 255U +#ifndef CY_BLE_CORE + #define CY_BLE_CORE 4U +#endif +#define CY_BLE_IRQ bless_interrupt_IRQn +#define CY_CAPSENSE_CORE 4u +#define CY_CAPSENSE_CPU_CLK 100000000u +#define CY_CAPSENSE_PERI_CLK 50000000u +#define CY_CAPSENSE_VDDA_MV 3300u +#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT +#define CY_CAPSENSE_PERI_DIV_INDEX 0u +#define Cmod_PORT GPIO_PRT7 +#define CintA_PORT GPIO_PRT7 +#define CintB_PORT GPIO_PRT7 +#define Button0_Rx0_PORT GPIO_PRT8 +#define Button0_Tx_PORT GPIO_PRT1 +#define Button1_Rx0_PORT GPIO_PRT8 +#define Button1_Tx_PORT GPIO_PRT1 +#define LinearSlider0_Sns0_PORT GPIO_PRT8 +#define LinearSlider0_Sns1_PORT GPIO_PRT8 +#define LinearSlider0_Sns2_PORT GPIO_PRT8 +#define LinearSlider0_Sns3_PORT GPIO_PRT8 +#define LinearSlider0_Sns4_PORT GPIO_PRT8 +#define Cmod_PIN 7u +#define CintA_PIN 1u +#define CintB_PIN 2u +#define Button0_Rx0_PIN 1u +#define Button0_Tx_PIN 0u +#define Button1_Rx0_PIN 2u +#define Button1_Tx_PIN 0u +#define LinearSlider0_Sns0_PIN 3u +#define LinearSlider0_Sns1_PIN 4u +#define LinearSlider0_Sns2_PIN 5u +#define LinearSlider0_Sns3_PIN 6u +#define LinearSlider0_Sns4_PIN 7u +#define Cmod_PORT_NUM 7u +#define CintA_PORT_NUM 7u +#define CintB_PORT_NUM 7u +#define CapSense_HW CSD0 +#define CapSense_IRQ csd_interrupt_IRQn +#define CSD_COMM_HW SCB3 +#define CSD_COMM_IRQ scb_3_interrupt_IRQn +#define KITPROG_UART_HW SCB5 +#define KITPROG_UART_IRQ scb_5_interrupt_IRQn +#define QSPI_HW SMIF0 +#define QSPI_IRQ smif_interrupt_IRQn +#define QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL) +#define QSPI_RX_DATA_FIFO_UNDERFLOW (0UL) +#define QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL) +#define QSPI_TX_DATA_FIFO_OVERFLOW (0UL) +#define QSPI_RX_FIFO_TRIGEER_LEVEL (0UL) +#define QSPI_TX_FIFO_TRIGEER_LEVEL (0UL) +#define QSPI_DATALINES0_1 (1UL) +#define QSPI_DATALINES2_3 (1UL) +#define QSPI_DATALINES4_5 (0UL) +#define QSPI_DATALINES6_7 (0UL) +#define QSPI_SS0 (1UL) +#define QSPI_SS1 (0UL) +#define QSPI_SS2 (0UL) +#define QSPI_SS3 (0UL) +#define QSPI_DESELECT_DELAY 7 +#define MCWDT0_HW MCWDT_STRUCT0 +#define RTC_10_MONTH_OFFSET (28U) +#define RTC_MONTH_OFFSET (24U) +#define RTC_10_DAY_OFFSET (20U) +#define RTC_DAY_OFFSET (16U) +#define RTC_1000_YEAR_OFFSET (12U) +#define RTC_100_YEAR_OFFSET (8U) +#define RTC_10_YEAR_OFFSET (4U) +#define RTC_YEAR_OFFSET (0U) + +extern cy_stc_csd_context_t cy_csd_0_context; +extern const cy_stc_scb_ezi2c_config_t CSD_COMM_config; +extern const cy_stc_scb_uart_config_t KITPROG_UART_config; +extern const cy_stc_smif_config_t QSPI_config; +extern const cy_stc_mcwdt_config_t MCWDT0_config; +extern const cy_stc_rtc_config_t RTC_config; + +void init_cycfg_peripherals(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PERIPHERALS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.c new file mode 100644 index 0000000000..9f927f5c86 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.c @@ -0,0 +1,595 @@ +/******************************************************************************* +* File Name: cycfg_pins.c +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_pins.h" + +const cy_stc_gpio_pin_config_t WCO_IN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = WCO_IN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t WCO_OUT_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = WCO_OUT_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED_RED_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED_RED_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SW2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = SW2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED_BLUE_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED_BLUE_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_SS0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = QSPI_SS0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = QSPI_SPI_CLOCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED9_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED9_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED_GREEN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED_GREEN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t ioss_0_port_1_pin_4_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = ioss_0_port_1_pin_4_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED8_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED8_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t UART_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = UART_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t EZI2C_SCL_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = EZI2C_SCL_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t EZI2C_SDA_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = EZI2C_SDA_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SWO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = SWO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SWDIO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = SWDIO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SWDCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLDOWN, + .hsiom = SWDCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CINA_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CINA_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CINB_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CINB_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CMOD_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CMOD_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_BTN0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_BTN0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_BTN1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_BTN1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD4_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD4_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; + + +void init_cycfg_pins(void) +{ + Cy_GPIO_Pin_Init(WCO_IN_PORT, WCO_IN_PIN, &WCO_IN_config); + + Cy_GPIO_Pin_Init(WCO_OUT_PORT, WCO_OUT_PIN, &WCO_OUT_config); + + Cy_GPIO_Pin_Init(LED_RED_PORT, LED_RED_PIN, &LED_RED_config); + + Cy_GPIO_Pin_Init(SW2_PORT, SW2_PIN, &SW2_config); + + Cy_GPIO_Pin_Init(LED_BLUE_PORT, LED_BLUE_PIN, &LED_BLUE_config); + + Cy_GPIO_Pin_Init(QSPI_SS0_PORT, QSPI_SS0_PIN, &QSPI_SS0_config); + + Cy_GPIO_Pin_Init(QSPI_DATA3_PORT, QSPI_DATA3_PIN, &QSPI_DATA3_config); + + Cy_GPIO_Pin_Init(QSPI_DATA2_PORT, QSPI_DATA2_PIN, &QSPI_DATA2_config); + + Cy_GPIO_Pin_Init(QSPI_DATA1_PORT, QSPI_DATA1_PIN, &QSPI_DATA1_config); + + Cy_GPIO_Pin_Init(QSPI_DATA0_PORT, QSPI_DATA0_PIN, &QSPI_DATA0_config); + + Cy_GPIO_Pin_Init(QSPI_SPI_CLOCK_PORT, QSPI_SPI_CLOCK_PIN, &QSPI_SPI_CLOCK_config); + + Cy_GPIO_Pin_Init(LED9_PORT, LED9_PIN, &LED9_config); + + + Cy_GPIO_Pin_Init(LED_GREEN_PORT, LED_GREEN_PIN, &LED_GREEN_config); + + Cy_GPIO_Pin_Init(ioss_0_port_1_pin_4_PORT, ioss_0_port_1_pin_4_PIN, &ioss_0_port_1_pin_4_config); + + Cy_GPIO_Pin_Init(LED8_PORT, LED8_PIN, &LED8_config); + + Cy_GPIO_Pin_Init(UART_TX_PORT, UART_TX_PIN, &UART_TX_config); + + Cy_GPIO_Pin_Init(EZI2C_SCL_PORT, EZI2C_SCL_PIN, &EZI2C_SCL_config); + + Cy_GPIO_Pin_Init(EZI2C_SDA_PORT, EZI2C_SDA_PIN, &EZI2C_SDA_config); + + Cy_GPIO_Pin_Init(SWO_PORT, SWO_PIN, &SWO_config); + + Cy_GPIO_Pin_Init(SWDIO_PORT, SWDIO_PIN, &SWDIO_config); + + Cy_GPIO_Pin_Init(SWDCK_PORT, SWDCK_PIN, &SWDCK_config); + + + + + + + + + + +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.h new file mode 100644 index 0000000000..39f5ff9f5e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.h @@ -0,0 +1,396 @@ +/******************************************************************************* +* File Name: cycfg_pins.h +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PINS_H) +#define CYCFG_PINS_H + +#include "cycfg_notices.h" +#include "cy_gpio.h" +#include "cycfg_connectivity.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define WCO_IN_PORT GPIO_PRT0 +#define WCO_IN_PIN 0U +#define WCO_IN_NUM 0U +#define WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG +#define WCO_IN_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_0_HSIOM + #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM +#define WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn +#define WCO_OUT_PORT GPIO_PRT0 +#define WCO_OUT_PIN 1U +#define WCO_OUT_NUM 1U +#define WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG +#define WCO_OUT_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_1_HSIOM + #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM +#define WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn +#define LED_RED_PORT GPIO_PRT0 +#define LED_RED_PIN 3U +#define LED_RED_NUM 3U +#define LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED_RED_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_3_HSIOM + #define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM +#define LED_RED_IRQ ioss_interrupts_gpio_0_IRQn +#define SW2_PORT GPIO_PRT0 +#define SW2_PIN 4U +#define SW2_NUM 4U +#define SW2_DRIVEMODE CY_GPIO_DM_PULLUP +#define SW2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_4_HSIOM + #define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define SW2_HSIOM ioss_0_port_0_pin_4_HSIOM +#define SW2_IRQ ioss_interrupts_gpio_0_IRQn +#define LED_BLUE_PORT GPIO_PRT11 +#define LED_BLUE_PIN 1U +#define LED_BLUE_NUM 1U +#define LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED_BLUE_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_1_HSIOM + #define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM +#define LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_SS0_PORT GPIO_PRT11 +#define QSPI_SS0_PIN 2U +#define QSPI_SS0_NUM 2U +#define QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define QSPI_SS0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_2_HSIOM + #define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM +#define QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA3_PORT GPIO_PRT11 +#define QSPI_DATA3_PIN 3U +#define QSPI_DATA3_NUM 3U +#define QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_3_HSIOM + #define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM +#define QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA2_PORT GPIO_PRT11 +#define QSPI_DATA2_PIN 4U +#define QSPI_DATA2_NUM 4U +#define QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_4_HSIOM + #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM +#define QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA1_PORT GPIO_PRT11 +#define QSPI_DATA1_PIN 5U +#define QSPI_DATA1_NUM 5U +#define QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_5_HSIOM + #define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM +#define QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA0_PORT GPIO_PRT11 +#define QSPI_DATA0_PIN 6U +#define QSPI_DATA0_NUM 6U +#define QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_6_HSIOM + #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM +#define QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_SPI_CLOCK_PORT GPIO_PRT11 +#define QSPI_SPI_CLOCK_PIN 7U +#define QSPI_SPI_CLOCK_NUM 7U +#define QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define QSPI_SPI_CLOCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_7_HSIOM + #define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM +#define QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn +#define LED9_PORT GPIO_PRT13 +#define LED9_PIN 7U +#define LED9_NUM 7U +#define LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED9_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_13_pin_7_HSIOM + #define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define LED9_HSIOM ioss_0_port_13_pin_7_HSIOM +#define LED9_IRQ ioss_interrupts_gpio_13_IRQn +#define CSD_TX_PORT GPIO_PRT1 +#define CSD_TX_PIN 0U +#define CSD_TX_NUM 0U +#define CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_0_HSIOM + #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM +#define CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn +#define LED_GREEN_PORT GPIO_PRT1 +#define LED_GREEN_PIN 1U +#define LED_GREEN_NUM 1U +#define LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED_GREEN_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_1_HSIOM + #define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM +#define LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn +#define ioss_0_port_1_pin_4_PORT GPIO_PRT1 +#define ioss_0_port_1_pin_4_PIN 4U +#define ioss_0_port_1_pin_4_NUM 4U +#define ioss_0_port_1_pin_4_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define ioss_0_port_1_pin_4_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_4_HSIOM + #define ioss_0_port_1_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define ioss_0_port_1_pin_4_IRQ ioss_interrupts_gpio_1_IRQn +#define LED8_PORT GPIO_PRT1 +#define LED8_PIN 5U +#define LED8_NUM 5U +#define LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED8_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_5_HSIOM + #define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define LED8_HSIOM ioss_0_port_1_pin_5_HSIOM +#define LED8_IRQ ioss_interrupts_gpio_1_IRQn +#define UART_TX_PORT GPIO_PRT5 +#define UART_TX_PIN 1U +#define UART_TX_NUM 1U +#define UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define UART_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_5_pin_1_HSIOM + #define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM +#define UART_TX_IRQ ioss_interrupts_gpio_5_IRQn +#define EZI2C_SCL_PORT GPIO_PRT6 +#define EZI2C_SCL_PIN 0U +#define EZI2C_SCL_NUM 0U +#define EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define EZI2C_SCL_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_0_HSIOM + #define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM +#define EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn +#define EZI2C_SDA_PORT GPIO_PRT6 +#define EZI2C_SDA_PIN 1U +#define EZI2C_SDA_NUM 1U +#define EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define EZI2C_SDA_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_1_HSIOM + #define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM +#define EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn +#define SWO_PORT GPIO_PRT6 +#define SWO_PIN 4U +#define SWO_NUM 4U +#define SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define SWO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_4_HSIOM + #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define SWO_HSIOM ioss_0_port_6_pin_4_HSIOM +#define SWO_IRQ ioss_interrupts_gpio_6_IRQn +#define SWDIO_PORT GPIO_PRT6 +#define SWDIO_PIN 6U +#define SWDIO_NUM 6U +#define SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP +#define SWDIO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_6_HSIOM + #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM +#define SWDIO_IRQ ioss_interrupts_gpio_6_IRQn +#define SWDCK_PORT GPIO_PRT6 +#define SWDCK_PIN 7U +#define SWDCK_NUM 7U +#define SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN +#define SWDCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_7_HSIOM + #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM +#define SWDCK_IRQ ioss_interrupts_gpio_6_IRQn +#define CINA_PORT GPIO_PRT7 +#define CINA_PIN 1U +#define CINA_NUM 1U +#define CINA_DRIVEMODE CY_GPIO_DM_ANALOG +#define CINA_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_1_HSIOM + #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CINA_HSIOM ioss_0_port_7_pin_1_HSIOM +#define CINA_IRQ ioss_interrupts_gpio_7_IRQn +#define CINB_PORT GPIO_PRT7 +#define CINB_PIN 2U +#define CINB_NUM 2U +#define CINB_DRIVEMODE CY_GPIO_DM_ANALOG +#define CINB_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_2_HSIOM + #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CINB_HSIOM ioss_0_port_7_pin_2_HSIOM +#define CINB_IRQ ioss_interrupts_gpio_7_IRQn +#define CMOD_PORT GPIO_PRT7 +#define CMOD_PIN 7U +#define CMOD_NUM 7U +#define CMOD_DRIVEMODE CY_GPIO_DM_ANALOG +#define CMOD_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_7_HSIOM + #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM +#define CMOD_IRQ ioss_interrupts_gpio_7_IRQn +#define CSD_BTN0_PORT GPIO_PRT8 +#define CSD_BTN0_PIN 1U +#define CSD_BTN0_NUM 1U +#define CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_BTN0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_1_HSIOM + #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM +#define CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_BTN1_PORT GPIO_PRT8 +#define CSD_BTN1_PIN 2U +#define CSD_BTN1_NUM 2U +#define CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_BTN1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_2_HSIOM + #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM +#define CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD0_PORT GPIO_PRT8 +#define CSD_SLD0_PIN 3U +#define CSD_SLD0_NUM 3U +#define CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_3_HSIOM + #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM +#define CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD1_PORT GPIO_PRT8 +#define CSD_SLD1_PIN 4U +#define CSD_SLD1_NUM 4U +#define CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_4_HSIOM + #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM +#define CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD2_PORT GPIO_PRT8 +#define CSD_SLD2_PIN 5U +#define CSD_SLD2_NUM 5U +#define CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_5_HSIOM + #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM +#define CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD3_PORT GPIO_PRT8 +#define CSD_SLD3_PIN 6U +#define CSD_SLD3_NUM 6U +#define CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_6_HSIOM + #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM +#define CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD4_PORT GPIO_PRT8 +#define CSD_SLD4_PIN 7U +#define CSD_SLD4_NUM 7U +#define CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD4_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_7_HSIOM + #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM +#define CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn + +extern const cy_stc_gpio_pin_config_t WCO_IN_config; +extern const cy_stc_gpio_pin_config_t WCO_OUT_config; +extern const cy_stc_gpio_pin_config_t LED_RED_config; +extern const cy_stc_gpio_pin_config_t SW2_config; +extern const cy_stc_gpio_pin_config_t LED_BLUE_config; +extern const cy_stc_gpio_pin_config_t QSPI_SS0_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA3_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA2_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA1_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA0_config; +extern const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config; +extern const cy_stc_gpio_pin_config_t LED9_config; +extern const cy_stc_gpio_pin_config_t CSD_TX_config; +extern const cy_stc_gpio_pin_config_t LED_GREEN_config; +extern const cy_stc_gpio_pin_config_t ioss_0_port_1_pin_4_config; +extern const cy_stc_gpio_pin_config_t LED8_config; +extern const cy_stc_gpio_pin_config_t UART_TX_config; +extern const cy_stc_gpio_pin_config_t EZI2C_SCL_config; +extern const cy_stc_gpio_pin_config_t EZI2C_SDA_config; +extern const cy_stc_gpio_pin_config_t SWO_config; +extern const cy_stc_gpio_pin_config_t SWDIO_config; +extern const cy_stc_gpio_pin_config_t SWDCK_config; +extern const cy_stc_gpio_pin_config_t CINA_config; +extern const cy_stc_gpio_pin_config_t CINB_config; +extern const cy_stc_gpio_pin_config_t CMOD_config; +extern const cy_stc_gpio_pin_config_t CSD_BTN0_config; +extern const cy_stc_gpio_pin_config_t CSD_BTN1_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD0_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD1_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD2_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD3_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD4_config; + +void init_cycfg_pins(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PINS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.c new file mode 100644 index 0000000000..9e81fbf418 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.c @@ -0,0 +1,506 @@ +/******************************************************************************* +* File Name: cycfg_platform.c +* +* Description: +* Platform configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_platform.h" + +#define CY_CFG_SYSCLK_ECO_ERROR 1 +#define CY_CFG_SYSCLK_ALTHF_ERROR 2 +#define CY_CFG_SYSCLK_PLL_ERROR 3 +#define CY_CFG_SYSCLK_FLL_ERROR 4 +#define CY_CFG_SYSCLK_WCO_ERROR 5 +#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 +#define CY_CFG_SYSCLK_FLL_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL +#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_ILO_ENABLED 1 +#define CY_CFG_SYSCLK_IMO_ENABLED 1 +#define CY_CFG_SYSCLK_CLKLF_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 +#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 +#define CY_CFG_SYSCLK_WCO_ENABLED 1 +#define CY_CFG_PWR_ENABLED 1 +#define CY_CFG_PWR_USING_LDO 1 +#define CY_CFG_PWR_USING_PMIC 0 +#define CY_CFG_PWR_VBAC_SUPPLY CY_CFG_PWR_VBAC_SUPPLY_VDD +#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_1_1V +#define CY_CFG_PWR_USING_ULP 0 + +static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = +{ + .fllMult = 500U, + .refDiv = 20U, + .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, + .enableOutputDiv = true, + .lockTolerance = 10U, + .igain = 9U, + .pgain = 5U, + .settlingCount = 8U, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, + .cco_Freq = 355U, +}; + +__WEAK void cycfg_ClockStartupError(uint32_t error) +{ + (void)error; /* Suppress the compiler warning */ + while(1); +} +__STATIC_INLINE void Cy_SysClk_ClkBakInit() +{ + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); +} +__STATIC_INLINE void Cy_SysClk_ClkFastInit() +{ + Cy_SysClk_ClkFastSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_FllInit() +{ + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } +} +__STATIC_INLINE void Cy_SysClk_ClkHf0Init() +{ + Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); +} +__STATIC_INLINE void Cy_SysClk_ClkHf2Init() +{ + Cy_SysClk_ClkHfSetSource(2U, CY_CFG_SYSCLK_CLKHF2_CLKPATH); + Cy_SysClk_ClkHfSetDivider(2U, CY_SYSCLK_CLKHF_DIVIDE_BY_2); + Cy_SysClk_ClkHfEnable(2U); +} +__STATIC_INLINE void Cy_SysClk_IloInit() +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_IloEnable(); + Cy_SysClk_IloHibernateOn(true); +} +__STATIC_INLINE void Cy_SysClk_ClkLfInit() +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO); +} +__STATIC_INLINE void Cy_SysClk_ClkPath0Init() +{ + Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath1Init() +{ + Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath2Init() +{ + Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath3Init() +{ + Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath4Init() +{ + Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPeriInit() +{ + Cy_SysClk_ClkPeriSetDivider(1U); +} +__STATIC_INLINE void Cy_SysClk_ClkSlowInit() +{ + Cy_SysClk_ClkSlowSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_WcoInit() +{ + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); + } +} + + +void init_cycfg_platform(void) +{ + /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ + Cy_SysLib_SetWaitStates(false, 150UL); + #if (CY_CFG_PWR_VBAC_SUPPLY == CY_CFG_PWR_VBAC_SUPPLY_VDD) + if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) + { + Cy_SysLib_ResetBackupDomain(); + Cy_SysClk_IloDisable(); + Cy_SysClk_IloInit(); + } + #endif + #ifdef CY_CFG_PWR_ENABLED + /* Configure power mode */ + #if CY_CFG_PWR_USING_LDO + Cy_SysPm_LdoSetVoltage(CY_CFG_PWR_LDO_VOLTAGE); + #else + Cy_SysPm_BuckEnable(CY_CFG_PWR_BUCK_VOLTAGE); + #endif + /* Configure PMIC */ + Cy_SysPm_UnlockPmic(); + #if CY_CFG_PWR_USING_PMIC + Cy_SysPm_PmicEnableOutput(); + #else + Cy_SysPm_PmicDisableOutput(); + #endif + #endif + + /* Reset the core clock path to default and disable all the FLLs/PLLs */ + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkFastSetDivider(0U); + Cy_SysClk_ClkPeriSetDivider(1U); + Cy_SysClk_ClkSlowSetDivider(0U); + Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH1); + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); + + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && + (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) + { + Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); + } + + Cy_SysClk_FllDisable(); + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); + #ifdef CY_IP_MXBLESS + (void)Cy_BLE_EcoReset(); + #endif + + #ifdef CY_CFG_SYSCLK_PLL1_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2); + #endif + + #ifdef CY_CFG_SYSCLK_PLL2_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH3); + #endif + + #ifdef CY_CFG_SYSCLK_PLL3_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH4); + #endif + + #ifdef CY_CFG_SYSCLK_PLL4_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH5); + #endif + + #ifdef CY_CFG_SYSCLK_PLL5_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH6); + #endif + + #ifdef CY_CFG_SYSCLK_PLL6_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH7); + #endif + + #ifdef CY_CFG_SYSCLK_PLL7_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH8); + #endif + + #ifdef CY_CFG_SYSCLK_PLL8_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH9); + #endif + + #ifdef CY_CFG_SYSCLK_PLL9_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH10); + #endif + + #ifdef CY_CFG_SYSCLK_PLL10_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH11); + #endif + + #ifdef CY_CFG_SYSCLK_PLL11_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH12); + #endif + + #ifdef CY_CFG_SYSCLK_PLL12_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH13); + #endif + + #ifdef CY_CFG_SYSCLK_PLL13_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH14); + #endif + + #ifdef CY_CFG_SYSCLK_PLL14_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH15); + #endif + + /* Enable all source clocks */ + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + Cy_SysClk_PiloInit(); + #endif + + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + Cy_SysClk_WcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + Cy_SysClk_ClkLfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED + Cy_SysClk_AltHfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + Cy_SysClk_EcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + Cy_SysClk_ExtClkInit(); + #endif + + /* Configure CPU clock dividers */ + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED + Cy_SysClk_ClkFastInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + Cy_SysClk_ClkPeriInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + Cy_SysClk_ClkSlowInit(); + #endif + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ + Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); + #else + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure Path Clocks */ + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + Cy_SysClk_ClkPath0Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + Cy_SysClk_ClkPath2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + Cy_SysClk_ClkPath3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + Cy_SysClk_ClkPath4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + Cy_SysClk_ClkPath5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED + Cy_SysClk_ClkPath6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED + Cy_SysClk_ClkPath7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED + Cy_SysClk_ClkPath8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED + Cy_SysClk_ClkPath9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED + Cy_SysClk_ClkPath10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED + Cy_SysClk_ClkPath11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED + Cy_SysClk_ClkPath12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED + Cy_SysClk_ClkPath13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED + Cy_SysClk_ClkPath14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED + Cy_SysClk_ClkPath15Init(); + #endif + + /* Configure and enable FLL */ + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + Cy_SysClk_FllInit(); + #endif + + Cy_SysClk_ClkHf0Init(); + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + /* Apply the ClkPath1 user setting */ + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure and enable PLLs */ + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + Cy_SysClk_Pll0Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + Cy_SysClk_Pll1Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL2_ENABLED + Cy_SysClk_Pll2Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL3_ENABLED + Cy_SysClk_Pll3Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL4_ENABLED + Cy_SysClk_Pll4Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL5_ENABLED + Cy_SysClk_Pll5Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL6_ENABLED + Cy_SysClk_Pll6Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL7_ENABLED + Cy_SysClk_Pll7Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL8_ENABLED + Cy_SysClk_Pll8Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL9_ENABLED + Cy_SysClk_Pll9Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL10_ENABLED + Cy_SysClk_Pll10Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL11_ENABLED + Cy_SysClk_Pll11Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL12_ENABLED + Cy_SysClk_Pll12Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL13_ENABLED + Cy_SysClk_Pll13Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL14_ENABLED + Cy_SysClk_Pll14Init(); + #endif + + /* Configure HF clocks */ + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + Cy_SysClk_ClkHf1Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + Cy_SysClk_ClkHf2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + Cy_SysClk_ClkHf3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + Cy_SysClk_ClkHf4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + Cy_SysClk_ClkHf5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED + Cy_SysClk_ClkHf6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED + Cy_SysClk_ClkHf7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED + Cy_SysClk_ClkHf8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED + Cy_SysClk_ClkHf9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED + Cy_SysClk_ClkHf10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED + Cy_SysClk_ClkHf11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED + Cy_SysClk_ClkHf12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED + Cy_SysClk_ClkHf13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED + Cy_SysClk_ClkHf14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED + Cy_SysClk_ClkHf15Init(); + #endif + + /* Configure miscellaneous clocks */ + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED + Cy_SysClk_ClkTimerInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + Cy_SysClk_ClkAltSysTickInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + Cy_SysClk_ClkPumpInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + Cy_SysClk_ClkBakInit(); + #endif + + /* Configure default enabled clocks */ + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + Cy_SysClk_IloInit(); + #else + Cy_SysClk_IloDisable(); + #endif + + #ifndef CY_CFG_SYSCLK_IMO_ENABLED + #error the IMO must be enabled for proper chip operation + #endif + + /* Set accurate flash wait states */ + #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) + Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); + #endif + + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ + SystemCoreClockUpdate(); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.h new file mode 100644 index 0000000000..8db1d577b5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.h @@ -0,0 +1,53 @@ +/******************************************************************************* +* File Name: cycfg_platform.h +* +* Description: +* Platform configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PLATFORM_H) +#define CYCFG_PLATFORM_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_ble_clk.h" +#include "cy_gpio.h" +#include "cy_syspm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000 +#define CY_CFG_PWR_VDDA_MV 3300 +#define CY_CFG_PWR_VDDD_MV 3300 +#define CY_CFG_PWR_VBACKUP_MV 3300 +#define CY_CFG_PWR_VDD_NS_MV 3300 +#define CY_CFG_PWR_VDDIO0_MV 3300 +#define CY_CFG_PWR_VDDIO1_MV 3300 + +void init_cycfg_platform(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PLATFORM_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.c new file mode 100644 index 0000000000..cf7ac0229a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.c @@ -0,0 +1,34 @@ +/******************************************************************************* +* File Name: cycfg.c +* +* Description: +* Wrapper function to initialize all generated code. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg.h" + +void init_cycfg_all(void) +{ + init_cycfg_clocks(); + init_cycfg_peripherals(); + init_cycfg_pins(); + init_cycfg_platform(); + init_cycfg_connectivity(); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.h new file mode 100644 index 0000000000..faa061e3c2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.h @@ -0,0 +1,48 @@ +/******************************************************************************* +* File Name: cycfg.h +* +* Description: +* Simple wrapper header containing all generated files. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_H) +#define CYCFG_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +#include "cycfg_clocks.h" +#include "cycfg_dmas.h" +#include "cycfg_peripherals.h" +#include "cycfg_pins.h" +#include "cycfg_platform.h" +#include "cycfg_connectivity.h" + +void init_cycfg_all(void); + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.c new file mode 100644 index 0000000000..5249f7d3a0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.c @@ -0,0 +1,53 @@ +/******************************************************************************* +* File Name: cycfg_clocks.c +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_clocks.h" + + +void init_cycfg_clocks(void) +{ + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 108U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 1U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 255U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.h new file mode 100644 index 0000000000..0da97983ce --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.h @@ -0,0 +1,55 @@ +/******************************************************************************* +* File Name: cycfg_clocks.h +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_CLOCKS_H) +#define CYCFG_CLOCKS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define peri_0_div_16_0_HW CY_SYSCLK_DIV_16_BIT +#define peri_0_div_16_0_NUM 0U +#define peri_0_div_8_0_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_0_NUM 0U +#define peri_0_div_8_1_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_1_NUM 1U +#define peri_0_div_8_2_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_2_NUM 2U +#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_3_NUM 3U +#define peri_0_div_8_4_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_4_NUM 4U + +void init_cycfg_clocks(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_CLOCKS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_connectivity.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_connectivity.c new file mode 100644 index 0000000000..12ffa2a389 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_connectivity.c @@ -0,0 +1,51 @@ +/******************************************************************************* +* File Name: cycfg_connectivity.c +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_connectivity.h" + +#include "cy_trigmux.h" + +#include "stdbool.h" + +#include "cy_device_headers.h" + +void init_cycfg_connectivity(void) +{ + Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT0, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT3, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT47, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT46, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT43, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT49, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT4, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT6, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL); + HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; + HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_connectivity.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_connectivity.h new file mode 100644 index 0000000000..cf3efa8aa3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_connectivity.h @@ -0,0 +1,89 @@ +/******************************************************************************* +* File Name: cycfg_connectivity.h +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_CONNECTIVITY_H) +#define CYCFG_CONNECTIVITY_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +void init_cycfg_connectivity(void); + +#define ioss_0_port_11_pin_1_HSIOM P11_1_TCPWM1_LINE_COMPL1 +#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 +#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 +#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 +#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 +#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 +#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK +#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_2_pin_0_HSIOM P2_0_DSI_DSI +#define ioss_0_port_2_pin_1_HSIOM P2_1_DSI_DSI +#define ioss_0_port_2_pin_2_HSIOM P2_2_DSI_DSI +#define ioss_0_port_2_pin_3_HSIOM P2_3_DSI_DSI +#define ioss_0_port_2_pin_4_HSIOM P2_4_DSI_DSI +#define ioss_0_port_2_pin_5_HSIOM P2_5_DSI_GPIO +#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX +#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX +#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS +#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS +#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX +#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX +#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL +#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA +#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO +#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS +#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK +#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA + +#define cpuss_0_dw0_0_chan_0_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN0 +#define cpuss_0_dw0_0_chan_1_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN1 +#define cpuss_0_dw1_0_chan_1_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN1 +#define cpuss_0_dw1_0_chan_3_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN3 +#define udb_0_out_p_116_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB0 +#define udb_0_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT4 +#define udb_0_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT3 +#define udb_0_out_p_117_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB1 +#define udb_0_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT0 +#define udb_0_out_p_119_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB3 +#define udb_0_out_p_123_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB7 +#define udb_0_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT6 + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_CONNECTIVITY_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.c new file mode 100644 index 0000000000..a8e9de3e06 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.c @@ -0,0 +1,179 @@ +/******************************************************************************* +* File Name: cycfg_dmas.c +* +* Description: +* DMA configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_dmas.h" + +const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config = +{ + .retrigger = CY_DMA_RETRIG_IM, + .interruptType = CY_DMA_1ELEMENT, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_1ELEMENT, + .dataSize = CY_DMA_BYTE, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_1D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 0, + .dstXincrement = 1, + .xCount = 6, + .srcYincrement = 0, + .dstYincrement = 0, + .yCount = 1, + .nextDescriptor = NULL, +}; +cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0 = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL, +}; +const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig = +{ + .descriptor = &cpuss_0_dw0_0_chan_0_Descriptor_0, + .preemptable = true, + .priority = 1, + .enable = false, + .bufferable = false, +}; +const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config = +{ + .retrigger = CY_DMA_RETRIG_16CYC, + .interruptType = CY_DMA_1ELEMENT, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_1ELEMENT, + .dataSize = CY_DMA_BYTE, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_1D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 1, + .dstXincrement = 0, + .xCount = 5, + .srcYincrement = 0, + .dstYincrement = 0, + .yCount = 1, + .nextDescriptor = NULL, +}; +cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0 = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL, +}; +const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig = +{ + .descriptor = &cpuss_0_dw0_0_chan_1_Descriptor_0, + .preemptable = true, + .priority = 1, + .enable = false, + .bufferable = false, +}; +const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config = +{ + .retrigger = CY_DMA_RETRIG_4CYC, + .interruptType = CY_DMA_DESCR, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_X_LOOP, + .dataSize = CY_DMA_HALFWORD, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_2D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 2, + .dstXincrement = 0, + .xCount = 10, + .srcYincrement = 10, + .dstYincrement = 0, + .yCount = 2, + .nextDescriptor = NULL, +}; +cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0 = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL, +}; +const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig = +{ + .descriptor = &cpuss_0_dw1_0_chan_1_Descriptor_0, + .preemptable = false, + .priority = 0, + .enable = false, + .bufferable = false, +}; +const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config = +{ + .retrigger = CY_DMA_RETRIG_IM, + .interruptType = CY_DMA_DESCR, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_X_LOOP, + .dataSize = CY_DMA_HALFWORD, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_2D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 0, + .dstXincrement = 2, + .xCount = 10, + .srcYincrement = 0, + .dstYincrement = 10, + .yCount = 2, + .nextDescriptor = NULL, +}; +cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0 = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL, +}; +const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig = +{ + .descriptor = &cpuss_0_dw1_0_chan_3_Descriptor_0, + .preemptable = false, + .priority = 0, + .enable = false, + .bufferable = false, +}; + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.h new file mode 100644 index 0000000000..c68d4b9ec8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* File Name: cycfg_dmas.h +* +* Description: +* DMA configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_DMAS_H) +#define CYCFG_DMAS_H + +#include "cycfg_notices.h" +#include "cy_dma.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define cpuss_0_dw0_0_chan_0_HW DW0 +#define cpuss_0_dw0_0_chan_0_CHANNEL 0 +#define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn +#define cpuss_0_dw0_0_chan_1_HW DW0 +#define cpuss_0_dw0_0_chan_1_CHANNEL 1 +#define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn +#define cpuss_0_dw1_0_chan_1_HW DW1 +#define cpuss_0_dw1_0_chan_1_CHANNEL 1 +#define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn +#define cpuss_0_dw1_0_chan_3_HW DW1 +#define cpuss_0_dw1_0_chan_3_CHANNEL 3 +#define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn + +extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config; +extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0; +extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig; +extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config; +extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0; +extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig; +extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config; +extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0; +extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig; +extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config; +extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0; +extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig; + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_DMAS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_notices.h new file mode 100644 index 0000000000..90f1013f8a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_notices.h @@ -0,0 +1,30 @@ +/******************************************************************************* +* File Name: cycfg_notices.h +* +* Description: +* Contains warnings and errors that occurred while generating code for the +* design. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_NOTICES_H) +#define CYCFG_NOTICES_H + + +#endif /* CYCFG_NOTICES_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.c new file mode 100644 index 0000000000..67b745f805 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.c @@ -0,0 +1,204 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.c +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_peripherals.h" + +#define PWM_INPUT_DISABLED 0x7U +#define USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \ + CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \ + CY_USBFS_DEV_DRV_SET_EP1_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_EP2_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U)) + +cy_stc_csd_context_t cy_csd_0_context = +{ + .lockKey = CY_CSD_NONE_KEY, +}; +const cy_stc_scb_uart_config_t BT_UART_config = +{ + .uartMode = CY_SCB_UART_STANDARD, + .enableMutliProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + .oversample = 8, + .enableMsbFirst = false, + .dataWidth = 8UL, + .parity = CY_SCB_UART_PARITY_NONE, + .stopBits = CY_SCB_UART_STOP_BITS_1, + .enableInputFilter = false, + .breakWidth = 11UL, + .dropOnFrameError = false, + .dropOnParityError = false, + .receiverAddress = 0x0UL, + .receiverAddressMask = 0x0UL, + .acceptAddrInFifo = false, + .enableCts = true, + .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rtsRxFifoLevel = 63, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rxFifoTriggerLevel = 1UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, +}; +const cy_stc_scb_ezi2c_config_t CSD_COMM_config = +{ + .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS, + .slaveAddress1 = 8U, + .slaveAddress2 = 0U, + .subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS, + .enableWakeFromSleep = false, +}; +const cy_stc_scb_uart_config_t KITPROG_UART_config = +{ + .uartMode = CY_SCB_UART_STANDARD, + .enableMutliProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + .oversample = 8, + .enableMsbFirst = false, + .dataWidth = 8UL, + .parity = CY_SCB_UART_PARITY_NONE, + .stopBits = CY_SCB_UART_STOP_BITS_1, + .enableInputFilter = false, + .breakWidth = 11UL, + .dropOnFrameError = false, + .dropOnParityError = false, + .receiverAddress = 0x0UL, + .receiverAddressMask = 0x0UL, + .acceptAddrInFifo = false, + .enableCts = false, + .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rtsRxFifoLevel = 0UL, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rxFifoTriggerLevel = 63UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, +}; +const cy_stc_smif_config_t QSPI_config = +{ + .mode = (uint32_t)CY_SMIF_NORMAL, + .deselectDelay = QSPI_DESELECT_DELAY, + .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK, + .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, +}; +const cy_stc_mcwdt_config_t MCWDT0_config = +{ + .c0Match = 32768U, + .c1Match = 32768U, + .c0Mode = CY_MCWDT_MODE_NONE, + .c1Mode = CY_MCWDT_MODE_NONE, + .c2ToggleBit = 16U, + .c2Mode = CY_MCWDT_MODE_NONE, + .c0ClearOnMatch = false, + .c1ClearOnMatch = false, + .c0c1Cascade = true, + .c1c2Cascade = false, +}; +const cy_stc_rtc_config_t RTC_config = +{ + .sec = 0U, + .min = 0U, + .hour = 12U, + .amPm = CY_RTC_AM, + .hrFormat = CY_RTC_24_HOURS, + .dayOfWeek = CY_RTC_SUNDAY, + .date = 1U, + .month = CY_RTC_JANUARY, + .year = 0U, +}; +const cy_stc_tcpwm_pwm_config_t PWM_config = +{ + .pwmMode = CY_TCPWM_PWM_MODE_PWM, + .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, + .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, + .deadTimeClocks = 0, + .runMode = CY_TCPWM_PWM_CONTINUOUS, + .period0 = 32000, + .period1 = 32768, + .enablePeriodSwap = false, + .compare0 = 16384, + .compare1 = 16384, + .enableCompareSwap = false, + .interruptSources = CY_TCPWM_INT_NONE, + .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE, + .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE, + .killMode = CY_TCPWM_PWM_STOP_ON_KILL, + .swapInputMode = PWM_INPUT_DISABLED & 0x3U, + .swapInput = CY_TCPWM_INPUT_0, + .reloadInputMode = PWM_INPUT_DISABLED & 0x3U, + .reloadInput = CY_TCPWM_INPUT_0, + .startInputMode = PWM_INPUT_DISABLED & 0x3U, + .startInput = CY_TCPWM_INPUT_0, + .killInputMode = PWM_INPUT_DISABLED & 0x3U, + .killInput = CY_TCPWM_INPUT_0, + .countInputMode = PWM_INPUT_DISABLED & 0x3U, + .countInput = CY_TCPWM_INPUT_1, +}; +const cy_stc_usbfs_dev_drv_config_t USBUART_config = +{ + .mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU, + .epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR, + .epBuffer = NULL, + .epBufferSize = 0U, + .dmaConfig[0] = NULL, + .dmaConfig[1] = NULL, + .dmaConfig[2] = NULL, + .dmaConfig[3] = NULL, + .dmaConfig[4] = NULL, + .dmaConfig[5] = NULL, + .dmaConfig[6] = NULL, + .dmaConfig[7] = NULL, + .enableLpm = false, + .intrLevelSel = USBUART_INTR_LVL_SEL, +}; + + +void init_cycfg_peripherals(void) +{ + Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U); + + Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM1_CLOCKS1, CY_SYSCLK_DIV_8_BIT, 3U); + + Cy_SysClk_PeriphAssignDivider(PCLK_UDB_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 0u); + + Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.h new file mode 100644 index 0000000000..2170ac28c6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.h @@ -0,0 +1,140 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.h +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PERIPHERALS_H) +#define CYCFG_PERIPHERALS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_csd.h" +#include "cy_scb_uart.h" +#include "cy_scb_ezi2c.h" +#include "cy_smif.h" +#include "cy_mcwdt.h" +#include "cy_rtc.h" +#include "cy_tcpwm_pwm.h" +#include "cycfg_connectivity.h" +#include "cy_usbfs_dev_drv.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CY_CAPSENSE_CORE 4u +#define CY_CAPSENSE_CPU_CLK 100000000u +#define CY_CAPSENSE_PERI_CLK 100000000u +#define CY_CAPSENSE_VDDA_MV 3300u +#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT +#define CY_CAPSENSE_PERI_DIV_INDEX 4u +#define Cmod_PORT GPIO_PRT7 +#define CintA_PORT GPIO_PRT7 +#define CintB_PORT GPIO_PRT7 +#define Button0_Rx0_PORT GPIO_PRT8 +#define Button0_Tx_PORT GPIO_PRT1 +#define Button1_Rx0_PORT GPIO_PRT8 +#define Button1_Tx_PORT GPIO_PRT1 +#define LinearSlider0_Sns0_PORT GPIO_PRT8 +#define LinearSlider0_Sns1_PORT GPIO_PRT8 +#define LinearSlider0_Sns2_PORT GPIO_PRT8 +#define LinearSlider0_Sns3_PORT GPIO_PRT8 +#define LinearSlider0_Sns4_PORT GPIO_PRT8 +#define Cmod_PIN 7u +#define CintA_PIN 1u +#define CintB_PIN 2u +#define Button0_Rx0_PIN 1u +#define Button0_Tx_PIN 0u +#define Button1_Rx0_PIN 2u +#define Button1_Tx_PIN 0u +#define LinearSlider0_Sns0_PIN 3u +#define LinearSlider0_Sns1_PIN 4u +#define LinearSlider0_Sns2_PIN 5u +#define LinearSlider0_Sns3_PIN 6u +#define LinearSlider0_Sns4_PIN 7u +#define Cmod_PORT_NUM 7u +#define CintA_PORT_NUM 7u +#define CintB_PORT_NUM 7u +#define CapSense_HW CSD0 +#define CapSense_IRQ csd_interrupt_IRQn +#define BT_UART_HW SCB2 +#define BT_UART_IRQ scb_2_interrupt_IRQn +#define CSD_COMM_HW SCB3 +#define CSD_COMM_IRQ scb_3_interrupt_IRQn +#define KITPROG_UART_HW SCB5 +#define KITPROG_UART_IRQ scb_5_interrupt_IRQn +#define QSPI_HW SMIF0 +#define QSPI_IRQ smif_interrupt_IRQn +#define QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL) +#define QSPI_RX_DATA_FIFO_UNDERFLOW (0UL) +#define QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL) +#define QSPI_TX_DATA_FIFO_OVERFLOW (0UL) +#define QSPI_RX_FIFO_TRIGEER_LEVEL (0UL) +#define QSPI_TX_FIFO_TRIGEER_LEVEL (0UL) +#define QSPI_DATALINES0_1 (1UL) +#define QSPI_DATALINES2_3 (1UL) +#define QSPI_DATALINES4_5 (0UL) +#define QSPI_DATALINES6_7 (0UL) +#define QSPI_SS0 (1UL) +#define QSPI_SS1 (0UL) +#define QSPI_SS2 (0UL) +#define QSPI_SS3 (0UL) +#define QSPI_DESELECT_DELAY 7 +#define MCWDT0_HW MCWDT_STRUCT0 +#define RTC_10_MONTH_OFFSET (28U) +#define RTC_MONTH_OFFSET (24U) +#define RTC_10_DAY_OFFSET (20U) +#define RTC_DAY_OFFSET (16U) +#define RTC_1000_YEAR_OFFSET (12U) +#define RTC_100_YEAR_OFFSET (8U) +#define RTC_10_YEAR_OFFSET (4U) +#define RTC_YEAR_OFFSET (0U) +#define PWM_HW TCPWM1 +#define PWM_NUM 1UL +#define PWM_MASK (1UL << 1) +#define USBUART_ACTIVE_ENDPOINTS_MASK 7U +#define USBUART_ENDPOINTS_BUFFER_SIZE 140U +#define USBUART_ENDPOINTS_ACCESS_TYPE 0U +#define USBUART_USB_CORE 4U +#define USBUART_HW USBFS0 +#define USBUART_HI_IRQ usb_interrupt_hi_IRQn +#define USBUART_MED_IRQ usb_interrupt_med_IRQn +#define USBUART_LO_IRQ usb_interrupt_lo_IRQn + +extern cy_stc_csd_context_t cy_csd_0_context; +extern const cy_stc_scb_uart_config_t BT_UART_config; +extern const cy_stc_scb_ezi2c_config_t CSD_COMM_config; +extern const cy_stc_scb_uart_config_t KITPROG_UART_config; +extern const cy_stc_smif_config_t QSPI_config; +extern const cy_stc_mcwdt_config_t MCWDT0_config; +extern const cy_stc_rtc_config_t RTC_config; +extern const cy_stc_tcpwm_pwm_config_t PWM_config; +extern const cy_stc_usbfs_dev_drv_config_t USBUART_config; + +void init_cycfg_peripherals(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PERIPHERALS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.c new file mode 100644 index 0000000000..8fed53e210 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.c @@ -0,0 +1,883 @@ +/******************************************************************************* +* File Name: cycfg_pins.c +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_pins.h" + +const cy_stc_gpio_pin_config_t WCO_IN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = WCO_IN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t WCO_OUT_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = WCO_OUT_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED_RED_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED_RED_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SW2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = SW2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED_BLUE_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED_BLUE_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_SS0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = QSPI_SS0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = QSPI_SPI_CLOCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED9_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED9_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = ioss_0_port_14_pin_0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = ioss_0_port_14_pin_1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED_GREEN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED_GREEN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED8_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED8_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_DAT0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_DAT0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_DAT1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_DAT1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_DAT2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_DAT2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_DAT3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_DAT3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_CMD_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_CMD_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_CLK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = SDHC0_CLK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t ENABLE_WIFI_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = ENABLE_WIFI_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_UART_RX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = BT_UART_RX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_UART_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = BT_UART_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_UART_RTS_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = BT_UART_RTS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_UART_CTS_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = BT_UART_CTS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_POWER_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF, + .hsiom = BT_POWER_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = BT_HOST_WAKE_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = BT_DEVICE_WAKE_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t UART_RX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = UART_RX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t UART_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = UART_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t EZI2C_SCL_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = EZI2C_SCL_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t EZI2C_SDA_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = EZI2C_SDA_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SWO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = SWO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SWDIO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = SWDIO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SWDCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLDOWN, + .hsiom = SWDCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CINA_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CINA_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CINB_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CINB_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CMOD_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CMOD_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_BTN0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_BTN0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_BTN1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_BTN1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD4_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD4_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; + + +void init_cycfg_pins(void) +{ + Cy_GPIO_Pin_Init(WCO_IN_PORT, WCO_IN_PIN, &WCO_IN_config); + + Cy_GPIO_Pin_Init(WCO_OUT_PORT, WCO_OUT_PIN, &WCO_OUT_config); + + Cy_GPIO_Pin_Init(LED_RED_PORT, LED_RED_PIN, &LED_RED_config); + + Cy_GPIO_Pin_Init(SW2_PORT, SW2_PIN, &SW2_config); + + Cy_GPIO_Pin_Init(LED_BLUE_PORT, LED_BLUE_PIN, &LED_BLUE_config); + + Cy_GPIO_Pin_Init(QSPI_SS0_PORT, QSPI_SS0_PIN, &QSPI_SS0_config); + + Cy_GPIO_Pin_Init(QSPI_DATA3_PORT, QSPI_DATA3_PIN, &QSPI_DATA3_config); + + Cy_GPIO_Pin_Init(QSPI_DATA2_PORT, QSPI_DATA2_PIN, &QSPI_DATA2_config); + + Cy_GPIO_Pin_Init(QSPI_DATA1_PORT, QSPI_DATA1_PIN, &QSPI_DATA1_config); + + Cy_GPIO_Pin_Init(QSPI_DATA0_PORT, QSPI_DATA0_PIN, &QSPI_DATA0_config); + + Cy_GPIO_Pin_Init(QSPI_SPI_CLOCK_PORT, QSPI_SPI_CLOCK_PIN, &QSPI_SPI_CLOCK_config); + + Cy_GPIO_Pin_Init(LED9_PORT, LED9_PIN, &LED9_config); + + Cy_GPIO_Pin_Init(ioss_0_port_14_pin_0_PORT, ioss_0_port_14_pin_0_PIN, &ioss_0_port_14_pin_0_config); + + Cy_GPIO_Pin_Init(ioss_0_port_14_pin_1_PORT, ioss_0_port_14_pin_1_PIN, &ioss_0_port_14_pin_1_config); + + + Cy_GPIO_Pin_Init(LED_GREEN_PORT, LED_GREEN_PIN, &LED_GREEN_config); + + Cy_GPIO_Pin_Init(LED8_PORT, LED8_PIN, &LED8_config); + + Cy_GPIO_Pin_Init(SDHC0_DAT0_PORT, SDHC0_DAT0_PIN, &SDHC0_DAT0_config); + + Cy_GPIO_Pin_Init(SDHC0_DAT1_PORT, SDHC0_DAT1_PIN, &SDHC0_DAT1_config); + + Cy_GPIO_Pin_Init(SDHC0_DAT2_PORT, SDHC0_DAT2_PIN, &SDHC0_DAT2_config); + + Cy_GPIO_Pin_Init(SDHC0_DAT3_PORT, SDHC0_DAT3_PIN, &SDHC0_DAT3_config); + + Cy_GPIO_Pin_Init(SDHC0_CMD_PORT, SDHC0_CMD_PIN, &SDHC0_CMD_config); + + Cy_GPIO_Pin_Init(SDHC0_CLK_PORT, SDHC0_CLK_PIN, &SDHC0_CLK_config); + + Cy_GPIO_Pin_Init(ENABLE_WIFI_PORT, ENABLE_WIFI_PIN, &ENABLE_WIFI_config); + + Cy_GPIO_Pin_Init(BT_UART_RX_PORT, BT_UART_RX_PIN, &BT_UART_RX_config); + + Cy_GPIO_Pin_Init(BT_UART_TX_PORT, BT_UART_TX_PIN, &BT_UART_TX_config); + + Cy_GPIO_Pin_Init(BT_UART_RTS_PORT, BT_UART_RTS_PIN, &BT_UART_RTS_config); + + Cy_GPIO_Pin_Init(BT_UART_CTS_PORT, BT_UART_CTS_PIN, &BT_UART_CTS_config); + + Cy_GPIO_Pin_Init(BT_POWER_PORT, BT_POWER_PIN, &BT_POWER_config); + + Cy_GPIO_Pin_Init(BT_HOST_WAKE_PORT, BT_HOST_WAKE_PIN, &BT_HOST_WAKE_config); + + Cy_GPIO_Pin_Init(BT_DEVICE_WAKE_PORT, BT_DEVICE_WAKE_PIN, &BT_DEVICE_WAKE_config); + + Cy_GPIO_Pin_Init(UART_RX_PORT, UART_RX_PIN, &UART_RX_config); + + Cy_GPIO_Pin_Init(UART_TX_PORT, UART_TX_PIN, &UART_TX_config); + + Cy_GPIO_Pin_Init(EZI2C_SCL_PORT, EZI2C_SCL_PIN, &EZI2C_SCL_config); + + Cy_GPIO_Pin_Init(EZI2C_SDA_PORT, EZI2C_SDA_PIN, &EZI2C_SDA_config); + + Cy_GPIO_Pin_Init(SWO_PORT, SWO_PIN, &SWO_config); + + Cy_GPIO_Pin_Init(SWDIO_PORT, SWDIO_PIN, &SWDIO_config); + + Cy_GPIO_Pin_Init(SWDCK_PORT, SWDCK_PIN, &SWDCK_config); + + + + + + + + + + +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.h new file mode 100644 index 0000000000..776325ec01 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.h @@ -0,0 +1,571 @@ +/******************************************************************************* +* File Name: cycfg_pins.h +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PINS_H) +#define CYCFG_PINS_H + +#include "cycfg_notices.h" +#include "cy_gpio.h" +#include "cycfg_connectivity.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define WCO_IN_PORT GPIO_PRT0 +#define WCO_IN_PIN 0U +#define WCO_IN_NUM 0U +#define WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG +#define WCO_IN_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_0_HSIOM + #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM +#define WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn +#define WCO_OUT_PORT GPIO_PRT0 +#define WCO_OUT_PIN 1U +#define WCO_OUT_NUM 1U +#define WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG +#define WCO_OUT_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_1_HSIOM + #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM +#define WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn +#define LED_RED_PORT GPIO_PRT0 +#define LED_RED_PIN 3U +#define LED_RED_NUM 3U +#define LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED_RED_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_3_HSIOM + #define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM +#define LED_RED_IRQ ioss_interrupts_gpio_0_IRQn +#define SW2_PORT GPIO_PRT0 +#define SW2_PIN 4U +#define SW2_NUM 4U +#define SW2_DRIVEMODE CY_GPIO_DM_PULLUP +#define SW2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_4_HSIOM + #define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define SW2_HSIOM ioss_0_port_0_pin_4_HSIOM +#define SW2_IRQ ioss_interrupts_gpio_0_IRQn +#define LED_BLUE_PORT GPIO_PRT11 +#define LED_BLUE_PIN 1U +#define LED_BLUE_NUM 1U +#define LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED_BLUE_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_1_HSIOM + #define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM +#define LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_SS0_PORT GPIO_PRT11 +#define QSPI_SS0_PIN 2U +#define QSPI_SS0_NUM 2U +#define QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define QSPI_SS0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_2_HSIOM + #define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM +#define QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA3_PORT GPIO_PRT11 +#define QSPI_DATA3_PIN 3U +#define QSPI_DATA3_NUM 3U +#define QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_3_HSIOM + #define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM +#define QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA2_PORT GPIO_PRT11 +#define QSPI_DATA2_PIN 4U +#define QSPI_DATA2_NUM 4U +#define QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_4_HSIOM + #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM +#define QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA1_PORT GPIO_PRT11 +#define QSPI_DATA1_PIN 5U +#define QSPI_DATA1_NUM 5U +#define QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_5_HSIOM + #define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM +#define QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA0_PORT GPIO_PRT11 +#define QSPI_DATA0_PIN 6U +#define QSPI_DATA0_NUM 6U +#define QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_6_HSIOM + #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM +#define QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_SPI_CLOCK_PORT GPIO_PRT11 +#define QSPI_SPI_CLOCK_PIN 7U +#define QSPI_SPI_CLOCK_NUM 7U +#define QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define QSPI_SPI_CLOCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_7_HSIOM + #define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM +#define QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn +#define LED9_PORT GPIO_PRT13 +#define LED9_PIN 7U +#define LED9_NUM 7U +#define LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED9_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_13_pin_7_HSIOM + #define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define LED9_HSIOM ioss_0_port_13_pin_7_HSIOM +#define LED9_IRQ ioss_interrupts_gpio_13_IRQn +#define ioss_0_port_14_pin_0_PORT GPIO_PRT14 +#define ioss_0_port_14_pin_0_PIN 0U +#define ioss_0_port_14_pin_0_NUM 0U +#define ioss_0_port_14_pin_0_DRIVEMODE CY_GPIO_DM_ANALOG +#define ioss_0_port_14_pin_0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_14_pin_0_HSIOM + #define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define ioss_0_port_14_pin_0_IRQ ioss_interrupts_gpio_14_IRQn +#define ioss_0_port_14_pin_1_PORT GPIO_PRT14 +#define ioss_0_port_14_pin_1_PIN 1U +#define ioss_0_port_14_pin_1_NUM 1U +#define ioss_0_port_14_pin_1_DRIVEMODE CY_GPIO_DM_ANALOG +#define ioss_0_port_14_pin_1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_14_pin_1_HSIOM + #define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define ioss_0_port_14_pin_1_IRQ ioss_interrupts_gpio_14_IRQn +#define CSD_TX_PORT GPIO_PRT1 +#define CSD_TX_PIN 0U +#define CSD_TX_NUM 0U +#define CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_0_HSIOM + #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM +#define CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn +#define LED_GREEN_PORT GPIO_PRT1 +#define LED_GREEN_PIN 1U +#define LED_GREEN_NUM 1U +#define LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED_GREEN_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_1_HSIOM + #define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM +#define LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn +#define LED8_PORT GPIO_PRT1 +#define LED8_PIN 5U +#define LED8_NUM 5U +#define LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED8_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_5_HSIOM + #define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define LED8_HSIOM ioss_0_port_1_pin_5_HSIOM +#define LED8_IRQ ioss_interrupts_gpio_1_IRQn +#define SDHC0_DAT0_PORT GPIO_PRT2 +#define SDHC0_DAT0_PIN 0U +#define SDHC0_DAT0_NUM 0U +#define SDHC0_DAT0_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_DAT0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_0_HSIOM + #define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_DAT0_HSIOM ioss_0_port_2_pin_0_HSIOM +#define SDHC0_DAT0_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_DAT1_PORT GPIO_PRT2 +#define SDHC0_DAT1_PIN 1U +#define SDHC0_DAT1_NUM 1U +#define SDHC0_DAT1_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_DAT1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_1_HSIOM + #define ioss_0_port_2_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_DAT1_HSIOM ioss_0_port_2_pin_1_HSIOM +#define SDHC0_DAT1_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_DAT2_PORT GPIO_PRT2 +#define SDHC0_DAT2_PIN 2U +#define SDHC0_DAT2_NUM 2U +#define SDHC0_DAT2_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_DAT2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_2_HSIOM + #define ioss_0_port_2_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_DAT2_HSIOM ioss_0_port_2_pin_2_HSIOM +#define SDHC0_DAT2_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_DAT3_PORT GPIO_PRT2 +#define SDHC0_DAT3_PIN 3U +#define SDHC0_DAT3_NUM 3U +#define SDHC0_DAT3_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_DAT3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_3_HSIOM + #define ioss_0_port_2_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_DAT3_HSIOM ioss_0_port_2_pin_3_HSIOM +#define SDHC0_DAT3_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_CMD_PORT GPIO_PRT2 +#define SDHC0_CMD_PIN 4U +#define SDHC0_CMD_NUM 4U +#define SDHC0_CMD_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_CMD_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_4_HSIOM + #define ioss_0_port_2_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM +#define SDHC0_CMD_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_CLK_PORT GPIO_PRT2 +#define SDHC0_CLK_PIN 5U +#define SDHC0_CLK_NUM 5U +#define SDHC0_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define SDHC0_CLK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_5_HSIOM + #define ioss_0_port_2_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM +#define SDHC0_CLK_IRQ ioss_interrupts_gpio_2_IRQn +#define ENABLE_WIFI_PORT GPIO_PRT2 +#define ENABLE_WIFI_PIN 6U +#define ENABLE_WIFI_NUM 6U +#define ENABLE_WIFI_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define ENABLE_WIFI_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_2_pin_6_HSIOM + #define ioss_0_port_2_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define ENABLE_WIFI_HSIOM ioss_0_port_2_pin_6_HSIOM +#define ENABLE_WIFI_IRQ ioss_interrupts_gpio_2_IRQn +#define BT_UART_RX_PORT GPIO_PRT3 +#define BT_UART_RX_PIN 0U +#define BT_UART_RX_NUM 0U +#define BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ +#define BT_UART_RX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_0_HSIOM + #define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM +#define BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_UART_TX_PORT GPIO_PRT3 +#define BT_UART_TX_PIN 1U +#define BT_UART_TX_NUM 1U +#define BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define BT_UART_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_1_HSIOM + #define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM +#define BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_UART_RTS_PORT GPIO_PRT3 +#define BT_UART_RTS_PIN 2U +#define BT_UART_RTS_NUM 2U +#define BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define BT_UART_RTS_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_2_HSIOM + #define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM +#define BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_UART_CTS_PORT GPIO_PRT3 +#define BT_UART_CTS_PIN 3U +#define BT_UART_CTS_NUM 3U +#define BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ +#define BT_UART_CTS_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_3_HSIOM + #define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM +#define BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_POWER_PORT GPIO_PRT3 +#define BT_POWER_PIN 4U +#define BT_POWER_NUM 4U +#define BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF +#define BT_POWER_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_4_HSIOM + #define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM +#define BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_HOST_WAKE_PORT GPIO_PRT3 +#define BT_HOST_WAKE_PIN 5U +#define BT_HOST_WAKE_NUM 5U +#define BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG +#define BT_HOST_WAKE_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_3_pin_5_HSIOM + #define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM +#define BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_DEVICE_WAKE_PORT GPIO_PRT4 +#define BT_DEVICE_WAKE_PIN 0U +#define BT_DEVICE_WAKE_NUM 0U +#define BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define BT_DEVICE_WAKE_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_4_pin_0_HSIOM + #define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM +#define BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn +#define UART_RX_PORT GPIO_PRT5 +#define UART_RX_PIN 0U +#define UART_RX_NUM 0U +#define UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ +#define UART_RX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_5_pin_0_HSIOM + #define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM +#define UART_RX_IRQ ioss_interrupts_gpio_5_IRQn +#define UART_TX_PORT GPIO_PRT5 +#define UART_TX_PIN 1U +#define UART_TX_NUM 1U +#define UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define UART_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_5_pin_1_HSIOM + #define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM +#define UART_TX_IRQ ioss_interrupts_gpio_5_IRQn +#define EZI2C_SCL_PORT GPIO_PRT6 +#define EZI2C_SCL_PIN 0U +#define EZI2C_SCL_NUM 0U +#define EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define EZI2C_SCL_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_0_HSIOM + #define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM +#define EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn +#define EZI2C_SDA_PORT GPIO_PRT6 +#define EZI2C_SDA_PIN 1U +#define EZI2C_SDA_NUM 1U +#define EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define EZI2C_SDA_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_1_HSIOM + #define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM +#define EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn +#define SWO_PORT GPIO_PRT6 +#define SWO_PIN 4U +#define SWO_NUM 4U +#define SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define SWO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_4_HSIOM + #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define SWO_HSIOM ioss_0_port_6_pin_4_HSIOM +#define SWO_IRQ ioss_interrupts_gpio_6_IRQn +#define SWDIO_PORT GPIO_PRT6 +#define SWDIO_PIN 6U +#define SWDIO_NUM 6U +#define SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP +#define SWDIO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_6_HSIOM + #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM +#define SWDIO_IRQ ioss_interrupts_gpio_6_IRQn +#define SWDCK_PORT GPIO_PRT6 +#define SWDCK_PIN 7U +#define SWDCK_NUM 7U +#define SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN +#define SWDCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_7_HSIOM + #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM +#define SWDCK_IRQ ioss_interrupts_gpio_6_IRQn +#define CINA_PORT GPIO_PRT7 +#define CINA_PIN 1U +#define CINA_NUM 1U +#define CINA_DRIVEMODE CY_GPIO_DM_ANALOG +#define CINA_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_1_HSIOM + #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CINA_HSIOM ioss_0_port_7_pin_1_HSIOM +#define CINA_IRQ ioss_interrupts_gpio_7_IRQn +#define CINB_PORT GPIO_PRT7 +#define CINB_PIN 2U +#define CINB_NUM 2U +#define CINB_DRIVEMODE CY_GPIO_DM_ANALOG +#define CINB_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_2_HSIOM + #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CINB_HSIOM ioss_0_port_7_pin_2_HSIOM +#define CINB_IRQ ioss_interrupts_gpio_7_IRQn +#define CMOD_PORT GPIO_PRT7 +#define CMOD_PIN 7U +#define CMOD_NUM 7U +#define CMOD_DRIVEMODE CY_GPIO_DM_ANALOG +#define CMOD_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_7_HSIOM + #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM +#define CMOD_IRQ ioss_interrupts_gpio_7_IRQn +#define CSD_BTN0_PORT GPIO_PRT8 +#define CSD_BTN0_PIN 1U +#define CSD_BTN0_NUM 1U +#define CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_BTN0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_1_HSIOM + #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM +#define CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_BTN1_PORT GPIO_PRT8 +#define CSD_BTN1_PIN 2U +#define CSD_BTN1_NUM 2U +#define CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_BTN1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_2_HSIOM + #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM +#define CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD0_PORT GPIO_PRT8 +#define CSD_SLD0_PIN 3U +#define CSD_SLD0_NUM 3U +#define CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_3_HSIOM + #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM +#define CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD1_PORT GPIO_PRT8 +#define CSD_SLD1_PIN 4U +#define CSD_SLD1_NUM 4U +#define CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_4_HSIOM + #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM +#define CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD2_PORT GPIO_PRT8 +#define CSD_SLD2_PIN 5U +#define CSD_SLD2_NUM 5U +#define CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_5_HSIOM + #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM +#define CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD3_PORT GPIO_PRT8 +#define CSD_SLD3_PIN 6U +#define CSD_SLD3_NUM 6U +#define CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_6_HSIOM + #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM +#define CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD4_PORT GPIO_PRT8 +#define CSD_SLD4_PIN 7U +#define CSD_SLD4_NUM 7U +#define CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD4_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_7_HSIOM + #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM +#define CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn + +extern const cy_stc_gpio_pin_config_t WCO_IN_config; +extern const cy_stc_gpio_pin_config_t WCO_OUT_config; +extern const cy_stc_gpio_pin_config_t LED_RED_config; +extern const cy_stc_gpio_pin_config_t SW2_config; +extern const cy_stc_gpio_pin_config_t LED_BLUE_config; +extern const cy_stc_gpio_pin_config_t QSPI_SS0_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA3_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA2_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA1_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA0_config; +extern const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config; +extern const cy_stc_gpio_pin_config_t LED9_config; +extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config; +extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config; +extern const cy_stc_gpio_pin_config_t CSD_TX_config; +extern const cy_stc_gpio_pin_config_t LED_GREEN_config; +extern const cy_stc_gpio_pin_config_t LED8_config; +extern const cy_stc_gpio_pin_config_t SDHC0_DAT0_config; +extern const cy_stc_gpio_pin_config_t SDHC0_DAT1_config; +extern const cy_stc_gpio_pin_config_t SDHC0_DAT2_config; +extern const cy_stc_gpio_pin_config_t SDHC0_DAT3_config; +extern const cy_stc_gpio_pin_config_t SDHC0_CMD_config; +extern const cy_stc_gpio_pin_config_t SDHC0_CLK_config; +extern const cy_stc_gpio_pin_config_t ENABLE_WIFI_config; +extern const cy_stc_gpio_pin_config_t BT_UART_RX_config; +extern const cy_stc_gpio_pin_config_t BT_UART_TX_config; +extern const cy_stc_gpio_pin_config_t BT_UART_RTS_config; +extern const cy_stc_gpio_pin_config_t BT_UART_CTS_config; +extern const cy_stc_gpio_pin_config_t BT_POWER_config; +extern const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config; +extern const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config; +extern const cy_stc_gpio_pin_config_t UART_RX_config; +extern const cy_stc_gpio_pin_config_t UART_TX_config; +extern const cy_stc_gpio_pin_config_t EZI2C_SCL_config; +extern const cy_stc_gpio_pin_config_t EZI2C_SDA_config; +extern const cy_stc_gpio_pin_config_t SWO_config; +extern const cy_stc_gpio_pin_config_t SWDIO_config; +extern const cy_stc_gpio_pin_config_t SWDCK_config; +extern const cy_stc_gpio_pin_config_t CINA_config; +extern const cy_stc_gpio_pin_config_t CINB_config; +extern const cy_stc_gpio_pin_config_t CMOD_config; +extern const cy_stc_gpio_pin_config_t CSD_BTN0_config; +extern const cy_stc_gpio_pin_config_t CSD_BTN1_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD0_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD1_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD2_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD3_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD4_config; + +void init_cycfg_pins(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PINS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.c new file mode 100644 index 0000000000..8f247b0267 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.c @@ -0,0 +1,557 @@ +/******************************************************************************* +* File Name: cycfg_platform.c +* +* Description: +* Platform configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_platform.h" + +#define CY_CFG_SYSCLK_ECO_ERROR 1 +#define CY_CFG_SYSCLK_ALTHF_ERROR 2 +#define CY_CFG_SYSCLK_PLL_ERROR 3 +#define CY_CFG_SYSCLK_FLL_ERROR 4 +#define CY_CFG_SYSCLK_WCO_ERROR 5 +#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 +#define CY_CFG_SYSCLK_FLL_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 48UL +#define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1 +#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL +#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL +#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1 +#define CY_CFG_SYSCLK_ILO_ENABLED 1 +#define CY_CFG_SYSCLK_IMO_ENABLED 1 +#define CY_CFG_SYSCLK_CLKLF_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 +#define CY_CFG_SYSCLK_PLL0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 +#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1 +#define CY_CFG_SYSCLK_WCO_ENABLED 1 +#define CY_CFG_PWR_ENABLED 1 +#define CY_CFG_PWR_USING_LDO 1 +#define CY_CFG_PWR_USING_PMIC 0 +#define CY_CFG_PWR_VBAC_SUPPLY CY_CFG_PWR_VBAC_SUPPLY_VDD +#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_1_1V +#define CY_CFG_PWR_USING_ULP 0 + +static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = +{ + .fllMult = 500U, + .refDiv = 20U, + .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, + .enableOutputDiv = true, + .lockTolerance = 4U, + .igain = 9U, + .pgain = 5U, + .settlingCount = 8U, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, + .cco_Freq = 355U, +}; +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = +{ + .feedbackDiv = 30, + .referenceDiv = 1, + .outputDiv = 5, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, +}; + +__WEAK void cycfg_ClockStartupError(uint32_t error) +{ + (void)error; /* Suppress the compiler warning */ + while(1); +} +__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit() +{ + Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF); +} +__STATIC_INLINE void Cy_SysClk_ClkBakInit() +{ + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); +} +__STATIC_INLINE void Cy_SysClk_ClkFastInit() +{ + Cy_SysClk_ClkFastSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_FllInit() +{ + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } +} +__STATIC_INLINE void Cy_SysClk_ClkHf0Init() +{ + Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); +} +__STATIC_INLINE void Cy_SysClk_ClkHf1Init() +{ + Cy_SysClk_ClkHfSetSource(1U, CY_CFG_SYSCLK_CLKHF1_CLKPATH); + Cy_SysClk_ClkHfSetDivider(1U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfEnable(1U); +} +__STATIC_INLINE void Cy_SysClk_ClkHf2Init() +{ + Cy_SysClk_ClkHfSetSource(2U, CY_CFG_SYSCLK_CLKHF2_CLKPATH); + Cy_SysClk_ClkHfSetDivider(2U, CY_SYSCLK_CLKHF_DIVIDE_BY_2); + Cy_SysClk_ClkHfEnable(2U); +} +__STATIC_INLINE void Cy_SysClk_ClkHf3Init() +{ + Cy_SysClk_ClkHfSetSource(3U, CY_CFG_SYSCLK_CLKHF3_CLKPATH); + Cy_SysClk_ClkHfSetDivider(3U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfEnable(3U); +} +__STATIC_INLINE void Cy_SysClk_IloInit() +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_IloEnable(); + Cy_SysClk_IloHibernateOn(true); +} +__STATIC_INLINE void Cy_SysClk_ClkLfInit() +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO); +} +__STATIC_INLINE void Cy_SysClk_ClkPath0Init() +{ + Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath1Init() +{ + Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath2Init() +{ + Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath3Init() +{ + Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath4Init() +{ + Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPeriInit() +{ + Cy_SysClk_ClkPeriSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_Pll0Init() +{ + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } +} +__STATIC_INLINE void Cy_SysClk_ClkSlowInit() +{ + Cy_SysClk_ClkSlowSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_ClkTimerInit() +{ + Cy_SysClk_ClkTimerDisable(); + Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO); + Cy_SysClk_ClkTimerSetDivider(0U); + Cy_SysClk_ClkTimerEnable(); +} +__STATIC_INLINE void Cy_SysClk_WcoInit() +{ + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); + } +} + + +void init_cycfg_platform(void) +{ + /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ + Cy_SysLib_SetWaitStates(false, 150UL); + #if (CY_CFG_PWR_VBAC_SUPPLY == CY_CFG_PWR_VBAC_SUPPLY_VDD) + if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) + { + Cy_SysLib_ResetBackupDomain(); + Cy_SysClk_IloDisable(); + Cy_SysClk_IloInit(); + } + #endif + #ifdef CY_CFG_PWR_ENABLED + /* Configure power mode */ + #if CY_CFG_PWR_USING_LDO + Cy_SysPm_LdoSetVoltage(CY_CFG_PWR_LDO_VOLTAGE); + #else + Cy_SysPm_BuckEnable(CY_CFG_PWR_BUCK_VOLTAGE); + #endif + /* Configure PMIC */ + Cy_SysPm_UnlockPmic(); + #if CY_CFG_PWR_USING_PMIC + Cy_SysPm_PmicEnableOutput(); + #else + Cy_SysPm_PmicDisableOutput(); + #endif + #endif + + /* Reset the core clock path to default and disable all the FLLs/PLLs */ + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkFastSetDivider(0U); + Cy_SysClk_ClkPeriSetDivider(1U); + Cy_SysClk_ClkSlowSetDivider(0U); + Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH1); + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); + + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && + (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) + { + Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); + } + + Cy_SysClk_FllDisable(); + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); + #ifdef CY_IP_MXBLESS + (void)Cy_BLE_EcoReset(); + #endif + + #ifdef CY_CFG_SYSCLK_PLL1_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2); + #endif + + #ifdef CY_CFG_SYSCLK_PLL2_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH3); + #endif + + #ifdef CY_CFG_SYSCLK_PLL3_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH4); + #endif + + #ifdef CY_CFG_SYSCLK_PLL4_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH5); + #endif + + #ifdef CY_CFG_SYSCLK_PLL5_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH6); + #endif + + #ifdef CY_CFG_SYSCLK_PLL6_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH7); + #endif + + #ifdef CY_CFG_SYSCLK_PLL7_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH8); + #endif + + #ifdef CY_CFG_SYSCLK_PLL8_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH9); + #endif + + #ifdef CY_CFG_SYSCLK_PLL9_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH10); + #endif + + #ifdef CY_CFG_SYSCLK_PLL10_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH11); + #endif + + #ifdef CY_CFG_SYSCLK_PLL11_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH12); + #endif + + #ifdef CY_CFG_SYSCLK_PLL12_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH13); + #endif + + #ifdef CY_CFG_SYSCLK_PLL13_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH14); + #endif + + #ifdef CY_CFG_SYSCLK_PLL14_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH15); + #endif + + /* Enable all source clocks */ + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + Cy_SysClk_PiloInit(); + #endif + + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + Cy_SysClk_WcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + Cy_SysClk_ClkLfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED + Cy_SysClk_AltHfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + Cy_SysClk_EcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + Cy_SysClk_ExtClkInit(); + #endif + + /* Configure CPU clock dividers */ + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED + Cy_SysClk_ClkFastInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + Cy_SysClk_ClkPeriInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + Cy_SysClk_ClkSlowInit(); + #endif + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ + Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); + #else + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure Path Clocks */ + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + Cy_SysClk_ClkPath0Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + Cy_SysClk_ClkPath2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + Cy_SysClk_ClkPath3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + Cy_SysClk_ClkPath4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + Cy_SysClk_ClkPath5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED + Cy_SysClk_ClkPath6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED + Cy_SysClk_ClkPath7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED + Cy_SysClk_ClkPath8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED + Cy_SysClk_ClkPath9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED + Cy_SysClk_ClkPath10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED + Cy_SysClk_ClkPath11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED + Cy_SysClk_ClkPath12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED + Cy_SysClk_ClkPath13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED + Cy_SysClk_ClkPath14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED + Cy_SysClk_ClkPath15Init(); + #endif + + /* Configure and enable FLL */ + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + Cy_SysClk_FllInit(); + #endif + + Cy_SysClk_ClkHf0Init(); + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + /* Apply the ClkPath1 user setting */ + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure and enable PLLs */ + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + Cy_SysClk_Pll0Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + Cy_SysClk_Pll1Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL2_ENABLED + Cy_SysClk_Pll2Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL3_ENABLED + Cy_SysClk_Pll3Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL4_ENABLED + Cy_SysClk_Pll4Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL5_ENABLED + Cy_SysClk_Pll5Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL6_ENABLED + Cy_SysClk_Pll6Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL7_ENABLED + Cy_SysClk_Pll7Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL8_ENABLED + Cy_SysClk_Pll8Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL9_ENABLED + Cy_SysClk_Pll9Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL10_ENABLED + Cy_SysClk_Pll10Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL11_ENABLED + Cy_SysClk_Pll11Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL12_ENABLED + Cy_SysClk_Pll12Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL13_ENABLED + Cy_SysClk_Pll13Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL14_ENABLED + Cy_SysClk_Pll14Init(); + #endif + + /* Configure HF clocks */ + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + Cy_SysClk_ClkHf1Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + Cy_SysClk_ClkHf2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + Cy_SysClk_ClkHf3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + Cy_SysClk_ClkHf4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + Cy_SysClk_ClkHf5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED + Cy_SysClk_ClkHf6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED + Cy_SysClk_ClkHf7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED + Cy_SysClk_ClkHf8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED + Cy_SysClk_ClkHf9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED + Cy_SysClk_ClkHf10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED + Cy_SysClk_ClkHf11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED + Cy_SysClk_ClkHf12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED + Cy_SysClk_ClkHf13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED + Cy_SysClk_ClkHf14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED + Cy_SysClk_ClkHf15Init(); + #endif + + /* Configure miscellaneous clocks */ + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED + Cy_SysClk_ClkTimerInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + Cy_SysClk_ClkAltSysTickInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + Cy_SysClk_ClkPumpInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + Cy_SysClk_ClkBakInit(); + #endif + + /* Configure default enabled clocks */ + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + Cy_SysClk_IloInit(); + #else + Cy_SysClk_IloDisable(); + #endif + + #ifndef CY_CFG_SYSCLK_IMO_ENABLED + #error the IMO must be enabled for proper chip operation + #endif + + /* Set accurate flash wait states */ + #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) + Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); + #endif + + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ + SystemCoreClockUpdate(); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.h new file mode 100644 index 0000000000..4feda6f95f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.h @@ -0,0 +1,53 @@ +/******************************************************************************* +* File Name: cycfg_platform.h +* +* Description: +* Platform configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PLATFORM_H) +#define CYCFG_PLATFORM_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_systick.h" +#include "cy_gpio.h" +#include "cy_syspm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000 +#define CY_CFG_PWR_VDDA_MV 3300 +#define CY_CFG_PWR_VDDD_MV 3300 +#define CY_CFG_PWR_VBACKUP_MV 3300 +#define CY_CFG_PWR_VDD_NS_MV 3300 +#define CY_CFG_PWR_VDDIO0_MV 3300 +#define CY_CFG_PWR_VDDIO1_MV 3300 + +void init_cycfg_platform(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PLATFORM_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.c new file mode 100644 index 0000000000..cf7ac0229a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.c @@ -0,0 +1,34 @@ +/******************************************************************************* +* File Name: cycfg.c +* +* Description: +* Wrapper function to initialize all generated code. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg.h" + +void init_cycfg_all(void) +{ + init_cycfg_clocks(); + init_cycfg_peripherals(); + init_cycfg_pins(); + init_cycfg_platform(); + init_cycfg_connectivity(); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.h new file mode 100644 index 0000000000..68bb40bf09 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.h @@ -0,0 +1,47 @@ +/******************************************************************************* +* File Name: cycfg.h +* +* Description: +* Simple wrapper header containing all generated files. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_H) +#define CYCFG_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +#include "cycfg_clocks.h" +#include "cycfg_peripherals.h" +#include "cycfg_pins.h" +#include "cycfg_platform.h" +#include "cycfg_connectivity.h" + +void init_cycfg_all(void); + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.c new file mode 100644 index 0000000000..9a6a4e3cf9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.c @@ -0,0 +1,45 @@ +/******************************************************************************* +* File Name: cycfg_clocks.c +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_clocks.h" + + +void init_cycfg_clocks(void) +{ + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 35U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 0U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.h new file mode 100644 index 0000000000..ce944e4bd0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.h @@ -0,0 +1,51 @@ +/******************************************************************************* +* File Name: cycfg_clocks.h +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_CLOCKS_H) +#define CYCFG_CLOCKS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define peri_0_div_8_0_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_0_NUM 0U +#define peri_0_div_8_1_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_1_NUM 1U +#define peri_0_div_8_2_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_2_NUM 2U +#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_3_NUM 3U + +void init_cycfg_clocks(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_CLOCKS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_connectivity.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_connectivity.c new file mode 100644 index 0000000000..c389562da2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_connectivity.c @@ -0,0 +1,39 @@ +/******************************************************************************* +* File Name: cycfg_connectivity.c +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_connectivity.h" + +#include "cy_device_headers.h" + +void init_cycfg_connectivity(void) +{ + HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; + HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | + HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_connectivity.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_connectivity.h new file mode 100644 index 0000000000..ff31e17f1e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_connectivity.h @@ -0,0 +1,75 @@ +/******************************************************************************* +* File Name: cycfg_connectivity.h +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_CONNECTIVITY_H) +#define CYCFG_CONNECTIVITY_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +void init_cycfg_connectivity(void); + +#define ioss_0_port_11_pin_1_HSIOM P11_1_TCPWM0_LINE_COMPL1 +#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 +#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 +#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 +#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 +#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 +#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK +#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_2_pin_0_HSIOM P2_0_SDHC0_CARD_DAT_3TO00 +#define ioss_0_port_2_pin_1_HSIOM P2_1_SDHC0_CARD_DAT_3TO01 +#define ioss_0_port_2_pin_2_HSIOM P2_2_SDHC0_CARD_DAT_3TO02 +#define ioss_0_port_2_pin_3_HSIOM P2_3_SDHC0_CARD_DAT_3TO03 +#define ioss_0_port_2_pin_4_HSIOM P2_4_SDHC0_CARD_CMD +#define ioss_0_port_2_pin_5_HSIOM P2_5_SDHC0_CLK_CARD +#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX +#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX +#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS +#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS +#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX +#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL +#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA +#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO +#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS +#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK +#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_CONNECTIVITY_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_notices.h new file mode 100644 index 0000000000..90f1013f8a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_notices.h @@ -0,0 +1,30 @@ +/******************************************************************************* +* File Name: cycfg_notices.h +* +* Description: +* Contains warnings and errors that occurred while generating code for the +* design. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_NOTICES_H) +#define CYCFG_NOTICES_H + + +#endif /* CYCFG_NOTICES_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.c new file mode 100644 index 0000000000..72e28490f0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.c @@ -0,0 +1,187 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.c +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_peripherals.h" + +#define PWM_INPUT_DISABLED 0x7U + +cy_stc_csd_context_t cy_csd_0_context = +{ + .lockKey = CY_CSD_NONE_KEY, +}; +const cy_stc_scb_uart_config_t BT_UART_config = +{ + .uartMode = CY_SCB_UART_STANDARD, + .enableMutliProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + .oversample = 12, + .enableMsbFirst = false, + .dataWidth = 8UL, + .parity = CY_SCB_UART_PARITY_NONE, + .stopBits = CY_SCB_UART_STOP_BITS_1, + .enableInputFilter = false, + .breakWidth = 11UL, + .dropOnFrameError = false, + .dropOnParityError = false, + .receiverAddress = 0x0UL, + .receiverAddressMask = 0x0UL, + .acceptAddrInFifo = false, + .enableCts = true, + .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rtsRxFifoLevel = 63, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rxFifoTriggerLevel = 1UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, +}; +const cy_stc_scb_ezi2c_config_t CSD_COMM_config = +{ + .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS, + .slaveAddress1 = 8U, + .slaveAddress2 = 0U, + .subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS, + .enableWakeFromSleep = false, +}; +const cy_stc_scb_uart_config_t KITPROG_UART_config = +{ + .uartMode = CY_SCB_UART_STANDARD, + .enableMutliProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + .oversample = 12, + .enableMsbFirst = false, + .dataWidth = 9UL, + .parity = CY_SCB_UART_PARITY_NONE, + .stopBits = CY_SCB_UART_STOP_BITS_1, + .enableInputFilter = false, + .breakWidth = 11UL, + .dropOnFrameError = false, + .dropOnParityError = false, + .receiverAddress = 0x0UL, + .receiverAddressMask = 0x0UL, + .acceptAddrInFifo = false, + .enableCts = false, + .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rtsRxFifoLevel = 0UL, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rxFifoTriggerLevel = 63UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, +}; +cy_en_sd_host_card_capacity_t RADIO_cardCapacity = CY_SD_HOST_SDSC; +cy_en_sd_host_card_type_t RADIO_cardType = CY_SD_HOST_NOT_EMMC; +uint32_t RADIO_rca = 0u; +const cy_stc_sd_host_init_config_t RADIO_config = +{ + .emmc = false, + .dmaType = CY_SD_HOST_DMA_SDMA, + .enableLedControl = false, +}; +cy_stc_sd_host_sd_card_config_t RADIO_card_cfg = +{ + .lowVoltageSignaling = false, + .busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT, + .cardType = &RADIO_cardType, + .rca = &RADIO_rca, + .cardCapacity = &RADIO_cardCapacity, +}; +const cy_stc_smif_config_t QSPI_config = +{ + .mode = (uint32_t)CY_SMIF_NORMAL, + .deselectDelay = QSPI_DESELECT_DELAY, + .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK, + .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, +}; +const cy_stc_mcwdt_config_t MCWDT0_config = +{ + .c0Match = 32768U, + .c1Match = 32768U, + .c0Mode = CY_MCWDT_MODE_NONE, + .c1Mode = CY_MCWDT_MODE_NONE, + .c2ToggleBit = 16U, + .c2Mode = CY_MCWDT_MODE_NONE, + .c0ClearOnMatch = false, + .c1ClearOnMatch = false, + .c0c1Cascade = true, + .c1c2Cascade = false, +}; +const cy_stc_rtc_config_t RTC_config = +{ + .sec = 0U, + .min = 0U, + .hour = 12U, + .amPm = CY_RTC_AM, + .hrFormat = CY_RTC_24_HOURS, + .dayOfWeek = CY_RTC_SUNDAY, + .date = 1U, + .month = CY_RTC_JANUARY, + .year = 0U, +}; +const cy_stc_tcpwm_pwm_config_t PWM_config = +{ + .pwmMode = CY_TCPWM_PWM_MODE_PWM, + .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, + .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, + .deadTimeClocks = 0, + .runMode = CY_TCPWM_PWM_CONTINUOUS, + .period0 = 32000, + .period1 = 32768, + .enablePeriodSwap = false, + .compare0 = 16384, + .compare1 = 16384, + .enableCompareSwap = false, + .interruptSources = CY_TCPWM_INT_NONE, + .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE, + .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE, + .killMode = CY_TCPWM_PWM_STOP_ON_KILL, + .swapInputMode = PWM_INPUT_DISABLED & 0x3U, + .swapInput = CY_TCPWM_INPUT_0, + .reloadInputMode = PWM_INPUT_DISABLED & 0x3U, + .reloadInput = CY_TCPWM_INPUT_0, + .startInputMode = PWM_INPUT_DISABLED & 0x3U, + .startInput = CY_TCPWM_INPUT_0, + .killInputMode = PWM_INPUT_DISABLED & 0x3U, + .killInput = CY_TCPWM_INPUT_0, + .countInputMode = PWM_INPUT_DISABLED & 0x3U, + .countInput = CY_TCPWM_INPUT_1, +}; + + +void init_cycfg_peripherals(void) +{ + Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U); + + Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCKS1, CY_SYSCLK_DIV_8_BIT, 3U); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.h new file mode 100644 index 0000000000..9ab7fdc86c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.h @@ -0,0 +1,138 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.h +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PERIPHERALS_H) +#define CYCFG_PERIPHERALS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_csd.h" +#include "cy_scb_uart.h" +#include "cy_scb_ezi2c.h" +#include "cy_sd_host.h" +#include "cy_smif.h" +#include "cy_mcwdt.h" +#include "cy_rtc.h" +#include "cy_tcpwm_pwm.h" +#include "cycfg_connectivity.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CY_CAPSENSE_CORE 4u +#define CY_CAPSENSE_CPU_CLK 100000000u +#define CY_CAPSENSE_PERI_CLK 50000000u +#define CY_CAPSENSE_VDDA_MV 3300u +#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT +#define CY_CAPSENSE_PERI_DIV_INDEX 0u +#define Cmod_PORT GPIO_PRT7 +#define CintA_PORT GPIO_PRT7 +#define CintB_PORT GPIO_PRT7 +#define Button0_Rx0_PORT GPIO_PRT8 +#define Button0_Tx_PORT GPIO_PRT1 +#define Button1_Rx0_PORT GPIO_PRT8 +#define Button1_Tx_PORT GPIO_PRT1 +#define LinearSlider0_Sns0_PORT GPIO_PRT8 +#define LinearSlider0_Sns1_PORT GPIO_PRT8 +#define LinearSlider0_Sns2_PORT GPIO_PRT8 +#define LinearSlider0_Sns3_PORT GPIO_PRT8 +#define LinearSlider0_Sns4_PORT GPIO_PRT8 +#define Cmod_PIN 7u +#define CintA_PIN 1u +#define CintB_PIN 2u +#define Button0_Rx0_PIN 1u +#define Button0_Tx_PIN 0u +#define Button1_Rx0_PIN 2u +#define Button1_Tx_PIN 0u +#define LinearSlider0_Sns0_PIN 3u +#define LinearSlider0_Sns1_PIN 4u +#define LinearSlider0_Sns2_PIN 5u +#define LinearSlider0_Sns3_PIN 6u +#define LinearSlider0_Sns4_PIN 7u +#define Cmod_PORT_NUM 7u +#define CintA_PORT_NUM 7u +#define CintB_PORT_NUM 7u +#define CapSense_HW CSD0 +#define CapSense_IRQ csd_interrupt_IRQn +#define BT_UART_HW SCB2 +#define BT_UART_IRQ scb_2_interrupt_IRQn +#define CSD_COMM_HW SCB3 +#define CSD_COMM_IRQ scb_3_interrupt_IRQn +#define KITPROG_UART_HW SCB5 +#define KITPROG_UART_IRQ scb_5_interrupt_IRQn +#define RADIO_HW SDHC0 +#define RADIO_IRQ sdhc_0_interrupt_general_IRQn +#define QSPI_HW SMIF0 +#define QSPI_IRQ smif_interrupt_IRQn +#define QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL) +#define QSPI_RX_DATA_FIFO_UNDERFLOW (0UL) +#define QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL) +#define QSPI_TX_DATA_FIFO_OVERFLOW (0UL) +#define QSPI_RX_FIFO_TRIGEER_LEVEL (0UL) +#define QSPI_TX_FIFO_TRIGEER_LEVEL (0UL) +#define QSPI_DATALINES0_1 (1UL) +#define QSPI_DATALINES2_3 (1UL) +#define QSPI_DATALINES4_5 (0UL) +#define QSPI_DATALINES6_7 (0UL) +#define QSPI_SS0 (1UL) +#define QSPI_SS1 (0UL) +#define QSPI_SS2 (0UL) +#define QSPI_SS3 (0UL) +#define QSPI_DESELECT_DELAY 7 +#define MCWDT0_HW MCWDT_STRUCT0 +#define RTC_10_MONTH_OFFSET (28U) +#define RTC_MONTH_OFFSET (24U) +#define RTC_10_DAY_OFFSET (20U) +#define RTC_DAY_OFFSET (16U) +#define RTC_1000_YEAR_OFFSET (12U) +#define RTC_100_YEAR_OFFSET (8U) +#define RTC_10_YEAR_OFFSET (4U) +#define RTC_YEAR_OFFSET (0U) +#define PWM_HW TCPWM0 +#define PWM_NUM 1UL +#define PWM_MASK (1UL << 1) + +extern cy_stc_csd_context_t cy_csd_0_context; +extern const cy_stc_scb_uart_config_t BT_UART_config; +extern const cy_stc_scb_ezi2c_config_t CSD_COMM_config; +extern const cy_stc_scb_uart_config_t KITPROG_UART_config; +extern cy_en_sd_host_card_capacity_t RADIO_cardCapacity; +extern cy_en_sd_host_card_type_t RADIO_cardType; +extern uint32_t RADIO_rca; +extern const cy_stc_sd_host_init_config_t RADIO_config; +extern cy_stc_sd_host_sd_card_config_t RADIO_card_cfg; +extern const cy_stc_smif_config_t QSPI_config; +extern const cy_stc_mcwdt_config_t MCWDT0_config; +extern const cy_stc_rtc_config_t RTC_config; +extern const cy_stc_tcpwm_pwm_config_t PWM_config; + +void init_cycfg_peripherals(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PERIPHERALS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.c new file mode 100644 index 0000000000..7f16b5f459 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.c @@ -0,0 +1,811 @@ +/******************************************************************************* +* File Name: cycfg_pins.c +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_pins.h" + +const cy_stc_gpio_pin_config_t WCO_IN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = WCO_IN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t WCO_OUT_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = WCO_OUT_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED_RED_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED_RED_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SW2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = SW2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED_BLUE_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED_BLUE_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_SS0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = QSPI_SS0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = QSPI_SPI_CLOCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED9_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED9_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED_GREEN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED_GREEN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED8_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED8_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_DAT0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_DAT0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_DAT1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_DAT1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_DAT2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_DAT2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_DAT3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_DAT3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_CMD_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_CMD_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_CLK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_CLK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_UART_RX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = BT_UART_RX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_UART_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = BT_UART_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_UART_RTS_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = BT_UART_RTS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_UART_CTS_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = BT_UART_CTS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_POWER_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF, + .hsiom = BT_POWER_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = BT_HOST_WAKE_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = BT_DEVICE_WAKE_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t UART_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = UART_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t EZI2C_SCL_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = EZI2C_SCL_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t EZI2C_SDA_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = EZI2C_SDA_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SWO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = SWO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SWDIO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = SWDIO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SWDCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLDOWN, + .hsiom = SWDCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CINA_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CINA_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CINB_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CINB_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CMOD_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CMOD_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_BTN0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_BTN0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_BTN1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_BTN1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD4_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD4_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; + + +void init_cycfg_pins(void) +{ + Cy_GPIO_Pin_Init(WCO_IN_PORT, WCO_IN_PIN, &WCO_IN_config); + + Cy_GPIO_Pin_Init(WCO_OUT_PORT, WCO_OUT_PIN, &WCO_OUT_config); + + Cy_GPIO_Pin_Init(LED_RED_PORT, LED_RED_PIN, &LED_RED_config); + + Cy_GPIO_Pin_Init(SW2_PORT, SW2_PIN, &SW2_config); + + Cy_GPIO_Pin_Init(LED_BLUE_PORT, LED_BLUE_PIN, &LED_BLUE_config); + + Cy_GPIO_Pin_Init(QSPI_SS0_PORT, QSPI_SS0_PIN, &QSPI_SS0_config); + + Cy_GPIO_Pin_Init(QSPI_DATA3_PORT, QSPI_DATA3_PIN, &QSPI_DATA3_config); + + Cy_GPIO_Pin_Init(QSPI_DATA2_PORT, QSPI_DATA2_PIN, &QSPI_DATA2_config); + + Cy_GPIO_Pin_Init(QSPI_DATA1_PORT, QSPI_DATA1_PIN, &QSPI_DATA1_config); + + Cy_GPIO_Pin_Init(QSPI_DATA0_PORT, QSPI_DATA0_PIN, &QSPI_DATA0_config); + + Cy_GPIO_Pin_Init(QSPI_SPI_CLOCK_PORT, QSPI_SPI_CLOCK_PIN, &QSPI_SPI_CLOCK_config); + + Cy_GPIO_Pin_Init(LED9_PORT, LED9_PIN, &LED9_config); + + + Cy_GPIO_Pin_Init(LED_GREEN_PORT, LED_GREEN_PIN, &LED_GREEN_config); + + Cy_GPIO_Pin_Init(LED8_PORT, LED8_PIN, &LED8_config); + + Cy_GPIO_Pin_Init(SDHC0_DAT0_PORT, SDHC0_DAT0_PIN, &SDHC0_DAT0_config); + + Cy_GPIO_Pin_Init(SDHC0_DAT1_PORT, SDHC0_DAT1_PIN, &SDHC0_DAT1_config); + + Cy_GPIO_Pin_Init(SDHC0_DAT2_PORT, SDHC0_DAT2_PIN, &SDHC0_DAT2_config); + + Cy_GPIO_Pin_Init(SDHC0_DAT3_PORT, SDHC0_DAT3_PIN, &SDHC0_DAT3_config); + + Cy_GPIO_Pin_Init(SDHC0_CMD_PORT, SDHC0_CMD_PIN, &SDHC0_CMD_config); + + Cy_GPIO_Pin_Init(SDHC0_CLK_PORT, SDHC0_CLK_PIN, &SDHC0_CLK_config); + + Cy_GPIO_Pin_Init(BT_UART_RX_PORT, BT_UART_RX_PIN, &BT_UART_RX_config); + + Cy_GPIO_Pin_Init(BT_UART_TX_PORT, BT_UART_TX_PIN, &BT_UART_TX_config); + + Cy_GPIO_Pin_Init(BT_UART_RTS_PORT, BT_UART_RTS_PIN, &BT_UART_RTS_config); + + Cy_GPIO_Pin_Init(BT_UART_CTS_PORT, BT_UART_CTS_PIN, &BT_UART_CTS_config); + + Cy_GPIO_Pin_Init(BT_POWER_PORT, BT_POWER_PIN, &BT_POWER_config); + + Cy_GPIO_Pin_Init(BT_HOST_WAKE_PORT, BT_HOST_WAKE_PIN, &BT_HOST_WAKE_config); + + Cy_GPIO_Pin_Init(BT_DEVICE_WAKE_PORT, BT_DEVICE_WAKE_PIN, &BT_DEVICE_WAKE_config); + + Cy_GPIO_Pin_Init(UART_TX_PORT, UART_TX_PIN, &UART_TX_config); + + Cy_GPIO_Pin_Init(EZI2C_SCL_PORT, EZI2C_SCL_PIN, &EZI2C_SCL_config); + + Cy_GPIO_Pin_Init(EZI2C_SDA_PORT, EZI2C_SDA_PIN, &EZI2C_SDA_config); + + Cy_GPIO_Pin_Init(SWO_PORT, SWO_PIN, &SWO_config); + + Cy_GPIO_Pin_Init(SWDIO_PORT, SWDIO_PIN, &SWDIO_config); + + Cy_GPIO_Pin_Init(SWDCK_PORT, SWDCK_PIN, &SWDCK_config); + + + + + + + + + + +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.h new file mode 100644 index 0000000000..b8b6546bfb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.h @@ -0,0 +1,529 @@ +/******************************************************************************* +* File Name: cycfg_pins.h +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PINS_H) +#define CYCFG_PINS_H + +#include "cycfg_notices.h" +#include "cy_gpio.h" +#include "cycfg_connectivity.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define WCO_IN_PORT GPIO_PRT0 +#define WCO_IN_PIN 0U +#define WCO_IN_NUM 0U +#define WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG +#define WCO_IN_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_0_HSIOM + #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM +#define WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn +#define WCO_OUT_PORT GPIO_PRT0 +#define WCO_OUT_PIN 1U +#define WCO_OUT_NUM 1U +#define WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG +#define WCO_OUT_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_1_HSIOM + #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM +#define WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn +#define LED_RED_PORT GPIO_PRT0 +#define LED_RED_PIN 3U +#define LED_RED_NUM 3U +#define LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED_RED_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_3_HSIOM + #define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM +#define LED_RED_IRQ ioss_interrupts_gpio_0_IRQn +#define SW2_PORT GPIO_PRT0 +#define SW2_PIN 4U +#define SW2_NUM 4U +#define SW2_DRIVEMODE CY_GPIO_DM_PULLUP +#define SW2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_4_HSIOM + #define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define SW2_HSIOM ioss_0_port_0_pin_4_HSIOM +#define SW2_IRQ ioss_interrupts_gpio_0_IRQn +#define LED_BLUE_PORT GPIO_PRT11 +#define LED_BLUE_PIN 1U +#define LED_BLUE_NUM 1U +#define LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED_BLUE_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_1_HSIOM + #define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM +#define LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_SS0_PORT GPIO_PRT11 +#define QSPI_SS0_PIN 2U +#define QSPI_SS0_NUM 2U +#define QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define QSPI_SS0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_2_HSIOM + #define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM +#define QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA3_PORT GPIO_PRT11 +#define QSPI_DATA3_PIN 3U +#define QSPI_DATA3_NUM 3U +#define QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_3_HSIOM + #define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM +#define QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA2_PORT GPIO_PRT11 +#define QSPI_DATA2_PIN 4U +#define QSPI_DATA2_NUM 4U +#define QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_4_HSIOM + #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM +#define QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA1_PORT GPIO_PRT11 +#define QSPI_DATA1_PIN 5U +#define QSPI_DATA1_NUM 5U +#define QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_5_HSIOM + #define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM +#define QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA0_PORT GPIO_PRT11 +#define QSPI_DATA0_PIN 6U +#define QSPI_DATA0_NUM 6U +#define QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_6_HSIOM + #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM +#define QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_SPI_CLOCK_PORT GPIO_PRT11 +#define QSPI_SPI_CLOCK_PIN 7U +#define QSPI_SPI_CLOCK_NUM 7U +#define QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define QSPI_SPI_CLOCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_7_HSIOM + #define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM +#define QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn +#define LED9_PORT GPIO_PRT13 +#define LED9_PIN 7U +#define LED9_NUM 7U +#define LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED9_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_13_pin_7_HSIOM + #define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define LED9_HSIOM ioss_0_port_13_pin_7_HSIOM +#define LED9_IRQ ioss_interrupts_gpio_13_IRQn +#define CSD_TX_PORT GPIO_PRT1 +#define CSD_TX_PIN 0U +#define CSD_TX_NUM 0U +#define CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_0_HSIOM + #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM +#define CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn +#define LED_GREEN_PORT GPIO_PRT1 +#define LED_GREEN_PIN 1U +#define LED_GREEN_NUM 1U +#define LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED_GREEN_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_1_HSIOM + #define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM +#define LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn +#define LED8_PORT GPIO_PRT1 +#define LED8_PIN 5U +#define LED8_NUM 5U +#define LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED8_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_5_HSIOM + #define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define LED8_HSIOM ioss_0_port_1_pin_5_HSIOM +#define LED8_IRQ ioss_interrupts_gpio_1_IRQn +#define SDHC0_DAT0_PORT GPIO_PRT2 +#define SDHC0_DAT0_PIN 0U +#define SDHC0_DAT0_NUM 0U +#define SDHC0_DAT0_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_DAT0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_0_HSIOM + #define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_DAT0_HSIOM ioss_0_port_2_pin_0_HSIOM +#define SDHC0_DAT0_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_DAT1_PORT GPIO_PRT2 +#define SDHC0_DAT1_PIN 1U +#define SDHC0_DAT1_NUM 1U +#define SDHC0_DAT1_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_DAT1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_1_HSIOM + #define ioss_0_port_2_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_DAT1_HSIOM ioss_0_port_2_pin_1_HSIOM +#define SDHC0_DAT1_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_DAT2_PORT GPIO_PRT2 +#define SDHC0_DAT2_PIN 2U +#define SDHC0_DAT2_NUM 2U +#define SDHC0_DAT2_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_DAT2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_2_HSIOM + #define ioss_0_port_2_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_DAT2_HSIOM ioss_0_port_2_pin_2_HSIOM +#define SDHC0_DAT2_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_DAT3_PORT GPIO_PRT2 +#define SDHC0_DAT3_PIN 3U +#define SDHC0_DAT3_NUM 3U +#define SDHC0_DAT3_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_DAT3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_3_HSIOM + #define ioss_0_port_2_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_DAT3_HSIOM ioss_0_port_2_pin_3_HSIOM +#define SDHC0_DAT3_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_CMD_PORT GPIO_PRT2 +#define SDHC0_CMD_PIN 4U +#define SDHC0_CMD_NUM 4U +#define SDHC0_CMD_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_CMD_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_4_HSIOM + #define ioss_0_port_2_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM +#define SDHC0_CMD_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_CLK_PORT GPIO_PRT2 +#define SDHC0_CLK_PIN 5U +#define SDHC0_CLK_NUM 5U +#define SDHC0_CLK_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_CLK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_5_HSIOM + #define ioss_0_port_2_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM +#define SDHC0_CLK_IRQ ioss_interrupts_gpio_2_IRQn +#define BT_UART_RX_PORT GPIO_PRT3 +#define BT_UART_RX_PIN 0U +#define BT_UART_RX_NUM 0U +#define BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ +#define BT_UART_RX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_0_HSIOM + #define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM +#define BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_UART_TX_PORT GPIO_PRT3 +#define BT_UART_TX_PIN 1U +#define BT_UART_TX_NUM 1U +#define BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define BT_UART_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_1_HSIOM + #define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM +#define BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_UART_RTS_PORT GPIO_PRT3 +#define BT_UART_RTS_PIN 2U +#define BT_UART_RTS_NUM 2U +#define BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define BT_UART_RTS_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_2_HSIOM + #define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM +#define BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_UART_CTS_PORT GPIO_PRT3 +#define BT_UART_CTS_PIN 3U +#define BT_UART_CTS_NUM 3U +#define BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ +#define BT_UART_CTS_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_3_HSIOM + #define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM +#define BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_POWER_PORT GPIO_PRT3 +#define BT_POWER_PIN 4U +#define BT_POWER_NUM 4U +#define BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF +#define BT_POWER_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_4_HSIOM + #define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM +#define BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_HOST_WAKE_PORT GPIO_PRT3 +#define BT_HOST_WAKE_PIN 5U +#define BT_HOST_WAKE_NUM 5U +#define BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG +#define BT_HOST_WAKE_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_3_pin_5_HSIOM + #define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM +#define BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_DEVICE_WAKE_PORT GPIO_PRT4 +#define BT_DEVICE_WAKE_PIN 0U +#define BT_DEVICE_WAKE_NUM 0U +#define BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define BT_DEVICE_WAKE_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_4_pin_0_HSIOM + #define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM +#define BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn +#define UART_TX_PORT GPIO_PRT5 +#define UART_TX_PIN 1U +#define UART_TX_NUM 1U +#define UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define UART_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_5_pin_1_HSIOM + #define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM +#define UART_TX_IRQ ioss_interrupts_gpio_5_IRQn +#define EZI2C_SCL_PORT GPIO_PRT6 +#define EZI2C_SCL_PIN 0U +#define EZI2C_SCL_NUM 0U +#define EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define EZI2C_SCL_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_0_HSIOM + #define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM +#define EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn +#define EZI2C_SDA_PORT GPIO_PRT6 +#define EZI2C_SDA_PIN 1U +#define EZI2C_SDA_NUM 1U +#define EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define EZI2C_SDA_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_1_HSIOM + #define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM +#define EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn +#define SWO_PORT GPIO_PRT6 +#define SWO_PIN 4U +#define SWO_NUM 4U +#define SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define SWO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_4_HSIOM + #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define SWO_HSIOM ioss_0_port_6_pin_4_HSIOM +#define SWO_IRQ ioss_interrupts_gpio_6_IRQn +#define SWDIO_PORT GPIO_PRT6 +#define SWDIO_PIN 6U +#define SWDIO_NUM 6U +#define SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP +#define SWDIO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_6_HSIOM + #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM +#define SWDIO_IRQ ioss_interrupts_gpio_6_IRQn +#define SWDCK_PORT GPIO_PRT6 +#define SWDCK_PIN 7U +#define SWDCK_NUM 7U +#define SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN +#define SWDCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_7_HSIOM + #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM +#define SWDCK_IRQ ioss_interrupts_gpio_6_IRQn +#define CINA_PORT GPIO_PRT7 +#define CINA_PIN 1U +#define CINA_NUM 1U +#define CINA_DRIVEMODE CY_GPIO_DM_ANALOG +#define CINA_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_1_HSIOM + #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CINA_HSIOM ioss_0_port_7_pin_1_HSIOM +#define CINA_IRQ ioss_interrupts_gpio_7_IRQn +#define CINB_PORT GPIO_PRT7 +#define CINB_PIN 2U +#define CINB_NUM 2U +#define CINB_DRIVEMODE CY_GPIO_DM_ANALOG +#define CINB_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_2_HSIOM + #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CINB_HSIOM ioss_0_port_7_pin_2_HSIOM +#define CINB_IRQ ioss_interrupts_gpio_7_IRQn +#define CMOD_PORT GPIO_PRT7 +#define CMOD_PIN 7U +#define CMOD_NUM 7U +#define CMOD_DRIVEMODE CY_GPIO_DM_ANALOG +#define CMOD_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_7_HSIOM + #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM +#define CMOD_IRQ ioss_interrupts_gpio_7_IRQn +#define CSD_BTN0_PORT GPIO_PRT8 +#define CSD_BTN0_PIN 1U +#define CSD_BTN0_NUM 1U +#define CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_BTN0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_1_HSIOM + #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM +#define CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_BTN1_PORT GPIO_PRT8 +#define CSD_BTN1_PIN 2U +#define CSD_BTN1_NUM 2U +#define CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_BTN1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_2_HSIOM + #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM +#define CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD0_PORT GPIO_PRT8 +#define CSD_SLD0_PIN 3U +#define CSD_SLD0_NUM 3U +#define CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_3_HSIOM + #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM +#define CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD1_PORT GPIO_PRT8 +#define CSD_SLD1_PIN 4U +#define CSD_SLD1_NUM 4U +#define CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_4_HSIOM + #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM +#define CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD2_PORT GPIO_PRT8 +#define CSD_SLD2_PIN 5U +#define CSD_SLD2_NUM 5U +#define CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_5_HSIOM + #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM +#define CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD3_PORT GPIO_PRT8 +#define CSD_SLD3_PIN 6U +#define CSD_SLD3_NUM 6U +#define CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_6_HSIOM + #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM +#define CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD4_PORT GPIO_PRT8 +#define CSD_SLD4_PIN 7U +#define CSD_SLD4_NUM 7U +#define CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD4_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_7_HSIOM + #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM +#define CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn + +extern const cy_stc_gpio_pin_config_t WCO_IN_config; +extern const cy_stc_gpio_pin_config_t WCO_OUT_config; +extern const cy_stc_gpio_pin_config_t LED_RED_config; +extern const cy_stc_gpio_pin_config_t SW2_config; +extern const cy_stc_gpio_pin_config_t LED_BLUE_config; +extern const cy_stc_gpio_pin_config_t QSPI_SS0_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA3_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA2_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA1_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA0_config; +extern const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config; +extern const cy_stc_gpio_pin_config_t LED9_config; +extern const cy_stc_gpio_pin_config_t CSD_TX_config; +extern const cy_stc_gpio_pin_config_t LED_GREEN_config; +extern const cy_stc_gpio_pin_config_t LED8_config; +extern const cy_stc_gpio_pin_config_t SDHC0_DAT0_config; +extern const cy_stc_gpio_pin_config_t SDHC0_DAT1_config; +extern const cy_stc_gpio_pin_config_t SDHC0_DAT2_config; +extern const cy_stc_gpio_pin_config_t SDHC0_DAT3_config; +extern const cy_stc_gpio_pin_config_t SDHC0_CMD_config; +extern const cy_stc_gpio_pin_config_t SDHC0_CLK_config; +extern const cy_stc_gpio_pin_config_t BT_UART_RX_config; +extern const cy_stc_gpio_pin_config_t BT_UART_TX_config; +extern const cy_stc_gpio_pin_config_t BT_UART_RTS_config; +extern const cy_stc_gpio_pin_config_t BT_UART_CTS_config; +extern const cy_stc_gpio_pin_config_t BT_POWER_config; +extern const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config; +extern const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config; +extern const cy_stc_gpio_pin_config_t UART_TX_config; +extern const cy_stc_gpio_pin_config_t EZI2C_SCL_config; +extern const cy_stc_gpio_pin_config_t EZI2C_SDA_config; +extern const cy_stc_gpio_pin_config_t SWO_config; +extern const cy_stc_gpio_pin_config_t SWDIO_config; +extern const cy_stc_gpio_pin_config_t SWDCK_config; +extern const cy_stc_gpio_pin_config_t CINA_config; +extern const cy_stc_gpio_pin_config_t CINB_config; +extern const cy_stc_gpio_pin_config_t CMOD_config; +extern const cy_stc_gpio_pin_config_t CSD_BTN0_config; +extern const cy_stc_gpio_pin_config_t CSD_BTN1_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD0_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD1_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD2_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD3_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD4_config; + +void init_cycfg_pins(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PINS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.c new file mode 100644 index 0000000000..9c14fabc8c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.c @@ -0,0 +1,516 @@ +/******************************************************************************* +* File Name: cycfg_platform.c +* +* Description: +* Platform configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_platform.h" + +#define CY_CFG_SYSCLK_ECO_ERROR 1 +#define CY_CFG_SYSCLK_ALTHF_ERROR 2 +#define CY_CFG_SYSCLK_PLL_ERROR 3 +#define CY_CFG_SYSCLK_FLL_ERROR 4 +#define CY_CFG_SYSCLK_WCO_ERROR 5 +#define CY_CFG_SYSCLK_PLL1_AVAILABLE 1 +#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 +#define CY_CFG_SYSCLK_FLL_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL +#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_ILO_ENABLED 1 +#define CY_CFG_SYSCLK_IMO_ENABLED 1 +#define CY_CFG_SYSCLK_CLKLF_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 +#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 +#define CY_CFG_SYSCLK_WCO_ENABLED 1 +#define CY_CFG_PWR_ENABLED 1 +#define CY_CFG_PWR_USING_LDO 1 +#define CY_CFG_PWR_USING_PMIC 0 +#define CY_CFG_PWR_VBAC_SUPPLY CY_CFG_PWR_VBAC_SUPPLY_VDD +#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_1_1V +#define CY_CFG_PWR_USING_ULP 0 + +static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = +{ + .fllMult = 500U, + .refDiv = 20U, + .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, + .enableOutputDiv = true, + .lockTolerance = 10U, + .igain = 9U, + .pgain = 5U, + .settlingCount = 8U, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, + .cco_Freq = 355U, +}; + +__WEAK void cycfg_ClockStartupError(uint32_t error) +{ + (void)error; /* Suppress the compiler warning */ + while(1); +} +__STATIC_INLINE void Cy_SysClk_ClkBakInit() +{ + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF); +} +__STATIC_INLINE void Cy_SysClk_ClkFastInit() +{ + Cy_SysClk_ClkFastSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_FllInit() +{ + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } +} +__STATIC_INLINE void Cy_SysClk_ClkHf0Init() +{ + Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); +} +__STATIC_INLINE void Cy_SysClk_ClkHf2Init() +{ + Cy_SysClk_ClkHfSetSource(2U, CY_CFG_SYSCLK_CLKHF2_CLKPATH); + Cy_SysClk_ClkHfSetDivider(2U, CY_SYSCLK_CLKHF_DIVIDE_BY_2); + Cy_SysClk_ClkHfEnable(2U); +} +__STATIC_INLINE void Cy_SysClk_ClkHf4Init() +{ + Cy_SysClk_ClkHfSetSource(4U, CY_CFG_SYSCLK_CLKHF4_CLKPATH); + Cy_SysClk_ClkHfSetDivider(4U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfEnable(4U); +} +__STATIC_INLINE void Cy_SysClk_IloInit() +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_IloEnable(); + Cy_SysClk_IloHibernateOn(true); +} +__STATIC_INLINE void Cy_SysClk_ClkLfInit() +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO); +} +__STATIC_INLINE void Cy_SysClk_ClkPath0Init() +{ + Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath1Init() +{ + Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath2Init() +{ + Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath3Init() +{ + Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath4Init() +{ + Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPeriInit() +{ + Cy_SysClk_ClkPeriSetDivider(1U); +} +__STATIC_INLINE void Cy_SysClk_ClkSlowInit() +{ + Cy_SysClk_ClkSlowSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_WcoInit() +{ + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); + } +} + + +void init_cycfg_platform(void) +{ + /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ + Cy_SysLib_SetWaitStates(false, 150UL); + #if (CY_CFG_PWR_VBAC_SUPPLY == CY_CFG_PWR_VBAC_SUPPLY_VDD) + if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) + { + Cy_SysLib_ResetBackupDomain(); + Cy_SysClk_IloDisable(); + Cy_SysClk_IloInit(); + } + #endif + #ifdef CY_CFG_PWR_ENABLED + /* Configure power mode */ + #if CY_CFG_PWR_USING_LDO + Cy_SysPm_LdoSetVoltage(CY_CFG_PWR_LDO_VOLTAGE); + #else + Cy_SysPm_BuckEnable(CY_CFG_PWR_BUCK_VOLTAGE); + #endif + /* Configure PMIC */ + Cy_SysPm_UnlockPmic(); + #if CY_CFG_PWR_USING_PMIC + Cy_SysPm_PmicEnableOutput(); + #else + Cy_SysPm_PmicDisableOutput(); + #endif + #endif + + /* Reset the core clock path to default and disable all the FLLs/PLLs */ + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkFastSetDivider(0U); + Cy_SysClk_ClkPeriSetDivider(1U); + Cy_SysClk_ClkSlowSetDivider(0U); + Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH1); + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); + + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && + (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) + { + Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); + } + + Cy_SysClk_FllDisable(); + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); + #ifdef CY_IP_MXBLESS + (void)Cy_BLE_EcoReset(); + #endif + + #ifdef CY_CFG_SYSCLK_PLL1_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2); + #endif + + #ifdef CY_CFG_SYSCLK_PLL2_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH3); + #endif + + #ifdef CY_CFG_SYSCLK_PLL3_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH4); + #endif + + #ifdef CY_CFG_SYSCLK_PLL4_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH5); + #endif + + #ifdef CY_CFG_SYSCLK_PLL5_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH6); + #endif + + #ifdef CY_CFG_SYSCLK_PLL6_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH7); + #endif + + #ifdef CY_CFG_SYSCLK_PLL7_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH8); + #endif + + #ifdef CY_CFG_SYSCLK_PLL8_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH9); + #endif + + #ifdef CY_CFG_SYSCLK_PLL9_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH10); + #endif + + #ifdef CY_CFG_SYSCLK_PLL10_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH11); + #endif + + #ifdef CY_CFG_SYSCLK_PLL11_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH12); + #endif + + #ifdef CY_CFG_SYSCLK_PLL12_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH13); + #endif + + #ifdef CY_CFG_SYSCLK_PLL13_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH14); + #endif + + #ifdef CY_CFG_SYSCLK_PLL14_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH15); + #endif + + /* Enable all source clocks */ + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + Cy_SysClk_PiloInit(); + #endif + + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + Cy_SysClk_WcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + Cy_SysClk_ClkLfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED + Cy_SysClk_AltHfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + Cy_SysClk_EcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + Cy_SysClk_ExtClkInit(); + #endif + + /* Configure CPU clock dividers */ + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED + Cy_SysClk_ClkFastInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + Cy_SysClk_ClkPeriInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + Cy_SysClk_ClkSlowInit(); + #endif + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ + Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); + #else + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure Path Clocks */ + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + Cy_SysClk_ClkPath0Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + Cy_SysClk_ClkPath2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + Cy_SysClk_ClkPath3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + Cy_SysClk_ClkPath4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + Cy_SysClk_ClkPath5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED + Cy_SysClk_ClkPath6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED + Cy_SysClk_ClkPath7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED + Cy_SysClk_ClkPath8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED + Cy_SysClk_ClkPath9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED + Cy_SysClk_ClkPath10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED + Cy_SysClk_ClkPath11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED + Cy_SysClk_ClkPath12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED + Cy_SysClk_ClkPath13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED + Cy_SysClk_ClkPath14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED + Cy_SysClk_ClkPath15Init(); + #endif + + /* Configure and enable FLL */ + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + Cy_SysClk_FllInit(); + #endif + + Cy_SysClk_ClkHf0Init(); + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + /* Apply the ClkPath1 user setting */ + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure and enable PLLs */ + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + Cy_SysClk_Pll0Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + Cy_SysClk_Pll1Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL2_ENABLED + Cy_SysClk_Pll2Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL3_ENABLED + Cy_SysClk_Pll3Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL4_ENABLED + Cy_SysClk_Pll4Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL5_ENABLED + Cy_SysClk_Pll5Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL6_ENABLED + Cy_SysClk_Pll6Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL7_ENABLED + Cy_SysClk_Pll7Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL8_ENABLED + Cy_SysClk_Pll8Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL9_ENABLED + Cy_SysClk_Pll9Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL10_ENABLED + Cy_SysClk_Pll10Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL11_ENABLED + Cy_SysClk_Pll11Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL12_ENABLED + Cy_SysClk_Pll12Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL13_ENABLED + Cy_SysClk_Pll13Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL14_ENABLED + Cy_SysClk_Pll14Init(); + #endif + + /* Configure HF clocks */ + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + Cy_SysClk_ClkHf1Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + Cy_SysClk_ClkHf2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + Cy_SysClk_ClkHf3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + Cy_SysClk_ClkHf4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + Cy_SysClk_ClkHf5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED + Cy_SysClk_ClkHf6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED + Cy_SysClk_ClkHf7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED + Cy_SysClk_ClkHf8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED + Cy_SysClk_ClkHf9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED + Cy_SysClk_ClkHf10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED + Cy_SysClk_ClkHf11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED + Cy_SysClk_ClkHf12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED + Cy_SysClk_ClkHf13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED + Cy_SysClk_ClkHf14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED + Cy_SysClk_ClkHf15Init(); + #endif + + /* Configure miscellaneous clocks */ + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED + Cy_SysClk_ClkTimerInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + Cy_SysClk_ClkAltSysTickInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + Cy_SysClk_ClkPumpInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + Cy_SysClk_ClkBakInit(); + #endif + + /* Configure default enabled clocks */ + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + Cy_SysClk_IloInit(); + #else + Cy_SysClk_IloDisable(); + #endif + + #ifndef CY_CFG_SYSCLK_IMO_ENABLED + #error the IMO must be enabled for proper chip operation + #endif + + /* Set accurate flash wait states */ + #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) + Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); + #endif + + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ + SystemCoreClockUpdate(); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.h new file mode 100644 index 0000000000..9778631b74 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* File Name: cycfg_platform.h +* +* Description: +* Platform configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PLATFORM_H) +#define CYCFG_PLATFORM_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_gpio.h" +#include "cy_syspm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000 +#define CY_CFG_PWR_VDDA_MV 3300 +#define CY_CFG_PWR_VDDD_MV 3300 +#define CY_CFG_PWR_VBACKUP_MV 3300 +#define CY_CFG_PWR_VDD_NS_MV 3300 +#define CY_CFG_PWR_VDDIO0_MV 3300 +#define CY_CFG_PWR_VDDIO1_MV 3300 + +void init_cycfg_platform(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PLATFORM_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.c new file mode 100644 index 0000000000..cf7ac0229a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.c @@ -0,0 +1,34 @@ +/******************************************************************************* +* File Name: cycfg.c +* +* Description: +* Wrapper function to initialize all generated code. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg.h" + +void init_cycfg_all(void) +{ + init_cycfg_clocks(); + init_cycfg_peripherals(); + init_cycfg_pins(); + init_cycfg_platform(); + init_cycfg_connectivity(); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.h new file mode 100644 index 0000000000..faa061e3c2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.h @@ -0,0 +1,48 @@ +/******************************************************************************* +* File Name: cycfg.h +* +* Description: +* Simple wrapper header containing all generated files. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_H) +#define CYCFG_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +#include "cycfg_clocks.h" +#include "cycfg_dmas.h" +#include "cycfg_peripherals.h" +#include "cycfg_pins.h" +#include "cycfg_platform.h" +#include "cycfg_connectivity.h" + +void init_cycfg_all(void); + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.c new file mode 100644 index 0000000000..5249f7d3a0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.c @@ -0,0 +1,53 @@ +/******************************************************************************* +* File Name: cycfg_clocks.c +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_clocks.h" + + +void init_cycfg_clocks(void) +{ + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 108U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 1U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 255U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.h new file mode 100644 index 0000000000..0da97983ce --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.h @@ -0,0 +1,55 @@ +/******************************************************************************* +* File Name: cycfg_clocks.h +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_CLOCKS_H) +#define CYCFG_CLOCKS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define peri_0_div_16_0_HW CY_SYSCLK_DIV_16_BIT +#define peri_0_div_16_0_NUM 0U +#define peri_0_div_8_0_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_0_NUM 0U +#define peri_0_div_8_1_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_1_NUM 1U +#define peri_0_div_8_2_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_2_NUM 2U +#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_3_NUM 3U +#define peri_0_div_8_4_HW CY_SYSCLK_DIV_8_BIT +#define peri_0_div_8_4_NUM 4U + +void init_cycfg_clocks(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_CLOCKS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_connectivity.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_connectivity.c new file mode 100644 index 0000000000..daf39a82a4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_connectivity.c @@ -0,0 +1,51 @@ +/******************************************************************************* +* File Name: cycfg_connectivity.c +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_connectivity.h" + +#include "cy_trigmux.h" + +#include "stdbool.h" + +#include "cy_device_headers.h" + +void init_cycfg_connectivity(void) +{ + Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT0, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT5, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT49, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT48, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT43, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT45, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT2, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT6, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL); + HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; + HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_connectivity.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_connectivity.h new file mode 100644 index 0000000000..cc92c76813 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_connectivity.h @@ -0,0 +1,93 @@ +/******************************************************************************* +* File Name: cycfg_connectivity.h +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_CONNECTIVITY_H) +#define CYCFG_CONNECTIVITY_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +void init_cycfg_connectivity(void); + +#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 +#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 +#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 +#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 +#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 +#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK +#define ioss_0_port_13_pin_0_HSIOM P13_0_SCB6_UART_RX +#define ioss_0_port_13_pin_1_HSIOM P13_1_SCB6_UART_TX +#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_2_pin_0_HSIOM P2_0_DSI_DSI +#define ioss_0_port_2_pin_1_HSIOM P2_1_DSI_DSI +#define ioss_0_port_2_pin_2_HSIOM P2_2_DSI_DSI +#define ioss_0_port_2_pin_3_HSIOM P2_3_DSI_DSI +#define ioss_0_port_2_pin_4_HSIOM P2_4_DSI_DSI +#define ioss_0_port_2_pin_5_HSIOM P2_5_DSI_GPIO +#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX +#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX +#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS +#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS +#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL +#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA +#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO +#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS +#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK +#define ioss_0_port_7_pin_0_HSIOM P7_0_CPUSS_TRACE_CLOCK +#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_9_pin_0_HSIOM P9_0_CPUSS_TRACE_DATA3 +#define ioss_0_port_9_pin_1_HSIOM P9_1_CPUSS_TRACE_DATA2 +#define ioss_0_port_9_pin_2_HSIOM P9_2_CPUSS_TRACE_DATA1 +#define ioss_0_port_9_pin_3_HSIOM P9_3_CPUSS_TRACE_DATA0 + +#define cpuss_0_dw0_0_chan_0_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN0 +#define cpuss_0_dw0_0_chan_1_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN1 +#define cpuss_0_dw1_0_chan_1_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN1 +#define cpuss_0_dw1_0_chan_3_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN3 +#define udb_0_out_p_116_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB0 +#define udb_0_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT6 +#define udb_0_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT5 +#define udb_0_out_p_117_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB1 +#define udb_0_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT0 +#define udb_0_out_p_119_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB3 +#define udb_0_out_p_123_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB7 +#define udb_0_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT2 + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_CONNECTIVITY_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_dmas.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_dmas.c new file mode 100644 index 0000000000..a8e9de3e06 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_dmas.c @@ -0,0 +1,179 @@ +/******************************************************************************* +* File Name: cycfg_dmas.c +* +* Description: +* DMA configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_dmas.h" + +const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config = +{ + .retrigger = CY_DMA_RETRIG_IM, + .interruptType = CY_DMA_1ELEMENT, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_1ELEMENT, + .dataSize = CY_DMA_BYTE, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_1D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 0, + .dstXincrement = 1, + .xCount = 6, + .srcYincrement = 0, + .dstYincrement = 0, + .yCount = 1, + .nextDescriptor = NULL, +}; +cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0 = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL, +}; +const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig = +{ + .descriptor = &cpuss_0_dw0_0_chan_0_Descriptor_0, + .preemptable = true, + .priority = 1, + .enable = false, + .bufferable = false, +}; +const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config = +{ + .retrigger = CY_DMA_RETRIG_16CYC, + .interruptType = CY_DMA_1ELEMENT, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_1ELEMENT, + .dataSize = CY_DMA_BYTE, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_1D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 1, + .dstXincrement = 0, + .xCount = 5, + .srcYincrement = 0, + .dstYincrement = 0, + .yCount = 1, + .nextDescriptor = NULL, +}; +cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0 = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL, +}; +const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig = +{ + .descriptor = &cpuss_0_dw0_0_chan_1_Descriptor_0, + .preemptable = true, + .priority = 1, + .enable = false, + .bufferable = false, +}; +const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config = +{ + .retrigger = CY_DMA_RETRIG_4CYC, + .interruptType = CY_DMA_DESCR, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_X_LOOP, + .dataSize = CY_DMA_HALFWORD, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_2D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 2, + .dstXincrement = 0, + .xCount = 10, + .srcYincrement = 10, + .dstYincrement = 0, + .yCount = 2, + .nextDescriptor = NULL, +}; +cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0 = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL, +}; +const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig = +{ + .descriptor = &cpuss_0_dw1_0_chan_1_Descriptor_0, + .preemptable = false, + .priority = 0, + .enable = false, + .bufferable = false, +}; +const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config = +{ + .retrigger = CY_DMA_RETRIG_IM, + .interruptType = CY_DMA_DESCR, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_X_LOOP, + .dataSize = CY_DMA_HALFWORD, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_2D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 0, + .dstXincrement = 2, + .xCount = 10, + .srcYincrement = 0, + .dstYincrement = 10, + .yCount = 2, + .nextDescriptor = NULL, +}; +cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0 = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL, +}; +const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig = +{ + .descriptor = &cpuss_0_dw1_0_chan_3_Descriptor_0, + .preemptable = false, + .priority = 0, + .enable = false, + .bufferable = false, +}; + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_dmas.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_dmas.h new file mode 100644 index 0000000000..c68d4b9ec8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_dmas.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* File Name: cycfg_dmas.h +* +* Description: +* DMA configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_DMAS_H) +#define CYCFG_DMAS_H + +#include "cycfg_notices.h" +#include "cy_dma.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define cpuss_0_dw0_0_chan_0_HW DW0 +#define cpuss_0_dw0_0_chan_0_CHANNEL 0 +#define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn +#define cpuss_0_dw0_0_chan_1_HW DW0 +#define cpuss_0_dw0_0_chan_1_CHANNEL 1 +#define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn +#define cpuss_0_dw1_0_chan_1_HW DW1 +#define cpuss_0_dw1_0_chan_1_CHANNEL 1 +#define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn +#define cpuss_0_dw1_0_chan_3_HW DW1 +#define cpuss_0_dw1_0_chan_3_CHANNEL 3 +#define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn + +extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config; +extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0; +extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig; +extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config; +extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0; +extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig; +extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config; +extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0; +extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig; +extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config; +extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0; +extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig; + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_DMAS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_notices.h new file mode 100644 index 0000000000..90f1013f8a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_notices.h @@ -0,0 +1,30 @@ +/******************************************************************************* +* File Name: cycfg_notices.h +* +* Description: +* Contains warnings and errors that occurred while generating code for the +* design. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_NOTICES_H) +#define CYCFG_NOTICES_H + + +#endif /* CYCFG_NOTICES_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.c new file mode 100644 index 0000000000..eff312bed2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.c @@ -0,0 +1,204 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.c +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_peripherals.h" + +#define PWM_INPUT_DISABLED 0x7U +#define USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \ + CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \ + CY_USBFS_DEV_DRV_SET_EP1_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_EP2_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U)) + +cy_stc_csd_context_t cy_csd_0_context = +{ + .lockKey = CY_CSD_NONE_KEY, +}; +const cy_stc_scb_uart_config_t BT_UART_config = +{ + .uartMode = CY_SCB_UART_STANDARD, + .enableMutliProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + .oversample = 8, + .enableMsbFirst = false, + .dataWidth = 8UL, + .parity = CY_SCB_UART_PARITY_NONE, + .stopBits = CY_SCB_UART_STOP_BITS_1, + .enableInputFilter = false, + .breakWidth = 11UL, + .dropOnFrameError = false, + .dropOnParityError = false, + .receiverAddress = 0x0UL, + .receiverAddressMask = 0x0UL, + .acceptAddrInFifo = false, + .enableCts = true, + .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rtsRxFifoLevel = 63, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rxFifoTriggerLevel = 1UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, +}; +const cy_stc_scb_ezi2c_config_t CSD_COMM_config = +{ + .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS, + .slaveAddress1 = 8U, + .slaveAddress2 = 0U, + .subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS, + .enableWakeFromSleep = false, +}; +const cy_stc_scb_uart_config_t KITPROG_UART_config = +{ + .uartMode = CY_SCB_UART_STANDARD, + .enableMutliProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + .oversample = 8, + .enableMsbFirst = false, + .dataWidth = 8UL, + .parity = CY_SCB_UART_PARITY_NONE, + .stopBits = CY_SCB_UART_STOP_BITS_1, + .enableInputFilter = false, + .breakWidth = 11UL, + .dropOnFrameError = false, + .dropOnParityError = false, + .receiverAddress = 0x0UL, + .receiverAddressMask = 0x0UL, + .acceptAddrInFifo = false, + .enableCts = false, + .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rtsRxFifoLevel = 0UL, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rxFifoTriggerLevel = 63UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, +}; +const cy_stc_smif_config_t QSPI_config = +{ + .mode = (uint32_t)CY_SMIF_NORMAL, + .deselectDelay = QSPI_DESELECT_DELAY, + .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK, + .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, +}; +const cy_stc_mcwdt_config_t MCWDT0_config = +{ + .c0Match = 32768U, + .c1Match = 32768U, + .c0Mode = CY_MCWDT_MODE_NONE, + .c1Mode = CY_MCWDT_MODE_NONE, + .c2ToggleBit = 16U, + .c2Mode = CY_MCWDT_MODE_NONE, + .c0ClearOnMatch = false, + .c1ClearOnMatch = false, + .c0c1Cascade = true, + .c1c2Cascade = false, +}; +const cy_stc_rtc_config_t RTC_config = +{ + .sec = 0U, + .min = 0U, + .hour = 12U, + .amPm = CY_RTC_AM, + .hrFormat = CY_RTC_24_HOURS, + .dayOfWeek = CY_RTC_SUNDAY, + .date = 1U, + .month = CY_RTC_JANUARY, + .year = 0U, +}; +const cy_stc_tcpwm_pwm_config_t PWM_config = +{ + .pwmMode = CY_TCPWM_PWM_MODE_PWM, + .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, + .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, + .deadTimeClocks = 0, + .runMode = CY_TCPWM_PWM_CONTINUOUS, + .period0 = 32000, + .period1 = 32768, + .enablePeriodSwap = false, + .compare0 = 16384, + .compare1 = 16384, + .enableCompareSwap = false, + .interruptSources = CY_TCPWM_INT_NONE, + .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE, + .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE, + .killMode = CY_TCPWM_PWM_STOP_ON_KILL, + .swapInputMode = PWM_INPUT_DISABLED & 0x3U, + .swapInput = CY_TCPWM_INPUT_0, + .reloadInputMode = PWM_INPUT_DISABLED & 0x3U, + .reloadInput = CY_TCPWM_INPUT_0, + .startInputMode = PWM_INPUT_DISABLED & 0x3U, + .startInput = CY_TCPWM_INPUT_0, + .killInputMode = PWM_INPUT_DISABLED & 0x3U, + .killInput = CY_TCPWM_INPUT_0, + .countInputMode = PWM_INPUT_DISABLED & 0x3U, + .countInput = CY_TCPWM_INPUT_1, +}; +const cy_stc_usbfs_dev_drv_config_t USBUART_config = +{ + .mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU, + .epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR, + .epBuffer = NULL, + .epBufferSize = 0U, + .dmaConfig[0] = NULL, + .dmaConfig[1] = NULL, + .dmaConfig[2] = NULL, + .dmaConfig[3] = NULL, + .dmaConfig[4] = NULL, + .dmaConfig[5] = NULL, + .dmaConfig[6] = NULL, + .dmaConfig[7] = NULL, + .enableLpm = false, + .intrLevelSel = USBUART_INTR_LVL_SEL, +}; + + +void init_cycfg_peripherals(void) +{ + Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB6_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U); + + Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM1_CLOCKS1, CY_SYSCLK_DIV_8_BIT, 3U); + + Cy_SysClk_PeriphAssignDivider(PCLK_UDB_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 0u); + + Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.h new file mode 100644 index 0000000000..6104f938c3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.h @@ -0,0 +1,140 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.h +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PERIPHERALS_H) +#define CYCFG_PERIPHERALS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_csd.h" +#include "cy_scb_uart.h" +#include "cy_scb_ezi2c.h" +#include "cy_smif.h" +#include "cy_mcwdt.h" +#include "cy_rtc.h" +#include "cy_tcpwm_pwm.h" +#include "cycfg_connectivity.h" +#include "cy_usbfs_dev_drv.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CY_CAPSENSE_CORE 4u +#define CY_CAPSENSE_CPU_CLK 100000000u +#define CY_CAPSENSE_PERI_CLK 100000000u +#define CY_CAPSENSE_VDDA_MV 3300u +#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT +#define CY_CAPSENSE_PERI_DIV_INDEX 4u +#define Cmod_PORT GPIO_PRT7 +#define CintA_PORT GPIO_PRT7 +#define CintB_PORT GPIO_PRT7 +#define Button0_Rx0_PORT GPIO_PRT8 +#define Button0_Tx_PORT GPIO_PRT1 +#define Button1_Rx0_PORT GPIO_PRT8 +#define Button1_Tx_PORT GPIO_PRT1 +#define LinearSlider0_Sns0_PORT GPIO_PRT8 +#define LinearSlider0_Sns1_PORT GPIO_PRT8 +#define LinearSlider0_Sns2_PORT GPIO_PRT8 +#define LinearSlider0_Sns3_PORT GPIO_PRT8 +#define LinearSlider0_Sns4_PORT GPIO_PRT8 +#define Cmod_PIN 7u +#define CintA_PIN 1u +#define CintB_PIN 2u +#define Button0_Rx0_PIN 1u +#define Button0_Tx_PIN 0u +#define Button1_Rx0_PIN 2u +#define Button1_Tx_PIN 0u +#define LinearSlider0_Sns0_PIN 3u +#define LinearSlider0_Sns1_PIN 4u +#define LinearSlider0_Sns2_PIN 5u +#define LinearSlider0_Sns3_PIN 6u +#define LinearSlider0_Sns4_PIN 7u +#define Cmod_PORT_NUM 7u +#define CintA_PORT_NUM 7u +#define CintB_PORT_NUM 7u +#define CapSense_HW CSD0 +#define CapSense_IRQ csd_interrupt_IRQn +#define BT_UART_HW SCB2 +#define BT_UART_IRQ scb_2_interrupt_IRQn +#define CSD_COMM_HW SCB3 +#define CSD_COMM_IRQ scb_3_interrupt_IRQn +#define KITPROG_UART_HW SCB6 +#define KITPROG_UART_IRQ scb_6_interrupt_IRQn +#define QSPI_HW SMIF0 +#define QSPI_IRQ smif_interrupt_IRQn +#define QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL) +#define QSPI_RX_DATA_FIFO_UNDERFLOW (0UL) +#define QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL) +#define QSPI_TX_DATA_FIFO_OVERFLOW (0UL) +#define QSPI_RX_FIFO_TRIGEER_LEVEL (0UL) +#define QSPI_TX_FIFO_TRIGEER_LEVEL (0UL) +#define QSPI_DATALINES0_1 (1UL) +#define QSPI_DATALINES2_3 (1UL) +#define QSPI_DATALINES4_5 (0UL) +#define QSPI_DATALINES6_7 (0UL) +#define QSPI_SS0 (1UL) +#define QSPI_SS1 (0UL) +#define QSPI_SS2 (0UL) +#define QSPI_SS3 (0UL) +#define QSPI_DESELECT_DELAY 7 +#define MCWDT0_HW MCWDT_STRUCT0 +#define RTC_10_MONTH_OFFSET (28U) +#define RTC_MONTH_OFFSET (24U) +#define RTC_10_DAY_OFFSET (20U) +#define RTC_DAY_OFFSET (16U) +#define RTC_1000_YEAR_OFFSET (12U) +#define RTC_100_YEAR_OFFSET (8U) +#define RTC_10_YEAR_OFFSET (4U) +#define RTC_YEAR_OFFSET (0U) +#define PWM_HW TCPWM1 +#define PWM_NUM 1UL +#define PWM_MASK (1UL << 1) +#define USBUART_ACTIVE_ENDPOINTS_MASK 7U +#define USBUART_ENDPOINTS_BUFFER_SIZE 140U +#define USBUART_ENDPOINTS_ACCESS_TYPE 0U +#define USBUART_USB_CORE 4U +#define USBUART_HW USBFS0 +#define USBUART_HI_IRQ usb_interrupt_hi_IRQn +#define USBUART_MED_IRQ usb_interrupt_med_IRQn +#define USBUART_LO_IRQ usb_interrupt_lo_IRQn + +extern cy_stc_csd_context_t cy_csd_0_context; +extern const cy_stc_scb_uart_config_t BT_UART_config; +extern const cy_stc_scb_ezi2c_config_t CSD_COMM_config; +extern const cy_stc_scb_uart_config_t KITPROG_UART_config; +extern const cy_stc_smif_config_t QSPI_config; +extern const cy_stc_mcwdt_config_t MCWDT0_config; +extern const cy_stc_rtc_config_t RTC_config; +extern const cy_stc_tcpwm_pwm_config_t PWM_config; +extern const cy_stc_usbfs_dev_drv_config_t USBUART_config; + +void init_cycfg_peripherals(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PERIPHERALS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.c new file mode 100644 index 0000000000..2c56839265 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.c @@ -0,0 +1,1045 @@ +/******************************************************************************* +* File Name: cycfg_pins.c +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_pins.h" + +const cy_stc_gpio_pin_config_t WCO_IN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = WCO_IN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t WCO_OUT_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = WCO_OUT_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED_RED_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED_RED_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SW6_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = SW6_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED_BLUE_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED_BLUE_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t WL_UART_RX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = WL_UART_RX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t WL_UART_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = WL_UART_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_SS0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = QSPI_SS0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_DATA0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = QSPI_DATA0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = QSPI_SPI_CLOCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t ioss_0_port_12_pin_6_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = ioss_0_port_12_pin_6_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t ioss_0_port_12_pin_7_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = ioss_0_port_12_pin_7_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t UART_RX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = UART_RX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t UART_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = UART_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED9_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED9_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = ioss_0_port_14_pin_0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = ioss_0_port_14_pin_1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED_GREEN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED_GREEN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t LED8_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = LED8_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_DAT0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_DAT0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_DAT1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_DAT1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_DAT2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_DAT2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_DAT3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_DAT3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_CMD_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = SDHC0_CMD_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SDHC0_CLK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = SDHC0_CLK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t ENABLE_WIFI_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = ENABLE_WIFI_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_UART_RX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = BT_UART_RX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_UART_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = BT_UART_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_UART_RTS_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = BT_UART_RTS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_UART_CTS_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = BT_UART_CTS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_POWER_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF, + .hsiom = BT_POWER_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = BT_HOST_WAKE_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config = +{ + .outVal = 0, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = BT_DEVICE_WAKE_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t EZI2C_SCL_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = EZI2C_SCL_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t EZI2C_SDA_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = EZI2C_SDA_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SWO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = SWO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SWDIO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = SWDIO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t SWDCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLDOWN, + .hsiom = SWDCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t ioss_0_port_7_pin_0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = ioss_0_port_7_pin_0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CINA_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CINA_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CINB_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CINB_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CMOD_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CMOD_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_BTN0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_BTN0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_BTN1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_BTN1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CSD_SLD4_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CSD_SLD4_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t ioss_0_port_9_pin_0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = ioss_0_port_9_pin_0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t ioss_0_port_9_pin_1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = ioss_0_port_9_pin_1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t ioss_0_port_9_pin_2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = ioss_0_port_9_pin_2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t ioss_0_port_9_pin_3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = ioss_0_port_9_pin_3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; + + +void init_cycfg_pins(void) +{ + Cy_GPIO_Pin_Init(WCO_IN_PORT, WCO_IN_PIN, &WCO_IN_config); + + Cy_GPIO_Pin_Init(WCO_OUT_PORT, WCO_OUT_PIN, &WCO_OUT_config); + + Cy_GPIO_Pin_Init(LED_RED_PORT, LED_RED_PIN, &LED_RED_config); + + Cy_GPIO_Pin_Init(SW6_PORT, SW6_PIN, &SW6_config); + + Cy_GPIO_Pin_Init(LED_BLUE_PORT, LED_BLUE_PIN, &LED_BLUE_config); + + Cy_GPIO_Pin_Init(WL_UART_RX_PORT, WL_UART_RX_PIN, &WL_UART_RX_config); + + Cy_GPIO_Pin_Init(WL_UART_TX_PORT, WL_UART_TX_PIN, &WL_UART_TX_config); + + Cy_GPIO_Pin_Init(QSPI_SS0_PORT, QSPI_SS0_PIN, &QSPI_SS0_config); + + Cy_GPIO_Pin_Init(QSPI_DATA3_PORT, QSPI_DATA3_PIN, &QSPI_DATA3_config); + + Cy_GPIO_Pin_Init(QSPI_DATA2_PORT, QSPI_DATA2_PIN, &QSPI_DATA2_config); + + Cy_GPIO_Pin_Init(QSPI_DATA1_PORT, QSPI_DATA1_PIN, &QSPI_DATA1_config); + + Cy_GPIO_Pin_Init(QSPI_DATA0_PORT, QSPI_DATA0_PIN, &QSPI_DATA0_config); + + Cy_GPIO_Pin_Init(QSPI_SPI_CLOCK_PORT, QSPI_SPI_CLOCK_PIN, &QSPI_SPI_CLOCK_config); + + Cy_GPIO_Pin_Init(ioss_0_port_12_pin_6_PORT, ioss_0_port_12_pin_6_PIN, &ioss_0_port_12_pin_6_config); + + Cy_GPIO_Pin_Init(ioss_0_port_12_pin_7_PORT, ioss_0_port_12_pin_7_PIN, &ioss_0_port_12_pin_7_config); + + Cy_GPIO_Pin_Init(UART_RX_PORT, UART_RX_PIN, &UART_RX_config); + + Cy_GPIO_Pin_Init(UART_TX_PORT, UART_TX_PIN, &UART_TX_config); + + Cy_GPIO_Pin_Init(LED9_PORT, LED9_PIN, &LED9_config); + + Cy_GPIO_Pin_Init(ioss_0_port_14_pin_0_PORT, ioss_0_port_14_pin_0_PIN, &ioss_0_port_14_pin_0_config); + + Cy_GPIO_Pin_Init(ioss_0_port_14_pin_1_PORT, ioss_0_port_14_pin_1_PIN, &ioss_0_port_14_pin_1_config); + + + Cy_GPIO_Pin_Init(LED_GREEN_PORT, LED_GREEN_PIN, &LED_GREEN_config); + + Cy_GPIO_Pin_Init(LED8_PORT, LED8_PIN, &LED8_config); + + Cy_GPIO_Pin_Init(SDHC0_DAT0_PORT, SDHC0_DAT0_PIN, &SDHC0_DAT0_config); + + Cy_GPIO_Pin_Init(SDHC0_DAT1_PORT, SDHC0_DAT1_PIN, &SDHC0_DAT1_config); + + Cy_GPIO_Pin_Init(SDHC0_DAT2_PORT, SDHC0_DAT2_PIN, &SDHC0_DAT2_config); + + Cy_GPIO_Pin_Init(SDHC0_DAT3_PORT, SDHC0_DAT3_PIN, &SDHC0_DAT3_config); + + Cy_GPIO_Pin_Init(SDHC0_CMD_PORT, SDHC0_CMD_PIN, &SDHC0_CMD_config); + + Cy_GPIO_Pin_Init(SDHC0_CLK_PORT, SDHC0_CLK_PIN, &SDHC0_CLK_config); + + Cy_GPIO_Pin_Init(ENABLE_WIFI_PORT, ENABLE_WIFI_PIN, &ENABLE_WIFI_config); + + Cy_GPIO_Pin_Init(BT_UART_RX_PORT, BT_UART_RX_PIN, &BT_UART_RX_config); + + Cy_GPIO_Pin_Init(BT_UART_TX_PORT, BT_UART_TX_PIN, &BT_UART_TX_config); + + Cy_GPIO_Pin_Init(BT_UART_RTS_PORT, BT_UART_RTS_PIN, &BT_UART_RTS_config); + + Cy_GPIO_Pin_Init(BT_UART_CTS_PORT, BT_UART_CTS_PIN, &BT_UART_CTS_config); + + Cy_GPIO_Pin_Init(BT_POWER_PORT, BT_POWER_PIN, &BT_POWER_config); + + Cy_GPIO_Pin_Init(BT_HOST_WAKE_PORT, BT_HOST_WAKE_PIN, &BT_HOST_WAKE_config); + + Cy_GPIO_Pin_Init(BT_DEVICE_WAKE_PORT, BT_DEVICE_WAKE_PIN, &BT_DEVICE_WAKE_config); + + Cy_GPIO_Pin_Init(EZI2C_SCL_PORT, EZI2C_SCL_PIN, &EZI2C_SCL_config); + + Cy_GPIO_Pin_Init(EZI2C_SDA_PORT, EZI2C_SDA_PIN, &EZI2C_SDA_config); + + Cy_GPIO_Pin_Init(SWO_PORT, SWO_PIN, &SWO_config); + + Cy_GPIO_Pin_Init(SWDIO_PORT, SWDIO_PIN, &SWDIO_config); + + Cy_GPIO_Pin_Init(SWDCK_PORT, SWDCK_PIN, &SWDCK_config); + + Cy_GPIO_Pin_Init(ioss_0_port_7_pin_0_PORT, ioss_0_port_7_pin_0_PIN, &ioss_0_port_7_pin_0_config); + + + + + + + + + + + + Cy_GPIO_Pin_Init(ioss_0_port_9_pin_0_PORT, ioss_0_port_9_pin_0_PIN, &ioss_0_port_9_pin_0_config); + + Cy_GPIO_Pin_Init(ioss_0_port_9_pin_1_PORT, ioss_0_port_9_pin_1_PIN, &ioss_0_port_9_pin_1_config); + + Cy_GPIO_Pin_Init(ioss_0_port_9_pin_2_PORT, ioss_0_port_9_pin_2_PIN, &ioss_0_port_9_pin_2_config); + + Cy_GPIO_Pin_Init(ioss_0_port_9_pin_3_PORT, ioss_0_port_9_pin_3_PIN, &ioss_0_port_9_pin_3_config); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.h new file mode 100644 index 0000000000..68fce9d2dd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.h @@ -0,0 +1,663 @@ +/******************************************************************************* +* File Name: cycfg_pins.h +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PINS_H) +#define CYCFG_PINS_H + +#include "cycfg_notices.h" +#include "cy_gpio.h" +#include "cycfg_connectivity.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define WCO_IN_PORT GPIO_PRT0 +#define WCO_IN_PIN 0U +#define WCO_IN_NUM 0U +#define WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG +#define WCO_IN_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_0_HSIOM + #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM +#define WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn +#define WCO_OUT_PORT GPIO_PRT0 +#define WCO_OUT_PIN 1U +#define WCO_OUT_NUM 1U +#define WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG +#define WCO_OUT_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_1_HSIOM + #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM +#define WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn +#define LED_RED_PORT GPIO_PRT0 +#define LED_RED_PIN 3U +#define LED_RED_NUM 3U +#define LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED_RED_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_3_HSIOM + #define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM +#define LED_RED_IRQ ioss_interrupts_gpio_0_IRQn +#define SW6_PORT GPIO_PRT0 +#define SW6_PIN 4U +#define SW6_NUM 4U +#define SW6_DRIVEMODE CY_GPIO_DM_PULLUP +#define SW6_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_4_HSIOM + #define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define SW6_HSIOM ioss_0_port_0_pin_4_HSIOM +#define SW6_IRQ ioss_interrupts_gpio_0_IRQn +#define LED_BLUE_PORT GPIO_PRT10 +#define LED_BLUE_PIN 6U +#define LED_BLUE_NUM 6U +#define LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED_BLUE_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_10_pin_6_HSIOM + #define ioss_0_port_10_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define LED_BLUE_HSIOM ioss_0_port_10_pin_6_HSIOM +#define LED_BLUE_IRQ ioss_interrupts_gpio_10_IRQn +#define WL_UART_RX_PORT GPIO_PRT11 +#define WL_UART_RX_PIN 0U +#define WL_UART_RX_NUM 0U +#define WL_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ +#define WL_UART_RX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_0_HSIOM + #define ioss_0_port_11_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define WL_UART_RX_HSIOM ioss_0_port_11_pin_0_HSIOM +#define WL_UART_RX_IRQ ioss_interrupts_gpio_11_IRQn +#define WL_UART_TX_PORT GPIO_PRT11 +#define WL_UART_TX_PIN 1U +#define WL_UART_TX_NUM 1U +#define WL_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define WL_UART_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_1_HSIOM + #define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define WL_UART_TX_HSIOM ioss_0_port_11_pin_1_HSIOM +#define WL_UART_TX_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_SS0_PORT GPIO_PRT11 +#define QSPI_SS0_PIN 2U +#define QSPI_SS0_NUM 2U +#define QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define QSPI_SS0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_2_HSIOM + #define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM +#define QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA3_PORT GPIO_PRT11 +#define QSPI_DATA3_PIN 3U +#define QSPI_DATA3_NUM 3U +#define QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_3_HSIOM + #define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM +#define QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA2_PORT GPIO_PRT11 +#define QSPI_DATA2_PIN 4U +#define QSPI_DATA2_NUM 4U +#define QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_4_HSIOM + #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM +#define QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA1_PORT GPIO_PRT11 +#define QSPI_DATA1_PIN 5U +#define QSPI_DATA1_NUM 5U +#define QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_5_HSIOM + #define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM +#define QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_DATA0_PORT GPIO_PRT11 +#define QSPI_DATA0_PIN 6U +#define QSPI_DATA0_NUM 6U +#define QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG +#define QSPI_DATA0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_6_HSIOM + #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM +#define QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn +#define QSPI_SPI_CLOCK_PORT GPIO_PRT11 +#define QSPI_SPI_CLOCK_PIN 7U +#define QSPI_SPI_CLOCK_NUM 7U +#define QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define QSPI_SPI_CLOCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_7_HSIOM + #define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM +#define QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn +#define ioss_0_port_12_pin_6_PORT GPIO_PRT12 +#define ioss_0_port_12_pin_6_PIN 6U +#define ioss_0_port_12_pin_6_NUM 6U +#define ioss_0_port_12_pin_6_DRIVEMODE CY_GPIO_DM_ANALOG +#define ioss_0_port_12_pin_6_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_12_pin_6_HSIOM + #define ioss_0_port_12_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define ioss_0_port_12_pin_6_IRQ ioss_interrupts_gpio_12_IRQn +#define ioss_0_port_12_pin_7_PORT GPIO_PRT12 +#define ioss_0_port_12_pin_7_PIN 7U +#define ioss_0_port_12_pin_7_NUM 7U +#define ioss_0_port_12_pin_7_DRIVEMODE CY_GPIO_DM_ANALOG +#define ioss_0_port_12_pin_7_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_12_pin_7_HSIOM + #define ioss_0_port_12_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define ioss_0_port_12_pin_7_IRQ ioss_interrupts_gpio_12_IRQn +#define UART_RX_PORT GPIO_PRT13 +#define UART_RX_PIN 0U +#define UART_RX_NUM 0U +#define UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ +#define UART_RX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_13_pin_0_HSIOM + #define ioss_0_port_13_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define UART_RX_HSIOM ioss_0_port_13_pin_0_HSIOM +#define UART_RX_IRQ ioss_interrupts_gpio_13_IRQn +#define UART_TX_PORT GPIO_PRT13 +#define UART_TX_PIN 1U +#define UART_TX_NUM 1U +#define UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define UART_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_13_pin_1_HSIOM + #define ioss_0_port_13_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define UART_TX_HSIOM ioss_0_port_13_pin_1_HSIOM +#define UART_TX_IRQ ioss_interrupts_gpio_13_IRQn +#define LED9_PORT GPIO_PRT13 +#define LED9_PIN 7U +#define LED9_NUM 7U +#define LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED9_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_13_pin_7_HSIOM + #define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define LED9_HSIOM ioss_0_port_13_pin_7_HSIOM +#define LED9_IRQ ioss_interrupts_gpio_13_IRQn +#define ioss_0_port_14_pin_0_PORT GPIO_PRT14 +#define ioss_0_port_14_pin_0_PIN 0U +#define ioss_0_port_14_pin_0_NUM 0U +#define ioss_0_port_14_pin_0_DRIVEMODE CY_GPIO_DM_ANALOG +#define ioss_0_port_14_pin_0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_14_pin_0_HSIOM + #define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define ioss_0_port_14_pin_0_IRQ ioss_interrupts_gpio_14_IRQn +#define ioss_0_port_14_pin_1_PORT GPIO_PRT14 +#define ioss_0_port_14_pin_1_PIN 1U +#define ioss_0_port_14_pin_1_NUM 1U +#define ioss_0_port_14_pin_1_DRIVEMODE CY_GPIO_DM_ANALOG +#define ioss_0_port_14_pin_1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_14_pin_1_HSIOM + #define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define ioss_0_port_14_pin_1_IRQ ioss_interrupts_gpio_14_IRQn +#define CSD_TX_PORT GPIO_PRT1 +#define CSD_TX_PIN 0U +#define CSD_TX_NUM 0U +#define CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_0_HSIOM + #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM +#define CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn +#define LED_GREEN_PORT GPIO_PRT1 +#define LED_GREEN_PIN 1U +#define LED_GREEN_NUM 1U +#define LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED_GREEN_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_1_HSIOM + #define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM +#define LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn +#define LED8_PORT GPIO_PRT1 +#define LED8_PIN 5U +#define LED8_NUM 5U +#define LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define LED8_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_5_HSIOM + #define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define LED8_HSIOM ioss_0_port_1_pin_5_HSIOM +#define LED8_IRQ ioss_interrupts_gpio_1_IRQn +#define SDHC0_DAT0_PORT GPIO_PRT2 +#define SDHC0_DAT0_PIN 0U +#define SDHC0_DAT0_NUM 0U +#define SDHC0_DAT0_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_DAT0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_0_HSIOM + #define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_DAT0_HSIOM ioss_0_port_2_pin_0_HSIOM +#define SDHC0_DAT0_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_DAT1_PORT GPIO_PRT2 +#define SDHC0_DAT1_PIN 1U +#define SDHC0_DAT1_NUM 1U +#define SDHC0_DAT1_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_DAT1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_1_HSIOM + #define ioss_0_port_2_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_DAT1_HSIOM ioss_0_port_2_pin_1_HSIOM +#define SDHC0_DAT1_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_DAT2_PORT GPIO_PRT2 +#define SDHC0_DAT2_PIN 2U +#define SDHC0_DAT2_NUM 2U +#define SDHC0_DAT2_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_DAT2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_2_HSIOM + #define ioss_0_port_2_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_DAT2_HSIOM ioss_0_port_2_pin_2_HSIOM +#define SDHC0_DAT2_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_DAT3_PORT GPIO_PRT2 +#define SDHC0_DAT3_PIN 3U +#define SDHC0_DAT3_NUM 3U +#define SDHC0_DAT3_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_DAT3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_3_HSIOM + #define ioss_0_port_2_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_DAT3_HSIOM ioss_0_port_2_pin_3_HSIOM +#define SDHC0_DAT3_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_CMD_PORT GPIO_PRT2 +#define SDHC0_CMD_PIN 4U +#define SDHC0_CMD_NUM 4U +#define SDHC0_CMD_DRIVEMODE CY_GPIO_DM_STRONG +#define SDHC0_CMD_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_4_HSIOM + #define ioss_0_port_2_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM +#define SDHC0_CMD_IRQ ioss_interrupts_gpio_2_IRQn +#define SDHC0_CLK_PORT GPIO_PRT2 +#define SDHC0_CLK_PIN 5U +#define SDHC0_CLK_NUM 5U +#define SDHC0_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define SDHC0_CLK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_2_pin_5_HSIOM + #define ioss_0_port_2_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define SDHC0_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM +#define SDHC0_CLK_IRQ ioss_interrupts_gpio_2_IRQn +#define ENABLE_WIFI_PORT GPIO_PRT2 +#define ENABLE_WIFI_PIN 6U +#define ENABLE_WIFI_NUM 6U +#define ENABLE_WIFI_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define ENABLE_WIFI_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_2_pin_6_HSIOM + #define ioss_0_port_2_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define ENABLE_WIFI_HSIOM ioss_0_port_2_pin_6_HSIOM +#define ENABLE_WIFI_IRQ ioss_interrupts_gpio_2_IRQn +#define BT_UART_RX_PORT GPIO_PRT3 +#define BT_UART_RX_PIN 0U +#define BT_UART_RX_NUM 0U +#define BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ +#define BT_UART_RX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_0_HSIOM + #define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM +#define BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_UART_TX_PORT GPIO_PRT3 +#define BT_UART_TX_PIN 1U +#define BT_UART_TX_NUM 1U +#define BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define BT_UART_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_1_HSIOM + #define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM +#define BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_UART_RTS_PORT GPIO_PRT3 +#define BT_UART_RTS_PIN 2U +#define BT_UART_RTS_NUM 2U +#define BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define BT_UART_RTS_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_2_HSIOM + #define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM +#define BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_UART_CTS_PORT GPIO_PRT3 +#define BT_UART_CTS_PIN 3U +#define BT_UART_CTS_NUM 3U +#define BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ +#define BT_UART_CTS_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_3_HSIOM + #define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM +#define BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_POWER_PORT GPIO_PRT3 +#define BT_POWER_PIN 4U +#define BT_POWER_NUM 4U +#define BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF +#define BT_POWER_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_3_pin_4_HSIOM + #define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM +#define BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_HOST_WAKE_PORT GPIO_PRT3 +#define BT_HOST_WAKE_PIN 5U +#define BT_HOST_WAKE_NUM 5U +#define BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG +#define BT_HOST_WAKE_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_3_pin_5_HSIOM + #define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM +#define BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn +#define BT_DEVICE_WAKE_PORT GPIO_PRT4 +#define BT_DEVICE_WAKE_PIN 0U +#define BT_DEVICE_WAKE_NUM 0U +#define BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define BT_DEVICE_WAKE_INIT_DRIVESTATE 0 +#ifndef ioss_0_port_4_pin_0_HSIOM + #define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM +#define BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn +#define EZI2C_SCL_PORT GPIO_PRT6 +#define EZI2C_SCL_PIN 0U +#define EZI2C_SCL_NUM 0U +#define EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define EZI2C_SCL_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_0_HSIOM + #define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM +#define EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn +#define EZI2C_SDA_PORT GPIO_PRT6 +#define EZI2C_SDA_PIN 1U +#define EZI2C_SDA_NUM 1U +#define EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define EZI2C_SDA_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_1_HSIOM + #define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM +#define EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn +#define SWO_PORT GPIO_PRT6 +#define SWO_PIN 4U +#define SWO_NUM 4U +#define SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define SWO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_4_HSIOM + #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define SWO_HSIOM ioss_0_port_6_pin_4_HSIOM +#define SWO_IRQ ioss_interrupts_gpio_6_IRQn +#define SWDIO_PORT GPIO_PRT6 +#define SWDIO_PIN 6U +#define SWDIO_NUM 6U +#define SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP +#define SWDIO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_6_HSIOM + #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM +#define SWDIO_IRQ ioss_interrupts_gpio_6_IRQn +#define SWDCK_PORT GPIO_PRT6 +#define SWDCK_PIN 7U +#define SWDCK_NUM 7U +#define SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN +#define SWDCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_7_HSIOM + #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM +#define SWDCK_IRQ ioss_interrupts_gpio_6_IRQn +#define ioss_0_port_7_pin_0_PORT GPIO_PRT7 +#define ioss_0_port_7_pin_0_PIN 0U +#define ioss_0_port_7_pin_0_NUM 0U +#define ioss_0_port_7_pin_0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define ioss_0_port_7_pin_0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_0_HSIOM + #define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define ioss_0_port_7_pin_0_IRQ ioss_interrupts_gpio_7_IRQn +#define CINA_PORT GPIO_PRT7 +#define CINA_PIN 1U +#define CINA_NUM 1U +#define CINA_DRIVEMODE CY_GPIO_DM_ANALOG +#define CINA_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_1_HSIOM + #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CINA_HSIOM ioss_0_port_7_pin_1_HSIOM +#define CINA_IRQ ioss_interrupts_gpio_7_IRQn +#define CINB_PORT GPIO_PRT7 +#define CINB_PIN 2U +#define CINB_NUM 2U +#define CINB_DRIVEMODE CY_GPIO_DM_ANALOG +#define CINB_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_2_HSIOM + #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CINB_HSIOM ioss_0_port_7_pin_2_HSIOM +#define CINB_IRQ ioss_interrupts_gpio_7_IRQn +#define CMOD_PORT GPIO_PRT7 +#define CMOD_PIN 7U +#define CMOD_NUM 7U +#define CMOD_DRIVEMODE CY_GPIO_DM_ANALOG +#define CMOD_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_7_HSIOM + #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM +#define CMOD_IRQ ioss_interrupts_gpio_7_IRQn +#define CSD_BTN0_PORT GPIO_PRT8 +#define CSD_BTN0_PIN 1U +#define CSD_BTN0_NUM 1U +#define CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_BTN0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_1_HSIOM + #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM +#define CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_BTN1_PORT GPIO_PRT8 +#define CSD_BTN1_PIN 2U +#define CSD_BTN1_NUM 2U +#define CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_BTN1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_2_HSIOM + #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM +#define CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD0_PORT GPIO_PRT8 +#define CSD_SLD0_PIN 3U +#define CSD_SLD0_NUM 3U +#define CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_3_HSIOM + #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM +#define CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD1_PORT GPIO_PRT8 +#define CSD_SLD1_PIN 4U +#define CSD_SLD1_NUM 4U +#define CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_4_HSIOM + #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM +#define CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD2_PORT GPIO_PRT8 +#define CSD_SLD2_PIN 5U +#define CSD_SLD2_NUM 5U +#define CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_5_HSIOM + #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM +#define CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD3_PORT GPIO_PRT8 +#define CSD_SLD3_PIN 6U +#define CSD_SLD3_NUM 6U +#define CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_6_HSIOM + #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM +#define CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn +#define CSD_SLD4_PORT GPIO_PRT8 +#define CSD_SLD4_PIN 7U +#define CSD_SLD4_NUM 7U +#define CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG +#define CSD_SLD4_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_7_HSIOM + #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM +#define CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn +#define ioss_0_port_9_pin_0_PORT GPIO_PRT9 +#define ioss_0_port_9_pin_0_PIN 0U +#define ioss_0_port_9_pin_0_NUM 0U +#define ioss_0_port_9_pin_0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define ioss_0_port_9_pin_0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_9_pin_0_HSIOM + #define ioss_0_port_9_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define ioss_0_port_9_pin_0_IRQ ioss_interrupts_gpio_9_IRQn +#define ioss_0_port_9_pin_1_PORT GPIO_PRT9 +#define ioss_0_port_9_pin_1_PIN 1U +#define ioss_0_port_9_pin_1_NUM 1U +#define ioss_0_port_9_pin_1_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define ioss_0_port_9_pin_1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_9_pin_1_HSIOM + #define ioss_0_port_9_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define ioss_0_port_9_pin_1_IRQ ioss_interrupts_gpio_9_IRQn +#define ioss_0_port_9_pin_2_PORT GPIO_PRT9 +#define ioss_0_port_9_pin_2_PIN 2U +#define ioss_0_port_9_pin_2_NUM 2U +#define ioss_0_port_9_pin_2_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define ioss_0_port_9_pin_2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_9_pin_2_HSIOM + #define ioss_0_port_9_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define ioss_0_port_9_pin_2_IRQ ioss_interrupts_gpio_9_IRQn +#define ioss_0_port_9_pin_3_PORT GPIO_PRT9 +#define ioss_0_port_9_pin_3_PIN 3U +#define ioss_0_port_9_pin_3_NUM 3U +#define ioss_0_port_9_pin_3_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define ioss_0_port_9_pin_3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_9_pin_3_HSIOM + #define ioss_0_port_9_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define ioss_0_port_9_pin_3_IRQ ioss_interrupts_gpio_9_IRQn + +extern const cy_stc_gpio_pin_config_t WCO_IN_config; +extern const cy_stc_gpio_pin_config_t WCO_OUT_config; +extern const cy_stc_gpio_pin_config_t LED_RED_config; +extern const cy_stc_gpio_pin_config_t SW6_config; +extern const cy_stc_gpio_pin_config_t LED_BLUE_config; +extern const cy_stc_gpio_pin_config_t WL_UART_RX_config; +extern const cy_stc_gpio_pin_config_t WL_UART_TX_config; +extern const cy_stc_gpio_pin_config_t QSPI_SS0_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA3_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA2_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA1_config; +extern const cy_stc_gpio_pin_config_t QSPI_DATA0_config; +extern const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config; +extern const cy_stc_gpio_pin_config_t ioss_0_port_12_pin_6_config; +extern const cy_stc_gpio_pin_config_t ioss_0_port_12_pin_7_config; +extern const cy_stc_gpio_pin_config_t UART_RX_config; +extern const cy_stc_gpio_pin_config_t UART_TX_config; +extern const cy_stc_gpio_pin_config_t LED9_config; +extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config; +extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config; +extern const cy_stc_gpio_pin_config_t CSD_TX_config; +extern const cy_stc_gpio_pin_config_t LED_GREEN_config; +extern const cy_stc_gpio_pin_config_t LED8_config; +extern const cy_stc_gpio_pin_config_t SDHC0_DAT0_config; +extern const cy_stc_gpio_pin_config_t SDHC0_DAT1_config; +extern const cy_stc_gpio_pin_config_t SDHC0_DAT2_config; +extern const cy_stc_gpio_pin_config_t SDHC0_DAT3_config; +extern const cy_stc_gpio_pin_config_t SDHC0_CMD_config; +extern const cy_stc_gpio_pin_config_t SDHC0_CLK_config; +extern const cy_stc_gpio_pin_config_t ENABLE_WIFI_config; +extern const cy_stc_gpio_pin_config_t BT_UART_RX_config; +extern const cy_stc_gpio_pin_config_t BT_UART_TX_config; +extern const cy_stc_gpio_pin_config_t BT_UART_RTS_config; +extern const cy_stc_gpio_pin_config_t BT_UART_CTS_config; +extern const cy_stc_gpio_pin_config_t BT_POWER_config; +extern const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config; +extern const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config; +extern const cy_stc_gpio_pin_config_t EZI2C_SCL_config; +extern const cy_stc_gpio_pin_config_t EZI2C_SDA_config; +extern const cy_stc_gpio_pin_config_t SWO_config; +extern const cy_stc_gpio_pin_config_t SWDIO_config; +extern const cy_stc_gpio_pin_config_t SWDCK_config; +extern const cy_stc_gpio_pin_config_t ioss_0_port_7_pin_0_config; +extern const cy_stc_gpio_pin_config_t CINA_config; +extern const cy_stc_gpio_pin_config_t CINB_config; +extern const cy_stc_gpio_pin_config_t CMOD_config; +extern const cy_stc_gpio_pin_config_t CSD_BTN0_config; +extern const cy_stc_gpio_pin_config_t CSD_BTN1_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD0_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD1_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD2_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD3_config; +extern const cy_stc_gpio_pin_config_t CSD_SLD4_config; +extern const cy_stc_gpio_pin_config_t ioss_0_port_9_pin_0_config; +extern const cy_stc_gpio_pin_config_t ioss_0_port_9_pin_1_config; +extern const cy_stc_gpio_pin_config_t ioss_0_port_9_pin_2_config; +extern const cy_stc_gpio_pin_config_t ioss_0_port_9_pin_3_config; + +void init_cycfg_pins(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PINS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.c new file mode 100644 index 0000000000..341b5d7da8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.c @@ -0,0 +1,571 @@ +/******************************************************************************* +* File Name: cycfg_platform.c +* +* Description: +* Platform configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_platform.h" + +#define CY_CFG_SYSCLK_ECO_ERROR 1 +#define CY_CFG_SYSCLK_ALTHF_ERROR 2 +#define CY_CFG_SYSCLK_PLL_ERROR 3 +#define CY_CFG_SYSCLK_FLL_ERROR 4 +#define CY_CFG_SYSCLK_WCO_ERROR 5 +#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 +#define CY_CFG_SYSCLK_ECO_ENABLED 1 +#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 +#define CY_CFG_SYSCLK_FLL_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 48UL +#define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1 +#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL +#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL +#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1 +#define CY_CFG_SYSCLK_ILO_ENABLED 1 +#define CY_CFG_SYSCLK_IMO_ENABLED 1 +#define CY_CFG_SYSCLK_CLKLF_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 +#define CY_CFG_SYSCLK_PLL0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 +#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1 +#define CY_CFG_SYSCLK_WCO_ENABLED 1 +#define CY_CFG_PWR_ENABLED 1 +#define CY_CFG_PWR_USING_LDO 1 +#define CY_CFG_PWR_USING_PMIC 0 +#define CY_CFG_PWR_VBAC_SUPPLY CY_CFG_PWR_VBAC_SUPPLY_VDD +#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_1_1V +#define CY_CFG_PWR_USING_ULP 0 + +static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = +{ + .fllMult = 500U, + .refDiv = 20U, + .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, + .enableOutputDiv = true, + .lockTolerance = 4U, + .igain = 9U, + .pgain = 5U, + .settlingCount = 8U, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, + .cco_Freq = 355U, +}; +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = +{ + .feedbackDiv = 30, + .referenceDiv = 1, + .outputDiv = 5, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, +}; + +__WEAK void cycfg_ClockStartupError(uint32_t error) +{ + (void)error; /* Suppress the compiler warning */ + while(1); +} +__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit() +{ + Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF); +} +__STATIC_INLINE void Cy_SysClk_ClkBakInit() +{ + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF); +} +__STATIC_INLINE void Cy_SysClk_EcoInit() +{ + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT12, 6, 0x00u, 0x00u, HSIOM_SEL_GPIO); + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT12, 7, 0x00u, 0x00u, HSIOM_SEL_GPIO); + if (CY_SYSCLK_BAD_PARAM == Cy_SysClk_EcoConfigure(24000000U, 18U, 50U, 100U)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_ECO_ERROR); + } + if (CY_SYSCLK_TIMEOUT == Cy_SysClk_EcoEnable(3000u)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_ECO_ERROR); + } +} +__STATIC_INLINE void Cy_SysClk_ClkFastInit() +{ + Cy_SysClk_ClkFastSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_FllInit() +{ + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } +} +__STATIC_INLINE void Cy_SysClk_ClkHf0Init() +{ + Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); +} +__STATIC_INLINE void Cy_SysClk_ClkHf1Init() +{ + Cy_SysClk_ClkHfSetSource(1U, CY_CFG_SYSCLK_CLKHF1_CLKPATH); + Cy_SysClk_ClkHfSetDivider(1U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfEnable(1U); +} +__STATIC_INLINE void Cy_SysClk_ClkHf2Init() +{ + Cy_SysClk_ClkHfSetSource(2U, CY_CFG_SYSCLK_CLKHF2_CLKPATH); + Cy_SysClk_ClkHfSetDivider(2U, CY_SYSCLK_CLKHF_DIVIDE_BY_2); + Cy_SysClk_ClkHfEnable(2U); +} +__STATIC_INLINE void Cy_SysClk_ClkHf3Init() +{ + Cy_SysClk_ClkHfSetSource(3U, CY_CFG_SYSCLK_CLKHF3_CLKPATH); + Cy_SysClk_ClkHfSetDivider(3U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfEnable(3U); +} +__STATIC_INLINE void Cy_SysClk_IloInit() +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_IloEnable(); + Cy_SysClk_IloHibernateOn(true); +} +__STATIC_INLINE void Cy_SysClk_ClkLfInit() +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO); +} +__STATIC_INLINE void Cy_SysClk_ClkPath0Init() +{ + Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath1Init() +{ + Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath2Init() +{ + Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath3Init() +{ + Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath4Init() +{ + Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPeriInit() +{ + Cy_SysClk_ClkPeriSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_Pll0Init() +{ + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } +} +__STATIC_INLINE void Cy_SysClk_ClkSlowInit() +{ + Cy_SysClk_ClkSlowSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_ClkTimerInit() +{ + Cy_SysClk_ClkTimerDisable(); + Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO); + Cy_SysClk_ClkTimerSetDivider(0U); + Cy_SysClk_ClkTimerEnable(); +} +__STATIC_INLINE void Cy_SysClk_WcoInit() +{ + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); + } +} + + +void init_cycfg_platform(void) +{ + /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ + Cy_SysLib_SetWaitStates(false, 150UL); + #if (CY_CFG_PWR_VBAC_SUPPLY == CY_CFG_PWR_VBAC_SUPPLY_VDD) + if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) + { + Cy_SysLib_ResetBackupDomain(); + Cy_SysClk_IloDisable(); + Cy_SysClk_IloInit(); + } + #endif + #ifdef CY_CFG_PWR_ENABLED + /* Configure power mode */ + #if CY_CFG_PWR_USING_LDO + Cy_SysPm_LdoSetVoltage(CY_CFG_PWR_LDO_VOLTAGE); + #else + Cy_SysPm_BuckEnable(CY_CFG_PWR_BUCK_VOLTAGE); + #endif + /* Configure PMIC */ + Cy_SysPm_UnlockPmic(); + #if CY_CFG_PWR_USING_PMIC + Cy_SysPm_PmicEnableOutput(); + #else + Cy_SysPm_PmicDisableOutput(); + #endif + #endif + + /* Reset the core clock path to default and disable all the FLLs/PLLs */ + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkFastSetDivider(0U); + Cy_SysClk_ClkPeriSetDivider(1U); + Cy_SysClk_ClkSlowSetDivider(0U); + Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH1); + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); + + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && + (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) + { + Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); + } + + Cy_SysClk_FllDisable(); + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); + #ifdef CY_IP_MXBLESS + (void)Cy_BLE_EcoReset(); + #endif + + #ifdef CY_CFG_SYSCLK_PLL1_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2); + #endif + + #ifdef CY_CFG_SYSCLK_PLL2_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH3); + #endif + + #ifdef CY_CFG_SYSCLK_PLL3_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH4); + #endif + + #ifdef CY_CFG_SYSCLK_PLL4_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH5); + #endif + + #ifdef CY_CFG_SYSCLK_PLL5_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH6); + #endif + + #ifdef CY_CFG_SYSCLK_PLL6_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH7); + #endif + + #ifdef CY_CFG_SYSCLK_PLL7_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH8); + #endif + + #ifdef CY_CFG_SYSCLK_PLL8_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH9); + #endif + + #ifdef CY_CFG_SYSCLK_PLL9_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH10); + #endif + + #ifdef CY_CFG_SYSCLK_PLL10_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH11); + #endif + + #ifdef CY_CFG_SYSCLK_PLL11_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH12); + #endif + + #ifdef CY_CFG_SYSCLK_PLL12_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH13); + #endif + + #ifdef CY_CFG_SYSCLK_PLL13_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH14); + #endif + + #ifdef CY_CFG_SYSCLK_PLL14_AVAILABLE + (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH15); + #endif + + /* Enable all source clocks */ + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + Cy_SysClk_PiloInit(); + #endif + + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + Cy_SysClk_WcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + Cy_SysClk_ClkLfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED + Cy_SysClk_AltHfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + Cy_SysClk_EcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + Cy_SysClk_ExtClkInit(); + #endif + + /* Configure CPU clock dividers */ + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED + Cy_SysClk_ClkFastInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + Cy_SysClk_ClkPeriInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + Cy_SysClk_ClkSlowInit(); + #endif + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ + Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); + #else + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure Path Clocks */ + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + Cy_SysClk_ClkPath0Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + Cy_SysClk_ClkPath2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + Cy_SysClk_ClkPath3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + Cy_SysClk_ClkPath4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + Cy_SysClk_ClkPath5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED + Cy_SysClk_ClkPath6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED + Cy_SysClk_ClkPath7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED + Cy_SysClk_ClkPath8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED + Cy_SysClk_ClkPath9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED + Cy_SysClk_ClkPath10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED + Cy_SysClk_ClkPath11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED + Cy_SysClk_ClkPath12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED + Cy_SysClk_ClkPath13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED + Cy_SysClk_ClkPath14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED + Cy_SysClk_ClkPath15Init(); + #endif + + /* Configure and enable FLL */ + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + Cy_SysClk_FllInit(); + #endif + + Cy_SysClk_ClkHf0Init(); + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + /* Apply the ClkPath1 user setting */ + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure and enable PLLs */ + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + Cy_SysClk_Pll0Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + Cy_SysClk_Pll1Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL2_ENABLED + Cy_SysClk_Pll2Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL3_ENABLED + Cy_SysClk_Pll3Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL4_ENABLED + Cy_SysClk_Pll4Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL5_ENABLED + Cy_SysClk_Pll5Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL6_ENABLED + Cy_SysClk_Pll6Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL7_ENABLED + Cy_SysClk_Pll7Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL8_ENABLED + Cy_SysClk_Pll8Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL9_ENABLED + Cy_SysClk_Pll9Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL10_ENABLED + Cy_SysClk_Pll10Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL11_ENABLED + Cy_SysClk_Pll11Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL12_ENABLED + Cy_SysClk_Pll12Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL13_ENABLED + Cy_SysClk_Pll13Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL14_ENABLED + Cy_SysClk_Pll14Init(); + #endif + + /* Configure HF clocks */ + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + Cy_SysClk_ClkHf1Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + Cy_SysClk_ClkHf2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + Cy_SysClk_ClkHf3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + Cy_SysClk_ClkHf4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + Cy_SysClk_ClkHf5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED + Cy_SysClk_ClkHf6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED + Cy_SysClk_ClkHf7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED + Cy_SysClk_ClkHf8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED + Cy_SysClk_ClkHf9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED + Cy_SysClk_ClkHf10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED + Cy_SysClk_ClkHf11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED + Cy_SysClk_ClkHf12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED + Cy_SysClk_ClkHf13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED + Cy_SysClk_ClkHf14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED + Cy_SysClk_ClkHf15Init(); + #endif + + /* Configure miscellaneous clocks */ + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED + Cy_SysClk_ClkTimerInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + Cy_SysClk_ClkAltSysTickInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + Cy_SysClk_ClkPumpInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + Cy_SysClk_ClkBakInit(); + #endif + + /* Configure default enabled clocks */ + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + Cy_SysClk_IloInit(); + #else + Cy_SysClk_IloDisable(); + #endif + + #ifndef CY_CFG_SYSCLK_IMO_ENABLED + #error the IMO must be enabled for proper chip operation + #endif + + /* Set accurate flash wait states */ + #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) + Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); + #endif + + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ + SystemCoreClockUpdate(); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.h new file mode 100644 index 0000000000..4feda6f95f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.h @@ -0,0 +1,53 @@ +/******************************************************************************* +* File Name: cycfg_platform.h +* +* Description: +* Platform configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PLATFORM_H) +#define CYCFG_PLATFORM_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_systick.h" +#include "cy_gpio.h" +#include "cy_syspm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000 +#define CY_CFG_PWR_VDDA_MV 3300 +#define CY_CFG_PWR_VDDD_MV 3300 +#define CY_CFG_PWR_VBACKUP_MV 3300 +#define CY_CFG_PWR_VDD_NS_MV 3300 +#define CY_CFG_PWR_VDDIO0_MV 3300 +#define CY_CFG_PWR_VDDIO1_MV 3300 + +void init_cycfg_platform(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PLATFORM_H */