diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_cy8ckit_062_ble.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_cy8ckit_062_ble.c new file mode 100644 index 0000000000..4ac5c10685 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_cy8ckit_062_ble.c @@ -0,0 +1,67 @@ +/***************************************************************************//** +* \file cybsp_cy8ckit_062_ble.c +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CY8CKIT-062-BLE pioneer kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "cybsp_cy8ckit_062_ble.h" +#include "cyhal_implementation.h" +#include "cycfg.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +cy_rslt_t cybsp_init(void) +{ + init_cycfg_system(); + + cy_rslt_t result = CY_RSLT_SUCCESS; + +#ifndef __MBED__ + /* Initialize User LEDs */ + result |= cybsp_led_init(CYBSP_USER_LED1); + result |= cybsp_led_init(CYBSP_USER_LED2); + result |= cybsp_led_init(CYBSP_USER_LED3); + result |= cybsp_led_init(CYBSP_USER_LED4); + result |= cybsp_led_init(CYBSP_USER_LED5); + /* Initialize User Buttons */ + result |= cybsp_btn_init(CYBSP_USER_BTN1); + + CY_ASSERT(CY_RSLT_SUCCESS == result); +#endif + +#if defined(CYBSP_RETARGET_ENABLED) + /* Initialize retargetting stdio to 'DEBUG_UART' peripheral */ + if (CY_RSLT_SUCCESS == result) + { + result = cybsp_retarget_init(); + } +#endif + + return result; +} + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_cy8ckit_062_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_cy8ckit_062_ble.h new file mode 100644 index 0000000000..77a24cb2b2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_cy8ckit_062_ble.h @@ -0,0 +1,76 @@ +/***************************************************************************//** +* \file cybsp_cy8ckit_062_ble.h +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CY8CKIT-062-BLE pioneer kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_bsp_cy8ckit_062_ble CY8CKIT-062-BLE +* \ingroup group_bsp +* \{ +* The PSoC 6 BLE Pioneer Kit is a low-cost hardware platform +* that enables design and debug of the PSoC 63 MCU (CY8C6347BZI-BLD53). +* +*
Kit Features:
+* +* +*
Kit Contents:
+* +* +* \defgroup group_bsp_cy8ckit_062_ble_macros Macros +* \defgroup group_bsp_cy8ckit_062_ble_functions Functions +* \defgroup group_bsp_cy8ckit_062_ble_enums Enumerated Types +*/ + +#pragma once + +#include "cybsp_api_core.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \cond INTERNAL */ + +// HAL HW configuration data +extern cyhal_qspi_t cybsp_qspi; +extern cyhal_uart_t cybsp_bt_uart; +extern cyhal_uart_t cybsp_uart; +extern cyhal_i2c_t cybsp_i2c; +extern cyhal_rtc_t cybsp_rtc; + +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +/** \} group_bsp_cy8ckit_062_ble */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_types.h new file mode 100644 index 0000000000..6669595f2b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_types.h @@ -0,0 +1,159 @@ +/***************************************************************************//** +* \file CY8CKIT-062-BLE/cybsp_types.h +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CY8CKIT-062-BLE pioneer kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_bsp_cy8ckit_062_ble CY8CKIT-062-BLE +* \ingroup group_bsp +* \{ +* \defgroup group_bsp_cy8ckit_062_ble_macros Macros +* \defgroup group_bsp_cy8ckit_062_ble_enums Enumerated Types +*/ + +#pragma once + +#include "cyhal.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_bsp_cy8ckit_062_ble_macros +* \{ +*/ + +// Generic signal names +/** Pin: WCO input */ +#define CYBSP_WCO_IN P0_0 +/** Pin: WCO output */ +#define CYBSP_WCO_OUT P0_1 + +/** Pin: UART RX */ +#define CYBSP_DEBUG_UART_RX P5_0 +/** Pin: UART TX */ +#define CYBSP_DEBUG_UART_TX P5_1 + +/** Pin: I2C SCL */ +#define CYBSP_I2C_SCL P6_0 +/** Pin: I2C SDA */ +#define CYBSP_I2C_SDA P6_1 + +/** Pin: SWO */ +#define CYBSP_SWO P6_4 +/** Pin: SWDIO */ +#define CYBSP_SWDIO P6_6 +/** Pin: SWDCK */ +#define CYBSP_SWDCK P6_7 + +/** Pin: CapSesnse TX */ +#define CYBSP_CSD_TX P1_0 +/** Pin: CapSesnse CINA */ +#define CYBSP_CINA P7_1 +/** Pin: CapSesnse CINB */ +#define CYBSP_CINB P7_2 +/** Pin: CapSesnse CMOD */ +#define CYBSP_CMOD P7_7 +/** Pin: CapSesnse Button 0 */ +#define CYBSP_CSD_BTN0 P8_1 +/** Pin: CapSesnse Button 1 */ +#define CYBSP_CSD_BTN1 P8_2 +/** Pin: CapSesnse Slider 0 */ +#define CYBSP_CSD_SLD0 P8_3 +/** Pin: CapSesnse Slider 1 */ +#define CYBSP_CSD_SLD1 P8_4 +/** Pin: CapSesnse Slider 2 */ +#define CYBSP_CSD_SLD2 P8_5 +/** Pin: CapSesnse Slider 3 */ +#define CYBSP_CSD_SLD3 P8_6 +/** Pin: CapSesnse Slider 4 */ +#define CYBSP_CSD_SLD4 P8_7 + +/** Pin: QUAD SPI SS */ +#define CYBSP_QSPI_SS P11_2 +/** Pin: QUAD SPI D3 */ +#define CYBSP_QSPI_D3 P11_3 +/** Pin: QUAD SPI D2 */ +#define CYBSP_QSPI_D2 P11_4 +/** Pin: QUAD SPI D1 */ +#define CYBSP_QSPI_D1 P11_5 +/** Pin: QUAD SPI D0 */ +#define CYBSP_QSPI_D0 P11_6 +/** Pin: QUAD SPI SCK */ +#define CYBSP_QSPI_SCK P11_7 + +/** \} group_bsp_cy8ckit_062_ble_macros */ + +/** +* \addtogroup group_bsp_cy8ckit_062_ble_enums +* \{ +*/ + +/** Enum defining the different states for the LED. */ +typedef enum +{ + CYBSP_LED_STATE_ON = 0, + CYBSP_LED_STATE_OFF = 1, +} cybsp_led_state_t; + +/** Enum defining the different states for a button. */ +typedef enum +{ + CYBSP_BTN_PRESSED = 0, + CYBSP_BTN_OFF = 1, +} cybsp_btn_state_t; + +/** Enum defining the different LED pins on the board. */ +typedef enum +{ + CYBSP_LED9 = P13_7, + CYBSP_LED8 = P1_5, + CYBSP_LED_RGB_RED = P0_3, + CYBSP_LED_RGB_GREEN = P1_1, + CYBSP_LED_RGB_BLUE = P11_1, + + CYBSP_USER_LED1 = CYBSP_LED8, + CYBSP_USER_LED2 = CYBSP_LED9, + CYBSP_USER_LED3 = CYBSP_LED_RGB_RED, + CYBSP_USER_LED4 = CYBSP_LED_RGB_GREEN, + CYBSP_USER_LED5 = CYBSP_LED_RGB_BLUE, + CYBSP_USER_LED = CYBSP_USER_LED1, +} cybsp_led_t; + +/** Enum defining the different button pins on the board. */ +typedef enum +{ + CYBSP_SW2 = P0_4, + + CYBSP_USER_BTN1 = CYBSP_SW2, + CYBSP_USER_BTN = CYBSP_USER_BTN1, +} cybsp_btn_t; + +/** \} group_bsp_cy8ckit_062_ble_enums */ + +#if defined(__cplusplus) +} +#endif + +/** \} group_bsp_cy8ckit_062_ble */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index 3319e48c9b..a23e6e13f6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4_dual.scat -;* \version 2.40 +;* \version 2.50 ;* ;* Linker file for the ARMCC. ;* @@ -78,7 +78,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -#define Stack_Size MBED_BOOT_STACK_SIZE +#define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. ; Use these defines to specify the memory regions available for allocation. @@ -190,7 +190,7 @@ LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE } ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -Stack_Size + ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE { * (STACK) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index b5e7d90d53..0cfd336d6e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.ld -* \version 2.40 +* \version 2.50 * * Linker file for the GNU C compiler. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf index 4be7d38872..1fd2e3e578 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.icf -* \version 2.40 +* \version 2.50 * * Linker file for the IAR compiler. * @@ -154,8 +154,9 @@ if (!isdefinedsymbol(__STACK_SIZE)) { define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; } +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x20000; + define symbol __ICFEDIT_size_heap__ = 0x400; } else { define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; } @@ -183,7 +184,7 @@ define block RAM_BSS {readwrite section .bss}; define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; define block RO {first section .intvec, readonly}; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S index ac9a099f33..75747c4fac 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S @@ -1,5 +1,5 @@ ;/**************************************************************************//** -; * @file startup_psoc6_01_cm4.s +; * @file startup_psoc6_01_cm4.S ; * @brief CMSIS Core Device Startup File for ; * ARMCM4 Device Series ; * @version V5.00 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6.h index 99f86760b3..53bc71262c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.40 +* \version 2.50 * * \brief Device system header file. * @@ -320,6 +320,11 @@ * Reason for Change * * +* 2.50 +* Updated assembler files, C files, linker scripts. +* Dynamic allocated HEAP size for Arm Compiler 6, IAR 8. +* +* * 2.40 * Updated assembler files, C files, linker scripts. * Added Arm Compiler 6 support. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6_cm4.c index c040a5c713..a5408385ee 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.40 +* \version 2.50 * * The device system-source file. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c new file mode 100644 index 0000000000..0c66057ed7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c @@ -0,0 +1,1346 @@ +/***************************************************************************//** +* \file cy_sdio.c +* \version 1.00 +* +* \brief +* This file provides the source code to the API for the UDB based SDIO driver. +* +******************************************************************************* +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SDIO_HOST.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#ifdef SEMAPHORE +#include "cyabs_rtos.h" + +#define NEVER_TIMEOUT ( (uint32_t)0xffffffffUL ) +static cy_semaphore_t sdio_transfer_finished_semaphore; +#endif + + +/*Globals Needed for DMA */ +/*DMA channel structures*/ +cy_stc_dma_channel_config_t respChannelConfig; +cy_stc_dma_channel_config_t cmdChannelConfig; +cy_stc_dma_channel_config_t writeChannelConfig; +cy_stc_dma_channel_config_t readChannelConfig; + +/*DMA Descriptor structures*/ +cy_stc_dma_descriptor_t respDesr; +cy_stc_dma_descriptor_t cmdDesr; +cy_stc_dma_descriptor_t readDesr0; +cy_stc_dma_descriptor_t readDesr1; +cy_stc_dma_descriptor_t writeDesr0; +cy_stc_dma_descriptor_t writeDesr1; + +/*Global structure used for data keeping*/ +stc_sdio_gInternalData_t gstcInternalData; + +/*Global CRC table*/ +static uint8_t crcTable[256]; + +/*Global values used for DMA interrupt*/ +static uint32_t yCountRemainder; +static uint32_t yCounts; + +static uint32_t udb_initialized = 0; + + +/******************************************************************************* +* Function Name: SDIO_Init +****************************************************************************//** +* +* Initializes the SDIO hardware, and register the callback +* +* \param pfuCb +* Pointer to structure that holds pointers to callback function +* see \ref stc_sdio_irq_cb_t. +* +* \note +* Sets SD Clock Frequency to 400 kHz +*******************************************************************************/ +void SDIO_Init(stc_sdio_irq_cb_t* pfuCb) +{ + if ( !udb_initialized ) + { + udb_initialized = 1; + SDIO_Host_Config_UDBs(); + } + + /*Set Number of Blocks to 1 initially, this will be updated later*/ + SDIO_SetNumBlocks(1); + + /*Enable SDIO ISR*/ + NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); + + /*Enable the Status Reg to generate an interrupt*/ + SDIO_STATUS_AUX_CTL |= (0x10); + + /*Set the priority of DW0, DW1, M4 and M0. DW1 should have highest*/ + /*First clear priority of all*/ + (* (reg32 *)CYREG_PROT_SMPU_MS0_CTL) &= ~0x0300; + (* (reg32 *)CYREG_PROT_SMPU_MS2_CTL) &= ~0x0300; + (* (reg32 *)CYREG_PROT_SMPU_MS3_CTL) &= ~0x0300; + (* (reg32 *)CYREG_PROT_SMPU_MS14_CTL) &= ~0x0300; + + /*Next set priority DW1 = 0, DW0 = 1, M4 = 2, M0 =3*/ + (* (reg32 *)CYREG_PROT_SMPU_MS2_CTL) |= 0x0100; + (* (reg32 *)CYREG_PROT_SMPU_MS0_CTL) |= 0x0200; + (* (reg32 *)CYREG_PROT_SMPU_MS14_CTL) |= 0x0200; + + /*Setup callback for card interrupt*/ + gstcInternalData.pstcCallBacks.pfnCardIntCb = pfuCb->pfnCardIntCb; + + /*Setup the DMA channels*/ + SDIO_SetupDMA(); + + /*Initialize CRC*/ + SDIO_Crc7Init(); + + /*Enable all the bit counters*/ + SDIO_CMD_BIT_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; + SDIO_WRITE_CRC_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; + SDIO_CRC_BIT_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; + SDIO_BYTE_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; + + /*Set block byte count to 64, this will be changed later */ + SDIO_SetBlockSize(64); + + /*Set the read and write FIFOs to use the half full status*/ + (*(reg32 *) SDIO_HOST_bSDIO_Write_DP__DP_AUX_CTL_REG) |= 0x0c; + (*(reg32 *) SDIO_HOST_bSDIO_Read_DP__DP_AUX_CTL_REG) |= 0x0c; + + /*Set clock to 400k, and enable it*/ + SDIO_SetSdClkFrequency(400000); + SDIO_EnableIntClock(); + SDIO_EnableSdClk(); + + /*Initalize the semaphore*/ +#ifdef SEMAPHORE + cy_rtos_init_semaphore( &sdio_transfer_finished_semaphore, 1, 1 ); +#endif +} + + +/******************************************************************************* +* Function Name: SDIO_SendCommand +****************************************************************************//** +* +* Send an SDIO command, don't wait for it to finish. +* +* \param pstcCmdConfig +* Command configuration structure. See \ref stc_sdio_cmd_config_t. +* +*******************************************************************************/ +void SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig) +{ + /*buffer to hold command data*/ + static uint8_t u8cmdBuf[6]; + + /*Populate buffer*/ + /*Element 0 is the Most Significant Byte*/ + u8cmdBuf[0] = SDIO_HOST_DIR | pstcCmdConfig->u8CmdIndex; + u8cmdBuf[1] = (uint8_t)((pstcCmdConfig->u32Argument & 0xff000000)>>24); + u8cmdBuf[2] = (uint8_t)((pstcCmdConfig->u32Argument & 0x00ff0000)>>16); + u8cmdBuf[3] = (uint8_t)((pstcCmdConfig->u32Argument & 0x0000ff00)>>8); + u8cmdBuf[4] = (uint8_t)((pstcCmdConfig->u32Argument & 0x000000ff)); + + /*calculate the CRC of above data*/ + u8cmdBuf[5] = SDIO_CalculateCrc7(u8cmdBuf, 5); + /*Shift it up by 1 as the CRC takes the upper 7 bits of the last byte of the cmd*/ + u8cmdBuf[5] = u8cmdBuf[5] << 1; + /*Add on the end bit*/ + u8cmdBuf[5] = u8cmdBuf[5] | SDIO_CMD_END_BIT; + + /*Load the first byte into A0*/ + SDIO_CMD_COMMAND_A0_REG = u8cmdBuf[0]; + + /*If a response is expected setup DMA to receive the response*/ + if (pstcCmdConfig->bResponseRequired == true) + { + /*Clear the flag in hardware that says skip response*/ + SDIO_CONTROL_REG &= ~SDIO_CTRL_SKIP_RESPONSE; + + /*Set the destination address*/ + respDesr.dst = (uint32_t)(pstcCmdConfig->pu8ResponseBuf); + + /*Initialize the channel with the descriptor*/ + Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL, &respDesr); + + /*Enable the channel*/ + Cy_DMA_Channel_Enable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL); + } + else + { + /*Set the skip flag*/ + SDIO_CONTROL_REG |= SDIO_CTRL_SKIP_RESPONSE; + } + + /*Setup the Command DMA*/ + /*Set the source address*/ + cmdDesr.src = (uint32_t)(&u8cmdBuf[1]); + + /*Initialize the channel with the descriptor*/ + Cy_DMA_Channel_SetDescriptor(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL , &cmdDesr); + + /*Enable the channel*/ + Cy_DMA_Channel_Enable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); +} + + +/******************************************************************************* +* Function Name: SDIO_GetResponse +****************************************************************************//** +* +* Takes a 6 byte response buffer, and extracts the 32 bit response, also checks +* for index errors, CRC errors, and end bit errors. +* +* \param bCmdIndexCheck +* If True check for index errors +* +* \param bCmdCrcCheck +* If True check for CRC errors +* +* \param u8cmdIdx +* Command index, used for checking the index error +* +* \param pu32Response +* location to store 32 bit response +* +* \param pu8ResponseBuf +* buffer that holds the 6 bytes of response data +* +* \return +* \ref en_sdio_result_t +* +*******************************************************************************/ +en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, uint8_t u8cmdIdx, uint32_t* pu32Response, uint8_t *pu8ResponseBuf) +{ + /*Function return*/ + en_sdio_result_t enRet = Error; + /*variable to hold temporary CRC*/ + uint8_t u8TmpCrc; + /*temporary response*/ + uint32_t u32TmpResponse; + + /*Zero out the pu32Response*/ + *pu32Response = 0; + + /*Check if the CRC needs to be checked*/ + if (bCmdCrcCheck) + { + /*Calculate the CRC*/ + u8TmpCrc = SDIO_CalculateCrc7(pu8ResponseBuf, 5); + + /*Shift calculated CRC up by one bit to match bit position of CRC*/ + u8TmpCrc = u8TmpCrc << 1; + + /*Compare calculated CRC with received CRC*/ + if ((u8TmpCrc & 0xfe) != (pu8ResponseBuf[5] & 0xfe)) + { + enRet |= CommandCrcError; + } + } + + /*Check if the index needs to be checked*/ + if (bCmdIndexCheck) + { + /*The index resides in the lower 6 bits of the 1st byte of the response*/ + if ((u8cmdIdx != (pu8ResponseBuf[0] & 0x3f))) + { + enRet |= CommandIdxError; + } + } + + /*Check the end bit*/ + if (!(pu8ResponseBuf[5] & 0x01)) + { + enRet |= CommandEndError; + } + + if (enRet == Error) + { + /*If we get here then there were no errors with the command populate the response*/ + u32TmpResponse = pu8ResponseBuf[1]; + u32TmpResponse = u32TmpResponse << 8; + u32TmpResponse |= pu8ResponseBuf[2]; + u32TmpResponse = u32TmpResponse << 8; + u32TmpResponse |= pu8ResponseBuf[3]; + u32TmpResponse = u32TmpResponse << 8; + u32TmpResponse |= pu8ResponseBuf[4]; + + *pu32Response = u32TmpResponse; + + enRet = Ok; + } + + return enRet; +} + + +/******************************************************************************* +* Function Name: SDIO_InitDataTransfer +****************************************************************************//** +* +* Configure the data channel for a data transfer. For a write this doesn't start +* the write, that must be done separately after the response is received. +* +* \param stc_sdio_data_config_t +* Data configuration structure. See \ref stc_sdio_data_config_t +* +* +*******************************************************************************/ +void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig) +{ + /*hold size of entire transfer*/ + uint32_t dataSize; + + /*calculate how many bytes are going to be sent*/ + dataSize = pstcDataConfig->u16BlockSize * pstcDataConfig->u16BlockCount; + + /*Set the block size and number of blocks*/ + SDIO_SetBlockSize(pstcDataConfig->u16BlockSize); + SDIO_SetNumBlocks((pstcDataConfig->u16BlockCount) - 1); + + /*If we are reading data setup the DMA to receive read data*/ + if (pstcDataConfig->bRead == true) + { + /*First disable the write channel*/ + Cy_DMA_Channel_Disable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL ); + + /*Clear any pending interrupts in the DMA*/ + Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL); + + NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + + /*setup the destination addresses*/ + readDesr0.dst = (uint32_t)(pstcDataConfig->pu8Data); + readDesr1.dst = (uint32_t)((pstcDataConfig->pu8Data) + 1024); + + /*Setup the X control to transfer two 16 bit elements per transfer for a total of 4 bytes + Remember X increment is in terms of data element size which is 16, thus why it is 1*/ + readDesr0.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 1); + readDesr1.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 1); + + /*The X Loop will always transfer 4 bytes. The FIFO will only trigger the + DMA when it has 4 bytes to send (2 in each F0 and F1). There is a possibility + that there could be 3,2,or 1 bytes still in the FIFOs. To solve this the DMA + will be SW triggered when hardware indicates all bytes have been received. + This leads to an extra 1, 2 or 3 bytes being received. So the RX buffer needs to + be at least 3 bytes bigger than the data size. + + Since the X loop is setup to 4, the maximum number of Y loop is 256 so one + descriptor can transfer 1024 bytes. Two descriptors can transfer 2048 bytes. + Since we don't know the maximum number of bytes to read only two descriptors will + be used. If more than 2048 bytes need to be read then and interrupt will be enabled + The descriptor that is not currently running will be updated in the ISR to receive + more data. + + So there are three conditions to check: + 1) Are we sending less than or equal to 1024 bytes if so use one descriptor + 2) Are we sending greater than 1024, but less than or equal to 2048, use two descriptors + 3) Greater than 2048, use two descriptors and the ISR + */ + + if (dataSize <= 1024) + { + /*Setup one descriptor*/ + /*Y Increment is 2 because the X is transfer 2 data elements (which are 16 bits)*/ + readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1) / 4) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + + /*Setup descriptor 0 to point to nothing and disable*/ + readDesr0.nextPtr = 0; + readDesr0.ctl |= 0x01000000; + + /*Disable Interrupt*/ + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + else if (dataSize <=2048) + { + /*setup the first descriptor for 1024, then setup 2nd descriptor for remainder*/ + + readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1025) / 4) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + + + /*Setup descriptor 0 to point to descriptor 1*/ + readDesr0.nextPtr = (uint32_t)(&readDesr1); + /*Setup descriptor 1 to point to nothing and disable */ + readDesr1.nextPtr = 0; + + /*Don't disable after first descriptor*/ + readDesr0.ctl &= ~0x01000000; + /*Disable after second descriptor*/ + readDesr1.ctl |= 0x01000000; + + /*Disable Interrupt*/ + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + else /*dataSize must be greater than 2048*/ + { + /*These are for the ISR, Need to figure out how many "descriptors" + need to run, and the yCount for last descriptor. + Example: dataSize = 2080 + yCounts = 2, yCountRemainder = 7 (send 8 more set of 4)*/ + yCounts = (dataSize / 1024); + + /*the Ycount register is a +1 register meaning 0 = 1. I However, need to know when there is + no remainder so I increase the value to make sure there is a remainder and decrement in the ISR*/ + yCountRemainder = (((dataSize - (yCounts * 1024)) + 3 ) / 4); + + /*Setup the Y Ctrl for both descriptors*/ + readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + + /*Setup descriptor 0 to point to descriptor 1*/ + readDesr0.nextPtr = (uint32_t)(&readDesr1); + /*Setup descriptor 1 to point to descriptor 0*/ + readDesr1.nextPtr = (uint32_t)(&readDesr0); + + /*Don't disable the channel on completion of descriptor*/ + readDesr0.ctl &= ~0x01000000; + readDesr1.ctl &= ~0x01000000; + + /*Decrement yCounts by 2 since we already have 2 descriptors setup*/ + yCounts -= 2; + + /*Enable DMA interrupt*/ + NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + + /*Initialize the channel with the first descriptor*/ + Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL , &readDesr0); + + /*Enable the channel*/ + Cy_DMA_Channel_Enable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); + + /*Set the flag in the control register to enable the read*/ + SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_READ; + } + + /*Otherwise it is a write*/ + else + { + /*First disable the Read channel*/ + Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); + + /*Clear any pending interrupts in the DMA*/ + Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); + + NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + + /*setup the SRC addresses*/ + writeDesr0.src = (uint32_t)(pstcDataConfig->pu8Data); + writeDesr1.src = (uint32_t)((pstcDataConfig->pu8Data) + 1024); + + + /*Setup the X control to transfer two 16 bit elements per transfer for a total of 4 bytes + Remember X increment is in terms of data element size which is 16, thus why it is 1*/ + writeDesr0.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 1); + writeDesr1.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 1); + + if (dataSize <= 1024) + { + /*Setup one descriptor*/ + /*Y Increment is 2 because the X is transfer 2 data elements (which are 16 bits)*/ + writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1) / 4) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + + /*Setup descriptor 0 to point to nothing and disable*/ + writeDesr0.nextPtr = 0; + writeDesr0.ctl |= 0x01000000; + + /*Disable Interrupt*/ + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + } + else if (dataSize <=2048) + { + /*setup the first descriptor for 1024, then setup 2nd descriptor for remainder*/ + + writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1025) / 4) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + + + /*Setup descriptor 0 to point to descriptor 1*/ + writeDesr0.nextPtr = (uint32_t)(&writeDesr1); + /*Setup descriptor 1 to point to nothing and disable */ + writeDesr1.nextPtr = 0; + + /*Don't disable after first descriptor*/ + writeDesr0.ctl &= ~0x01000000; + /*Disable after second descriptor*/ + writeDesr1.ctl |= 0x01000000; + + /*Disable Interrupt*/ + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + } + else /*dataSize must be greater than 2048*/ + { + /*These are for the ISR, Need to figure out how many "descriptors" + need to run, and the yCount for last descriptor. + Example: dataSize = 2080 + yCounts = 2, yCountRemainder = 7 (send 8 more set of 4)*/ + yCounts = (dataSize / 1024); + + /*the Ycount register is a +1 register meaning 0 = 1. I However, need to know when there is + no remainder so I increase the value to make sure there is a remainder and decrement in the ISR*/ + yCountRemainder = (((dataSize - (yCounts * 1024)) + 3 ) / 4); + + /*Setup the Y Ctrl for both descriptors*/ + writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + + /*Setup descriptor 0 to point to descriptor 1*/ + writeDesr0.nextPtr = (uint32_t)(&writeDesr1); + /*Setup descriptor 1 to point to descriptor 0*/ + writeDesr1.nextPtr = (uint32_t)(&writeDesr0); + + /*Don't disable the channel on completion of descriptor*/ + writeDesr0.ctl &= ~0x01000000; + writeDesr1.ctl &= ~0x01000000; + + /*Decrement yCounts by 2 since we already have 2 descriptors setup*/ + yCounts -= 2; + + /*Enable DMA interrupt*/ + NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + } + + /*Initialize the channel with the first descriptor*/ + Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL , &writeDesr0); + } +} + + +/******************************************************************************* +* Function Name: SDIO_SendCommandAndWait +****************************************************************************//** +* +* This function sends a command on the command channel and waits for that +* command to finish before returning. If a Command 53 is issued this function +* will handle all of the data transfer and wait to return until it is done. +* +* \param pstcCmd +* Pointer command configuration structure see \ref stc_sdio_cmd_t. +* +* \return +* \ref en_sdio_result_t +* +*******************************************************************************/ +en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) +{ + /*Store the command and data configurations*/ + stc_sdio_cmd_config_t stcCmdConfig; + stc_sdio_data_config_t stcDataConfig; + +#ifdef SEMAPHORE + en_sdio_result_t result; +#endif + + /*variable used for holding timeout value*/ +#ifndef SEMAPHORE + uint32_t u32Timeout = 0; +#endif + +#ifndef SEMAPHORE_CMD + uint32_t u32CmdTimeout = 0; +#endif + + /*Returns from various function calls*/ + en_sdio_result_t enRet = Error; + en_sdio_result_t enRetTmp = Ok; + + /*Hold value of if these checks are needed*/ + uint8_t bCmdIndexCheck; + uint8_t bCmdCrcCheck; + static uint8_t u8responseBuf[6]; + + /*Clear statuses*/ + gstcInternalData.stcEvents.u8CmdComplete = 0; + gstcInternalData.stcEvents.u8TransComplete = 0; + gstcInternalData.stcEvents.u8CRCError = 0; + + /*Setup the command configuration*/ + stcCmdConfig.u8CmdIndex = (uint8_t)pstcCmd->u32CmdIdx; + stcCmdConfig.u32Argument = pstcCmd->u32Arg; + + /*Determine the type of response and if we need to do any checks*/ + /*Command 0 and 8 have no response, so don't wait for one*/ + if (pstcCmd->u32CmdIdx == 0 || pstcCmd->u32CmdIdx == 8) + { + bCmdIndexCheck = false; + bCmdCrcCheck = false; + stcCmdConfig.bResponseRequired = false; + stcCmdConfig.pu8ResponseBuf = NULL; + } + + /*Command 5's response doesn't have a CRC or index, so don't check*/ + else if (pstcCmd->u32CmdIdx == 5) + { + bCmdIndexCheck = false; + bCmdCrcCheck = false; + stcCmdConfig.bResponseRequired = true; + stcCmdConfig.pu8ResponseBuf = u8responseBuf; + } + /*Otherwise check everything*/ + else + { + bCmdIndexCheck = true; + bCmdCrcCheck = true; + stcCmdConfig.bResponseRequired = true; + stcCmdConfig.pu8ResponseBuf = u8responseBuf; + } + + /*Check if the command is 53, if it is then setup the data transfer*/ + if (pstcCmd->u32CmdIdx == 53) + { + /*Set the number of blocks in the global struct*/ + stcDataConfig.u16BlockCount = (uint16_t)pstcCmd->u16BlockCnt; + /*Set the size of the data transfer*/ + stcDataConfig.u16BlockSize = (uint16_t)pstcCmd->u16BlockSize; + /*Set the direction are we reading or writing*/ + stcDataConfig.bRead = pstcCmd->bRead; + /*Set the pointer for the data*/ + stcDataConfig.pu8Data = pstcCmd->pu8Data; + + /*Get the data Transfer Ready*/ + SDIO_InitDataTransfer(&stcDataConfig); + + /*Set bit saying this was a CMD_53*/ + SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_INT; + } + + /*Send the command*/ + SDIO_SendCommand(&stcCmdConfig); + + /*Wait for the command to finish*/ + do + { + //TODO: Use RTOS timeout + u32CmdTimeout++; + enRetTmp = SDIO_CheckForEvent(SdCmdEventCmdDone); + + } while ((enRetTmp != Ok) && (u32CmdTimeout < SDIO_CMD_TIMEOUT)); + + + if (u32CmdTimeout == SDIO_CMD_TIMEOUT) + { + enRet |= CMDTimeout; + } + else /*CMD Passed*/ + { + /*If a response is expected check it*/ + if (stcCmdConfig.bResponseRequired == true) + { + enRetTmp = SDIO_GetResponse(bCmdCrcCheck, bCmdIndexCheck, (uint8_t)pstcCmd->u32CmdIdx, pstcCmd->pu32Response, u8responseBuf); + if (enRetTmp != Ok) + { + enRet |= enRetTmp; + } + else /*Response good*/ + { + /*if it was command 53, check the response to ensure there was no error*/ + if ((pstcCmd->u32CmdIdx) == 53) + { + /*Make sure none of the error bits are set*/ + if (*(pstcCmd->pu32Response) & 0x0000cf00) + { + enRet |= ResponseFlagError; + } + else /*CMD53 Response good*/ + { + /*If it was command 53 and it was a write enable the write*/ + if (pstcCmd->bRead == false && enRet == Error) + { + Cy_DMA_Channel_Disable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL ); + Cy_DMA_Channel_Disable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); + Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); + + /*Set the flag in the control register to enable the write*/ + Cy_DMA_Channel_Enable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); + /*Enable the channel*/ + Cy_SysLib_DelayCycles(35); + SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_WRITE; + } + +#ifndef SEMAPHORE + /*Wait for the transfer to finish*/ + do + { + + u32Timeout++; + enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone); + + } while (!((enRetTmp == Ok) || (enRetTmp == DataCrcError) || (u32Timeout >= SDIO_DAT_TIMEOUT))); + + /*if it was a read it is possible there is still extra data hanging out, trigger the + DMA again. This can result in extra data being transfered so the read buffer should be + 3 bytes bigger than needed*/ + if (pstcCmd->bRead == true) + { + Cy_TrigMux_SwTrigger((uint32_t)SDIO_HOST_Read_DMA_DW__TR_IN, 2); + } + + if (u32Timeout == SDIO_DAT_TIMEOUT) +#else + result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false ); + enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone); + + /* if it was a read it is possible there is still extra data hanging out, trigger the + DMA again. This can result in extra data being transfered so the read buffer should be + 3 bytes bigger than needed*/ + if (pstcCmd->bRead == true) + { + Cy_TrigMux_SwTrigger((uint32_t)SDIO_HOST_Read_DMA_DW__TR_IN, 2); + } + + if (result != Ok) +#endif + { + enRet |= DataTimeout; + } + + if (enRetTmp == DataCrcError) + { + enRet |= DataCrcError; + } + }/*CMD53 response good*/ + }/*Not a CMD53*/ + } /*Response Good*/ + } /*No Response Required, thus no CMD53*/ + } /*CMD Passed*/ + + +#ifndef SEMAPHORE + u32Timeout = 0; +#endif + + /*If there were no errors then indicate transfer was okay*/ + if (enRet == Error) + { + enRet = Ok; + } + + /*reset CmdTimeout value*/ + u32CmdTimeout = 0; + + /*Always Reset on exit to clean up*/ + Cy_DMA_Channel_Disable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL ); + Cy_DMA_Channel_Disable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); + Cy_DMA_Channel_Disable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL ); + Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); + /*No longer a CMD_53*/ + SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_INT | SDIO_CTRL_ENABLE_WRITE | SDIO_CTRL_ENABLE_READ); + SDIO_Reset(); + + return enRet; +} + + +/******************************************************************************* +* Function Name: SDIO_CheckForEvent +****************************************************************************//** +* +* Checks to see if a specific event has occurred such a command complete or +* transfer complete. +* +* \param enEventType +* The type of event to check for. See \ref en_sdio_event_t. +* +* \return +* \ref en_sdio_result_t +* +*******************************************************************************/ +en_sdio_result_t SDIO_CheckForEvent(en_sdio_event_t enEventType) +{ + en_sdio_result_t enRet = Error; + + /*Disable Interrupts while modifying the global*/ + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); + + /*Switch the event to check*/ + switch ( enEventType ) + { + /*If the command is done clear the flag*/ + case SdCmdEventCmdDone: + if (gstcInternalData.stcEvents.u8CmdComplete > 0) + { + gstcInternalData.stcEvents.u8CmdComplete = 0; + enRet = Ok; + } + break; + + /*If the transfer is done check for CRC Error and clear the flag*/ + case SdCmdEventTransferDone: + if (gstcInternalData.stcEvents.u8TransComplete > 0) + { + gstcInternalData.stcEvents.u8TransComplete = 0; + enRet = Ok; + } + /*Check for CRC error and set flags*/ + if (gstcInternalData.stcEvents.u8CRCError > 0) + { + enRet = DataCrcError; + gstcInternalData.stcEvents.u8CRCError = 0; + } + break; + } + + /*Re-enable Interrupts*/ + NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); + return enRet; +} + + +/******************************************************************************* +* Function Name: SDIO_CalculateCrc7 +****************************************************************************//** +* +* Calculate the 7 bit CRC for the command channel +* +* \param pu8Data +* Data to calculate CRC on +* +* \param u8Size +* Number of bytes to calculate CRC on +* +* \return +* CRC +* +* \note +* This code was copied from +* http://www.barrgroup.com/Embedded-Systems/How-To/CRC-Calculation-C-Code +* +*******************************************************************************/ +uint8_t SDIO_CalculateCrc7(uint8_t* pu8Data, uint8_t u8Size) +{ + uint8_t data; + uint8_t remainder = 0; + uint32_t byte; + + for(byte = 0; byte < u8Size; ++byte) + { + data = pu8Data[byte] ^ remainder; + remainder = crcTable[data] ^ (remainder << 8); + } + + return (remainder>>1); +} + + +/******************************************************************************* +* Function Name: SDIO_Crc7Init +****************************************************************************//** +* +* Initialize 7-bit CRC Table +* +* \note +* This code was copied from +* http://www.barrgroup.com/Embedded-Systems/How-To/CRC-Calculation-C-Code +* +*******************************************************************************/ +void SDIO_Crc7Init(void) +{ + uint8_t remainder; + uint8_t bit; + uint32_t dividend; + + for(dividend = 0; dividend < 256; ++dividend) + { + remainder = dividend; + + for(bit = 8; bit > 0; --bit) + { + if (remainder & SDIO_CRC_UPPER_BIT) + { + remainder = (remainder << 1) ^ SDIO_CRC7_POLY; + } + else + { + remainder = (remainder << 1); + } + } + + crcTable[dividend] = (remainder); + } +} + + +/******************************************************************************* +* Function Name: SDIO_SetBlockSize +****************************************************************************//** +* +* Sets the size of each block +* +* \param u8ByteCount +* Size of the block +* +*******************************************************************************/ +void SDIO_SetBlockSize(uint8_t u8ByteCount) +{ + SDIO_BYTE_COUNT_REG = u8ByteCount; +} + + +/******************************************************************************* +* Function Name: SDIO_SetNumBlocks +****************************************************************************//** +* +* Sets the number of blocks to send +* +* \param u8ByteCount +* Size of the block +* +*******************************************************************************/ +void SDIO_SetNumBlocks(uint8_t u8BlockCount) +{ + SDIO_DATA_BLOCK_COUNTER_A0_REG = u8BlockCount; + SDIO_DATA_BLOCK_COUNTER_D0_REG = u8BlockCount; + /*The one is used so that we can do 256 bytes*/ + SDIO_DATA_BLOCK_COUNTER_A1_REG = 1; + SDIO_DATA_BLOCK_COUNTER_D1_REG = 1; +} + + +/******************************************************************************* +* Function Name: SDIO_EnableIntClock +****************************************************************************//** +* +* Enable Internal clock for the block +* +*******************************************************************************/ +void SDIO_EnableIntClock(void) +{ + SDIO_CONTROL_REG |= SDIO_CTRL_INT_CLK; + Cy_SysClk_PeriphEnableDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM); +} + + +/******************************************************************************* +* Function Name: SDIO_DisableIntClock +****************************************************************************//** +* +* Enable Disable clock for the block +* +*******************************************************************************/ +void SDIO_DisableIntClock(void) +{ + SDIO_CONTROL_REG &= ~SDIO_CTRL_INT_CLK; + Cy_SysClk_PeriphDisableDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM); +} + + +/******************************************************************************* +* Function Name: SDIO_EnableSdClk +****************************************************************************//** +* +* Enable SD Clock out to pin +* +*******************************************************************************/ +void SDIO_EnableSdClk(void) +{ + SDIO_CONTROL_REG |= SDIO_CTRL_SD_CLK; +} + + +/******************************************************************************* +* Function Name: SDIO_DisableSdClk +****************************************************************************//** +* +* Disable SD Clock out to the pin +* +*******************************************************************************/ +void SDIO_DisableSdClk(void) +{ + SDIO_CONTROL_REG &= ~SDIO_CTRL_SD_CLK; +} + + +/******************************************************************************* +* Function Name: SDIO_SetSdClkFrequency +****************************************************************************//** +* +* Sets the frequency of the SD Clock +* +* \param u32SdClkFreqHz +* Frequency of SD Clock in Hz. +* +* \note +* Only an integer divider is used, so the desired frequency may not be meet +*******************************************************************************/ +void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz) +{ + uint16_t u16Div; + u16Div = Cy_SysClk_ClkPeriGetFrequency() / u32SdClkFreqHz; + Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, (u16Div-1)); +} + + +/******************************************************************************* +* Function Name: SDIO_SetupDMA +****************************************************************************//** +* +* Configures the DMA for the SDIO block +* +*******************************************************************************/ +void SDIO_SetupDMA(void) +{ + /*Set the number of bytes to send*/ + SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config.xCount = (SDIO_NUM_RESP_BYTES - 1); + /*Set the destination address*/ + SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config.dstAddress = (void*)SDIO_CMD_COMMAND_PTR; + + /*Initialize descriptor for cmd channel*/ + Cy_DMA_Descriptor_Init(&cmdDesr, &SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config); + + /*Set flag to disable descriptor when done*/ + cmdDesr.ctl |= 0x01000000; + + /*Configure channel*/ + /*CMD channel can be preempted, and has lower priority*/ + cmdChannelConfig.descriptor = &cmdDesr; + cmdChannelConfig.preemptable = 1; + cmdChannelConfig.priority = 1; + cmdChannelConfig.enable = 0u; + + /*Configure Channel with initial Settings*/ + Cy_DMA_Channel_Init(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL, &cmdChannelConfig); + + /*Enable DMA block*/ + Cy_DMA_Enable(SDIO_HOST_CMD_DMA_HW); + + /*Set the number of bytes to receive*/ + SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config.xCount = SDIO_NUM_RESP_BYTES; + /*Set the source address*/ + SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config.srcAddress = (void*)SDIO_CMD_RESPONSE_PTR; + + /*Initialize descriptor for response channel*/ + Cy_DMA_Descriptor_Init(&respDesr, &SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config); + + /*Set flag to disable descriptor when done*/ + respDesr.ctl |= 0x01000000; + + /*Configure channel*/ + /*response channel can be preempted, and has lower priority*/ + respChannelConfig.descriptor = &respDesr; + respChannelConfig.preemptable = 1; + respChannelConfig.priority = 1; + respChannelConfig.enable = 0u; + + /*Configure Channel with initial Settings*/ + Cy_DMA_Channel_Init(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL, &respChannelConfig); + /*Enable DMA block*/ + Cy_DMA_Enable(SDIO_HOST_Resp_DMA_HW); + + /*Set the destination address*/ + SDIO_HOST_Write_DMA_Write_DMA_Desc_config.dstAddress = (void*)SDIO_DAT_WRITE_PTR; + + /*Initialize descriptor for write channel*/ + Cy_DMA_Descriptor_Init(&writeDesr0, &SDIO_HOST_Write_DMA_Write_DMA_Desc_config); + Cy_DMA_Descriptor_Init(&writeDesr1, &SDIO_HOST_Write_DMA_Write_DMA_Desc_config); + + /*Configure channel*/ + /*write channel cannot be preempted, and has highest priority*/ + writeChannelConfig.descriptor = &writeDesr0; + writeChannelConfig.preemptable = 0; + writeChannelConfig.priority = 0; + writeChannelConfig.enable = 0u; + + /*Configure Channel with initial Settings*/ + Cy_DMA_Channel_Init(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL, &writeChannelConfig); + + /*Enable the interrupt*/ + Cy_DMA_Channel_SetInterruptMask(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL,CY_DMA_INTR_MASK); + + /*Enable DMA block*/ + Cy_DMA_Enable(SDIO_HOST_Write_DMA_HW); + + /*Set the source address*/ + SDIO_HOST_Read_DMA_Read_DMA_Desc_config.srcAddress = (void*)SDIO_DAT_READ_PTR; + /*Initialize descriptor for read channel*/ + Cy_DMA_Descriptor_Init(&readDesr0, &SDIO_HOST_Read_DMA_Read_DMA_Desc_config); + Cy_DMA_Descriptor_Init(&readDesr1, &SDIO_HOST_Read_DMA_Read_DMA_Desc_config); + + /*Configure channel*/ + /*read channel cannot be preempted, and has highest priority*/ + readChannelConfig.descriptor = &readDesr0; + readChannelConfig.preemptable = 0; + readChannelConfig.priority = 0; + readChannelConfig.enable = 0u; + + /*Configure Channel with initial Settings*/ + Cy_DMA_Channel_Init(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL, &readChannelConfig); + + /*Enable the interrupt*/ + Cy_DMA_Channel_SetInterruptMask(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL,CY_DMA_INTR_MASK); + + /*Enable DMA block*/ + Cy_DMA_Enable(SDIO_HOST_Read_DMA_HW); +} + + +/******************************************************************************* +* Function Name: SDIO_Reset +****************************************************************************//** +* +* Reset the SDIO interface +* +*******************************************************************************/ +void SDIO_Reset(void) +{ + /*Control register is in pulse mode, so this just pulses the reset*/ + SDIO_CONTROL_REG |= (SDIO_CTRL_RESET_DP); +} + + +/******************************************************************************* +* Function Name: SDIO_EnableChipInt +****************************************************************************//** +* +* Enables the SDIO Chip Int by setting the mask bit +* +*******************************************************************************/ +void SDIO_EnableChipInt(void) +{ + SDIO_STATUS_INT_MSK |= SDIO_STS_CARD_INT; +} + + +/******************************************************************************* +* Function Name: SDIO_DisableChipInt +****************************************************************************//** +* +* Enables the SDIO Chip Int by setting the mask bit +* +*******************************************************************************/ +void SDIO_DisableChipInt(void) +{ + SDIO_STATUS_INT_MSK &= ~SDIO_STS_CARD_INT; +} + + +/******************************************************************************* +* Function Name: SDIO_IRQ +****************************************************************************//** +* +* SDIO interrupt, checks for events, and calls callbacks +* +*******************************************************************************/ +void SDIO_IRQ(void) +{ + uint8_t u8Status; + + /*first read the status register*/ + u8Status = SDIO_STATUS_REG; + + /*Check card interrupt*/ + if (u8Status & SDIO_STS_CARD_INT ) + { + if (NULL != gstcInternalData.pstcCallBacks.pfnCardIntCb) + { + gstcInternalData.pstcCallBacks.pfnCardIntCb(); + } + } + + /*If the command is complete set the flag*/ + if (u8Status & SDIO_STS_CMD_DONE) + { + gstcInternalData.stcEvents.u8CmdComplete++; + } + + /*Check if a write is complete*/ + if (u8Status & SDIO_STS_WRITE_DONE ) + { + + /*Clear the Write flag and CMD53 flag*/ + SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_WRITE | SDIO_CTRL_ENABLE_INT); + + /*Check if the CRC status return was bad*/ + if (u8Status & SDIO_STS_CRC_ERR ) + { + /*CRC was bad, set the flag*/ + gstcInternalData.stcEvents.u8CRCError++; + } + /*set the done flag*/ +#ifdef SEMAPHORE + cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true ); +#else + gstcInternalData.stcEvents.u8TransComplete++; +#endif + } + + /*Check if a read is complete*/ + if (u8Status & SDIO_STS_READ_DONE) + { + /*Clear the read flag*/ + SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_READ| SDIO_CTRL_ENABLE_INT); + + /*check the CRC*/ + if (u8Status & SDIO_STS_CRC_ERR) + { + /*CRC was bad, set the flag*/ + gstcInternalData.stcEvents.u8CRCError++; + } + /*Okay we're done so set the done flag*/ +#ifdef SEMAPHORE + cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true ); +#else + gstcInternalData.stcEvents.u8TransComplete++; +#endif + } + + NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); +} + + +void SDIO_READ_DMA_IRQ(void) +{ + /*Shouldn't have to change anything unless it is the last descriptor*/ + + /*If the current descriptor is 0, then change descriptor 1*/ + if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL) == &readDesr0) + { + /*We need to increment the destination address every time*/ + readDesr1.dst += 2048; + + /*If this is the last descriptor*/ + if ((yCounts == 1) && (yCountRemainder == 0)) + { + /* In this case all we need to change is the next descriptor and disable*/ + readDesr1.nextPtr = 0; + readDesr1.ctl |= 0x01000000; + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + else if (yCounts == 0 && (yCountRemainder > 0)) + { + /*change next descriptor, and disable*/ + readDesr1.nextPtr = 0; + readDesr1.ctl |= 0x01000000; + /*Also change the yCount*/ + readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder-1)) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + } + + /*If the current descriptor is 1, then change descriptor 0*/ + if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL) == &readDesr1) + { + /*We need to increment the destination address everytime*/ + readDesr0.dst += 2048; + + /*If this is the last descriptor*/ + if ((yCounts == 1) && (yCountRemainder == 0)) + { + /* In this case all we need to change is the next descriptor and disable*/ + readDesr0.nextPtr = 0; + readDesr0.ctl |= 0x01000000; + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + else if (yCounts == 0 && (yCountRemainder > 0)) + { + /*change next descriptor, and disable*/ + readDesr0.nextPtr = 0; + readDesr0.ctl |= 0x01000000; + /*Also change the yCount*/ + readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder-1)) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + } + + /*Clear the interrupt*/ + Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL); + /*decrement y counts*/ + yCounts--; +} + + +void SDIO_WRITE_DMA_IRQ(void) +{ + /*We shouldn't have to change anything unless it is the last descriptor*/ + + /*If the current descriptor is 0, then change descriptor 1*/ + if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL) == &writeDesr0) + { + /*We also need to increment the destination address every-time*/ + writeDesr1.src += 2048; + + /*If this is the last descriptor*/ + if ((yCounts == 1) && (yCountRemainder == 0)) + { + /* In this case all we need to change is the next descriptor and disable*/ + writeDesr1.nextPtr = 0; + writeDesr1.ctl |= 0x01000000; + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + + } + else if (yCounts == 0 && (yCountRemainder > 0)) + { + /*change next descriptor, and disable*/ + writeDesr1.nextPtr = 0; + writeDesr1.ctl |= 0x01000000; + /*Also change the yCount*/ + writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder -1)) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + } + } + + /*If the current descriptor is 1, then change descriptor 0*/ + if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL) == &writeDesr1) + { + /*We also need to increment the destination address*/ + writeDesr0.src += 2048; + /*If this is the last descriptor*/ + if ((yCounts == 1) && (yCountRemainder == 0)) + { + /* In this case all we need to change is the next descriptor and disable*/ + writeDesr0.nextPtr = 0; + writeDesr0.ctl |= 0x01000000; + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + } + else if (yCounts == 0 && (yCountRemainder > 0)) + { + /*change next descriptor, and disable*/ + writeDesr0.nextPtr = 0; + writeDesr0.ctl |= 0x01000000; + /*Also change the yCount*/ + writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder -1)) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + } + } + + /*Clear the interrupt*/ + Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); + yCounts--; +} + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h new file mode 100644 index 0000000000..f63649e38c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h @@ -0,0 +1,404 @@ +/***************************************************************************//** +* \file SDIO_HOST.h +* \version 1.00 +* +* \brief +* This file provides types definition, constants and function definition for +* the SDIO driver. +* +******************************************************************************* +* \copyright +* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +******************************************************************************* +* \addtogroup group_udb_sdio_changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+*******************************************************************************/ + +/** +* \defgroup group_udb_sdio UDB_SDIO +* \ingroup group_bsp +* \{ +* SDIO - Secure Digital Input Output Is a standard for communicating with various + external devices such as Wifi and bluetooth devices. +* \{ +* \defgroup group_udb_sdio_general_description General Description +* \defgroup group_udb_sdio_changelog Changelog +* \} +* \defgroup group_udb_sdio_API API Reference +* \{ +* \defgroup group_udb_sdio_macros Macros +* \defgroup group_udb_sdio_functions Functions +* \defgroup group_udb_sdio_data_structures Data Structures +* \} +*/ + +/** +* \addtogroup group_udb_sdio_general_description +* \section group_udb_sdio_section_overview Overview +* This driver is currently designed to only support communication with certain +* Broadcom Wifi and Bluetooth chipsets, it is not designed to work with a general +* SDIO card, or even and SD card. Consult TDU#315 for information on limitations +* +* \section group_udb_sdio_section_configuration_considerations Configuration Considerations +* Features: +* * Always Four Wire Mode +* * Supports Card Interrupt +* * Uses DMA for command and data transfer +** +* \section group_udb_sdio_section_more_information More Information +* +* \} group_udb_sdio_general_description +*/ + +#if !defined(CY_SDIO_H) +#define CY_SDIO_H + +#include "SDIO_HOST_cfg.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*************************************** +* API Constants +***************************************/ + +/** +* \addtogroup group_udb_sdio_macros +* \{ +*/ + +#define SDIO_CMD_TIMEOUT (100000u) /**< Value used for firmware timeout*/ +#define SDIO_DAT_TIMEOUT (500000u) /**< Value used for firmware timeout*/ +#define SDIO_SRC_CLK_FREQ_HZ (10000000u) /**< Frequency of CLK_PERI*/ +#define SDIO_ENABLE_CNT (0x20u) /**< Bit to set in Aux Ctrl reg to enable 7 bit counters.*/ + +/*! +\defgroup group_sdio_cmd_constants Constants for the command channel +*/ +/* @{*/ +#define SDIO_HOST_DIR (0x40u) /**< Direction bit set in command */ +#define SDIO_CMD_END_BIT (0x01u) /**< End bit set in command*/ +#define SDIO_NUM_CMD_BYTES (6u) /**< Number of command bytes to send*/ +#define SDIO_NUM_RESP_BYTES (6u) /**< Number of response bytes to receive*/ +/*@} group_sdio_cmd_constants */ + +/*! +\defgroup group_sdio_ctrl_reg SDIO control register bits +*/ +/* @{*/ +#define SDIO_CTRL_INT_CLK (0x01u) /**< Enable the internal clock running the SDIO block*/ +#define SDIO_CTRL_SD_CLK (0x02u) /**< Enable the the SD Clock*/ +#define SDIO_CTRL_ENABLE_WRITE (0x04u) /**< Enable a write, should not be set if ENABLE_READ is set*/ +#define SDIO_CTRL_ENABLE_READ (0x08u) /**< Enable a read, should not be set if ENABLE_WRITE is set*/ +#define SDIO_CTRL_SKIP_RESPONSE (0x10u) /**< If set no response is required for the command*/ +#define SDIO_CTRL_RESET (0x20u) /**< If set the SDIO interface is reset*/ +#define SDIO_CTRL_RESET_DP (0x40u) /**< If set the SDIO interface is reset*/ +#define SDIO_CTRL_ENABLE_INT (0x80u) /**< Enables logic to detect card interrupt*/ +/*@} group_sdio_ctrl_reg */ + +/*! +\defgroup group_sdio_status_reg SDIO status register bits +*/ +/* @{*/ +#define SDIO_STS_CMD_DONE (0x01u) /**< The command is done*/ +#define SDIO_STS_WRITE_DONE (0x02u) /**< All data for a write has been sent*/ +#define SDIO_STS_READ_DONE (0x04u) /**< All data for a read has been read*/ +#define SDIO_STS_CRC_ERR (0x08u) /**< A CRC error was detected during a read or write*/ +#define SDIO_STS_CMD_IDLE (0x10u) /**< The command channel is idle*/ +#define SDIO_STS_DAT_IDLE (0x20u) /**< The data channel is idle*/ +#define SDIO_STS_CARD_INT (0x40u) /**< The SDIO card indicated an interrupt by driving DAT[1] low*/ +/*@} group_sdio_status_reg */ + +/*! +\defgroup group_sdio_crc Constants for 7bit CRC for command +*/ +/* @{*/ +#define SDIO_CRC7_POLY (0x12u) /**< Value of CRC polynomial*/ +#define SDIO_CRC_UPPER_BIT (0x80u) /**< Upper bit to test if it is high*/ +/*@} group_sdio_crc */ + +/** \} group_udb_sdio_macros */ + + +/*************************************** +* Type Definitions +***************************************/ + +/** +* \addtogroup group_udb_sdio_data_structures +* \{ +*/ + +/** +* Create a type for the card interrupt call back +*/ +typedef void (* sdio_card_int_cb_t)(void); + +/** +* \brief This enum is used when checking for specific events +*/ +typedef enum en_sdio_event +{ + SdCmdEventCmdDone = (1u), /**< Check to see if a command is done*/ + SdCmdEventTransferDone = (2u) /**< Check to see if a transfer is done*/ + +}en_sdio_event_t; + +/** +* \brief Used to indicate the result of a function +*/ +typedef enum en_sdio_result +{ + Ok = 0x00, /**< No error*/ + Error = 0x01, /**< Non-specific error code*/ + CommandCrcError = 0x02, /**< There was a CRC error on the Command/Response*/ + CommandIdxError = 0x04, /**< The index for the command didn't match*/ + CommandEndError = 0x08, /**< There was an end bit error on the command*/ + DataCrcError = 0x10, /**< There was a data CRC Error*/ + CMDTimeout = 0x20, /**< The command didn't finish before the timeout period was over*/ + DataTimeout = 0x40, /**< The data didn't finish before the timeout period was over*/ + ResponseFlagError = 0x80 /**< There was an error in the response flag for command 53*/ + +} en_sdio_result_t; + +/** +* \brief Flags used to indicate an event occurred, set in the interrupt, cleared in the check events function +*/ +typedef struct stc_sdcmd_event_flag +{ + uint8_t u8CmdComplete; /**< If non-zero a command has completed*/ + uint8_t u8TransComplete; /**< If non-zero a transfer has completed*/ + uint8_t u8CRCError; /**< If non-zero a CRC error was detected in a data transfer*/ + +}stc_sdio_event_flag_t; + +/** +* \brief Holds pointers to callback functions +*/ +typedef struct stc_sdio_irq_cb +{ + sdio_card_int_cb_t pfnCardIntCb; /**< Pointer to card interrupt callback function*/ +}stc_sdio_irq_cb_t; + +/** +* \brief Global structure used to hold data from interrupt and other functions +*/ +typedef struct stc_sdio_gInternalData +{ + stc_sdio_irq_cb_t pstcCallBacks; /**< Holds pointers to all the call back functions*/ + stc_sdio_event_flag_t stcEvents; /**< Holds all of the event count flags, set in interrupt used in check events*/ +}stc_sdio_gInternalData_t; + +/** +* \brief structure used for configuring command +*/ +typedef struct stc_sdio_cmd_config +{ + uint8_t u8CmdIndex; /**< Command index*/ + uint32_t u32Argument; /**< The argument of command */ + uint8_t bResponseRequired; /**< TRUE: A Response is required*/ + uint8_t *pu8ResponseBuf; /**< Pointer to location to store response*/ + +}stc_sdio_cmd_config_t; + +/** +* \brief structure used for the data channel +*/ +typedef struct stc_sdio_data_config +{ + uint8_t bRead; /**< TRUE: Read, FALSE: write*/ + uint16_t u16BlockSize; /**< Block size*/ + uint16_t u16BlockCount; /**< Holds the number of blocks to send*/ + uint8_t *pu8Data; /**< Pointer data buffer*/ + +}stc_sdio_data_config_t; + +/** +* \brief structure used for configuring command and data +*/ +typedef struct stc_sdio_cmd +{ + uint32_t u32CmdIdx; /**< Command index*/ + uint32_t u32Arg; /**< The argument of command*/ + uint32_t *pu32Response; /**< Pointer to location to store response*/ + uint8_t *pu8Data; /**< Pointer data buffer*/ + uint8_t bRead; /**< TRUE: Read, FALSE: write*/ + uint16_t u16BlockCnt; /**< Number of blocks to send*/ + uint16_t u16BlockSize; /**< Block size*/ +}stc_sdio_cmd_t; + +/** \} group_udb_sdio_data_structures */ + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_udb_sdio_functions +* \{ +*/ + +/** \cond INTERNAL */ + +/* Main functions*/ +void SDIO_Init(stc_sdio_irq_cb_t* pfuCb); +en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd); +void SDIO_EnableIntClock(void); +void SDIO_DisableIntClock(void); +void SDIO_EnableSdClk(void); +void SDIO_DisableSdClk(void); +void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz); +void SDIO_Reset(void); +void SDIO_EnableChipInt(void); +void SDIO_DisableChipInt(void); + +/*Low Level Functions*/ +void SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig); +en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, uint8_t u8CmdIdx, uint32_t* pu32Response, uint8_t* pu8ResponseBuf); +void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig); +en_sdio_result_t SDIO_CheckForEvent(en_sdio_event_t enEventType); +uint8_t SDIO_CalculateCrc7(uint8_t* pu8Data, uint8_t pu8Size); +void SDIO_SetBlockSize(uint8_t u8ByteCount); +void SDIO_SetNumBlocks(uint8_t u8BlockCount); +en_sdio_result_t SDIO_CheckReadCRC(void); + +/*DMA setup function*/ +void SDIO_SetupDMA(void); + +/*Interrupt Function*/ +void SDIO_IRQ(void); +void SDIO_READ_DMA_IRQ(void); +void SDIO_WRITE_DMA_IRQ(void); + +void SDIO_Crc7Init(void); + +/** \endcond */ + +/** \} group_udb_sdio_functions */ + + +/*************************************** +* Hardware Registers +***************************************/ + +/** \cond INTERNAL */ + +#define SDIO_CONTROL_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG) + +#define SDIO_CONTROL_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG) + +#define SDIO_STATUS_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_StatusReg__STATUS_REG) + +#define SDIO_STATUS_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_StatusReg__STATUS_REG) + +#define SDIO_STATUS_INT_MSK (* (reg8*) \ +SDIO_HOST_bSDIO_StatusReg__MASK_REG) + +#define SDIO_STATUS_AUX_CTL (* (reg8 *) \ +SDIO_HOST_bSDIO_StatusReg__STATUS_AUX_CTL_REG) + +#define SDIO_CMD_BIT_CNT_CONTROL_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_CMD_BIT_CNT_CONTROL_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_WRITE_CRC_CNT_CONTROL_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_WRITE_CRC_CNT_CONTROL_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_BYTE_CNT_CONTROL_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_BYTE_CNT_CONTROL_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_CRC_BIT_CNT_CONTROL_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_CRC_BIT_CNT_CONTROL_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_DATA_BLOCK_COUNTER_A0_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__A0_REG) + +#define SDIO_DATA_BLOCK_COUNTER_A0_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__A0_REG) + +#define SDIO_DATA_BLOCK_COUNTER_D0_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__D0_REG) + +#define SDIO_DATA_BLOCK_COUNTER_D0_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__D0_REG) + +#define SDIO_DATA_BLOCK_COUNTER_A1_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__A1_REG) + +#define SDIO_DATA_BLOCK_COUNTER_A1_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__A1_REG) + +#define SDIO_DATA_BLOCK_COUNTER_D1_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__D1_REG) + +#define SDIO_DATA_BLOCK_COUNTER_D1_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__D1_REG) + +#define SDIO_CMD_COMMAND_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_CMD__F0_REG) + +#define SDIO_CMD_COMMAND_A0_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_CMD__A0_REG) + +#define SDIO_CMD_COMMAND_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_CMD__F0_REG) + +#define SDIO_CMD_RESPONSE_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_CMD__F1_REG) + +#define SDIO_CMD_RESPONSE_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_CMD__F1_REG) + +#define SDIO_DAT_WRITE_REG (* (reg16 *) \ +SDIO_HOST_bSDIO_Write_DP__F0_F1_REG) + +#define SDIO_DAT_WRITE_PTR ( (reg16 *) \ +SDIO_HOST_bSDIO_Write_DP__F0_F1_REG) + +#define SDIO_DAT_READ_REG (* (reg16 *) \ +SDIO_HOST_bSDIO_Read_DP__F0_F1_REG) + +#define SDIO_DAT_READ_PTR ( (reg16 *) \ +SDIO_HOST_bSDIO_Read_DP__F0_F1_REG) + +#define SDIO_BYTE_COUNT_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_byteCounter__PERIOD_REG) + +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +#endif /* (CY_SDIO_H) */ + +/** \} group_udb_sdio */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c new file mode 100644 index 0000000000..fced70b846 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c @@ -0,0 +1,1018 @@ +#include "SDIO_HOST_cfg.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/***************************CMD DMA Config Struct****************************/ +cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config = +{ + .retrigger = CY_DMA_RETRIG_16CYC, + .interruptType = CY_DMA_1ELEMENT, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_1ELEMENT, + .dataSize = CY_DMA_BYTE, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_1D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 1L, + .dstXincrement = 0L, + .xCount = 5UL, + .srcYincrement = 0L, + .dstYincrement = 0L, + .yCount = 1UL, + .nextDescriptor = NULL +}; + +cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL +}; + +/***************************Read DMA Config Struct****************************/ +cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config = +{ + .retrigger = CY_DMA_RETRIG_IM, + .interruptType = CY_DMA_DESCR, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_X_LOOP, + .dataSize = CY_DMA_HALFWORD, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_2D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 0L, + .dstXincrement = 2L, + .xCount = 10UL, + .srcYincrement = 0L, + .dstYincrement = 10L, + .yCount = 2UL, + .nextDescriptor = NULL +}; + +cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL +}; + +/***************************Resp DMA Config Struct****************************/ +cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config = +{ + .retrigger = CY_DMA_RETRIG_IM, + .interruptType = CY_DMA_1ELEMENT, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_1ELEMENT, + .dataSize = CY_DMA_BYTE, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_1D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 0L, + .dstXincrement = 1L, + .xCount = 6UL, + .srcYincrement = 0L, + .dstYincrement = 0L, + .yCount = 1UL, + .nextDescriptor = NULL +}; + +cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL +}; + +/***************************Write DMA Config Struct****************************/ +cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config = +{ + .retrigger = CY_DMA_RETRIG_4CYC, + .interruptType = CY_DMA_DESCR, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_X_LOOP, + .dataSize = CY_DMA_HALFWORD, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_2D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 2L, + .dstXincrement = 0L, + .xCount = 10UL, + .srcYincrement = 10L, + .dstYincrement = 0L, + .yCount = 2UL, + .nextDescriptor = NULL +}; + +cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL +}; + + + +/***************UDB Config code *****************/ + +#define CY_CFG_BASE_ADDR_COUNT 12u + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) + #define CYPACKED + #define CYPACKED_ATTR __attribute__ ((packed)) + #define CY_CFG_UNUSED __attribute__ ((unused)) + + +#elif defined(__ICCARM__) + #include + + #define CYPACKED __packed + #define CYPACKED_ATTR + #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") + + +#else + #error Unsupported toolchain +#endif + + +#ifndef CYCODE + #define CYCODE +#endif +#ifndef CYFAR + #define CYFAR +#endif + + +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n); +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n) +{ + (void)memset(s, 0, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} + +CYPACKED typedef struct +{ + uint8 offset; + uint8 value; +} CYPACKED_ATTR cy_cfg_addrvalue_t; + + +/******************************************************************************* +* Function Name: cfg_write_bytes32 +******************************************************************************** +* Summary: +* This function is used for setting up the chip configuration areas that +* contain relatively sparse data. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ + +static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]); +static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]) +{ + /* For 32-bit little-endian architectures */ + uint32 i, j = 0u; + for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) + { + uint32 baseAddr = addr_table[i]; + uint8 count = (uint8)baseAddr; + baseAddr &= 0xFFFFFF00u; + while (count != 0u) + { + CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value); + j++; + count--; + } + } +} + +static const uint32 CYCODE cy_cfg_addr_table[] = +{ + 0x40340002u, /* Base address: 0x40340000 Count: 2 */ + 0x4034010Au, /* Base address: 0x40340100 Count: 10 */ + 0x40340301u, /* Base address: 0x40340300 Count: 1 */ + 0x40340405u, /* Base address: 0x40340400 Count: 5 */ + 0x40342466u, /* Base address: 0x40342400 Count: 102 */ + 0x40342632u, /* Base address: 0x40342600 Count: 50 */ + 0x4034282Bu, /* Base address: 0x40342800 Count: 43 */ + 0x40342A5Eu, /* Base address: 0x40342A00 Count: 94 */ + 0x40347005u, /* Base address: 0x40347000 Count: 5 */ + 0x40347102u, /* Base address: 0x40347100 Count: 2 */ + 0x40347202u, /* Base address: 0x40347200 Count: 2 */ + 0x40347804u, /* Base address: 0x40347800 Count: 4 */ +}; + +static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = +{ + {0x18u, 0xFFu}, + {0x1Du, 0x01u}, + {0x00u, 0x10u}, + {0x04u, 0x88u}, + {0x09u, 0x02u}, + {0x10u, 0x10u}, + {0x14u, 0x88u}, + {0x1Du, 0x01u}, + {0x20u, 0x10u}, + {0x24u, 0x88u}, + {0x28u, 0x10u}, + {0x2Cu, 0x88u}, + {0x15u, 0x40u}, + {0x04u, 0x07u}, + {0x14u, 0x47u}, + {0x1Cu, 0x2Fu}, + {0x20u, 0x03u}, + {0x28u, 0x0Fu}, + {0x01u, 0x8Eu}, + {0x03u, 0x70u}, + {0x05u, 0x04u}, + {0x0Au, 0x01u}, + {0x0Du, 0x04u}, + {0x11u, 0x60u}, + {0x13u, 0x80u}, + {0x15u, 0x04u}, + {0x18u, 0x02u}, + {0x19u, 0xD0u}, + {0x1Bu, 0x23u}, + {0x21u, 0x01u}, + {0x23u, 0x20u}, + {0x25u, 0xD0u}, + {0x27u, 0x2Fu}, + {0x2Du, 0x10u}, + {0x2Eu, 0x01u}, + {0x2Fu, 0x48u}, + {0x30u, 0x01u}, + {0x31u, 0xE0u}, + {0x34u, 0x02u}, + {0x35u, 0x1Fu}, + {0x3Bu, 0x02u}, + {0x3Du, 0x22u}, + {0x3Eu, 0x11u}, + {0x40u, 0x52u}, + {0x41u, 0x01u}, + {0x44u, 0x06u}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Cu, 0x12u}, + {0x4Du, 0x5Cu}, + {0x4Eu, 0x78u}, + {0x5Cu, 0x04u}, + {0x5Du, 0x0Cu}, + {0x5Eu, 0x0Cu}, + {0x63u, 0x09u}, + {0x64u, 0x50u}, + {0x65u, 0xA8u}, + {0x69u, 0x1Cu}, + {0x6Au, 0x58u}, + {0x6Bu, 0xA1u}, + {0x6Du, 0x10u}, + {0x70u, 0x10u}, + {0x71u, 0x1Du}, + {0x86u, 0x20u}, + {0x8Au, 0x20u}, + {0x8Bu, 0x02u}, + {0x8Cu, 0x20u}, + {0x90u, 0xBAu}, + {0x92u, 0x04u}, + {0x94u, 0x08u}, + {0x96u, 0x11u}, + {0x98u, 0x78u}, + {0x9Au, 0x02u}, + {0x9Cu, 0x18u}, + {0x9Eu, 0xC4u}, + {0xA3u, 0x01u}, + {0xA4u, 0x08u}, + {0xA6u, 0x10u}, + {0xA8u, 0xFEu}, + {0xABu, 0x01u}, + {0xADu, 0x02u}, + {0xAEu, 0x20u}, + {0xB0u, 0x01u}, + {0xB2u, 0x18u}, + {0xB3u, 0x01u}, + {0xB4u, 0x06u}, + {0xB5u, 0x02u}, + {0xB6u, 0xE0u}, + {0xBAu, 0x08u}, + {0xBFu, 0x14u}, + {0xC0u, 0x52u}, + {0xC1u, 0x01u}, + {0xC4u, 0x06u}, + {0xC5u, 0xB0u}, + {0xC7u, 0x40u}, + {0xC8u, 0x22u}, + {0xC9u, 0xFFu}, + {0xCAu, 0xFFu}, + {0xCBu, 0xFFu}, + {0xCCu, 0x13u}, + {0xCDu, 0x5Cu}, + {0xCEu, 0x77u}, + {0xD4u, 0xDEu}, + {0xD5u, 0x40u}, + {0xD6u, 0x4Bu}, + {0xD7u, 0x04u}, + {0xDCu, 0x0Cu}, + {0xDDu, 0x04u}, + {0xDEu, 0x0Cu}, + {0xDFu, 0x0Cu}, + {0xE3u, 0x09u}, + {0xE4u, 0x50u}, + {0xE5u, 0xA8u}, + {0xE9u, 0x1Cu}, + {0xEAu, 0x58u}, + {0xEBu, 0xA1u}, + {0xEDu, 0x10u}, + {0xF0u, 0x10u}, + {0xF1u, 0x1Du}, + {0x00u, 0x08u}, + {0x04u, 0x01u}, + {0x05u, 0x07u}, + {0x08u, 0x01u}, + {0x0Au, 0x08u}, + {0x0Fu, 0x05u}, + {0x12u, 0x01u}, + {0x14u, 0x10u}, + {0x16u, 0x01u}, + {0x18u, 0x01u}, + {0x1Au, 0x04u}, + {0x1Eu, 0x0Eu}, + {0x1Fu, 0x06u}, + {0x20u, 0x01u}, + {0x22u, 0x02u}, + {0x25u, 0x03u}, + {0x2Au, 0x10u}, + {0x2Bu, 0x01u}, + {0x32u, 0x10u}, + {0x36u, 0x0Fu}, + {0x37u, 0x07u}, + {0x3Cu, 0x80u}, + {0x40u, 0x36u}, + {0x41u, 0x01u}, + {0x42u, 0x20u}, + {0x44u, 0x05u}, + {0x45u, 0xFBu}, + {0x46u, 0xC0u}, + {0x47u, 0xE0u}, + {0x48u, 0x2Bu}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Cu, 0x02u}, + {0x4Fu, 0x0Cu}, + {0x50u, 0x08u}, + {0x51u, 0x10u}, + {0x5Cu, 0x0Cu}, + {0x5Du, 0x0Cu}, + {0x5Eu, 0x0Cu}, + {0x63u, 0x09u}, + {0x65u, 0x08u}, + {0x68u, 0xC0u}, + {0x6Cu, 0x10u}, + {0x6Du, 0x11u}, + {0x6Eu, 0x40u}, + {0x6Fu, 0x01u}, + {0x71u, 0x10u}, + {0x72u, 0x50u}, + {0x73u, 0xA8u}, + {0x82u, 0x08u}, + {0x84u, 0x07u}, + {0x86u, 0xF8u}, + {0x8Cu, 0x0Eu}, + {0x8Eu, 0xD1u}, + {0x92u, 0x21u}, + {0x96u, 0x01u}, + {0x98u, 0x04u}, + {0x9Eu, 0x04u}, + {0xA0u, 0x04u}, + {0xA4u, 0xB9u}, + {0xA6u, 0x06u}, + {0xA8u, 0x89u}, + {0xAAu, 0x72u}, + {0xAEu, 0x60u}, + {0xB0u, 0x80u}, + {0xB2u, 0x7Fu}, + {0xBAu, 0x08u}, + {0xBCu, 0x08u}, + {0xBEu, 0x01u}, + {0xC0u, 0x42u}, + {0xC1u, 0x05u}, + {0xC4u, 0x06u}, + {0xC6u, 0x40u}, + {0xC7u, 0xB0u}, + {0xC8u, 0x28u}, + {0xC9u, 0xFFu}, + {0xCAu, 0xFFu}, + {0xCBu, 0xFFu}, + {0xCCu, 0x13u}, + {0xCDu, 0x5Cu}, + {0xCEu, 0x77u}, + {0xDCu, 0x0Cu}, + {0xDEu, 0x0Cu}, + {0xE3u, 0x09u}, + {0xE4u, 0x50u}, + {0xE5u, 0xA8u}, + {0xE9u, 0x1Cu}, + {0xEAu, 0x58u}, + {0xEBu, 0xA1u}, + {0xEDu, 0x10u}, + {0xF0u, 0x10u}, + {0xF1u, 0x1Du}, + {0x03u, 0x40u}, + {0x09u, 0x10u}, + {0x0Cu, 0x2Au}, + {0x0Du, 0x30u}, + {0x0Eu, 0x01u}, + {0x0Fu, 0x0Au}, + {0x15u, 0x30u}, + {0x17u, 0x0Au}, + {0x1Du, 0x0Cu}, + {0x1Eu, 0x14u}, + {0x20u, 0x02u}, + {0x22u, 0x29u}, + {0x23u, 0x35u}, + {0x24u, 0x30u}, + {0x25u, 0x03u}, + {0x28u, 0x03u}, + {0x29u, 0x20u}, + {0x2Au, 0x28u}, + {0x2Cu, 0x0Cu}, + {0x2Du, 0x0Au}, + {0x2Fu, 0x30u}, + {0x30u, 0x01u}, + {0x31u, 0x70u}, + {0x32u, 0x30u}, + {0x33u, 0x0Cu}, + {0x34u, 0x0Cu}, + {0x35u, 0x03u}, + {0x36u, 0x02u}, + {0x38u, 0x28u}, + {0x39u, 0x28u}, + {0x3Eu, 0x55u}, + {0x3Fu, 0x15u}, + {0x40u, 0x42u}, + {0x41u, 0x05u}, + {0x44u, 0x06u}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Cu, 0x12u}, + {0x4Du, 0x5Cu}, + {0x4Eu, 0x78u}, + {0x57u, 0x02u}, + {0x58u, 0x7Fu}, + {0x5Cu, 0x04u}, + {0x5Du, 0x04u}, + {0x5Eu, 0x0Cu}, + {0x5Fu, 0x0Cu}, + {0x62u, 0x08u}, + {0x63u, 0x09u}, + {0x64u, 0x50u}, + {0x65u, 0xA8u}, + {0x69u, 0x1Cu}, + {0x6Au, 0x58u}, + {0x6Bu, 0xA1u}, + {0x6Du, 0x10u}, + {0x70u, 0x10u}, + {0x71u, 0x1Du}, + {0x82u, 0x01u}, + {0x86u, 0x01u}, + {0x8Au, 0x02u}, + {0x8Cu, 0x01u}, + {0x98u, 0x01u}, + {0x9Cu, 0x03u}, + {0x9Eu, 0x04u}, + {0xA0u, 0x01u}, + {0xA8u, 0x01u}, + {0xACu, 0x03u}, + {0xAEu, 0x04u}, + {0xB4u, 0x07u}, + {0xB6u, 0x07u}, + {0xBCu, 0xA0u}, + {0xC0u, 0x42u}, + {0xC1u, 0x05u}, + {0xC4u, 0x06u}, + {0xC7u, 0xB4u}, + {0xC8u, 0x30u}, + {0xC9u, 0xFFu}, + {0xCAu, 0xFFu}, + {0xCBu, 0xFFu}, + {0xCCu, 0x13u}, + {0xCDu, 0x5Cu}, + {0xCEu, 0x77u}, + {0xDCu, 0x0Fu}, + {0xDEu, 0x0Fu}, + {0xDFu, 0x04u}, + {0xE3u, 0x09u}, + {0xE4u, 0x50u}, + {0xE5u, 0xA8u}, + {0xE9u, 0x1Cu}, + {0xEAu, 0x58u}, + {0xEBu, 0xA1u}, + {0xEDu, 0x10u}, + {0xF0u, 0x10u}, + {0xF1u, 0x1Du}, + {0x28u, 0x10u}, + {0xA8u, 0xE1u}, + {0xACu, 0x52u}, + {0xB0u, 0xAAu}, + {0xB4u, 0x01u}, + {0xA8u, 0xA1u}, + {0xE8u, 0x02u}, + {0xA8u, 0x87u}, + {0xACu, 0x53u}, + {0x00u, 0x01u}, + {0x10u, 0x01u}, + {0x14u, 0x01u}, + {0x18u, 0x01u}, +}; + + + +CYPACKED typedef struct +{ +void *address; +uint16 size; +} CYPACKED_ATTR cfg_memset_t; + + +CYPACKED typedef struct +{ + void *dest; + const void *src; + size_t size; +} CYPACKED_ATTR cfg_memcpy_t; + +static const cfg_memset_t CYCODE cfg_memset_list[] = +{ + /* address, size */ + {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_UDBSNG0_BASE), 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE), 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE), 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE), 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_UDBSNG0_BASE), 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE), 116u}, +}; + +/* UDB_UDBPAIR4_UDBSNG0 Address: CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE Size (bytes): 116 */ +static const uint8 CYCODE BS_UDB_UDBPAIR4_UDBSNG0_VAL[] = +{ + 0x42u, 0x00u, 0x25u, 0x0Au, 0x50u, 0x00u, 0x08u, 0x00u, 0x48u, 0x00u, 0x10u, 0x05u, 0x04u, 0x00u, 0x00u, 0x00u, + 0x61u, 0x00u, 0x06u, 0x00u, 0x00u, 0x0Au, 0x00u, 0x00u, 0x41u, 0x0Cu, 0x26u, 0x03u, 0x00u, 0x00u, 0x04u, 0x0Au, + 0x48u, 0x05u, 0x10u, 0x00u, 0x40u, 0x00u, 0x18u, 0x05u, 0x04u, 0x00u, 0x00u, 0x05u, 0x02u, 0x00u, 0x00u, 0x00u, + 0x07u, 0x0Cu, 0x40u, 0x03u, 0x07u, 0x00u, 0x38u, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x22u, 0x00u, 0x44u, 0x05u, + 0x42u, 0x05u, 0x00u, 0x00u, 0x06u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0x5Cu, 0x78u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x71u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x04u, 0x0Cu, 0x0Cu, + 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, + 0x10u, 0x1Du, 0x00u, 0x00u +}; + +/* UDB_UDBPAIR3_UDBSNG1 Address: CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE Size (bytes): 116 */ +static const uint8 CYCODE BS_UDB_UDBPAIR3_UDBSNG1_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x88u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x02u, 0x88u, 0x01u, 0x00u, + 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x88u, 0x03u, 0x00u, 0x01u, 0xBCu, 0x00u, 0x40u, 0x39u, 0x22u, 0x46u, 0xC5u, + 0x00u, 0x00u, 0x04u, 0x01u, 0x28u, 0xA2u, 0x56u, 0x4Du, 0x51u, 0x00u, 0x2Eu, 0x00u, 0x08u, 0x00u, 0x00u, 0x10u, + 0x00u, 0x60u, 0x00u, 0x80u, 0x1Fu, 0x00u, 0x60u, 0x1Fu, 0x00u, 0x80u, 0x20u, 0x00u, 0x20u, 0x80u, 0x40u, 0x05u, + 0x64u, 0x03u, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x06u, 0x11u, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0xA0u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x73u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, + 0x00u, 0x00u, 0x08u, 0x09u, 0x00u, 0x00u, 0x40u, 0x40u, 0x10u, 0x50u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u +}; + +/* UDB_UDBPAIR1_UDBSNG1 Address: CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE Size (bytes): 116 */ +static const uint8 CYCODE BS_UDB_UDBPAIR1_UDBSNG1_VAL[] = +{ + 0x04u, 0x20u, 0x02u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x79u, 0x00u, 0x82u, 0x11u, 0x48u, 0x2Eu, 0x95u, + 0x09u, 0x08u, 0x16u, 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x8Du, 0x00u, 0x72u, 0x20u, 0x08u, 0x00u, 0x00u, + 0x2Eu, 0x00u, 0x11u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x84u, + 0x38u, 0xE0u, 0x02u, 0x07u, 0x04u, 0x18u, 0x01u, 0x07u, 0x00u, 0x00u, 0x82u, 0x22u, 0x82u, 0xAAu, 0x14u, 0x00u, + 0x41u, 0x05u, 0x63u, 0x00u, 0x00u, 0x0Eu, 0x00u, 0xF0u, 0x21u, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x2Fu, + 0x08u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x04u, + 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x08u, 0x03u, 0x08u, 0x00u, 0x18u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x58u, 0xECu, 0x00u, 0x00u +}; + +/* UDB_UDBPAIR0_UDBSNG0 Address: CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE Size (bytes): 116 */ +static const uint8 CYCODE BS_UDB_UDBPAIR0_UDBSNG0_VAL[] = +{ + 0x95u, 0x08u, 0x6Au, 0x00u, 0x26u, 0x62u, 0xD9u, 0x9Du, 0x82u, 0x00u, 0x40u, 0x42u, 0x00u, 0x00u, 0x80u, 0x00u, + 0x00u, 0x00u, 0x90u, 0x32u, 0x4Eu, 0x00u, 0xB1u, 0x01u, 0x92u, 0x00u, 0x6Du, 0x00u, 0x00u, 0xB5u, 0x04u, 0x4Au, + 0x04u, 0x00u, 0x00u, 0x00u, 0x04u, 0xF2u, 0x00u, 0x09u, 0x00u, 0x66u, 0x01u, 0x88u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x3Fu, 0xE0u, 0xC0u, 0x1Fu, 0x3Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x2Au, 0x0Au, 0x2Au, 0x0Au, 0x00u, 0x00u, + 0x43u, 0x01u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0x5Cu, 0x78u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x00u, + 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, + 0x10u, 0x1Du, 0x00u, 0x00u +}; + +/* UDB_UDBPAIR1_UDBSNG0 Address: CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE Size (bytes): 116 */ +static const uint8 CYCODE BS_UDB_UDBPAIR1_UDBSNG0_VAL[] = +{ + 0x00u, 0x01u, 0x00u, 0x00u, 0xABu, 0x00u, 0x00u, 0x03u, 0x2Bu, 0xC9u, 0x54u, 0x12u, 0x02u, 0x00u, 0x00u, 0x40u, + 0xAAu, 0x00u, 0x01u, 0x01u, 0x81u, 0x05u, 0x2Au, 0xBAu, 0xAAu, 0x00u, 0x00u, 0x40u, 0x08u, 0xB3u, 0x00u, 0x4Cu, + 0x04u, 0x20u, 0x00u, 0x80u, 0x40u, 0x00u, 0x00u, 0x01u, 0x10u, 0x01u, 0x00u, 0x80u, 0x20u, 0xB1u, 0x00u, 0x04u, + 0x19u, 0x00u, 0x07u, 0x80u, 0x61u, 0x00u, 0x80u, 0x7Fu, 0x2Au, 0x00u, 0x00u, 0x80u, 0x00u, 0x80u, 0x55u, 0x04u, + 0x24u, 0x06u, 0x00u, 0x00u, 0x01u, 0x0Eu, 0x00u, 0xC4u, 0x31u, 0xFFu, 0xFFu, 0x0Eu, 0x82u, 0x20u, 0x00u, 0x00u, + 0x08u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x0Cu, 0x0Cu, 0x04u, + 0x00u, 0x00u, 0x00u, 0x09u, 0x40u, 0x09u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x10u, 0x00u, 0x13u, 0x10u, 0x13u, + 0x40u, 0x03u, 0x00u, 0x10u +}; + +/* UDB_UDBPAIR0_UDBSNG1 Address: CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE Size (bytes): 116 */ +static const uint8 CYCODE BS_UDB_UDBPAIR0_UDBSNG1_VAL[] = +{ + 0x00u, 0x00u, 0x80u, 0x03u, 0x7Bu, 0x04u, 0x80u, 0x00u, 0x33u, 0x1Cu, 0xCCu, 0x00u, 0x04u, 0x03u, 0x00u, 0x00u, + 0x8Au, 0x00u, 0x71u, 0x04u, 0xB9u, 0x00u, 0x42u, 0x0Cu, 0x00u, 0x03u, 0x20u, 0x00u, 0x00u, 0x14u, 0x00u, 0x00u, + 0x00u, 0x00u, 0xA0u, 0x03u, 0x0Au, 0x1Cu, 0xD0u, 0x00u, 0x02u, 0x02u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, + 0x00u, 0x07u, 0x00u, 0x18u, 0xF8u, 0x00u, 0x07u, 0x00u, 0x80u, 0x08u, 0x20u, 0x00u, 0x20u, 0x00u, 0x40u, 0x05u, + 0x43u, 0x01u, 0x00u, 0x00u, 0x02u, 0x00u, 0x40u, 0x0Bu, 0x18u, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, 0x77u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x7Fu, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x04u, 0x0Cu, 0x0Cu, + 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, + 0x10u, 0x1Du, 0x00u, 0x00u +}; + +/* UDB_UDBPAIR0_ROUTE Address: CYDEV_UDB_UDBPAIR0_ROUTE_BASE Size (bytes): 144 */ +static const uint8 CYCODE BS_UDB_UDBPAIR0_ROUTE_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x25u, 0x40u, 0x13u, 0x30u, + 0x54u, 0xF1u, 0x1Fu, 0xF6u, 0xF5u, 0x33u, 0x05u, 0x12u, 0x33u, 0x51u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x32u, + 0xFFu, 0x00u, 0x00u, 0x00u, 0x21u, 0x32u, 0x75u, 0x37u, 0x23u, 0xF5u, 0x51u, 0x14u, 0x54u, 0x32u, 0x11u, 0x41u, + 0x33u, 0x51u, 0xFFu, 0x0Fu, 0x5Fu, 0xFFu, 0x2Fu, 0x22u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x14u, 0x01u, 0x01u, 0x11u, 0x10u, 0x44u, 0x53u, 0x33u, 0x14u, 0x11u, 0x40u, 0x01u, 0x01u, 0x33u, 0x4Cu, 0x04u, + 0x11u, 0x01u, 0x3Bu, 0x01u, 0x01u, 0x10u, 0x11u, 0x00u, 0x62u, 0x10u, 0x11u, 0x13u, 0x11u, 0x19u, 0x11u, 0x16u, + 0x09u, 0x73u, 0x10u, 0x66u, 0x11u, 0x11u, 0x11u, 0x11u, 0x12u, 0x11u, 0x11u, 0x14u, 0x11u, 0x14u, 0x11u, 0x11u +}; + +/* UDB_UDBPAIR1_ROUTE Address: CYDEV_UDB_UDBPAIR1_ROUTE_BASE Size (bytes): 144 */ +static const uint8 CYCODE BS_UDB_UDBPAIR1_ROUTE_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x0Fu, 0xF5u, 0x5Fu, + 0x22u, 0xFFu, 0x04u, 0xF1u, 0x56u, 0x63u, 0x61u, 0x12u, 0xF7u, 0x04u, 0x37u, 0x16u, 0x63u, 0xFFu, 0xFFu, 0x32u, + 0xFFu, 0x00u, 0x00u, 0x00u, 0x2Fu, 0x52u, 0x75u, 0x60u, 0x45u, 0x04u, 0x14u, 0x31u, 0x44u, 0x12u, 0x76u, 0x13u, + 0x51u, 0x73u, 0x70u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x25u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x00u, 0xF5u, + 0x4Fu, 0x06u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x03u, 0x06u, 0x00u, 0xA1u, 0x06u, 0x0Cu, 0x36u, 0xF5u, 0x0Du, 0x10u, 0xF3u, 0x01u, 0x00u, 0xFFu, 0x3Fu, 0x0Fu, + 0x15u, 0x00u, 0xFBu, 0x01u, 0x03u, 0x10u, 0x11u, 0x4Cu, 0x11u, 0x52u, 0x90u, 0xC1u, 0xD2u, 0x15u, 0xC3u, 0x5Fu, + 0x36u, 0x0Fu, 0x23u, 0x3Cu, 0x00u, 0x11u, 0x15u, 0x11u, 0x11u, 0x31u, 0x14u, 0x1Fu, 0x11u, 0x8Fu, 0x11u, 0xC1u +}; + +/* UDB_UDBPAIR2_ROUTE Address: CYDEV_UDB_UDBPAIR2_ROUTE_BASE Size (bytes): 144 */ +static const uint8 CYCODE BS_UDB_UDBPAIR2_ROUTE_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x11u, 0xFFu, 0x45u, + 0xFFu, 0x5Fu, 0xF5u, 0x44u, 0x4Fu, 0x36u, 0x43u, 0x73u, 0x13u, 0xFFu, 0x23u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x32u, + 0xFFu, 0x00u, 0x00u, 0x00u, 0x6Fu, 0x24u, 0x45u, 0x44u, 0x1Fu, 0x63u, 0x17u, 0x1Fu, 0xFFu, 0xFFu, 0x4Fu, 0xFFu, + 0x13u, 0x14u, 0x63u, 0x07u, 0x55u, 0xF7u, 0xF7u, 0x72u, 0xF0u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x05u, 0x2Fu, 0x10u, + 0xF0u, 0xF3u, 0xF0u, 0x10u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x01u, 0x00u, 0x8Du, 0x16u, 0x21u, 0x0Fu, 0x1Fu, 0x1Fu, 0xAFu, 0xB0u, 0x0Fu, 0xADu, 0x00u, 0xFFu, 0x4Fu, 0x00u, + 0x05u, 0x0Du, 0x0Au, 0x41u, 0x00u, 0xAAu, 0x01u, 0xF1u, 0xC4u, 0x10u, 0xF0u, 0x04u, 0xF3u, 0x1Fu, 0xC4u, 0x3Fu, + 0x1Fu, 0x03u, 0xF0u, 0xF0u, 0x88u, 0x01u, 0x3Fu, 0x01u, 0x11u, 0xB1u, 0x57u, 0x81u, 0x11u, 0xC1u, 0x1Du, 0x14u +}; + +/* UDB_UDBPAIR3_ROUTE Address: CYDEV_UDB_UDBPAIR3_ROUTE_BASE Size (bytes): 144 */ +static const uint8 CYCODE BS_UDB_UDBPAIR3_ROUTE_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x36u, 0x34u, 0x32u, + 0x06u, 0x14u, 0xF5u, 0x46u, 0x43u, 0xF6u, 0xF3u, 0x43u, 0xFFu, 0x37u, 0x5Fu, 0xFFu, 0x5Fu, 0xF2u, 0xFFu, 0x32u, + 0xFFu, 0x00u, 0x00u, 0x00u, 0x45u, 0xF4u, 0x37u, 0x40u, 0xF0u, 0xF2u, 0x7Fu, 0xF4u, 0xF4u, 0xFFu, 0xF3u, 0x03u, + 0x73u, 0xF0u, 0x77u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xF2u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x07u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x00u, 0x06u, 0xBFu, 0x17u, 0x11u, 0x7Fu, 0x71u, 0x11u, 0x5Fu, 0x70u, 0x5Fu, 0xFFu, 0x06u, 0xFFu, 0x0Fu, 0x07u, + 0x7Fu, 0x3Fu, 0x0Fu, 0xF6u, 0x00u, 0x2Fu, 0x7Fu, 0x48u, 0xF4u, 0x30u, 0xB0u, 0x5Fu, 0x11u, 0x0Fu, 0x91u, 0xFFu, + 0x1Fu, 0x0Au, 0xF3u, 0xFBu, 0x15u, 0x11u, 0x1Fu, 0xA1u, 0x11u, 0x81u, 0x11u, 0x12u, 0x14u, 0x11u, 0x1Fu, 0x31u +}; + +/* UDB_UDBPAIR4_ROUTE Address: CYDEV_UDB_UDBPAIR4_ROUTE_BASE Size (bytes): 144 */ +static const uint8 CYCODE BS_UDB_UDBPAIR4_ROUTE_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x60u, 0x17u, 0xF5u, 0x65u, + 0x77u, 0x77u, 0x7Fu, 0x05u, 0x14u, 0xF4u, 0x5Fu, 0x0Fu, 0x1Fu, 0x5Fu, 0x43u, 0x5Fu, 0xFFu, 0xF2u, 0xFFu, 0x05u, + 0xFFu, 0x00u, 0x00u, 0x00u, 0x23u, 0x7Fu, 0x52u, 0x64u, 0x55u, 0x75u, 0xFFu, 0xFFu, 0xF5u, 0xFFu, 0x11u, 0xFFu, + 0x1Fu, 0x52u, 0x13u, 0x40u, 0xFFu, 0xF3u, 0xFFu, 0xF5u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x25u, 0x00u, 0x30u, + 0x00u, 0x00u, 0x00u, 0x13u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x00u, 0x81u, 0x1Fu, 0x11u, 0x11u, 0x5Fu, 0x91u, 0x10u, 0xFFu, 0x33u, 0x0Fu, 0xFFu, 0x30u, 0xFFu, 0x4Fu, 0x31u, + 0x1Fu, 0xFFu, 0x06u, 0x06u, 0x0Au, 0x28u, 0x08u, 0x66u, 0x11u, 0x10u, 0xF9u, 0x17u, 0x20u, 0x3Fu, 0x10u, 0x2Fu, + 0x1Fu, 0x00u, 0xF1u, 0xF6u, 0x1Bu, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x33u, 0x31u, 0x11u, 0x17u, 0x11u, 0x11u, 0x1Bu +}; + +/* UDB_UDBPAIR5_ROUTE Address: CYDEV_UDB_UDBPAIR5_ROUTE_BASE Size (bytes): 144 */ +static const uint8 CYCODE BS_UDB_UDBPAIR5_ROUTE_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x43u, 0x43u, 0xFFu, 0x30u, + 0xF0u, 0x22u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x1Fu, 0x5Fu, 0x53u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x42u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x3Fu, 0xF3u, 0x1Fu, 0x15u, 0x11u, 0x13u, 0x13u, 0x41u, 0xF1u, 0x31u, 0x3Fu, + 0x1Fu, 0x53u, 0x03u, 0xF0u, 0x4Fu, 0xFFu, 0x2Fu, 0x13u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x01u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x23u, 0x11u, 0x1Fu, 0x11u, 0x31u, 0x7Fu, 0x61u, 0x17u, 0xBFu, 0x8Cu, 0x8Fu, 0xFFu, 0x39u, 0x1Fu, 0x95u, 0x1Cu, + 0x1Fu, 0xFFu, 0x6Cu, 0x7Fu, 0x33u, 0x1Fu, 0x7Fu, 0xFFu, 0x44u, 0x13u, 0x11u, 0x11u, 0x13u, 0x81u, 0x7Cu, 0x12u, + 0x11u, 0xCCu, 0x16u, 0x16u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI0 Address: CYDEV_UDB_DSI0_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI0_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x11u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Du, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI1 Address: CYDEV_UDB_DSI1_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI1_VAL[] = +{ + 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x20u, 0xF1u, 0x0Fu, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0xD1u, 0x11u, 0x11u, + 0x11u, 0xF1u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0xD1u, 0x11u, 0x10u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Du, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI2 Address: CYDEV_UDB_DSI2_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI2_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x0Au, 0x0Au, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x0Au, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x13u, 0x0Au, 0x00u, 0x0Du, 0x16u, 0x1Fu, 0x11u, 0x1Fu, + 0x1Fu, 0x1Fu, 0x0Au, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0xF4u, 0xF0u, 0x10u, 0x10u, 0x50u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x01u, 0x11u, 0x11u, + 0x11u, 0xF1u, 0x12u, 0x11u, 0xBFu, 0x11u, 0x11u, 0x1Du, 0x01u, 0x11u, 0x12u, 0x11u, 0x11u, 0x01u, 0xF1u, 0x10u, + 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x16u, 0x11u, 0x11u, 0x11u, 0x11u, 0x10u, 0x11u, + 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI3 Address: CYDEV_UDB_DSI3_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI3_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x11u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0xF1u, 0x11u, 0x11u, 0x03u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI4 Address: CYDEV_UDB_DSI4_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI4_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI5 Address: CYDEV_UDB_DSI5_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI5_VAL[] = +{ + 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI6 Address: CYDEV_UDB_DSI6_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI6_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x08u, 0x03u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI7 Address: CYDEV_UDB_DSI7_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI7_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x0Au, 0x1Fu, 0x08u, + 0x1Fu, 0x1Fu, 0x1Fu, 0x02u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x0Eu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x10u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x10u, 0x11u, 0x10u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u +}; + +/* UDB_DSI8 Address: CYDEV_UDB_DSI8_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI8_VAL[] = +{ + 0x00u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0xF0u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x1Du, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Du, 0x11u, 0x1Du, 0x11u, + 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI9 Address: CYDEV_UDB_DSI9_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI9_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI10 Address: CYDEV_UDB_DSI10_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI10_VAL[] = +{ + 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x16u, 0x0Cu, 0x1Fu, 0x03u, 0x06u, 0x1Fu, 0x1Fu, 0x05u, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0xFFu, 0x00u, 0xF0u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0xD1u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI11 Address: CYDEV_UDB_DSI11_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI11_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { + /* dest, src, size */ + {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE), BS_UDB_UDBPAIR4_UDBSNG0_VAL, 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE), BS_UDB_UDBPAIR3_UDBSNG1_VAL, 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE), BS_UDB_UDBPAIR1_UDBSNG1_VAL, 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE), BS_UDB_UDBPAIR0_UDBSNG0_VAL, 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE), BS_UDB_UDBPAIR1_UDBSNG0_VAL, 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE), BS_UDB_UDBPAIR0_UDBSNG1_VAL, 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_ROUTE_BASE), BS_UDB_UDBPAIR0_ROUTE_VAL, 144u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_ROUTE_BASE), BS_UDB_UDBPAIR1_ROUTE_VAL, 144u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_ROUTE_BASE), BS_UDB_UDBPAIR2_ROUTE_VAL, 144u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_ROUTE_BASE), BS_UDB_UDBPAIR3_ROUTE_VAL, 144u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_ROUTE_BASE), BS_UDB_UDBPAIR4_ROUTE_VAL, 144u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_ROUTE_BASE), BS_UDB_UDBPAIR5_ROUTE_VAL, 144u}, + {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), BS_UDB_DSI0_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI1_BASE), BS_UDB_DSI1_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI2_BASE), BS_UDB_DSI2_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI3_BASE), BS_UDB_DSI3_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI4_BASE), BS_UDB_DSI4_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI5_BASE), BS_UDB_DSI5_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI6_BASE), BS_UDB_DSI6_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI7_BASE), BS_UDB_DSI7_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI8_BASE), BS_UDB_DSI8_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI9_BASE), BS_UDB_DSI9_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI10_BASE), BS_UDB_DSI10_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI11_BASE), BS_UDB_DSI11_VAL, 124u}, +}; + +void SDIO_Host_Config_UDBs(void) +{ + size_t i; + + /* Power on the UDB array */ + CY_SET_REG32(0x402101F0u, 0x05FA0003u); + + /* Zero out critical memory blocks before beginning configuration */ + for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) + { + const cfg_memset_t *ms = &cfg_memset_list[i]; + CYMEMZERO(ms->address, ms->size); + } + + /* Copy device configuration data into registers */ + for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) + { + const cfg_memcpy_t *mc = &cfg_memcpy_list[i]; + CYCONFIGCPYCODE(mc->dest, mc->src, mc->size); + } + + cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); + + /* UDB_INT_CFG Starting address: CYDEV_UDB_UDBIF_INT_CLK_CTL */ + CY_SET_REG32((void *)(CYREG_UDB_UDBIF_INT_CLK_CTL), 0x00000001u); + + /* UDB_UDBPAIR0_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG0_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR0_UDBSNG0_RC_CFG0), 0x004C4C4Cu); + + /* UDB_UDBPAIR0_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG1_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR0_UDBSNG1_RC_CFG0), 0x4C4C444Cu); + + /* UDB_UDBPAIR1_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG0_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR1_UDBSNG0_RC_CFG0), 0x044C4C44u); + + /* UDB_UDBPAIR1_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG1_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR1_UDBSNG1_RC_CFG0), 0x044C4C4Cu); + + /* UDB_UDBPAIR2_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG0_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR2_UDBSNG0_RC_CFG0), 0x004C4C44u); + + /* UDB_UDBPAIR2_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG1_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR2_UDBSNG1_RC_CFG0), 0x0C4C040Cu); + + /* UDB_UDBPAIR3_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG0_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR3_UDBSNG0_RC_CFG0), 0x008C8C8Cu); + + /* UDB_UDBPAIR3_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG1_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR3_UDBSNG1_RC_CFG0), 0x4C4C4C4Cu); + + /* UDB_UDBPAIR4_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG0_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR4_UDBSNG0_RC_CFG0), 0x4C4C444Cu); + + /* UDB_UDBPAIR4_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG1_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR4_UDBSNG1_RC_CFG0), 0x008C808Cu); + + /* UDB_UDBPAIR5_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG0_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR5_UDBSNG0_RC_CFG0), 0x8C8C0404u); + + /* UDB_UDBPAIR5_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG1_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR5_UDBSNG1_RC_CFG0), 0x048F808Fu); + + /* Enable UDB array and digital routing */ + CY_SET_REG32((void *)0x40347900u, CY_GET_REG32((void *)0x40347900u) | 0x106u); +} + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h new file mode 100644 index 0000000000..22914b0ae2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h @@ -0,0 +1,905 @@ +#if !defined(CY_SDIO_CFG_H) +#define CY_SDIO_CFG_H + +#include + +#include "cy_dma.h" +#include "cy_sysclk.h" +#include "cy_trigmux.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CYREG_PROT_SMPU_MS0_CTL 0x40240000u +#define CYREG_PROT_SMPU_MS1_CTL 0x40240004u +#define CYREG_PROT_SMPU_MS2_CTL 0x40240008u +#define CYREG_PROT_SMPU_MS3_CTL 0x4024000cu +#define CYREG_PROT_SMPU_MS14_CTL 0x40240038u + +#define CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE 0x40342200u +#define CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE 0x40342080u + +#define CYREG_UDB_UDBPAIR0_UDBSNG0_RC_CFG0 0x4034205cu +#define CYREG_UDB_UDBPAIR0_UDBSNG1_RC_CFG0 0x403420dcu + +#define CYREG_UDB_UDBPAIR1_UDBSNG0_RC_CFG0 0x4034225cu +#define CYREG_UDB_UDBPAIR1_UDBSNG1_RC_CFG0 0x403422dcu + +#define CYREG_UDB_UDBPAIR2_UDBSNG0_RC_CFG0 0x4034245cu +#define CYREG_UDB_UDBPAIR2_UDBSNG1_RC_CFG0 0x403424dcu +#define CYREG_UDB_UDBPAIR3_UDBSNG0_RC_CFG0 0x4034265cu +#define CYREG_UDB_UDBPAIR3_UDBSNG1_RC_CFG0 0x403426dcu +#define CYREG_UDB_UDBPAIR4_UDBSNG0_RC_CFG0 0x4034285cu +#define CYREG_UDB_UDBPAIR4_UDBSNG1_RC_CFG0 0x403428dcu +#define CYREG_UDB_UDBPAIR5_UDBSNG0_RC_CFG0 0x40342a5cu +#define CYREG_UDB_UDBPAIR5_UDBSNG1_RC_CFG0 0x40342adcu + +#define CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE 0x40342800u +#define CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE 0x40342680u +#define CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE 0x40342280u +#define CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE 0x40342000u + +#define CYDEV_UDB_UDBPAIR0_ROUTE_BASE 0x40342100u +#define CYDEV_UDB_UDBPAIR1_ROUTE_BASE 0x40342300u +#define CYDEV_UDB_UDBPAIR2_ROUTE_BASE 0x40342500u +#define CYDEV_UDB_UDBPAIR3_ROUTE_BASE 0x40342700u +#define CYDEV_UDB_UDBPAIR4_ROUTE_BASE 0x40342900u +#define CYDEV_UDB_UDBPAIR5_ROUTE_BASE 0x40342b00u + + +#define CYDEV_UDB_UDBPAIR2_UDBSNG0_BASE 0x40342400u +#define CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE 0x40342480u +#define CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE 0x40342600u +#define CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE 0x40342880u +#define CYDEV_UDB_UDBPAIR5_UDBSNG0_BASE 0x40342a00u +#define CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE 0x40342a80u + + +#define CYDEV_UDB_DSI0_BASE 0x40346000u +#define CYDEV_UDB_DSI1_BASE 0x40346080u +#define CYDEV_UDB_DSI2_BASE 0x40346100u +#define CYDEV_UDB_DSI3_BASE 0x40346180u +#define CYDEV_UDB_DSI4_BASE 0x40346200u +#define CYDEV_UDB_DSI5_BASE 0x40346280u +#define CYDEV_UDB_DSI6_BASE 0x40346300u +#define CYDEV_UDB_DSI7_BASE 0x40346380u +#define CYDEV_UDB_DSI8_BASE 0x40346400u +#define CYDEV_UDB_DSI9_BASE 0x40346480u +#define CYDEV_UDB_DSI10_BASE 0x40346500u +#define CYDEV_UDB_DSI11_BASE 0x40346580u + +#define CYREG_UDB_UDBIF_INT_CLK_CTL 0x40347904u + +/*************Defines for UDBs from Creator*****************************/ +/***********These come for cyfitter.h**********************************/ + +/* TFT_DMA */ +#define TFT_DMA_DW__BLOCK_HW DW0 +#define TFT_DMA_DW__BLOCK_NUMBER 0u +#define TFT_DMA_DW__CHANNEL_HW DW0_CH_STRUCT2 +#define TFT_DMA_DW__CHANNEL_NUMBER 2u +#define TFT_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN2 +#define TFT_DMA_DW__TR_OUT TRIG10_IN_CPUSS_DW0_TR_OUT2 + +/* TFT_CTRL */ +#define TFT_CTRL_Sync_ctrl_reg__0__MASK 0x01u +#define TFT_CTRL_Sync_ctrl_reg__0__POS 0 +#define TFT_CTRL_Sync_ctrl_reg__1__MASK 0x02u +#define TFT_CTRL_Sync_ctrl_reg__1__POS 1 +#define TFT_CTRL_Sync_ctrl_reg__2__MASK 0x04u +#define TFT_CTRL_Sync_ctrl_reg__2__POS 2 +#define TFT_CTRL_Sync_ctrl_reg__3__MASK 0x08u +#define TFT_CTRL_Sync_ctrl_reg__3__POS 3 +#define TFT_CTRL_Sync_ctrl_reg__4__MASK 0x10u +#define TFT_CTRL_Sync_ctrl_reg__4__POS 4 +#define TFT_CTRL_Sync_ctrl_reg__5__MASK 0x20u +#define TFT_CTRL_Sync_ctrl_reg__5__POS 5 +#define TFT_CTRL_Sync_ctrl_reg__6__MASK 0x40u +#define TFT_CTRL_Sync_ctrl_reg__6__POS 6 +#define TFT_CTRL_Sync_ctrl_reg__7__MASK 0x80u +#define TFT_CTRL_Sync_ctrl_reg__7__POS 7 +#define TFT_CTRL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG 0x4034192Cu +#define TFT_CTRL_Sync_ctrl_reg__CONTROL_REG 0x4034172Cu +#define TFT_CTRL_Sync_ctrl_reg__CONTROL_ST_REG 0x4034032Cu +#define TFT_CTRL_Sync_ctrl_reg__COUNT_REG 0x4034172Cu +#define TFT_CTRL_Sync_ctrl_reg__COUNT_ST_REG 0x4034032Cu +#define TFT_CTRL_Sync_ctrl_reg__MASK 0xFFu +#define TFT_CTRL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG 0x4034042Cu +#define TFT_CTRL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG 0x4034042Cu +#define TFT_CTRL_Sync_ctrl_reg__PERIOD_REG 0x4034182Cu +#define TFT_CTRL_Sync_ctrl_reg__RC_CFG0 0x40342ADCu +#define TFT_CTRL_Sync_ctrl_reg__RC_CFG1 0x40342AE0u +#define TFT_CTRL_Sync_ctrl_reg__SC_CFG0 0x40342AD4u +#define TFT_CTRL_Sync_ctrl_reg__SC_CFG1 0x40342AD8u + +/* SDIO_HOST */ +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A0_REG 0x4034101Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A1_REG 0x4034111Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D0_REG 0x4034121Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D1_REG 0x4034131Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_DP_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_F0_REG 0x4034141Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_F1_REG 0x4034151Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_A0_REG 0x4034101Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_A1_REG 0x4034111Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_D0_REG 0x4034121Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_D1_REG 0x4034131Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_DP_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_F0_REG 0x4034141Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_F1_REG 0x4034151Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__A0_A1_REG 0x4034001Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__A0_REG 0x4034101Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__A1_REG 0x4034111Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__D0_D1_REG 0x4034011Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__D0_REG 0x4034121Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__D1_REG 0x4034131Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__DP_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG0 0x403426C0u +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG1 0x403426C4u +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG2 0x403426C8u +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG3 0x403426CCu +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG4 0x403426D0u +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC0 0x403426E4u +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC1 0x403426E8u +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC2 0x403426ECu +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC3 0x403426F0u +#define SDIO_HOST_bSDIO_blockCounter_u0__F0_F1_REG 0x4034021Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__F0_REG 0x4034141Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__F1_REG 0x4034151Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__MSK_DP_AUX_CTL_REG 0x4034041Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__PER_DP_AUX_CTL_REG 0x4034041Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__RC_CFG0 0x403426DCu +#define SDIO_HOST_bSDIO_blockCounter_u0__RC_CFG1 0x403426E0u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_CONTROL_REG 0x40341720u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_COUNT_REG 0x40341720u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_COUNT_CONTROL_REG 0x40341720u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_COUNT_COUNT_REG 0x40341720u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_MASK_MASK_REG 0x40341820u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_MASK_PERIOD_REG 0x40341820u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_PERIOD_MASK_REG 0x40341820u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_PERIOD_PERIOD_REG 0x40341820u +#define SDIO_HOST_bSDIO_byteCounter__32BIT_CONTROL_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_byteCounter__32BIT_CONTROL_REG 0x40341720u +#define SDIO_HOST_bSDIO_byteCounter__32BIT_COUNT_REG 0x40341720u +#define SDIO_HOST_bSDIO_byteCounter__32BIT_PERIOD_REG 0x40341820u +#define SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_byteCounter__CONTROL_REG 0x40341720u +#define SDIO_HOST_bSDIO_byteCounter__CONTROL_ST_REG 0x40340320u +#define SDIO_HOST_bSDIO_byteCounter__COUNT_REG 0x40341720u +#define SDIO_HOST_bSDIO_byteCounter__COUNT_ST_REG 0x40340320u +#define SDIO_HOST_bSDIO_byteCounter__MASK_CTL_AUX_CTL_REG 0x40340420u +#define SDIO_HOST_bSDIO_byteCounter__PER_CTL_AUX_CTL_REG 0x40340420u +#define SDIO_HOST_bSDIO_byteCounter__PERIOD_REG 0x40341820u +#define SDIO_HOST_bSDIO_byteCounter__RC_CFG0 0x4034285Cu +#define SDIO_HOST_bSDIO_byteCounter__RC_CFG1 0x40342860u +#define SDIO_HOST_bSDIO_byteCounter__SC_CFG0 0x40342854u +#define SDIO_HOST_bSDIO_byteCounter__SC_CFG1 0x40342858u +#define SDIO_HOST_bSDIO_byteCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_byteCounter_ST__16BIT_STATUS_REG 0x40341620u +#define SDIO_HOST_bSDIO_byteCounter_ST__32BIT_MASK_REG 0x40341820u +#define SDIO_HOST_bSDIO_byteCounter_ST__32BIT_STATUS_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_byteCounter_ST__32BIT_STATUS_REG 0x40341620u +#define SDIO_HOST_bSDIO_byteCounter_ST__MASK_REG 0x40341820u +#define SDIO_HOST_bSDIO_byteCounter_ST__MASK_ST_AUX_CTL_REG 0x40340420u +#define SDIO_HOST_bSDIO_byteCounter_ST__PER_ST_AUX_CTL_REG 0x40340420u +#define SDIO_HOST_bSDIO_byteCounter_ST__RC_CFG0 0x4034285Cu +#define SDIO_HOST_bSDIO_byteCounter_ST__RC_CFG1 0x40342860u +#define SDIO_HOST_bSDIO_byteCounter_ST__SC_CFG0 0x40342854u +#define SDIO_HOST_bSDIO_byteCounter_ST__SC_CFG1 0x40342858u +#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_CNT_REG 0x40340320u +#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_CONTROL_REG 0x40340320u +#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_REG 0x40341620u +#define SDIO_HOST_bSDIO_CMD__16BIT_A0_REG 0x40341018u +#define SDIO_HOST_bSDIO_CMD__16BIT_A1_REG 0x40341118u +#define SDIO_HOST_bSDIO_CMD__16BIT_D0_REG 0x40341218u +#define SDIO_HOST_bSDIO_CMD__16BIT_D1_REG 0x40341318u +#define SDIO_HOST_bSDIO_CMD__16BIT_DP_AUX_CTL_REG 0x40341918u +#define SDIO_HOST_bSDIO_CMD__16BIT_F0_REG 0x40341418u +#define SDIO_HOST_bSDIO_CMD__16BIT_F1_REG 0x40341518u +#define SDIO_HOST_bSDIO_CMD__32BIT_A0_REG 0x40341018u +#define SDIO_HOST_bSDIO_CMD__32BIT_A1_REG 0x40341118u +#define SDIO_HOST_bSDIO_CMD__32BIT_D0_REG 0x40341218u +#define SDIO_HOST_bSDIO_CMD__32BIT_D1_REG 0x40341318u +#define SDIO_HOST_bSDIO_CMD__32BIT_DP_AUX_CTL_REG 0x40341918u +#define SDIO_HOST_bSDIO_CMD__32BIT_F0_REG 0x40341418u +#define SDIO_HOST_bSDIO_CMD__32BIT_F1_REG 0x40341518u +#define SDIO_HOST_bSDIO_CMD__A0_A1_REG 0x40340018u +#define SDIO_HOST_bSDIO_CMD__A0_REG 0x40341018u +#define SDIO_HOST_bSDIO_CMD__A1_REG 0x40341118u +#define SDIO_HOST_bSDIO_CMD__D0_D1_REG 0x40340118u +#define SDIO_HOST_bSDIO_CMD__D0_REG 0x40341218u +#define SDIO_HOST_bSDIO_CMD__D1_REG 0x40341318u +#define SDIO_HOST_bSDIO_CMD__DP_AUX_CTL_REG 0x40341918u +#define SDIO_HOST_bSDIO_CMD__DPATH_CFG0 0x40342640u +#define SDIO_HOST_bSDIO_CMD__DPATH_CFG1 0x40342644u +#define SDIO_HOST_bSDIO_CMD__DPATH_CFG2 0x40342648u +#define SDIO_HOST_bSDIO_CMD__DPATH_CFG3 0x4034264Cu +#define SDIO_HOST_bSDIO_CMD__DPATH_CFG4 0x40342650u +#define SDIO_HOST_bSDIO_CMD__DPATH_OPC0 0x40342664u +#define SDIO_HOST_bSDIO_CMD__DPATH_OPC1 0x40342668u +#define SDIO_HOST_bSDIO_CMD__DPATH_OPC2 0x4034266Cu +#define SDIO_HOST_bSDIO_CMD__DPATH_OPC3 0x40342670u +#define SDIO_HOST_bSDIO_CMD__F0_F1_REG 0x40340218u +#define SDIO_HOST_bSDIO_CMD__F0_REG 0x40341418u +#define SDIO_HOST_bSDIO_CMD__F1_REG 0x40341518u +#define SDIO_HOST_bSDIO_CMD__RC_CFG0 0x4034265Cu +#define SDIO_HOST_bSDIO_CMD__RC_CFG1 0x40342660u +#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_CONTROL_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_CONTROL_CONTROL_REG 0x4034171Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_CONTROL_COUNT_REG 0x4034171Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_COUNT_CONTROL_REG 0x4034171Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_COUNT_COUNT_REG 0x4034171Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_MASK_MASK_REG 0x4034181Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_MASK_PERIOD_REG 0x4034181Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_PERIOD_MASK_REG 0x4034181Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_PERIOD_PERIOD_REG 0x4034181Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_CONTROL_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_CONTROL_REG 0x4034171Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_COUNT_REG 0x4034171Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_PERIOD_REG 0x4034181Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_REG 0x4034171Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_ST_REG 0x4034031Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__COUNT_REG 0x4034171Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__COUNT_ST_REG 0x4034031Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__MASK_CTL_AUX_CTL_REG 0x4034041Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__PER_CTL_AUX_CTL_REG 0x4034041Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__PERIOD_REG 0x4034181Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__RC_CFG0 0x403426DCu +#define SDIO_HOST_bSDIO_cmdBitCounter__RC_CFG1 0x403426E0u +#define SDIO_HOST_bSDIO_cmdBitCounter__SC_CFG0 0x403426D4u +#define SDIO_HOST_bSDIO_cmdBitCounter__SC_CFG1 0x403426D8u +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__16BIT_STATUS_REG 0x4034161Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__32BIT_MASK_REG 0x4034181Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__32BIT_STATUS_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__32BIT_STATUS_REG 0x4034161Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__MASK_REG 0x4034181Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__MASK_ST_AUX_CTL_REG 0x4034041Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__PER_ST_AUX_CTL_REG 0x4034041Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__RC_CFG0 0x403426DCu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__RC_CFG1 0x403426E0u +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__SC_CFG0 0x403426D4u +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__SC_CFG1 0x403426D8u +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_CNT_REG 0x4034031Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_CONTROL_REG 0x4034031Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_REG 0x4034161Cu +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341928u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_CONTROL_REG 0x40341728u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_COUNT_REG 0x40341728u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_COUNT_CONTROL_REG 0x40341728u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_COUNT_COUNT_REG 0x40341728u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_MASK_MASK_REG 0x40341828u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_MASK_PERIOD_REG 0x40341828u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_PERIOD_MASK_REG 0x40341828u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_PERIOD_PERIOD_REG 0x40341828u +#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG 0x40341928u +#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_REG 0x40341728u +#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_ST_REG 0x40340328u +#define SDIO_HOST_bSDIO_crcBitCounter__COUNT_REG 0x40341728u +#define SDIO_HOST_bSDIO_crcBitCounter__COUNT_ST_REG 0x40340328u +#define SDIO_HOST_bSDIO_crcBitCounter__MASK_CTL_AUX_CTL_REG 0x40340428u +#define SDIO_HOST_bSDIO_crcBitCounter__PER_CTL_AUX_CTL_REG 0x40340428u +#define SDIO_HOST_bSDIO_crcBitCounter__PERIOD_REG 0x40341828u +#define SDIO_HOST_bSDIO_crcBitCounter__RC_CFG0 0x40342A5Cu +#define SDIO_HOST_bSDIO_crcBitCounter__RC_CFG1 0x40342A60u +#define SDIO_HOST_bSDIO_crcBitCounter__SC_CFG0 0x40342A54u +#define SDIO_HOST_bSDIO_crcBitCounter__SC_CFG1 0x40342A58u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341928u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__16BIT_STATUS_REG 0x40341628u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__MASK_REG 0x40341828u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__MASK_ST_AUX_CTL_REG 0x40340428u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__PER_ST_AUX_CTL_REG 0x40340428u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__RC_CFG0 0x40342A5Cu +#define SDIO_HOST_bSDIO_crcBitCounter_ST__RC_CFG1 0x40342A60u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__SC_CFG0 0x40342A54u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__SC_CFG1 0x40342A58u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_AUX_CTL_REG 0x40341928u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_CNT_REG 0x40340328u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_CONTROL_REG 0x40340328u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_REG 0x40341628u +#define SDIO_HOST_bSDIO_CtrlReg__0__MASK 0x01u +#define SDIO_HOST_bSDIO_CtrlReg__0__POS 0 +#define SDIO_HOST_bSDIO_CtrlReg__1__MASK 0x02u +#define SDIO_HOST_bSDIO_CtrlReg__1__POS 1 +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_CONTROL_REG 0x40341714u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_COUNT_REG 0x40341714u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_COUNT_CONTROL_REG 0x40341714u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_COUNT_COUNT_REG 0x40341714u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_MASK_MASK_REG 0x40341814u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_MASK_PERIOD_REG 0x40341814u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_PERIOD_MASK_REG 0x40341814u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_PERIOD_PERIOD_REG 0x40341814u +#define SDIO_HOST_bSDIO_CtrlReg__2__MASK 0x04u +#define SDIO_HOST_bSDIO_CtrlReg__2__POS 2 +#define SDIO_HOST_bSDIO_CtrlReg__3__MASK 0x08u +#define SDIO_HOST_bSDIO_CtrlReg__3__POS 3 +#define SDIO_HOST_bSDIO_CtrlReg__32BIT_CONTROL_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_CtrlReg__32BIT_CONTROL_REG 0x40341714u +#define SDIO_HOST_bSDIO_CtrlReg__32BIT_COUNT_REG 0x40341714u +#define SDIO_HOST_bSDIO_CtrlReg__32BIT_PERIOD_REG 0x40341814u +#define SDIO_HOST_bSDIO_CtrlReg__4__MASK 0x10u +#define SDIO_HOST_bSDIO_CtrlReg__4__POS 4 +#define SDIO_HOST_bSDIO_CtrlReg__6__MASK 0x40u +#define SDIO_HOST_bSDIO_CtrlReg__6__POS 6 +#define SDIO_HOST_bSDIO_CtrlReg__7__MASK 0x80u +#define SDIO_HOST_bSDIO_CtrlReg__7__POS 7 +#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG 0x40341714u +#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_ST_REG 0x40340314u +#define SDIO_HOST_bSDIO_CtrlReg__COUNT_REG 0x40341714u +#define SDIO_HOST_bSDIO_CtrlReg__COUNT_ST_REG 0x40340314u +#define SDIO_HOST_bSDIO_CtrlReg__MASK 0xDFu +#define SDIO_HOST_bSDIO_CtrlReg__MASK_CTL_AUX_CTL_REG 0x40340414u +#define SDIO_HOST_bSDIO_CtrlReg__PER_CTL_AUX_CTL_REG 0x40340414u +#define SDIO_HOST_bSDIO_CtrlReg__PERIOD_REG 0x40341814u +#define SDIO_HOST_bSDIO_CtrlReg__RC_CFG0 0x403424DCu +#define SDIO_HOST_bSDIO_CtrlReg__RC_CFG1 0x403424E0u +#define SDIO_HOST_bSDIO_CtrlReg__SC_CFG0 0x403424D4u +#define SDIO_HOST_bSDIO_CtrlReg__SC_CFG1 0x403424D8u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_A0_REG 0x40341000u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_A1_REG 0x40341100u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_D0_REG 0x40341200u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_D1_REG 0x40341300u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_DP_AUX_CTL_REG 0x40341900u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_F0_REG 0x40341400u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_F1_REG 0x40341500u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_A0_REG 0x40341000u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_A1_REG 0x40341100u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_D0_REG 0x40341200u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_D1_REG 0x40341300u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_DP_AUX_CTL_REG 0x40341900u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_F0_REG 0x40341400u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_F1_REG 0x40341500u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A0_A1_REG 0x40340000u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A0_REG 0x40341000u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A1_REG 0x40341100u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D0_D1_REG 0x40340100u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D0_REG 0x40341200u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D1_REG 0x40341300u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DP_AUX_CTL_REG 0x40341900u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG0 0x40342040u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG1 0x40342044u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG2 0x40342048u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG3 0x4034204Cu +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG4 0x40342050u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC0 0x40342064u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC1 0x40342068u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC2 0x4034206Cu +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC3 0x40342070u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F0_F1_REG 0x40340200u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F0_REG 0x40341400u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F1_REG 0x40341500u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__RC_CFG0 0x4034205Cu +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__RC_CFG1 0x40342060u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_A0_REG 0x40341004u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_A1_REG 0x40341104u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_D0_REG 0x40341204u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_D1_REG 0x40341304u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_DP_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_F0_REG 0x40341404u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_F1_REG 0x40341504u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_A0_REG 0x40341004u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_A1_REG 0x40341104u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_D0_REG 0x40341204u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_D1_REG 0x40341304u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_DP_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_F0_REG 0x40341404u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_F1_REG 0x40341504u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A0_A1_REG 0x40340004u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A0_REG 0x40341004u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A1_REG 0x40341104u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D0_D1_REG 0x40340104u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D0_REG 0x40341204u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D1_REG 0x40341304u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DP_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG0 0x403420C0u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG1 0x403420C4u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG2 0x403420C8u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG3 0x403420CCu +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG4 0x403420D0u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC0 0x403420E4u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC1 0x403420E8u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC2 0x403420ECu +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC3 0x403420F0u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F0_F1_REG 0x40340204u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F0_REG 0x40341404u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F1_REG 0x40341504u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__MSK_DP_AUX_CTL_REG 0x40340404u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__PER_DP_AUX_CTL_REG 0x40340404u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__RC_CFG0 0x403420DCu +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__RC_CFG1 0x403420E0u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_A0_REG 0x40341010u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_A1_REG 0x40341110u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_D0_REG 0x40341210u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_D1_REG 0x40341310u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_DP_AUX_CTL_REG 0x40341910u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_F0_REG 0x40341410u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_F1_REG 0x40341510u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_A0_REG 0x40341010u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_A1_REG 0x40341110u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_D0_REG 0x40341210u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_D1_REG 0x40341310u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_DP_AUX_CTL_REG 0x40341910u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_F0_REG 0x40341410u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_F1_REG 0x40341510u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A0_A1_REG 0x40340010u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A0_REG 0x40341010u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A1_REG 0x40341110u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D0_D1_REG 0x40340110u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D0_REG 0x40341210u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D1_REG 0x40341310u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DP_AUX_CTL_REG 0x40341910u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG0 0x40342440u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG1 0x40342444u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG2 0x40342448u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG3 0x4034244Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG4 0x40342450u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC0 0x40342464u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC1 0x40342468u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC2 0x4034246Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC3 0x40342470u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F0_F1_REG 0x40340210u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F0_REG 0x40341410u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F1_REG 0x40341510u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__RC_CFG0 0x4034245Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__RC_CFG1 0x40342460u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_A0_REG 0x40341014u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_A1_REG 0x40341114u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_D0_REG 0x40341214u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_D1_REG 0x40341314u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_DP_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_F0_REG 0x40341414u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_F1_REG 0x40341514u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_A0_REG 0x40341014u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_A1_REG 0x40341114u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_D0_REG 0x40341214u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_D1_REG 0x40341314u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_DP_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_F0_REG 0x40341414u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_F1_REG 0x40341514u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A0_A1_REG 0x40340014u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A0_REG 0x40341014u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A1_REG 0x40341114u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D0_D1_REG 0x40340114u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D0_REG 0x40341214u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D1_REG 0x40341314u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DP_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG0 0x403424C0u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG1 0x403424C4u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG2 0x403424C8u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG3 0x403424CCu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG4 0x403424D0u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC0 0x403424E4u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC1 0x403424E8u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC2 0x403424ECu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC3 0x403424F0u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F0_F1_REG 0x40340214u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F0_REG 0x40341414u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F1_REG 0x40341514u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__MSK_DP_AUX_CTL_REG 0x40340414u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__PER_DP_AUX_CTL_REG 0x40340414u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__RC_CFG0 0x403424DCu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__RC_CFG1 0x403424E0u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_A0_REG 0x40341028u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_A1_REG 0x40341128u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_D0_REG 0x40341228u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_D1_REG 0x40341328u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_DP_AUX_CTL_REG 0x40341928u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_F0_REG 0x40341428u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_F1_REG 0x40341528u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A0_A1_REG 0x40340028u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A0_REG 0x40341028u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A1_REG 0x40341128u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D0_D1_REG 0x40340128u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D0_REG 0x40341228u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D1_REG 0x40341328u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DP_AUX_CTL_REG 0x40341928u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG0 0x40342A40u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG1 0x40342A44u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG2 0x40342A48u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG3 0x40342A4Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG4 0x40342A50u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC0 0x40342A64u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC1 0x40342A68u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC2 0x40342A6Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC3 0x40342A70u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F0_F1_REG 0x40340228u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F0_REG 0x40341428u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F1_REG 0x40341528u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__MSK_DP_AUX_CTL_REG 0x40340428u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__PER_DP_AUX_CTL_REG 0x40340428u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__RC_CFG0 0x40342A5Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__RC_CFG1 0x40342A60u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A0_A1_REG 0x4034002Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A0_REG 0x4034102Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A1_REG 0x4034112Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D0_D1_REG 0x4034012Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D0_REG 0x4034122Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D1_REG 0x4034132Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DP_AUX_CTL_REG 0x4034192Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG0 0x40342AC0u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG1 0x40342AC4u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG2 0x40342AC8u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG3 0x40342ACCu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG4 0x40342AD0u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC0 0x40342AE4u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC1 0x40342AE8u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC2 0x40342AECu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC3 0x40342AF0u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F0_F1_REG 0x4034022Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F0_REG 0x4034142Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F1_REG 0x4034152Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__MSK_DP_AUX_CTL_REG 0x4034042Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__PER_DP_AUX_CTL_REG 0x4034042Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__RC_CFG0 0x40342ADCu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__RC_CFG1 0x40342AE0u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_A0_REG 0x40341020u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_A1_REG 0x40341120u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_D0_REG 0x40341220u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_D1_REG 0x40341320u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_DP_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_F0_REG 0x40341420u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_F1_REG 0x40341520u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_A0_REG 0x40341020u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_A1_REG 0x40341120u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_D0_REG 0x40341220u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_D1_REG 0x40341320u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_DP_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_F0_REG 0x40341420u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_F1_REG 0x40341520u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A0_A1_REG 0x40340020u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A0_REG 0x40341020u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A1_REG 0x40341120u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D0_D1_REG 0x40340120u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D0_REG 0x40341220u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D1_REG 0x40341320u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DP_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG0 0x40342840u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG1 0x40342844u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG2 0x40342848u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG3 0x4034284Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG4 0x40342850u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC0 0x40342864u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC1 0x40342868u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC2 0x4034286Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC3 0x40342870u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F0_F1_REG 0x40340220u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F0_REG 0x40341420u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F1_REG 0x40341520u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__MSK_DP_AUX_CTL_REG 0x40340420u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__PER_DP_AUX_CTL_REG 0x40340420u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__RC_CFG0 0x4034285Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__RC_CFG1 0x40342860u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_A0_REG 0x40341024u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_A1_REG 0x40341124u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_D0_REG 0x40341224u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_D1_REG 0x40341324u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_DP_AUX_CTL_REG 0x40341924u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_F0_REG 0x40341424u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_F1_REG 0x40341524u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A0_A1_REG 0x40340024u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A0_REG 0x40341024u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A1_REG 0x40341124u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D0_D1_REG 0x40340124u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D0_REG 0x40341224u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D1_REG 0x40341324u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DP_AUX_CTL_REG 0x40341924u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG0 0x403428C0u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG1 0x403428C4u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG2 0x403428C8u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG3 0x403428CCu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG4 0x403428D0u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC0 0x403428E4u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC1 0x403428E8u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC2 0x403428ECu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC3 0x403428F0u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F0_F1_REG 0x40340224u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F0_REG 0x40341424u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F1_REG 0x40341524u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__RC_CFG0 0x403428DCu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__RC_CFG1 0x403428E0u +#define SDIO_HOST_bSDIO_Read_DP__16BIT_A0_REG 0x4034100Cu +#define SDIO_HOST_bSDIO_Read_DP__16BIT_A1_REG 0x4034110Cu +#define SDIO_HOST_bSDIO_Read_DP__16BIT_D0_REG 0x4034120Cu +#define SDIO_HOST_bSDIO_Read_DP__16BIT_D1_REG 0x4034130Cu +#define SDIO_HOST_bSDIO_Read_DP__16BIT_DP_AUX_CTL_REG 0x4034190Cu +#define SDIO_HOST_bSDIO_Read_DP__16BIT_F0_REG 0x4034140Cu +#define SDIO_HOST_bSDIO_Read_DP__16BIT_F1_REG 0x4034150Cu +#define SDIO_HOST_bSDIO_Read_DP__32BIT_A0_REG 0x4034100Cu +#define SDIO_HOST_bSDIO_Read_DP__32BIT_A1_REG 0x4034110Cu +#define SDIO_HOST_bSDIO_Read_DP__32BIT_D0_REG 0x4034120Cu +#define SDIO_HOST_bSDIO_Read_DP__32BIT_D1_REG 0x4034130Cu +#define SDIO_HOST_bSDIO_Read_DP__32BIT_DP_AUX_CTL_REG 0x4034190Cu +#define SDIO_HOST_bSDIO_Read_DP__32BIT_F0_REG 0x4034140Cu +#define SDIO_HOST_bSDIO_Read_DP__32BIT_F1_REG 0x4034150Cu +#define SDIO_HOST_bSDIO_Read_DP__A0_A1_REG 0x4034000Cu +#define SDIO_HOST_bSDIO_Read_DP__A0_REG 0x4034100Cu +#define SDIO_HOST_bSDIO_Read_DP__A1_REG 0x4034110Cu +#define SDIO_HOST_bSDIO_Read_DP__D0_D1_REG 0x4034010Cu +#define SDIO_HOST_bSDIO_Read_DP__D0_REG 0x4034120Cu +#define SDIO_HOST_bSDIO_Read_DP__D1_REG 0x4034130Cu +#define SDIO_HOST_bSDIO_Read_DP__DP_AUX_CTL_REG 0x4034190Cu +#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG0 0x403422C0u +#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG1 0x403422C4u +#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG2 0x403422C8u +#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG3 0x403422CCu +#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG4 0x403422D0u +#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC0 0x403422E4u +#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC1 0x403422E8u +#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC2 0x403422ECu +#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC3 0x403422F0u +#define SDIO_HOST_bSDIO_Read_DP__F0_F1_REG 0x4034020Cu +#define SDIO_HOST_bSDIO_Read_DP__F0_REG 0x4034140Cu +#define SDIO_HOST_bSDIO_Read_DP__F1_REG 0x4034150Cu +#define SDIO_HOST_bSDIO_Read_DP__RC_CFG0 0x403422DCu +#define SDIO_HOST_bSDIO_Read_DP__RC_CFG1 0x403422E0u +#define SDIO_HOST_bSDIO_Read_DP_PI__16BIT_STATUS_AUX_CTL_REG 0x4034190Cu +#define SDIO_HOST_bSDIO_Read_DP_PI__16BIT_STATUS_REG 0x4034160Cu +#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_MASK_REG 0x4034180Cu +#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_STATUS_AUX_CTL_REG 0x4034190Cu +#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_STATUS_REG 0x4034160Cu +#define SDIO_HOST_bSDIO_Read_DP_PI__MASK_REG 0x4034180Cu +#define SDIO_HOST_bSDIO_Read_DP_PI__RC_CFG0 0x403422DCu +#define SDIO_HOST_bSDIO_Read_DP_PI__RC_CFG1 0x403422E0u +#define SDIO_HOST_bSDIO_Read_DP_PI__SC_CFG0 0x403422D4u +#define SDIO_HOST_bSDIO_Read_DP_PI__SC_CFG1 0x403422D8u +#define SDIO_HOST_bSDIO_Read_DP_PI__STATUS_AUX_CTL_REG 0x4034190Cu +#define SDIO_HOST_bSDIO_Read_DP_PI__STATUS_REG 0x4034160Cu +#define SDIO_HOST_bSDIO_StatusReg__0__MASK 0x01u +#define SDIO_HOST_bSDIO_StatusReg__0__POS 0 +#define SDIO_HOST_bSDIO_StatusReg__1__MASK 0x02u +#define SDIO_HOST_bSDIO_StatusReg__1__POS 1 +#define SDIO_HOST_bSDIO_StatusReg__16BIT_STATUS_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_StatusReg__16BIT_STATUS_REG 0x40341614u +#define SDIO_HOST_bSDIO_StatusReg__2__MASK 0x04u +#define SDIO_HOST_bSDIO_StatusReg__2__POS 2 +#define SDIO_HOST_bSDIO_StatusReg__3__MASK 0x08u +#define SDIO_HOST_bSDIO_StatusReg__3__POS 3 +#define SDIO_HOST_bSDIO_StatusReg__32BIT_MASK_REG 0x40341814u +#define SDIO_HOST_bSDIO_StatusReg__32BIT_STATUS_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_StatusReg__32BIT_STATUS_REG 0x40341614u +#define SDIO_HOST_bSDIO_StatusReg__6__MASK 0x40u +#define SDIO_HOST_bSDIO_StatusReg__6__POS 6 +#define SDIO_HOST_bSDIO_StatusReg__MASK 0x4Fu +#define SDIO_HOST_bSDIO_StatusReg__MASK_REG 0x40341814u +#define SDIO_HOST_bSDIO_StatusReg__MASK_ST_AUX_CTL_REG 0x40340414u +#define SDIO_HOST_bSDIO_StatusReg__PER_ST_AUX_CTL_REG 0x40340414u +#define SDIO_HOST_bSDIO_StatusReg__RC_CFG0 0x403424DCu +#define SDIO_HOST_bSDIO_StatusReg__RC_CFG1 0x403424E0u +#define SDIO_HOST_bSDIO_StatusReg__SC_CFG0 0x403424D4u +#define SDIO_HOST_bSDIO_StatusReg__SC_CFG1 0x403424D8u +#define SDIO_HOST_bSDIO_StatusReg__STATUS_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_StatusReg__STATUS_CNT_REG 0x40340314u +#define SDIO_HOST_bSDIO_StatusReg__STATUS_CONTROL_REG 0x40340314u +#define SDIO_HOST_bSDIO_StatusReg__STATUS_REG 0x40341614u +#define SDIO_HOST_bSDIO_Write_DP__16BIT_A0_REG 0x40341008u +#define SDIO_HOST_bSDIO_Write_DP__16BIT_A1_REG 0x40341108u +#define SDIO_HOST_bSDIO_Write_DP__16BIT_D0_REG 0x40341208u +#define SDIO_HOST_bSDIO_Write_DP__16BIT_D1_REG 0x40341308u +#define SDIO_HOST_bSDIO_Write_DP__16BIT_DP_AUX_CTL_REG 0x40341908u +#define SDIO_HOST_bSDIO_Write_DP__16BIT_F0_REG 0x40341408u +#define SDIO_HOST_bSDIO_Write_DP__16BIT_F1_REG 0x40341508u +#define SDIO_HOST_bSDIO_Write_DP__32BIT_A0_REG 0x40341008u +#define SDIO_HOST_bSDIO_Write_DP__32BIT_A1_REG 0x40341108u +#define SDIO_HOST_bSDIO_Write_DP__32BIT_D0_REG 0x40341208u +#define SDIO_HOST_bSDIO_Write_DP__32BIT_D1_REG 0x40341308u +#define SDIO_HOST_bSDIO_Write_DP__32BIT_DP_AUX_CTL_REG 0x40341908u +#define SDIO_HOST_bSDIO_Write_DP__32BIT_F0_REG 0x40341408u +#define SDIO_HOST_bSDIO_Write_DP__32BIT_F1_REG 0x40341508u +#define SDIO_HOST_bSDIO_Write_DP__A0_A1_REG 0x40340008u +#define SDIO_HOST_bSDIO_Write_DP__A0_REG 0x40341008u +#define SDIO_HOST_bSDIO_Write_DP__A1_REG 0x40341108u +#define SDIO_HOST_bSDIO_Write_DP__D0_D1_REG 0x40340108u +#define SDIO_HOST_bSDIO_Write_DP__D0_REG 0x40341208u +#define SDIO_HOST_bSDIO_Write_DP__D1_REG 0x40341308u +#define SDIO_HOST_bSDIO_Write_DP__DP_AUX_CTL_REG 0x40341908u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG0 0x40342240u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG1 0x40342244u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG2 0x40342248u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG3 0x4034224Cu +#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG4 0x40342250u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC0 0x40342264u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC1 0x40342268u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC2 0x4034226Cu +#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC3 0x40342270u +#define SDIO_HOST_bSDIO_Write_DP__F0_F1_REG 0x40340208u +#define SDIO_HOST_bSDIO_Write_DP__F0_REG 0x40341408u +#define SDIO_HOST_bSDIO_Write_DP__F1_REG 0x40341508u +#define SDIO_HOST_bSDIO_Write_DP__MSK_DP_AUX_CTL_REG 0x40340408u +#define SDIO_HOST_bSDIO_Write_DP__PER_DP_AUX_CTL_REG 0x40340408u +#define SDIO_HOST_bSDIO_Write_DP__RC_CFG0 0x4034225Cu +#define SDIO_HOST_bSDIO_Write_DP__RC_CFG1 0x40342260u +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_AUX_CTL_REG 0x40341908u +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_CONTROL_REG 0x40341708u +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_COUNT_REG 0x40341708u +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_COUNT_CONTROL_REG 0x40341708u +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_COUNT_COUNT_REG 0x40341708u +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_MASK_MASK_REG 0x40341808u +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_MASK_PERIOD_REG 0x40341808u +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_PERIOD_MASK_REG 0x40341808u +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_PERIOD_PERIOD_REG 0x40341808u +#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_CONTROL_AUX_CTL_REG 0x40341908u +#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_CONTROL_REG 0x40341708u +#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_COUNT_REG 0x40341708u +#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_PERIOD_REG 0x40341808u +#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_AUX_CTL_REG 0x40341908u +#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_REG 0x40341708u +#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_ST_REG 0x40340308u +#define SDIO_HOST_bSDIO_Write_DP_PO__COUNT_REG 0x40341708u +#define SDIO_HOST_bSDIO_Write_DP_PO__COUNT_ST_REG 0x40340308u +#define SDIO_HOST_bSDIO_Write_DP_PO__MASK_CTL_AUX_CTL_REG 0x40340408u +#define SDIO_HOST_bSDIO_Write_DP_PO__PER_CTL_AUX_CTL_REG 0x40340408u +#define SDIO_HOST_bSDIO_Write_DP_PO__PERIOD_REG 0x40341808u +#define SDIO_HOST_bSDIO_Write_DP_PO__RC_CFG0 0x4034225Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__RC_CFG1 0x40342260u +#define SDIO_HOST_bSDIO_Write_DP_PO__SC_CFG0 0x40342254u +#define SDIO_HOST_bSDIO_Write_DP_PO__SC_CFG1 0x40342258u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_CONTROL_REG 0x40341704u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_COUNT_REG 0x40341704u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_COUNT_CONTROL_REG 0x40341704u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_COUNT_COUNT_REG 0x40341704u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_MASK_MASK_REG 0x40341804u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_MASK_PERIOD_REG 0x40341804u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_PERIOD_MASK_REG 0x40341804u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_PERIOD_PERIOD_REG 0x40341804u +#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_CONTROL_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_CONTROL_REG 0x40341704u +#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_COUNT_REG 0x40341704u +#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_PERIOD_REG 0x40341804u +#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_REG 0x40341704u +#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_ST_REG 0x40340304u +#define SDIO_HOST_bSDIO_writeCrcCounter__COUNT_REG 0x40341704u +#define SDIO_HOST_bSDIO_writeCrcCounter__COUNT_ST_REG 0x40340304u +#define SDIO_HOST_bSDIO_writeCrcCounter__MASK_CTL_AUX_CTL_REG 0x40340404u +#define SDIO_HOST_bSDIO_writeCrcCounter__PER_CTL_AUX_CTL_REG 0x40340404u +#define SDIO_HOST_bSDIO_writeCrcCounter__PERIOD_REG 0x40341804u +#define SDIO_HOST_bSDIO_writeCrcCounter__RC_CFG0 0x403420DCu +#define SDIO_HOST_bSDIO_writeCrcCounter__RC_CFG1 0x403420E0u +#define SDIO_HOST_bSDIO_writeCrcCounter__SC_CFG0 0x403420D4u +#define SDIO_HOST_bSDIO_writeCrcCounter__SC_CFG1 0x403420D8u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__16BIT_STATUS_REG 0x40341604u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_MASK_REG 0x40341804u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_STATUS_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_STATUS_REG 0x40341604u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__MASK_REG 0x40341804u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__MASK_ST_AUX_CTL_REG 0x40340404u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__PER_ST_AUX_CTL_REG 0x40340404u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__RC_CFG0 0x403420DCu +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__RC_CFG1 0x403420E0u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__SC_CFG0 0x403420D4u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__SC_CFG1 0x403420D8u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_CNT_REG 0x40340304u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_CONTROL_REG 0x40340304u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_REG 0x40341604u +#define SDIO_HOST_CMD_DMA_DW__BLOCK_HW DW0 +#define SDIO_HOST_CMD_DMA_DW__BLOCK_NUMBER 0u +#define SDIO_HOST_CMD_DMA_DW__CHANNEL_HW DW0_CH_STRUCT1 +#define SDIO_HOST_CMD_DMA_DW__CHANNEL_NUMBER 1u +#define SDIO_HOST_CMD_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN1 +#define SDIO_HOST_Internal_Clock__DIV_IDX 0 +#define SDIO_HOST_Internal_Clock__DIV_NUM 0 +#define SDIO_HOST_Internal_Clock__DIV_TYPE CY_SYSCLK_DIV_8_BIT +#define SDIO_HOST_Read_DMA_DW__BLOCK_HW DW1 +#define SDIO_HOST_Read_DMA_DW__BLOCK_NUMBER 1u +#define SDIO_HOST_Read_DMA_DW__CHANNEL_HW DW1_CH_STRUCT3 +#define SDIO_HOST_Read_DMA_DW__CHANNEL_NUMBER 3u +#define SDIO_HOST_Read_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN3 +#define SDIO_HOST_Resp_DMA_DW__BLOCK_HW DW0 +#define SDIO_HOST_Resp_DMA_DW__BLOCK_NUMBER 0u +#define SDIO_HOST_Resp_DMA_DW__CHANNEL_HW DW0_CH_STRUCT0 +#define SDIO_HOST_Resp_DMA_DW__CHANNEL_NUMBER 0u +#define SDIO_HOST_Resp_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN0 +#define SDIO_HOST_Write_DMA_DW__BLOCK_HW DW1 +#define SDIO_HOST_Write_DMA_DW__BLOCK_NUMBER 1u +#define SDIO_HOST_Write_DMA_DW__CHANNEL_HW DW1_CH_STRUCT1 +#define SDIO_HOST_Write_DMA_DW__CHANNEL_NUMBER 1u +#define SDIO_HOST_Write_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN1 + + +/***************************CMD DMA***************************************/ +#define SDIO_HOST_CMD_DMA_DW_BLOCK (0u) +#define SDIO_HOST_CMD_DMA_DW_CHANNEL (1u) +#define SDIO_HOST_CMD_DMA_HW (DW0) +#define SDIO_HOST_CMD_DMA_INTR_MASK (CY_DMA_INTR_MASK) + +/* Channel settings */ +#define SDIO_HOST_CMD_DMA_PRIORITY (1u) +#define SDIO_HOST_CMD_DMA_DESCRIPTOR_NUM (1u) +#define SDIO_HOST_CMD_DMA_PREEMPTABLE (true) + +extern cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config; +extern cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc; + +/***************************Read DMA***************************************/ +#define SDIO_HOST_Read_DMA_DW_BLOCK (1u) +#define SDIO_HOST_Read_DMA_DW_CHANNEL (3u) +#define SDIO_HOST_Read_DMA_HW (DW1) +#define SDIO_HOST_Read_DMA_INTR_MASK (CY_DMA_INTR_MASK) + +/* Channel settings */ +#define SDIO_HOST_Read_DMA_PRIORITY (0u) +#define SDIO_HOST_Read_DMA_DESCRIPTOR_NUM (1u) +#define SDIO_HOST_Read_DMA_PREEMPTABLE (false) + +extern cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config; +extern cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc; + +/***************************Resp DMA***************************************/ +#define SDIO_HOST_Resp_DMA_DW_BLOCK (0u) +#define SDIO_HOST_Resp_DMA_DW_CHANNEL (0u) +#define SDIO_HOST_Resp_DMA_HW (DW0) +#define SDIO_HOST_Resp_DMA_INTR_MASK (CY_DMA_INTR_MASK) + +/* Channel settings */ +#define SDIO_HOST_Resp_DMA_PRIORITY (1u) +#define SDIO_HOST_Resp_DMA_DESCRIPTOR_NUM (1u) +#define SDIO_HOST_Resp_DMA_PREEMPTABLE (true) + +extern cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config; +extern cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc; + +/***************************Write DMA***************************************/ +#define SDIO_HOST_Write_DMA_DW_BLOCK (1u) +#define SDIO_HOST_Write_DMA_DW_CHANNEL (1u) +#define SDIO_HOST_Write_DMA_HW (DW1) +#define SDIO_HOST_Write_DMA_INTR_MASK (CY_DMA_INTR_MASK) + +/* Channel settings */ +#define SDIO_HOST_Write_DMA_PRIORITY (0u) +#define SDIO_HOST_Write_DMA_DESCRIPTOR_NUM (1u) +#define SDIO_HOST_Write_DMA_PREEMPTABLE (false) + +extern cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config; +extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc; + +/***************************SDIO Clock**************************************/ +/* The peripheral clock divider number */ +#define SDIO_HOST_Internal_Clock_DIV_NUM ((uint32_t)0) +/* The peripheral clock divider type */ +#define SDIO_HOST_Internal_Clock_DIV_TYPE ((cy_en_divider_types_t)CY_SYSCLK_DIV_8_BIT) + + +/*Function for configuring UDBs*/ +void SDIO_Host_Config_UDBs(void); + +/* SDIO_HOST_Read_Int */ +#define SDIO_HOST_Read_Int__INTC_CORTEXM4_ASSIGNED 1 +#define SDIO_HOST_Read_Int__INTC_CORTEXM4_PRIORITY 7u +#define SDIO_HOST_Read_Int__INTC_NUMBER 69u +#define SDIO_HOST_Read_Int_INTC_CORTEXM4_ASSIGNED 1 +#define SDIO_HOST_Read_Int_INTC_CORTEXM4_PRIORITY 7u +#define SDIO_HOST_Read_Int_INTC_NUMBER 69u + +/* SDIO_HOST_sdio_int */ +#define SDIO_HOST_sdio_int__INTC_CORTEXM4_ASSIGNED 1 +#define SDIO_HOST_sdio_int__INTC_CORTEXM4_PRIORITY 7u +#define SDIO_HOST_sdio_int__INTC_NUMBER 122u +#define SDIO_HOST_sdio_int_INTC_CORTEXM4_ASSIGNED 1 +#define SDIO_HOST_sdio_int_INTC_CORTEXM4_PRIORITY 7u +#define SDIO_HOST_sdio_int_INTC_NUMBER 122u + +/* SDIO_HOST_Write_Int */ +#define SDIO_HOST_Write_Int__INTC_CORTEXM4_ASSIGNED 1 +#define SDIO_HOST_Write_Int__INTC_CORTEXM4_PRIORITY 7u +#define SDIO_HOST_Write_Int__INTC_NUMBER 67u +#define SDIO_HOST_Write_Int_INTC_CORTEXM4_ASSIGNED 1 +#define SDIO_HOST_Write_Int_INTC_CORTEXM4_PRIORITY 7u +#define SDIO_HOST_Write_Int_INTC_NUMBER 67u + +#if defined(__cplusplus) +} +#endif + +#endif /* !defined(CY_SDIO_CFG_H) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_cy8ckit_062_wifi_bt.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_cy8ckit_062_wifi_bt.c new file mode 100644 index 0000000000..fe0be77883 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_cy8ckit_062_wifi_bt.c @@ -0,0 +1,79 @@ +/***************************************************************************//** +* \file cybsp_cy8ckit_062_wifi_bt.c +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CY8CKIT-062-WIFI-BT pioneer kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "cybsp_cy8ckit_062_wifi_bt.h" +#include "cyhal_utils.h" +#include "cyhal_implementation.h" +#include "cycfg.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +cy_rslt_t cybsp_init(void) +{ + init_cycfg_system(); + + cy_rslt_t result = CY_RSLT_SUCCESS; + +#ifndef __MBED__ + /* Initialize User LEDs */ + result |= cybsp_led_init(CYBSP_USER_LED1); + result |= cybsp_led_init(CYBSP_USER_LED2); + result |= cybsp_led_init(CYBSP_USER_LED3); + result |= cybsp_led_init(CYBSP_USER_LED4); + result |= cybsp_led_init(CYBSP_USER_LED5); + /* Initialize User Buttons */ + result |= cybsp_btn_init(CYBSP_USER_BTN1); + + CY_ASSERT(CY_RSLT_SUCCESS == result); +#endif + +#if defined(CYBSP_WIFI_CAPABLE) + /* Initialize UDB SDIO interface. This must be done before any other HAL API attempts to allocate clocks or DMA + instances. The UDB SDIO interface uses specific instances which are reserved as part of this call. + NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init(). This is typically done + when starting up WiFi. */ + if (CY_RSLT_SUCCESS == result) + { + result = cybsp_sdio_init(); + } +#endif + +#if defined(CYBSP_RETARGET_ENABLED) + /* Initialize retargetting stdio to 'DEBUG_UART' peripheral */ + if (CY_RSLT_SUCCESS == result) + { + result = cybsp_retarget_init(); + } +#endif + + return result; +} + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_cy8ckit_062_wifi_bt.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_cy8ckit_062_wifi_bt.h new file mode 100644 index 0000000000..d03b7c7630 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_cy8ckit_062_wifi_bt.h @@ -0,0 +1,80 @@ +/***************************************************************************//** +* \file cybsp_cy8ckit_062_wifi_bt.h +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CY8CKIT-062-WIFI-BT pioneer kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_bsp_cy8ckit_062_wifi_bt CY8CKIT-062-WIFI-BT +* \ingroup group_bsp +* \{ +* The PSoC 6 WiFi-BT Pioneer Kit is a low-cost hardware platform +* that enables design and debug of the PSoC 62 MCU (CY8C6247BZI-D54) +* and the Murata LBEE5KL1DX Module (CYW4343W WiFi + Bluetooth Combo Chip). +* +*
Kit Features:
+*
    +*
  • BLE v5.0
    • +*
  • Serial memory interface
    • +*
  • PDM-PCM digital microphone interface
    • +*
  • Industry-leading CapSense
    • +*
+* +*
Kit Contents:
+*
    +*
  • CY8CKIT-062-WIFI-BT evaluation board
    • +*
  • TFT display shield with a 2.4" TFT display, light sensor, 6-axis motion sensor, and digital microphone
    • +*
  • USB cable
    • +*
+* +* \defgroup group_bsp_cy8ckit_062_wifi_bt_macros Macros +* \defgroup group_bsp_cy8ckit_062_wifi_bt_functions Functions +* \defgroup group_bsp_cy8ckit_062_wifi_bt_enums Enumerated Types +*/ + +#pragma once + +#include "cybsp_api_core.h" +#ifdef MBED +#include "cybsp_api_wifi.h" +#endif /* MBED */ + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \cond INTERNAL */ + +// HAL HW configuration data +extern cyhal_qspi_t cybsp_qspi; +extern cyhal_uart_t cybsp_bt_uart; +extern cyhal_uart_t cybsp_debug_uart; +extern cyhal_i2c_t cybsp_i2c; +extern cyhal_rtc_t cybsp_rtc; + +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +/** \} group_bsp_cy8ckit_062_wifi_bt */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h new file mode 100644 index 0000000000..fb8caec7ce --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h @@ -0,0 +1,197 @@ +/***************************************************************************//** +* \file CY8CKIT-062-WIFI-BT/cybsp_types.h +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CY8CKIT-062-WIFI-BT pioneer kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_bsp_cy8ckit_062_wifi_bt CY8CKIT-062-WIFI-BT +* \ingroup group_bsp +* \{ +* \defgroup group_bsp_cy8ckit_062_wifi_bt_macros Macros +* \defgroup group_bsp_cy8ckit_062_wifi_bt_enums Enumerated Types +*/ + +#pragma once + +#include "cyhal.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_bsp_cy8ckit_062_wifi_bt_macros +* \{ +*/ + +// Generic signal names +/** Pin: WCO input */ +#define CYBSP_WCO_IN P0_0 +/** Pin: WCO output */ +#define CYBSP_WCO_OUT P0_1 + +/** Pin: WIFI SDIO D0 */ +#define CYBSP_WIFI_SDIO_D0 P2_0 +/** Pin: WIFI SDIO D1 */ +#define CYBSP_WIFI_SDIO_D1 P2_1 +/** Pin: WIFI SDIO D2 */ +#define CYBSP_WIFI_SDIO_D2 P2_2 +/** Pin: WIFI SDIO D3 */ +#define CYBSP_WIFI_SDIO_D3 P2_3 +/** Pin: WIFI SDIO CMD */ +#define CYBSP_WIFI_SDIO_CMD P2_4 +/** Pin: WIFI SDIO CLK */ +#define CYBSP_WIFI_SDIO_CLK P2_5 +/** Pin: WIFI ON */ +#define CYBSP_WIFI_WL_REG_ON P2_6 +/** Pin: WIFI Host Wakeup */ +#define CYBSP_WIFI_HOST_WAKE P2_7 + +/** Pin: BT UART RX */ +#define CYBSP_BT_UART_RX P3_0 +/** Pin: BT UART TX */ +#define CYBSP_BT_UART_TX P3_1 +/** Pin: BT UART RTS */ +#define CYBSP_BT_UART_RTS P3_2 +/** Pin: BT UART CTS */ +#define CYBSP_BT_UART_CTS P3_3 + +/** Pin: BT Power */ +#define CYBSP_BT_POWER P3_4 +/** Pin: BT Host Wakeup */ +#define CYBSP_BT_HOST_WAKE P3_5 +/** Pin: BT Device Wakeup */ +#define CYBSP_BT_DEVICE_WAKE P4_0 + +/** Pin: UART RX */ +#define CYBSP_DEBUG_UART_RX P5_0 +/** Pin: UART TX */ +#define CYBSP_DEBUG_UART_TX P5_1 + +/** Pin: I2C SCL */ +#define CYBSP_I2C_SCL P6_0 +/** Pin: I2C SDA */ +#define CYBSP_I2C_SDA P6_1 + +/** Pin: SWO */ +#define CYBSP_SWO P6_4 +/** Pin: SWDIO */ +#define CYBSP_SWDIO P6_6 +/** Pin: SWDCK */ +#define CYBSP_SWDCK P6_7 + +/** Pin: CapSesnse TX */ +#define CYBSP_CSD_TX P1_0 +/** Pin: CapSesnse CINA */ +#define CYBSP_CINA P7_1 +/** Pin: CapSesnse CINB */ +#define CYBSP_CINB P7_2 +/** Pin: CapSesnse CMOD */ +#define CYBSP_CMOD P7_7 +/** Pin: CapSesnse Button 0 */ +#define CYBSP_CSD_BTN0 P8_1 +/** Pin: CapSesnse Button 1 */ +#define CYBSP_CSD_BTN1 P8_2 +/** Pin: CapSesnse Slider 0 */ +#define CYBSP_CSD_SLD0 P8_3 +/** Pin: CapSesnse Slider 1 */ +#define CYBSP_CSD_SLD1 P8_4 +/** Pin: CapSesnse Slider 2 */ +#define CYBSP_CSD_SLD2 P8_5 +/** Pin: CapSesnse Slider 3 */ +#define CYBSP_CSD_SLD3 P8_6 +/** Pin: CapSesnse Slider 4 */ +#define CYBSP_CSD_SLD4 P8_7 + +/** Pin: QUAD SPI SS */ +#define CYBSP_QSPI_SS P11_2 +/** Pin: QUAD SPI D3 */ +#define CYBSP_QSPI_D3 P11_3 +/** Pin: QUAD SPI D2 */ +#define CYBSP_QSPI_D2 P11_4 +/** Pin: QUAD SPI D1 */ +#define CYBSP_QSPI_D1 P11_5 +/** Pin: QUAD SPI D0 */ +#define CYBSP_QSPI_D0 P11_6 +/** Pin: QUAD SPI SCK */ +#define CYBSP_QSPI_SCK P11_7 + +/** Host-wake GPIO drive mode */ +#define CYBSP_WIFI_HOST_WAKE_GPIO_DM CYHAL_GPIO_DRIVE_ANALOG +/** Host-wake IRQ event */ +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_RISE + +/** \} group_bsp_cy8ckit_062_wifi_bt_macros */ + +/** +* \addtogroup group_bsp_cy8ckit_062_wifi_bt_enums +* \{ +*/ + +/** Enum defining the different states for the LED. */ +typedef enum +{ + CYBSP_LED_STATE_ON = 0, + CYBSP_LED_STATE_OFF = 1, +} cybsp_led_state_t; + +/** Enum defining the different states for a button. */ +typedef enum +{ + CYBSP_BTN_PRESSED = 0, + CYBSP_BTN_OFF = 1, +} cybsp_btn_state_t; + +/** Enum defining the different LED pins on the board. */ +typedef enum +{ + CYBSP_LED9 = P13_7, + CYBSP_LED8 = P1_5, + CYBSP_LED_RGB_RED = P0_3, + CYBSP_LED_RGB_GREEN = P1_1, + CYBSP_LED_RGB_BLUE = P11_1, + + CYBSP_USER_LED1 = CYBSP_LED8, + CYBSP_USER_LED2 = CYBSP_LED9, + CYBSP_USER_LED3 = CYBSP_LED_RGB_RED, + CYBSP_USER_LED4 = CYBSP_LED_RGB_GREEN, + CYBSP_USER_LED5 = CYBSP_LED_RGB_BLUE, + CYBSP_USER_LED = CYBSP_USER_LED1, +} cybsp_led_t; + +/** Enum defining the different button pins on the board. */ +typedef enum +{ + CYBSP_SW2 = P0_4, + + CYBSP_USER_BTN1 = CYBSP_SW2, + CYBSP_USER_BTN = CYBSP_USER_BTN1, +} cybsp_btn_t; + +/** \} group_bsp_cy8ckit_062_wifi_bt_enums */ + +#if defined(__cplusplus) +} +#endif + +/** \} group_bsp_cy8ckit_062_wifi_bt */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct index f6812aa522..0152835028 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm0plus.scat -;* \version 2.40 +;* \version 2.50 ;* ;* Linker file for the ARMCC. ;* @@ -86,7 +86,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -#define Stack_Size MBED_BOOT_STACK_SIZE +#define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. ; Use these defines to specify the memory regions available for allocation. @@ -193,7 +193,7 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) } ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -Stack_Size + ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE { * (STACK) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld index 729633cdfe..45285e64c3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm0plus.ld -* \version 2.40 +* \version 2.50 * * Linker file for the GNU C compiler. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf index a82c796310..dc77b4ce23 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm0plus.icf -* \version 2.40 +* \version 2.50 * * Linker file for the IAR compiler. * @@ -163,8 +163,10 @@ if (!isdefinedsymbol(__STACK_SIZE)) { define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; } define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x4000; + define symbol __ICFEDIT_size_heap__ = 0x400; } else { define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; } @@ -191,7 +193,7 @@ define block RAM_BSS {readwrite section .bss}; define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; define block RO {first section .intvec, readonly}; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c index b28ca95120..010eac6188 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm0plus.c -* \version 2.40 +* \version 2.50 * * The device system-source file. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index 3319e48c9b..a23e6e13f6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4_dual.scat -;* \version 2.40 +;* \version 2.50 ;* ;* Linker file for the ARMCC. ;* @@ -78,7 +78,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -#define Stack_Size MBED_BOOT_STACK_SIZE +#define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. ; Use these defines to specify the memory regions available for allocation. @@ -190,7 +190,7 @@ LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE } ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -Stack_Size + ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE { * (STACK) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index b5e7d90d53..0cfd336d6e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.ld -* \version 2.40 +* \version 2.50 * * Linker file for the GNU C compiler. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf index 4be7d38872..1fd2e3e578 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.icf -* \version 2.40 +* \version 2.50 * * Linker file for the IAR compiler. * @@ -154,8 +154,9 @@ if (!isdefinedsymbol(__STACK_SIZE)) { define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; } +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x20000; + define symbol __ICFEDIT_size_heap__ = 0x400; } else { define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; } @@ -183,7 +184,7 @@ define block RAM_BSS {readwrite section .bss}; define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; define block RO {first section .intvec, readonly}; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S index ac9a099f33..75747c4fac 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S @@ -1,5 +1,5 @@ ;/**************************************************************************//** -; * @file startup_psoc6_01_cm4.s +; * @file startup_psoc6_01_cm4.S ; * @brief CMSIS Core Device Startup File for ; * ARMCM4 Device Series ; * @version V5.00 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c index c040a5c713..a5408385ee 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.40 +* \version 2.50 * * The device system-source file. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h index 99f86760b3..53bc71262c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.40 +* \version 2.50 * * \brief Device system header file. * @@ -320,6 +320,11 @@ * Reason for Change * * +* 2.50 +* Updated assembler files, C files, linker scripts. +* Dynamic allocated HEAP size for Arm Compiler 6, IAR 8. +* +* * 2.40 * Updated assembler files, C files, linker scripts. * Added Arm Compiler 6 support. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/cybsp_cy8cproto_062_4343w.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/cybsp_cy8cproto_062_4343w.c new file mode 100644 index 0000000000..a1d99885f2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/cybsp_cy8cproto_062_4343w.c @@ -0,0 +1,62 @@ +/***************************************************************************//** +* \file cybsp_cy8cproto_062_4343w.c +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CY8CPROTO-062-4343W prototyping kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "cybsp_cy8cproto_062_4343w.h" +#include "cyhal_implementation.h" +#include "cycfg.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +cy_rslt_t cybsp_init(void) +{ + init_cycfg_system(); + + cy_rslt_t result = CY_RSLT_SUCCESS; + +#ifndef __MBED__ + /* Initialize User LEDs */ + result |= cybsp_led_init(CYBSP_USER_LED1); + /* Initialize User Buttons */ + result |= cybsp_btn_init(CYBSP_USER_BTN1); + CY_ASSERT(CY_RSLT_SUCCESS == result); +#endif + +#if defined(CYBSP_RETARGET_ENABLED) + /* Initialize retargetting stdio to 'DEBUG_UART' peripheral */ + if (CY_RSLT_SUCCESS == result) + { + result = cybsp_retarget_init(); + } +#endif + + return result; +} + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/cybsp_cy8cproto_062_4343w.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/cybsp_cy8cproto_062_4343w.h new file mode 100644 index 0000000000..141a065e67 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/cybsp_cy8cproto_062_4343w.h @@ -0,0 +1,76 @@ +/***************************************************************************//** +* \file cybsp_cy8cproto_062_4343w.h +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CY8CPROTO-062-4343W prototyping kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_bsp_cy8cproto_062_4343w CY8CPROTO-062-4343W +* \ingroup group_bsp +* \{ +* The CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Prototyping Kit is a low-cost hardware platform that enables design and debug of PSoC 6 MCUs. +* It comes with a Murata LBEE5KL1DX module, based on the CYW4343W combo device, industry-leading CapSense for touch buttons and slider, on-board debugger/programmer with KitProg3, microSD card interface, 512-Mb Quad-SPI NOR flash, PDM-PCM microphone, and a thermistor. This kit is designed with a snap-away form-factor, allowing the user to separate the different components and features that come with this kit and use independently. +* In addition, support for Digilent's Pmod interface is also provided with this kit. +* +*
Kit Features:
+*
    +*
  • Support of up to 2MB Flash and 1MB SRAM
    • +*
  • Dedicated SDHC to interface with WICED wireless devices.
    • +*
  • Delivers dual-cores, with a 150-MHz Arm Cortex-M4 as the primary application processor and a 100-MHz Arm Cortex-M0+ as the secondary processor for low-power operations.
    • +*
  • Supports Full-Speed USB, capacitive-sensing with CapSense, a PDM-PCM digital microphone interface, a Quad-SPI interface, 13 serial communication blocks, 7 programmable analog blocks, and 56 programmable digital blocks.
    • +*
+* +*
Kit Contents:
+*
    +*
  • PSoC 6 Wi-Fi BT Prototyping Board
    • +*
  • USB Type-A to Micro-B cable
    • +*
  • Quick Start Guide
    • +*
+* +* \defgroup group_bsp_cy8cproto_062_4343w_macros Macros +* \defgroup group_bsp_cy8cproto_062_4343w_functions Functions +* \defgroup group_bsp_cy8cproto_062_4343w_enums Enumerated Types +*/ + +#pragma once + +#include +#include +#include "cybsp_api_core.h" + +#ifdef MBED +#include "cybsp_api_wifi.h" +#endif /* MBED */ + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \cond INTERNAL */ + +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +/** \} group_bsp_cy8cproto_062_4343w */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/cybsp_types.h new file mode 100644 index 0000000000..1c0ba6c8e6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/cybsp_types.h @@ -0,0 +1,119 @@ +/***************************************************************************//** +* \file CY8CPROTO-062-4343W/cybsp_types.h +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CY8CPROTO-062-4343W kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_bsp_cy8cproto_062_4343w CY8CPROTO-062-4343W +* \ingroup group_bsp +* \{ +* \defgroup group_bsp_cy8cproto_062_4343w_macros Macros +* \defgroup group_bsp_cy8cproto_062_4343w_enums Enumerated Types +*/ + +#pragma once + +#include "cyhal.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_bsp_cy8cproto_062_4343w_macros +* \{ +*/ + +/** Pin: WIFI SDIO D0 */ +#define CYBSP_WIFI_SDIO_D0 P2_0 +/** Pin: WIFI SDIO D1 */ +#define CYBSP_WIFI_SDIO_D1 P2_1 +/** Pin: WIFI SDIO D2 */ +#define CYBSP_WIFI_SDIO_D2 P2_2 +/** Pin: WIFI SDIO D3 */ +#define CYBSP_WIFI_SDIO_D3 P2_3 +/** Pin: WIFI SDIO CMD */ +#define CYBSP_WIFI_SDIO_CMD P2_4 +/** Pin: WIFI SDIO CLK */ +#define CYBSP_WIFI_SDIO_CLK P2_5 +/** Pin: WIFI ON */ +#define CYBSP_WIFI_WL_REG_ON P2_6 +/** Pin: WIFI Host Wakeup */ +#define CYBSP_WIFI_HOST_WAKE P1_4 + +/** Pin: UART RX */ +#define CYBSP_DEBUG_UART_RX P5_0 +/** Pin: UART TX */ +#define CYBSP_DEBUG_UART_TX P5_1 + +/** Host-wake GPIO drive mode */ +#define CYBSP_WIFI_HOST_WAKE_GPIO_DM CYHAL_GPIO_DRIVE_ANALOG +/** Host-wake IRQ event */ +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_RISE + +/** \} group_bsp_cy8cproto_062_4343w_macros */ + +/** +* \addtogroup group_bsp_cy8cproto_062_4343w_enums +* \{ +*/ + +/** Enum defining the different states for the LED. */ +typedef enum +{ + CYBSP_LED_STATE_ON = 0, + CYBSP_LED_STATE_OFF = 1, +} cybsp_led_state_t; + +/** Enum defining the different states for a button. */ +typedef enum +{ + CYBSP_BTN_PRESSED = 0, + CYBSP_BTN_OFF = 1, +} cybsp_btn_state_t; + +/** Enum defining the different LED pins on the board. */ +typedef enum +{ + CYBSP_LED_RED = P13_7, + + CYBSP_USER_LED1 = CYBSP_LED_RED, + CYBSP_USER_LED = CYBSP_USER_LED1, +} cybsp_led_t; + +/** Enum defining the different button pins on the board. */ +typedef enum +{ + CYBSP_SW2 = P0_4, + + CYBSP_USER_BTN1 = CYBSP_SW2, + CYBSP_USER_BTN = CYBSP_USER_BTN1, +} cybsp_btn_t; + +/** \} group_bsp_cy8cproto_062_4343w_enums */ + +#if defined(__cplusplus) +} +#endif + +/** \} group_bsp_cy8cproto_062_4343w */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct index 86f0aa1d0e..4cac0dd77d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xxa_cm4_dual.scat -;* \version 2.40 +;* \version 2.50 ;* ;* Linker file for the ARMCC. ;* @@ -78,7 +78,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -#define Stack_Size MBED_BOOT_STACK_SIZE +#define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. ; Use these defines to specify the memory regions available for allocation. @@ -190,7 +190,7 @@ LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE } ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -Stack_Size + ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE { * (STACK) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld index 50fd0e6636..d1e01ff2bf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm4_dual.ld -* \version 2.40 +* \version 2.50 * * Linker file for the GNU C compiler. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf index 74894ec0b8..2ee6f7c67d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm4_dual.icf -* \version 2.40 +* \version 2.50 * * Linker file for the IAR compiler. * @@ -154,8 +154,9 @@ if (!isdefinedsymbol(__STACK_SIZE)) { define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; } +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x20000; + define symbol __ICFEDIT_size_heap__ = 0x400; } else { define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; } @@ -183,7 +184,7 @@ define block RAM_BSS {readwrite section .bss}; define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; define block RO {first section .intvec, readonly}; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S index f16771c7c0..ade874af4d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S @@ -1,5 +1,5 @@ ;/**************************************************************************//** -; * @file startup_psoc6_02_cm4.s +; * @file startup_psoc6_02_cm4.S ; * @brief CMSIS Core Device Startup File for ; * ARMCM4 Device Series ; * @version V5.00 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6.h index 99f86760b3..53bc71262c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.40 +* \version 2.50 * * \brief Device system header file. * @@ -320,6 +320,11 @@ * Reason for Change * * +* 2.50 +* Updated assembler files, C files, linker scripts. +* Dynamic allocated HEAP size for Arm Compiler 6, IAR 8. +* +* * 2.40 * Updated assembler files, C files, linker scripts. * Added Arm Compiler 6 support. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6_cm4.c index c040a5c713..a5408385ee 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.40 +* \version 2.50 * * The device system-source file. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c new file mode 100644 index 0000000000..0c66057ed7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c @@ -0,0 +1,1346 @@ +/***************************************************************************//** +* \file cy_sdio.c +* \version 1.00 +* +* \brief +* This file provides the source code to the API for the UDB based SDIO driver. +* +******************************************************************************* +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SDIO_HOST.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#ifdef SEMAPHORE +#include "cyabs_rtos.h" + +#define NEVER_TIMEOUT ( (uint32_t)0xffffffffUL ) +static cy_semaphore_t sdio_transfer_finished_semaphore; +#endif + + +/*Globals Needed for DMA */ +/*DMA channel structures*/ +cy_stc_dma_channel_config_t respChannelConfig; +cy_stc_dma_channel_config_t cmdChannelConfig; +cy_stc_dma_channel_config_t writeChannelConfig; +cy_stc_dma_channel_config_t readChannelConfig; + +/*DMA Descriptor structures*/ +cy_stc_dma_descriptor_t respDesr; +cy_stc_dma_descriptor_t cmdDesr; +cy_stc_dma_descriptor_t readDesr0; +cy_stc_dma_descriptor_t readDesr1; +cy_stc_dma_descriptor_t writeDesr0; +cy_stc_dma_descriptor_t writeDesr1; + +/*Global structure used for data keeping*/ +stc_sdio_gInternalData_t gstcInternalData; + +/*Global CRC table*/ +static uint8_t crcTable[256]; + +/*Global values used for DMA interrupt*/ +static uint32_t yCountRemainder; +static uint32_t yCounts; + +static uint32_t udb_initialized = 0; + + +/******************************************************************************* +* Function Name: SDIO_Init +****************************************************************************//** +* +* Initializes the SDIO hardware, and register the callback +* +* \param pfuCb +* Pointer to structure that holds pointers to callback function +* see \ref stc_sdio_irq_cb_t. +* +* \note +* Sets SD Clock Frequency to 400 kHz +*******************************************************************************/ +void SDIO_Init(stc_sdio_irq_cb_t* pfuCb) +{ + if ( !udb_initialized ) + { + udb_initialized = 1; + SDIO_Host_Config_UDBs(); + } + + /*Set Number of Blocks to 1 initially, this will be updated later*/ + SDIO_SetNumBlocks(1); + + /*Enable SDIO ISR*/ + NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); + + /*Enable the Status Reg to generate an interrupt*/ + SDIO_STATUS_AUX_CTL |= (0x10); + + /*Set the priority of DW0, DW1, M4 and M0. DW1 should have highest*/ + /*First clear priority of all*/ + (* (reg32 *)CYREG_PROT_SMPU_MS0_CTL) &= ~0x0300; + (* (reg32 *)CYREG_PROT_SMPU_MS2_CTL) &= ~0x0300; + (* (reg32 *)CYREG_PROT_SMPU_MS3_CTL) &= ~0x0300; + (* (reg32 *)CYREG_PROT_SMPU_MS14_CTL) &= ~0x0300; + + /*Next set priority DW1 = 0, DW0 = 1, M4 = 2, M0 =3*/ + (* (reg32 *)CYREG_PROT_SMPU_MS2_CTL) |= 0x0100; + (* (reg32 *)CYREG_PROT_SMPU_MS0_CTL) |= 0x0200; + (* (reg32 *)CYREG_PROT_SMPU_MS14_CTL) |= 0x0200; + + /*Setup callback for card interrupt*/ + gstcInternalData.pstcCallBacks.pfnCardIntCb = pfuCb->pfnCardIntCb; + + /*Setup the DMA channels*/ + SDIO_SetupDMA(); + + /*Initialize CRC*/ + SDIO_Crc7Init(); + + /*Enable all the bit counters*/ + SDIO_CMD_BIT_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; + SDIO_WRITE_CRC_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; + SDIO_CRC_BIT_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; + SDIO_BYTE_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; + + /*Set block byte count to 64, this will be changed later */ + SDIO_SetBlockSize(64); + + /*Set the read and write FIFOs to use the half full status*/ + (*(reg32 *) SDIO_HOST_bSDIO_Write_DP__DP_AUX_CTL_REG) |= 0x0c; + (*(reg32 *) SDIO_HOST_bSDIO_Read_DP__DP_AUX_CTL_REG) |= 0x0c; + + /*Set clock to 400k, and enable it*/ + SDIO_SetSdClkFrequency(400000); + SDIO_EnableIntClock(); + SDIO_EnableSdClk(); + + /*Initalize the semaphore*/ +#ifdef SEMAPHORE + cy_rtos_init_semaphore( &sdio_transfer_finished_semaphore, 1, 1 ); +#endif +} + + +/******************************************************************************* +* Function Name: SDIO_SendCommand +****************************************************************************//** +* +* Send an SDIO command, don't wait for it to finish. +* +* \param pstcCmdConfig +* Command configuration structure. See \ref stc_sdio_cmd_config_t. +* +*******************************************************************************/ +void SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig) +{ + /*buffer to hold command data*/ + static uint8_t u8cmdBuf[6]; + + /*Populate buffer*/ + /*Element 0 is the Most Significant Byte*/ + u8cmdBuf[0] = SDIO_HOST_DIR | pstcCmdConfig->u8CmdIndex; + u8cmdBuf[1] = (uint8_t)((pstcCmdConfig->u32Argument & 0xff000000)>>24); + u8cmdBuf[2] = (uint8_t)((pstcCmdConfig->u32Argument & 0x00ff0000)>>16); + u8cmdBuf[3] = (uint8_t)((pstcCmdConfig->u32Argument & 0x0000ff00)>>8); + u8cmdBuf[4] = (uint8_t)((pstcCmdConfig->u32Argument & 0x000000ff)); + + /*calculate the CRC of above data*/ + u8cmdBuf[5] = SDIO_CalculateCrc7(u8cmdBuf, 5); + /*Shift it up by 1 as the CRC takes the upper 7 bits of the last byte of the cmd*/ + u8cmdBuf[5] = u8cmdBuf[5] << 1; + /*Add on the end bit*/ + u8cmdBuf[5] = u8cmdBuf[5] | SDIO_CMD_END_BIT; + + /*Load the first byte into A0*/ + SDIO_CMD_COMMAND_A0_REG = u8cmdBuf[0]; + + /*If a response is expected setup DMA to receive the response*/ + if (pstcCmdConfig->bResponseRequired == true) + { + /*Clear the flag in hardware that says skip response*/ + SDIO_CONTROL_REG &= ~SDIO_CTRL_SKIP_RESPONSE; + + /*Set the destination address*/ + respDesr.dst = (uint32_t)(pstcCmdConfig->pu8ResponseBuf); + + /*Initialize the channel with the descriptor*/ + Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL, &respDesr); + + /*Enable the channel*/ + Cy_DMA_Channel_Enable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL); + } + else + { + /*Set the skip flag*/ + SDIO_CONTROL_REG |= SDIO_CTRL_SKIP_RESPONSE; + } + + /*Setup the Command DMA*/ + /*Set the source address*/ + cmdDesr.src = (uint32_t)(&u8cmdBuf[1]); + + /*Initialize the channel with the descriptor*/ + Cy_DMA_Channel_SetDescriptor(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL , &cmdDesr); + + /*Enable the channel*/ + Cy_DMA_Channel_Enable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); +} + + +/******************************************************************************* +* Function Name: SDIO_GetResponse +****************************************************************************//** +* +* Takes a 6 byte response buffer, and extracts the 32 bit response, also checks +* for index errors, CRC errors, and end bit errors. +* +* \param bCmdIndexCheck +* If True check for index errors +* +* \param bCmdCrcCheck +* If True check for CRC errors +* +* \param u8cmdIdx +* Command index, used for checking the index error +* +* \param pu32Response +* location to store 32 bit response +* +* \param pu8ResponseBuf +* buffer that holds the 6 bytes of response data +* +* \return +* \ref en_sdio_result_t +* +*******************************************************************************/ +en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, uint8_t u8cmdIdx, uint32_t* pu32Response, uint8_t *pu8ResponseBuf) +{ + /*Function return*/ + en_sdio_result_t enRet = Error; + /*variable to hold temporary CRC*/ + uint8_t u8TmpCrc; + /*temporary response*/ + uint32_t u32TmpResponse; + + /*Zero out the pu32Response*/ + *pu32Response = 0; + + /*Check if the CRC needs to be checked*/ + if (bCmdCrcCheck) + { + /*Calculate the CRC*/ + u8TmpCrc = SDIO_CalculateCrc7(pu8ResponseBuf, 5); + + /*Shift calculated CRC up by one bit to match bit position of CRC*/ + u8TmpCrc = u8TmpCrc << 1; + + /*Compare calculated CRC with received CRC*/ + if ((u8TmpCrc & 0xfe) != (pu8ResponseBuf[5] & 0xfe)) + { + enRet |= CommandCrcError; + } + } + + /*Check if the index needs to be checked*/ + if (bCmdIndexCheck) + { + /*The index resides in the lower 6 bits of the 1st byte of the response*/ + if ((u8cmdIdx != (pu8ResponseBuf[0] & 0x3f))) + { + enRet |= CommandIdxError; + } + } + + /*Check the end bit*/ + if (!(pu8ResponseBuf[5] & 0x01)) + { + enRet |= CommandEndError; + } + + if (enRet == Error) + { + /*If we get here then there were no errors with the command populate the response*/ + u32TmpResponse = pu8ResponseBuf[1]; + u32TmpResponse = u32TmpResponse << 8; + u32TmpResponse |= pu8ResponseBuf[2]; + u32TmpResponse = u32TmpResponse << 8; + u32TmpResponse |= pu8ResponseBuf[3]; + u32TmpResponse = u32TmpResponse << 8; + u32TmpResponse |= pu8ResponseBuf[4]; + + *pu32Response = u32TmpResponse; + + enRet = Ok; + } + + return enRet; +} + + +/******************************************************************************* +* Function Name: SDIO_InitDataTransfer +****************************************************************************//** +* +* Configure the data channel for a data transfer. For a write this doesn't start +* the write, that must be done separately after the response is received. +* +* \param stc_sdio_data_config_t +* Data configuration structure. See \ref stc_sdio_data_config_t +* +* +*******************************************************************************/ +void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig) +{ + /*hold size of entire transfer*/ + uint32_t dataSize; + + /*calculate how many bytes are going to be sent*/ + dataSize = pstcDataConfig->u16BlockSize * pstcDataConfig->u16BlockCount; + + /*Set the block size and number of blocks*/ + SDIO_SetBlockSize(pstcDataConfig->u16BlockSize); + SDIO_SetNumBlocks((pstcDataConfig->u16BlockCount) - 1); + + /*If we are reading data setup the DMA to receive read data*/ + if (pstcDataConfig->bRead == true) + { + /*First disable the write channel*/ + Cy_DMA_Channel_Disable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL ); + + /*Clear any pending interrupts in the DMA*/ + Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL); + + NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + + /*setup the destination addresses*/ + readDesr0.dst = (uint32_t)(pstcDataConfig->pu8Data); + readDesr1.dst = (uint32_t)((pstcDataConfig->pu8Data) + 1024); + + /*Setup the X control to transfer two 16 bit elements per transfer for a total of 4 bytes + Remember X increment is in terms of data element size which is 16, thus why it is 1*/ + readDesr0.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 1); + readDesr1.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 1); + + /*The X Loop will always transfer 4 bytes. The FIFO will only trigger the + DMA when it has 4 bytes to send (2 in each F0 and F1). There is a possibility + that there could be 3,2,or 1 bytes still in the FIFOs. To solve this the DMA + will be SW triggered when hardware indicates all bytes have been received. + This leads to an extra 1, 2 or 3 bytes being received. So the RX buffer needs to + be at least 3 bytes bigger than the data size. + + Since the X loop is setup to 4, the maximum number of Y loop is 256 so one + descriptor can transfer 1024 bytes. Two descriptors can transfer 2048 bytes. + Since we don't know the maximum number of bytes to read only two descriptors will + be used. If more than 2048 bytes need to be read then and interrupt will be enabled + The descriptor that is not currently running will be updated in the ISR to receive + more data. + + So there are three conditions to check: + 1) Are we sending less than or equal to 1024 bytes if so use one descriptor + 2) Are we sending greater than 1024, but less than or equal to 2048, use two descriptors + 3) Greater than 2048, use two descriptors and the ISR + */ + + if (dataSize <= 1024) + { + /*Setup one descriptor*/ + /*Y Increment is 2 because the X is transfer 2 data elements (which are 16 bits)*/ + readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1) / 4) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + + /*Setup descriptor 0 to point to nothing and disable*/ + readDesr0.nextPtr = 0; + readDesr0.ctl |= 0x01000000; + + /*Disable Interrupt*/ + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + else if (dataSize <=2048) + { + /*setup the first descriptor for 1024, then setup 2nd descriptor for remainder*/ + + readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1025) / 4) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + + + /*Setup descriptor 0 to point to descriptor 1*/ + readDesr0.nextPtr = (uint32_t)(&readDesr1); + /*Setup descriptor 1 to point to nothing and disable */ + readDesr1.nextPtr = 0; + + /*Don't disable after first descriptor*/ + readDesr0.ctl &= ~0x01000000; + /*Disable after second descriptor*/ + readDesr1.ctl |= 0x01000000; + + /*Disable Interrupt*/ + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + else /*dataSize must be greater than 2048*/ + { + /*These are for the ISR, Need to figure out how many "descriptors" + need to run, and the yCount for last descriptor. + Example: dataSize = 2080 + yCounts = 2, yCountRemainder = 7 (send 8 more set of 4)*/ + yCounts = (dataSize / 1024); + + /*the Ycount register is a +1 register meaning 0 = 1. I However, need to know when there is + no remainder so I increase the value to make sure there is a remainder and decrement in the ISR*/ + yCountRemainder = (((dataSize - (yCounts * 1024)) + 3 ) / 4); + + /*Setup the Y Ctrl for both descriptors*/ + readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + + /*Setup descriptor 0 to point to descriptor 1*/ + readDesr0.nextPtr = (uint32_t)(&readDesr1); + /*Setup descriptor 1 to point to descriptor 0*/ + readDesr1.nextPtr = (uint32_t)(&readDesr0); + + /*Don't disable the channel on completion of descriptor*/ + readDesr0.ctl &= ~0x01000000; + readDesr1.ctl &= ~0x01000000; + + /*Decrement yCounts by 2 since we already have 2 descriptors setup*/ + yCounts -= 2; + + /*Enable DMA interrupt*/ + NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + + /*Initialize the channel with the first descriptor*/ + Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL , &readDesr0); + + /*Enable the channel*/ + Cy_DMA_Channel_Enable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); + + /*Set the flag in the control register to enable the read*/ + SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_READ; + } + + /*Otherwise it is a write*/ + else + { + /*First disable the Read channel*/ + Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); + + /*Clear any pending interrupts in the DMA*/ + Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); + + NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + + /*setup the SRC addresses*/ + writeDesr0.src = (uint32_t)(pstcDataConfig->pu8Data); + writeDesr1.src = (uint32_t)((pstcDataConfig->pu8Data) + 1024); + + + /*Setup the X control to transfer two 16 bit elements per transfer for a total of 4 bytes + Remember X increment is in terms of data element size which is 16, thus why it is 1*/ + writeDesr0.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 1); + writeDesr1.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 1); + + if (dataSize <= 1024) + { + /*Setup one descriptor*/ + /*Y Increment is 2 because the X is transfer 2 data elements (which are 16 bits)*/ + writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1) / 4) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + + /*Setup descriptor 0 to point to nothing and disable*/ + writeDesr0.nextPtr = 0; + writeDesr0.ctl |= 0x01000000; + + /*Disable Interrupt*/ + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + } + else if (dataSize <=2048) + { + /*setup the first descriptor for 1024, then setup 2nd descriptor for remainder*/ + + writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1025) / 4) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + + + /*Setup descriptor 0 to point to descriptor 1*/ + writeDesr0.nextPtr = (uint32_t)(&writeDesr1); + /*Setup descriptor 1 to point to nothing and disable */ + writeDesr1.nextPtr = 0; + + /*Don't disable after first descriptor*/ + writeDesr0.ctl &= ~0x01000000; + /*Disable after second descriptor*/ + writeDesr1.ctl |= 0x01000000; + + /*Disable Interrupt*/ + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + } + else /*dataSize must be greater than 2048*/ + { + /*These are for the ISR, Need to figure out how many "descriptors" + need to run, and the yCount for last descriptor. + Example: dataSize = 2080 + yCounts = 2, yCountRemainder = 7 (send 8 more set of 4)*/ + yCounts = (dataSize / 1024); + + /*the Ycount register is a +1 register meaning 0 = 1. I However, need to know when there is + no remainder so I increase the value to make sure there is a remainder and decrement in the ISR*/ + yCountRemainder = (((dataSize - (yCounts * 1024)) + 3 ) / 4); + + /*Setup the Y Ctrl for both descriptors*/ + writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + + /*Setup descriptor 0 to point to descriptor 1*/ + writeDesr0.nextPtr = (uint32_t)(&writeDesr1); + /*Setup descriptor 1 to point to descriptor 0*/ + writeDesr1.nextPtr = (uint32_t)(&writeDesr0); + + /*Don't disable the channel on completion of descriptor*/ + writeDesr0.ctl &= ~0x01000000; + writeDesr1.ctl &= ~0x01000000; + + /*Decrement yCounts by 2 since we already have 2 descriptors setup*/ + yCounts -= 2; + + /*Enable DMA interrupt*/ + NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + } + + /*Initialize the channel with the first descriptor*/ + Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL , &writeDesr0); + } +} + + +/******************************************************************************* +* Function Name: SDIO_SendCommandAndWait +****************************************************************************//** +* +* This function sends a command on the command channel and waits for that +* command to finish before returning. If a Command 53 is issued this function +* will handle all of the data transfer and wait to return until it is done. +* +* \param pstcCmd +* Pointer command configuration structure see \ref stc_sdio_cmd_t. +* +* \return +* \ref en_sdio_result_t +* +*******************************************************************************/ +en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) +{ + /*Store the command and data configurations*/ + stc_sdio_cmd_config_t stcCmdConfig; + stc_sdio_data_config_t stcDataConfig; + +#ifdef SEMAPHORE + en_sdio_result_t result; +#endif + + /*variable used for holding timeout value*/ +#ifndef SEMAPHORE + uint32_t u32Timeout = 0; +#endif + +#ifndef SEMAPHORE_CMD + uint32_t u32CmdTimeout = 0; +#endif + + /*Returns from various function calls*/ + en_sdio_result_t enRet = Error; + en_sdio_result_t enRetTmp = Ok; + + /*Hold value of if these checks are needed*/ + uint8_t bCmdIndexCheck; + uint8_t bCmdCrcCheck; + static uint8_t u8responseBuf[6]; + + /*Clear statuses*/ + gstcInternalData.stcEvents.u8CmdComplete = 0; + gstcInternalData.stcEvents.u8TransComplete = 0; + gstcInternalData.stcEvents.u8CRCError = 0; + + /*Setup the command configuration*/ + stcCmdConfig.u8CmdIndex = (uint8_t)pstcCmd->u32CmdIdx; + stcCmdConfig.u32Argument = pstcCmd->u32Arg; + + /*Determine the type of response and if we need to do any checks*/ + /*Command 0 and 8 have no response, so don't wait for one*/ + if (pstcCmd->u32CmdIdx == 0 || pstcCmd->u32CmdIdx == 8) + { + bCmdIndexCheck = false; + bCmdCrcCheck = false; + stcCmdConfig.bResponseRequired = false; + stcCmdConfig.pu8ResponseBuf = NULL; + } + + /*Command 5's response doesn't have a CRC or index, so don't check*/ + else if (pstcCmd->u32CmdIdx == 5) + { + bCmdIndexCheck = false; + bCmdCrcCheck = false; + stcCmdConfig.bResponseRequired = true; + stcCmdConfig.pu8ResponseBuf = u8responseBuf; + } + /*Otherwise check everything*/ + else + { + bCmdIndexCheck = true; + bCmdCrcCheck = true; + stcCmdConfig.bResponseRequired = true; + stcCmdConfig.pu8ResponseBuf = u8responseBuf; + } + + /*Check if the command is 53, if it is then setup the data transfer*/ + if (pstcCmd->u32CmdIdx == 53) + { + /*Set the number of blocks in the global struct*/ + stcDataConfig.u16BlockCount = (uint16_t)pstcCmd->u16BlockCnt; + /*Set the size of the data transfer*/ + stcDataConfig.u16BlockSize = (uint16_t)pstcCmd->u16BlockSize; + /*Set the direction are we reading or writing*/ + stcDataConfig.bRead = pstcCmd->bRead; + /*Set the pointer for the data*/ + stcDataConfig.pu8Data = pstcCmd->pu8Data; + + /*Get the data Transfer Ready*/ + SDIO_InitDataTransfer(&stcDataConfig); + + /*Set bit saying this was a CMD_53*/ + SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_INT; + } + + /*Send the command*/ + SDIO_SendCommand(&stcCmdConfig); + + /*Wait for the command to finish*/ + do + { + //TODO: Use RTOS timeout + u32CmdTimeout++; + enRetTmp = SDIO_CheckForEvent(SdCmdEventCmdDone); + + } while ((enRetTmp != Ok) && (u32CmdTimeout < SDIO_CMD_TIMEOUT)); + + + if (u32CmdTimeout == SDIO_CMD_TIMEOUT) + { + enRet |= CMDTimeout; + } + else /*CMD Passed*/ + { + /*If a response is expected check it*/ + if (stcCmdConfig.bResponseRequired == true) + { + enRetTmp = SDIO_GetResponse(bCmdCrcCheck, bCmdIndexCheck, (uint8_t)pstcCmd->u32CmdIdx, pstcCmd->pu32Response, u8responseBuf); + if (enRetTmp != Ok) + { + enRet |= enRetTmp; + } + else /*Response good*/ + { + /*if it was command 53, check the response to ensure there was no error*/ + if ((pstcCmd->u32CmdIdx) == 53) + { + /*Make sure none of the error bits are set*/ + if (*(pstcCmd->pu32Response) & 0x0000cf00) + { + enRet |= ResponseFlagError; + } + else /*CMD53 Response good*/ + { + /*If it was command 53 and it was a write enable the write*/ + if (pstcCmd->bRead == false && enRet == Error) + { + Cy_DMA_Channel_Disable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL ); + Cy_DMA_Channel_Disable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); + Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); + + /*Set the flag in the control register to enable the write*/ + Cy_DMA_Channel_Enable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); + /*Enable the channel*/ + Cy_SysLib_DelayCycles(35); + SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_WRITE; + } + +#ifndef SEMAPHORE + /*Wait for the transfer to finish*/ + do + { + + u32Timeout++; + enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone); + + } while (!((enRetTmp == Ok) || (enRetTmp == DataCrcError) || (u32Timeout >= SDIO_DAT_TIMEOUT))); + + /*if it was a read it is possible there is still extra data hanging out, trigger the + DMA again. This can result in extra data being transfered so the read buffer should be + 3 bytes bigger than needed*/ + if (pstcCmd->bRead == true) + { + Cy_TrigMux_SwTrigger((uint32_t)SDIO_HOST_Read_DMA_DW__TR_IN, 2); + } + + if (u32Timeout == SDIO_DAT_TIMEOUT) +#else + result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false ); + enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone); + + /* if it was a read it is possible there is still extra data hanging out, trigger the + DMA again. This can result in extra data being transfered so the read buffer should be + 3 bytes bigger than needed*/ + if (pstcCmd->bRead == true) + { + Cy_TrigMux_SwTrigger((uint32_t)SDIO_HOST_Read_DMA_DW__TR_IN, 2); + } + + if (result != Ok) +#endif + { + enRet |= DataTimeout; + } + + if (enRetTmp == DataCrcError) + { + enRet |= DataCrcError; + } + }/*CMD53 response good*/ + }/*Not a CMD53*/ + } /*Response Good*/ + } /*No Response Required, thus no CMD53*/ + } /*CMD Passed*/ + + +#ifndef SEMAPHORE + u32Timeout = 0; +#endif + + /*If there were no errors then indicate transfer was okay*/ + if (enRet == Error) + { + enRet = Ok; + } + + /*reset CmdTimeout value*/ + u32CmdTimeout = 0; + + /*Always Reset on exit to clean up*/ + Cy_DMA_Channel_Disable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL ); + Cy_DMA_Channel_Disable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); + Cy_DMA_Channel_Disable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL ); + Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); + /*No longer a CMD_53*/ + SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_INT | SDIO_CTRL_ENABLE_WRITE | SDIO_CTRL_ENABLE_READ); + SDIO_Reset(); + + return enRet; +} + + +/******************************************************************************* +* Function Name: SDIO_CheckForEvent +****************************************************************************//** +* +* Checks to see if a specific event has occurred such a command complete or +* transfer complete. +* +* \param enEventType +* The type of event to check for. See \ref en_sdio_event_t. +* +* \return +* \ref en_sdio_result_t +* +*******************************************************************************/ +en_sdio_result_t SDIO_CheckForEvent(en_sdio_event_t enEventType) +{ + en_sdio_result_t enRet = Error; + + /*Disable Interrupts while modifying the global*/ + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); + + /*Switch the event to check*/ + switch ( enEventType ) + { + /*If the command is done clear the flag*/ + case SdCmdEventCmdDone: + if (gstcInternalData.stcEvents.u8CmdComplete > 0) + { + gstcInternalData.stcEvents.u8CmdComplete = 0; + enRet = Ok; + } + break; + + /*If the transfer is done check for CRC Error and clear the flag*/ + case SdCmdEventTransferDone: + if (gstcInternalData.stcEvents.u8TransComplete > 0) + { + gstcInternalData.stcEvents.u8TransComplete = 0; + enRet = Ok; + } + /*Check for CRC error and set flags*/ + if (gstcInternalData.stcEvents.u8CRCError > 0) + { + enRet = DataCrcError; + gstcInternalData.stcEvents.u8CRCError = 0; + } + break; + } + + /*Re-enable Interrupts*/ + NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); + return enRet; +} + + +/******************************************************************************* +* Function Name: SDIO_CalculateCrc7 +****************************************************************************//** +* +* Calculate the 7 bit CRC for the command channel +* +* \param pu8Data +* Data to calculate CRC on +* +* \param u8Size +* Number of bytes to calculate CRC on +* +* \return +* CRC +* +* \note +* This code was copied from +* http://www.barrgroup.com/Embedded-Systems/How-To/CRC-Calculation-C-Code +* +*******************************************************************************/ +uint8_t SDIO_CalculateCrc7(uint8_t* pu8Data, uint8_t u8Size) +{ + uint8_t data; + uint8_t remainder = 0; + uint32_t byte; + + for(byte = 0; byte < u8Size; ++byte) + { + data = pu8Data[byte] ^ remainder; + remainder = crcTable[data] ^ (remainder << 8); + } + + return (remainder>>1); +} + + +/******************************************************************************* +* Function Name: SDIO_Crc7Init +****************************************************************************//** +* +* Initialize 7-bit CRC Table +* +* \note +* This code was copied from +* http://www.barrgroup.com/Embedded-Systems/How-To/CRC-Calculation-C-Code +* +*******************************************************************************/ +void SDIO_Crc7Init(void) +{ + uint8_t remainder; + uint8_t bit; + uint32_t dividend; + + for(dividend = 0; dividend < 256; ++dividend) + { + remainder = dividend; + + for(bit = 8; bit > 0; --bit) + { + if (remainder & SDIO_CRC_UPPER_BIT) + { + remainder = (remainder << 1) ^ SDIO_CRC7_POLY; + } + else + { + remainder = (remainder << 1); + } + } + + crcTable[dividend] = (remainder); + } +} + + +/******************************************************************************* +* Function Name: SDIO_SetBlockSize +****************************************************************************//** +* +* Sets the size of each block +* +* \param u8ByteCount +* Size of the block +* +*******************************************************************************/ +void SDIO_SetBlockSize(uint8_t u8ByteCount) +{ + SDIO_BYTE_COUNT_REG = u8ByteCount; +} + + +/******************************************************************************* +* Function Name: SDIO_SetNumBlocks +****************************************************************************//** +* +* Sets the number of blocks to send +* +* \param u8ByteCount +* Size of the block +* +*******************************************************************************/ +void SDIO_SetNumBlocks(uint8_t u8BlockCount) +{ + SDIO_DATA_BLOCK_COUNTER_A0_REG = u8BlockCount; + SDIO_DATA_BLOCK_COUNTER_D0_REG = u8BlockCount; + /*The one is used so that we can do 256 bytes*/ + SDIO_DATA_BLOCK_COUNTER_A1_REG = 1; + SDIO_DATA_BLOCK_COUNTER_D1_REG = 1; +} + + +/******************************************************************************* +* Function Name: SDIO_EnableIntClock +****************************************************************************//** +* +* Enable Internal clock for the block +* +*******************************************************************************/ +void SDIO_EnableIntClock(void) +{ + SDIO_CONTROL_REG |= SDIO_CTRL_INT_CLK; + Cy_SysClk_PeriphEnableDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM); +} + + +/******************************************************************************* +* Function Name: SDIO_DisableIntClock +****************************************************************************//** +* +* Enable Disable clock for the block +* +*******************************************************************************/ +void SDIO_DisableIntClock(void) +{ + SDIO_CONTROL_REG &= ~SDIO_CTRL_INT_CLK; + Cy_SysClk_PeriphDisableDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM); +} + + +/******************************************************************************* +* Function Name: SDIO_EnableSdClk +****************************************************************************//** +* +* Enable SD Clock out to pin +* +*******************************************************************************/ +void SDIO_EnableSdClk(void) +{ + SDIO_CONTROL_REG |= SDIO_CTRL_SD_CLK; +} + + +/******************************************************************************* +* Function Name: SDIO_DisableSdClk +****************************************************************************//** +* +* Disable SD Clock out to the pin +* +*******************************************************************************/ +void SDIO_DisableSdClk(void) +{ + SDIO_CONTROL_REG &= ~SDIO_CTRL_SD_CLK; +} + + +/******************************************************************************* +* Function Name: SDIO_SetSdClkFrequency +****************************************************************************//** +* +* Sets the frequency of the SD Clock +* +* \param u32SdClkFreqHz +* Frequency of SD Clock in Hz. +* +* \note +* Only an integer divider is used, so the desired frequency may not be meet +*******************************************************************************/ +void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz) +{ + uint16_t u16Div; + u16Div = Cy_SysClk_ClkPeriGetFrequency() / u32SdClkFreqHz; + Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, (u16Div-1)); +} + + +/******************************************************************************* +* Function Name: SDIO_SetupDMA +****************************************************************************//** +* +* Configures the DMA for the SDIO block +* +*******************************************************************************/ +void SDIO_SetupDMA(void) +{ + /*Set the number of bytes to send*/ + SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config.xCount = (SDIO_NUM_RESP_BYTES - 1); + /*Set the destination address*/ + SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config.dstAddress = (void*)SDIO_CMD_COMMAND_PTR; + + /*Initialize descriptor for cmd channel*/ + Cy_DMA_Descriptor_Init(&cmdDesr, &SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config); + + /*Set flag to disable descriptor when done*/ + cmdDesr.ctl |= 0x01000000; + + /*Configure channel*/ + /*CMD channel can be preempted, and has lower priority*/ + cmdChannelConfig.descriptor = &cmdDesr; + cmdChannelConfig.preemptable = 1; + cmdChannelConfig.priority = 1; + cmdChannelConfig.enable = 0u; + + /*Configure Channel with initial Settings*/ + Cy_DMA_Channel_Init(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL, &cmdChannelConfig); + + /*Enable DMA block*/ + Cy_DMA_Enable(SDIO_HOST_CMD_DMA_HW); + + /*Set the number of bytes to receive*/ + SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config.xCount = SDIO_NUM_RESP_BYTES; + /*Set the source address*/ + SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config.srcAddress = (void*)SDIO_CMD_RESPONSE_PTR; + + /*Initialize descriptor for response channel*/ + Cy_DMA_Descriptor_Init(&respDesr, &SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config); + + /*Set flag to disable descriptor when done*/ + respDesr.ctl |= 0x01000000; + + /*Configure channel*/ + /*response channel can be preempted, and has lower priority*/ + respChannelConfig.descriptor = &respDesr; + respChannelConfig.preemptable = 1; + respChannelConfig.priority = 1; + respChannelConfig.enable = 0u; + + /*Configure Channel with initial Settings*/ + Cy_DMA_Channel_Init(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL, &respChannelConfig); + /*Enable DMA block*/ + Cy_DMA_Enable(SDIO_HOST_Resp_DMA_HW); + + /*Set the destination address*/ + SDIO_HOST_Write_DMA_Write_DMA_Desc_config.dstAddress = (void*)SDIO_DAT_WRITE_PTR; + + /*Initialize descriptor for write channel*/ + Cy_DMA_Descriptor_Init(&writeDesr0, &SDIO_HOST_Write_DMA_Write_DMA_Desc_config); + Cy_DMA_Descriptor_Init(&writeDesr1, &SDIO_HOST_Write_DMA_Write_DMA_Desc_config); + + /*Configure channel*/ + /*write channel cannot be preempted, and has highest priority*/ + writeChannelConfig.descriptor = &writeDesr0; + writeChannelConfig.preemptable = 0; + writeChannelConfig.priority = 0; + writeChannelConfig.enable = 0u; + + /*Configure Channel with initial Settings*/ + Cy_DMA_Channel_Init(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL, &writeChannelConfig); + + /*Enable the interrupt*/ + Cy_DMA_Channel_SetInterruptMask(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL,CY_DMA_INTR_MASK); + + /*Enable DMA block*/ + Cy_DMA_Enable(SDIO_HOST_Write_DMA_HW); + + /*Set the source address*/ + SDIO_HOST_Read_DMA_Read_DMA_Desc_config.srcAddress = (void*)SDIO_DAT_READ_PTR; + /*Initialize descriptor for read channel*/ + Cy_DMA_Descriptor_Init(&readDesr0, &SDIO_HOST_Read_DMA_Read_DMA_Desc_config); + Cy_DMA_Descriptor_Init(&readDesr1, &SDIO_HOST_Read_DMA_Read_DMA_Desc_config); + + /*Configure channel*/ + /*read channel cannot be preempted, and has highest priority*/ + readChannelConfig.descriptor = &readDesr0; + readChannelConfig.preemptable = 0; + readChannelConfig.priority = 0; + readChannelConfig.enable = 0u; + + /*Configure Channel with initial Settings*/ + Cy_DMA_Channel_Init(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL, &readChannelConfig); + + /*Enable the interrupt*/ + Cy_DMA_Channel_SetInterruptMask(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL,CY_DMA_INTR_MASK); + + /*Enable DMA block*/ + Cy_DMA_Enable(SDIO_HOST_Read_DMA_HW); +} + + +/******************************************************************************* +* Function Name: SDIO_Reset +****************************************************************************//** +* +* Reset the SDIO interface +* +*******************************************************************************/ +void SDIO_Reset(void) +{ + /*Control register is in pulse mode, so this just pulses the reset*/ + SDIO_CONTROL_REG |= (SDIO_CTRL_RESET_DP); +} + + +/******************************************************************************* +* Function Name: SDIO_EnableChipInt +****************************************************************************//** +* +* Enables the SDIO Chip Int by setting the mask bit +* +*******************************************************************************/ +void SDIO_EnableChipInt(void) +{ + SDIO_STATUS_INT_MSK |= SDIO_STS_CARD_INT; +} + + +/******************************************************************************* +* Function Name: SDIO_DisableChipInt +****************************************************************************//** +* +* Enables the SDIO Chip Int by setting the mask bit +* +*******************************************************************************/ +void SDIO_DisableChipInt(void) +{ + SDIO_STATUS_INT_MSK &= ~SDIO_STS_CARD_INT; +} + + +/******************************************************************************* +* Function Name: SDIO_IRQ +****************************************************************************//** +* +* SDIO interrupt, checks for events, and calls callbacks +* +*******************************************************************************/ +void SDIO_IRQ(void) +{ + uint8_t u8Status; + + /*first read the status register*/ + u8Status = SDIO_STATUS_REG; + + /*Check card interrupt*/ + if (u8Status & SDIO_STS_CARD_INT ) + { + if (NULL != gstcInternalData.pstcCallBacks.pfnCardIntCb) + { + gstcInternalData.pstcCallBacks.pfnCardIntCb(); + } + } + + /*If the command is complete set the flag*/ + if (u8Status & SDIO_STS_CMD_DONE) + { + gstcInternalData.stcEvents.u8CmdComplete++; + } + + /*Check if a write is complete*/ + if (u8Status & SDIO_STS_WRITE_DONE ) + { + + /*Clear the Write flag and CMD53 flag*/ + SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_WRITE | SDIO_CTRL_ENABLE_INT); + + /*Check if the CRC status return was bad*/ + if (u8Status & SDIO_STS_CRC_ERR ) + { + /*CRC was bad, set the flag*/ + gstcInternalData.stcEvents.u8CRCError++; + } + /*set the done flag*/ +#ifdef SEMAPHORE + cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true ); +#else + gstcInternalData.stcEvents.u8TransComplete++; +#endif + } + + /*Check if a read is complete*/ + if (u8Status & SDIO_STS_READ_DONE) + { + /*Clear the read flag*/ + SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_READ| SDIO_CTRL_ENABLE_INT); + + /*check the CRC*/ + if (u8Status & SDIO_STS_CRC_ERR) + { + /*CRC was bad, set the flag*/ + gstcInternalData.stcEvents.u8CRCError++; + } + /*Okay we're done so set the done flag*/ +#ifdef SEMAPHORE + cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true ); +#else + gstcInternalData.stcEvents.u8TransComplete++; +#endif + } + + NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); +} + + +void SDIO_READ_DMA_IRQ(void) +{ + /*Shouldn't have to change anything unless it is the last descriptor*/ + + /*If the current descriptor is 0, then change descriptor 1*/ + if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL) == &readDesr0) + { + /*We need to increment the destination address every time*/ + readDesr1.dst += 2048; + + /*If this is the last descriptor*/ + if ((yCounts == 1) && (yCountRemainder == 0)) + { + /* In this case all we need to change is the next descriptor and disable*/ + readDesr1.nextPtr = 0; + readDesr1.ctl |= 0x01000000; + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + else if (yCounts == 0 && (yCountRemainder > 0)) + { + /*change next descriptor, and disable*/ + readDesr1.nextPtr = 0; + readDesr1.ctl |= 0x01000000; + /*Also change the yCount*/ + readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder-1)) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + } + + /*If the current descriptor is 1, then change descriptor 0*/ + if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL) == &readDesr1) + { + /*We need to increment the destination address everytime*/ + readDesr0.dst += 2048; + + /*If this is the last descriptor*/ + if ((yCounts == 1) && (yCountRemainder == 0)) + { + /* In this case all we need to change is the next descriptor and disable*/ + readDesr0.nextPtr = 0; + readDesr0.ctl |= 0x01000000; + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + else if (yCounts == 0 && (yCountRemainder > 0)) + { + /*change next descriptor, and disable*/ + readDesr0.nextPtr = 0; + readDesr0.ctl |= 0x01000000; + /*Also change the yCount*/ + readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder-1)) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + } + + /*Clear the interrupt*/ + Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL); + /*decrement y counts*/ + yCounts--; +} + + +void SDIO_WRITE_DMA_IRQ(void) +{ + /*We shouldn't have to change anything unless it is the last descriptor*/ + + /*If the current descriptor is 0, then change descriptor 1*/ + if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL) == &writeDesr0) + { + /*We also need to increment the destination address every-time*/ + writeDesr1.src += 2048; + + /*If this is the last descriptor*/ + if ((yCounts == 1) && (yCountRemainder == 0)) + { + /* In this case all we need to change is the next descriptor and disable*/ + writeDesr1.nextPtr = 0; + writeDesr1.ctl |= 0x01000000; + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + + } + else if (yCounts == 0 && (yCountRemainder > 0)) + { + /*change next descriptor, and disable*/ + writeDesr1.nextPtr = 0; + writeDesr1.ctl |= 0x01000000; + /*Also change the yCount*/ + writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder -1)) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + } + } + + /*If the current descriptor is 1, then change descriptor 0*/ + if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL) == &writeDesr1) + { + /*We also need to increment the destination address*/ + writeDesr0.src += 2048; + /*If this is the last descriptor*/ + if ((yCounts == 1) && (yCountRemainder == 0)) + { + /* In this case all we need to change is the next descriptor and disable*/ + writeDesr0.nextPtr = 0; + writeDesr0.ctl |= 0x01000000; + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + } + else if (yCounts == 0 && (yCountRemainder > 0)) + { + /*change next descriptor, and disable*/ + writeDesr0.nextPtr = 0; + writeDesr0.ctl |= 0x01000000; + /*Also change the yCount*/ + writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder -1)) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + } + } + + /*Clear the interrupt*/ + Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); + yCounts--; +} + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.h new file mode 100644 index 0000000000..f63649e38c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.h @@ -0,0 +1,404 @@ +/***************************************************************************//** +* \file SDIO_HOST.h +* \version 1.00 +* +* \brief +* This file provides types definition, constants and function definition for +* the SDIO driver. +* +******************************************************************************* +* \copyright +* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +******************************************************************************* +* \addtogroup group_udb_sdio_changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+*******************************************************************************/ + +/** +* \defgroup group_udb_sdio UDB_SDIO +* \ingroup group_bsp +* \{ +* SDIO - Secure Digital Input Output Is a standard for communicating with various + external devices such as Wifi and bluetooth devices. +* \{ +* \defgroup group_udb_sdio_general_description General Description +* \defgroup group_udb_sdio_changelog Changelog +* \} +* \defgroup group_udb_sdio_API API Reference +* \{ +* \defgroup group_udb_sdio_macros Macros +* \defgroup group_udb_sdio_functions Functions +* \defgroup group_udb_sdio_data_structures Data Structures +* \} +*/ + +/** +* \addtogroup group_udb_sdio_general_description +* \section group_udb_sdio_section_overview Overview +* This driver is currently designed to only support communication with certain +* Broadcom Wifi and Bluetooth chipsets, it is not designed to work with a general +* SDIO card, or even and SD card. Consult TDU#315 for information on limitations +* +* \section group_udb_sdio_section_configuration_considerations Configuration Considerations +* Features: +* * Always Four Wire Mode +* * Supports Card Interrupt +* * Uses DMA for command and data transfer +** +* \section group_udb_sdio_section_more_information More Information +* +* \} group_udb_sdio_general_description +*/ + +#if !defined(CY_SDIO_H) +#define CY_SDIO_H + +#include "SDIO_HOST_cfg.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*************************************** +* API Constants +***************************************/ + +/** +* \addtogroup group_udb_sdio_macros +* \{ +*/ + +#define SDIO_CMD_TIMEOUT (100000u) /**< Value used for firmware timeout*/ +#define SDIO_DAT_TIMEOUT (500000u) /**< Value used for firmware timeout*/ +#define SDIO_SRC_CLK_FREQ_HZ (10000000u) /**< Frequency of CLK_PERI*/ +#define SDIO_ENABLE_CNT (0x20u) /**< Bit to set in Aux Ctrl reg to enable 7 bit counters.*/ + +/*! +\defgroup group_sdio_cmd_constants Constants for the command channel +*/ +/* @{*/ +#define SDIO_HOST_DIR (0x40u) /**< Direction bit set in command */ +#define SDIO_CMD_END_BIT (0x01u) /**< End bit set in command*/ +#define SDIO_NUM_CMD_BYTES (6u) /**< Number of command bytes to send*/ +#define SDIO_NUM_RESP_BYTES (6u) /**< Number of response bytes to receive*/ +/*@} group_sdio_cmd_constants */ + +/*! +\defgroup group_sdio_ctrl_reg SDIO control register bits +*/ +/* @{*/ +#define SDIO_CTRL_INT_CLK (0x01u) /**< Enable the internal clock running the SDIO block*/ +#define SDIO_CTRL_SD_CLK (0x02u) /**< Enable the the SD Clock*/ +#define SDIO_CTRL_ENABLE_WRITE (0x04u) /**< Enable a write, should not be set if ENABLE_READ is set*/ +#define SDIO_CTRL_ENABLE_READ (0x08u) /**< Enable a read, should not be set if ENABLE_WRITE is set*/ +#define SDIO_CTRL_SKIP_RESPONSE (0x10u) /**< If set no response is required for the command*/ +#define SDIO_CTRL_RESET (0x20u) /**< If set the SDIO interface is reset*/ +#define SDIO_CTRL_RESET_DP (0x40u) /**< If set the SDIO interface is reset*/ +#define SDIO_CTRL_ENABLE_INT (0x80u) /**< Enables logic to detect card interrupt*/ +/*@} group_sdio_ctrl_reg */ + +/*! +\defgroup group_sdio_status_reg SDIO status register bits +*/ +/* @{*/ +#define SDIO_STS_CMD_DONE (0x01u) /**< The command is done*/ +#define SDIO_STS_WRITE_DONE (0x02u) /**< All data for a write has been sent*/ +#define SDIO_STS_READ_DONE (0x04u) /**< All data for a read has been read*/ +#define SDIO_STS_CRC_ERR (0x08u) /**< A CRC error was detected during a read or write*/ +#define SDIO_STS_CMD_IDLE (0x10u) /**< The command channel is idle*/ +#define SDIO_STS_DAT_IDLE (0x20u) /**< The data channel is idle*/ +#define SDIO_STS_CARD_INT (0x40u) /**< The SDIO card indicated an interrupt by driving DAT[1] low*/ +/*@} group_sdio_status_reg */ + +/*! +\defgroup group_sdio_crc Constants for 7bit CRC for command +*/ +/* @{*/ +#define SDIO_CRC7_POLY (0x12u) /**< Value of CRC polynomial*/ +#define SDIO_CRC_UPPER_BIT (0x80u) /**< Upper bit to test if it is high*/ +/*@} group_sdio_crc */ + +/** \} group_udb_sdio_macros */ + + +/*************************************** +* Type Definitions +***************************************/ + +/** +* \addtogroup group_udb_sdio_data_structures +* \{ +*/ + +/** +* Create a type for the card interrupt call back +*/ +typedef void (* sdio_card_int_cb_t)(void); + +/** +* \brief This enum is used when checking for specific events +*/ +typedef enum en_sdio_event +{ + SdCmdEventCmdDone = (1u), /**< Check to see if a command is done*/ + SdCmdEventTransferDone = (2u) /**< Check to see if a transfer is done*/ + +}en_sdio_event_t; + +/** +* \brief Used to indicate the result of a function +*/ +typedef enum en_sdio_result +{ + Ok = 0x00, /**< No error*/ + Error = 0x01, /**< Non-specific error code*/ + CommandCrcError = 0x02, /**< There was a CRC error on the Command/Response*/ + CommandIdxError = 0x04, /**< The index for the command didn't match*/ + CommandEndError = 0x08, /**< There was an end bit error on the command*/ + DataCrcError = 0x10, /**< There was a data CRC Error*/ + CMDTimeout = 0x20, /**< The command didn't finish before the timeout period was over*/ + DataTimeout = 0x40, /**< The data didn't finish before the timeout period was over*/ + ResponseFlagError = 0x80 /**< There was an error in the response flag for command 53*/ + +} en_sdio_result_t; + +/** +* \brief Flags used to indicate an event occurred, set in the interrupt, cleared in the check events function +*/ +typedef struct stc_sdcmd_event_flag +{ + uint8_t u8CmdComplete; /**< If non-zero a command has completed*/ + uint8_t u8TransComplete; /**< If non-zero a transfer has completed*/ + uint8_t u8CRCError; /**< If non-zero a CRC error was detected in a data transfer*/ + +}stc_sdio_event_flag_t; + +/** +* \brief Holds pointers to callback functions +*/ +typedef struct stc_sdio_irq_cb +{ + sdio_card_int_cb_t pfnCardIntCb; /**< Pointer to card interrupt callback function*/ +}stc_sdio_irq_cb_t; + +/** +* \brief Global structure used to hold data from interrupt and other functions +*/ +typedef struct stc_sdio_gInternalData +{ + stc_sdio_irq_cb_t pstcCallBacks; /**< Holds pointers to all the call back functions*/ + stc_sdio_event_flag_t stcEvents; /**< Holds all of the event count flags, set in interrupt used in check events*/ +}stc_sdio_gInternalData_t; + +/** +* \brief structure used for configuring command +*/ +typedef struct stc_sdio_cmd_config +{ + uint8_t u8CmdIndex; /**< Command index*/ + uint32_t u32Argument; /**< The argument of command */ + uint8_t bResponseRequired; /**< TRUE: A Response is required*/ + uint8_t *pu8ResponseBuf; /**< Pointer to location to store response*/ + +}stc_sdio_cmd_config_t; + +/** +* \brief structure used for the data channel +*/ +typedef struct stc_sdio_data_config +{ + uint8_t bRead; /**< TRUE: Read, FALSE: write*/ + uint16_t u16BlockSize; /**< Block size*/ + uint16_t u16BlockCount; /**< Holds the number of blocks to send*/ + uint8_t *pu8Data; /**< Pointer data buffer*/ + +}stc_sdio_data_config_t; + +/** +* \brief structure used for configuring command and data +*/ +typedef struct stc_sdio_cmd +{ + uint32_t u32CmdIdx; /**< Command index*/ + uint32_t u32Arg; /**< The argument of command*/ + uint32_t *pu32Response; /**< Pointer to location to store response*/ + uint8_t *pu8Data; /**< Pointer data buffer*/ + uint8_t bRead; /**< TRUE: Read, FALSE: write*/ + uint16_t u16BlockCnt; /**< Number of blocks to send*/ + uint16_t u16BlockSize; /**< Block size*/ +}stc_sdio_cmd_t; + +/** \} group_udb_sdio_data_structures */ + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_udb_sdio_functions +* \{ +*/ + +/** \cond INTERNAL */ + +/* Main functions*/ +void SDIO_Init(stc_sdio_irq_cb_t* pfuCb); +en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd); +void SDIO_EnableIntClock(void); +void SDIO_DisableIntClock(void); +void SDIO_EnableSdClk(void); +void SDIO_DisableSdClk(void); +void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz); +void SDIO_Reset(void); +void SDIO_EnableChipInt(void); +void SDIO_DisableChipInt(void); + +/*Low Level Functions*/ +void SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig); +en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, uint8_t u8CmdIdx, uint32_t* pu32Response, uint8_t* pu8ResponseBuf); +void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig); +en_sdio_result_t SDIO_CheckForEvent(en_sdio_event_t enEventType); +uint8_t SDIO_CalculateCrc7(uint8_t* pu8Data, uint8_t pu8Size); +void SDIO_SetBlockSize(uint8_t u8ByteCount); +void SDIO_SetNumBlocks(uint8_t u8BlockCount); +en_sdio_result_t SDIO_CheckReadCRC(void); + +/*DMA setup function*/ +void SDIO_SetupDMA(void); + +/*Interrupt Function*/ +void SDIO_IRQ(void); +void SDIO_READ_DMA_IRQ(void); +void SDIO_WRITE_DMA_IRQ(void); + +void SDIO_Crc7Init(void); + +/** \endcond */ + +/** \} group_udb_sdio_functions */ + + +/*************************************** +* Hardware Registers +***************************************/ + +/** \cond INTERNAL */ + +#define SDIO_CONTROL_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG) + +#define SDIO_CONTROL_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG) + +#define SDIO_STATUS_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_StatusReg__STATUS_REG) + +#define SDIO_STATUS_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_StatusReg__STATUS_REG) + +#define SDIO_STATUS_INT_MSK (* (reg8*) \ +SDIO_HOST_bSDIO_StatusReg__MASK_REG) + +#define SDIO_STATUS_AUX_CTL (* (reg8 *) \ +SDIO_HOST_bSDIO_StatusReg__STATUS_AUX_CTL_REG) + +#define SDIO_CMD_BIT_CNT_CONTROL_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_CMD_BIT_CNT_CONTROL_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_WRITE_CRC_CNT_CONTROL_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_WRITE_CRC_CNT_CONTROL_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_BYTE_CNT_CONTROL_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_BYTE_CNT_CONTROL_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_CRC_BIT_CNT_CONTROL_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_CRC_BIT_CNT_CONTROL_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_DATA_BLOCK_COUNTER_A0_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__A0_REG) + +#define SDIO_DATA_BLOCK_COUNTER_A0_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__A0_REG) + +#define SDIO_DATA_BLOCK_COUNTER_D0_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__D0_REG) + +#define SDIO_DATA_BLOCK_COUNTER_D0_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__D0_REG) + +#define SDIO_DATA_BLOCK_COUNTER_A1_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__A1_REG) + +#define SDIO_DATA_BLOCK_COUNTER_A1_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__A1_REG) + +#define SDIO_DATA_BLOCK_COUNTER_D1_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__D1_REG) + +#define SDIO_DATA_BLOCK_COUNTER_D1_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__D1_REG) + +#define SDIO_CMD_COMMAND_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_CMD__F0_REG) + +#define SDIO_CMD_COMMAND_A0_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_CMD__A0_REG) + +#define SDIO_CMD_COMMAND_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_CMD__F0_REG) + +#define SDIO_CMD_RESPONSE_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_CMD__F1_REG) + +#define SDIO_CMD_RESPONSE_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_CMD__F1_REG) + +#define SDIO_DAT_WRITE_REG (* (reg16 *) \ +SDIO_HOST_bSDIO_Write_DP__F0_F1_REG) + +#define SDIO_DAT_WRITE_PTR ( (reg16 *) \ +SDIO_HOST_bSDIO_Write_DP__F0_F1_REG) + +#define SDIO_DAT_READ_REG (* (reg16 *) \ +SDIO_HOST_bSDIO_Read_DP__F0_F1_REG) + +#define SDIO_DAT_READ_PTR ( (reg16 *) \ +SDIO_HOST_bSDIO_Read_DP__F0_F1_REG) + +#define SDIO_BYTE_COUNT_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_byteCounter__PERIOD_REG) + +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +#endif /* (CY_SDIO_H) */ + +/** \} group_udb_sdio */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.c new file mode 100644 index 0000000000..fced70b846 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.c @@ -0,0 +1,1018 @@ +#include "SDIO_HOST_cfg.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/***************************CMD DMA Config Struct****************************/ +cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config = +{ + .retrigger = CY_DMA_RETRIG_16CYC, + .interruptType = CY_DMA_1ELEMENT, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_1ELEMENT, + .dataSize = CY_DMA_BYTE, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_1D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 1L, + .dstXincrement = 0L, + .xCount = 5UL, + .srcYincrement = 0L, + .dstYincrement = 0L, + .yCount = 1UL, + .nextDescriptor = NULL +}; + +cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL +}; + +/***************************Read DMA Config Struct****************************/ +cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config = +{ + .retrigger = CY_DMA_RETRIG_IM, + .interruptType = CY_DMA_DESCR, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_X_LOOP, + .dataSize = CY_DMA_HALFWORD, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_2D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 0L, + .dstXincrement = 2L, + .xCount = 10UL, + .srcYincrement = 0L, + .dstYincrement = 10L, + .yCount = 2UL, + .nextDescriptor = NULL +}; + +cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL +}; + +/***************************Resp DMA Config Struct****************************/ +cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config = +{ + .retrigger = CY_DMA_RETRIG_IM, + .interruptType = CY_DMA_1ELEMENT, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_1ELEMENT, + .dataSize = CY_DMA_BYTE, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_1D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 0L, + .dstXincrement = 1L, + .xCount = 6UL, + .srcYincrement = 0L, + .dstYincrement = 0L, + .yCount = 1UL, + .nextDescriptor = NULL +}; + +cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL +}; + +/***************************Write DMA Config Struct****************************/ +cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config = +{ + .retrigger = CY_DMA_RETRIG_4CYC, + .interruptType = CY_DMA_DESCR, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_X_LOOP, + .dataSize = CY_DMA_HALFWORD, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_2D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 2L, + .dstXincrement = 0L, + .xCount = 10UL, + .srcYincrement = 10L, + .dstYincrement = 0L, + .yCount = 2UL, + .nextDescriptor = NULL +}; + +cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL +}; + + + +/***************UDB Config code *****************/ + +#define CY_CFG_BASE_ADDR_COUNT 12u + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) + #define CYPACKED + #define CYPACKED_ATTR __attribute__ ((packed)) + #define CY_CFG_UNUSED __attribute__ ((unused)) + + +#elif defined(__ICCARM__) + #include + + #define CYPACKED __packed + #define CYPACKED_ATTR + #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") + + +#else + #error Unsupported toolchain +#endif + + +#ifndef CYCODE + #define CYCODE +#endif +#ifndef CYFAR + #define CYFAR +#endif + + +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n); +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n) +{ + (void)memset(s, 0, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} + +CYPACKED typedef struct +{ + uint8 offset; + uint8 value; +} CYPACKED_ATTR cy_cfg_addrvalue_t; + + +/******************************************************************************* +* Function Name: cfg_write_bytes32 +******************************************************************************** +* Summary: +* This function is used for setting up the chip configuration areas that +* contain relatively sparse data. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ + +static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]); +static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]) +{ + /* For 32-bit little-endian architectures */ + uint32 i, j = 0u; + for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) + { + uint32 baseAddr = addr_table[i]; + uint8 count = (uint8)baseAddr; + baseAddr &= 0xFFFFFF00u; + while (count != 0u) + { + CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value); + j++; + count--; + } + } +} + +static const uint32 CYCODE cy_cfg_addr_table[] = +{ + 0x40340002u, /* Base address: 0x40340000 Count: 2 */ + 0x4034010Au, /* Base address: 0x40340100 Count: 10 */ + 0x40340301u, /* Base address: 0x40340300 Count: 1 */ + 0x40340405u, /* Base address: 0x40340400 Count: 5 */ + 0x40342466u, /* Base address: 0x40342400 Count: 102 */ + 0x40342632u, /* Base address: 0x40342600 Count: 50 */ + 0x4034282Bu, /* Base address: 0x40342800 Count: 43 */ + 0x40342A5Eu, /* Base address: 0x40342A00 Count: 94 */ + 0x40347005u, /* Base address: 0x40347000 Count: 5 */ + 0x40347102u, /* Base address: 0x40347100 Count: 2 */ + 0x40347202u, /* Base address: 0x40347200 Count: 2 */ + 0x40347804u, /* Base address: 0x40347800 Count: 4 */ +}; + +static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = +{ + {0x18u, 0xFFu}, + {0x1Du, 0x01u}, + {0x00u, 0x10u}, + {0x04u, 0x88u}, + {0x09u, 0x02u}, + {0x10u, 0x10u}, + {0x14u, 0x88u}, + {0x1Du, 0x01u}, + {0x20u, 0x10u}, + {0x24u, 0x88u}, + {0x28u, 0x10u}, + {0x2Cu, 0x88u}, + {0x15u, 0x40u}, + {0x04u, 0x07u}, + {0x14u, 0x47u}, + {0x1Cu, 0x2Fu}, + {0x20u, 0x03u}, + {0x28u, 0x0Fu}, + {0x01u, 0x8Eu}, + {0x03u, 0x70u}, + {0x05u, 0x04u}, + {0x0Au, 0x01u}, + {0x0Du, 0x04u}, + {0x11u, 0x60u}, + {0x13u, 0x80u}, + {0x15u, 0x04u}, + {0x18u, 0x02u}, + {0x19u, 0xD0u}, + {0x1Bu, 0x23u}, + {0x21u, 0x01u}, + {0x23u, 0x20u}, + {0x25u, 0xD0u}, + {0x27u, 0x2Fu}, + {0x2Du, 0x10u}, + {0x2Eu, 0x01u}, + {0x2Fu, 0x48u}, + {0x30u, 0x01u}, + {0x31u, 0xE0u}, + {0x34u, 0x02u}, + {0x35u, 0x1Fu}, + {0x3Bu, 0x02u}, + {0x3Du, 0x22u}, + {0x3Eu, 0x11u}, + {0x40u, 0x52u}, + {0x41u, 0x01u}, + {0x44u, 0x06u}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Cu, 0x12u}, + {0x4Du, 0x5Cu}, + {0x4Eu, 0x78u}, + {0x5Cu, 0x04u}, + {0x5Du, 0x0Cu}, + {0x5Eu, 0x0Cu}, + {0x63u, 0x09u}, + {0x64u, 0x50u}, + {0x65u, 0xA8u}, + {0x69u, 0x1Cu}, + {0x6Au, 0x58u}, + {0x6Bu, 0xA1u}, + {0x6Du, 0x10u}, + {0x70u, 0x10u}, + {0x71u, 0x1Du}, + {0x86u, 0x20u}, + {0x8Au, 0x20u}, + {0x8Bu, 0x02u}, + {0x8Cu, 0x20u}, + {0x90u, 0xBAu}, + {0x92u, 0x04u}, + {0x94u, 0x08u}, + {0x96u, 0x11u}, + {0x98u, 0x78u}, + {0x9Au, 0x02u}, + {0x9Cu, 0x18u}, + {0x9Eu, 0xC4u}, + {0xA3u, 0x01u}, + {0xA4u, 0x08u}, + {0xA6u, 0x10u}, + {0xA8u, 0xFEu}, + {0xABu, 0x01u}, + {0xADu, 0x02u}, + {0xAEu, 0x20u}, + {0xB0u, 0x01u}, + {0xB2u, 0x18u}, + {0xB3u, 0x01u}, + {0xB4u, 0x06u}, + {0xB5u, 0x02u}, + {0xB6u, 0xE0u}, + {0xBAu, 0x08u}, + {0xBFu, 0x14u}, + {0xC0u, 0x52u}, + {0xC1u, 0x01u}, + {0xC4u, 0x06u}, + {0xC5u, 0xB0u}, + {0xC7u, 0x40u}, + {0xC8u, 0x22u}, + {0xC9u, 0xFFu}, + {0xCAu, 0xFFu}, + {0xCBu, 0xFFu}, + {0xCCu, 0x13u}, + {0xCDu, 0x5Cu}, + {0xCEu, 0x77u}, + {0xD4u, 0xDEu}, + {0xD5u, 0x40u}, + {0xD6u, 0x4Bu}, + {0xD7u, 0x04u}, + {0xDCu, 0x0Cu}, + {0xDDu, 0x04u}, + {0xDEu, 0x0Cu}, + {0xDFu, 0x0Cu}, + {0xE3u, 0x09u}, + {0xE4u, 0x50u}, + {0xE5u, 0xA8u}, + {0xE9u, 0x1Cu}, + {0xEAu, 0x58u}, + {0xEBu, 0xA1u}, + {0xEDu, 0x10u}, + {0xF0u, 0x10u}, + {0xF1u, 0x1Du}, + {0x00u, 0x08u}, + {0x04u, 0x01u}, + {0x05u, 0x07u}, + {0x08u, 0x01u}, + {0x0Au, 0x08u}, + {0x0Fu, 0x05u}, + {0x12u, 0x01u}, + {0x14u, 0x10u}, + {0x16u, 0x01u}, + {0x18u, 0x01u}, + {0x1Au, 0x04u}, + {0x1Eu, 0x0Eu}, + {0x1Fu, 0x06u}, + {0x20u, 0x01u}, + {0x22u, 0x02u}, + {0x25u, 0x03u}, + {0x2Au, 0x10u}, + {0x2Bu, 0x01u}, + {0x32u, 0x10u}, + {0x36u, 0x0Fu}, + {0x37u, 0x07u}, + {0x3Cu, 0x80u}, + {0x40u, 0x36u}, + {0x41u, 0x01u}, + {0x42u, 0x20u}, + {0x44u, 0x05u}, + {0x45u, 0xFBu}, + {0x46u, 0xC0u}, + {0x47u, 0xE0u}, + {0x48u, 0x2Bu}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Cu, 0x02u}, + {0x4Fu, 0x0Cu}, + {0x50u, 0x08u}, + {0x51u, 0x10u}, + {0x5Cu, 0x0Cu}, + {0x5Du, 0x0Cu}, + {0x5Eu, 0x0Cu}, + {0x63u, 0x09u}, + {0x65u, 0x08u}, + {0x68u, 0xC0u}, + {0x6Cu, 0x10u}, + {0x6Du, 0x11u}, + {0x6Eu, 0x40u}, + {0x6Fu, 0x01u}, + {0x71u, 0x10u}, + {0x72u, 0x50u}, + {0x73u, 0xA8u}, + {0x82u, 0x08u}, + {0x84u, 0x07u}, + {0x86u, 0xF8u}, + {0x8Cu, 0x0Eu}, + {0x8Eu, 0xD1u}, + {0x92u, 0x21u}, + {0x96u, 0x01u}, + {0x98u, 0x04u}, + {0x9Eu, 0x04u}, + {0xA0u, 0x04u}, + {0xA4u, 0xB9u}, + {0xA6u, 0x06u}, + {0xA8u, 0x89u}, + {0xAAu, 0x72u}, + {0xAEu, 0x60u}, + {0xB0u, 0x80u}, + {0xB2u, 0x7Fu}, + {0xBAu, 0x08u}, + {0xBCu, 0x08u}, + {0xBEu, 0x01u}, + {0xC0u, 0x42u}, + {0xC1u, 0x05u}, + {0xC4u, 0x06u}, + {0xC6u, 0x40u}, + {0xC7u, 0xB0u}, + {0xC8u, 0x28u}, + {0xC9u, 0xFFu}, + {0xCAu, 0xFFu}, + {0xCBu, 0xFFu}, + {0xCCu, 0x13u}, + {0xCDu, 0x5Cu}, + {0xCEu, 0x77u}, + {0xDCu, 0x0Cu}, + {0xDEu, 0x0Cu}, + {0xE3u, 0x09u}, + {0xE4u, 0x50u}, + {0xE5u, 0xA8u}, + {0xE9u, 0x1Cu}, + {0xEAu, 0x58u}, + {0xEBu, 0xA1u}, + {0xEDu, 0x10u}, + {0xF0u, 0x10u}, + {0xF1u, 0x1Du}, + {0x03u, 0x40u}, + {0x09u, 0x10u}, + {0x0Cu, 0x2Au}, + {0x0Du, 0x30u}, + {0x0Eu, 0x01u}, + {0x0Fu, 0x0Au}, + {0x15u, 0x30u}, + {0x17u, 0x0Au}, + {0x1Du, 0x0Cu}, + {0x1Eu, 0x14u}, + {0x20u, 0x02u}, + {0x22u, 0x29u}, + {0x23u, 0x35u}, + {0x24u, 0x30u}, + {0x25u, 0x03u}, + {0x28u, 0x03u}, + {0x29u, 0x20u}, + {0x2Au, 0x28u}, + {0x2Cu, 0x0Cu}, + {0x2Du, 0x0Au}, + {0x2Fu, 0x30u}, + {0x30u, 0x01u}, + {0x31u, 0x70u}, + {0x32u, 0x30u}, + {0x33u, 0x0Cu}, + {0x34u, 0x0Cu}, + {0x35u, 0x03u}, + {0x36u, 0x02u}, + {0x38u, 0x28u}, + {0x39u, 0x28u}, + {0x3Eu, 0x55u}, + {0x3Fu, 0x15u}, + {0x40u, 0x42u}, + {0x41u, 0x05u}, + {0x44u, 0x06u}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Cu, 0x12u}, + {0x4Du, 0x5Cu}, + {0x4Eu, 0x78u}, + {0x57u, 0x02u}, + {0x58u, 0x7Fu}, + {0x5Cu, 0x04u}, + {0x5Du, 0x04u}, + {0x5Eu, 0x0Cu}, + {0x5Fu, 0x0Cu}, + {0x62u, 0x08u}, + {0x63u, 0x09u}, + {0x64u, 0x50u}, + {0x65u, 0xA8u}, + {0x69u, 0x1Cu}, + {0x6Au, 0x58u}, + {0x6Bu, 0xA1u}, + {0x6Du, 0x10u}, + {0x70u, 0x10u}, + {0x71u, 0x1Du}, + {0x82u, 0x01u}, + {0x86u, 0x01u}, + {0x8Au, 0x02u}, + {0x8Cu, 0x01u}, + {0x98u, 0x01u}, + {0x9Cu, 0x03u}, + {0x9Eu, 0x04u}, + {0xA0u, 0x01u}, + {0xA8u, 0x01u}, + {0xACu, 0x03u}, + {0xAEu, 0x04u}, + {0xB4u, 0x07u}, + {0xB6u, 0x07u}, + {0xBCu, 0xA0u}, + {0xC0u, 0x42u}, + {0xC1u, 0x05u}, + {0xC4u, 0x06u}, + {0xC7u, 0xB4u}, + {0xC8u, 0x30u}, + {0xC9u, 0xFFu}, + {0xCAu, 0xFFu}, + {0xCBu, 0xFFu}, + {0xCCu, 0x13u}, + {0xCDu, 0x5Cu}, + {0xCEu, 0x77u}, + {0xDCu, 0x0Fu}, + {0xDEu, 0x0Fu}, + {0xDFu, 0x04u}, + {0xE3u, 0x09u}, + {0xE4u, 0x50u}, + {0xE5u, 0xA8u}, + {0xE9u, 0x1Cu}, + {0xEAu, 0x58u}, + {0xEBu, 0xA1u}, + {0xEDu, 0x10u}, + {0xF0u, 0x10u}, + {0xF1u, 0x1Du}, + {0x28u, 0x10u}, + {0xA8u, 0xE1u}, + {0xACu, 0x52u}, + {0xB0u, 0xAAu}, + {0xB4u, 0x01u}, + {0xA8u, 0xA1u}, + {0xE8u, 0x02u}, + {0xA8u, 0x87u}, + {0xACu, 0x53u}, + {0x00u, 0x01u}, + {0x10u, 0x01u}, + {0x14u, 0x01u}, + {0x18u, 0x01u}, +}; + + + +CYPACKED typedef struct +{ +void *address; +uint16 size; +} CYPACKED_ATTR cfg_memset_t; + + +CYPACKED typedef struct +{ + void *dest; + const void *src; + size_t size; +} CYPACKED_ATTR cfg_memcpy_t; + +static const cfg_memset_t CYCODE cfg_memset_list[] = +{ + /* address, size */ + {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_UDBSNG0_BASE), 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE), 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE), 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE), 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_UDBSNG0_BASE), 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE), 116u}, +}; + +/* UDB_UDBPAIR4_UDBSNG0 Address: CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE Size (bytes): 116 */ +static const uint8 CYCODE BS_UDB_UDBPAIR4_UDBSNG0_VAL[] = +{ + 0x42u, 0x00u, 0x25u, 0x0Au, 0x50u, 0x00u, 0x08u, 0x00u, 0x48u, 0x00u, 0x10u, 0x05u, 0x04u, 0x00u, 0x00u, 0x00u, + 0x61u, 0x00u, 0x06u, 0x00u, 0x00u, 0x0Au, 0x00u, 0x00u, 0x41u, 0x0Cu, 0x26u, 0x03u, 0x00u, 0x00u, 0x04u, 0x0Au, + 0x48u, 0x05u, 0x10u, 0x00u, 0x40u, 0x00u, 0x18u, 0x05u, 0x04u, 0x00u, 0x00u, 0x05u, 0x02u, 0x00u, 0x00u, 0x00u, + 0x07u, 0x0Cu, 0x40u, 0x03u, 0x07u, 0x00u, 0x38u, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x22u, 0x00u, 0x44u, 0x05u, + 0x42u, 0x05u, 0x00u, 0x00u, 0x06u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0x5Cu, 0x78u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x71u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x04u, 0x0Cu, 0x0Cu, + 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, + 0x10u, 0x1Du, 0x00u, 0x00u +}; + +/* UDB_UDBPAIR3_UDBSNG1 Address: CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE Size (bytes): 116 */ +static const uint8 CYCODE BS_UDB_UDBPAIR3_UDBSNG1_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x88u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x02u, 0x88u, 0x01u, 0x00u, + 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x88u, 0x03u, 0x00u, 0x01u, 0xBCu, 0x00u, 0x40u, 0x39u, 0x22u, 0x46u, 0xC5u, + 0x00u, 0x00u, 0x04u, 0x01u, 0x28u, 0xA2u, 0x56u, 0x4Du, 0x51u, 0x00u, 0x2Eu, 0x00u, 0x08u, 0x00u, 0x00u, 0x10u, + 0x00u, 0x60u, 0x00u, 0x80u, 0x1Fu, 0x00u, 0x60u, 0x1Fu, 0x00u, 0x80u, 0x20u, 0x00u, 0x20u, 0x80u, 0x40u, 0x05u, + 0x64u, 0x03u, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x06u, 0x11u, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0xA0u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x73u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, + 0x00u, 0x00u, 0x08u, 0x09u, 0x00u, 0x00u, 0x40u, 0x40u, 0x10u, 0x50u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u +}; + +/* UDB_UDBPAIR1_UDBSNG1 Address: CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE Size (bytes): 116 */ +static const uint8 CYCODE BS_UDB_UDBPAIR1_UDBSNG1_VAL[] = +{ + 0x04u, 0x20u, 0x02u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x79u, 0x00u, 0x82u, 0x11u, 0x48u, 0x2Eu, 0x95u, + 0x09u, 0x08u, 0x16u, 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x8Du, 0x00u, 0x72u, 0x20u, 0x08u, 0x00u, 0x00u, + 0x2Eu, 0x00u, 0x11u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x84u, + 0x38u, 0xE0u, 0x02u, 0x07u, 0x04u, 0x18u, 0x01u, 0x07u, 0x00u, 0x00u, 0x82u, 0x22u, 0x82u, 0xAAu, 0x14u, 0x00u, + 0x41u, 0x05u, 0x63u, 0x00u, 0x00u, 0x0Eu, 0x00u, 0xF0u, 0x21u, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x2Fu, + 0x08u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x04u, + 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x08u, 0x03u, 0x08u, 0x00u, 0x18u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x58u, 0xECu, 0x00u, 0x00u +}; + +/* UDB_UDBPAIR0_UDBSNG0 Address: CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE Size (bytes): 116 */ +static const uint8 CYCODE BS_UDB_UDBPAIR0_UDBSNG0_VAL[] = +{ + 0x95u, 0x08u, 0x6Au, 0x00u, 0x26u, 0x62u, 0xD9u, 0x9Du, 0x82u, 0x00u, 0x40u, 0x42u, 0x00u, 0x00u, 0x80u, 0x00u, + 0x00u, 0x00u, 0x90u, 0x32u, 0x4Eu, 0x00u, 0xB1u, 0x01u, 0x92u, 0x00u, 0x6Du, 0x00u, 0x00u, 0xB5u, 0x04u, 0x4Au, + 0x04u, 0x00u, 0x00u, 0x00u, 0x04u, 0xF2u, 0x00u, 0x09u, 0x00u, 0x66u, 0x01u, 0x88u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x3Fu, 0xE0u, 0xC0u, 0x1Fu, 0x3Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x2Au, 0x0Au, 0x2Au, 0x0Au, 0x00u, 0x00u, + 0x43u, 0x01u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0x5Cu, 0x78u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x00u, + 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, + 0x10u, 0x1Du, 0x00u, 0x00u +}; + +/* UDB_UDBPAIR1_UDBSNG0 Address: CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE Size (bytes): 116 */ +static const uint8 CYCODE BS_UDB_UDBPAIR1_UDBSNG0_VAL[] = +{ + 0x00u, 0x01u, 0x00u, 0x00u, 0xABu, 0x00u, 0x00u, 0x03u, 0x2Bu, 0xC9u, 0x54u, 0x12u, 0x02u, 0x00u, 0x00u, 0x40u, + 0xAAu, 0x00u, 0x01u, 0x01u, 0x81u, 0x05u, 0x2Au, 0xBAu, 0xAAu, 0x00u, 0x00u, 0x40u, 0x08u, 0xB3u, 0x00u, 0x4Cu, + 0x04u, 0x20u, 0x00u, 0x80u, 0x40u, 0x00u, 0x00u, 0x01u, 0x10u, 0x01u, 0x00u, 0x80u, 0x20u, 0xB1u, 0x00u, 0x04u, + 0x19u, 0x00u, 0x07u, 0x80u, 0x61u, 0x00u, 0x80u, 0x7Fu, 0x2Au, 0x00u, 0x00u, 0x80u, 0x00u, 0x80u, 0x55u, 0x04u, + 0x24u, 0x06u, 0x00u, 0x00u, 0x01u, 0x0Eu, 0x00u, 0xC4u, 0x31u, 0xFFu, 0xFFu, 0x0Eu, 0x82u, 0x20u, 0x00u, 0x00u, + 0x08u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x0Cu, 0x0Cu, 0x04u, + 0x00u, 0x00u, 0x00u, 0x09u, 0x40u, 0x09u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x10u, 0x00u, 0x13u, 0x10u, 0x13u, + 0x40u, 0x03u, 0x00u, 0x10u +}; + +/* UDB_UDBPAIR0_UDBSNG1 Address: CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE Size (bytes): 116 */ +static const uint8 CYCODE BS_UDB_UDBPAIR0_UDBSNG1_VAL[] = +{ + 0x00u, 0x00u, 0x80u, 0x03u, 0x7Bu, 0x04u, 0x80u, 0x00u, 0x33u, 0x1Cu, 0xCCu, 0x00u, 0x04u, 0x03u, 0x00u, 0x00u, + 0x8Au, 0x00u, 0x71u, 0x04u, 0xB9u, 0x00u, 0x42u, 0x0Cu, 0x00u, 0x03u, 0x20u, 0x00u, 0x00u, 0x14u, 0x00u, 0x00u, + 0x00u, 0x00u, 0xA0u, 0x03u, 0x0Au, 0x1Cu, 0xD0u, 0x00u, 0x02u, 0x02u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, + 0x00u, 0x07u, 0x00u, 0x18u, 0xF8u, 0x00u, 0x07u, 0x00u, 0x80u, 0x08u, 0x20u, 0x00u, 0x20u, 0x00u, 0x40u, 0x05u, + 0x43u, 0x01u, 0x00u, 0x00u, 0x02u, 0x00u, 0x40u, 0x0Bu, 0x18u, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, 0x77u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x7Fu, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x04u, 0x0Cu, 0x0Cu, + 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, + 0x10u, 0x1Du, 0x00u, 0x00u +}; + +/* UDB_UDBPAIR0_ROUTE Address: CYDEV_UDB_UDBPAIR0_ROUTE_BASE Size (bytes): 144 */ +static const uint8 CYCODE BS_UDB_UDBPAIR0_ROUTE_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x25u, 0x40u, 0x13u, 0x30u, + 0x54u, 0xF1u, 0x1Fu, 0xF6u, 0xF5u, 0x33u, 0x05u, 0x12u, 0x33u, 0x51u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x32u, + 0xFFu, 0x00u, 0x00u, 0x00u, 0x21u, 0x32u, 0x75u, 0x37u, 0x23u, 0xF5u, 0x51u, 0x14u, 0x54u, 0x32u, 0x11u, 0x41u, + 0x33u, 0x51u, 0xFFu, 0x0Fu, 0x5Fu, 0xFFu, 0x2Fu, 0x22u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x14u, 0x01u, 0x01u, 0x11u, 0x10u, 0x44u, 0x53u, 0x33u, 0x14u, 0x11u, 0x40u, 0x01u, 0x01u, 0x33u, 0x4Cu, 0x04u, + 0x11u, 0x01u, 0x3Bu, 0x01u, 0x01u, 0x10u, 0x11u, 0x00u, 0x62u, 0x10u, 0x11u, 0x13u, 0x11u, 0x19u, 0x11u, 0x16u, + 0x09u, 0x73u, 0x10u, 0x66u, 0x11u, 0x11u, 0x11u, 0x11u, 0x12u, 0x11u, 0x11u, 0x14u, 0x11u, 0x14u, 0x11u, 0x11u +}; + +/* UDB_UDBPAIR1_ROUTE Address: CYDEV_UDB_UDBPAIR1_ROUTE_BASE Size (bytes): 144 */ +static const uint8 CYCODE BS_UDB_UDBPAIR1_ROUTE_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x0Fu, 0xF5u, 0x5Fu, + 0x22u, 0xFFu, 0x04u, 0xF1u, 0x56u, 0x63u, 0x61u, 0x12u, 0xF7u, 0x04u, 0x37u, 0x16u, 0x63u, 0xFFu, 0xFFu, 0x32u, + 0xFFu, 0x00u, 0x00u, 0x00u, 0x2Fu, 0x52u, 0x75u, 0x60u, 0x45u, 0x04u, 0x14u, 0x31u, 0x44u, 0x12u, 0x76u, 0x13u, + 0x51u, 0x73u, 0x70u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x25u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x00u, 0xF5u, + 0x4Fu, 0x06u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x03u, 0x06u, 0x00u, 0xA1u, 0x06u, 0x0Cu, 0x36u, 0xF5u, 0x0Du, 0x10u, 0xF3u, 0x01u, 0x00u, 0xFFu, 0x3Fu, 0x0Fu, + 0x15u, 0x00u, 0xFBu, 0x01u, 0x03u, 0x10u, 0x11u, 0x4Cu, 0x11u, 0x52u, 0x90u, 0xC1u, 0xD2u, 0x15u, 0xC3u, 0x5Fu, + 0x36u, 0x0Fu, 0x23u, 0x3Cu, 0x00u, 0x11u, 0x15u, 0x11u, 0x11u, 0x31u, 0x14u, 0x1Fu, 0x11u, 0x8Fu, 0x11u, 0xC1u +}; + +/* UDB_UDBPAIR2_ROUTE Address: CYDEV_UDB_UDBPAIR2_ROUTE_BASE Size (bytes): 144 */ +static const uint8 CYCODE BS_UDB_UDBPAIR2_ROUTE_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x11u, 0xFFu, 0x45u, + 0xFFu, 0x5Fu, 0xF5u, 0x44u, 0x4Fu, 0x36u, 0x43u, 0x73u, 0x13u, 0xFFu, 0x23u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x32u, + 0xFFu, 0x00u, 0x00u, 0x00u, 0x6Fu, 0x24u, 0x45u, 0x44u, 0x1Fu, 0x63u, 0x17u, 0x1Fu, 0xFFu, 0xFFu, 0x4Fu, 0xFFu, + 0x13u, 0x14u, 0x63u, 0x07u, 0x55u, 0xF7u, 0xF7u, 0x72u, 0xF0u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x05u, 0x2Fu, 0x10u, + 0xF0u, 0xF3u, 0xF0u, 0x10u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x01u, 0x00u, 0x8Du, 0x16u, 0x21u, 0x0Fu, 0x1Fu, 0x1Fu, 0xAFu, 0xB0u, 0x0Fu, 0xADu, 0x00u, 0xFFu, 0x4Fu, 0x00u, + 0x05u, 0x0Du, 0x0Au, 0x41u, 0x00u, 0xAAu, 0x01u, 0xF1u, 0xC4u, 0x10u, 0xF0u, 0x04u, 0xF3u, 0x1Fu, 0xC4u, 0x3Fu, + 0x1Fu, 0x03u, 0xF0u, 0xF0u, 0x88u, 0x01u, 0x3Fu, 0x01u, 0x11u, 0xB1u, 0x57u, 0x81u, 0x11u, 0xC1u, 0x1Du, 0x14u +}; + +/* UDB_UDBPAIR3_ROUTE Address: CYDEV_UDB_UDBPAIR3_ROUTE_BASE Size (bytes): 144 */ +static const uint8 CYCODE BS_UDB_UDBPAIR3_ROUTE_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x36u, 0x34u, 0x32u, + 0x06u, 0x14u, 0xF5u, 0x46u, 0x43u, 0xF6u, 0xF3u, 0x43u, 0xFFu, 0x37u, 0x5Fu, 0xFFu, 0x5Fu, 0xF2u, 0xFFu, 0x32u, + 0xFFu, 0x00u, 0x00u, 0x00u, 0x45u, 0xF4u, 0x37u, 0x40u, 0xF0u, 0xF2u, 0x7Fu, 0xF4u, 0xF4u, 0xFFu, 0xF3u, 0x03u, + 0x73u, 0xF0u, 0x77u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xF2u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x07u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x00u, 0x06u, 0xBFu, 0x17u, 0x11u, 0x7Fu, 0x71u, 0x11u, 0x5Fu, 0x70u, 0x5Fu, 0xFFu, 0x06u, 0xFFu, 0x0Fu, 0x07u, + 0x7Fu, 0x3Fu, 0x0Fu, 0xF6u, 0x00u, 0x2Fu, 0x7Fu, 0x48u, 0xF4u, 0x30u, 0xB0u, 0x5Fu, 0x11u, 0x0Fu, 0x91u, 0xFFu, + 0x1Fu, 0x0Au, 0xF3u, 0xFBu, 0x15u, 0x11u, 0x1Fu, 0xA1u, 0x11u, 0x81u, 0x11u, 0x12u, 0x14u, 0x11u, 0x1Fu, 0x31u +}; + +/* UDB_UDBPAIR4_ROUTE Address: CYDEV_UDB_UDBPAIR4_ROUTE_BASE Size (bytes): 144 */ +static const uint8 CYCODE BS_UDB_UDBPAIR4_ROUTE_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x60u, 0x17u, 0xF5u, 0x65u, + 0x77u, 0x77u, 0x7Fu, 0x05u, 0x14u, 0xF4u, 0x5Fu, 0x0Fu, 0x1Fu, 0x5Fu, 0x43u, 0x5Fu, 0xFFu, 0xF2u, 0xFFu, 0x05u, + 0xFFu, 0x00u, 0x00u, 0x00u, 0x23u, 0x7Fu, 0x52u, 0x64u, 0x55u, 0x75u, 0xFFu, 0xFFu, 0xF5u, 0xFFu, 0x11u, 0xFFu, + 0x1Fu, 0x52u, 0x13u, 0x40u, 0xFFu, 0xF3u, 0xFFu, 0xF5u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x25u, 0x00u, 0x30u, + 0x00u, 0x00u, 0x00u, 0x13u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x00u, 0x81u, 0x1Fu, 0x11u, 0x11u, 0x5Fu, 0x91u, 0x10u, 0xFFu, 0x33u, 0x0Fu, 0xFFu, 0x30u, 0xFFu, 0x4Fu, 0x31u, + 0x1Fu, 0xFFu, 0x06u, 0x06u, 0x0Au, 0x28u, 0x08u, 0x66u, 0x11u, 0x10u, 0xF9u, 0x17u, 0x20u, 0x3Fu, 0x10u, 0x2Fu, + 0x1Fu, 0x00u, 0xF1u, 0xF6u, 0x1Bu, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x33u, 0x31u, 0x11u, 0x17u, 0x11u, 0x11u, 0x1Bu +}; + +/* UDB_UDBPAIR5_ROUTE Address: CYDEV_UDB_UDBPAIR5_ROUTE_BASE Size (bytes): 144 */ +static const uint8 CYCODE BS_UDB_UDBPAIR5_ROUTE_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x43u, 0x43u, 0xFFu, 0x30u, + 0xF0u, 0x22u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x1Fu, 0x5Fu, 0x53u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x42u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x3Fu, 0xF3u, 0x1Fu, 0x15u, 0x11u, 0x13u, 0x13u, 0x41u, 0xF1u, 0x31u, 0x3Fu, + 0x1Fu, 0x53u, 0x03u, 0xF0u, 0x4Fu, 0xFFu, 0x2Fu, 0x13u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x01u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x23u, 0x11u, 0x1Fu, 0x11u, 0x31u, 0x7Fu, 0x61u, 0x17u, 0xBFu, 0x8Cu, 0x8Fu, 0xFFu, 0x39u, 0x1Fu, 0x95u, 0x1Cu, + 0x1Fu, 0xFFu, 0x6Cu, 0x7Fu, 0x33u, 0x1Fu, 0x7Fu, 0xFFu, 0x44u, 0x13u, 0x11u, 0x11u, 0x13u, 0x81u, 0x7Cu, 0x12u, + 0x11u, 0xCCu, 0x16u, 0x16u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI0 Address: CYDEV_UDB_DSI0_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI0_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x11u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Du, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI1 Address: CYDEV_UDB_DSI1_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI1_VAL[] = +{ + 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x20u, 0xF1u, 0x0Fu, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0xD1u, 0x11u, 0x11u, + 0x11u, 0xF1u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0xD1u, 0x11u, 0x10u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Du, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI2 Address: CYDEV_UDB_DSI2_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI2_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x0Au, 0x0Au, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x0Au, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x13u, 0x0Au, 0x00u, 0x0Du, 0x16u, 0x1Fu, 0x11u, 0x1Fu, + 0x1Fu, 0x1Fu, 0x0Au, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0xF4u, 0xF0u, 0x10u, 0x10u, 0x50u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x01u, 0x11u, 0x11u, + 0x11u, 0xF1u, 0x12u, 0x11u, 0xBFu, 0x11u, 0x11u, 0x1Du, 0x01u, 0x11u, 0x12u, 0x11u, 0x11u, 0x01u, 0xF1u, 0x10u, + 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x16u, 0x11u, 0x11u, 0x11u, 0x11u, 0x10u, 0x11u, + 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI3 Address: CYDEV_UDB_DSI3_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI3_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x11u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0xF1u, 0x11u, 0x11u, 0x03u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI4 Address: CYDEV_UDB_DSI4_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI4_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI5 Address: CYDEV_UDB_DSI5_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI5_VAL[] = +{ + 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI6 Address: CYDEV_UDB_DSI6_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI6_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x08u, 0x03u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI7 Address: CYDEV_UDB_DSI7_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI7_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x0Au, 0x1Fu, 0x08u, + 0x1Fu, 0x1Fu, 0x1Fu, 0x02u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x0Eu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x10u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x10u, 0x11u, 0x10u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u +}; + +/* UDB_DSI8 Address: CYDEV_UDB_DSI8_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI8_VAL[] = +{ + 0x00u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0xF0u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x1Du, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Du, 0x11u, 0x1Du, 0x11u, + 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI9 Address: CYDEV_UDB_DSI9_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI9_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x01u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI10 Address: CYDEV_UDB_DSI10_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI10_VAL[] = +{ + 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x16u, 0x0Cu, 0x1Fu, 0x03u, 0x06u, 0x1Fu, 0x1Fu, 0x05u, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0xFFu, 0x00u, 0xF0u, 0x00u, 0x00u, 0x00u, 0xFFu, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0xD1u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +/* UDB_DSI11 Address: CYDEV_UDB_DSI11_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI11_VAL[] = +{ + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u +}; + +static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { + /* dest, src, size */ + {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE), BS_UDB_UDBPAIR4_UDBSNG0_VAL, 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE), BS_UDB_UDBPAIR3_UDBSNG1_VAL, 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE), BS_UDB_UDBPAIR1_UDBSNG1_VAL, 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE), BS_UDB_UDBPAIR0_UDBSNG0_VAL, 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE), BS_UDB_UDBPAIR1_UDBSNG0_VAL, 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE), BS_UDB_UDBPAIR0_UDBSNG1_VAL, 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_ROUTE_BASE), BS_UDB_UDBPAIR0_ROUTE_VAL, 144u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_ROUTE_BASE), BS_UDB_UDBPAIR1_ROUTE_VAL, 144u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_ROUTE_BASE), BS_UDB_UDBPAIR2_ROUTE_VAL, 144u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_ROUTE_BASE), BS_UDB_UDBPAIR3_ROUTE_VAL, 144u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_ROUTE_BASE), BS_UDB_UDBPAIR4_ROUTE_VAL, 144u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_ROUTE_BASE), BS_UDB_UDBPAIR5_ROUTE_VAL, 144u}, + {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), BS_UDB_DSI0_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI1_BASE), BS_UDB_DSI1_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI2_BASE), BS_UDB_DSI2_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI3_BASE), BS_UDB_DSI3_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI4_BASE), BS_UDB_DSI4_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI5_BASE), BS_UDB_DSI5_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI6_BASE), BS_UDB_DSI6_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI7_BASE), BS_UDB_DSI7_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI8_BASE), BS_UDB_DSI8_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI9_BASE), BS_UDB_DSI9_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI10_BASE), BS_UDB_DSI10_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI11_BASE), BS_UDB_DSI11_VAL, 124u}, +}; + +void SDIO_Host_Config_UDBs(void) +{ + size_t i; + + /* Power on the UDB array */ + CY_SET_REG32(0x402101F0u, 0x05FA0003u); + + /* Zero out critical memory blocks before beginning configuration */ + for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) + { + const cfg_memset_t *ms = &cfg_memset_list[i]; + CYMEMZERO(ms->address, ms->size); + } + + /* Copy device configuration data into registers */ + for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) + { + const cfg_memcpy_t *mc = &cfg_memcpy_list[i]; + CYCONFIGCPYCODE(mc->dest, mc->src, mc->size); + } + + cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); + + /* UDB_INT_CFG Starting address: CYDEV_UDB_UDBIF_INT_CLK_CTL */ + CY_SET_REG32((void *)(CYREG_UDB_UDBIF_INT_CLK_CTL), 0x00000001u); + + /* UDB_UDBPAIR0_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG0_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR0_UDBSNG0_RC_CFG0), 0x004C4C4Cu); + + /* UDB_UDBPAIR0_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG1_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR0_UDBSNG1_RC_CFG0), 0x4C4C444Cu); + + /* UDB_UDBPAIR1_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG0_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR1_UDBSNG0_RC_CFG0), 0x044C4C44u); + + /* UDB_UDBPAIR1_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG1_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR1_UDBSNG1_RC_CFG0), 0x044C4C4Cu); + + /* UDB_UDBPAIR2_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG0_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR2_UDBSNG0_RC_CFG0), 0x004C4C44u); + + /* UDB_UDBPAIR2_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG1_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR2_UDBSNG1_RC_CFG0), 0x0C4C040Cu); + + /* UDB_UDBPAIR3_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG0_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR3_UDBSNG0_RC_CFG0), 0x008C8C8Cu); + + /* UDB_UDBPAIR3_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG1_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR3_UDBSNG1_RC_CFG0), 0x4C4C4C4Cu); + + /* UDB_UDBPAIR4_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG0_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR4_UDBSNG0_RC_CFG0), 0x4C4C444Cu); + + /* UDB_UDBPAIR4_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG1_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR4_UDBSNG1_RC_CFG0), 0x008C808Cu); + + /* UDB_UDBPAIR5_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG0_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR5_UDBSNG0_RC_CFG0), 0x8C8C0404u); + + /* UDB_UDBPAIR5_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG1_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR5_UDBSNG1_RC_CFG0), 0x048F808Fu); + + /* Enable UDB array and digital routing */ + CY_SET_REG32((void *)0x40347900u, CY_GET_REG32((void *)0x40347900u) | 0x106u); +} + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.h new file mode 100644 index 0000000000..22914b0ae2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.h @@ -0,0 +1,905 @@ +#if !defined(CY_SDIO_CFG_H) +#define CY_SDIO_CFG_H + +#include + +#include "cy_dma.h" +#include "cy_sysclk.h" +#include "cy_trigmux.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CYREG_PROT_SMPU_MS0_CTL 0x40240000u +#define CYREG_PROT_SMPU_MS1_CTL 0x40240004u +#define CYREG_PROT_SMPU_MS2_CTL 0x40240008u +#define CYREG_PROT_SMPU_MS3_CTL 0x4024000cu +#define CYREG_PROT_SMPU_MS14_CTL 0x40240038u + +#define CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE 0x40342200u +#define CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE 0x40342080u + +#define CYREG_UDB_UDBPAIR0_UDBSNG0_RC_CFG0 0x4034205cu +#define CYREG_UDB_UDBPAIR0_UDBSNG1_RC_CFG0 0x403420dcu + +#define CYREG_UDB_UDBPAIR1_UDBSNG0_RC_CFG0 0x4034225cu +#define CYREG_UDB_UDBPAIR1_UDBSNG1_RC_CFG0 0x403422dcu + +#define CYREG_UDB_UDBPAIR2_UDBSNG0_RC_CFG0 0x4034245cu +#define CYREG_UDB_UDBPAIR2_UDBSNG1_RC_CFG0 0x403424dcu +#define CYREG_UDB_UDBPAIR3_UDBSNG0_RC_CFG0 0x4034265cu +#define CYREG_UDB_UDBPAIR3_UDBSNG1_RC_CFG0 0x403426dcu +#define CYREG_UDB_UDBPAIR4_UDBSNG0_RC_CFG0 0x4034285cu +#define CYREG_UDB_UDBPAIR4_UDBSNG1_RC_CFG0 0x403428dcu +#define CYREG_UDB_UDBPAIR5_UDBSNG0_RC_CFG0 0x40342a5cu +#define CYREG_UDB_UDBPAIR5_UDBSNG1_RC_CFG0 0x40342adcu + +#define CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE 0x40342800u +#define CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE 0x40342680u +#define CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE 0x40342280u +#define CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE 0x40342000u + +#define CYDEV_UDB_UDBPAIR0_ROUTE_BASE 0x40342100u +#define CYDEV_UDB_UDBPAIR1_ROUTE_BASE 0x40342300u +#define CYDEV_UDB_UDBPAIR2_ROUTE_BASE 0x40342500u +#define CYDEV_UDB_UDBPAIR3_ROUTE_BASE 0x40342700u +#define CYDEV_UDB_UDBPAIR4_ROUTE_BASE 0x40342900u +#define CYDEV_UDB_UDBPAIR5_ROUTE_BASE 0x40342b00u + + +#define CYDEV_UDB_UDBPAIR2_UDBSNG0_BASE 0x40342400u +#define CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE 0x40342480u +#define CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE 0x40342600u +#define CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE 0x40342880u +#define CYDEV_UDB_UDBPAIR5_UDBSNG0_BASE 0x40342a00u +#define CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE 0x40342a80u + + +#define CYDEV_UDB_DSI0_BASE 0x40346000u +#define CYDEV_UDB_DSI1_BASE 0x40346080u +#define CYDEV_UDB_DSI2_BASE 0x40346100u +#define CYDEV_UDB_DSI3_BASE 0x40346180u +#define CYDEV_UDB_DSI4_BASE 0x40346200u +#define CYDEV_UDB_DSI5_BASE 0x40346280u +#define CYDEV_UDB_DSI6_BASE 0x40346300u +#define CYDEV_UDB_DSI7_BASE 0x40346380u +#define CYDEV_UDB_DSI8_BASE 0x40346400u +#define CYDEV_UDB_DSI9_BASE 0x40346480u +#define CYDEV_UDB_DSI10_BASE 0x40346500u +#define CYDEV_UDB_DSI11_BASE 0x40346580u + +#define CYREG_UDB_UDBIF_INT_CLK_CTL 0x40347904u + +/*************Defines for UDBs from Creator*****************************/ +/***********These come for cyfitter.h**********************************/ + +/* TFT_DMA */ +#define TFT_DMA_DW__BLOCK_HW DW0 +#define TFT_DMA_DW__BLOCK_NUMBER 0u +#define TFT_DMA_DW__CHANNEL_HW DW0_CH_STRUCT2 +#define TFT_DMA_DW__CHANNEL_NUMBER 2u +#define TFT_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN2 +#define TFT_DMA_DW__TR_OUT TRIG10_IN_CPUSS_DW0_TR_OUT2 + +/* TFT_CTRL */ +#define TFT_CTRL_Sync_ctrl_reg__0__MASK 0x01u +#define TFT_CTRL_Sync_ctrl_reg__0__POS 0 +#define TFT_CTRL_Sync_ctrl_reg__1__MASK 0x02u +#define TFT_CTRL_Sync_ctrl_reg__1__POS 1 +#define TFT_CTRL_Sync_ctrl_reg__2__MASK 0x04u +#define TFT_CTRL_Sync_ctrl_reg__2__POS 2 +#define TFT_CTRL_Sync_ctrl_reg__3__MASK 0x08u +#define TFT_CTRL_Sync_ctrl_reg__3__POS 3 +#define TFT_CTRL_Sync_ctrl_reg__4__MASK 0x10u +#define TFT_CTRL_Sync_ctrl_reg__4__POS 4 +#define TFT_CTRL_Sync_ctrl_reg__5__MASK 0x20u +#define TFT_CTRL_Sync_ctrl_reg__5__POS 5 +#define TFT_CTRL_Sync_ctrl_reg__6__MASK 0x40u +#define TFT_CTRL_Sync_ctrl_reg__6__POS 6 +#define TFT_CTRL_Sync_ctrl_reg__7__MASK 0x80u +#define TFT_CTRL_Sync_ctrl_reg__7__POS 7 +#define TFT_CTRL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG 0x4034192Cu +#define TFT_CTRL_Sync_ctrl_reg__CONTROL_REG 0x4034172Cu +#define TFT_CTRL_Sync_ctrl_reg__CONTROL_ST_REG 0x4034032Cu +#define TFT_CTRL_Sync_ctrl_reg__COUNT_REG 0x4034172Cu +#define TFT_CTRL_Sync_ctrl_reg__COUNT_ST_REG 0x4034032Cu +#define TFT_CTRL_Sync_ctrl_reg__MASK 0xFFu +#define TFT_CTRL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG 0x4034042Cu +#define TFT_CTRL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG 0x4034042Cu +#define TFT_CTRL_Sync_ctrl_reg__PERIOD_REG 0x4034182Cu +#define TFT_CTRL_Sync_ctrl_reg__RC_CFG0 0x40342ADCu +#define TFT_CTRL_Sync_ctrl_reg__RC_CFG1 0x40342AE0u +#define TFT_CTRL_Sync_ctrl_reg__SC_CFG0 0x40342AD4u +#define TFT_CTRL_Sync_ctrl_reg__SC_CFG1 0x40342AD8u + +/* SDIO_HOST */ +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A0_REG 0x4034101Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A1_REG 0x4034111Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D0_REG 0x4034121Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D1_REG 0x4034131Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_DP_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_F0_REG 0x4034141Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_F1_REG 0x4034151Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_A0_REG 0x4034101Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_A1_REG 0x4034111Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_D0_REG 0x4034121Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_D1_REG 0x4034131Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_DP_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_F0_REG 0x4034141Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_F1_REG 0x4034151Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__A0_A1_REG 0x4034001Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__A0_REG 0x4034101Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__A1_REG 0x4034111Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__D0_D1_REG 0x4034011Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__D0_REG 0x4034121Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__D1_REG 0x4034131Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__DP_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG0 0x403426C0u +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG1 0x403426C4u +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG2 0x403426C8u +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG3 0x403426CCu +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG4 0x403426D0u +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC0 0x403426E4u +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC1 0x403426E8u +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC2 0x403426ECu +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC3 0x403426F0u +#define SDIO_HOST_bSDIO_blockCounter_u0__F0_F1_REG 0x4034021Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__F0_REG 0x4034141Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__F1_REG 0x4034151Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__MSK_DP_AUX_CTL_REG 0x4034041Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__PER_DP_AUX_CTL_REG 0x4034041Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__RC_CFG0 0x403426DCu +#define SDIO_HOST_bSDIO_blockCounter_u0__RC_CFG1 0x403426E0u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_CONTROL_REG 0x40341720u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_COUNT_REG 0x40341720u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_COUNT_CONTROL_REG 0x40341720u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_COUNT_COUNT_REG 0x40341720u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_MASK_MASK_REG 0x40341820u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_MASK_PERIOD_REG 0x40341820u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_PERIOD_MASK_REG 0x40341820u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_PERIOD_PERIOD_REG 0x40341820u +#define SDIO_HOST_bSDIO_byteCounter__32BIT_CONTROL_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_byteCounter__32BIT_CONTROL_REG 0x40341720u +#define SDIO_HOST_bSDIO_byteCounter__32BIT_COUNT_REG 0x40341720u +#define SDIO_HOST_bSDIO_byteCounter__32BIT_PERIOD_REG 0x40341820u +#define SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_byteCounter__CONTROL_REG 0x40341720u +#define SDIO_HOST_bSDIO_byteCounter__CONTROL_ST_REG 0x40340320u +#define SDIO_HOST_bSDIO_byteCounter__COUNT_REG 0x40341720u +#define SDIO_HOST_bSDIO_byteCounter__COUNT_ST_REG 0x40340320u +#define SDIO_HOST_bSDIO_byteCounter__MASK_CTL_AUX_CTL_REG 0x40340420u +#define SDIO_HOST_bSDIO_byteCounter__PER_CTL_AUX_CTL_REG 0x40340420u +#define SDIO_HOST_bSDIO_byteCounter__PERIOD_REG 0x40341820u +#define SDIO_HOST_bSDIO_byteCounter__RC_CFG0 0x4034285Cu +#define SDIO_HOST_bSDIO_byteCounter__RC_CFG1 0x40342860u +#define SDIO_HOST_bSDIO_byteCounter__SC_CFG0 0x40342854u +#define SDIO_HOST_bSDIO_byteCounter__SC_CFG1 0x40342858u +#define SDIO_HOST_bSDIO_byteCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_byteCounter_ST__16BIT_STATUS_REG 0x40341620u +#define SDIO_HOST_bSDIO_byteCounter_ST__32BIT_MASK_REG 0x40341820u +#define SDIO_HOST_bSDIO_byteCounter_ST__32BIT_STATUS_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_byteCounter_ST__32BIT_STATUS_REG 0x40341620u +#define SDIO_HOST_bSDIO_byteCounter_ST__MASK_REG 0x40341820u +#define SDIO_HOST_bSDIO_byteCounter_ST__MASK_ST_AUX_CTL_REG 0x40340420u +#define SDIO_HOST_bSDIO_byteCounter_ST__PER_ST_AUX_CTL_REG 0x40340420u +#define SDIO_HOST_bSDIO_byteCounter_ST__RC_CFG0 0x4034285Cu +#define SDIO_HOST_bSDIO_byteCounter_ST__RC_CFG1 0x40342860u +#define SDIO_HOST_bSDIO_byteCounter_ST__SC_CFG0 0x40342854u +#define SDIO_HOST_bSDIO_byteCounter_ST__SC_CFG1 0x40342858u +#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_CNT_REG 0x40340320u +#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_CONTROL_REG 0x40340320u +#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_REG 0x40341620u +#define SDIO_HOST_bSDIO_CMD__16BIT_A0_REG 0x40341018u +#define SDIO_HOST_bSDIO_CMD__16BIT_A1_REG 0x40341118u +#define SDIO_HOST_bSDIO_CMD__16BIT_D0_REG 0x40341218u +#define SDIO_HOST_bSDIO_CMD__16BIT_D1_REG 0x40341318u +#define SDIO_HOST_bSDIO_CMD__16BIT_DP_AUX_CTL_REG 0x40341918u +#define SDIO_HOST_bSDIO_CMD__16BIT_F0_REG 0x40341418u +#define SDIO_HOST_bSDIO_CMD__16BIT_F1_REG 0x40341518u +#define SDIO_HOST_bSDIO_CMD__32BIT_A0_REG 0x40341018u +#define SDIO_HOST_bSDIO_CMD__32BIT_A1_REG 0x40341118u +#define SDIO_HOST_bSDIO_CMD__32BIT_D0_REG 0x40341218u +#define SDIO_HOST_bSDIO_CMD__32BIT_D1_REG 0x40341318u +#define SDIO_HOST_bSDIO_CMD__32BIT_DP_AUX_CTL_REG 0x40341918u +#define SDIO_HOST_bSDIO_CMD__32BIT_F0_REG 0x40341418u +#define SDIO_HOST_bSDIO_CMD__32BIT_F1_REG 0x40341518u +#define SDIO_HOST_bSDIO_CMD__A0_A1_REG 0x40340018u +#define SDIO_HOST_bSDIO_CMD__A0_REG 0x40341018u +#define SDIO_HOST_bSDIO_CMD__A1_REG 0x40341118u +#define SDIO_HOST_bSDIO_CMD__D0_D1_REG 0x40340118u +#define SDIO_HOST_bSDIO_CMD__D0_REG 0x40341218u +#define SDIO_HOST_bSDIO_CMD__D1_REG 0x40341318u +#define SDIO_HOST_bSDIO_CMD__DP_AUX_CTL_REG 0x40341918u +#define SDIO_HOST_bSDIO_CMD__DPATH_CFG0 0x40342640u +#define SDIO_HOST_bSDIO_CMD__DPATH_CFG1 0x40342644u +#define SDIO_HOST_bSDIO_CMD__DPATH_CFG2 0x40342648u +#define SDIO_HOST_bSDIO_CMD__DPATH_CFG3 0x4034264Cu +#define SDIO_HOST_bSDIO_CMD__DPATH_CFG4 0x40342650u +#define SDIO_HOST_bSDIO_CMD__DPATH_OPC0 0x40342664u +#define SDIO_HOST_bSDIO_CMD__DPATH_OPC1 0x40342668u +#define SDIO_HOST_bSDIO_CMD__DPATH_OPC2 0x4034266Cu +#define SDIO_HOST_bSDIO_CMD__DPATH_OPC3 0x40342670u +#define SDIO_HOST_bSDIO_CMD__F0_F1_REG 0x40340218u +#define SDIO_HOST_bSDIO_CMD__F0_REG 0x40341418u +#define SDIO_HOST_bSDIO_CMD__F1_REG 0x40341518u +#define SDIO_HOST_bSDIO_CMD__RC_CFG0 0x4034265Cu +#define SDIO_HOST_bSDIO_CMD__RC_CFG1 0x40342660u +#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_CONTROL_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_CONTROL_CONTROL_REG 0x4034171Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_CONTROL_COUNT_REG 0x4034171Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_COUNT_CONTROL_REG 0x4034171Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_COUNT_COUNT_REG 0x4034171Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_MASK_MASK_REG 0x4034181Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_MASK_PERIOD_REG 0x4034181Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_PERIOD_MASK_REG 0x4034181Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__16BIT_PERIOD_PERIOD_REG 0x4034181Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_CONTROL_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_CONTROL_REG 0x4034171Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_COUNT_REG 0x4034171Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__32BIT_PERIOD_REG 0x4034181Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_REG 0x4034171Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_ST_REG 0x4034031Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__COUNT_REG 0x4034171Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__COUNT_ST_REG 0x4034031Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__MASK_CTL_AUX_CTL_REG 0x4034041Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__PER_CTL_AUX_CTL_REG 0x4034041Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__PERIOD_REG 0x4034181Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__RC_CFG0 0x403426DCu +#define SDIO_HOST_bSDIO_cmdBitCounter__RC_CFG1 0x403426E0u +#define SDIO_HOST_bSDIO_cmdBitCounter__SC_CFG0 0x403426D4u +#define SDIO_HOST_bSDIO_cmdBitCounter__SC_CFG1 0x403426D8u +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__16BIT_STATUS_REG 0x4034161Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__32BIT_MASK_REG 0x4034181Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__32BIT_STATUS_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__32BIT_STATUS_REG 0x4034161Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__MASK_REG 0x4034181Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__MASK_ST_AUX_CTL_REG 0x4034041Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__PER_ST_AUX_CTL_REG 0x4034041Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__RC_CFG0 0x403426DCu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__RC_CFG1 0x403426E0u +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__SC_CFG0 0x403426D4u +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__SC_CFG1 0x403426D8u +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_CNT_REG 0x4034031Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_CONTROL_REG 0x4034031Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_REG 0x4034161Cu +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341928u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_CONTROL_REG 0x40341728u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_COUNT_REG 0x40341728u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_COUNT_CONTROL_REG 0x40341728u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_COUNT_COUNT_REG 0x40341728u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_MASK_MASK_REG 0x40341828u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_MASK_PERIOD_REG 0x40341828u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_PERIOD_MASK_REG 0x40341828u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_PERIOD_PERIOD_REG 0x40341828u +#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG 0x40341928u +#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_REG 0x40341728u +#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_ST_REG 0x40340328u +#define SDIO_HOST_bSDIO_crcBitCounter__COUNT_REG 0x40341728u +#define SDIO_HOST_bSDIO_crcBitCounter__COUNT_ST_REG 0x40340328u +#define SDIO_HOST_bSDIO_crcBitCounter__MASK_CTL_AUX_CTL_REG 0x40340428u +#define SDIO_HOST_bSDIO_crcBitCounter__PER_CTL_AUX_CTL_REG 0x40340428u +#define SDIO_HOST_bSDIO_crcBitCounter__PERIOD_REG 0x40341828u +#define SDIO_HOST_bSDIO_crcBitCounter__RC_CFG0 0x40342A5Cu +#define SDIO_HOST_bSDIO_crcBitCounter__RC_CFG1 0x40342A60u +#define SDIO_HOST_bSDIO_crcBitCounter__SC_CFG0 0x40342A54u +#define SDIO_HOST_bSDIO_crcBitCounter__SC_CFG1 0x40342A58u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341928u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__16BIT_STATUS_REG 0x40341628u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__MASK_REG 0x40341828u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__MASK_ST_AUX_CTL_REG 0x40340428u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__PER_ST_AUX_CTL_REG 0x40340428u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__RC_CFG0 0x40342A5Cu +#define SDIO_HOST_bSDIO_crcBitCounter_ST__RC_CFG1 0x40342A60u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__SC_CFG0 0x40342A54u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__SC_CFG1 0x40342A58u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_AUX_CTL_REG 0x40341928u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_CNT_REG 0x40340328u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_CONTROL_REG 0x40340328u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_REG 0x40341628u +#define SDIO_HOST_bSDIO_CtrlReg__0__MASK 0x01u +#define SDIO_HOST_bSDIO_CtrlReg__0__POS 0 +#define SDIO_HOST_bSDIO_CtrlReg__1__MASK 0x02u +#define SDIO_HOST_bSDIO_CtrlReg__1__POS 1 +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_CONTROL_REG 0x40341714u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_COUNT_REG 0x40341714u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_COUNT_CONTROL_REG 0x40341714u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_COUNT_COUNT_REG 0x40341714u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_MASK_MASK_REG 0x40341814u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_MASK_PERIOD_REG 0x40341814u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_PERIOD_MASK_REG 0x40341814u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_PERIOD_PERIOD_REG 0x40341814u +#define SDIO_HOST_bSDIO_CtrlReg__2__MASK 0x04u +#define SDIO_HOST_bSDIO_CtrlReg__2__POS 2 +#define SDIO_HOST_bSDIO_CtrlReg__3__MASK 0x08u +#define SDIO_HOST_bSDIO_CtrlReg__3__POS 3 +#define SDIO_HOST_bSDIO_CtrlReg__32BIT_CONTROL_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_CtrlReg__32BIT_CONTROL_REG 0x40341714u +#define SDIO_HOST_bSDIO_CtrlReg__32BIT_COUNT_REG 0x40341714u +#define SDIO_HOST_bSDIO_CtrlReg__32BIT_PERIOD_REG 0x40341814u +#define SDIO_HOST_bSDIO_CtrlReg__4__MASK 0x10u +#define SDIO_HOST_bSDIO_CtrlReg__4__POS 4 +#define SDIO_HOST_bSDIO_CtrlReg__6__MASK 0x40u +#define SDIO_HOST_bSDIO_CtrlReg__6__POS 6 +#define SDIO_HOST_bSDIO_CtrlReg__7__MASK 0x80u +#define SDIO_HOST_bSDIO_CtrlReg__7__POS 7 +#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG 0x40341714u +#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_ST_REG 0x40340314u +#define SDIO_HOST_bSDIO_CtrlReg__COUNT_REG 0x40341714u +#define SDIO_HOST_bSDIO_CtrlReg__COUNT_ST_REG 0x40340314u +#define SDIO_HOST_bSDIO_CtrlReg__MASK 0xDFu +#define SDIO_HOST_bSDIO_CtrlReg__MASK_CTL_AUX_CTL_REG 0x40340414u +#define SDIO_HOST_bSDIO_CtrlReg__PER_CTL_AUX_CTL_REG 0x40340414u +#define SDIO_HOST_bSDIO_CtrlReg__PERIOD_REG 0x40341814u +#define SDIO_HOST_bSDIO_CtrlReg__RC_CFG0 0x403424DCu +#define SDIO_HOST_bSDIO_CtrlReg__RC_CFG1 0x403424E0u +#define SDIO_HOST_bSDIO_CtrlReg__SC_CFG0 0x403424D4u +#define SDIO_HOST_bSDIO_CtrlReg__SC_CFG1 0x403424D8u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_A0_REG 0x40341000u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_A1_REG 0x40341100u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_D0_REG 0x40341200u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_D1_REG 0x40341300u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_DP_AUX_CTL_REG 0x40341900u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_F0_REG 0x40341400u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_F1_REG 0x40341500u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_A0_REG 0x40341000u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_A1_REG 0x40341100u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_D0_REG 0x40341200u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_D1_REG 0x40341300u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_DP_AUX_CTL_REG 0x40341900u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_F0_REG 0x40341400u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_F1_REG 0x40341500u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A0_A1_REG 0x40340000u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A0_REG 0x40341000u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A1_REG 0x40341100u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D0_D1_REG 0x40340100u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D0_REG 0x40341200u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D1_REG 0x40341300u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DP_AUX_CTL_REG 0x40341900u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG0 0x40342040u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG1 0x40342044u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG2 0x40342048u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG3 0x4034204Cu +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG4 0x40342050u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC0 0x40342064u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC1 0x40342068u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC2 0x4034206Cu +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC3 0x40342070u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F0_F1_REG 0x40340200u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F0_REG 0x40341400u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F1_REG 0x40341500u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__RC_CFG0 0x4034205Cu +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__RC_CFG1 0x40342060u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_A0_REG 0x40341004u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_A1_REG 0x40341104u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_D0_REG 0x40341204u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_D1_REG 0x40341304u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_DP_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_F0_REG 0x40341404u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_F1_REG 0x40341504u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_A0_REG 0x40341004u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_A1_REG 0x40341104u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_D0_REG 0x40341204u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_D1_REG 0x40341304u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_DP_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_F0_REG 0x40341404u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_F1_REG 0x40341504u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A0_A1_REG 0x40340004u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A0_REG 0x40341004u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A1_REG 0x40341104u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D0_D1_REG 0x40340104u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D0_REG 0x40341204u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D1_REG 0x40341304u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DP_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG0 0x403420C0u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG1 0x403420C4u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG2 0x403420C8u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG3 0x403420CCu +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG4 0x403420D0u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC0 0x403420E4u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC1 0x403420E8u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC2 0x403420ECu +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC3 0x403420F0u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F0_F1_REG 0x40340204u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F0_REG 0x40341404u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F1_REG 0x40341504u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__MSK_DP_AUX_CTL_REG 0x40340404u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__PER_DP_AUX_CTL_REG 0x40340404u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__RC_CFG0 0x403420DCu +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__RC_CFG1 0x403420E0u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_A0_REG 0x40341010u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_A1_REG 0x40341110u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_D0_REG 0x40341210u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_D1_REG 0x40341310u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_DP_AUX_CTL_REG 0x40341910u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_F0_REG 0x40341410u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_F1_REG 0x40341510u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_A0_REG 0x40341010u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_A1_REG 0x40341110u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_D0_REG 0x40341210u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_D1_REG 0x40341310u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_DP_AUX_CTL_REG 0x40341910u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_F0_REG 0x40341410u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__32BIT_F1_REG 0x40341510u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A0_A1_REG 0x40340010u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A0_REG 0x40341010u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A1_REG 0x40341110u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D0_D1_REG 0x40340110u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D0_REG 0x40341210u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D1_REG 0x40341310u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DP_AUX_CTL_REG 0x40341910u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG0 0x40342440u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG1 0x40342444u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG2 0x40342448u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG3 0x4034244Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG4 0x40342450u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC0 0x40342464u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC1 0x40342468u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC2 0x4034246Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC3 0x40342470u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F0_F1_REG 0x40340210u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F0_REG 0x40341410u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F1_REG 0x40341510u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__RC_CFG0 0x4034245Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__RC_CFG1 0x40342460u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_A0_REG 0x40341014u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_A1_REG 0x40341114u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_D0_REG 0x40341214u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_D1_REG 0x40341314u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_DP_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_F0_REG 0x40341414u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__16BIT_F1_REG 0x40341514u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_A0_REG 0x40341014u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_A1_REG 0x40341114u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_D0_REG 0x40341214u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_D1_REG 0x40341314u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_DP_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_F0_REG 0x40341414u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__32BIT_F1_REG 0x40341514u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A0_A1_REG 0x40340014u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A0_REG 0x40341014u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A1_REG 0x40341114u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D0_D1_REG 0x40340114u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D0_REG 0x40341214u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D1_REG 0x40341314u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DP_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG0 0x403424C0u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG1 0x403424C4u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG2 0x403424C8u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG3 0x403424CCu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG4 0x403424D0u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC0 0x403424E4u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC1 0x403424E8u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC2 0x403424ECu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC3 0x403424F0u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F0_F1_REG 0x40340214u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F0_REG 0x40341414u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F1_REG 0x40341514u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__MSK_DP_AUX_CTL_REG 0x40340414u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__PER_DP_AUX_CTL_REG 0x40340414u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__RC_CFG0 0x403424DCu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__RC_CFG1 0x403424E0u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_A0_REG 0x40341028u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_A1_REG 0x40341128u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_D0_REG 0x40341228u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_D1_REG 0x40341328u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_DP_AUX_CTL_REG 0x40341928u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_F0_REG 0x40341428u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_F1_REG 0x40341528u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A0_A1_REG 0x40340028u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A0_REG 0x40341028u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A1_REG 0x40341128u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D0_D1_REG 0x40340128u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D0_REG 0x40341228u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D1_REG 0x40341328u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DP_AUX_CTL_REG 0x40341928u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG0 0x40342A40u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG1 0x40342A44u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG2 0x40342A48u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG3 0x40342A4Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG4 0x40342A50u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC0 0x40342A64u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC1 0x40342A68u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC2 0x40342A6Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC3 0x40342A70u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F0_F1_REG 0x40340228u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F0_REG 0x40341428u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F1_REG 0x40341528u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__MSK_DP_AUX_CTL_REG 0x40340428u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__PER_DP_AUX_CTL_REG 0x40340428u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__RC_CFG0 0x40342A5Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__RC_CFG1 0x40342A60u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A0_A1_REG 0x4034002Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A0_REG 0x4034102Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A1_REG 0x4034112Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D0_D1_REG 0x4034012Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D0_REG 0x4034122Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D1_REG 0x4034132Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DP_AUX_CTL_REG 0x4034192Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG0 0x40342AC0u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG1 0x40342AC4u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG2 0x40342AC8u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG3 0x40342ACCu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG4 0x40342AD0u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC0 0x40342AE4u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC1 0x40342AE8u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC2 0x40342AECu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC3 0x40342AF0u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F0_F1_REG 0x4034022Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F0_REG 0x4034142Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F1_REG 0x4034152Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__MSK_DP_AUX_CTL_REG 0x4034042Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__PER_DP_AUX_CTL_REG 0x4034042Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__RC_CFG0 0x40342ADCu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__RC_CFG1 0x40342AE0u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_A0_REG 0x40341020u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_A1_REG 0x40341120u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_D0_REG 0x40341220u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_D1_REG 0x40341320u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_DP_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_F0_REG 0x40341420u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_F1_REG 0x40341520u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_A0_REG 0x40341020u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_A1_REG 0x40341120u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_D0_REG 0x40341220u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_D1_REG 0x40341320u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_DP_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_F0_REG 0x40341420u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_F1_REG 0x40341520u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A0_A1_REG 0x40340020u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A0_REG 0x40341020u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A1_REG 0x40341120u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D0_D1_REG 0x40340120u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D0_REG 0x40341220u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D1_REG 0x40341320u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DP_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG0 0x40342840u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG1 0x40342844u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG2 0x40342848u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG3 0x4034284Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG4 0x40342850u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC0 0x40342864u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC1 0x40342868u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC2 0x4034286Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC3 0x40342870u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F0_F1_REG 0x40340220u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F0_REG 0x40341420u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F1_REG 0x40341520u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__MSK_DP_AUX_CTL_REG 0x40340420u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__PER_DP_AUX_CTL_REG 0x40340420u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__RC_CFG0 0x4034285Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__RC_CFG1 0x40342860u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_A0_REG 0x40341024u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_A1_REG 0x40341124u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_D0_REG 0x40341224u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_D1_REG 0x40341324u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_DP_AUX_CTL_REG 0x40341924u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_F0_REG 0x40341424u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_F1_REG 0x40341524u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A0_A1_REG 0x40340024u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A0_REG 0x40341024u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A1_REG 0x40341124u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D0_D1_REG 0x40340124u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D0_REG 0x40341224u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D1_REG 0x40341324u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DP_AUX_CTL_REG 0x40341924u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG0 0x403428C0u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG1 0x403428C4u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG2 0x403428C8u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG3 0x403428CCu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG4 0x403428D0u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC0 0x403428E4u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC1 0x403428E8u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC2 0x403428ECu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC3 0x403428F0u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F0_F1_REG 0x40340224u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F0_REG 0x40341424u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F1_REG 0x40341524u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__RC_CFG0 0x403428DCu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__RC_CFG1 0x403428E0u +#define SDIO_HOST_bSDIO_Read_DP__16BIT_A0_REG 0x4034100Cu +#define SDIO_HOST_bSDIO_Read_DP__16BIT_A1_REG 0x4034110Cu +#define SDIO_HOST_bSDIO_Read_DP__16BIT_D0_REG 0x4034120Cu +#define SDIO_HOST_bSDIO_Read_DP__16BIT_D1_REG 0x4034130Cu +#define SDIO_HOST_bSDIO_Read_DP__16BIT_DP_AUX_CTL_REG 0x4034190Cu +#define SDIO_HOST_bSDIO_Read_DP__16BIT_F0_REG 0x4034140Cu +#define SDIO_HOST_bSDIO_Read_DP__16BIT_F1_REG 0x4034150Cu +#define SDIO_HOST_bSDIO_Read_DP__32BIT_A0_REG 0x4034100Cu +#define SDIO_HOST_bSDIO_Read_DP__32BIT_A1_REG 0x4034110Cu +#define SDIO_HOST_bSDIO_Read_DP__32BIT_D0_REG 0x4034120Cu +#define SDIO_HOST_bSDIO_Read_DP__32BIT_D1_REG 0x4034130Cu +#define SDIO_HOST_bSDIO_Read_DP__32BIT_DP_AUX_CTL_REG 0x4034190Cu +#define SDIO_HOST_bSDIO_Read_DP__32BIT_F0_REG 0x4034140Cu +#define SDIO_HOST_bSDIO_Read_DP__32BIT_F1_REG 0x4034150Cu +#define SDIO_HOST_bSDIO_Read_DP__A0_A1_REG 0x4034000Cu +#define SDIO_HOST_bSDIO_Read_DP__A0_REG 0x4034100Cu +#define SDIO_HOST_bSDIO_Read_DP__A1_REG 0x4034110Cu +#define SDIO_HOST_bSDIO_Read_DP__D0_D1_REG 0x4034010Cu +#define SDIO_HOST_bSDIO_Read_DP__D0_REG 0x4034120Cu +#define SDIO_HOST_bSDIO_Read_DP__D1_REG 0x4034130Cu +#define SDIO_HOST_bSDIO_Read_DP__DP_AUX_CTL_REG 0x4034190Cu +#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG0 0x403422C0u +#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG1 0x403422C4u +#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG2 0x403422C8u +#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG3 0x403422CCu +#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG4 0x403422D0u +#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC0 0x403422E4u +#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC1 0x403422E8u +#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC2 0x403422ECu +#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC3 0x403422F0u +#define SDIO_HOST_bSDIO_Read_DP__F0_F1_REG 0x4034020Cu +#define SDIO_HOST_bSDIO_Read_DP__F0_REG 0x4034140Cu +#define SDIO_HOST_bSDIO_Read_DP__F1_REG 0x4034150Cu +#define SDIO_HOST_bSDIO_Read_DP__RC_CFG0 0x403422DCu +#define SDIO_HOST_bSDIO_Read_DP__RC_CFG1 0x403422E0u +#define SDIO_HOST_bSDIO_Read_DP_PI__16BIT_STATUS_AUX_CTL_REG 0x4034190Cu +#define SDIO_HOST_bSDIO_Read_DP_PI__16BIT_STATUS_REG 0x4034160Cu +#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_MASK_REG 0x4034180Cu +#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_STATUS_AUX_CTL_REG 0x4034190Cu +#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_STATUS_REG 0x4034160Cu +#define SDIO_HOST_bSDIO_Read_DP_PI__MASK_REG 0x4034180Cu +#define SDIO_HOST_bSDIO_Read_DP_PI__RC_CFG0 0x403422DCu +#define SDIO_HOST_bSDIO_Read_DP_PI__RC_CFG1 0x403422E0u +#define SDIO_HOST_bSDIO_Read_DP_PI__SC_CFG0 0x403422D4u +#define SDIO_HOST_bSDIO_Read_DP_PI__SC_CFG1 0x403422D8u +#define SDIO_HOST_bSDIO_Read_DP_PI__STATUS_AUX_CTL_REG 0x4034190Cu +#define SDIO_HOST_bSDIO_Read_DP_PI__STATUS_REG 0x4034160Cu +#define SDIO_HOST_bSDIO_StatusReg__0__MASK 0x01u +#define SDIO_HOST_bSDIO_StatusReg__0__POS 0 +#define SDIO_HOST_bSDIO_StatusReg__1__MASK 0x02u +#define SDIO_HOST_bSDIO_StatusReg__1__POS 1 +#define SDIO_HOST_bSDIO_StatusReg__16BIT_STATUS_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_StatusReg__16BIT_STATUS_REG 0x40341614u +#define SDIO_HOST_bSDIO_StatusReg__2__MASK 0x04u +#define SDIO_HOST_bSDIO_StatusReg__2__POS 2 +#define SDIO_HOST_bSDIO_StatusReg__3__MASK 0x08u +#define SDIO_HOST_bSDIO_StatusReg__3__POS 3 +#define SDIO_HOST_bSDIO_StatusReg__32BIT_MASK_REG 0x40341814u +#define SDIO_HOST_bSDIO_StatusReg__32BIT_STATUS_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_StatusReg__32BIT_STATUS_REG 0x40341614u +#define SDIO_HOST_bSDIO_StatusReg__6__MASK 0x40u +#define SDIO_HOST_bSDIO_StatusReg__6__POS 6 +#define SDIO_HOST_bSDIO_StatusReg__MASK 0x4Fu +#define SDIO_HOST_bSDIO_StatusReg__MASK_REG 0x40341814u +#define SDIO_HOST_bSDIO_StatusReg__MASK_ST_AUX_CTL_REG 0x40340414u +#define SDIO_HOST_bSDIO_StatusReg__PER_ST_AUX_CTL_REG 0x40340414u +#define SDIO_HOST_bSDIO_StatusReg__RC_CFG0 0x403424DCu +#define SDIO_HOST_bSDIO_StatusReg__RC_CFG1 0x403424E0u +#define SDIO_HOST_bSDIO_StatusReg__SC_CFG0 0x403424D4u +#define SDIO_HOST_bSDIO_StatusReg__SC_CFG1 0x403424D8u +#define SDIO_HOST_bSDIO_StatusReg__STATUS_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_StatusReg__STATUS_CNT_REG 0x40340314u +#define SDIO_HOST_bSDIO_StatusReg__STATUS_CONTROL_REG 0x40340314u +#define SDIO_HOST_bSDIO_StatusReg__STATUS_REG 0x40341614u +#define SDIO_HOST_bSDIO_Write_DP__16BIT_A0_REG 0x40341008u +#define SDIO_HOST_bSDIO_Write_DP__16BIT_A1_REG 0x40341108u +#define SDIO_HOST_bSDIO_Write_DP__16BIT_D0_REG 0x40341208u +#define SDIO_HOST_bSDIO_Write_DP__16BIT_D1_REG 0x40341308u +#define SDIO_HOST_bSDIO_Write_DP__16BIT_DP_AUX_CTL_REG 0x40341908u +#define SDIO_HOST_bSDIO_Write_DP__16BIT_F0_REG 0x40341408u +#define SDIO_HOST_bSDIO_Write_DP__16BIT_F1_REG 0x40341508u +#define SDIO_HOST_bSDIO_Write_DP__32BIT_A0_REG 0x40341008u +#define SDIO_HOST_bSDIO_Write_DP__32BIT_A1_REG 0x40341108u +#define SDIO_HOST_bSDIO_Write_DP__32BIT_D0_REG 0x40341208u +#define SDIO_HOST_bSDIO_Write_DP__32BIT_D1_REG 0x40341308u +#define SDIO_HOST_bSDIO_Write_DP__32BIT_DP_AUX_CTL_REG 0x40341908u +#define SDIO_HOST_bSDIO_Write_DP__32BIT_F0_REG 0x40341408u +#define SDIO_HOST_bSDIO_Write_DP__32BIT_F1_REG 0x40341508u +#define SDIO_HOST_bSDIO_Write_DP__A0_A1_REG 0x40340008u +#define SDIO_HOST_bSDIO_Write_DP__A0_REG 0x40341008u +#define SDIO_HOST_bSDIO_Write_DP__A1_REG 0x40341108u +#define SDIO_HOST_bSDIO_Write_DP__D0_D1_REG 0x40340108u +#define SDIO_HOST_bSDIO_Write_DP__D0_REG 0x40341208u +#define SDIO_HOST_bSDIO_Write_DP__D1_REG 0x40341308u +#define SDIO_HOST_bSDIO_Write_DP__DP_AUX_CTL_REG 0x40341908u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG0 0x40342240u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG1 0x40342244u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG2 0x40342248u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG3 0x4034224Cu +#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG4 0x40342250u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC0 0x40342264u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC1 0x40342268u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC2 0x4034226Cu +#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC3 0x40342270u +#define SDIO_HOST_bSDIO_Write_DP__F0_F1_REG 0x40340208u +#define SDIO_HOST_bSDIO_Write_DP__F0_REG 0x40341408u +#define SDIO_HOST_bSDIO_Write_DP__F1_REG 0x40341508u +#define SDIO_HOST_bSDIO_Write_DP__MSK_DP_AUX_CTL_REG 0x40340408u +#define SDIO_HOST_bSDIO_Write_DP__PER_DP_AUX_CTL_REG 0x40340408u +#define SDIO_HOST_bSDIO_Write_DP__RC_CFG0 0x4034225Cu +#define SDIO_HOST_bSDIO_Write_DP__RC_CFG1 0x40342260u +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_AUX_CTL_REG 0x40341908u +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_CONTROL_REG 0x40341708u +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_COUNT_REG 0x40341708u +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_COUNT_CONTROL_REG 0x40341708u +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_COUNT_COUNT_REG 0x40341708u +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_MASK_MASK_REG 0x40341808u +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_MASK_PERIOD_REG 0x40341808u +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_PERIOD_MASK_REG 0x40341808u +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_PERIOD_PERIOD_REG 0x40341808u +#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_CONTROL_AUX_CTL_REG 0x40341908u +#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_CONTROL_REG 0x40341708u +#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_COUNT_REG 0x40341708u +#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_PERIOD_REG 0x40341808u +#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_AUX_CTL_REG 0x40341908u +#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_REG 0x40341708u +#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_ST_REG 0x40340308u +#define SDIO_HOST_bSDIO_Write_DP_PO__COUNT_REG 0x40341708u +#define SDIO_HOST_bSDIO_Write_DP_PO__COUNT_ST_REG 0x40340308u +#define SDIO_HOST_bSDIO_Write_DP_PO__MASK_CTL_AUX_CTL_REG 0x40340408u +#define SDIO_HOST_bSDIO_Write_DP_PO__PER_CTL_AUX_CTL_REG 0x40340408u +#define SDIO_HOST_bSDIO_Write_DP_PO__PERIOD_REG 0x40341808u +#define SDIO_HOST_bSDIO_Write_DP_PO__RC_CFG0 0x4034225Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__RC_CFG1 0x40342260u +#define SDIO_HOST_bSDIO_Write_DP_PO__SC_CFG0 0x40342254u +#define SDIO_HOST_bSDIO_Write_DP_PO__SC_CFG1 0x40342258u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_CONTROL_REG 0x40341704u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_COUNT_REG 0x40341704u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_COUNT_CONTROL_REG 0x40341704u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_COUNT_COUNT_REG 0x40341704u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_MASK_MASK_REG 0x40341804u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_MASK_PERIOD_REG 0x40341804u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_PERIOD_MASK_REG 0x40341804u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_PERIOD_PERIOD_REG 0x40341804u +#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_CONTROL_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_CONTROL_REG 0x40341704u +#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_COUNT_REG 0x40341704u +#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_PERIOD_REG 0x40341804u +#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_REG 0x40341704u +#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_ST_REG 0x40340304u +#define SDIO_HOST_bSDIO_writeCrcCounter__COUNT_REG 0x40341704u +#define SDIO_HOST_bSDIO_writeCrcCounter__COUNT_ST_REG 0x40340304u +#define SDIO_HOST_bSDIO_writeCrcCounter__MASK_CTL_AUX_CTL_REG 0x40340404u +#define SDIO_HOST_bSDIO_writeCrcCounter__PER_CTL_AUX_CTL_REG 0x40340404u +#define SDIO_HOST_bSDIO_writeCrcCounter__PERIOD_REG 0x40341804u +#define SDIO_HOST_bSDIO_writeCrcCounter__RC_CFG0 0x403420DCu +#define SDIO_HOST_bSDIO_writeCrcCounter__RC_CFG1 0x403420E0u +#define SDIO_HOST_bSDIO_writeCrcCounter__SC_CFG0 0x403420D4u +#define SDIO_HOST_bSDIO_writeCrcCounter__SC_CFG1 0x403420D8u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__16BIT_STATUS_REG 0x40341604u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_MASK_REG 0x40341804u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_STATUS_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_STATUS_REG 0x40341604u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__MASK_REG 0x40341804u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__MASK_ST_AUX_CTL_REG 0x40340404u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__PER_ST_AUX_CTL_REG 0x40340404u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__RC_CFG0 0x403420DCu +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__RC_CFG1 0x403420E0u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__SC_CFG0 0x403420D4u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__SC_CFG1 0x403420D8u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_CNT_REG 0x40340304u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_CONTROL_REG 0x40340304u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_REG 0x40341604u +#define SDIO_HOST_CMD_DMA_DW__BLOCK_HW DW0 +#define SDIO_HOST_CMD_DMA_DW__BLOCK_NUMBER 0u +#define SDIO_HOST_CMD_DMA_DW__CHANNEL_HW DW0_CH_STRUCT1 +#define SDIO_HOST_CMD_DMA_DW__CHANNEL_NUMBER 1u +#define SDIO_HOST_CMD_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN1 +#define SDIO_HOST_Internal_Clock__DIV_IDX 0 +#define SDIO_HOST_Internal_Clock__DIV_NUM 0 +#define SDIO_HOST_Internal_Clock__DIV_TYPE CY_SYSCLK_DIV_8_BIT +#define SDIO_HOST_Read_DMA_DW__BLOCK_HW DW1 +#define SDIO_HOST_Read_DMA_DW__BLOCK_NUMBER 1u +#define SDIO_HOST_Read_DMA_DW__CHANNEL_HW DW1_CH_STRUCT3 +#define SDIO_HOST_Read_DMA_DW__CHANNEL_NUMBER 3u +#define SDIO_HOST_Read_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN3 +#define SDIO_HOST_Resp_DMA_DW__BLOCK_HW DW0 +#define SDIO_HOST_Resp_DMA_DW__BLOCK_NUMBER 0u +#define SDIO_HOST_Resp_DMA_DW__CHANNEL_HW DW0_CH_STRUCT0 +#define SDIO_HOST_Resp_DMA_DW__CHANNEL_NUMBER 0u +#define SDIO_HOST_Resp_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN0 +#define SDIO_HOST_Write_DMA_DW__BLOCK_HW DW1 +#define SDIO_HOST_Write_DMA_DW__BLOCK_NUMBER 1u +#define SDIO_HOST_Write_DMA_DW__CHANNEL_HW DW1_CH_STRUCT1 +#define SDIO_HOST_Write_DMA_DW__CHANNEL_NUMBER 1u +#define SDIO_HOST_Write_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN1 + + +/***************************CMD DMA***************************************/ +#define SDIO_HOST_CMD_DMA_DW_BLOCK (0u) +#define SDIO_HOST_CMD_DMA_DW_CHANNEL (1u) +#define SDIO_HOST_CMD_DMA_HW (DW0) +#define SDIO_HOST_CMD_DMA_INTR_MASK (CY_DMA_INTR_MASK) + +/* Channel settings */ +#define SDIO_HOST_CMD_DMA_PRIORITY (1u) +#define SDIO_HOST_CMD_DMA_DESCRIPTOR_NUM (1u) +#define SDIO_HOST_CMD_DMA_PREEMPTABLE (true) + +extern cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config; +extern cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc; + +/***************************Read DMA***************************************/ +#define SDIO_HOST_Read_DMA_DW_BLOCK (1u) +#define SDIO_HOST_Read_DMA_DW_CHANNEL (3u) +#define SDIO_HOST_Read_DMA_HW (DW1) +#define SDIO_HOST_Read_DMA_INTR_MASK (CY_DMA_INTR_MASK) + +/* Channel settings */ +#define SDIO_HOST_Read_DMA_PRIORITY (0u) +#define SDIO_HOST_Read_DMA_DESCRIPTOR_NUM (1u) +#define SDIO_HOST_Read_DMA_PREEMPTABLE (false) + +extern cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config; +extern cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc; + +/***************************Resp DMA***************************************/ +#define SDIO_HOST_Resp_DMA_DW_BLOCK (0u) +#define SDIO_HOST_Resp_DMA_DW_CHANNEL (0u) +#define SDIO_HOST_Resp_DMA_HW (DW0) +#define SDIO_HOST_Resp_DMA_INTR_MASK (CY_DMA_INTR_MASK) + +/* Channel settings */ +#define SDIO_HOST_Resp_DMA_PRIORITY (1u) +#define SDIO_HOST_Resp_DMA_DESCRIPTOR_NUM (1u) +#define SDIO_HOST_Resp_DMA_PREEMPTABLE (true) + +extern cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config; +extern cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc; + +/***************************Write DMA***************************************/ +#define SDIO_HOST_Write_DMA_DW_BLOCK (1u) +#define SDIO_HOST_Write_DMA_DW_CHANNEL (1u) +#define SDIO_HOST_Write_DMA_HW (DW1) +#define SDIO_HOST_Write_DMA_INTR_MASK (CY_DMA_INTR_MASK) + +/* Channel settings */ +#define SDIO_HOST_Write_DMA_PRIORITY (0u) +#define SDIO_HOST_Write_DMA_DESCRIPTOR_NUM (1u) +#define SDIO_HOST_Write_DMA_PREEMPTABLE (false) + +extern cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config; +extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc; + +/***************************SDIO Clock**************************************/ +/* The peripheral clock divider number */ +#define SDIO_HOST_Internal_Clock_DIV_NUM ((uint32_t)0) +/* The peripheral clock divider type */ +#define SDIO_HOST_Internal_Clock_DIV_TYPE ((cy_en_divider_types_t)CY_SYSCLK_DIV_8_BIT) + + +/*Function for configuring UDBs*/ +void SDIO_Host_Config_UDBs(void); + +/* SDIO_HOST_Read_Int */ +#define SDIO_HOST_Read_Int__INTC_CORTEXM4_ASSIGNED 1 +#define SDIO_HOST_Read_Int__INTC_CORTEXM4_PRIORITY 7u +#define SDIO_HOST_Read_Int__INTC_NUMBER 69u +#define SDIO_HOST_Read_Int_INTC_CORTEXM4_ASSIGNED 1 +#define SDIO_HOST_Read_Int_INTC_CORTEXM4_PRIORITY 7u +#define SDIO_HOST_Read_Int_INTC_NUMBER 69u + +/* SDIO_HOST_sdio_int */ +#define SDIO_HOST_sdio_int__INTC_CORTEXM4_ASSIGNED 1 +#define SDIO_HOST_sdio_int__INTC_CORTEXM4_PRIORITY 7u +#define SDIO_HOST_sdio_int__INTC_NUMBER 122u +#define SDIO_HOST_sdio_int_INTC_CORTEXM4_ASSIGNED 1 +#define SDIO_HOST_sdio_int_INTC_CORTEXM4_PRIORITY 7u +#define SDIO_HOST_sdio_int_INTC_NUMBER 122u + +/* SDIO_HOST_Write_Int */ +#define SDIO_HOST_Write_Int__INTC_CORTEXM4_ASSIGNED 1 +#define SDIO_HOST_Write_Int__INTC_CORTEXM4_PRIORITY 7u +#define SDIO_HOST_Write_Int__INTC_NUMBER 67u +#define SDIO_HOST_Write_Int_INTC_CORTEXM4_ASSIGNED 1 +#define SDIO_HOST_Write_Int_INTC_CORTEXM4_PRIORITY 7u +#define SDIO_HOST_Write_Int_INTC_NUMBER 67u + +#if defined(__cplusplus) +} +#endif + +#endif /* !defined(CY_SDIO_CFG_H) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp_cyw943012p6evb_01.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp_cyw943012p6evb_01.c new file mode 100644 index 0000000000..4af9d9fbb7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp_cyw943012p6evb_01.c @@ -0,0 +1,76 @@ +/***************************************************************************//** +* \file cybsp_cyw943012p6evb_01.c +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CYW943012P6EVB-01 kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "cybsp_cyw943012p6evb_01.h" +#include "cyhal_implementation.h" +#include "cycfg.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +cy_rslt_t cybsp_init(void) +{ + init_cycfg_system(); + + cy_rslt_t result = CY_RSLT_SUCCESS; + +#ifndef __MBED__ + /* Initialize User LEDs */ + result |= cybsp_led_init(CYBSP_USER_LED1); + result |= cybsp_led_init(CYBSP_USER_LED2); + result |= cybsp_led_init(CYBSP_USER_LED3); + /* Initialize User Buttons */ + result |= cybsp_btn_init(CYBSP_USER_BTN1); + + CY_ASSERT(CY_RSLT_SUCCESS == result); +#endif + +#if defined(CYBSP_WIFI_CAPABLE) + /* Initialize UDB SDIO interface. This must be done before any other HAL API attempts to allocate clocks or DMA + instances. The UDB SDIO interface uses specific instances which are reserved as part of this call. + NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init(). This is typically done + when starting up WiFi. */ + if (CY_RSLT_SUCCESS == result) + { + result = cybsp_sdio_init(); + } +#endif + +#if defined(CYBSP_RETARGET_ENABLED) + /* Initialize retargetting stdio to 'DEBUG_UART' peripheral */ + if (CY_RSLT_SUCCESS == result) + { + result = cybsp_retarget_init(); + } +#endif + + return result; +} + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp_cyw943012p6evb_01.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp_cyw943012p6evb_01.h new file mode 100644 index 0000000000..d0df079f60 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp_cyw943012p6evb_01.h @@ -0,0 +1,72 @@ +/***************************************************************************//** +* \file cybsp_cyw943012p6evb_01.h +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CYW943012P6EVB-01 kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_bsp_cyw943012p6evb_01 CYW943012P6EVB-01 +* \ingroup group_bsp +* \{ +* The PSoC 6 CYW943012P6EVB-01 board is a low-cost hardware platform that +* enables design and debug of the PSoC 62 MCU (CY8C6247BZI-D54) and the +* Murata LBEE59B1LV Module (CYW43012 WiFi + Bluetooth Combo Chip). +* +*
Kit Features:
+*
    +*
  • BLE v5.0
    • +*
  • Serial memory interface
    • +*
  • PDM-PCM digital microphone interface
    • +*
  • Industry-leading CapSense
    • +*
+* +*
Kit Contents:
+*
    +*
  • CYW943012P6EVB-01 evaluation board
    • +*
  • USB cable
    • +*
+* +* \defgroup group_bsp_cyw943012p6evb_01_macros Macros +* \defgroup group_bsp_cyw943012p6evb_01_functions Functions +* \defgroup group_bsp_cyw943012p6evb_01_enums Enumerated Types +*/ + +#pragma once + +#ifdef MBED +#include "cybsp_api_wifi.h" +#else +#include "cybsp_api_core.h" +#endif /* MBED */ + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \cond INTERNAL */ +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +/** \} group_bsp_cyw943012p6evb_01 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp_types.h new file mode 100644 index 0000000000..5510cd7d28 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp_types.h @@ -0,0 +1,260 @@ +/***************************************************************************//** +* \file CYW943012P6EVB-01/cybsp_types.h +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CYW943012P6EVB-01 pioneer kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_bsp_cyw943012p6evb_01 CYW943012P6EVB-01 +* \ingroup group_bsp +* \{ +* \defgroup group_bsp_cyw943012p6evb_01_macros Macros +* \defgroup group_bsp_cyw943012p6evb_01_enums Enumerated Types +*/ + +#pragma once + +#include "cyhal.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_bsp_cyw943012p6evb_01_macros +* \{ +*/ + +// Generic signal names +/** Pin: CYBSP_WCO_IN */ +#define CYBSP_WCO_IN P0_0 +/** Pin: CYBSP_WCO_OUT */ +#define CYBSP_WCO_OUT P0_1 + +/** Pin: CYBSP_CSD_TX */ +#define CYBSP_CSD_TX P1_0 +/** Pin: CYBSP_WL_SECI_IN */ +#define CYBSP_WL_SECI_IN P1_2 +/** Pin: CYBSP_WL_FRAM_SYNC */ +#define CYBSP_WL_FRAM_SYNC P1_3 +/** Pin: CYBSP_WL_PRIORITY */ +#define CYBSP_WL_PRIORITY P1_4 +/** Pin: CYBSP_WL_SECI_OUT */ +#define CYBSP_WL_SECI_OUT P1_5 + +/** Pin: CYBSP_WIFI_SDIO_D0 */ +#define CYBSP_WIFI_SDIO_D0 P2_0 +/** Pin: CYBSP_WIFI_SDIO_D1 */ +#define CYBSP_WIFI_SDIO_D1 P2_1 +/** Pin: CYBSP_WIFI_SDIO_D2 */ +#define CYBSP_WIFI_SDIO_D2 P2_2 +/** Pin: CYBSP_WIFI_SDIO_D3 */ +#define CYBSP_WIFI_SDIO_D3 P2_3 +/** Pin: CYBSP_WIFI_SDIO_CMD */ +#define CYBSP_WIFI_SDIO_CMD P2_4 +/** Pin: CYBSP_WIFI_SDIO_CLK */ +#define CYBSP_WIFI_SDIO_CLK P2_5 +/** Pin: CYBSP_WIFI_WL_REG_ON */ +#define CYBSP_WIFI_WL_REG_ON P2_6 +/** Pin: CYBSP_WIFI_HOST_WAKE */ +#define CYBSP_WIFI_HOST_WAKE P2_7 +/** Host-wake GPIO drive mode */ +#define CYBSP_WIFI_HOST_WAKE_GPIO_DM CYHAL_GPIO_DRIVE_ANALOG +/** Host-wake IRQ event */ +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_RISE + +/** Pin: CYBSP_BT_UART_RX */ +#define CYBSP_BT_UART_RX P3_0 +/** Pin: CYBSP_BT_UART_TX */ +#define CYBSP_BT_UART_TX P3_1 +/** Pin: CYBSP_BT_UART_RTS */ +#define CYBSP_BT_UART_RTS P3_2 +/** Pin: CYBSP_BT_UART_CTS */ +#define CYBSP_BT_UART_CTS P3_3 +/** Pin: CYBSP_BT_REG_ON */ +#define CYBSP_BT_REG_ON P3_4 +/** Pin: CYBSP_BT_HOST_WAKE */ +#define CYBSP_BT_HOST_WAKE P3_5 + +/** Pin: CYBSP_BT_DEVICE_WAKE */ +#define CYBSP_BT_DEVICE_WAKE P4_0 +/** Pin: CYBSP_BT_RST */ +#define CYBSP_BT_RST P4_1 + +/** Pin: UART RX */ +#define CYBSP_DEBUG_UART_RX P5_0 +/** Pin: UART TX */ +#define CYBSP_DEBUG_UART_TX P5_1 + +/** Pin: CYBSP_I2C_SCL */ +#define CYBSP_I2C_SCL P6_0 +/** Pin: CYBSP_I2C_SDA */ +#define CYBSP_I2C_SDA P6_1 +/** Pin: CYBSP_TDO_SWO */ +#define CYBSP_TDO_SWO P6_4 +/** Pin: CYBSP_TMS_SWDIO */ +#define CYBSP_TMS_SWDIO P6_6 +/** Pin: CYBSP_SWCLK */ +#define CYBSP_SWCLK P6_7 + +/** Pin: CYBSP_TRACECLK */ +#define CYBSP_TRACECLK P7_0 +/** Pin: CYBSP_CINTA */ +#define CYBSP_CINTA P7_1 +/** Pin: CYBSP_CINTB */ +#define CYBSP_CINTB P7_2 +/** Pin: CYBSP_CMOD */ +#define CYBSP_CMOD P7_7 + +/** Pin: CYBSP_CSD_BTN0 */ +#define CYBSP_CSD_BTN0 P8_1 +/** Pin: CYBSP_CSD_BTN1 */ +#define CYBSP_CSD_BTN1 P8_2 +/** Pin: CYBSP_CSD_SLD0 */ +#define CYBSP_CSD_SLD0 P8_3 +/** Pin: CYBSP_CSD_SLD1 */ +#define CYBSP_CSD_SLD1 P8_4 +/** Pin: CYBSP_CSD_SLD2 */ +#define CYBSP_CSD_SLD2 P8_5 +/** Pin: CYBSP_CSD_SLD3 */ +#define CYBSP_CSD_SLD3 P8_6 +/** Pin: CYBSP_CSD_SLD4 */ +#define CYBSP_CSD_SLD4 P8_7 + +/** Pin: CYBSP_TRACEDATA3 */ +#define CYBSP_TRACEDATA3 P9_0 +/** Pin: CYBSP_TRACEDATA2 */ +#define CYBSP_TRACEDATA2 P9_1 +/** Pin: CYBSP_TRACEDATA1 */ +#define CYBSP_TRACEDATA1 P9_2 +/** Pin: CYBSP_TRACEDATA0 */ +#define CYBSP_TRACEDATA0 P9_3 + +/** Pin: CYBSP_ROW6_SPI_MOSI */ +#define CYBSP_ROW6_SPI_MOSI P10_0 +/** Pin: CYBSP_COL8_SPI_MISO */ +#define CYBSP_COL8_SPI_MISO P10_1 +/** Pin: CYBSP_ROW7_SPI_CLK */ +#define CYBSP_ROW7_SPI_CLK P10_2 +/** Pin: CYBSP_COL7_SPI_CS */ +#define CYBSP_COL7_SPI_CS P10_3 +/** Pin: CYBSP_BAT_MON */ +#define CYBSP_BAT_MON P10_4 +/** Pin: CYBSP_WL_WAKE */ +#define CYBSP_WL_WAKE P10_7 + +/** Pin: CYBSP_UART_RX */ +#define CYBSP_UART_RX P11_0 +/** Pin: CYBSP_UART_TX */ +#define CYBSP_UART_TX P11_1 +/** Pin: CYBSP_QSPI_SS */ +#define CYBSP_QSPI_SS P11_2 +/** Pin: CYBSP_QSPI_D3 */ +#define CYBSP_QSPI_D3 P11_3 +/** Pin: CYBSP_QSPI_D2 */ +#define CYBSP_QSPI_D2 P11_4 +/** Pin: CYBSP_QSPI_D1 */ +#define CYBSP_QSPI_D1 P11_5 +/** Pin: CYBSP_QSPI_D0 */ +#define CYBSP_QSPI_D0 P11_6 +/** Pin: CYBSP_QSPI_SCK */ +#define CYBSP_QSPI_SCK P11_7 + +/** Pin: CYBSP_BT_GPIO4 */ +#define CYBSP_BT_GPIO4 P12_0 +/** Pin: CYBSP_BT_GPIO5 */ +#define CYBSP_BT_GPIO5 P12_1 +/** Pin: CYBSP_BT_GPIO2 */ +#define CYBSP_BT_GPIO2 P12_2 +/** Pin: CYBSP_BT_GPIO3 */ +#define CYBSP_BT_GPIO3 P12_3 +/** Pin: CYBSP_ECO_IN */ +#define CYBSP_ECO_IN P12_6 +/** Pin: CYBSP_ECO_OUT */ +#define CYBSP_ECO_OUT P12_7 + +/** Pin: CYBSP_P6_UART_RX */ +#define CYBSP_P6_UART_RX P13_0 +/** Pin: CYBSP_P6_UART_TX */ +#define CYBSP_P6_UART_TX P13_1 +/** Pin: CYBSP_USB_DEV_VBUS_DET */ +#define CYBSP_USB_DEV_VBUS_DET P13_4 +/** Pin: CYBSP_USB_HOST_EN */ +#define CYBSP_USB_HOST_EN P13_5 +/** Pin: CYBSP_USB_INT_L */ +#define CYBSP_USB_INT_L P13_7 + +/** Pin: CYBSP_USB_DP */ +#define CYBSP_USB_DP P14_0 +/** Pin: CYBSP_USB_DM */ +#define CYBSP_USB_DM P14_1 + +/** \} group_bsp_cyw943012p6evb_01_macros */ + +/** +* \addtogroup group_bsp_cyw943012p6evb_01_enums +* \{ +*/ + +/** Enum defining the different states for the LED. */ +typedef enum +{ + CYBSP_LED_STATE_ON = 0, + CYBSP_LED_STATE_OFF = 1, +} cybsp_led_state_t; + +/** Enum defining the different states for a button. */ +typedef enum +{ + CYBSP_BTN_PRESSED = 0, + CYBSP_BTN_OFF = 1, +} cybsp_btn_state_t; + +/** Enum defining the different LED pins on the board. */ +typedef enum +{ + CYBSP_LED_RGB_RED = P0_3, + CYBSP_LED_RGB_GREEN = P1_1, + CYBSP_LED_RGB_BLUE = P10_6, + + CYBSP_USER_LED1 = CYBSP_LED_RGB_RED, + CYBSP_USER_LED2 = CYBSP_LED_RGB_GREEN, + CYBSP_USER_LED3 = CYBSP_LED_RGB_BLUE, + CYBSP_USER_LED = CYBSP_USER_LED1, +} cybsp_led_t; + +/** Enum defining the different button pins on the board. */ +typedef enum +{ + CYBSP_SW6 = P0_4, + + CYBSP_USER_BTN1 = CYBSP_SW6, + CYBSP_USER_BTN = CYBSP_USER_BTN1, +} cybsp_btn_t; + +/** \} group_bsp_cyw943012p6evb_01_enums */ + +#if defined(__cplusplus) +} +#endif + +/** \} group_bsp_cyw943012p6evb_01 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct index f6812aa522..0152835028 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm0plus.scat -;* \version 2.40 +;* \version 2.50 ;* ;* Linker file for the ARMCC. ;* @@ -86,7 +86,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -#define Stack_Size MBED_BOOT_STACK_SIZE +#define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. ; Use these defines to specify the memory regions available for allocation. @@ -193,7 +193,7 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) } ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -Stack_Size + ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE { * (STACK) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld index 729633cdfe..45285e64c3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm0plus.ld -* \version 2.40 +* \version 2.50 * * Linker file for the GNU C compiler. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf index a82c796310..dc77b4ce23 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm0plus.icf -* \version 2.40 +* \version 2.50 * * Linker file for the IAR compiler. * @@ -163,8 +163,10 @@ if (!isdefinedsymbol(__STACK_SIZE)) { define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; } define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x4000; + define symbol __ICFEDIT_size_heap__ = 0x400; } else { define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; } @@ -191,7 +193,7 @@ define block RAM_BSS {readwrite section .bss}; define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; define block RO {first section .intvec, readonly}; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c index b28ca95120..010eac6188 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm0plus.c -* \version 2.40 +* \version 2.50 * * The device system-source file. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct index 3319e48c9b..a23e6e13f6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xx7_cm4_dual.scat -;* \version 2.40 +;* \version 2.50 ;* ;* Linker file for the ARMCC. ;* @@ -78,7 +78,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -#define Stack_Size MBED_BOOT_STACK_SIZE +#define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. ; Use these defines to specify the memory regions available for allocation. @@ -190,7 +190,7 @@ LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE } ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE -Stack_Size + ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE { * (STACK) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index b5e7d90d53..0cfd336d6e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.ld -* \version 2.40 +* \version 2.50 * * Linker file for the GNU C compiler. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf index 4be7d38872..1fd2e3e578 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xx7_cm4_dual.icf -* \version 2.40 +* \version 2.50 * * Linker file for the IAR compiler. * @@ -154,8 +154,9 @@ if (!isdefinedsymbol(__STACK_SIZE)) { define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; } +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x20000; + define symbol __ICFEDIT_size_heap__ = 0x400; } else { define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; } @@ -183,7 +184,7 @@ define block RAM_BSS {readwrite section .bss}; define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; define block RO {first section .intvec, readonly}; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S index ac9a099f33..75747c4fac 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S @@ -1,5 +1,5 @@ ;/**************************************************************************//** -; * @file startup_psoc6_01_cm4.s +; * @file startup_psoc6_01_cm4.S ; * @brief CMSIS Core Device Startup File for ; * ARMCM4 Device Series ; * @version V5.00 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c index c040a5c713..a5408385ee 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.40 +* \version 2.50 * * The device system-source file. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/system_psoc6.h index 99f86760b3..53bc71262c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.40 +* \version 2.50 * * \brief Device system header file. * @@ -320,6 +320,11 @@ * Reason for Change * * +* 2.50 +* Updated assembler files, C files, linker scripts. +* Dynamic allocated HEAP size for Arm Compiler 6, IAR 8. +* +* * 2.40 * Updated assembler files, C files, linker scripts. * Added Arm Compiler 6 support. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_network_buffer.c b/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_network_buffer.c new file mode 100644 index 0000000000..621fee3746 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_network_buffer.c @@ -0,0 +1,100 @@ +/******************************************************************************* +* File Name: cy_network_buffer.c +* +* Description: +* Basic set of APIs for dealing with network packet buffers. This is used by WHD +* for relaying data between the network stack and the connectivity chip. +* +******************************************************************************** +* Copyright (c) 2018-2019 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#if defined(TARGET_WHD) + +#include +#include "cy_network_buffer.h" +#include "cy_utils.h" +#include "memp.h" +#define SDIO_BLOCK_SIZE (64U) + +whd_result_t cy_host_buffer_get(whd_buffer_t *buffer, whd_buffer_dir_t direction, unsigned short size, unsigned long timeout_ms) +{ + UNUSED_PARAMETER( direction ); + struct pbuf *p = NULL; + if ( ( direction == WHD_NETWORK_TX) && ( size <= PBUF_POOL_BUFSIZE ) ) + { + p = pbuf_alloc(PBUF_RAW, size, PBUF_POOL); + } + else + { + p = pbuf_alloc(PBUF_RAW, size+SDIO_BLOCK_SIZE, PBUF_RAM); + if ( p != NULL ) + { + p->len = size; + p->tot_len -= SDIO_BLOCK_SIZE; + } + } + if (p != NULL ) + { + *buffer = p; + return WHD_SUCCESS; + } + else + { + return WHD_BUFFER_ALLOC_FAIL; + } +} + +void cy_buffer_release(whd_buffer_t buffer, whd_buffer_dir_t direction) +{ + UNUSED_PARAMETER( direction ); + (void) pbuf_free( (struct pbuf *)buffer ); +} + +uint8_t *cy_buffer_get_current_piece_data_pointer(whd_buffer_t buffer) +{ + CY_ASSERT(buffer != NULL); + struct pbuf *pbuffer= (struct pbuf*) buffer; + return (uint8_t*) pbuffer->payload; +} + +uint16_t cy_buffer_get_current_piece_size(whd_buffer_t buffer) +{ + CY_ASSERT(buffer != NULL); + struct pbuf *pbuffer = (struct pbuf*) buffer; + return (uint16_t) pbuffer->len; +} + +whd_result_t cy_buffer_set_size(whd_buffer_t buffer, unsigned short size) +{ + CY_ASSERT(buffer != NULL); + struct pbuf * pbuffer = (struct pbuf *) buffer; + + if ( size > (unsigned short) WHD_LINK_MTU + LWIP_MEM_ALIGN_SIZE(LWIP_MEM_ALIGN_SIZE(sizeof(struct pbuf))) + LWIP_MEM_ALIGN_SIZE(size) ) + { + return WHD_PMK_WRONG_LENGTH; + } + + pbuffer->tot_len = size; + pbuffer->len = size; + + return CY_RSLT_SUCCESS; +} + +whd_result_t cy_buffer_add_remove_at_front(whd_buffer_t *buffer, int32_t add_remove_amount) +{ + CY_ASSERT(buffer != NULL); + struct pbuf **pbuffer = (struct pbuf**) buffer; + + if ( (u8_t) 0 != pbuf_header( *pbuffer, ( s16_t )( -add_remove_amount ) ) ) + { + return WHD_PMK_WRONG_LENGTH; + } + + return WHD_SUCCESS; +} + +#endif /* defined(TARGET_WHD) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_network_buffer.h b/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_network_buffer.h new file mode 100644 index 0000000000..35a833223c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_network_buffer.h @@ -0,0 +1,172 @@ +/******************************************************************************* +* File Name: cy_network_buffer.h +* +* Description: +* Basic set of APIs for dealing with network packet buffers. This is used by WHD +* for relaying data between the network stack and the connectivity chip. +* +******************************************************************************** +* Copyright (c) 2018-2019 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +/** +* \addtogroup group_abstraction_buffer Buffer management abstraction +* \ingroup group_abstraction +* \{ +* TODO: Buffer abstraction high-level description +* to be set in abstraction/include/cy_network_buffer.h +* +* \defgroup group_abstraction_buffer_functions Functions +*/ + +#pragma once +#if defined(TARGET_WHD) + +#include +#include +#include "cy_result.h" +#include "whd.h" +#include "whd_network_types.h" +#include "pbuf.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/** +* \addtogroup group_abstraction_buffer_functions +* \{ +*/ + +/** Allocates a packet buffer + * + * Attempts to allocate a packet buffer of the size requested. It can do this + * by allocating a pre-existing packet from a pool, using a static buffer, + * or by dynamically allocating memory. The method of allocation does not + * concern WHD, however it must match the way the network stack expects packet + * buffers to be allocated. Usually WHD requires packet of size of WHD_LINK_MTU + * which includes the MTU. Refer to whd_types.h to find the size of WHD_LINK_MTU. + * + * @param buffer : A pointer which receives the allocated packet buffer handle + * @param direction : Indicates transmit/receive direction that the packet buffer is + * used for. This may be needed if tx/rx pools are separate. + * @param size : The number of bytes to allocate. + * @param timeout_ms: Time to wait for a packet buffer to be available + * + * @return : CY_RSLT_SUCCESS or WHD_BUFFER_ALLOC_FAIL if the buffer could not be allocated + */ +whd_result_t cy_host_buffer_get(whd_buffer_t *buffer, whd_buffer_dir_t direction, unsigned short size, unsigned long timeout_ms); + +/** Releases a packet buffer + * + * This function is used by WHD to indicate that it no longer requires + * a packet buffer. The buffer can then be released back into a pool for + * reuse, or the dynamically allocated memory can be freed, according to + * how the packet was allocated. + * Returns void since WHD cannot do anything about failures + * + * @param buffer : The handle of the packet buffer to be released + * @param direction : Indicates transmit/receive direction that the packet buffer has + * been used for. This might be needed if tx/rx pools are separate. + */ +void cy_buffer_release(whd_buffer_t buffer, whd_buffer_dir_t direction); + +/** Retrieves the current pointer of a packet buffer + * + * Since packet buffers usually need to be created with space at the + * front for additional headers, this function allows WHD to get + * the current 'front' location pointer. + * + * @param buffer : The handle of the packet buffer whose pointer is to be retrieved + * + * @return : The packet buffer's current pointer. + */ +uint8_t *cy_buffer_get_current_piece_data_pointer(whd_buffer_t buffer); + +/** Retrieves the size of a packet buffer + * + * Since packet buffers usually need to be created with space at the + * front for additional headers, the memory block used to contain a packet buffer + * will often be larger than the current size of the packet buffer data. + * This function allows WHD to retrieve the current size of a packet buffer's data. + * + * @param buffer : The handle of the packet buffer whose size is to be retrieved + * + * @return : The size of the packet buffer. + */ +uint16_t cy_buffer_get_current_piece_size(whd_buffer_t buffer); + +/** Sets the current size of a WHD packet + * + * This function sets the current length of a WHD packet buffer + * + * @param buffer : The packet to be modified + * @param size : The new size of the packet buffer + * + * @return : CY_RSLT_SUCCESS or WHD_PMK_WRONG_LENGTH if the requested size is not valid + */ +whd_result_t cy_buffer_set_size(whd_buffer_t buffer, unsigned short size); + +/** Moves the current pointer of a packet buffer + * + * Since packet buffers usually need to be created with space at the front for additional headers, + * this function allows WHD to move the current 'front' location pointer so that it has space to + * add headers to transmit packets, and so that the network stack does not see the internal WHD + * headers on received packets. + * + * @param buffer : A pointer to the handle of the current packet buffer for which the + * current pointer will be moved. On return this may contain a pointer + * to a newly allocated packet buffer which has been daisy chained to + * the front of the given one. This would be the case if the given packet + * buffer didn't have enough space at the front. + * @param add_remove_amount : This is the number of bytes to move the current pointer of the packet + * buffer - a negative value increases the space for headers at the front + * of the packet, a positive value decreases the space. + * + * @return : CY_RSLT_SUCCESS or WHD_PMK_WRONG_LENGTH if the added amount is outside + * the size of the buffer + */ +whd_result_t cy_buffer_add_remove_at_front(whd_buffer_t *buffer, int32_t add_remove_amount); + + +/** Called by WHD to pass received data to the network stack + * + * Packets received from the Wi-Fi network by WHD are forwarded to by calling function ptr which + * must be implemented in the network interface. Ethernet headers + * are present at the start of these packet buffers. + * + * This function is called asynchronously in the context of the + * WHD thread whenever new data has arrived. + * Packet buffers are allocated within WHD, and ownership is transferred + * to the network stack. The network stack or application is thus + * responsible for releasing the packet buffers. + * Most packet buffering systems have a pointer to the 'current point' within + * the packet buffer. When this function is called, the pointer points + * to the start of the Ethernet header. There is other inconsequential data + * before the Ethernet header. + * + * It is preferable that the (whd_network_process_ethernet_data)() function simply puts + * the received packet on a queue for processing by another thread. This avoids the + * WHD thread being unnecessarily tied up which would delay other packets + * being transmitted or received. + * + * @param interface : The interface on which the packet was received. + * @param buffer : Handle of the packet which has just been received. Responsibility for + * releasing this buffer is transferred from WHD at this point. + * + */ +void cy_network_process_ethernet_data(whd_interface_t interface, whd_buffer_t buffer); + +/** \} group_abstraction_buffer_functions */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* defined(TARGET_WHD) */ + +/** \} group_abstraction_buffer */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_common.c b/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_common.c new file mode 100644 index 0000000000..7f883481de --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_common.c @@ -0,0 +1,78 @@ +/***************************************************************************//** +* \file cybsp_utils.c +* +* \brief +* Provides utility functions that are used by board support packages. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cybsp_api_core.h" +#include "cyhal.h" +#include "cyhal_implementation.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +static void (*btn_interrupt_call_back) (void); + +cy_rslt_t cybsp_led_init(cybsp_led_t which) +{ + return cyhal_gpio_init((cyhal_gpio_t)which, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, CYBSP_LED_STATE_OFF); +} + +void cybsp_led_set_state(cybsp_led_t which, bool on) +{ + cyhal_gpio_write((cyhal_gpio_t)which, on); +} + +void cybsp_led_toggle(cybsp_led_t which) +{ + cyhal_gpio_toggle((cyhal_gpio_t)which); +} + +cy_rslt_t cybsp_btn_init(cybsp_btn_t which) +{ + return cyhal_gpio_init((cyhal_gpio_t)which, CYHAL_GPIO_DIR_INPUT, CYHAL_GPIO_DRIVE_PULLUP, CYBSP_BTN_OFF); +} + +bool cybsp_btn_get_state(cybsp_btn_t which) +{ + return cyhal_gpio_read((cyhal_gpio_t)which); +} + +static void gpio_call_back_wrapper(void *handler_arg, cyhal_gpio_irq_event_t event) +{ + if (btn_interrupt_call_back != NULL) + { + btn_interrupt_call_back(); + } +} + +void cybsp_btn_set_interrupt(cybsp_btn_t which, cyhal_gpio_irq_event_t type, void (*callback)(void)) +{ + btn_interrupt_call_back = callback; + cyhal_gpio_register_irq((cyhal_gpio_t)which, 7, &gpio_call_back_wrapper, NULL); + cyhal_gpio_irq_enable((cyhal_gpio_t)which, type, 1); +} + + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi.c b/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi.c new file mode 100644 index 0000000000..c04ec7bc9f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi.c @@ -0,0 +1,337 @@ +/***************************************************************************//** +* \file cybsp_utils.c +* +* \brief +* Provides utility functions that are used by board support packages. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ +#if defined(TARGET_WHD) + +#include "cybsp_api_wifi.h" +#include "cy_network_buffer.h" +#include "cmsis_os2.h" +#include "whd_bus_types.h" +#include "cyhal.h" +#include "cyhal_implementation.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define THREAD_STACK_SIZE 5120 +#define THREAD_PRIORITY osPriorityHigh +#define COUNTRY WHD_COUNTRY_AUSTRALIA +#define DEFAULT_OOB_PIN 0 +#define WLAN_INTR_PRIORITY 1 +#define WLAN_POWER_UP_DELAY_MS 250 + +#define SDIO_ENUMERATION_TRIES 500 +#define SDIO_RETRY_DELAY_MS 1 +#define SDIO_BUS_LEVEL_MAX_RETRIES 5 + +/* Determine whether to use the SDIO oob interrupt. + * When CY_SDIO_BUS_NEEDS_OOB_INTR is defined, + * use its value to determine enable status; otherwise, + * default to enable. Use CY_WIFI_HOST_WAKE_SW_FORCE + * to force the enable status. + */ +#if !defined(CY_WIFI_HOST_WAKE_SW_FORCE) + +#if !defined(CY_SDIO_BUS_NEEDS_OOB_INTR) +#define CY_SDIO_BUS_USE_OOB_INTR (1u) +#else +#define CY_SDIO_BUS_USE_OOB_INTR CY_SDIO_BUS_NEEDS_OOB_INTR +#endif /* !defined(CY_SDIO_BUS_NEEDS_OOB_INTR) */ + +#else + +#define CY_SDIO_BUS_USE_OOB_INTR CY_WIFI_HOST_WAKE_SW_FORCE + +#endif /* defined(CY_WIFI_HOST_WAKE_SW_FORCE) */ + +/* Define the host-wake configuration. + * Choose the configurator settings over the HAL. + */ +#if (CY_SDIO_BUS_USE_OOB_INTR != 0) + +/* Prefer configurator declarations over HAL */ + +#if defined(CYCFG_WIFI_HOST_WAKE_GPIO) +#define CY_WIFI_HOST_WAKE_GPIO CYCFG_WIFI_HOST_WAKE_GPIO +#else +#define CY_WIFI_HOST_WAKE_GPIO CYBSP_WIFI_HOST_WAKE +#endif + +#if defined(CYCFG_WIFI_HOST_WAKE_GPIO_DM) +#define CY_WIFI_HOST_WAKE_GPIO_DM CYCFG_WIFI_HOST_WAKE_GPIO_DM +#else +#define CY_WIFI_HOST_WAKE_GPIO_DM CYBSP_WIFI_HOST_WAKE_GPIO_DM +#endif + +#if defined(CYCFG_WIFI_HOST_WAKE_IRQ_EVENT) +#define CY_WIFI_HOST_WAKE_IRQ_EVENT CYCFG_WIFI_HOST_WAKE_IRQ_EVENT +#else +#define CY_WIFI_HOST_WAKE_IRQ_EVENT CYBSP_WIFI_HOST_WAKE_IRQ_EVENT +#endif + +#else + +/* Dummy macro declarations to appease compiler */ +#define CY_WIFI_HOST_WAKE_GPIO 0 +#define CY_WIFI_HOST_WAKE_GPIO_DM 0 +#define CY_WIFI_HOST_WAKE_IRQ_EVENT 0 + +#endif /* (CY_SDIO_BUS_USE_OOB_INTR != 0) */ + +whd_driver_t whd_drv; +bool sdio_initialized = false; +cyhal_sdio_t sdio_obj; + +static void cy_enable_oob_intr(whd_driver_t whd_driver, const whd_variant_t intr, whd_bool_t whd_enable); +static void cy_get_intr_config(whd_driver_t whd_driver, const whd_variant_t intr, whd_intr_config_t *config); + +static whd_buffer_funcs_t buffer_ops = +{ + .whd_host_buffer_get = cy_host_buffer_get, + .whd_buffer_release = cy_buffer_release, + .whd_buffer_get_current_piece_data_pointer = cy_buffer_get_current_piece_data_pointer, + .whd_buffer_get_current_piece_size = cy_buffer_get_current_piece_size, + .whd_buffer_set_size = cy_buffer_set_size, + .whd_buffer_add_remove_at_front = cy_buffer_add_remove_at_front, +}; + +static whd_netif_funcs_t netif_ops = +{ + .whd_network_process_ethernet_data = cy_network_process_ethernet_data, +}; + +static whd_sdio_funcs_t sdio_ops = +{ + .whd_enable_intr = cy_enable_oob_intr, + .whd_get_intr_config = cy_get_intr_config, +}; + +//TODO: Need to use resource implemenatation from abstraction layer. +extern whd_resource_source_t resource_ops; + +static void whd_wake_host_irq_handler(void *arg, cyhal_gpio_irq_event_t event) +{ + //TODO: Swtich out from deep sleep or LP mode. + whd_bus_sdio_oob_intr_asserted(arg); +} + +static cy_rslt_t sdio_try_send_cmd(const cyhal_sdio_t *sdio_object, cyhal_transfer_t direction, \ + cyhal_sdio_command_t command, uint32_t argument, uint32_t* response) +{ + uint8_t loop_count = 0; + cy_rslt_t result = CYBSP_RSLT_WIFI_SDIO_ENUM_TIMEOUT; + do + { + result = cyhal_sdio_send_cmd(sdio_object, direction, command, argument, response); + if(result != CY_RSLT_SUCCESS) + { + Cy_SysLib_Delay(SDIO_RETRY_DELAY_MS); + } + loop_count++; + } + while(result != CY_RSLT_SUCCESS && loop_count <= SDIO_BUS_LEVEL_MAX_RETRIES); + + return result; +} + +static cy_rslt_t cybsp_sdio_enumerate(const cyhal_sdio_t *sdio_object) +{ + cy_rslt_t result = CYBSP_RSLT_WIFI_SDIO_ENUM_TIMEOUT; + uint32_t loop_count = 0; + uint32_t rel_addr; + uint32_t response_ignored = 0; + uint32_t no_argument = 0; + + do + { + /* Send CMD0 to set it to idle state */ + sdio_try_send_cmd(sdio_object, CYHAL_WRITE, CYHAL_SDIO_CMD_GO_IDLE_STATE, no_argument, &response_ignored /*ignored*/); + + /* CMD5. */ + sdio_try_send_cmd(sdio_object, CYHAL_READ, CYHAL_SDIO_CMD_IO_SEND_OP_COND, no_argument, &response_ignored /*ignored*/); + + /* Send CMD3 to get RCA. */ + result = sdio_try_send_cmd(sdio_object, CYHAL_READ, CYHAL_SDIO_CMD_SEND_RELATIVE_ADDR, no_argument, &rel_addr); + if(result != CY_RSLT_SUCCESS) + { + Cy_SysLib_Delay(SDIO_RETRY_DELAY_MS); + } + loop_count++; + } while (result != CY_RSLT_SUCCESS && loop_count <= SDIO_ENUMERATION_TRIES); + + if(result == CY_RSLT_SUCCESS) + { + /* Send CMD7 with the returned RCA to select the card */ + result = sdio_try_send_cmd(sdio_object, CYHAL_WRITE, CYHAL_SDIO_CMD_SELECT_CARD, rel_addr, &response_ignored); + } + return result; +} + +static cy_rslt_t init_sdio_whd(void) +{ + /* WiFi into reset */ + cy_rslt_t result = cyhal_gpio_init(CYBSP_WIFI_WL_REG_ON, CYHAL_GPIO_DIR_OUTPUT, CY_GPIO_DM_PULLUP, 0); + + if(result == CY_RSLT_SUCCESS) + { + /* Init SDIO Host */ + if (!sdio_initialized) + { + result = cybsp_sdio_init(); + } + if(result == CY_RSLT_SUCCESS) + { + /* WiFi out of reset */ + cyhal_gpio_write(CYBSP_WIFI_WL_REG_ON, true); + Cy_SysLib_Delay(WLAN_POWER_UP_DELAY_MS); + } + else + { + cyhal_gpio_free(CYBSP_WIFI_WL_REG_ON); + } + } + return result; +} + +static void deinit_sdio_whd(void) +{ + cyhal_sdio_free(&sdio_obj); + cyhal_gpio_free(CYBSP_WIFI_WL_REG_ON); + sdio_initialized = false; +} + +static cy_rslt_t init_sdio_bus(void) +{ + whd_sdio_config_t whd_sdio_config; + cyhal_sdio_cfg_t config; + + cy_rslt_t result = cybsp_sdio_enumerate(&sdio_obj); + + if(result == CY_RSLT_SUCCESS) + { + whd_sdio_config.flags = 0; + whd_sdio_config.sdio_1bit_mode = WHD_FALSE; + whd_sdio_config.high_speed_sdio_clock = WHD_FALSE; + if(CY_SDIO_BUS_USE_OOB_INTR != 0) + { + whd_sdio_config.flags |= WHD_BUS_SDIO_OOB_INTR; + whd_sdio_config.oob_intr.u32val = 0; /* reserved for multi whd instances */ + } + whd_bus_sdio_attach(whd_drv, &whd_sdio_config, &sdio_obj, &sdio_ops); + + /* Increase frequency to 25 MHz for better performance */ + config.frequencyhal_hz = 25000000; + config.block_size = 0; + cyhal_sdio_configure(&sdio_obj, &config); + } + return result; +} + +static cy_rslt_t init_wlan_wakeup(void) +{ + /* assert(CY_SDIO_BUS_USE_OOB_INTR != 0) */ + cy_rslt_t result = cyhal_gpio_init(CY_WIFI_HOST_WAKE_GPIO, CYHAL_GPIO_DIR_INPUT, CY_WIFI_HOST_WAKE_GPIO_DM, 0); + if(result == CY_RSLT_SUCCESS) + { + cyhal_gpio_register_irq(CY_WIFI_HOST_WAKE_GPIO, WLAN_INTR_PRIORITY, whd_wake_host_irq_handler, whd_drv); + } + return result; +} + +static void cy_enable_oob_intr(whd_driver_t whd_driver, const whd_variant_t intr, whd_bool_t whd_enable) +{ + /* assert(CY_SDIO_BUS_USE_OOB_INTR != 0) */ + (void)whd_driver; + (void)intr; + //TODO: This needs to be enabled in the WHD after the rtos is initialized. The current location where this is called + //causes a crash in the interrupt handler since it tries to set data on the thread before it is initialized. + //Need to review where this should be called in the WHD. + // cyhal_gpio_irq_enable(CY_WIFI_HOST_WAKE_GPIO, CY_WIFI_HOST_WAKE_IRQ_EVENT, + // (whd_enable == WHD_TRUE) ? true : false); +} + +static void cy_get_intr_config(whd_driver_t whd_driver, const whd_variant_t intr, whd_intr_config_t *config) +{ + /* assert(CY_SDIO_BUS_USE_OOB_INTR != 0) */ + (void)whd_driver; + (void)intr; + config->dev_gpio_sel = DEFAULT_OOB_PIN; + config->is_falling_edge = (CY_WIFI_HOST_WAKE_IRQ_EVENT == CYHAL_GPIO_IRQ_FALL) + ? WHD_TRUE + : WHD_FALSE; +} + +cy_rslt_t cybsp_sdio_init(void) +{ + cy_rslt_t result = cyhal_sdio_init(&sdio_obj, CYBSP_WIFI_SDIO_CMD, CYBSP_WIFI_SDIO_CLK, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3); + sdio_initialized = (result == CY_RSLT_SUCCESS); + return result; +} + +cy_rslt_t cybsp_wifi_init(void) +{ + cy_rslt_t result = init_sdio_whd(); + if(result != CY_RSLT_SUCCESS) + { + return result; + } + + whd_init_config_t whd_init_config; + whd_init_config.thread_stack_size = (uint32_t) THREAD_STACK_SIZE; + whd_init_config.thread_stack_start = (uint8_t *)malloc(THREAD_STACK_SIZE); + whd_init_config.thread_priority = (uint32_t) THREAD_PRIORITY; + whd_init_config.country = COUNTRY; + + uint32_t ret = whd_init(&whd_drv, &whd_init_config, &resource_ops, &buffer_ops, &netif_ops); + if(ret == WHD_SUCCESS) + { + result = init_sdio_bus(); + if (result == CY_RSLT_SUCCESS && CY_SDIO_BUS_USE_OOB_INTR != 0) + { + result = init_wlan_wakeup(); + } + } + else + { + result = CYBSP_RSLT_WIFI_INIT_FAILED; + } + + if (result != CY_RSLT_SUCCESS) + { + deinit_sdio_whd(); + } + + return result; +} + +whd_driver_t* cybsp_get_wifi_driver(void) +{ + return &whd_drv; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* defined(TARGET_WHD) */