From 8b428764845db25756f621774741d10e933c445b Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Thu, 25 Dec 2014 16:19:29 +0400 Subject: [PATCH 001/139] add LPC2460 platform --- libraries/USBDevice/USBDevice/USBEndpoints.h | 2 +- .../USBDevice/USBDevice/USBHAL_LPC17.cpp | 2 +- .../cmsis/TARGET_NXP/TARGET_LPC2460/LPC24xx.h | 972 ++++++++++++++++++ .../TOOLCHAIN_GCC_ARM/LPC2460.ld | 209 ++++ .../TOOLCHAIN_GCC_ARM/vector_functions.s | 154 +++ .../TOOLCHAIN_GCC_ARM/vector_table.s | 45 + .../cmsis/TARGET_NXP/TARGET_LPC2460/cmsis.h | 13 + .../TARGET_NXP/TARGET_LPC2460/cmsis_nvic.c | 40 + .../TARGET_NXP/TARGET_LPC2460/cmsis_nvic.h | 51 + .../TARGET_NXP/TARGET_LPC2460/core_arm7.c | 44 + .../TARGET_NXP/TARGET_LPC2460/core_arm7.h | 276 +++++ .../TARGET_LPC2460/system_LPC24xx.c | 164 +++ .../TARGET_LPC2460/system_LPC24xx.h | 44 + .../TARGET_NXP/TARGET_LPC2460/vector_defns.h | 77 ++ .../TARGET_LPC2460/vector_realmonitor.c | 22 + .../TARGET_LPC2460/PeripheralNames.h | 110 ++ .../hal/TARGET_NXP/TARGET_LPC2460/PinNames.h | 107 ++ .../hal/TARGET_NXP/TARGET_LPC2460/PortNames.h | 38 + .../TARGET_NXP/TARGET_LPC2460/analogin_api.c | 125 +++ .../TARGET_NXP/TARGET_LPC2460/analogout_api.c | 75 ++ .../hal/TARGET_NXP/TARGET_LPC2460/can_api.c | 303 ++++++ .../hal/TARGET_NXP/TARGET_LPC2460/device.h | 59 ++ .../TARGET_NXP/TARGET_LPC2460/ethernet_api.c | 935 +++++++++++++++++ .../hal/TARGET_NXP/TARGET_LPC2460/gpio_api.c | 54 + .../TARGET_NXP/TARGET_LPC2460/gpio_irq_api.c | 154 +++ .../TARGET_NXP/TARGET_LPC2460/gpio_object.h | 55 + .../hal/TARGET_NXP/TARGET_LPC2460/i2c_api.c | 393 +++++++ .../hal/TARGET_NXP/TARGET_LPC2460/objects.h | 78 ++ .../hal/TARGET_NXP/TARGET_LPC2460/pinmap.c | 46 + .../hal/TARGET_NXP/TARGET_LPC2460/port_api.c | 71 ++ .../TARGET_NXP/TARGET_LPC2460/pwmout_api.c | 171 +++ .../hal/TARGET_NXP/TARGET_LPC2460/rtc_api.c | 117 +++ .../TARGET_NXP/TARGET_LPC2460/serial_api.c | 338 ++++++ .../hal/TARGET_NXP/TARGET_LPC2460/spi_api.c | 219 ++++ .../hal/TARGET_NXP/TARGET_LPC2460/us_ticker.c | 64 ++ workspace_tools/build_release.py | 2 + workspace_tools/export/gcc_arm_lpc2460.tmpl | 72 ++ workspace_tools/export/gccarm.py | 1 + workspace_tools/export_test.py | 17 +- workspace_tools/settings.py | 2 +- workspace_tools/targets.py | 8 + 41 files changed, 5719 insertions(+), 10 deletions(-) create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/LPC24xx.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/LPC2460.ld create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_functions.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_table.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/cmsis.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/cmsis_nvic.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/cmsis_nvic.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/core_arm7.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/core_arm7.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/system_LPC24xx.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/system_LPC24xx.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/vector_defns.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/vector_realmonitor.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PeripheralNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PinNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PortNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/analogin_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/analogout_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/can_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/device.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/ethernet_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_irq_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_object.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/i2c_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/objects.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/pinmap.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/port_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/pwmout_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/rtc_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/serial_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/spi_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/us_ticker.c create mode 100644 workspace_tools/export/gcc_arm_lpc2460.tmpl diff --git a/libraries/USBDevice/USBDevice/USBEndpoints.h b/libraries/USBDevice/USBDevice/USBEndpoints.h index fd4b914803..e15d2ed5ed 100644 --- a/libraries/USBDevice/USBDevice/USBEndpoints.h +++ b/libraries/USBDevice/USBDevice/USBEndpoints.h @@ -37,7 +37,7 @@ typedef enum { } EP_STATUS; /* Include configuration for specific target */ -#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) +#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC2460) #include "USBEndpoints_LPC17_LPC23.h" #elif defined(TARGET_LPC11UXX) || defined(TARGET_LPC1347) || defined (TARGET_LPC11U6X) || defined (TARGET_LPC1549) #include "USBEndpoints_LPC11U.h" diff --git a/libraries/USBDevice/USBDevice/USBHAL_LPC17.cpp b/libraries/USBDevice/USBDevice/USBHAL_LPC17.cpp index 8bffe10ace..9734b1f356 100644 --- a/libraries/USBDevice/USBDevice/USBHAL_LPC17.cpp +++ b/libraries/USBDevice/USBDevice/USBHAL_LPC17.cpp @@ -16,7 +16,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) +#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC2560) #include "USBHAL.h" diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/LPC24xx.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/LPC24xx.h new file mode 100644 index 0000000000..77b247a179 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/LPC24xx.h @@ -0,0 +1,972 @@ +/* mbed Microcontroller Library - LPC24xx CMSIS-like structs + * Copyright (C) 2014 Mera NN. All rights reserved. + * + * An LPC24xx header file, based on LPC23xx.h + */ + +#ifndef __LPC24xx_H +#define __LPC24xx_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ +/****** LPC23xx Specific Interrupt Numbers *******************************************************/ + WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ + + TIMER0_IRQn = 4, /*!< Timer0 Interrupt */ + TIMER1_IRQn = 5, /*!< Timer1 Interrupt */ + UART0_IRQn = 6, /*!< UART0 Interrupt */ + UART1_IRQn = 7, /*!< UART1 Interrupt */ + PWM0_IRQn = 8, /*!< PWM0 Interrupt */ + PWM1_IRQn = 8, /*!< PWM1 Interrupt */ + I2C0_IRQn = 9, /*!< I2C0 Interrupt */ + SPI_IRQn = 10, /*!< SPI Interrupt */ + SSP0_IRQn = 10, /*!< SSP0 Interrupt */ + SSP1_IRQn = 11, /*!< SSP1 Interrupt */ + PLL0_IRQn = 12, /*!< PLL0 Lock (Main PLL) Interrupt */ + RTC_IRQn = 13, /*!< Real Time Clock Interrupt */ + EINT0_IRQn = 14, /*!< External Interrupt 0 Interrupt */ + EINT1_IRQn = 15, /*!< External Interrupt 1 Interrupt */ + EINT2_IRQn = 16, /*!< External Interrupt 2 Interrupt */ + EINT3_IRQn = 17, /*!< External Interrupt 3 Interrupt */ + ADC_IRQn = 18, /*!< A/D Converter Interrupt */ + I2C1_IRQn = 19, /*!< I2C1 Interrupt */ + BOD_IRQn = 20, /*!< Brown-Out Detect Interrupt */ + ENET_IRQn = 21, /*!< Ethernet Interrupt */ + USB_IRQn = 22, /*!< USB Interrupt */ + CAN_IRQn = 23, /*!< CAN Interrupt */ + SDMMC_IRQn = 24, /*!< SD/MMC Interrupt */ + DMA_IRQn = 25, /*!< General Purpose DMA Interrupt */ + TIMER2_IRQn = 26, /*!< Timer2 Interrupt */ + TIMER3_IRQn = 27, /*!< Timer3 Interrupt */ + UART2_IRQn = 28, /*!< UART2 Interrupt */ + UART3_IRQn = 29, /*!< UART3 Interrupt */ + I2C2_IRQn = 30, /*!< I2C2 Interrupt */ + I2S_IRQn = 31, /*!< I2S Interrupt */ +} IRQn_Type; + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the ARM7 Processor and Core Peripherals */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + + +#include +#include "system_LPC24xx.h" /* System Header */ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/*------------- Vector Interupt Controler (VIC) ------------------------------*/ +typedef struct +{ + __I uint32_t IRQStatus; + __I uint32_t FIQStatus; + __I uint32_t RawIntr; + __IO uint32_t IntSelect; + __IO uint32_t IntEnable; + __O uint32_t IntEnClr; + __IO uint32_t SoftInt; + __O uint32_t SoftIntClr; + __IO uint32_t Protection; + __IO uint32_t SWPriorityMask; + __IO uint32_t RESERVED0[54]; + __IO uint32_t VectAddr[32]; + __IO uint32_t RESERVED1[32]; + __IO uint32_t VectPriority[32]; + __IO uint32_t RESERVED2[800]; + __IO uint32_t Address; +} LPC_VIC_TypeDef; + +/*------------- System Control (SC) ------------------------------------------*/ +typedef struct +{ + __IO uint32_t MAMCR; + __IO uint32_t MAMTIM; + uint32_t RESERVED0[14]; + __IO uint32_t MEMMAP; + uint32_t RESERVED1[15]; + __IO uint32_t PLL0CON; /* Clocking and Power Control */ + __IO uint32_t PLL0CFG; + __I uint32_t PLL0STAT; + __O uint32_t PLL0FEED; + uint32_t RESERVED2[12]; + __IO uint32_t PCON; + __IO uint32_t PCONP; + uint32_t RESERVED3[15]; + __IO uint32_t CCLKCFG; + __IO uint32_t USBCLKCFG; + __IO uint32_t CLKSRCSEL; + uint32_t RESERVED4[12]; + __IO uint32_t EXTINT; /* External Interrupts */ + __IO uint32_t INTWAKE; + __IO uint32_t EXTMODE; + __IO uint32_t EXTPOLAR; + uint32_t RESERVED6[12]; + __IO uint32_t RSID; /* Reset */ + __IO uint32_t CSPR; + __IO uint32_t AHBCFG1; + __IO uint32_t AHBCFG2; + uint32_t RESERVED7[4]; + __IO uint32_t SCS; /* Syscon Miscellaneous Registers */ + __IO uint32_t IRCTRIM; /* Clock Dividers */ + __IO uint32_t PCLKSEL0; + __IO uint32_t PCLKSEL1; + uint32_t RESERVED8[4]; + __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */ + uint32_t RESERVED9; +// __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */ + } LPC_SC_TypeDef; + +/*------------- Pin Connect Block (PINCON) -----------------------------------*/ +typedef struct +{ + __IO uint32_t PINSEL0; + __IO uint32_t PINSEL1; + __IO uint32_t PINSEL2; + __IO uint32_t PINSEL3; + __IO uint32_t PINSEL4; + __IO uint32_t PINSEL5; + __IO uint32_t PINSEL6; + __IO uint32_t PINSEL7; + __IO uint32_t PINSEL8; + __IO uint32_t PINSEL9; + __IO uint32_t PINSEL10; + uint32_t RESERVED0[5]; + __IO uint32_t PINMODE0; + __IO uint32_t PINMODE1; + __IO uint32_t PINMODE2; + __IO uint32_t PINMODE3; + __IO uint32_t PINMODE4; + __IO uint32_t PINMODE5; + __IO uint32_t PINMODE6; + __IO uint32_t PINMODE7; + __IO uint32_t PINMODE8; + __IO uint32_t PINMODE9; + __IO uint32_t PINMODE_OD0; + __IO uint32_t PINMODE_OD1; + __IO uint32_t PINMODE_OD2; + __IO uint32_t PINMODE_OD3; + __IO uint32_t PINMODE_OD4; +} LPC_PINCON_TypeDef; + +#define PCTIM0 1 +#define PCTIM1 2 +#define PCUART0 3 +#define PCUART1 4 +#define PCPWM1 6 +#define PCI2C0 7 +#define PCSPI 8 +#define PCRTC 9 +#define PCSSP1 10 +#define PCEMC 11 +#define PCAD 12 +#define PCAN1 13 +#define PCAN2 14 +#define PCI2C1 19 +#define PCSSP0 21 +#define PCTIM2 22 +#define PCTIM3 23 +#define PCUART2 24 +#define PCUART3 25 +#define PCI2C2 26 +#define PCI2S 27 +#define PCSDC 28 +#define PCGPDMA 29 +#define PCENET 30 +#define PCUSB 31 + +/*------------- General Purpose Input/Output (GPIO) --------------------------*/ +typedef struct +{ + __IO uint32_t FIODIR; + uint32_t RESERVED0[3]; + __IO uint32_t FIOMASK; + __IO uint32_t FIOPIN; + __IO uint32_t FIOSET; + __O uint32_t FIOCLR; +} LPC_GPIO_TypeDef; + +typedef struct +{ + __I uint32_t IntStatus; + __I uint32_t IO0IntStatR; + __I uint32_t IO0IntStatF; + __O uint32_t IO0IntClr; + __IO uint32_t IO0IntEnR; + __IO uint32_t IO0IntEnF; + uint32_t RESERVED0[3]; + __I uint32_t IO2IntStatR; + __I uint32_t IO2IntStatF; + __O uint32_t IO2IntClr; + __IO uint32_t IO2IntEnR; + __IO uint32_t IO2IntEnF; +} LPC_GPIOINT_TypeDef; + +/*------------- Timer (TIM) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t IR; + __IO uint32_t TCR; + __IO uint32_t TC; + __IO uint32_t PR; + __IO uint32_t PC; + __IO uint32_t MCR; + __IO uint32_t MR0; + __IO uint32_t MR1; + __IO uint32_t MR2; + __IO uint32_t MR3; + __IO uint32_t CCR; + __I uint32_t CR0; + __I uint32_t CR1; + uint32_t RESERVED0[2]; + __IO uint32_t EMR; + uint32_t RESERVED1[12]; + __IO uint32_t CTCR; +} LPC_TIM_TypeDef; + +/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ +typedef struct +{ + __IO uint32_t IR; + __IO uint32_t TCR; + __IO uint32_t TC; + __IO uint32_t PR; + __IO uint32_t PC; + __IO uint32_t MCR; + __IO uint32_t MR0; + __IO uint32_t MR1; + __IO uint32_t MR2; + __IO uint32_t MR3; + __IO uint32_t CCR; + __I uint32_t CR0; + __I uint32_t CR1; + __I uint32_t CR2; + __I uint32_t CR3; + uint32_t RESERVED0; + __IO uint32_t MR4; + __IO uint32_t MR5; + __IO uint32_t MR6; + __IO uint32_t PCR; + __IO uint32_t LER; + uint32_t RESERVED1[7]; + __IO uint32_t CTCR; +} LPC_PWM_TypeDef; + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + __IO uint8_t LCR; + uint8_t RESERVED1[7]; + __IO uint8_t LSR; + uint8_t RESERVED2[7]; + __IO uint8_t SCR; + uint8_t RESERVED3[3]; + __IO uint32_t ACR; + __IO uint8_t ICR; + uint8_t RESERVED4[3]; + __IO uint8_t FDR; + uint8_t RESERVED5[7]; + __IO uint8_t TER; + uint8_t RESERVED6[27]; + __IO uint8_t RS485CTRL; + uint8_t RESERVED7[3]; + __IO uint8_t ADRMATCH; +} LPC_UART_TypeDef; + +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + __IO uint8_t LCR; + uint8_t RESERVED1[3]; + __IO uint8_t MCR; + uint8_t RESERVED2[3]; + __IO uint8_t LSR; + uint8_t RESERVED3[3]; + __IO uint8_t MSR; + uint8_t RESERVED4[3]; + __IO uint8_t SCR; + uint8_t RESERVED5[3]; + __IO uint32_t ACR; + uint32_t RESERVED6; + __IO uint32_t FDR; + uint32_t RESERVED7; + __IO uint8_t TER; + uint8_t RESERVED8[27]; + __IO uint8_t RS485CTRL; + uint8_t RESERVED9[3]; + __IO uint8_t ADRMATCH; + uint8_t RESERVED10[3]; + __IO uint8_t RS485DLY; +} LPC_UART1_TypeDef; + +/*------------- Serial Peripheral Interface (SPI) ----------------------------*/ +typedef struct +{ + __IO uint32_t SPCR; + __I uint32_t SPSR; + __IO uint32_t SPDR; + __IO uint32_t SPCCR; + uint32_t RESERVED0[3]; + __IO uint32_t SPINT; +} LPC_SPI_TypeDef; + +/*------------- Synchronous Serial Communication (SSP) -----------------------*/ +typedef struct +{ + __IO uint32_t CR0; + __IO uint32_t CR1; + __IO uint32_t DR; + __I uint32_t SR; + __IO uint32_t CPSR; + __IO uint32_t IMSC; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t ICR; + __IO uint32_t DMACR; +} LPC_SSP_TypeDef; + +/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ +typedef struct +{ + __IO uint32_t I2CONSET; + __I uint32_t I2STAT; + __IO uint32_t I2DAT; + __IO uint32_t I2ADR0; + __IO uint32_t I2SCLH; + __IO uint32_t I2SCLL; + __O uint32_t I2CONCLR; + __IO uint32_t MMCTRL; + __IO uint32_t I2ADR1; + __IO uint32_t I2ADR2; + __IO uint32_t I2ADR3; + __I uint32_t I2DATA_BUFFER; + __IO uint32_t I2MASK0; + __IO uint32_t I2MASK1; + __IO uint32_t I2MASK2; + __IO uint32_t I2MASK3; +} LPC_I2C_TypeDef; + +/*------------- Inter IC Sound (I2S) -----------------------------------------*/ +typedef struct +{ + __IO uint32_t I2SDAO; + __I uint32_t I2SDAI; + __O uint32_t I2STXFIFO; + __I uint32_t I2SRXFIFO; + __I uint32_t I2SSTATE; + __IO uint32_t I2SDMA1; + __IO uint32_t I2SDMA2; + __IO uint32_t I2SIRQ; + __IO uint32_t I2STXRATE; + __IO uint32_t I2SRXRATE; + __IO uint32_t I2STXBITRATE; + __IO uint32_t I2SRXBITRATE; + __IO uint32_t I2STXMODE; + __IO uint32_t I2SRXMODE; +} LPC_I2S_TypeDef; + +/*------------- Real-Time Clock (RTC) ----------------------------------------*/ +typedef struct +{ + __IO uint8_t ILR; + uint8_t RESERVED0[3]; + __IO uint8_t CTC; + uint8_t RESERVED1[3]; + __IO uint8_t CCR; + uint8_t RESERVED2[3]; + __IO uint8_t CIIR; + uint8_t RESERVED3[3]; + __IO uint8_t AMR; + uint8_t RESERVED4[3]; + __I uint32_t CTIME0; + __I uint32_t CTIME1; + __I uint32_t CTIME2; + __IO uint8_t SEC; + uint8_t RESERVED5[3]; + __IO uint8_t MIN; + uint8_t RESERVED6[3]; + __IO uint8_t HOUR; + uint8_t RESERVED7[3]; + __IO uint8_t DOM; + uint8_t RESERVED8[3]; + __IO uint8_t DOW; + uint8_t RESERVED9[3]; + __IO uint16_t DOY; + uint16_t RESERVED10; + __IO uint8_t MONTH; + uint8_t RESERVED11[3]; + __IO uint16_t YEAR; + uint16_t RESERVED12; + __IO uint32_t CALIBRATION; + __IO uint32_t GPREG0; + __IO uint32_t GPREG1; + __IO uint32_t GPREG2; + __IO uint32_t GPREG3; + __IO uint32_t GPREG4; + __IO uint8_t WAKEUPDIS; + uint8_t RESERVED13[3]; + __IO uint8_t PWRCTRL; + uint8_t RESERVED14[3]; + __IO uint8_t ALSEC; + uint8_t RESERVED15[3]; + __IO uint8_t ALMIN; + uint8_t RESERVED16[3]; + __IO uint8_t ALHOUR; + uint8_t RESERVED17[3]; + __IO uint8_t ALDOM; + uint8_t RESERVED18[3]; + __IO uint8_t ALDOW; + uint8_t RESERVED19[3]; + __IO uint16_t ALDOY; + uint16_t RESERVED20; + __IO uint8_t ALMON; + uint8_t RESERVED21[3]; + __IO uint16_t ALYEAR; + uint16_t RESERVED22; +} LPC_RTC_TypeDef; + +/*------------- Watchdog Timer (WDT) -----------------------------------------*/ +typedef struct +{ + __IO uint8_t WDMOD; + uint8_t RESERVED0[3]; + __IO uint32_t WDTC; + __O uint8_t WDFEED; + uint8_t RESERVED1[3]; + __I uint32_t WDTV; + __IO uint32_t WDCLKSEL; +} LPC_WDT_TypeDef; + +/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ +typedef struct +{ + __IO uint32_t ADCR; + __IO uint32_t ADGDR; + uint32_t RESERVED0; + __IO uint32_t ADINTEN; + __I uint32_t ADDR0; + __I uint32_t ADDR1; + __I uint32_t ADDR2; + __I uint32_t ADDR3; + __I uint32_t ADDR4; + __I uint32_t ADDR5; + __I uint32_t ADDR6; + __I uint32_t ADDR7; + __I uint32_t ADSTAT; + __IO uint32_t ADTRM; +} LPC_ADC_TypeDef; + +/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ +typedef struct +{ + __IO uint32_t DACR; + __IO uint32_t DACCTRL; + __IO uint16_t DACCNTVAL; +} LPC_DAC_TypeDef; + +/*------------- Multimedia Card Interface (MCI) ------------------------------*/ +typedef struct +{ + __IO uint32_t MCIPower; /* Power control */ + __IO uint32_t MCIClock; /* Clock control */ + __IO uint32_t MCIArgument; + __IO uint32_t MMCCommand; + __I uint32_t MCIRespCmd; + __I uint32_t MCIResponse0; + __I uint32_t MCIResponse1; + __I uint32_t MCIResponse2; + __I uint32_t MCIResponse3; + __IO uint32_t MCIDataTimer; + __IO uint32_t MCIDataLength; + __IO uint32_t MCIDataCtrl; + __I uint32_t MCIDataCnt; + __I uint32_t MCIStatus; + __O uint32_t MCIClear; + __IO uint32_t MCIMask0; + uint32_t RESERVED1[2]; + __I uint32_t MCIFifoCnt; + uint32_t RESERVED2[13]; + __IO uint32_t MCIFIFO[16]; +} LPC_MCI_TypeDef; + +/*------------- Controller Area Network (CAN) --------------------------------*/ +typedef struct +{ + __IO uint32_t mask[512]; /* ID Masks */ +} LPC_CANAF_RAM_TypeDef; + +typedef struct /* Acceptance Filter Registers */ +{ + __IO uint32_t AFMR; + __IO uint32_t SFF_sa; + __IO uint32_t SFF_GRP_sa; + __IO uint32_t EFF_sa; + __IO uint32_t EFF_GRP_sa; + __IO uint32_t ENDofTable; + __I uint32_t LUTerrAd; + __I uint32_t LUTerr; + __IO uint32_t FCANIE; + __IO uint32_t FCANIC0; + __IO uint32_t FCANIC1; +} LPC_CANAF_TypeDef; + +typedef struct /* Central Registers */ +{ + __I uint32_t CANTxSR; + __I uint32_t CANRxSR; + __I uint32_t CANMSR; +} LPC_CANCR_TypeDef; + +typedef struct /* Controller Registers */ +{ + __IO uint32_t MOD; + __O uint32_t CMR; + __IO uint32_t GSR; + __I uint32_t ICR; + __IO uint32_t IER; + __IO uint32_t BTR; + __IO uint32_t EWL; + __I uint32_t SR; + __IO uint32_t RFS; + __IO uint32_t RID; + __IO uint32_t RDA; + __IO uint32_t RDB; + __IO uint32_t TFI1; + __IO uint32_t TID1; + __IO uint32_t TDA1; + __IO uint32_t TDB1; + __IO uint32_t TFI2; + __IO uint32_t TID2; + __IO uint32_t TDA2; + __IO uint32_t TDB2; + __IO uint32_t TFI3; + __IO uint32_t TID3; + __IO uint32_t TDA3; + __IO uint32_t TDB3; +} LPC_CAN_TypeDef; + +/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ +typedef struct /* Common Registers */ +{ + __I uint32_t DMACIntStat; + __I uint32_t DMACIntTCStat; + __O uint32_t DMACIntTCClear; + __I uint32_t DMACIntErrStat; + __O uint32_t DMACIntErrClr; + __I uint32_t DMACRawIntTCStat; + __I uint32_t DMACRawIntErrStat; + __I uint32_t DMACEnbldChns; + __IO uint32_t DMACSoftBReq; + __IO uint32_t DMACSoftSReq; + __IO uint32_t DMACSoftLBReq; + __IO uint32_t DMACSoftLSReq; + __IO uint32_t DMACConfig; + __IO uint32_t DMACSync; +} LPC_GPDMA_TypeDef; + +typedef struct /* Channel Registers */ +{ + __IO uint32_t DMACCSrcAddr; + __IO uint32_t DMACCDestAddr; + __IO uint32_t DMACCLLI; + __IO uint32_t DMACCControl; + __IO uint32_t DMACCConfig; +} LPC_GPDMACH_TypeDef; + +/*------------- Universal Serial Bus (USB) -----------------------------------*/ +typedef struct +{ + __I uint32_t HcRevision; /* USB Host Registers */ + __IO uint32_t HcControl; + __IO uint32_t HcCommandStatus; + __IO uint32_t HcInterruptStatus; + __IO uint32_t HcInterruptEnable; + __IO uint32_t HcInterruptDisable; + __IO uint32_t HcHCCA; + __I uint32_t HcPeriodCurrentED; + __IO uint32_t HcControlHeadED; + __IO uint32_t HcControlCurrentED; + __IO uint32_t HcBulkHeadED; + __IO uint32_t HcBulkCurrentED; + __I uint32_t HcDoneHead; + __IO uint32_t HcFmInterval; + __I uint32_t HcFmRemaining; + __I uint32_t HcFmNumber; + __IO uint32_t HcPeriodicStart; + __IO uint32_t HcLSTreshold; + __IO uint32_t HcRhDescriptorA; + __IO uint32_t HcRhDescriptorB; + __IO uint32_t HcRhStatus; + __IO uint32_t HcRhPortStatus1; + __IO uint32_t HcRhPortStatus2; + uint32_t RESERVED0[40]; + __I uint32_t Module_ID; + + __I uint32_t OTGIntSt; /* USB On-The-Go Registers */ + __IO uint32_t OTGIntEn; + __O uint32_t OTGIntSet; + __O uint32_t OTGIntClr; + __IO uint32_t OTGStCtrl; + __IO uint32_t OTGTmr; + uint32_t RESERVED1[58]; + + __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */ + __IO uint32_t USBDevIntEn; + __O uint32_t USBDevIntClr; + __O uint32_t USBDevIntSet; + + __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */ + __I uint32_t USBCmdData; + + __I uint32_t USBRxData; /* USB Device Transfer Registers */ + __O uint32_t USBTxData; + __I uint32_t USBRxPLen; + __O uint32_t USBTxPLen; + __IO uint32_t USBCtrl; + __O uint32_t USBDevIntPri; + + __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */ + __IO uint32_t USBEpIntEn; + __O uint32_t USBEpIntClr; + __O uint32_t USBEpIntSet; + __O uint32_t USBEpIntPri; + + __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/ + __O uint32_t USBEpInd; + __IO uint32_t USBMaxPSize; + + __I uint32_t USBDMARSt; /* USB Device DMA Registers */ + __O uint32_t USBDMARClr; + __O uint32_t USBDMARSet; + uint32_t RESERVED2[9]; + __IO uint32_t USBUDCAH; + __I uint32_t USBEpDMASt; + __O uint32_t USBEpDMAEn; + __O uint32_t USBEpDMADis; + __I uint32_t USBDMAIntSt; + __IO uint32_t USBDMAIntEn; + uint32_t RESERVED3[2]; + __I uint32_t USBEoTIntSt; + __O uint32_t USBEoTIntClr; + __O uint32_t USBEoTIntSet; + __I uint32_t USBNDDRIntSt; + __O uint32_t USBNDDRIntClr; + __O uint32_t USBNDDRIntSet; + __I uint32_t USBSysErrIntSt; + __O uint32_t USBSysErrIntClr; + __O uint32_t USBSysErrIntSet; + uint32_t RESERVED4[15]; + + __I uint32_t I2C_RX; /* USB OTG I2C Registers */ + __O uint32_t I2C_WO; + __I uint32_t I2C_STS; + __IO uint32_t I2C_CTL; + __IO uint32_t I2C_CLKHI; + __O uint32_t I2C_CLKLO; + uint32_t RESERVED5[823]; + + union { + __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ + __IO uint32_t OTGClkCtrl; + }; + union { + __I uint32_t USBClkSt; + __I uint32_t OTGClkSt; + }; +} LPC_USB_TypeDef; + +/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ +typedef struct +{ + __IO uint32_t MAC1; /* MAC Registers */ + __IO uint32_t MAC2; + __IO uint32_t IPGT; + __IO uint32_t IPGR; + __IO uint32_t CLRT; + __IO uint32_t MAXF; + __IO uint32_t SUPP; + __IO uint32_t TEST; + __IO uint32_t MCFG; + __IO uint32_t MCMD; + __IO uint32_t MADR; + __O uint32_t MWTD; + __I uint32_t MRDD; + __I uint32_t MIND; + uint32_t RESERVED0[2]; + __IO uint32_t SA0; + __IO uint32_t SA1; + __IO uint32_t SA2; + uint32_t RESERVED1[45]; + __IO uint32_t Command; /* Control Registers */ + __I uint32_t Status; + __IO uint32_t RxDescriptor; + __IO uint32_t RxStatus; + __IO uint32_t RxDescriptorNumber; + __I uint32_t RxProduceIndex; + __IO uint32_t RxConsumeIndex; + __IO uint32_t TxDescriptor; + __IO uint32_t TxStatus; + __IO uint32_t TxDescriptorNumber; + __IO uint32_t TxProduceIndex; + __I uint32_t TxConsumeIndex; + uint32_t RESERVED2[10]; + __I uint32_t TSV0; + __I uint32_t TSV1; + __I uint32_t RSV; + uint32_t RESERVED3[3]; + __IO uint32_t FlowControlCounter; + __I uint32_t FlowControlStatus; + uint32_t RESERVED4[34]; + __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ + __IO uint32_t RxFilterWoLStatus; + __IO uint32_t RxFilterWoLClear; + uint32_t RESERVED5; + __IO uint32_t HashFilterL; + __IO uint32_t HashFilterH; + uint32_t RESERVED6[882]; + __I uint32_t IntStatus; /* Module Control Registers */ + __IO uint32_t IntEnable; + __O uint32_t IntClear; + __O uint32_t IntSet; + uint32_t RESERVED7; + __IO uint32_t PowerDown; + uint32_t RESERVED8; + __IO uint32_t Module_ID; +} LPC_EMAC_TypeDef; + +/*-------------------- External Memory Controller (EMC) ----------------------*/ +typedef struct +{ + __IO uint32_t EMCControl; + __I uint32_t EMCStatus; + __IO uint32_t EMCConfig; + uint32_t RESERVED1[5]; + __IO uint32_t EMCDynamicControl; + __IO uint32_t EMCDynamicRefresh; + __IO uint32_t EMCDynamicReadConfig; + uint32_t RESERVED2; + __IO uint32_t EMCDynamicRP; + __IO uint32_t EMCDynamicRAS; + __IO uint32_t EMCDynamicSREX; + __IO uint32_t EMCDynamicAPR; + __IO uint32_t EMCDynamicDAL; + __IO uint32_t EMCDynamicWR; + __IO uint32_t EMCDynamicRC; + __IO uint32_t EMCDynamicRFC; + __IO uint32_t EMCDynamicXSR; + __IO uint32_t EMCDynamicRRD; + __IO uint32_t EMCDynamicMRD; + uint32_t RESERVED3[9]; + __IO uint32_t EMCStaticExtendedWait; + uint32_t RESERVED4[31]; + __IO uint32_t EMCDynamicConfig0; + __IO uint32_t EMCDynamicRasCas0; + uint32_t RESERVED5[6]; + __IO uint32_t EMCDynamicConfig1; + __IO uint32_t EMCDynamicRasCas1; + uint32_t RESERVED6[6]; + __IO uint32_t EMCDynamicConfic2; + __IO uint32_t EMCDynamicRasCas2; + uint32_t RESERVED7[6]; + __IO uint32_t EMCDynamicConfig3; + __IO uint32_t EMCDynamicRasCas3; + uint32_t RESERVED8[38]; + __IO uint32_t EMCStaticConfig0; + __IO uint32_t EMCStaticWaitWen0; + __IO uint32_t EMCStaticWaitOen0; + __IO uint32_t EMCStaticWaitRd0; + __IO uint32_t EMCStaticWaitPage0; + __IO uint32_t EMCStaticWaitWr0; + __IO uint32_t EMCStaticWaitTurn0; + uint32_t RESERVED9; + __IO uint32_t EMCStaticConfig1; + __IO uint32_t EMCStaticWaitWen1; + __IO uint32_t EMCStaticWaitOen1; + __IO uint32_t EMCStaticWaitRd1; + __IO uint32_t EMCStaticWaitPage1; + __IO uint32_t EMCStaticWaitWr1; + __IO uint32_t EMCStaticWaitTurn1; + uint32_t RESERVED10; + __IO uint32_t EMCStaticConfig2; + __IO uint32_t EMCStaticWaitWen2; + __IO uint32_t EMCStaticWaitOen2; + __IO uint32_t EMCStaticWaitRd2; + __IO uint32_t EMCStaticWaitPage2; + __IO uint32_t EMCStaticWaitWr2; + __IO uint32_t EMCStaticWaitTurn2; + uint32_t RESERVED11; + __IO uint32_t EMCStaticConfig3; + __IO uint32_t EMCStaticWaitWen3; + __IO uint32_t EMCStaticWaitOen3; + __IO uint32_t EMCStaticWaitRd3; + __IO uint32_t EMCStaticWaitPage3; + __IO uint32_t EMCStaticWaitWr3; + __IO uint32_t EMCStaticWaitTurn3; +} LPC_EMC_TypeDef; +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Base addresses */ + +/* AHB Peripheral # 0 */ + +/* +#define FLASH_BASE (0x00000000UL) +#define RAM_BASE (0x10000000UL) +#define GPIO_BASE (0x2009C000UL) +#define APB0_BASE (0x40000000UL) +#define APB1_BASE (0x40080000UL) +#define AHB_BASE (0x50000000UL) +#define CM3_BASE (0xE0000000UL) +*/ + +// TODO - #define VIC_BASE_ADDR 0xFFFFF000 + +#define LPC_WDT_BASE (0xE0000000) +#define LPC_TIM0_BASE (0xE0004000) +#define LPC_TIM1_BASE (0xE0008000) +#define LPC_UART0_BASE (0xE000C000) +#define LPC_UART1_BASE (0xE0010000) +#define LPC_PWM1_BASE (0xE0018000) +#define LPC_I2C0_BASE (0xE001C000) +#define LPC_SPI_BASE (0xE0020000) +#define LPC_RTC_BASE (0xE0024000) +#define LPC_GPIOINT_BASE (0xE0028080) +#define LPC_PINCON_BASE (0xE002C000) +#define LPC_SSP1_BASE (0xE0030000) +#define LPC_ADC_BASE (0xE0034000) +#define LPC_CANAF_RAM_BASE (0xE0038000) +#define LPC_CANAF_BASE (0xE003C000) +#define LPC_CANCR_BASE (0xE0040000) +#define LPC_CAN1_BASE (0xE0044000) +#define LPC_CAN2_BASE (0xE0048000) +#define LPC_I2C1_BASE (0xE005C000) +#define LPC_SSP0_BASE (0xE0068000) +#define LPC_DAC_BASE (0xE006C000) +#define LPC_TIM2_BASE (0xE0070000) +#define LPC_TIM3_BASE (0xE0074000) +#define LPC_UART2_BASE (0xE0078000) +#define LPC_UART3_BASE (0xE007C000) +#define LPC_I2C2_BASE (0xE0080000) +#define LPC_I2S_BASE (0xE0088000) +#define LPC_MCI_BASE (0xE008C000) +#define LPC_SC_BASE (0xE01FC000) +#define LPC_EMAC_BASE (0xFFE00000) +#define LPC_GPDMA_BASE (0xFFE04000) +#define LPC_GPDMACH0_BASE (0xFFE04100) +#define LPC_GPDMACH1_BASE (0xFFE04120) +#define LPC_EMC_BASE (0xFFE08000) +#define LPC_USB_BASE (0xFFE0C000) +#define LPC_VIC_BASE (0xFFFFF000) + +/* GPIOs */ +#define LPC_GPIO0_BASE (0x3FFFC000) +#define LPC_GPIO1_BASE (0x3FFFC020) +#define LPC_GPIO2_BASE (0x3FFFC040) +#define LPC_GPIO3_BASE (0x3FFFC060) +#define LPC_GPIO4_BASE (0x3FFFC080) + + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define LPC_SC (( LPC_SC_TypeDef *) LPC_SC_BASE) +#define LPC_GPIO0 (( LPC_GPIO_TypeDef *) LPC_GPIO0_BASE) +#define LPC_GPIO1 (( LPC_GPIO_TypeDef *) LPC_GPIO1_BASE) +#define LPC_GPIO2 (( LPC_GPIO_TypeDef *) LPC_GPIO2_BASE) +#define LPC_GPIO3 (( LPC_GPIO_TypeDef *) LPC_GPIO3_BASE) +#define LPC_GPIO4 (( LPC_GPIO_TypeDef *) LPC_GPIO4_BASE) +#define LPC_WDT (( LPC_WDT_TypeDef *) LPC_WDT_BASE) +#define LPC_TIM0 (( LPC_TIM_TypeDef *) LPC_TIM0_BASE) +#define LPC_TIM1 (( LPC_TIM_TypeDef *) LPC_TIM1_BASE) +#define LPC_TIM2 (( LPC_TIM_TypeDef *) LPC_TIM2_BASE) +#define LPC_TIM3 (( LPC_TIM_TypeDef *) LPC_TIM3_BASE) +#define LPC_UART0 (( LPC_UART_TypeDef *) LPC_UART0_BASE) +#define LPC_UART1 (( LPC_UART1_TypeDef *) LPC_UART1_BASE) +#define LPC_UART2 (( LPC_UART_TypeDef *) LPC_UART2_BASE) +#define LPC_UART3 (( LPC_UART_TypeDef *) LPC_UART3_BASE) +#define LPC_PWM1 (( LPC_PWM_TypeDef *) LPC_PWM1_BASE) +#define LPC_I2C0 (( LPC_I2C_TypeDef *) LPC_I2C0_BASE) +#define LPC_I2C1 (( LPC_I2C_TypeDef *) LPC_I2C1_BASE) +#define LPC_I2C2 (( LPC_I2C_TypeDef *) LPC_I2C2_BASE) +#define LPC_I2S (( LPC_I2S_TypeDef *) LPC_I2S_BASE) +#define LPC_SPI (( LPC_SPI_TypeDef *) LPC_SPI_BASE) +#define LPC_RTC (( LPC_RTC_TypeDef *) LPC_RTC_BASE) +#define LPC_GPIOINT (( LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE) +#define LPC_PINCON (( LPC_PINCON_TypeDef *) LPC_PINCON_BASE) +#define LPC_SSP0 (( LPC_SSP_TypeDef *) LPC_SSP0_BASE) +#define LPC_SSP1 (( LPC_SSP_TypeDef *) LPC_SSP1_BASE) +#define LPC_ADC (( LPC_ADC_TypeDef *) LPC_ADC_BASE) +#define LPC_DAC (( LPC_DAC_TypeDef *) LPC_DAC_BASE) +#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) +#define LPC_CANAF (( LPC_CANAF_TypeDef *) LPC_CANAF_BASE) +#define LPC_CANCR (( LPC_CANCR_TypeDef *) LPC_CANCR_BASE) +#define LPC_CAN1 (( LPC_CAN_TypeDef *) LPC_CAN1_BASE) +#define LPC_CAN2 (( LPC_CAN_TypeDef *) LPC_CAN2_BASE) +#define LPC_MCI (( LPC_MCI_TypeDef *) LPC_MCI_BASE) +#define LPC_EMAC (( LPC_EMAC_TypeDef *) LPC_EMAC_BASE) +#define LPC_GPDMA (( LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE) +#define LPC_GPDMACH0 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE) +#define LPC_GPDMACH1 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE) +#define LPC_USB (( LPC_USB_TypeDef *) LPC_USB_BASE) +#define LPC_VIC (( LPC_VIC_TypeDef *) LPC_VIC_BASE) +#define LPC_EMC (( LPC_EMC_TypeDef *) LPC_EMC_BASE) + +#ifdef __cplusplus + } +#endif + +#endif // __LPC24xx_H + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/LPC2460.ld b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/LPC2460.ld new file mode 100644 index 0000000000..257cd5971b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/LPC2460.ld @@ -0,0 +1,209 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(vectors) + +/* Memory Definitions: */ +MEMORY +{ + Flash (rx) : ORIGIN = 0xA0001000, LENGTH = 512k + Ram (rwx) : ORIGIN = 0x40000040, LENGTH = 64k - 0x40 + UsbRam (rw) : ORIGIN = 0x7FD00000, LENGTH = 8k + EthRam (rw) : ORIGIN = 0x7FE00000, LENGTH = 16k + CanRam (rw) : ORIGIN = 0xE0038000, LENGTH = 2k + BatRam (rw) : ORIGIN = 0xE0084000, LENGTH = 2k +} + +/* Stack sizes: */ +UND_Stack_Size = 64; +SVC_Stack_Size = 64; +ABT_Stack_Size = 64; +FIQ_Stack_Size = 64; +IRQ_Stack_Size = 64; +User_Stack_Size = 4096; +Stack_Size_Total = UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size + User_Stack_Size; + +/* Stack tops for each mode: */ +__und_stack_top__ = __stacks_top__; +__abt_stack_top__ = __und_stack_top__ - UND_Stack_Size ; +__fiq_stack_top__ = __abt_stack_top__ - ABT_Stack_Size ; +__irq_stack_top__ = __fiq_stack_top__ - FIQ_Stack_Size ; +__svc_stack_top__ = __irq_stack_top__ - IRQ_Stack_Size ; + +/* C-accessible symbols for memory address ranges: */ +__FLASH_segment_start__ = ORIGIN( Flash ); +__FLASH_segment_end__ = ORIGIN( Flash ) + LENGTH( Flash ); +__SRAM_segment_start__ = ORIGIN( Ram ); +__SRAM_segment_end__ = ORIGIN( Ram ) + LENGTH( Ram ); + +/* Stacks (full descending) at top of RAM, grows downward: + * + * __stack_min__ is used by the malloc implementation to ensure heap never collides + * with stack (assuming stack never grows beyond Stack_Size_Total in length) */ +__stacks_top__ = __SRAM_segment_end__; +__stacks_min__ = __SRAM_segment_end__ - Stack_Size_Total; + +SECTIONS +{ + /* first section is .text which is used for code */ + __text_start__ = . ; + .text : { + __privileged_code_start__ = . ; + KEEP( *( .vectors ) ) + *( .privileged_code ) + + __privileged_code_end__ = .; + + *( .text .text.* .gnu.linkonce.t.* ) + *( .plt ) + *( .gnu.warning ) + *( .glue_7t ) *( .glue_7 ) *( .vfp11_veneer ) + + *( .rodata .rodata.* .gnu.linkonce.r.* ) + + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + *(.eh_frame_hdr) + *(.eh_frame) + + . = ALIGN( 4 ) ; + KEEP( *( .init ) ) + . = ALIGN( 4 ) ; + __preinit_array_start = . ; + KEEP( *( .preinit_array ) ) + __preinit_array_end = . ; + . = ALIGN( 4 ) ; + __init_array_start = . ; + KEEP( *( SORT( .init_array.* ) ) ) + KEEP( *( .init_array ) ) + __init_array_end = . ; + + . = ALIGN( 4 ) ; + KEEP( *crtbegin.o( .ctors ) ) + KEEP( *( EXCLUDE_FILE( *crtend.o ) .ctors ) ) + KEEP( *( SORT( .ctors.* ) ) ) + KEEP( *crtend.o( .ctors ) ) + + . = ALIGN( 4 ) ; + KEEP( *( .fini ) ) + . = ALIGN( 4 ) ; + __fini_array_start = . ; + KEEP( *( .fini_array ) ) + KEEP( *( SORT( .fini_array.* ) ) ) + __fini_array_end = . ; + + KEEP( *crtbegin.o( .dtors ) ) + KEEP( *( EXCLUDE_FILE( *crtend.o ) .dtors ) ) + KEEP( *( SORT( .dtors.* ) ) ) + KEEP( *crtend.o( .dtors ) ) + + } >Flash + + __exidx_start = . ; + .ARM.exidx : { + *( .ARM.exidx* .gnu.linkonce.armexidx.* ) + } >Flash + __exidx_end = . ; + + .text.align : { . = ALIGN( 8 ) ; } >Flash /* Alignment schenanigans */ + __text_end__ = . ; + + /* .bss section -- used for uninitialized data */ + /* Located at the start of RAM */ + .bss (NOLOAD) : { + __bss_start__ = . ; + *crt0.o( .ram_vectors ) + + __user_bss_start__ = . ; + *( .user_bss ) + __user_bss_end__ = . ; + + *( .shbss ) + *( .bss .bss.* .gnu.linkonce.b.* ) + *( COMMON ) + *( .ram.b ) + . = ALIGN( 8 ) ; + + __bss_end__ = . ; + } >Ram AT>Flash + + /* .data section -- used for initialized data */ + .data : { + __data_start__ = . ; + KEEP( *( .jcr ) ) + *( .got.plt ) *( .got ) + *( .shdata ) + *( .data .data.* .gnu.linkonce.d.* ) + *( .ram ) + . = ALIGN( 8 ) ; + __data_end__ = . ; + } >Ram AT>Flash + + __data_init_start__ = LOADADDR( .data ) ; + + /* Heap starts here and grows up in memory */ + . = ALIGN( 8 ) ; + __heap_start__ = . ; + end = . ; + __end__ = . ; + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + /* DWARF debug sections. */ + /* Symbols in the DWARF debugging sections are relative to the */ + /* beginning of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* DWARF 3 */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + + .note.gnu.arm.ident 0 : { KEEP( *( .note.gnu.arm.ident ) ) } + .ARM.attributes 0 : { + KEEP( *( .ARM.attributes ) ) + KEEP( *( .gnu.attributes ) ) + } + /DISCARD/ : { *( .note.GNU-stack ) } + + /* C data can be defined as being in special purpose RAMs using + * __attribute__ ((section ("ethram"))) for example. */ + .usbram (NOLOAD): + { + *( .usbram ) + *( .usbram.* ) + } > UsbRam + .ethram (NOLOAD): + { + *( .ethram ) + *( .ethram.* ) + } > EthRam + .canram (NOLOAD): + { + *( .canram ) + *( .canram.* ) + } > CanRam + .batram (NOLOAD): + { + *( .batram ) + *( .batram.* ) + } > BatRam +} diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_functions.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_functions.s new file mode 100644 index 0000000000..a2e3e1dda5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_functions.s @@ -0,0 +1,154 @@ +/* .include "vector_defns.h" */ + + + +.section .privileged_code, "ax" +.arm + + +.weak __mbed_fiq +.weak __mbed_undef +.weak __mbed_prefetch_abort +.weak __mbed_data_abort +.weak __mbed_irq +.weak __mbed_swi +.weak __mbed_dcc_irq +.weak __mbed_reset +.global __mbed_init_realmonitor +/* .global __mbed_init */ + + + + +__mbed_fiq: + B __mbed_fiq +__mbed_undef: + LDR PC, =0x7fffffa0 +__mbed_prefetch_abort: + LDR PC, =0x7fffffb0 +__mbed_data_abort: + LDR PC, =0x7fffffc0 +__mbed_irq: + MSR CPSR_c, #0x1F|0x80|0x40 + + STMDB sp!, {r0-r3,r12,lr} + + MOV r0, #0xFFFFFF00 + LDR r0, [r0] + + MOV lr, pc + BX r0 + + MOV r0, #0xFFFFFF00 + STR r0, [r0] + + LDMFD sp!,{r0-r3,r12,lr} + + MSR CPSR_c, #0x12|0x80|0x40 + + SUBS pc, lr, #4 +__mbed_swi: + STMFD sp!, {a4, r4, ip, lr} + + LDR r4, =0x40000040 + + LDR a4, =0x00940000 + LDR PC, =0x7ffff820 +__mbed_dcc_irq: + LDMFD sp!,{r0-r3,r12,lr} + + MSR CPSR_c, #0x12|0x80|0x40 + + SUB lr, lr, #4 + STMFD sp!, {ip,lr} + + LDR LR, =0xfffff000 + STR LR, [LR, #0xf00] + + LDR PC, =0x7fffffe0 +/* + __mbed_reset is called after reset + we setup the stacks and realmonitor, then call Reset_Handler like on M3 +*/ + +.section .text, "ax" +.arm +.global Reset_handler +Reset_Handler: + .extern __libc_init_array + .extern SystemInit + LDR R0, =SystemInit + MOV LR, PC + BX R0 + + LDR R0, =__libc_init_array + MOV LR, PC + BX R0 + + MSR CPSR_c, #0x1F /* enable irq */ + + LDR R0, =main + BX R0 + +__mbed_reset: + LDR R0, =( __SRAM_segment_end__ ) + + MSR CPSR_c, #0x1B|0x80|0x40 + MOV SP, R0 + SUB R0, R0, #0x00000040 + + MSR CPSR_c, #0x17|0x80|0x40 + MOV SP, R0 + SUB R0, R0, #0x00000040 + + MSR CPSR_c, #0x11|0x80|0x40 + MOV SP, R0 + SUB R0, R0, #0x00000040 + + MSR CPSR_c, #0x12|0x80|0x40 + MOV SP, R0 + SUB R0, R0, #0x00000040 + + MSR CPSR_c, #0x13|0x80|0x40 + MOV SP, R0 + SUB R0, R0, #0x00000040 + +/* MSR CPSR_c, #0x10|0x80|0x40 + MOV SP, R0 +*/ + MSR CPSR_c, #0x1F|0x80|0x40 + MOV SP, R0 + +/* Relocate .data section (Copy from ROM to RAM) */ + LDR R1, =__text_end__ /* _etext */ + LDR R2, =__data_start__ /* _data */ + LDR R3, =__data_end__ /* _edata */ + CMP R2, R3 + BEQ DataIsEmpty +LoopRel: CMP R2, R3 + LDRLO R0, [R1], #4 + STRLO R0, [R2], #4 + BLO LoopRel +DataIsEmpty: + +/* Clear .bss section (Zero init) */ + MOV R0, #0 + LDR R1, =__bss_start__ + LDR R2, =__bss_end__ + CMP R1,R2 + BEQ BSSIsEmpty +LoopZI: CMP R1, R2 + STRLO R0, [R1], #4 + BLO LoopZI +BSSIsEmpty: + + +/* Init realmonitor */ +/* LDR R0, =__mbed_init_realmonitor + MOV LR, PC + BX R0 +/* + +/* Go to Reset_Handler */ + LDR R0, =Reset_Handler + BX R0 diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_table.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_table.s new file mode 100644 index 0000000000..d797c3794d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_table.s @@ -0,0 +1,45 @@ +# 1 "vector_table.s" +# 1 "" +# 1 "" +# 1 "vector_table.s" +; + + + + +# 1 "vector_defns.h" 1 +# 7 "vector_table.s" 2 + +; + + + + + + + + .section .vectors, "ax" + .arm + + + .global __main + .global __mbed_reset + .global __mbed_undef + .global __mbed_swi + .global __mbed_prefetch_abort + .global __mbed_data_abort + .global __mbed_irq + .global __mbed_fiq + +; + + +_start: + LDR PC, =__mbed_reset + LDR PC, =__mbed_undef + LDR PC, =__mbed_swi + LDR PC, =__mbed_prefetch_abort + LDR PC, =__mbed_data_abort + NOP ; + LDR PC, =__mbed_irq + LDR PC, =__mbed_fiq diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/cmsis.h new file mode 100644 index 0000000000..b614854371 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/cmsis.h @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC2368 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "LPC24xx.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/cmsis_nvic.c new file mode 100644 index 0000000000..6df47d1b3e --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/cmsis_nvic.c @@ -0,0 +1,40 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + LPC_VIC->VectAddr[(int)IRQn] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + return LPC_VIC->VectAddr[(int)IRQn]; +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/cmsis_nvic.h new file mode 100644 index 0000000000..a4ab256498 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/cmsis_nvic.h @@ -0,0 +1,51 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS 32 +#define NVIC_USER_IRQ_OFFSET 0 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/core_arm7.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/core_arm7.c new file mode 100644 index 0000000000..3ed1daeeb4 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/core_arm7.c @@ -0,0 +1,44 @@ +/* mbed Microcontroller Library + * Copyright (C) 2008-2009 ARM Limited. All rights reserved. + * + * ARM7 version of CMSIS-like functionality - not advised for use outside mbed! + * based on core_cm3.h, V1.20 + */ + +#include + + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for armcc */ + #define __INLINE __inline /*!< inline keyword for armcc */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for iarcc */ + #define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for gcc */ + #define __INLINE inline /*!< inline keyword for gcc */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +#if defined ( __CC_ARM ) +/** + * @brief Return the Main Stack Pointer (return current ARM7 stack) + * + * @param none + * @return uint32_t Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) +{ + return __current_sp(); +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/core_arm7.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/core_arm7.h new file mode 100644 index 0000000000..9655813058 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/core_arm7.h @@ -0,0 +1,276 @@ +/* mbed Microcontroller Library + * Copyright (C) 2008-2009 ARM Limited. All rights reserved. + * + * ARM7 version of CMSIS-like functionality - not advised for use outside mbed! + * based on core_cm3.h, V1.20 + */ + +#ifndef __ARM7_CORE_H__ +#define __ARM7_CORE_H__ + +#include "vector_defns.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +/** + * Lint configuration \n + * ----------------------- \n + * + * The following Lint messages will be suppressed and not shown: \n + * \n + * --- Error 10: --- \n + * register uint32_t __regBasePri __asm("basepri"); \n + * Error 10: Expecting ';' \n + * \n + * --- Error 530: --- \n + * return(__regBasePri); \n + * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n + * \n + * --- Error 550: --- \n + * __regBasePri = (basePri & 0x1ff); \n + * } \n + * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n + * \n + * --- Error 754: --- \n + * uint32_t RESERVED0[24]; \n + * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced \n + * \n + * --- Error 750: --- \n + * #define __CM3_CORE_H__ \n + * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n + * \n + * --- Error 528: --- \n + * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n + * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n + * \n + * --- Error 751: --- \n + * } InterruptType_Type; \n + * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n + * \n + * \n + * Note: To re-enable a Message, insert a space before 'lint' * \n + * + */ + +/*lint -save */ +/*lint -e10 */ +/*lint -e530 */ +/*lint -e550 */ +/*lint -e754 */ +/*lint -e750 */ +/*lint -e528 */ +/*lint -e751 */ + +#include /* Include standard types */ + +#if defined ( __CC_ARM ) +/** + * @brief Return the Main Stack Pointer (current ARM7 stack) + * + * @param none + * @return uint32_t Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); +#endif + + +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ +#endif + +typedef struct +{ + uint32_t IRQStatus; + uint32_t FIQStatus; + uint32_t RawIntr; + uint32_t IntSelect; + uint32_t IntEnable; + uint32_t IntEnClr; + uint32_t SoftInt; + uint32_t SoftIntClr; + uint32_t Protection; + uint32_t SWPriorityMask; + uint32_t RESERVED0[54]; + uint32_t VectAddr[32]; + uint32_t RESERVED1[32]; + uint32_t VectPriority[32]; + uint32_t RESERVED2[800]; + uint32_t Address; +} NVIC_TypeDef; + +#define NVIC_BASE (0xFFFFF000) +#define NVIC (( NVIC_TypeDef *) NVIC_BASE) + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus +#define __I volatile /*!< defines 'read only' permissions */ +#else +#define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#define __enable_fault_irq __enable_fiq +#define __disable_fault_irq __disable_fiq + +#define __NOP __nop +//#define __WFI __wfi +//#define __WFE __wfe +//#define __SEV __sev +//#define __ISB() __isb(0) +//#define __DSB() __dsb(0) +//#define __DMB() __dmb(0) +//#define __REV __rev +//#define __RBIT __rbit +#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) +#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) +#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) +#define __STREXB(value, ptr) __strex(value, ptr) +#define __STREXH(value, ptr) __strex(value, ptr) +#define __STREXW(value, ptr) __strex(value, ptr) + +#define __disable_irq() unsigned tmp_IntEnable = LPC_VIC->IntEnable; \ + LPC_VIC->IntEnClr = 0xffffffff + +#define __enable_irq() LPC_VIC->IntEnable = tmp_IntEnable + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ + +#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ +#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ +#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */ + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ + +static __INLINE void __enable_irq() { + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + +static __INLINE void __disable_irq() { + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + // return (old & 0x80) == 0; +} + +static __INLINE void __NOP() { __ASM volatile ("nop"); } + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn_Type IRQn specifies the interrupt number + * @return none + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->IntEnable = 1 << (uint32_t)IRQn; +} + + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn_Type IRQn is the positive number of the external interrupt + * @return none + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->IntEnClr = 1 << (uint32_t)IRQn; +} + +static __INLINE uint32_t __get_IPSR(void) +{ + unsigned i; + + for(i = 0; i < 32; i ++) + if(NVIC->Address == NVIC->VectAddr[i]) + return i; + return 1; // 1 is an invalid entry in the interrupt table on LPC2368 +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ARM7_CORE_H__ */ + +/*lint -restore */ diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/system_LPC24xx.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/system_LPC24xx.c new file mode 100644 index 0000000000..ad285b69ba --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/system_LPC24xx.c @@ -0,0 +1,164 @@ +/* mbed Microcontroller Library + * Copyright (C) 2008-2009 ARM Limited. All rights reserved. + * + * ARM7 version of CMSIS-like functionality - not advised for use outside mbed! + */ + +#include +#include "LPC24xx.h" + +#define CLOCK_SETUP 1 +#define SCS_Val ((1<<4) | (1 << 5)) +#define CLKSRCSEL_Val 0x00000001 + +#define PLL0_SETUP 1 +#define PLL0CFG_Val 0x0000000B +#define CCLKCFG_Val 0x00000003 +#define USBCLKCFG_Val 0x00000005 +#define PCLKSEL0_Val 0x00000000 +#define PCLKSEL1_Val 0x00000000 +#define PCONP_Val (1 << PCEMC) +#define CLKOUTCFG_Val 0x00000000 +#define MAMCR_Val 0x00000002 +#define MAMTIM_Val 0x00000004 + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ + +#define XTAL (12000000UL) /* Oscillator frequency */ +#define OSC_CLK ( XTAL) /* Main oscillator frequency */ +#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */ +#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ + +/* F_cco0 = (2 * M * F_in) / N */ +#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1) +#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1) +#define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N) +#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1) + +/* Determine core clock frequency according to settings */ + #if (PLL0_SETUP) + #if ((CLKSRCSEL_Val & 0x03) == 1) + #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV) + #elif ((CLKSRCSEL_Val & 0x03) == 2) + #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV) + #else + #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV) + #endif + #endif + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + /* Determine clock frequency according to clock register values */ + if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */ + switch (LPC_SC->CLKSRCSEL & 0x03) { + case 0: /* Int. RC oscillator => PLL0 */ + case 3: /* Reserved, default to Int. RC */ + SystemCoreClock = (IRC_OSC * + (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / + (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) / + ((LPC_SC->CCLKCFG & 0xFF)+ 1)); + break; + case 1: /* Main oscillator => PLL0 */ + SystemCoreClock = (OSC_CLK * + (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / + (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) / + ((LPC_SC->CCLKCFG & 0xFF)+ 1)); + break; + case 2: /* RTC oscillator => PLL0 */ + SystemCoreClock = (RTC_CLK * + (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / + (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) / + ((LPC_SC->CCLKCFG & 0xFF)+ 1)); + break; + } + } else { + switch (LPC_SC->CLKSRCSEL & 0x03) { + case 0: /* Int. RC oscillator => PLL0 */ + case 3: /* Reserved, default to Int. RC */ + SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); + break; + case 1: /* Main oscillator => PLL0 */ + SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); + break; + case 2: /* RTC oscillator => PLL0 */ + SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); + break; + } + } +} + +void vectorRemap() +{ + #define ARM_VECTOR_REBASE (0x40000000) + extern unsigned long __privileged_code_start__; /* Startup code address from linker */ + int i; + + /* Copy ARM vector table into internal RAM */ + for (i = 0; i <= 56; i+=2) + { + *(unsigned short *)(ARM_VECTOR_REBASE + i) = *(unsigned short *)((unsigned long)(&__privileged_code_start__) + i); + } + +// *(unsigned long *)(ARM_VECTOR_REBASE) = (unsigned long)armUnexpReset; + /* Remap the interrupt vectors to RAM */ + LPC_SC->MEMMAP = 2; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemFrequency variable. + */ +void SystemInit (void) +{ + LPC_WDT->WDMOD = 0; /* Disable internal watchdog */ +#if (CLOCK_SETUP) /* Clock Setup */ + LPC_SC->SCS = SCS_Val; + if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ + while ((LPC_SC->SCS & (1 << 6)) == 0); /* Wait for Oscillator to be ready */ + } + + LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ + +#if (PLL0_SETUP) + LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ + LPC_SC->PLL0CFG = PLL0CFG_Val; + LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ + LPC_SC->PLL0FEED = 0xAA; + LPC_SC->PLL0FEED = 0x55; + while (!(LPC_SC->PLL0STAT & (1 << 26))); /* Wait for PLOCK0 */ + + LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ + LPC_SC->PLL0FEED = 0xAA; + LPC_SC->PLL0FEED = 0x55; +#endif + + LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */ +#endif + + LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ + LPC_SC->PCLKSEL1 = PCLKSEL1_Val; + + LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ + + // Setup MAM + LPC_SC->MAMTIM = MAMTIM_Val; + LPC_SC->MAMCR = MAMCR_Val; + vectorRemap(); +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/system_LPC24xx.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/system_LPC24xx.h new file mode 100644 index 0000000000..714ddb661c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/system_LPC24xx.h @@ -0,0 +1,44 @@ +/* mbed Microcontroller Library + * Copyright (C) 2008-2009 ARM Limited. All rights reserved. + * + * ARM7 version of CMSIS-like functionality - not advised for use outside mbed! + * based on cmsis system_LPC17xx.h + */ + +#ifndef __SYSTEM_LPC24xx_H +#define __SYSTEM_LPC24xx_H + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/vector_defns.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/vector_defns.h new file mode 100644 index 0000000000..46b5f1f720 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/vector_defns.h @@ -0,0 +1,77 @@ +/* mbed Microcontroller Library - Vectors + * Copyright (c) 2006-2009 ARM Limited. All rights reserved. + */ + +#ifndef MBED_VECTOR_DEFNS_H +#define MBED_VECTOR_DEFNS_H + +// Assember Macros +#ifdef __ARMCC_VERSION +#define EXPORT(x) EXPORT x +#define WEAK_EXPORT(x) EXPORT x [WEAK] +#define IMPORT(x) IMPORT x +#define LABEL(x) x +#else +#define EXPORT(x) .global x +#define WEAK_EXPORT(x) .weak x +#define IMPORT(x) .global x +#define LABEL(x) x: +#endif + +// RealMonitor +// Requires RAM (0x40000040-0x4000011F) to be allocated by the linker + +// RealMonitor entry points +#define rm_init_entry 0x7fffff91 +#define rm_undef_handler 0x7fffffa0 +#define rm_prefetchabort_handler 0x7fffffb0 +#define rm_dataabort_handler 0x7fffffc0 +#define rm_irqhandler2 0x7fffffe0 +//#define rm_RunningToStopped 0x7ffff808 // ARM - MBED64 +#define rm_RunningToStopped 0x7ffff820 // ARM - PHAT40 + +// Unofficial RealMonitor entry points and variables +#define RM_MSG_SWI 0x00940000 +#define StateP 0x40000040 + +// VIC register addresses +#define VIC_Base 0xfffff000 +#define VICAddress_Offset 0xf00 +#define VICVectAddr0_Offset 0x100 +#define VICVectAddr2_Offset 0x108 +#define VICVectAddr3_Offset 0x10c +#define VICVectAddr31_Offset 0x17c +#define VICIntEnClr_Offset 0x014 +#define VICIntEnClr (*(volatile unsigned long *)(VIC_Base + 0x014)) +#define VICVectAddr2 (*(volatile unsigned long *)(VIC_Base + 0x108)) +#define VICVectAddr3 (*(volatile unsigned long *)(VIC_Base + 0x10C)) + +// ARM Mode bits and Interrupt flags in PSRs +#define Mode_USR 0x10 +#define Mode_FIQ 0x11 +#define Mode_IRQ 0x12 +#define Mode_SVC 0x13 +#define Mode_ABT 0x17 +#define Mode_UND 0x1B +#define Mode_SYS 0x1F +#define I_Bit 0x80 // when I bit is set, IRQ is disabled +#define F_Bit 0x40 // when F bit is set, FIQ is disabled + +// MCU RAM +#define LPC2460_RAM_ADDRESS 0x40000000 // RAM Base +#define LPC2460_RAM_SIZE 0x10000 // 64KB + +// ISR Stack Allocation +#define UND_stack_size 0x00000040 +#define SVC_stack_size 0x00000040 +#define ABT_stack_size 0x00000040 +#define FIQ_stack_size 0x00000000 +#define IRQ_stack_size 0x00000040 + +#define ISR_stack_size (UND_stack_size + SVC_stack_size + ABT_stack_size + FIQ_stack_size + IRQ_stack_size) + +// Full Descending Stack, so top-most stack points to just above the top of RAM +#define LPC2460_STACK_TOP (LPC2460_RAM_ADDRESS + LPC2460_RAM_SIZE) +#define USR_STACK_TOP (LPC2460_STACK_TOP - ISR_stack_size) + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/vector_realmonitor.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/vector_realmonitor.c new file mode 100644 index 0000000000..921fe43299 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/vector_realmonitor.c @@ -0,0 +1,22 @@ +/* mbed Microcontroller Library - RealMonitor + * Copyright (c) 2006-2009 ARM Limited. All rights reserved. + */ +#include "vector_defns.h" + +extern void __mbed_dcc_irq(void); + +/* Function: __mbed_init_realmonitor + * Setup the RealMonitor DCC Interrupt Handlers + */ +void __mbed_init_realmonitor(void) __attribute__((weak)); +void __mbed_init_realmonitor() { + // Disable all interrupts + VICIntEnClr = 0xffffffff; + + // Set DCC interrupt vector addresses + VICVectAddr2 = (unsigned)&__mbed_dcc_irq; + VICVectAddr3 = (unsigned)&__mbed_dcc_irq; + + // Initialise RealMonitor + ((void (*)(void))rm_init_entry)(); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PeripheralNames.h new file mode 100644 index 0000000000..addae6382f --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PeripheralNames.h @@ -0,0 +1,110 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = (int)LPC_UART0_BASE, + UART_1 = (int)LPC_UART1_BASE, + UART_2 = (int)LPC_UART2_BASE, + UART_3 = (int)LPC_UART3_BASE +} UARTName; + +typedef enum { + ADC0_0 = 0, + ADC0_1, + ADC0_2, + ADC0_3, + ADC0_4, + ADC0_5, + ADC0_6, + ADC0_7 +} ADCName; + +typedef enum { + DAC_0 = 0 +} DACName; + +typedef enum { + SPI_0 = (int)LPC_SSP0_BASE, + SPI_1 = (int)LPC_SSP1_BASE +} SPIName; + +typedef enum { + I2C_0 = (int)LPC_I2C0_BASE, + I2C_1 = (int)LPC_I2C1_BASE, + I2C_2 = (int)LPC_I2C2_BASE +} I2CName; + +typedef enum { + PWM_1 = 1, + PWM_2, + PWM_3, + PWM_4, + PWM_5, + PWM_6 +} PWMName; + +typedef enum { + CAN_1 = (int)LPC_CAN1_BASE, + CAN_2 = (int)LPC_CAN2_BASE +} CANName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_2 + +// Default peripherals +#define MBED_SPI0 p5, p6, p7, p8 +#define MBED_SPI1 p11, p12, p13, p14 + +#define MBED_UART0 p9, p10 +#define MBED_UART1 p13, p14 +#define MBED_UART2 p27, p28 +#define MBED_UARTUSB USBTX, USBRX + +#define MBED_I2C0 p28, p27 +#define MBED_I2C1 p9, p10 + +#define MBED_CAN0 p30, p29 + +#define MBED_ANALOGOUT0 p18 + +#define MBED_ANALOGIN0 p15 +#define MBED_ANALOGIN1 p16 +#define MBED_ANALOGIN2 p17 +#define MBED_ANALOGIN3 p18 +#define MBED_ANALOGIN4 p19 +#define MBED_ANALOGIN5 p20 + +#define MBED_PWMOUT0 p26 +#define MBED_PWMOUT1 p25 +#define MBED_PWMOUT2 p24 +#define MBED_PWMOUT3 p23 +#define MBED_PWMOUT4 p22 +#define MBED_PWMOUT5 p21 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PinNames.h new file mode 100644 index 0000000000..727c6089e9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PinNames.h @@ -0,0 +1,107 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 5 + +typedef enum { + // LPC Pin Names + P0_0 = LPC_GPIO0_BASE, + P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31, + P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31, + P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31, + P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31, + P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31, + + // mbed DIP Pin Names + p5 = P0_18, + p6 = P0_17, + p7 = P0_15, + p8 = P0_16, + + p9 = P0_2, + p10 = P0_3, + p11 = P0_18, + p12 = P0_17, + p13 = P2_0, + p14 = P2_1, + p15 = P0_23, + p16 = P0_24, + p17 = P0_25, + p18 = P0_26, + p19 = P1_30, + p20 = P1_31, + p21 = P2_5, + p22 = P2_4, + p23 = P2_3, + p24 = P2_2, + p25 = P2_1, + p26 = P2_0, + p27 = P2_8, + p28 = P2_9, + p29 = P0_5, + p30 = P0_4, + + // Other mbed Pin Names + LED1 = P1_19, + LED2 = P2_26, + LED3 = P2_27, + LED4 = P2_27, + + USBTX = P2_8, + USBRX = P2_9, + + EXT_WDT = P0_10, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullUp = 0, + PullDown = 3, + PullNone = 2, + OpenDrain = 4, + PullDefault = PullDown +} PinMode; + +// version of PINCON_TypeDef using register arrays +typedef struct { + __IO uint32_t PINSEL[11]; + uint32_t RESERVED0[5]; + __IO uint32_t PINMODE[10]; +} PINCONARRAY_TypeDef; + +#define PINCONARRAY ((PINCONARRAY_TypeDef *)LPC_PINCON_BASE) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PortNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PortNames.h new file mode 100644 index 0000000000..e89310d059 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PortNames.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + Port0 = 0, + Port1 = 1, + Port2 = 2, + Port3 = 3, + Port4 = 4 +} PortName; + +#define PORT_0 Port0 +#define PORT_1 Port1 +#define PORT_2 Port2 +#define PORT_3 Port3 +#ifdef __cplusplus +} +#endif +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/analogin_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/analogin_api.c new file mode 100644 index 0000000000..9a660de266 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/analogin_api.c @@ -0,0 +1,125 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "analogin_api.h" +#include "cmsis.h" +#include "pinmap.h" + +#define ANALOGIN_MEDIAN_FILTER 1 + +#define ADC_10BIT_RANGE 0x3FF +#define ADC_12BIT_RANGE 0xFFF + +static inline int div_round_up(int x, int y) { + return (x + (y - 1)) / y; +} + +static const PinMap PinMap_ADC[] = { + {P0_23, ADC0_0, 1}, + {P0_24, ADC0_1, 1}, + {P0_25, ADC0_2, 1}, + {P0_26, ADC0_3, 1}, + {P1_30, ADC0_4, 3}, + {P1_31, ADC0_5, 3}, + {P0_12, ADC0_6, 3}, + {P0_13, ADC0_7, 3}, + {NC, NC, 0} +}; + +#define ADC_RANGE ADC_10BIT_RANGE + + +void analogin_init(analogin_t *obj, PinName pin) { + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName)NC); + + // ensure power is turned on + LPC_SC->PCONP |= (1 << 12); + + // set PCLK of ADC to /1 + LPC_SC->PCLKSEL0 &= ~(0x3 << 24); + LPC_SC->PCLKSEL0 |= (0x1 << 24); + uint32_t PCLK = SystemCoreClock; + + // calculate minimum clock divider + // clkdiv = divider - 1 + uint32_t MAX_ADC_CLK = 13000000; + uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1; + + // Set the generic software-controlled ADC settings + LPC_ADC->ADCR = (0 << 0) // SEL: 0 = no channels selected + | (clkdiv << 8) // CLKDIV: PCLK max ~= 25MHz, /25 to give safe 1MHz at fastest + | (0 << 16) // BURST: 0 = software control + | (0 << 17) // CLKS: not applicable + | (1 << 21) // PDN: 1 = operational + | (0 << 24) // START: 0 = no start + | (0 << 27); // EDGE: not applicable + + pinmap_pinout(pin, PinMap_ADC); +} + +static inline uint32_t adc_read(analogin_t *obj) { + // Select the appropriate channel and start conversion + LPC_ADC->ADCR &= ~0xFF; + LPC_ADC->ADCR |= 1 << (int)obj->adc; + LPC_ADC->ADCR |= 1 << 24; + + // Repeatedly get the sample data until DONE bit + unsigned int data; + do { + data = LPC_ADC->ADGDR; + } while ((data & ((unsigned int)1 << 31)) == 0); + + // Stop conversion + LPC_ADC->ADCR &= ~(1 << 24); + + return (data >> 6) & ADC_RANGE; // 10 bit +} + +static inline void order(uint32_t *a, uint32_t *b) { + if (*a > *b) { + uint32_t t = *a; + *a = *b; + *b = t; + } +} + +static inline uint32_t adc_read_u32(analogin_t *obj) { + uint32_t value; +#if ANALOGIN_MEDIAN_FILTER + uint32_t v1 = adc_read(obj); + uint32_t v2 = adc_read(obj); + uint32_t v3 = adc_read(obj); + order(&v1, &v2); + order(&v2, &v3); + order(&v1, &v2); + value = v2; +#else + value = adc_read(obj); +#endif + return value; +} + +uint16_t analogin_read_u16(analogin_t *obj) { + uint32_t value = adc_read_u32(obj); + + return (value << 6) | ((value >> 4) & 0x003F); // 10 bit +} + +float analogin_read(analogin_t *obj) { + uint32_t value = adc_read_u32(obj); + return (float)value * (1.0f / (float)ADC_RANGE); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/analogout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/analogout_api.c new file mode 100644 index 0000000000..66c77ceace --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/analogout_api.c @@ -0,0 +1,75 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "analogout_api.h" +#include "cmsis.h" +#include "pinmap.h" + +static const PinMap PinMap_DAC[] = { + {P0_26, DAC_0, 2}, + {NC , NC , 0} +}; + +void analogout_init(dac_t *obj, PinName pin) { + obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); + MBED_ASSERT(obj->dac != (DACName)NC); + + // power is on by default, set DAC clk divider is /4 + LPC_SC->PCLKSEL0 &= ~(0x3 << 22); + + // map out (must be done before accessing registers) + pinmap_pinout(pin, PinMap_DAC); + + analogout_write_u16(obj, 0); +} + +void analogout_free(dac_t *obj) {} + +static inline void dac_write(int value) { + value &= 0x3FF; // 10-bit + + // Set the DAC output + LPC_DAC->DACR = (0 << 16) // bias = 0 + | (value << 6); +} + +static inline int dac_read() { + return (LPC_DAC->DACR >> 6) & 0x3FF; +} + +void analogout_write(dac_t *obj, float value) { + if (value < 0.0f) { + dac_write(0); + } else if (value > 1.0f) { + dac_write(0x3FF); + } else { + dac_write(value * (float)0x3FF); + } +} + +void analogout_write_u16(dac_t *obj, uint16_t value) { + dac_write(value >> 6); // 10-bit +} + +float analogout_read(dac_t *obj) { + uint32_t value = dac_read(); + return (float)value * (1.0f / (float)0x3FF); +} + +uint16_t analogout_read_u16(dac_t *obj) { + uint32_t value = dac_read(); // 10-bit + return (value << 6) | ((value >> 4) & 0x003F); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/can_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/can_api.c new file mode 100644 index 0000000000..a3170acc1d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/can_api.c @@ -0,0 +1,303 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "can_api.h" +#include "cmsis.h" +#include "pinmap.h" + +#include +#include + +/* Acceptance filter mode in AFMR register */ +#define ACCF_OFF 0x01 +#define ACCF_BYPASS 0x02 +#define ACCF_ON 0x00 +#define ACCF_FULLCAN 0x04 + +/* There are several bit timing calculators on the internet. +http://www.port.de/engl/canprod/sv_req_form.html +http://www.kvaser.com/can/index.htm +*/ + +static const PinMap PinMap_CAN_RD[] = { + {P0_0 , CAN_1, 1}, + {P0_4 , CAN_2, 2}, + {P0_21, CAN_1, 3}, + {P2_7 , CAN_2, 1}, + {NC , NC , 0} +}; + +static const PinMap PinMap_CAN_TD[] = { + {P0_1 , CAN_1, 1}, + {P0_5 , CAN_2, 2}, + {P0_22, CAN_1, 3}, + {P2_8 , CAN_2, 1}, + {NC , NC , 0} +}; + +// Type definition to hold a CAN message +struct CANMsg { + unsigned int reserved1 : 16; + unsigned int dlc : 4; // Bits 16..19: DLC - Data Length Counter + unsigned int reserved0 : 10; + unsigned int rtr : 1; // Bit 30: Set if this is a RTR message + unsigned int type : 1; // Bit 31: Set if this is a 29-bit ID message + unsigned int id; // CAN Message ID (11-bit or 29-bit) + unsigned char data[8]; // CAN Message Data Bytes 0-7 +}; +typedef struct CANMsg CANMsg; + +static uint32_t can_disable(can_t *obj) { + uint32_t sm = obj->dev->MOD; + obj->dev->MOD |= 1; + return sm; +} + +static inline void can_enable(can_t *obj) { + if (obj->dev->MOD & 1) { + obj->dev->MOD &= ~(1); + } +} + +int can_mode(can_t *obj, CanMode mode) { + return 0; // not implemented +} + +int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) { + return 0; // not implemented +} + +static int can_pclk(can_t *obj) { + int value = 0; + switch ((int)obj->dev) { + case CAN_1: value = (LPC_SC->PCLKSEL0 & (0x3 << 26)) >> 26; break; + case CAN_2: value = (LPC_SC->PCLKSEL0 & (0x3 << 28)) >> 28; break; + } + + switch (value) { + case 1: return 1; + case 2: return 2; + case 3: return 6; + default: return 4; + } +} + +// This table has the sampling points as close to 75% as possible. The first +// value is TSEG1, the second TSEG2. +static const int timing_pts[23][2] = { + {0x0, 0x0}, // 2, 50% + {0x1, 0x0}, // 3, 67% + {0x2, 0x0}, // 4, 75% + {0x3, 0x0}, // 5, 80% + {0x3, 0x1}, // 6, 67% + {0x4, 0x1}, // 7, 71% + {0x5, 0x1}, // 8, 75% + {0x6, 0x1}, // 9, 78% + {0x6, 0x2}, // 10, 70% + {0x7, 0x2}, // 11, 73% + {0x8, 0x2}, // 12, 75% + {0x9, 0x2}, // 13, 77% + {0x9, 0x3}, // 14, 71% + {0xA, 0x3}, // 15, 73% + {0xB, 0x3}, // 16, 75% + {0xC, 0x3}, // 17, 76% + {0xD, 0x3}, // 18, 78% + {0xD, 0x4}, // 19, 74% + {0xE, 0x4}, // 20, 75% + {0xF, 0x4}, // 21, 76% + {0xF, 0x5}, // 22, 73% + {0xF, 0x6}, // 23, 70% + {0xF, 0x7}, // 24, 67% +}; + +static unsigned int can_speed(unsigned int sclk, unsigned int pclk, unsigned int cclk, unsigned char psjw) { + uint32_t btr; + uint16_t brp = 0; + uint32_t calcbit; + uint32_t bitwidth; + int hit = 0; + int bits; + + bitwidth = sclk / (pclk * cclk); + + brp = bitwidth / 0x18; + while ((!hit) && (brp < bitwidth / 4)) { + brp++; + for (bits = 22; bits > 0; bits--) { + calcbit = (bits + 3) * (brp + 1); + if (calcbit == bitwidth) { + hit = 1; + break; + } + } + } + + if (hit) { + btr = ((timing_pts[bits][1] << 20) & 0x00700000) + | ((timing_pts[bits][0] << 16) & 0x000F0000) + | ((psjw << 14) & 0x0000C000) + | ((brp << 0) & 0x000003FF); + } else { + btr = 0xFFFFFFFF; + } + + return btr; +} + +void can_init(can_t *obj, PinName rd, PinName td) { + CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD); + CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD); + obj->dev = (LPC_CAN_TypeDef *)pinmap_merge(can_rd, can_td); + MBED_ASSERT((int)obj->dev != NC); + + switch ((int)obj->dev) { + case CAN_1: LPC_SC->PCONP |= 1 << 13; break; + case CAN_2: LPC_SC->PCONP |= 1 << 14; break; + } + + pinmap_pinout(rd, PinMap_CAN_RD); + pinmap_pinout(td, PinMap_CAN_TD); + + can_reset(obj); + obj->dev->IER = 0; // Disable Interrupts + can_frequency(obj, 100000); + + LPC_CANAF->AFMR = ACCF_BYPASS; // Bypass Filter +} + +void can_free(can_t *obj) { + switch ((int)obj->dev) { + case CAN_1: LPC_SC->PCONP &= ~(1 << 13); break; + case CAN_2: LPC_SC->PCONP &= ~(1 << 14); break; + } +} + +int can_frequency(can_t *obj, int f) { + int pclk = can_pclk(obj); + int btr = can_speed(SystemCoreClock, pclk, (unsigned int)f, 1); + + if (btr > 0) { + uint32_t modmask = can_disable(obj); + obj->dev->BTR = btr; + obj->dev->MOD = modmask; + return 1; + } else { + return 0; + } +} + +int can_write(can_t *obj, CAN_Message msg, int cc) { + unsigned int CANStatus; + CANMsg m; + + can_enable(obj); + + m.id = msg.id ; + m.dlc = msg.len & 0xF; + m.rtr = msg.type; + m.type = msg.format; + memcpy(m.data, msg.data, msg.len); + const unsigned int *buf = (const unsigned int *)&m; + + CANStatus = obj->dev->SR; + if (CANStatus & 0x00000004) { + obj->dev->TFI1 = buf[0] & 0xC00F0000; + obj->dev->TID1 = buf[1]; + obj->dev->TDA1 = buf[2]; + obj->dev->TDB1 = buf[3]; + if (cc) { + obj->dev->CMR = 0x30; + } else { + obj->dev->CMR = 0x21; + } + return 1; + + } else if (CANStatus & 0x00000400) { + obj->dev->TFI2 = buf[0] & 0xC00F0000; + obj->dev->TID2 = buf[1]; + obj->dev->TDA2 = buf[2]; + obj->dev->TDB2 = buf[3]; + if (cc) { + obj->dev->CMR = 0x50; + } else { + obj->dev->CMR = 0x41; + } + return 1; + + } else if (CANStatus & 0x00040000) { + obj->dev->TFI3 = buf[0] & 0xC00F0000; + obj->dev->TID3 = buf[1]; + obj->dev->TDA3 = buf[2]; + obj->dev->TDB3 = buf[3]; + if (cc) { + obj->dev->CMR = 0x90; + } else { + obj->dev->CMR = 0x81; + } + return 1; + } + + return 0; +} + +int can_read(can_t *obj, CAN_Message *msg, int handle) { + CANMsg x; + unsigned int *i = (unsigned int *)&x; + + can_enable(obj); + + if (obj->dev->GSR & 0x1) { + *i++ = obj->dev->RFS; // Frame + *i++ = obj->dev->RID; // ID + *i++ = obj->dev->RDA; // Data A + *i++ = obj->dev->RDB; // Data B + obj->dev->CMR = 0x04; // release receive buffer + + msg->id = x.id; + msg->len = x.dlc; + msg->format = (x.type)? CANExtended : CANStandard; + msg->type = (x.rtr)? CANRemote: CANData; + memcpy(msg->data,x.data,x.dlc); + return 1; + } + + return 0; +} + +void can_reset(can_t *obj) { + can_disable(obj); + obj->dev->GSR = 0; // Reset error counter when CAN1MOD is in reset +} + +unsigned char can_rderror(can_t *obj) { + return (obj->dev->GSR >> 16) & 0xFF; +} + +unsigned char can_tderror(can_t *obj) { + return (obj->dev->GSR >> 24) & 0xFF; +} + +void can_monitor(can_t *obj, int silent) { + uint32_t mod_mask = can_disable(obj); + if (silent) { + obj->dev->MOD |= (1 << 1); + } else { + obj->dev->MOD &= ~(1 << 1); + } + if (!(mod_mask & 1)) { + can_enable(obj); + } +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/device.h new file mode 100644 index 0000000000..9a20ae4a36 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/device.h @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 1 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 1 +#define DEVICE_LOCALFILESYSTEM 1 +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + +#define DEVICE_SLEEP 0 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_PATTERN 1 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/ethernet_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/ethernet_api.c new file mode 100644 index 0000000000..ba76cbc916 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/ethernet_api.c @@ -0,0 +1,935 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "ethernet_api.h" +#include "cmsis.h" +#include "mbed_interface.h" +#include "toolchain.h" +#include "mbed_error.h" + +#define NEW_LOGIC 0 +#define NEW_ETH_BUFFER 0 + +#if NEW_ETH_BUFFER + +#define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets) +#define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets) + +#define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size +#define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length) + +#else + +// Memfree calculation: +// (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) + +// (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556 +/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ +#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ +#define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */ +//#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ + +//#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ +#define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */ +#define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */ + +const int ethernet_MTU_SIZE = 0x300; + +#endif + +#define ETHERNET_ADDR_SIZE 6 + +PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */ + unsigned int Packet; + unsigned int Ctrl; +}; +typedef struct RX_DESC_TypeDef RX_DESC_TypeDef; + +PACKED struct RX_STAT_TypeDef { /* RX Status struct */ + unsigned int Info; + unsigned int HashCRC; +}; +typedef struct RX_STAT_TypeDef RX_STAT_TypeDef; + +PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */ + unsigned int Packet; + unsigned int Ctrl; +}; +typedef struct TX_DESC_TypeDef TX_DESC_TypeDef; + +PACKED struct TX_STAT_TypeDef { /* TX Status struct */ + unsigned int Info; +}; +typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; + +/* MAC Configuration Register 1 */ +#define MAC1_REC_EN 0x00000001 /* Receive Enable */ +#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ +#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ +#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ +#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ +#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ +#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ +#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ +#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ +#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ +#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ + +/* MAC Configuration Register 2 */ +#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ +#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ +#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ +#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ +#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ +#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ +#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ +#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ +#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ +#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ +#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ +#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ +#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ + +/* Back-to-Back Inter-Packet-Gap Register */ +#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ +#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ + +/* Non Back-to-Back Inter-Packet-Gap Register */ +#define IPGR_DEF 0x00000012 /* Recommended value */ + +/* Collision Window/Retry Register */ +#define CLRT_DEF 0x0000370F /* Default value */ + +/* PHY Support Register */ +#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ +//#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ +#define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */ + +/* Test Register */ +#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ +#define TEST_TST_PAUSE 0x00000002 /* Test Pause */ +#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ + +/* MII Management Configuration Register */ +#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ +#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ +#define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */ +#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ + +/* MII Management Command Register */ +#define MCMD_READ 0x00000001 /* MII Read */ +#define MCMD_SCAN 0x00000002 /* MII Scan continuously */ + +#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ +#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ + +/* MII Management Address Register */ +#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ +#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ + +/* MII Management Indicators Register */ +#define MIND_BUSY 0x00000001 /* MII is Busy */ +#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ +#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ +#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ + +/* Command Register */ +#define CR_RX_EN 0x00000001 /* Enable Receive */ +#define CR_TX_EN 0x00000002 /* Enable Transmit */ +#define CR_REG_RES 0x00000008 /* Reset Host Registers */ +#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ +#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ +#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ +#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ +#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ +#define CR_RMII 0x00000200 /* Reduced MII Interface */ +#define CR_FULL_DUP 0x00000400 /* Full Duplex */ + +/* Status Register */ +#define SR_RX_EN 0x00000001 /* Enable Receive */ +#define SR_TX_EN 0x00000002 /* Enable Transmit */ + +/* Transmit Status Vector 0 Register */ +#define TSV0_CRC_ERR 0x00000001 /* CRC error */ +#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ +#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ +#define TSV0_DONE 0x00000008 /* Tramsmission Completed */ +#define TSV0_MCAST 0x00000010 /* Multicast Destination */ +#define TSV0_BCAST 0x00000020 /* Broadcast Destination */ +#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ +#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ +#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ +#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ +#define TSV0_GIANT 0x00000400 /* Giant Frame */ +#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ +#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ +#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ +#define TSV0_PAUSE 0x20000000 /* Pause Frame */ +#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ +#define TSV0_VLAN 0x80000000 /* VLAN Frame */ + +/* Transmit Status Vector 1 Register */ +#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ +#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ + +/* Receive Status Vector Register */ +#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ +#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ +#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ +#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ +#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ +#define RSV_CRC_ERR 0x00100000 /* CRC Error */ +#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ +#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ +#define RSV_REC_OK 0x00800000 /* Frame Received OK */ +#define RSV_MCAST 0x01000000 /* Multicast Frame */ +#define RSV_BCAST 0x02000000 /* Broadcast Frame */ +#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ +#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ +#define RSV_PAUSE 0x10000000 /* Pause Frame */ +#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ +#define RSV_VLAN 0x40000000 /* VLAN Frame */ + +/* Flow Control Counter Register */ +#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ +#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ + +/* Flow Control Status Register */ +#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ + +/* Receive Filter Control Register */ +#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ +#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ +#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ +#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ +#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ +#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ +#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ +#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ + +/* Receive Filter WoL Status/Clear Registers */ +#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ +#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ +#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ +#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ +#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ +#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ +#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ +#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ + +/* Interrupt Status/Enable/Clear/Set Registers */ +#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ +#define INT_RX_ERR 0x00000002 /* Receive Error */ +#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ +#define INT_RX_DONE 0x00000008 /* Receive Done */ +#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ +#define INT_TX_ERR 0x00000020 /* Transmit Error */ +#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ +#define INT_TX_DONE 0x00000080 /* Transmit Done */ +#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ +#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ + +/* Power Down Register */ +#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ + +/* RX Descriptor Control Word */ +#define RCTRL_SIZE 0x000007FF /* Buffer size mask */ +#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ + +/* RX Status Hash CRC Word */ +#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ +#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ + +/* RX Status Information Word */ +#define RINFO_SIZE 0x000007FF /* Data size in bytes */ +#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ +#define RINFO_VLAN 0x00080000 /* VLAN Frame */ +#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ +#define RINFO_MCAST 0x00200000 /* Multicast Frame */ +#define RINFO_BCAST 0x00400000 /* Broadcast Frame */ +#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ +#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ +#define RINFO_LEN_ERR 0x02000000 /* Length Error */ +#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ +#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ +#define RINFO_OVERRUN 0x10000000 /* Receive overrun */ +#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ +#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ +#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +//#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) +#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \ + RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) + + +/* TX Descriptor Control Word */ +#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ +#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ +#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ +#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ +#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ +#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ +#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ + +/* TX Status Information Word */ +#define TINFO_COL_CNT 0x01E00000 /* Collision Count */ +#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ +#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ +#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ +#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ +#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ +#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ +#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +/* ENET Device Revision ID */ +#define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ + +/* DP83848C PHY Registers */ +#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ +#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ +#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ +#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ +#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ +#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ +#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ +#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ + +/* PHY Extended Registers */ +#define PHY_REG_STS 0x10 /* Status Register */ +#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ +#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ +#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ +#define PHY_REG_RECR 0x15 /* Receive Error Counter */ +#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ +#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ +#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ +#define PHY_REG_PHYCR 0x19 /* PHY Control Register */ +#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ +#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ +#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ + +#define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */ + +#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ +#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ +#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ +#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ +#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ + +#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ +#define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */ + +#define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */ + +#define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */ +#define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */ +#define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */ + +#define PHY_BMCR_RESET 0x8000 /* PHY Reset */ + +#define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */ + +#define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */ +#define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */ + + +static int phy_read(unsigned int PhyReg); +static int phy_write(unsigned int PhyReg, unsigned short Data); + +static void txdscr_init(void); +static void rxdscr_init(void); + +#if defined (__ICCARM__) +# define AHBSRAM1 +#elif defined(TOOLCHAIN_GCC_CR) +# define AHBSRAM1 __attribute__((section(".data.$RamPeriph32"))) +#else +# define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned)) +#endif + +AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE]; +AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE]; +AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG]; +AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG]; +AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG]; +AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG]; + + +#if NEW_LOGIC +static int rx_consume_offset = -1; +static int tx_produce_offset = -1; +#else +static int send_doff = 0; +static int send_idx = -1; +static int send_size = 0; + +static int receive_soff = 0; +static int receive_idx = -1; +#endif + +static uint32_t phy_id = 0; + +static inline int rinc(int idx, int mod) { + ++idx; + idx %= mod; + return idx; +} + +//extern unsigned int SystemFrequency; +static inline unsigned int clockselect() { + if(SystemCoreClock < 10000000) { + return 1; + } else if(SystemCoreClock < 15000000) { + return 2; + } else if(SystemCoreClock < 20000000) { + return 3; + } else if(SystemCoreClock < 25000000) { + return 4; + } else if(SystemCoreClock < 35000000) { + return 5; + } else if(SystemCoreClock < 50000000) { + return 6; + } else if(SystemCoreClock < 70000000) { + return 7; + } else if(SystemCoreClock < 80000000) { + return 8; + } else if(SystemCoreClock < 90000000) { + return 9; + } else if(SystemCoreClock < 100000000) { + return 10; + } else if(SystemCoreClock < 120000000) { + return 11; + } else if(SystemCoreClock < 130000000) { + return 12; + } else if(SystemCoreClock < 140000000) { + return 13; + } else if(SystemCoreClock < 150000000) { + return 15; + } else if(SystemCoreClock < 160000000) { + return 16; + } else { + return 0; + } +} + +#ifndef min +#define min(x, y) (((x)<(y))?(x):(y)) +#endif + +/*---------------------------------------------------------------------------- + Ethernet Device initialize + *----------------------------------------------------------------------------*/ +int ethernet_init() { + int regv, tout; + char mac[ETHERNET_ADDR_SIZE]; + unsigned int clock = clockselect(); + + LPC_SC->PCONP |= 0x40000000; /* Power Up the EMAC controller. */ + + LPC_PINCON->PINSEL2 = 0x50150105; /* Enable P1 Ethernet Pins. */ + LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005; + + /* Reset all EMAC internal modules. */ + LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | + MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES; + LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM; + + for(tout = 100; tout; tout--) __NOP(); /* A short delay after reset. */ + + LPC_EMAC->MAC1 = MAC1_PASS_ALL; /* Initialize MAC control registers. */ + LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; + LPC_EMAC->MAXF = ETH_MAX_FLEN; + LPC_EMAC->CLRT = CLRT_DEF; + LPC_EMAC->IPGR = IPGR_DEF; + + LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; /* Enable Reduced MII interface. */ + + LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; /* Set clock */ + LPC_EMAC->MCFG |= MCFG_RES_MII; /* and reset */ + + for(tout = 100; tout; tout--) __NOP(); /* A short delay */ + + LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; + LPC_EMAC->MCMD = 0; + + LPC_EMAC->SUPP = SUPP_RES_RMII; /* Reset Reduced MII Logic. */ + + for (tout = 100; tout; tout--) __NOP(); /* A short delay */ + + LPC_EMAC->SUPP = 0; + + phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */ + for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */ + regv = phy_read(PHY_REG_BMCR); + if(regv < 0 || tout == 0) { + return -1; /* Error */ + } + if(!(regv & PHY_BMCR_RESET)) { + break; /* Reset complete. */ + } + } + + phy_id = (phy_read(PHY_REG_IDR1) << 16); + phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0); + + if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) { + error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id); + } + + ethernet_set_link(-1, 0); + + /* Set the Ethernet MAC Address registers */ + ethernet_address(mac); + LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4]; + LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2]; + LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0]; + + txdscr_init(); /* initialize DMA TX Descriptor */ + rxdscr_init(); /* initialize DMA RX Descriptor */ + + LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN; + /* Receive Broadcast, Perfect Match Packets */ + + LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Enable EMAC interrupts. */ + LPC_EMAC->IntClear = 0xFFFF; /* Reset all interrupts */ + + + LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); /* Enable receive and transmit mode of MAC Ethernet core */ + LPC_EMAC->MAC1 |= MAC1_REC_EN; + +#if NEW_LOGIC + rx_consume_offset = -1; + tx_produce_offset = -1; +#else + send_doff = 0; + send_idx = -1; + send_size = 0; + + receive_soff = 0; + receive_idx = -1; +#endif + + return 0; +} + +/*---------------------------------------------------------------------------- + Ethernet Device Uninitialize + *----------------------------------------------------------------------------*/ +void ethernet_free() { + LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE); + LPC_EMAC->IntClear = 0xFFFF; + + LPC_SC->PCONP &= ~0x40000000; /* Power down the EMAC controller. */ + + LPC_PINCON->PINSEL2 &= ~0x50150105; /* Disable P1 ethernet pins. */ + LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000000; +} + +// if(TxProduceIndex == TxConsumeIndex) buffer array is empty +// if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill +// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment +// TxConsumeIndex - The buffer that will/is beign sent by hardware + +int ethernet_write(const char *data, int slen) { + +#if NEW_LOGIC + + if(tx_produce_offset < 0) { // mark as active if not already + tx_produce_offset = 0; + } + + int index = LPC_EMAC->TxProduceIndex; + + int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum + int requested = slen; + int ncopy = min(remaining, requested); + + void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset); + void *psrc = (void *)(data); + + if(ncopy > 0 ){ + if(data != NULL) { + memcpy(pdst, psrc, ncopy); + } else { + memset(pdst, 0, ncopy); + } + } + + tx_produce_offset += ncopy; + + return ncopy; + +#else + void *pdst, *psrc; + const int dlen = ETH_FRAG_SIZE; + int copy = 0; + int soff = 0; + + if(send_idx == -1) { + send_idx = LPC_EMAC->TxProduceIndex; + } + + if(slen + send_doff > ethernet_MTU_SIZE) { + return -1; + } + + do { + copy = min(slen - soff, dlen - send_doff); + pdst = (void *)(txdesc[send_idx].Packet + send_doff); + psrc = (void *)(data + soff); + if(send_doff + copy > ETH_FRAG_SIZE) { + txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT); + send_idx = rinc(send_idx, NUM_TX_FRAG); + send_doff = 0; + } + + if(data != NULL) { + memcpy(pdst, psrc, copy); + } else { + memset(pdst, 0, copy); + } + + soff += copy; + send_doff += copy; + send_size += copy; + } while(soff != slen); + + return soff; +#endif +} + +int ethernet_send() { + +#if NEW_LOGIC + if(tx_produce_offset < 0) { // no buffer active + return -1; + } + + // ensure there is a link + if(!ethernet_link()) { + return -2; + } + + // we have been writing in to a buffer, so finalise it + int size = tx_produce_offset; + int index = LPC_EMAC->TxProduceIndex; + txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST); + + // Increment ProduceIndex to allow it to be sent + // We can only do this if the next slot is free + int next = rinc(index, NUM_TX_FRAG); + while(next == LPC_EMAC->TxConsumeIndex) { + for(int i=0; i<1000; i++) { __NOP(); } + } + + LPC_EMAC->TxProduceIndex = next; + tx_produce_offset = -1; + return size; + +#else + int s = send_size; + txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST); + send_idx = rinc(send_idx, NUM_TX_FRAG); + LPC_EMAC->TxProduceIndex = send_idx; + send_doff = 0; + send_idx = -1; + send_size = 0; + return s; +#endif +} + +// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read +// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd +// +// if(RxConsumeIndex == RxProduceIndex) buffer array is empty +// if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full + +// Recevies an arrived ethernet packet. +// Receiving an ethernet packet will drop the last received ethernet packet +// and make a new ethernet packet ready to read. +// Returns size of packet, else 0 if nothing to receive + +// We read from RxConsumeIndex from position rx_consume_offset +// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading +// rx_consume_offset = -1 // no frame +// rx_consume_offset = 0 // start of frame +// Assumption: A fragment should alway be a whole frame + +int ethernet_receive() { +#if NEW_LOGIC + + // if we are currently reading a valid RxConsume buffer, increment to the next one + if(rx_consume_offset >= 0) { + LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG); + } + + // if the buffer is empty, mark it as no valid buffer + if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) { + rx_consume_offset = -1; + return 0; + } + + uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info; + rx_consume_offset = 0; + + // check if it is not marked as last or for errors + if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) { + return -1; + } + + int size = (info & RINFO_SIZE) + 1; + return size - 4; // don't include checksum bytes + +#else + if(receive_idx == -1) { + receive_idx = LPC_EMAC->RxConsumeIndex; + } else { + while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && ((uint32_t)receive_idx != LPC_EMAC->RxProduceIndex)) { + receive_idx = rinc(receive_idx, NUM_RX_FRAG); + } + unsigned int info = rxstat[receive_idx].Info; + int slen = (info & RINFO_SIZE) + 1; + + if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) { + /* Invalid frame, ignore it and free buffer. */ + receive_idx = rinc(receive_idx, NUM_RX_FRAG); + } + receive_idx = rinc(receive_idx, NUM_RX_FRAG); + receive_soff = 0; + + LPC_EMAC->RxConsumeIndex = receive_idx; + } + + if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex) { + receive_idx = -1; + return 0; + } + + return (rxstat[receive_idx].Info & RINFO_SIZE) - 3; +#endif +} + +// Read from an recevied ethernet packet. +// After receive returnd a number bigger than 0 it is +// possible to read bytes from this packet. +// Read will write up to size bytes into data. +// It is possible to use read multible times. +// Each time read will start reading after the last read byte before. + +int ethernet_read(char *data, int dlen) { +#if NEW_LOGIC + // Check we have a valid buffer to read + if(rx_consume_offset < 0) { + return 0; + } + + // Assume 1 fragment block + uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info; + int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum + + int remaining = size - rx_consume_offset; + int requested = dlen; + int ncopy = min(remaining, requested); + + void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset); + void *pdst = (void *)(data); + + if(data != NULL && ncopy > 0) { + memcpy(pdst, psrc, ncopy); + } + + rx_consume_offset += ncopy; + + return ncopy; +#else + int slen; + int copy = 0; + unsigned int more; + unsigned int info; + void *pdst, *psrc; + int doff = 0; + + if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) { + return 0; + } + + do { + info = rxstat[receive_idx].Info; + more = !(info & RINFO_LAST_FLAG); + slen = (info & RINFO_SIZE) + 1; + + if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) { + /* Invalid frame, ignore it and free buffer. */ + receive_idx = rinc(receive_idx, NUM_RX_FRAG); + } else { + + copy = min(slen - receive_soff, dlen - doff); + psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff); + pdst = (void *)(data + doff); + + if(data != NULL) { + /* check if Buffer available */ + memcpy(pdst, psrc, copy); + } + + receive_soff += copy; + doff += copy; + + if((more && (receive_soff == slen))) { + receive_idx = rinc(receive_idx, NUM_RX_FRAG); + receive_soff = 0; + } + } + } while(more && !(doff == dlen) && !receive_soff); + + return doff; +#endif +} + +int ethernet_link(void) { + if (phy_id == DP83848C_ID) { + return (phy_read(PHY_REG_STS) & PHY_STS_LINK); + } + else { // LAN8720_ID + return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK); + } +} + +static int phy_write(unsigned int PhyReg, unsigned short Data) { + unsigned int timeOut; + + LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; + LPC_EMAC->MWTD = Data; + + for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) { /* Wait until operation completed */ + if((LPC_EMAC->MIND & MIND_BUSY) == 0) { + return 0; + } + } + + return -1; +} + +static int phy_read(unsigned int PhyReg) { + unsigned int timeOut; + + LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; + LPC_EMAC->MCMD = MCMD_READ; + + for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) { /* Wait until operation completed */ + if((LPC_EMAC->MIND & MIND_BUSY) == 0) { + LPC_EMAC->MCMD = 0; + return LPC_EMAC->MRDD; /* Return a 16-bit value. */ + } + } + + return -1; +} + + +static void txdscr_init() { + int i; + + for(i = 0; i < NUM_TX_FRAG; i++) { + txdesc[i].Packet = (uint32_t)&txbuf[i]; + txdesc[i].Ctrl = 0; + txstat[i].Info = 0; + } + + LPC_EMAC->TxDescriptor = (uint32_t)txdesc; /* Set EMAC Transmit Descriptor Registers. */ + LPC_EMAC->TxStatus = (uint32_t)txstat; + LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1; + + LPC_EMAC->TxProduceIndex = 0; /* Tx Descriptors Point to 0 */ +} + +static void rxdscr_init() { + int i; + + for(i = 0; i < NUM_RX_FRAG; i++) { + rxdesc[i].Packet = (uint32_t)&rxbuf[i]; + rxdesc[i].Ctrl = RCTRL_INT | (ETH_FRAG_SIZE-1); + rxstat[i].Info = 0; + rxstat[i].HashCRC = 0; + } + + LPC_EMAC->RxDescriptor = (uint32_t)rxdesc; /* Set EMAC Receive Descriptor Registers. */ + LPC_EMAC->RxStatus = (uint32_t)rxstat; + LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1; + + LPC_EMAC->RxConsumeIndex = 0; /* Rx Descriptors Point to 0 */ +} + +void ethernet_address(char *mac) { + mbed_mac_address(mac); +} + +void ethernet_set_link(int speed, int duplex) { + unsigned short phy_data; + int tout; + + if((speed < 0) || (speed > 1)) { + phy_data = PHY_AUTO_NEG; + } else { + phy_data = (((unsigned short) speed << 13) | + ((unsigned short) duplex << 8)); + } + + phy_write(PHY_REG_BMCR, phy_data); + + for(tout = 100; tout; tout--) { __NOP(); } /* A short delay */ + + switch(phy_id) { + case DP83848C_ID: + phy_data = phy_read(PHY_REG_STS); + + if(phy_data & PHY_STS_DUPLEX) { + LPC_EMAC->MAC2 |= MAC2_FULL_DUP; + LPC_EMAC->Command |= CR_FULL_DUP; + LPC_EMAC->IPGT = IPGT_FULL_DUP; + } else { + LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP; + LPC_EMAC->Command &= ~CR_FULL_DUP; + LPC_EMAC->IPGT = IPGT_HALF_DUP; + } + + if(phy_data & PHY_STS_SPEED) { + LPC_EMAC->SUPP &= ~SUPP_SPEED; + } else { + LPC_EMAC->SUPP |= SUPP_SPEED; + } + break; + + case LAN8720_ID: + phy_data = phy_read(PHY_REG_SCSR); + + if (phy_data & PHY_SCSR_DUPLEX) { + LPC_EMAC->MAC2 |= MAC2_FULL_DUP; + LPC_EMAC->Command |= CR_FULL_DUP; + LPC_EMAC->IPGT = IPGT_FULL_DUP; + } else { + LPC_EMAC->Command &= ~CR_FULL_DUP; + LPC_EMAC->IPGT = IPGT_HALF_DUP; + } + + if(phy_data & PHY_SCSR_100MBIT) { + LPC_EMAC->SUPP |= SUPP_SPEED; + } else { + LPC_EMAC->SUPP &= ~SUPP_SPEED; + } + break; + } +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_api.c new file mode 100644 index 0000000000..fd9c29b528 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_api.c @@ -0,0 +1,54 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "gpio_api.h" +#include "pinmap.h" + +uint32_t gpio_set(PinName pin) { + LPC_SC->SCS |= 1; // High speed GPIO is enabled on ports 0 and 1 + + pin_function(pin, 0); + + return (1 << ((int)pin & 0x1F)); +} + +void gpio_init(gpio_t *obj, PinName pin) { + if (pin == (PinName)NC) + return; + obj->pin = pin; + obj->mask = gpio_set(pin); + + LPC_GPIO_TypeDef *port_reg = (LPC_GPIO_TypeDef *) ((int)pin & ~0x1F); + + obj->reg_set = &port_reg->FIOSET; + obj->reg_mask = &port_reg->FIOMASK; + obj->reg_clr = &port_reg->FIOCLR; + obj->reg_in = &port_reg->FIOPIN; + obj->reg_dir = &port_reg->FIODIR; +} + +void gpio_mode(gpio_t *obj, PinMode mode) { + pin_mode(obj->pin, mode); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) { + if (obj->pin == (PinName)NC) + return; + switch (direction) { + case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break; + case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; + } +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_irq_api.c new file mode 100644 index 0000000000..40fcaa6dbe --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_irq_api.c @@ -0,0 +1,154 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_irq_api.h" +#include "mbed_error.h" +#include +#include "cmsis.h" + +#define CHANNEL_NUM 48 + +static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static gpio_irq_handler irq_handler; + +static void handle_interrupt_in(void) { + // Read in all current interrupt registers. We do this once as the + // GPIO interrupt registers are on the APB bus, and this is slow. + uint32_t rise0 = LPC_GPIOINT->IO0IntStatR; + uint32_t fall0 = LPC_GPIOINT->IO0IntStatF; + uint32_t rise2 = LPC_GPIOINT->IO2IntStatR; + uint32_t fall2 = LPC_GPIOINT->IO2IntStatF; + uint32_t mask0 = 0; + uint32_t mask2 = 0; + int i; + + // P0.0-0.31 + for (i = 0; i < 32; i++) { + uint32_t pmask = (1 << i); + if (rise0 & pmask) { + mask0 |= pmask; + if (channel_ids[i] != 0) + irq_handler(channel_ids[i], IRQ_RISE); + } + if (fall0 & pmask) { + mask0 |= pmask; + if (channel_ids[i] != 0) + irq_handler(channel_ids[i], IRQ_FALL); + } + } + + // P2.0-2.15 + for (i = 0; i < 16; i++) { + uint32_t pmask = (1 << i); + int channel_index = i + 32; + if (rise2 & pmask) { + mask2 |= pmask; + if (channel_ids[channel_index] != 0) + irq_handler(channel_ids[channel_index], IRQ_RISE); + } + if (fall2 & pmask) { + mask2 |= pmask; + if (channel_ids[channel_index] != 0) + irq_handler(channel_ids[channel_index], IRQ_FALL); + } + } + + // Clear the interrupts we just handled + LPC_GPIOINT->IO0IntClr = mask0; + LPC_GPIOINT->IO2IntClr = mask2; +} + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { + if (pin == NC) return -1; + + irq_handler = handler; + + obj->port = (int)pin & ~0x1F; + obj->pin = (int)pin & 0x1F; + + // Interrupts available only on GPIO0 and GPIO2 + if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) { + error("pins on this port cannot generate interrupts"); + } + + // put us in the interrupt table + int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32; + channel_ids[index] = id; + obj->ch = index; + + NVIC_SetVector(EINT3_IRQn, (uint32_t)handle_interrupt_in); + NVIC_EnableIRQ(EINT3_IRQn); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) { + channel_ids[obj->ch] = 0; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { + // ensure nothing is pending + switch (obj->port) { + case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break; + case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break; + } + + // enable the pin interrupt + if (event == IRQ_RISE) { + switch (obj->port) { + case LPC_GPIO0_BASE: + if (enable) { + LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin; + } else { + LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin); + } + break; + case LPC_GPIO2_BASE: + if (enable) { + LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin; + } else { + LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin); + } + break; + } + } else { + switch (obj->port) { + case LPC_GPIO0_BASE: + if (enable) { + LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin; + } else { + LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin); + } + break; + + case LPC_GPIO2_BASE: + if (enable) { + LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin; + } else { + LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin); + } + break; + } + } +} + +void gpio_irq_enable(gpio_irq_t *obj) { + NVIC_EnableIRQ(EINT3_IRQn); +} + +void gpio_irq_disable(gpio_irq_t *obj) { + NVIC_DisableIRQ(EINT3_IRQn); +} + diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_object.h new file mode 100644 index 0000000000..f149950b16 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_object.h @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; + uint32_t mask; + + __IO uint32_t *reg_dir; + __IO uint32_t *reg_mask; + __IO uint32_t *reg_set; + __IO uint32_t *reg_clr; + __I uint32_t *reg_in; +} gpio_t; + +static inline void gpio_write(gpio_t *obj, int value) { + MBED_ASSERT(obj->pin != (PinName)NC); + *obj->reg_mask &= ~obj->mask; + if (value) + *obj->reg_set = obj->mask; + else + *obj->reg_clr = obj->mask; +} + +static inline int gpio_read(gpio_t *obj) { + MBED_ASSERT(obj->pin != (PinName)NC); + *obj->reg_mask &= ~obj->mask; + return ((*obj->reg_in & obj->mask) ? 1 : 0); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/i2c_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/i2c_api.c new file mode 100644 index 0000000000..f4bceb4969 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/i2c_api.c @@ -0,0 +1,393 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "i2c_api.h" +#include "cmsis.h" +#include "pinmap.h" + +static const PinMap PinMap_I2C_SDA[] = { + {P0_0 , I2C_1, 3}, + {P0_10, I2C_2, 2}, + {P0_19, I2C_1, 3}, + {P0_27, I2C_0, 1}, + {NC , NC , 0} +}; + +static const PinMap PinMap_I2C_SCL[] = { + {P0_1 , I2C_1, 3}, + {P0_11, I2C_2, 2}, + {P0_20, I2C_1, 3}, + {P0_28, I2C_0, 1}, + {NC , NC, 0} +}; + +#define I2C_CONSET(x) (x->i2c->I2CONSET) +#define I2C_CONCLR(x) (x->i2c->I2CONCLR) +#define I2C_STAT(x) (x->i2c->I2STAT) +#define I2C_DAT(x) (x->i2c->I2DAT) +#define I2C_SCLL(x, val) (x->i2c->I2SCLL = val) +#define I2C_SCLH(x, val) (x->i2c->I2SCLH = val) + +static const uint32_t I2C_addr_offset[2][4] = { + {0x0C, 0x20, 0x24, 0x28}, + {0x30, 0x34, 0x38, 0x3C} +}; + +static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) { + I2C_CONCLR(obj) = (start << 5) + | (stop << 4) + | (interrupt << 3) + | (acknowledge << 2); +} + +static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) { + I2C_CONSET(obj) = (start << 5) + | (stop << 4) + | (interrupt << 3) + | (acknowledge << 2); +} + +// Clear the Serial Interrupt (SI) +static inline void i2c_clear_SI(i2c_t *obj) { + i2c_conclr(obj, 0, 0, 1, 0); +} + +static inline int i2c_status(i2c_t *obj) { + return I2C_STAT(obj); +} + +// Wait until the Serial Interrupt (SI) is set +static int i2c_wait_SI(i2c_t *obj) { + int timeout = 0; + while (!(I2C_CONSET(obj) & (1 << 3))) { + timeout++; + if (timeout > 100000) return -1; + } + return 0; +} + +static inline void i2c_interface_enable(i2c_t *obj) { + I2C_CONSET(obj) = 0x40; +} + +static inline void i2c_power_enable(i2c_t *obj) { + switch ((int)obj->i2c) { + case I2C_0: LPC_SC->PCONP |= 1 << 7; break; + case I2C_1: LPC_SC->PCONP |= 1 << 19; break; + case I2C_2: LPC_SC->PCONP |= 1 << 26; break; + } +} + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) { + // determine the SPI to use + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)obj->i2c != NC); + + // enable power + i2c_power_enable(obj); + + // set default frequency at 100k + i2c_frequency(obj, 100000); + i2c_conclr(obj, 1, 1, 1, 1); + i2c_interface_enable(obj); + + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); +} + +inline int i2c_start(i2c_t *obj) { + int status = 0; + // 8.1 Before master mode can be entered, I2CON must be initialised to: + // - I2EN STA STO SI AA - - + // - 1 0 0 0 x - - + // if AA = 0, it can't enter slave mode + i2c_conclr(obj, 1, 1, 1, 1); + + // The master mode may now be entered by setting the STA bit + // this will generate a start condition when the bus becomes free + i2c_conset(obj, 1, 0, 0, 1); + + i2c_wait_SI(obj); + status = i2c_status(obj); + + // Clear start bit now transmitted, and interrupt bit + i2c_conclr(obj, 1, 0, 0, 0); + return status; +} + +inline int i2c_stop(i2c_t *obj) { + int timeout = 0; + + // write the stop bit + i2c_conset(obj, 0, 1, 0, 0); + i2c_clear_SI(obj); + + // wait for STO bit to reset + while (I2C_CONSET(obj) & (1 << 4)) { + timeout ++; + if (timeout > 100000) return 1; + } + + return 0; +} + +static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) { + // write the data + I2C_DAT(obj) = value; + + // clear SI to init a send + i2c_clear_SI(obj); + + // wait and return status + i2c_wait_SI(obj); + return i2c_status(obj); +} + +static inline int i2c_do_read(i2c_t *obj, int last) { + // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack) + if (last) { + i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK + } else { + i2c_conset(obj, 0, 0, 0, 1); // send a ACK + } + + // accept byte + i2c_clear_SI(obj); + + // wait for it to arrive + i2c_wait_SI(obj); + + // return the data + return (I2C_DAT(obj) & 0xFF); +} + +void i2c_frequency(i2c_t *obj, int hz) { + // [TODO] set pclk to /4 + uint32_t PCLK = SystemCoreClock / 4; + + uint32_t pulse = PCLK / (hz * 2); + + // I2C Rate + I2C_SCLL(obj, pulse); + I2C_SCLH(obj, pulse); +} + +// The I2C does a read or a write as a whole operation +// There are two types of error conditions it can encounter +// 1) it can not obtain the bus +// 2) it gets error responses at part of the transmission +// +// We tackle them as follows: +// 1) we retry until we get the bus. we could have a "timeout" if we can not get it +// which basically turns it in to a 2) +// 2) on error, we use the standard error mechanisms to report/debug +// +// Therefore an I2C transaction should always complete. If it doesn't it is usually +// because something is setup wrong (e.g. wiring), and we don't need to programatically +// check for that +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { + int count, status; + + status = i2c_start(obj); + + if ((status != 0x10) && (status != 0x08)) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + + status = i2c_do_write(obj, (address | 0x01), 1); + if (status != 0x40) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + // Read in all except last byte + for (count = 0; count < (length - 1); count++) { + int value = i2c_do_read(obj, 0); + status = i2c_status(obj); + if (status != 0x50) { + i2c_stop(obj); + return count; + } + data[count] = (char) value; + } + + // read in last byte + int value = i2c_do_read(obj, 1); + status = i2c_status(obj); + if (status != 0x58) { + i2c_stop(obj); + return length - 1; + } + + data[count] = (char) value; + + // If not repeated start, send stop. + if (stop) { + i2c_stop(obj); + } + + return length; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { + int i, status; + + status = i2c_start(obj); + + if ((status != 0x10) && (status != 0x08)) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + + status = i2c_do_write(obj, (address & 0xFE), 1); + if (status != 0x18) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + for (i=0; i= 0) && (idx <= 3)) { + addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx]; + *((uint32_t *) addr) = address & 0xFF; + } +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/objects.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/objects.h new file mode 100644 index 0000000000..41d717adc6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/objects.h @@ -0,0 +1,78 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + uint32_t port; + uint32_t pin; + uint32_t ch; +}; + +struct port_s { + __IO uint32_t *reg_dir; + __IO uint32_t *reg_out; + __I uint32_t *reg_in; + PortName port; + uint32_t mask; +}; + +struct pwmout_s { + __IO uint32_t *MR; + PWMName pwm; +}; + +struct serial_s { + LPC_UART_TypeDef *uart; + int index; +}; + +struct analogin_s { + ADCName adc; +}; + +struct dac_s { + DACName dac; +}; + +struct can_s { + LPC_CAN_TypeDef *dev; +}; + +struct i2c_s { + LPC_I2C_TypeDef *i2c; +}; + +struct spi_s { + LPC_SSP_TypeDef *spi; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/pinmap.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/pinmap.c new file mode 100644 index 0000000000..12636f5d69 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/pinmap.c @@ -0,0 +1,46 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pinmap.h" +#include "mbed_error.h" + +void pin_function(PinName pin, int function) { + MBED_ASSERT(pin != (PinName)NC); + + uint32_t pin_number = (uint32_t)pin - (uint32_t)P0_0; + int index = pin_number >> 4; + int offset = (pin_number & 0xF) << 1; + + PINCONARRAY->PINSEL[index] &= ~(0x3 << offset); + PINCONARRAY->PINSEL[index] |= function << offset; +} + +void pin_mode(PinName pin, PinMode mode) { + MBED_ASSERT((pin != (PinName)NC) && (mode != OpenDrain)); + + uint32_t pin_number = (uint32_t)pin - (uint32_t)P0_0; + int index = pin_number >> 5; + int offset = pin_number & 0x1F; + uint32_t drain = ((uint32_t) mode & (uint32_t) OpenDrain) >> 2; + + if (!drain) { + index = pin_number >> 4; + offset = (pin_number & 0xF) << 1; + + PINCONARRAY->PINMODE[index] &= ~(0x3 << offset); + PINCONARRAY->PINMODE[index] |= (uint32_t)mode << offset; + } +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/port_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/port_api.c new file mode 100644 index 0000000000..2a84a3ffc4 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/port_api.c @@ -0,0 +1,71 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" +#include "pinmap.h" +#include "gpio_api.h" + +PinName port_pin(PortName port, int pin_n) { + return (PinName)(LPC_GPIO0_BASE + ((port << PORT_SHIFT) | pin_n)); +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { + obj->port = port; + obj->mask = mask; + + LPC_GPIO_TypeDef *port_reg = (LPC_GPIO_TypeDef *)(LPC_GPIO0_BASE + ((int)port * 0x20)); + + // Do not use masking, because it prevents the use of the unmasked pins + // port_reg->FIOMASK = ~mask; + + obj->reg_out = &port_reg->FIOPIN; + obj->reg_in = &port_reg->FIOPIN; + obj->reg_dir = &port_reg->FIODIR; + + uint32_t i; + // The function is set per pin: reuse gpio logic + for (i=0; i<32; i++) { + if (obj->mask & (1<port, i)); + } + } + + port_dir(obj, dir); +} + +void port_mode(port_t *obj, PinMode mode) { + uint32_t i; + // The mode is set per pin: reuse pinmap logic + for (i=0; i<32; i++) { + if (obj->mask & (1<port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) { + switch (dir) { + case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break; + case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; + } +} + +void port_write(port_t *obj, int value) { + *obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask); +} + +int port_read(port_t *obj) { + return (*obj->reg_in & obj->mask); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/pwmout_api.c new file mode 100644 index 0000000000..3773d7e6b7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/pwmout_api.c @@ -0,0 +1,171 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pwmout_api.h" +#include "cmsis.h" +#include "pinmap.h" + +#define TCR_CNT_EN 0x00000001 +#define TCR_RESET 0x00000002 + +// PORT ID, PWM ID, Pin function +static const PinMap PinMap_PWM[] = { + {P1_18, PWM_1, 2}, + {P1_20, PWM_2, 2}, + {P1_21, PWM_3, 2}, + {P1_23, PWM_4, 2}, + {P1_24, PWM_5, 2}, + {P1_26, PWM_6, 2}, + {P2_0 , PWM_1, 1}, + {P2_1 , PWM_2, 1}, + {P2_2 , PWM_3, 1}, + {P2_3 , PWM_4, 1}, + {P2_4 , PWM_5, 1}, + {P2_5 , PWM_6, 1}, + {P3_25, PWM_2, 3}, + {P3_26, PWM_3, 3}, + {NC, NC, 0} +}; + +__IO uint32_t *PWM_MATCH[] = { + &(LPC_PWM1->MR0), + &(LPC_PWM1->MR1), + &(LPC_PWM1->MR2), + &(LPC_PWM1->MR3), + &(LPC_PWM1->MR4), + &(LPC_PWM1->MR5), + &(LPC_PWM1->MR6) +}; + +#define TCR_PWM_EN 0x00000008 + +static unsigned int pwm_clock_mhz; + +void pwmout_init(pwmout_t* obj, PinName pin) { + // determine the channel + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + MBED_ASSERT(pwm != (PWMName)NC); + + obj->pwm = pwm; + obj->MR = PWM_MATCH[pwm]; + + // ensure the power is on + LPC_SC->PCONP |= 1 << 6; + + // ensure clock to /4 + LPC_SC->PCLKSEL0 &= ~(0x3 << 12); // pclk = /4 + LPC_PWM1->PR = 0; // no pre-scale + + // ensure single PWM mode + LPC_PWM1->MCR = 1 << 1; // reset TC on match 0 + + // enable the specific PWM output + LPC_PWM1->PCR |= 1 << (8 + pwm); + + pwm_clock_mhz = SystemCoreClock / 4000000; + + // default to 20ms: standard for servos, and fine for e.g. brightness control + pwmout_period_ms(obj, 20); + pwmout_write (obj, 0); + + // Wire pinout + pinmap_pinout(pin, PinMap_PWM); +} + +void pwmout_free(pwmout_t* obj) { + // [TODO] +} + +void pwmout_write(pwmout_t* obj, float value) { + if (value < 0.0f) { + value = 0.0; + } else if (value > 1.0f) { + value = 1.0; + } + + // set channel match to percentage + uint32_t v = (uint32_t)((float)(LPC_PWM1->MR0) * value); + + // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout + if (v == LPC_PWM1->MR0) { + v++; + } + + *obj->MR = v; + + // accept on next period start + LPC_PWM1->LER |= 1 << obj->pwm; +} + +float pwmout_read(pwmout_t* obj) { + float v = (float)(*obj->MR) / (float)(LPC_PWM1->MR0); + return (v > 1.0f) ? (1.0f) : (v); +} + +void pwmout_period(pwmout_t* obj, float seconds) { + pwmout_period_us(obj, seconds * 1000000.0f); +} + +void pwmout_period_ms(pwmout_t* obj, int ms) { + pwmout_period_us(obj, ms * 1000); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t* obj, int us) { + // calculate number of ticks + uint32_t ticks = pwm_clock_mhz * us; + + // set reset + LPC_PWM1->TCR = TCR_RESET; + + // set the global match register + LPC_PWM1->MR0 = ticks; + + // Scale the pulse width to preserve the duty ratio + if (LPC_PWM1->MR0 > 0) { + *obj->MR = (*obj->MR * ticks) / LPC_PWM1->MR0; + } + + // set the channel latch to update value at next period start + LPC_PWM1->LER |= 1 << 0; + + // enable counter and pwm, clear reset + LPC_PWM1->TCR = TCR_CNT_EN | TCR_PWM_EN; +} + +void pwmout_pulsewidth(pwmout_t* obj, float seconds) { + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t* obj, int us) { + // calculate number of ticks + uint32_t v = pwm_clock_mhz * us; + + // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout + if (v == LPC_PWM1->MR0) { + v++; + } + + // set the match register value + *obj->MR = v; + + // set the channel latch to update value at next period start + LPC_PWM1->LER |= 1 << obj->pwm; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/rtc_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/rtc_api.c new file mode 100644 index 0000000000..a4e7b96a61 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/rtc_api.c @@ -0,0 +1,117 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "rtc_api.h" + +// ensure rtc is running (unchanged if already running) + +/* Setup the RTC based on a time structure, ensuring RTC is enabled + * + * Can be clocked by a 32.768KHz oscillator or prescale divider based on the APB clock + * - We want to use the 32khz clock, allowing for sleep mode + * + * Most registers are not changed by a Reset + * - We must initialize these registers between power-on and setting the RTC into operation + + * Clock Control Register + * RTC_CCR[0] : Enable - 0 = Disabled, 1 = Enabled + * RTC_CCR[1] : Reset - 0 = Normal, 1 = Reset + * RTC_CCR[4] : Clock Source - 0 = Prescaler, 1 = 32k Xtal + * + * The RTC may already be running, so we should set it up + * without impacting if it is the case + */ +void rtc_init(void) { + LPC_SC->PCONP |= 0x200; // Ensure power is on + LPC_RTC->CCR = 0x00; + + // clock source on 2368 is special test mode on 1768! + LPC_RTC->CCR |= 1 << 4; // Ensure clock source is 32KHz Xtal + + LPC_RTC->CCR |= 1 << 0; // Ensure the RTC is enabled +} + +void rtc_free(void) { + // [TODO] +} + +/* + * Little check routine to see if the RTC has been enabled + * + * Clock Control Register + * RTC_CCR[0] : 0 = Disabled, 1 = Enabled + * + */ + +int rtc_isenabled(void) { + return(((LPC_RTC->CCR) & 0x01) != 0); +} + +/* + * RTC Registers + * RTC_SEC Seconds 0-59 + * RTC_MIN Minutes 0-59 + * RTC_HOUR Hour 0-23 + * RTC_DOM Day of Month 1-28..31 + * RTC_DOW Day of Week 0-6 + * RTC_DOY Day of Year 1-365 + * RTC_MONTH Month 1-12 + * RTC_YEAR Year 0-4095 + * + * struct tm + * tm_sec seconds after the minute 0-61 + * tm_min minutes after the hour 0-59 + * tm_hour hours since midnight 0-23 + * tm_mday day of the month 1-31 + * tm_mon months since January 0-11 + * tm_year years since 1900 + * tm_wday days since Sunday 0-6 + * tm_yday days since January 1 0-365 + * tm_isdst Daylight Saving Time flag + */ +time_t rtc_read(void) { + // Setup a tm structure based on the RTC + struct tm timeinfo; + timeinfo.tm_sec = LPC_RTC->SEC; + timeinfo.tm_min = LPC_RTC->MIN; + timeinfo.tm_hour = LPC_RTC->HOUR; + timeinfo.tm_mday = LPC_RTC->DOM; + timeinfo.tm_mon = LPC_RTC->MONTH - 1; + timeinfo.tm_year = LPC_RTC->YEAR - 1900; + + // Convert to timestamp + time_t t = mktime(&timeinfo); + + return t; +} + +void rtc_write(time_t t) { + // Convert the time in to a tm + struct tm *timeinfo = localtime(&t); + + // Pause clock, and clear counter register (clears us count) + LPC_RTC->CCR |= 2; + + // Set the RTC + LPC_RTC->SEC = timeinfo->tm_sec; + LPC_RTC->MIN = timeinfo->tm_min; + LPC_RTC->HOUR = timeinfo->tm_hour; + LPC_RTC->DOM = timeinfo->tm_mday; + LPC_RTC->MONTH = timeinfo->tm_mon + 1; + LPC_RTC->YEAR = timeinfo->tm_year + 1900; + + // Restart clock + LPC_RTC->CCR &= ~((uint32_t)2); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/serial_api.c new file mode 100644 index 0000000000..8b233293f7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/serial_api.c @@ -0,0 +1,338 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// math.h required for floating point operations for baud rate calculation +#include "mbed_assert.h" +#include +#include +#include + +#include "serial_api.h" +#include "cmsis.h" +#include "pinmap.h" + +/****************************************************************************** + * INITIALIZATION + ******************************************************************************/ +#define UART_NUM 4 + +static const PinMap PinMap_UART_TX[] = { + {P0_0, UART_3, 2}, + {P0_2, UART_0, 1}, + {P0_10, UART_2, 1}, + {P0_15, UART_1, 1}, + {P0_25, UART_3, 3}, + {P2_0 , UART_1, 2}, + {P2_8 , UART_2, 2}, + {P4_28, UART_3, 3}, + {NC , NC , 0} +}; + +static const PinMap PinMap_UART_RX[] = { + {P0_1 , UART_3, 2}, + {P0_3 , UART_0, 1}, + {P0_11, UART_2, 1}, + {P0_16, UART_1, 1}, + {P0_26, UART_3, 3}, + {P2_1 , UART_1, 2}, + {P2_9 , UART_2, 2}, + {P4_29, UART_3, 3}, + {NC , NC , 0} +}; + +static uint32_t serial_irq_ids[UART_NUM] = {0}; +static uart_irq_handler irq_handler; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +void serial_init(serial_t *obj, PinName tx, PinName rx) { + int is_stdio_uart = 0; + + // determine the UART to use + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)uart != NC); + + obj->uart = (LPC_UART_TypeDef *)uart; + // enable power + switch (uart) { + case UART_0: LPC_SC->PCONP |= 1 << 3; break; + case UART_1: LPC_SC->PCONP |= 1 << 4; break; + case UART_2: LPC_SC->PCONP |= 1 << 24; break; + case UART_3: LPC_SC->PCONP |= 1 << 25; break; + } + + // enable fifos and default rx trigger level + obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled + | 0 << 1 // Rx Fifo Reset + | 0 << 2 // Tx Fifo Reset + | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars + + // disable irqs + obj->uart->IER = 0 << 0 // Rx Data available irq enable + | 0 << 1 // Tx Fifo empty irq enable + | 0 << 2; // Rx Line Status irq enable + + // set default baud rate and format + serial_baud (obj, 9600); + serial_format(obj, 8, ParityNone, 1); + + // pinout the chosen uart + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + // set rx/tx pins in PullUp mode + if (tx != NC) { + pin_mode(tx, PullUp); + } + if (rx != NC) { + pin_mode(rx, PullUp); + } + + switch (uart) { + case UART_0: obj->index = 0; break; + case UART_1: obj->index = 1; break; + case UART_2: obj->index = 2; break; + case UART_3: obj->index = 3; break; + } + + is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); + + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) { + serial_irq_ids[obj->index] = 0; +} + +// serial_baud +// set the baud rate, taking in to account the current SystemFrequency +void serial_baud(serial_t *obj, int baudrate) { + MBED_ASSERT((int)obj->uart <= UART_3); + // The LPC2300 and LPC1700 have a divider and a fractional divider to control the + // baud rate. The formula is: + // + // Baudrate = (1 / PCLK) * 16 * DL * (1 + DivAddVal / MulVal) + // where: + // 1 < MulVal <= 15 + // 0 <= DivAddVal < 14 + // DivAddVal < MulVal + // + // set pclk to /1 + switch ((int)obj->uart) { + case UART_0: LPC_SC->PCLKSEL0 &= ~(0x3 << 6); LPC_SC->PCLKSEL0 |= (0x1 << 6); break; + case UART_1: LPC_SC->PCLKSEL0 &= ~(0x3 << 8); LPC_SC->PCLKSEL0 |= (0x1 << 8); break; + case UART_2: LPC_SC->PCLKSEL1 &= ~(0x3 << 16); LPC_SC->PCLKSEL1 |= (0x1 << 16); break; + case UART_3: LPC_SC->PCLKSEL1 &= ~(0x3 << 18); LPC_SC->PCLKSEL1 |= (0x1 << 18); break; + default: break; + } + + uint32_t PCLK = SystemCoreClock; + + // First we check to see if the basic divide with no DivAddVal/MulVal + // ratio gives us an integer result. If it does, we set DivAddVal = 0, + // MulVal = 1. Otherwise, we search the valid ratio value range to find + // the closest match. This could be more elegant, using search methods + // and/or lookup tables, but the brute force method is not that much + // slower, and is more maintainable. + uint16_t DL = PCLK / (16 * baudrate); + + uint8_t DivAddVal = 0; + uint8_t MulVal = 1; + int hit = 0; + uint16_t dlv; + uint8_t mv, dav; + if ((PCLK % (16 * baudrate)) != 0) { // Checking for zero remainder + int err_best = baudrate, b; + for (mv = 1; mv < 16 && !hit; mv++) + { + for (dav = 0; dav < mv; dav++) + { + // baudrate = PCLK / (16 * dlv * (1 + (DivAdd / Mul)) + // solving for dlv, we get dlv = mul * PCLK / (16 * baudrate * (divadd + mul)) + // mul has 4 bits, PCLK has 27 so we have 1 bit headroom which can be used for rounding + // for many values of mul and PCLK we have 2 or more bits of headroom which can be used to improve precision + // note: X / 32 doesn't round correctly. Instead, we use ((X / 16) + 1) / 2 for correct rounding + + if ((mv * PCLK * 2) & 0x80000000) // 1 bit headroom + dlv = ((((2 * mv * PCLK) / (baudrate * (dav + mv))) / 16) + 1) / 2; + else // 2 bits headroom, use more precision + dlv = ((((4 * mv * PCLK) / (baudrate * (dav + mv))) / 32) + 1) / 2; + + // datasheet says if DLL==DLM==0, then 1 is used instead since divide by zero is ungood + if (dlv == 0) + dlv = 1; + + // datasheet says if dav > 0 then DL must be >= 2 + if ((dav > 0) && (dlv < 2)) + dlv = 2; + + // integer rearrangement of the baudrate equation (with rounding) + b = ((PCLK * mv / (dlv * (dav + mv) * 8)) + 1) / 2; + + // check to see how we went + b = abs(b - baudrate); + if (b < err_best) + { + err_best = b; + + DL = dlv; + MulVal = mv; + DivAddVal = dav; + + if (b == baudrate) + { + hit = 1; + break; + } + } + } + } + } + + // set LCR[DLAB] to enable writing to divider registers + obj->uart->LCR |= (1 << 7); + + // set divider values + obj->uart->DLM = (DL >> 8) & 0xFF; + obj->uart->DLL = (DL >> 0) & 0xFF; + obj->uart->FDR = (uint32_t) DivAddVal << 0 + | (uint32_t) MulVal << 4; + + // clear LCR[DLAB] + obj->uart->LCR &= ~(1 << 7); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits + MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || + (parity == ParityForced1) || (parity == ParityForced0)); + + stop_bits -= 1; + data_bits -= 5; + + int parity_enable = 0, parity_select = 0; + switch (parity) { + case ParityNone: parity_enable = 0; parity_select = 0; break; + case ParityOdd : parity_enable = 1; parity_select = 0; break; + case ParityEven: parity_enable = 1; parity_select = 1; break; + case ParityForced1: parity_enable = 1; parity_select = 2; break; + case ParityForced0: parity_enable = 1; parity_select = 3; break; + default: + break; + } + + obj->uart->LCR = data_bits << 0 + | stop_bits << 2 + | parity_enable << 3 + | parity_select << 4; +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ +static inline void uart_irq(uint32_t iir, uint32_t index) { + // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling + SerialIrq irq_type; + switch (iir) { + case 1: irq_type = TxIrq; break; + case 2: irq_type = RxIrq; break; + default: return; + } + + if (serial_irq_ids[index] != 0){ + irq_handler(serial_irq_ids[index], irq_type); + } +} + +void uart0_irq() {uart_irq((LPC_UART0->IIR >> 1) & 0x7, 0);} +void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1);} +void uart2_irq() {uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2);} +void uart3_irq() {uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3);} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { + IRQn_Type irq_n = (IRQn_Type)0; + uint32_t vector = 0; + switch ((int)obj->uart) { + case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break; + case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break; + case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break; + case UART_3: irq_n=UART3_IRQn; vector = (uint32_t)&uart3_irq; break; + } + + if (enable) { + obj->uart->IER |= 1 << irq; + NVIC_SetVector(irq_n, vector); + NVIC_EnableIRQ(irq_n); + } else { // disable + int all_disabled = 0; + SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); + obj->uart->IER &= ~(1 << irq); + all_disabled = (obj->uart->IER & (1 << other_irq)) == 0; + if (all_disabled) + NVIC_DisableIRQ(irq_n); + } +} + +/****************************************************************************** + * READ/WRITE + ******************************************************************************/ +int serial_getc(serial_t *obj) { + while (!serial_readable(obj)); + return obj->uart->RBR; +} + +void serial_putc(serial_t *obj, int c) { + while (!serial_writable(obj)); + obj->uart->THR = c; +} + +int serial_readable(serial_t *obj) { + return obj->uart->LSR & 0x01; +} + +int serial_writable(serial_t *obj) { + return obj->uart->LSR & 0x20; +} + +void serial_clear(serial_t *obj) { + obj->uart->FCR = 1 << 1 // rx FIFO reset + | 1 << 2 // tx FIFO reset + | 0 << 6; // interrupt depth +} + +void serial_pinout_tx(PinName tx) { + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) { + obj->uart->LCR |= (1 << 6); +} + +void serial_break_clear(serial_t *obj) { + obj->uart->LCR &= ~(1 << 6); +} + diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/spi_api.c new file mode 100644 index 0000000000..b658769889 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/spi_api.c @@ -0,0 +1,219 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include + +#include "spi_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" + +static const PinMap PinMap_SPI_SCLK[] = { + {P0_7 , SPI_1, 2}, + {P0_15, SPI_0, 2}, + {P1_20, SPI_0, 3}, + {P1_31, SPI_1, 2}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MOSI[] = { + {P0_9 , SPI_1, 2}, + {P0_13, SPI_1, 2}, + {P0_18, SPI_0, 2}, + {P1_24, SPI_0, 3}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {P0_8 , SPI_1, 2}, + {P0_12, SPI_1, 2}, + {P0_17, SPI_0, 2}, + {P1_23, SPI_0, 3}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {P0_6 , SPI_1, 2}, + {P0_11, SPI_1, 2}, + {P0_16, SPI_0, 2}, + {P1_21, SPI_0, 3}, + {NC , NC , 0} +}; + +static inline int ssp_disable(spi_t *obj); +static inline int ssp_enable(spi_t *obj); + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { + // determine the SPI to use + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj->spi != NC); + + // enable power and clocking + switch ((int)obj->spi) { + case SPI_0: LPC_SC->PCONP |= 1 << 21; break; + case SPI_1: LPC_SC->PCONP |= 1 << 10; break; + } + + // set default format and frequency + if (ssel == NC) { + spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master + } else { + spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave + } + spi_frequency(obj, 1000000); + + // enable the ssp channel + ssp_enable(obj); + + // pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } +} + +void spi_free(spi_t *obj) {} + +void spi_format(spi_t *obj, int bits, int mode, int slave) { + MBED_ASSERT(((bits >= 4) && (bits <= 16)) && ((mode >= 0) && (mode <= 3))); + ssp_disable(obj); + + int polarity = (mode & 0x2) ? 1 : 0; + int phase = (mode & 0x1) ? 1 : 0; + + // set it up + int DSS = bits - 1; // DSS (data select size) + int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity + int SPH = (phase) ? 1 : 0; // SPH - clock out phase + + int FRF = 0; // FRF (frame format) = SPI + uint32_t tmp = obj->spi->CR0; + tmp &= ~(0xFFFF); + tmp |= DSS << 0 + | FRF << 4 + | SPO << 6 + | SPH << 7; + obj->spi->CR0 = tmp; + + tmp = obj->spi->CR1; + tmp &= ~(0xD); + tmp |= 0 << 0 // LBM - loop back mode - off + | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave + | 0 << 3; // SOD - slave output disable - na + obj->spi->CR1 = tmp; + + ssp_enable(obj); +} + +void spi_frequency(spi_t *obj, int hz) { + ssp_disable(obj); + + // setup the spi clock diveder to /1 + switch ((int)obj->spi) { + case SPI_0: + LPC_SC->PCLKSEL1 &= ~(3 << 10); + LPC_SC->PCLKSEL1 |= (1 << 10); + break; + case SPI_1: + LPC_SC->PCLKSEL0 &= ~(3 << 20); + LPC_SC->PCLKSEL0 |= (1 << 20); + break; + } + + uint32_t PCLK = SystemCoreClock; + + int prescaler; + + for (prescaler = 2; prescaler <= 254; prescaler += 2) { + int prescale_hz = PCLK / prescaler; + + // calculate the divider + int divider = floor(((float)prescale_hz / (float)hz) + 0.5f); + + // check we can support the divider + if (divider < 256) { + // prescaler + obj->spi->CPSR = prescaler; + + // divider + obj->spi->CR0 &= ~(0xFFFF << 8); + obj->spi->CR0 |= (divider - 1) << 8; + ssp_enable(obj); + return; + } + } + error("Couldn't setup requested SPI frequency"); +} + +static inline int ssp_disable(spi_t *obj) { + return obj->spi->CR1 &= ~(1 << 1); +} + +static inline int ssp_enable(spi_t *obj) { + return obj->spi->CR1 |= (1 << 1); +} + +static inline int ssp_readable(spi_t *obj) { + return obj->spi->SR & (1 << 2); +} + +static inline int ssp_writeable(spi_t *obj) { + return obj->spi->SR & (1 << 1); +} + +static inline void ssp_write(spi_t *obj, int value) { + while (!ssp_writeable(obj)); + obj->spi->DR = value; +} + +static inline int ssp_read(spi_t *obj) { + while (!ssp_readable(obj)); + return obj->spi->DR; +} + +static inline int ssp_busy(spi_t *obj) { + return (obj->spi->SR & (1 << 4)) ? (1) : (0); +} + +int spi_master_write(spi_t *obj, int value) { + ssp_write(obj, value); + return ssp_read(obj); +} + +int spi_slave_receive(spi_t *obj) { + return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); +} + +int spi_slave_read(spi_t *obj) { + return obj->spi->DR; +} + +void spi_slave_write(spi_t *obj, int value) { + while (ssp_writeable(obj) == 0) ; + obj->spi->DR = value; +} + +int spi_busy(spi_t *obj) { + return ssp_busy(obj); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/us_ticker.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/us_ticker.c new file mode 100644 index 0000000000..b46d75e6bc --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/us_ticker.c @@ -0,0 +1,64 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "us_ticker_api.h" +#include "PeripheralNames.h" + +#define US_TICKER_TIMER ((LPC_TIM_TypeDef *)LPC_TIM3_BASE) +#define US_TICKER_TIMER_IRQn TIMER3_IRQn + +int us_ticker_inited = 0; + +void us_ticker_init(void) { + if (us_ticker_inited) return; + us_ticker_inited = 1; + + LPC_SC->PCONP |= 1 << 23; // Clock TIMER_3 + + US_TICKER_TIMER->CTCR = 0x0; // timer mode + uint32_t PCLK = SystemCoreClock / 4; + + US_TICKER_TIMER->TCR = 0x2; // reset + + uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks) + US_TICKER_TIMER->PR = prescale - 1; + US_TICKER_TIMER->TCR = 1; // enable = 1, reset = 0 + + NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); +} + +uint32_t us_ticker_read() { + if (!us_ticker_inited) + us_ticker_init(); + + return US_TICKER_TIMER->TC; +} + +void us_ticker_set_interrupt(timestamp_t timestamp) { + // set match value + US_TICKER_TIMER->MR0 = (uint32_t)timestamp; + // enable match interrupt + US_TICKER_TIMER->MCR |= 1; +} + +void us_ticker_disable_interrupt(void) { + US_TICKER_TIMER->MCR &= ~1; +} + +void us_ticker_clear_interrupt(void) { + US_TICKER_TIMER->IR = 1; +} diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 5a1140d474..6b053a547f 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -1,3 +1,4 @@ +#! /usr/bin/env python """ mbed SDK Copyright (c) 2011-2013 ARM Limited @@ -32,6 +33,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('UBLOX_C027', ('ARM', 'GCC_ARM', 'GCC_CR', 'GCC_CS', 'IAR')), ('ARCH_PRO', ('ARM', 'GCC_ARM', 'GCC_CR', 'GCC_CS', 'IAR')), ('LPC2368', ('ARM', 'GCC_ARM')), + ('LPC2460', ('ARM', 'GCC_ARM')), ('LPC812', ('uARM','IAR')), ('LPC824', ('uARM',)), ('SSCI824', ('uARM',)), diff --git a/workspace_tools/export/gcc_arm_lpc2460.tmpl b/workspace_tools/export/gcc_arm_lpc2460.tmpl new file mode 100644 index 0000000000..98c466278f --- /dev/null +++ b/workspace_tools/export/gcc_arm_lpc2460.tmpl @@ -0,0 +1,72 @@ +# This file was automagically generated by mbed.org. For more information, +# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded + +GCC_BIN = +PROJECT = {{name}} +OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %} +SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %} +INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %} +LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %} +LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %} +LINKER_SCRIPT = {{linker_script}} + +############################################################################### +AS = $(GCC_BIN)arm-none-eabi-as +CC = $(GCC_BIN)arm-none-eabi-gcc +CPP = $(GCC_BIN)arm-none-eabi-g++ +LD = $(GCC_BIN)arm-none-eabi-gcc +OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy +OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump +SIZE = $(GCC_BIN)arm-none-eabi-size + +CPU = -mcpu=arm7tdmi-s +CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer +CC_FLAGS += -MMD -MP +CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %} + +LD_FLAGS = $(CPU) -Wl,--gc-sections --specs=nano.specs -u _printf_float -u _scanf_float -Wl,--wrap,main +LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref -Wl,--entry=_start +LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys + +ifeq ($(DEBUG), 1) + CC_FLAGS += -DDEBUG -O0 +else + CC_FLAGS += -DNDEBUG -Os +endif + +all: $(PROJECT).bin $(PROJECT).hex + +clean: + rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS) + +.s.o: + $(AS) $(CPU) -o $@ $< + +.c.o: + $(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $< + +.cpp.o: + $(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 -fno-rtti $(INCLUDE_PATHS) -o $@ $< + + +$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS) + $(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS) + $(SIZE) $@ + +$(PROJECT).bin: $(PROJECT).elf + @$(OBJCOPY) -O binary $< $@ + +$(PROJECT).hex: $(PROJECT).elf + @$(OBJCOPY) -O ihex $< $@ + +$(PROJECT).lst: $(PROJECT).elf + @$(OBJDUMP) -Sdh $< > $@ + +lst: $(PROJECT).lst + +size: + $(SIZE) $(PROJECT).elf + +DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d) +-include $(DEPS) + diff --git a/workspace_tools/export/gccarm.py b/workspace_tools/export/gccarm.py index a248c1e02e..ea4834dfb2 100644 --- a/workspace_tools/export/gccarm.py +++ b/workspace_tools/export/gccarm.py @@ -48,6 +48,7 @@ class GccArm(Exporter): 'NRF51822', 'HRM1017', 'LPC2368', + 'LPC2460', 'LPCCAPPUCCINO', 'ARCH_BLE', 'MTS_GAMBIT', diff --git a/workspace_tools/export_test.py b/workspace_tools/export_test.py index a711dc08e7..3c07a087b9 100755 --- a/workspace_tools/export_test.py +++ b/workspace_tools/export_test.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python """ mbed SDK Copyright (c) 2011-2013 ARM Limited @@ -26,7 +27,7 @@ from workspace_tools.utils import mkdir, cmd from workspace_tools.export import export, setup_user_prj -USR_PRJ_NAME = "usr_prj" +USR_PRJ_NAME = "myapp" USER_PRJ = join(EXPORT_WORKSPACE, USR_PRJ_NAME) USER_SRC = join(USER_PRJ, "src") @@ -74,8 +75,7 @@ def test_export(toolchain, target, expected_error=None): if __name__ == '__main__': setup_test_user_prj() - - for toolchain, target in [ + exportlist = [ ('emblocks', 'LPC1768'), ('emblocks', 'LPC1549'), ('emblocks', 'LPC1114'), @@ -147,6 +147,7 @@ if __name__ == '__main__': ('gcc_arm', 'LPC11U35_501'), ('gcc_arm', 'LPCCAPPUCCINO'), ('gcc_arm', 'LPC2368'), + ('gcc_arm', 'LPC2460'), ('gcc_arm', 'STM32F407'), ('gcc_arm', 'DISCO_F100RB'), @@ -179,10 +180,12 @@ if __name__ == '__main__': ('iar', 'STM32F407'), ('iar', 'MTS_MDOT_F405RG'), - (None, None), - ]: - print '\n=== Exporting to "%s::%s" ===' % (toolchain, target) - test_export(toolchain, target) + (None, None) ] +# print exportlist + test_export('gcc_arm', 'LPC2460') + for (toolchain, target) in exportlist : + print '\n=== Exporting to "%s::%s" ===' % (toolchain, target) + test_export(toolchain, target) print "\n=== Test error messages ===" test_export('lpcxpresso', 'LPC11U24', expected_error='lpcxpresso') diff --git a/workspace_tools/settings.py b/workspace_tools/settings.py index 3444f86ff0..cd0b83a7ff 100644 --- a/workspace_tools/settings.py +++ b/workspace_tools/settings.py @@ -39,7 +39,7 @@ if armcc == "keil": ARM_LIB = join(ARM_PATH, "RV31", "LIB") elif armcc == "standalone": - ARM_PATH = "C:/Program Files/ARM/armcc_4.1_791" + ARM_PATH = "/" ARM_BIN = join(ARM_PATH, "bin") ARM_INC = join(ARM_PATH, "include") ARM_LIB = join(ARM_PATH, "lib") diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 0749c6a891..48c1f3ce3b 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -217,6 +217,13 @@ class LPC2368(LPCTarget): self.extra_labels = ['NXP', 'LPC23XX'] self.supported_toolchains = ["ARM", "GCC_ARM", "GCC_CR"] +class LPC2460(LPCTarget): + def __init__(self): + LPCTarget.__init__(self) + self.core = "ARM7TDMI-S" + self.extra_labels = ['NXP', 'LPC2460'] + self.supported_toolchains = ["ARM", "GCC_ARM", "GCC_CR"] + class LPC810(LPCTarget): def __init__(self): LPCTarget.__init__(self) @@ -796,6 +803,7 @@ TARGETS = [ ARCH_PRO(), # LPC1768 UBLOX_C027(), # LPC1768 LPC2368(), + LPC2460(), LPC810(), LPC812(), LPC824(), From a523cb7da9b5c4b854bb14512e2c0013134f2444 Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Wed, 18 Feb 2015 19:07:41 +0400 Subject: [PATCH 002/139] Add support of RTOS to LPC2460 platform --- .../TOOLCHAIN_GCC_ARM/LPC2460.ld | 1 + .../TOOLCHAIN_GCC_ARM/vector_functions.s | 31 +- .../TARGET_NXP/TARGET_LPC2460/core_arm7.h | 81 +- .../TARGET_ARM7/ARM7/TOOLCHAIN_ARM/HAL_CM0.c | 301 +++ .../ARM7/TOOLCHAIN_ARM/SVC_Table.s | 57 + .../TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s | 342 +++ .../ARM7/TOOLCHAIN_GCC/SVC_Table.s | 56 + .../TARGET_ARM7/ARM7/TOOLCHAIN_IAR/HAL_CM0.s | 312 +++ .../ARM7/TOOLCHAIN_IAR/SVC_Table.s | 58 + libraries/rtos/rtx/TARGET_ARM7/HAL_CM.c | 161 ++ libraries/rtos/rtx/TARGET_ARM7/RTX_CM_lib.h | 467 +++++ libraries/rtos/rtx/TARGET_ARM7/RTX_Conf.h | 72 + libraries/rtos/rtx/TARGET_ARM7/RTX_Conf_CM.c | 293 +++ libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h | 774 +++++++ libraries/rtos/rtx/TARGET_ARM7/os_tcb.h | 54 + libraries/rtos/rtx/TARGET_ARM7/rt_CMSIS.c | 1852 +++++++++++++++++ libraries/rtos/rtx/TARGET_ARM7/rt_Event.c | 190 ++ libraries/rtos/rtx/TARGET_ARM7/rt_Event.h | 46 + libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h | 227 ++ libraries/rtos/rtx/TARGET_ARM7/rt_List.c | 320 +++ libraries/rtos/rtx/TARGET_ARM7/rt_List.h | 67 + libraries/rtos/rtx/TARGET_ARM7/rt_Mailbox.c | 292 +++ libraries/rtos/rtx/TARGET_ARM7/rt_Mailbox.h | 48 + libraries/rtos/rtx/TARGET_ARM7/rt_MemBox.c | 166 ++ libraries/rtos/rtx/TARGET_ARM7/rt_MemBox.h | 46 + libraries/rtos/rtx/TARGET_ARM7/rt_Mutex.c | 197 ++ libraries/rtos/rtx/TARGET_ARM7/rt_Mutex.h | 44 + libraries/rtos/rtx/TARGET_ARM7/rt_Robin.c | 84 + libraries/rtos/rtx/TARGET_ARM7/rt_Robin.h | 45 + libraries/rtos/rtx/TARGET_ARM7/rt_Semaphore.c | 183 ++ libraries/rtos/rtx/TARGET_ARM7/rt_Semaphore.h | 46 + libraries/rtos/rtx/TARGET_ARM7/rt_System.c | 293 +++ libraries/rtos/rtx/TARGET_ARM7/rt_System.h | 52 + libraries/rtos/rtx/TARGET_ARM7/rt_Task.c | 341 +++ libraries/rtos/rtx/TARGET_ARM7/rt_Task.h | 73 + libraries/rtos/rtx/TARGET_ARM7/rt_Time.c | 94 + libraries/rtos/rtx/TARGET_ARM7/rt_Time.h | 47 + libraries/rtos/rtx/TARGET_ARM7/rt_TypeDef.h | 128 ++ 38 files changed, 7928 insertions(+), 13 deletions(-) create mode 100644 libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_ARM/HAL_CM0.c create mode 100644 libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_ARM/SVC_Table.s create mode 100644 libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s create mode 100644 libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/SVC_Table.s create mode 100644 libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_IAR/HAL_CM0.s create mode 100644 libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_IAR/SVC_Table.s create mode 100644 libraries/rtos/rtx/TARGET_ARM7/HAL_CM.c create mode 100755 libraries/rtos/rtx/TARGET_ARM7/RTX_CM_lib.h create mode 100644 libraries/rtos/rtx/TARGET_ARM7/RTX_Conf.h create mode 100755 libraries/rtos/rtx/TARGET_ARM7/RTX_Conf_CM.c create mode 100644 libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h create mode 100644 libraries/rtos/rtx/TARGET_ARM7/os_tcb.h create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_CMSIS.c create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_Event.c create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_Event.h create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_List.c create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_List.h create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_Mailbox.c create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_Mailbox.h create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_MemBox.c create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_MemBox.h create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_Mutex.c create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_Mutex.h create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_Robin.c create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_Robin.h create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_Semaphore.c create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_Semaphore.h create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_System.c create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_System.h create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_Task.c create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_Task.h create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_Time.c create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_Time.h create mode 100644 libraries/rtos/rtx/TARGET_ARM7/rt_TypeDef.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/LPC2460.ld b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/LPC2460.ld index 257cd5971b..db36b39dcc 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/LPC2460.ld +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/LPC2460.ld @@ -28,6 +28,7 @@ __abt_stack_top__ = __und_stack_top__ - UND_Stack_Size ; __fiq_stack_top__ = __abt_stack_top__ - ABT_Stack_Size ; __irq_stack_top__ = __fiq_stack_top__ - FIQ_Stack_Size ; __svc_stack_top__ = __irq_stack_top__ - IRQ_Stack_Size ; +__usr_stack_top__ = __svc_stack_top__ - User_Stack_Size ; /* C-accessible symbols for memory address ranges: */ __FLASH_segment_start__ = ORIGIN( Flash ); diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_functions.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_functions.s index a2e3e1dda5..3c9a11a125 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_functions.s +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_functions.s @@ -15,6 +15,8 @@ .weak __mbed_dcc_irq .weak __mbed_reset .global __mbed_init_realmonitor +.extern SVC_Handler +.extern IRQ_Handler /* .global __mbed_init */ @@ -29,7 +31,8 @@ __mbed_prefetch_abort: __mbed_data_abort: LDR PC, =0x7fffffc0 __mbed_irq: - MSR CPSR_c, #0x1F|0x80|0x40 + B IRQ_Handler +/* MSR CPSR_c, #0x1F|0x80|0x40 STMDB sp!, {r0-r3,r12,lr} @@ -47,13 +50,16 @@ __mbed_irq: MSR CPSR_c, #0x12|0x80|0x40 SUBS pc, lr, #4 +*/ __mbed_swi: - STMFD sp!, {a4, r4, ip, lr} + B SVC_Handler +/* STMFD sp!, {a4, r4, ip, lr} LDR r4, =0x40000040 LDR a4, =0x00940000 LDR PC, =0x7ffff820 +*/ __mbed_dcc_irq: LDMFD sp!,{r0-r3,r12,lr} @@ -76,13 +82,24 @@ __mbed_dcc_irq: .global Reset_handler Reset_Handler: .extern __libc_init_array - .extern SystemInit + .extern SystemInit + .extern software_init_hook LDR R0, =SystemInit - MOV LR, PC + MOV LR, PC BX R0 +/* if (software_init_hook) // give control to the RTOS + software_init_hook(); // this will also call __libc_init_array +*/ + LDR R0, =software_init_hook + CMP R0, #0 + BEQ nortos + ORR R0,R0,#1 /* set thumb address */ + BX R0 +/* else */ +nortos: LDR R0, =__libc_init_array - MOV LR, PC + MOV LR, PC BX R0 MSR CPSR_c, #0x1F /* enable irq */ @@ -118,6 +135,8 @@ __mbed_reset: */ MSR CPSR_c, #0x1F|0x80|0x40 MOV SP, R0 + + MSR CPSR_c, #0x13|0x80|0x40 /* execute in Supervisor mode */ /* Relocate .data section (Copy from ROM to RAM) */ LDR R1, =__text_end__ /* _etext */ @@ -147,7 +166,7 @@ BSSIsEmpty: /* LDR R0, =__mbed_init_realmonitor MOV LR, PC BX R0 -/* +*/ /* Go to Reset_Handler */ LDR R0, =Reset_Handler diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/core_arm7.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/core_arm7.h index 9655813058..7994d320c2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/core_arm7.h +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/core_arm7.h @@ -9,16 +9,16 @@ #define __ARM7_CORE_H__ #include "vector_defns.h" - #ifdef __cplusplus extern "C" { #endif +//#include "cmsis_nvic.h" #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ -#define __CORTEX_M (0x03) /*!< Cortex core */ +#define __CORTEX_M (0x00) /*!< Cortex core */ /** * Lint configuration \n @@ -203,7 +203,7 @@ static __INLINE void __enable_irq() { : "memory"); } -static __INLINE void __disable_irq() { +static __INLINE uint32_t __disable_irq() { unsigned long old,temp; __asm__ __volatile__("mrs %0, cpsr\n" "orr %1, %0, #0xc0\n" @@ -211,11 +211,34 @@ static __INLINE void __disable_irq() { : "=r" (old), "=r" (temp) : : "memory"); - // return (old & 0x80) == 0; + return (old & 0x80) == 0; } static __INLINE void __NOP() { __ASM volatile ("nop"); } +/** \brief Get Control Bits of Status Register + + This function returns the content of the Control Bits from the Program Status Register. + + \return Control Bits value + */ +__attribute__( ( always_inline ) ) static inline uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __asm__ __volatile__ ("MRS %0, CPSR \n" + "AND %0,%0,#31" : "=r" (result) ); + return(result); +} +#define MODE_USER 0x10 +#define MODE_FIQ 0x11 +#define MODE_IRQ 0x12 +#define MODE_SUPERVISOR 0x13 +#define MODE_ABORT 0x17 +#define MODE_UNDEFINED 0x1B +#define MODE_SYSTEM 0x1F + + #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ /* TASKING carm specific functions */ @@ -237,7 +260,7 @@ static __INLINE void __NOP() { __ASM volatile ("nop"); } * Enable a device specific interupt in the NVIC interrupt controller. * The interrupt number cannot be a negative value. */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +static __INLINE void NVIC_EnableIRQ(uint32_t IRQn) { NVIC->IntEnable = 1 << (uint32_t)IRQn; } @@ -252,11 +275,55 @@ static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) * Disable a device specific interupt in the NVIC interrupt controller. * The interrupt number cannot be a negative value. */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) { NVIC->IntEnClr = 1 << (uint32_t)IRQn; } +/** + * @brief Pend Interrupt in NVIC Interrupt Controller + * + * @param IRQn_Type IRQn specifies the interrupt number + * @return none + * + * Force software a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_PendIRQ(uint32_t IRQn) +{ + NVIC->SoftInt = 1 << (uint32_t)IRQn; +} + + +/** + * @brief Unpend the interrupt in NVIC Interrupt Controller + * + * @param IRQn_Type IRQn is the positive number of the external interrupt + * @return none + * + * Clear software device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_UnpendIRQ(uint32_t IRQn) +{ + NVIC->SoftIntClr = 1 << (uint32_t)IRQn; +} + +/** + * @brief Is IRQ pending + * + * @param IRQn_Type IRQn is the positive number of the external interrupt + * @return 0 if IRQ is not pending + * 1 if IRQ is pending + * + * Returns software device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE uint32_t NVIC_Pending(uint32_t IRQn) +{ + return (NVIC->SoftInt & (1 << (uint32_t)IRQn)) != 0; +} + static __INLINE uint32_t __get_IPSR(void) { unsigned i; @@ -264,7 +331,7 @@ static __INLINE uint32_t __get_IPSR(void) for(i = 0; i < 32; i ++) if(NVIC->Address == NVIC->VectAddr[i]) return i; - return 1; // 1 is an invalid entry in the interrupt table on LPC2368 + return 1; // 1 is an invalid entry in the interrupt table on LPC2460 } #ifdef __cplusplus diff --git a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_ARM/HAL_CM0.c b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_ARM/HAL_CM0.c new file mode 100644 index 0000000000..492e94a197 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_ARM/HAL_CM0.c @@ -0,0 +1,301 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: HAL_CM0.C + * Purpose: Hardware Abstraction Layer for Cortex-M0 + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Conf.h" +#include "rt_System.h" +#include "rt_HAL_CM.h" +#include "rt_Task.h" +#include "rt_MemBox.h" + + +/*---------------------------------------------------------------------------- + * Functions + *---------------------------------------------------------------------------*/ + + +/*--------------------------- rt_set_PSP ------------------------------------*/ + +__asm void rt_set_PSP (U32 stack) { + MSR PSP,R0 + BX LR +} + + +/*--------------------------- rt_get_PSP ------------------------------------*/ + +__asm U32 rt_get_PSP (void) { + MRS R0,PSP + BX LR +} + + +/*--------------------------- os_set_env ------------------------------------*/ + +__asm void os_set_env (void) { + /* Switch to Unprivileged/Privileged Thread mode, use PSP. */ + MOV R0,SP ; PSP = MSP + MSR PSP,R0 + LDR R0,=__cpp(&os_flags) + LDRB R0,[R0] + LSLS R0,#31 + BNE PrivilegedE + MOVS R0,#0x03 ; Unprivileged Thread mode, use PSP + MSR CONTROL,R0 + BX LR +PrivilegedE + MOVS R0,#0x02 ; Privileged Thread mode, use PSP + MSR CONTROL,R0 + BX LR + + ALIGN +} + + +/*--------------------------- _alloc_box ------------------------------------*/ + +__asm void *_alloc_box (void *box_mem) { + /* Function wrapper for Unprivileged/Privileged mode. */ + LDR R3,=__cpp(rt_alloc_box) + MOV R12,R3 + MRS R3,IPSR + LSLS R3,#24 + BNE PrivilegedA + MRS R3,CONTROL + LSLS R3,#31 + BEQ PrivilegedA + SVC 0 + BX LR +PrivilegedA + BX R12 + + ALIGN +} + + +/*--------------------------- _free_box -------------------------------------*/ + +__asm int _free_box (void *box_mem, void *box) { + /* Function wrapper for Unprivileged/Privileged mode. */ + LDR R3,=__cpp(rt_free_box) + MOV R12,R3 + MRS R3,IPSR + LSLS R3,#24 + BNE PrivilegedF + MRS R3,CONTROL + LSLS R3,#31 + BEQ PrivilegedF + SVC 0 + BX LR +PrivilegedF + BX R12 + + ALIGN +} + + +/*-------------------------- SVC_Handler ------------------------------------*/ + +__asm void SVC_Handler (void) { + PRESERVE8 + + IMPORT SVC_Count + IMPORT SVC_Table + IMPORT rt_stk_check + + MRS R0,PSP ; Read PSP + LDR R1,[R0,#24] ; Read Saved PC from Stack + SUBS R1,R1,#2 ; Point to SVC Instruction + LDRB R1,[R1] ; Load SVC Number + CMP R1,#0 + BNE SVC_User ; User SVC Number > 0 + + MOV LR,R4 + LDMIA R0,{R0-R3,R4} ; Read R0-R3,R12 from stack + MOV R12,R4 + MOV R4,LR + BLX R12 ; Call SVC Function + + MRS R3,PSP ; Read PSP + STMIA R3!,{R0-R2} ; Store return values + + LDR R3,=__cpp(&os_tsk) + LDMIA R3!,{R1,R2} ; os_tsk.run, os_tsk.new + CMP R1,R2 + BEQ SVC_Exit ; no task switch + + SUBS R3,#8 + CMP R1,#0 ; Runtask deleted? + BEQ SVC_Next + + MRS R0,PSP ; Read PSP + SUBS R0,R0,#32 ; Adjust Start Address + STR R0,[R1,#TCB_TSTACK] ; Update os_tsk.run->tsk_stack + STMIA R0!,{R4-R7} ; Save old context (R4-R7) + MOV R4,R8 + MOV R5,R9 + MOV R6,R10 + MOV R7,R11 + STMIA R0!,{R4-R7} ; Save old context (R8-R11) + + PUSH {R2,R3} + BL rt_stk_check ; Check for Stack overflow + POP {R2,R3} + +SVC_Next + STR R2,[R3] ; os_tsk.run = os_tsk.new + + LDR R0,[R2,#TCB_TSTACK] ; os_tsk.new->tsk_stack + ADDS R0,R0,#16 ; Adjust Start Address + LDMIA R0!,{R4-R7} ; Restore new Context (R8-R11) + MOV R8,R4 + MOV R9,R5 + MOV R10,R6 + MOV R11,R7 + MSR PSP,R0 ; Write PSP + SUBS R0,R0,#32 ; Adjust Start Address + LDMIA R0!,{R4-R7} ; Restore new Context (R4-R7) + +SVC_Exit + MOVS R0,#:NOT:0xFFFFFFFD ; Set EXC_RETURN value + MVNS R0,R0 + BX R0 ; RETI to Thread Mode, use PSP + + /*------------------- User SVC ------------------------------*/ + +SVC_User + PUSH {R4,LR} ; Save Registers + LDR R2,=SVC_Count + LDR R2,[R2] + CMP R1,R2 + BHI SVC_Done ; Overflow + + LDR R4,=SVC_Table-4 + LSLS R1,R1,#2 + LDR R4,[R4,R1] ; Load SVC Function Address + MOV LR,R4 + + LDMIA R0,{R0-R3,R4} ; Read R0-R3,R12 from stack + MOV R12,R4 + BLX LR ; Call SVC Function + + MRS R4,PSP ; Read PSP + STMIA R4!,{R0-R3} ; Function return values +SVC_Done + POP {R4,PC} ; RETI + + ALIGN +} + + +/*-------------------------- PendSV_Handler ---------------------------------*/ + +__asm void PendSV_Handler (void) { + PRESERVE8 + + BL __cpp(rt_pop_req) + +Sys_Switch + LDR R3,=__cpp(&os_tsk) + LDMIA R3!,{R1,R2} ; os_tsk.run, os_tsk.new + CMP R1,R2 + BEQ Sys_Exit ; no task switch + + SUBS R3,#8 + + MRS R0,PSP ; Read PSP + SUBS R0,R0,#32 ; Adjust Start Address + STR R0,[R1,#TCB_TSTACK] ; Update os_tsk.run->tsk_stack + STMIA R0!,{R4-R7} ; Save old context (R4-R7) + MOV R4,R8 + MOV R5,R9 + MOV R6,R10 + MOV R7,R11 + STMIA R0!,{R4-R7} ; Save old context (R8-R11) + + PUSH {R2,R3} + BL rt_stk_check ; Check for Stack overflow + POP {R2,R3} + + STR R2,[R3] ; os_tsk.run = os_tsk.new + + LDR R0,[R2,#TCB_TSTACK] ; os_tsk.new->tsk_stack + ADDS R0,R0,#16 ; Adjust Start Address + LDMIA R0!,{R4-R7} ; Restore new Context (R8-R11) + MOV R8,R4 + MOV R9,R5 + MOV R10,R6 + MOV R11,R7 + MSR PSP,R0 ; Write PSP + SUBS R0,R0,#32 ; Adjust Start Address + LDMIA R0!,{R4-R7} ; Restore new Context (R4-R7) + +Sys_Exit + MOVS R0,#:NOT:0xFFFFFFFD ; Set EXC_RETURN value + MVNS R0,R0 + BX R0 ; RETI to Thread Mode, use PSP + + ALIGN +} + + +/*-------------------------- SysTick_Handler --------------------------------*/ + +__asm void SysTick_Handler (void) { + PRESERVE8 + + BL __cpp(rt_systick) + B Sys_Switch + + ALIGN +} + + +/*-------------------------- OS_Tick_Handler --------------------------------*/ + +__asm void OS_Tick_Handler (void) { + PRESERVE8 + + BL __cpp(os_tick_irqack) + BL __cpp(rt_systick) + B Sys_Switch + + ALIGN +} + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_ARM/SVC_Table.s b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_ARM/SVC_Table.s new file mode 100644 index 0000000000..817f024883 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_ARM/SVC_Table.s @@ -0,0 +1,57 @@ +;/*---------------------------------------------------------------------------- +; * RL-ARM - RTX +; *---------------------------------------------------------------------------- +; * Name: SVC_TABLE.S +; * Purpose: Pre-defined SVC Table for Cortex-M +; * Rev.: V4.60 +; *---------------------------------------------------------------------------- +; * +; * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH +; * All rights reserved. +; * Redistribution and use in source and binary forms, with or without +; * modification, are permitted provided that the following conditions are met: +; * - Redistributions of source code must retain the above copyright +; * notice, this list of conditions and the following disclaimer. +; * - Redistributions in binary form must reproduce the above copyright +; * notice, this list of conditions and the following disclaimer in the +; * documentation and/or other materials provided with the distribution. +; * - Neither the name of ARM nor the names of its contributors may be used +; * to endorse or promote products derived from this software without +; * specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; * POSSIBILITY OF SUCH DAMAGE. +; *---------------------------------------------------------------------------*/ + + + AREA SVC_TABLE, CODE, READONLY + + EXPORT SVC_Count + +SVC_Cnt EQU (SVC_End-SVC_Table)/4 +SVC_Count DCD SVC_Cnt + +; Import user SVC functions here. +; IMPORT __SVC_1 + + EXPORT SVC_Table +SVC_Table +; Insert user SVC functions here. SVC 0 used by RTL Kernel. +; DCD __SVC_1 ; user SVC function + +SVC_End + + END + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s new file mode 100644 index 0000000000..91fb1668fb --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s @@ -0,0 +1,342 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: HAL_CM0.S + * Purpose: Hardware Abstraction Layer for Cortex-M0 + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + + .file "HAL_CM0.S" + .syntax unified + + .equ TCB_TSTACK, 36 + + +/*---------------------------------------------------------------------------- + * Functions + *---------------------------------------------------------------------------*/ + + .arm + + .section ".text" + .align 2 + +/*-------------------------- Save Context --------------------------------*/ +/* MUST be called the first */ +.macro SaveContext + + /* Push R0 as we are going to use the register. */ \ + STMDB SP!, {R0} + + /* Set R0 to SP(user) */ + STMDB SP,{SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!,{R0} + + /* Push the LR return address onto the user stack. */ + STMDB R0!, {LR} + + /* Now we have saved LR we can use it instead of R0. */ + MOV LR, R0 + + /* Pop R0 so we can save it onto the system mode stack. */ + LDMIA SP!, {R0} + + /* Push all the system mode registers onto the task stack. */ + STMDB LR,{R0-R12,LR}^ /* LR can not be changed because user's LR is used*/ + NOP /* pass 1 cycle before changing LR */ + SUB LR, LR, #14*4 /* change LR now -15 dwords (R0-R14)*/ + + /* Push the SPSR onto the task stack. */ + MRS R0, SPSR + STMDB LR!, {R0} + + /* Store the new top of stack for the task. */ + LDR R0,=os_tsk + LDR R0, [R0] /* R0 = (tcb) os_tsk.run */ + STR LR, [R0, 36] /* tcb.tsk_stack = SP(user) */ +.endm + +/*-------------------------- Restore Context --------------------------------*/ + .type RestoreContext, %function + .global RestoreContext +RestoreContext: + .fnstart + .cantunwind + /* Set the LR to the task stack. */ + LDR R0,=os_tsk + LDR R1, [R0, 4] /* R1 = (tcb) os_tsk.new */ + STR R1, [R0] /* os_tsk.run = os_tsk_newk */ + LDR LR, [R1, 36] /* LR = tcb.tsk_stack */ + + /* Get the SPSR from the stack. */ + LDMFD LR!, {R0} /* SPSR */ + MSR SPSR, R0 + + /* Restore all system mode registers for the task. */ + LDMFD LR, {R0-R12,LR}^ + NOP + + ADD LR, LR, 15*4 /* increase starck pointer */ + /* Set SP(user) to LR */ + STMDB SP!,{LR} + LDMIA SP,{SP}^ + NOP + ADD SP, SP, #4 + + /* Restore the return address. */ + LDR LR, [LR,#-4] /* last dword is task's PC register */ + + /* And return - correcting the offset in the LR to obtain the */ + /* correct address. */ + SUBS PC, LR, #4 + +/*-------------------------- End --------------------------------*/ + .fnend + .size RestoreContext, .-RestoreContext + + + +/*--------------------------- rt_set_PSP ------------------------------------*/ + +# void rt_set_PSP (U32 stack); + + .type rt_set_PSP, %function + .global rt_set_PSP +rt_set_PSP: + .fnstart + .cantunwind + + MOV SP,R0 + BX LR + + .fnend + .size rt_set_PSP, .-rt_set_PSP + + +/*--------------------------- rt_get_PSP ------------------------------------*/ + +# U32 rt_get_PSP (void); + + .type rt_get_PSP, %function + .global rt_get_PSP +rt_get_PSP: + .fnstart + .cantunwind + + MOV R0,SP + BX LR + + .fnend + .size rt_get_PSP, .-rt_get_PSP + + + +/*--------------------------- _alloc_box ------------------------------------*/ + +# void *_alloc_box (void *box_mem); + /* Function wrapper for Unprivileged/Privileged mode. */ + + .type _alloc_box, %function + .global _alloc_box +_alloc_box: + .fnstart + .cantunwind + + LDR R3,=rt_alloc_box + MOV R12, R3 + MRS R3, CPSR + AND R3, 0x1F + CMP R3, 0x12 /* IRQ mode*/ + BNE PrivilegedA + CMP R3, 0x1F /* System mode*/ + BNE PrivilegedA + SVC 0 + BX LR +PrivilegedA: + BX R12 + + .fnend + .size _alloc_box, .-_alloc_box + + +/*--------------------------- _free_box -------------------------------------*/ + +# int _free_box (void *box_mem, void *box); + /* Function wrapper for Unprivileged/Privileged mode. */ + + .type _free_box, %function + .global _free_box +_free_box: + .fnstart + .cantunwind + + LDR R3,=rt_free_box + MOV R12, R3 + MRS R3, CPSR + AND R3, 0x1F + CMP R3, 0x12 /* IRQ mode*/ + BNE PrivilegedA + CMP R3, 0x1F /* System mode*/ + BNE PrivilegedA + SVC 0 + BX LR +PrivilegedF: + BX R12 + + .fnend + .size _free_box, .-_free_box + + +/*-------------------------- SVC_Handler ------------------------------------*/ + +# void SVC_Handler (void); + + .type SVC_Handler, %function + .global SVC_Handler +SVC_Handler: + .fnstart + .cantunwind + /* Within an IRQ ISR the link register has an offset from the true return + address, but an SWI ISR does not. Add the offset manually so the same + ISR return code can be used in both cases. */ + + STMFD SP!, {R0,LR} /* Store registers. */ + ADD LR, LR, #4 + SaveContext + MOV R11, LR /* Save Task Stack Pointer */ + LDMFD SP!, {R0,LR} /* Restore registers and return. */ + STMFD SP!, {R11} /* Save Task Stack Pointer */ + + LDR R5, [LR,#-4] /* Calculate address of SWI instruction and load it into r5. */ + BIC R5, R5,#0xff000000 /* Mask off top 8 bits of instruction to give SWI number. */ + + CMP R5, #0 + BNE SVC_User /* User SVC Number > 0 */ + MOV LR, PC /* set LR to return address */ + BX R12 /* Call SVC Function */ + STMFD SP!, {R0-R3} /* Store return values */ + + LDR R3, =os_tsk + LDMIA R3!, {R1,R2} /* os_tsk.run, os_tsk.new */ + CMP R1,0 + LDMFD SP!, {R0-R3} /* Restore return values */ + LDMFD SP!, {R11} /* Load Task Stack Pointer */ + BEQ SVC_Exit /* no need in return values */ + + ADD R11, 4 /* Offset to R0 in the Task Stack */ + STMDB R11, {R0-R3} /* Save return values in the Task Stack */ +SVC_Exit: + B RestoreContext /* return to the task */ + + /*------------------- User SVC ------------------------------*/ + +SVC_User: + LDR R6,=SVC_Count + LDR R6,[R6] + CMP R5,R6 + LDMFDHI SP!, {R11} + BHI SVC_Done /* Overflow */ + + LDR R4,=SVC_Table - 4 + LSLS R5,R5,#2 + LDR R4,[R4,R5] /* Load SVC Function Address */ + /* R0-R3,R12 are unchanged */ + MOV LR, PC /* set LR to return address */ + BX R4 /* Call SVC Function */ + + LDMFD SP!, {R11} /* Load Task Stack Pointer */ + BEQ SVC_Exit /* no need in return values */ + + STMDB R11, {R0-R3} /* Save return values in the Task Stack */ +SVC_Done: + B RestoreContext /* return to the task */ + + .fnend + .size SVC_Handler, .-SVC_Handler + + +/*-------------------------- IRQ_Handler ---------------------------------*/ + +# void IRQ_Handler (void); + + .type IRQ_Handler, %function + .global IRQ_Handler +IRQ_Handler: + .fnstart + .cantunwind + + SaveContext + + MOV R0, #0xFFFFFF00 + LDR R0, [R0] /* Load address of raised IRQ handler*/ + + MOV LR, PC + BX R0 + + MOV R0, #0xFFFFFF00 + STR R0, [R0] /* Clear interrupt */ + + B RestoreContext + + .fnend + .size IRQ_Handler, .-IRQ_Handler + +/*-------------------------- PendSV_Handler ---------------------------------*/ +PendSV_Handler: + BL rt_pop_req + B RestoreContext + + +/*-------------------------- SysTick_Handler --------------------------------*/ + +# void SysTick_Handler (void); + + .type SysTick_Handler, %function + .global SysTick_Handler +SysTick_Handler: + .fnstart + .cantunwind + + PUSH {LR} + BL rt_systick + POP {LR} + BX LR + +/*-------------------------- End --------------------------------*/ + .fnend + .size SysTick_Handler, .-SysTick_Handler + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + +.end \ No newline at end of file diff --git a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/SVC_Table.s b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/SVC_Table.s new file mode 100644 index 0000000000..47bf2d9d38 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/SVC_Table.s @@ -0,0 +1,56 @@ +;/*---------------------------------------------------------------------------- +; * RL-ARM - RTX +; *---------------------------------------------------------------------------- +; * Name: SVC_TABLE.S +; * Purpose: Pre-defined SVC Table for Cortex-M +; * Rev.: V4.60 +; *---------------------------------------------------------------------------- +; * +; * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH +; * All rights reserved. +; * Redistribution and use in source and binary forms, with or without +; * modification, are permitted provided that the following conditions are met: +; * - Redistributions of source code must retain the above copyright +; * notice, this list of conditions and the following disclaimer. +; * - Redistributions in binary form must reproduce the above copyright +; * notice, this list of conditions and the following disclaimer in the +; * documentation and/or other materials provided with the distribution. +; * - Neither the name of ARM nor the names of its contributors may be used +; * to endorse or promote products derived from this software without +; * specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; * POSSIBILITY OF SUCH DAMAGE. +; *---------------------------------------------------------------------------*/ + + + .file "SVC_Table.S" + + + .section ".svc_table" + + .global SVC_Table +SVC_Table: +/* Insert user SVC functions here. SVC 0 used by RTL Kernel. */ +# .long __SVC_1 /* user SVC function */ +SVC_End: + + .global SVC_Count +SVC_Count: + .long (SVC_End-SVC_Table)/4 + + + .end + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_IAR/HAL_CM0.s b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_IAR/HAL_CM0.s new file mode 100644 index 0000000000..5aa21f38c2 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_IAR/HAL_CM0.s @@ -0,0 +1,312 @@ +/*---------------------------------------------------------------------------- + * CMSIS-RTOS - RTX + *---------------------------------------------------------------------------- + * Name: HAL_CM0.S + * Purpose: Hardware Abstraction Layer for Cortex-M0 + * Rev.: V4.70 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + + NAME HAL_CM0.S + + #define TCB_TSTACK 36 + + EXTERN os_flags + EXTERN os_tsk + EXTERN rt_alloc_box + EXTERN rt_free_box + EXTERN rt_stk_check + EXTERN rt_pop_req + EXTERN rt_systick + EXTERN os_tick_irqack + EXTERN SVC_Table + EXTERN SVC_Count + +/*---------------------------------------------------------------------------- + * Functions + *---------------------------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB + +/*--------------------------- rt_set_PSP ------------------------------------*/ + +; void rt_set_PSP (U32 stack); + + PUBLIC rt_set_PSP +rt_set_PSP: + + MSR PSP,R0 + BX LR + + +/*--------------------------- rt_get_PSP ------------------------------------*/ + +; U32 rt_get_PSP (void); + + PUBLIC rt_get_PSP +rt_get_PSP: + + MRS R0,PSP + BX LR + + +/*--------------------------- os_set_env ------------------------------------*/ + +; void os_set_env (void); + /* Switch to Unprivileged/Privileged Thread mode, use PSP. */ + + PUBLIC os_set_env +os_set_env: + + MOV R0,SP /* PSP = MSP */ + MSR PSP,R0 + LDR R0,=os_flags + LDRB R0,[R0] + LSLS R0,#31 + BNE PrivilegedE + MOVS R0,#0x03 /* Unprivileged Thread mode, use PSP */ + MSR CONTROL,R0 + BX LR +PrivilegedE: + MOVS R0,#0x02 /* Privileged Thread mode, use PSP */ + MSR CONTROL,R0 + BX LR + + +/*--------------------------- _alloc_box ------------------------------------*/ + +; void *_alloc_box (void *box_mem); + /* Function wrapper for Unprivileged/Privileged mode. */ + + PUBLIC _alloc_box +_alloc_box: + + LDR R3,=rt_alloc_box + MOV R12,R3 + MRS R3,IPSR + LSLS R3,#24 + BNE PrivilegedA + MRS R3,CONTROL + LSLS R3,#31 + BEQ PrivilegedA + SVC 0 + BX LR +PrivilegedA: + BX R12 + + +/*--------------------------- _free_box -------------------------------------*/ + +; int _free_box (void *box_mem, void *box); + /* Function wrapper for Unprivileged/Privileged mode. */ + + PUBLIC _free_box +_free_box: + + LDR R3,=rt_free_box + MOV R12,R3 + MRS R3,IPSR + LSLS R3,#24 + BNE PrivilegedF + MRS R3,CONTROL + LSLS R3,#31 + BEQ PrivilegedF + SVC 0 + BX LR +PrivilegedF: + BX R12 + + +/*-------------------------- SVC_Handler ------------------------------------*/ + +; void SVC_Handler (void); + + PUBLIC SVC_Handler +SVC_Handler: + + MRS R0,PSP /* Read PSP */ + LDR R1,[R0,#24] /* Read Saved PC from Stack */ + SUBS R1,R1,#2 /* Point to SVC Instruction */ + LDRB R1,[R1] /* Load SVC Number */ + CMP R1,#0 + BNE SVC_User /* User SVC Number > 0 */ + + MOV LR,R4 + LDMIA R0,{R0-R3,R4} /* Read R0-R3,R12 from stack */ + MOV R12,R4 + MOV R4,LR + BLX R12 /* Call SVC Function */ + + MRS R3,PSP /* Read PSP */ + STMIA R3!,{R0-R2} /* Store return values */ + + LDR R3,=os_tsk + LDMIA R3!,{R1,R2} /* os_tsk.run, os_tsk.new */ + CMP R1,R2 + BEQ SVC_Exit /* no task switch */ + + SUBS R3,#8 + CMP R1,#0 /* Runtask deleted? */ + BEQ SVC_Next + + MRS R0,PSP /* Read PSP */ + SUBS R0,R0,#32 /* Adjust Start Address */ + STR R0,[R1,#TCB_TSTACK] /* Update os_tsk.run->tsk_stack */ + STMIA R0!,{R4-R7} /* Save old context (R4-R7) */ + MOV R4,R8 + MOV R5,R9 + MOV R6,R10 + MOV R7,R11 + STMIA R0!,{R4-R7} /* Save old context (R8-R11) */ + + PUSH {R2,R3} + BL rt_stk_check /* Check for Stack overflow */ + POP {R2,R3} + +SVC_Next: + STR R2,[R3] /* os_tsk.run = os_tsk.new */ + + LDR R0,[R2,#TCB_TSTACK] /* os_tsk.new->tsk_stack */ + ADDS R0,R0,#16 /* Adjust Start Address */ + LDMIA R0!,{R4-R7} /* Restore new Context (R8-R11) */ + MOV R8,R4 + MOV R9,R5 + MOV R10,R6 + MOV R11,R7 + MSR PSP,R0 /* Write PSP */ + SUBS R0,R0,#32 /* Adjust Start Address */ + LDMIA R0!,{R4-R7} /* Restore new Context (R4-R7) */ + +SVC_Exit: + MOVS R0,#~0xFFFFFFFD /* Set EXC_RETURN value */ + MVNS R0,R0 + BX R0 /* RETI to Thread Mode, use PSP */ + + /*------------------- User SVC ------------------------------*/ + +SVC_User: + PUSH {R4,LR} /* Save Registers */ + LDR R2,=SVC_Count + LDR R2,[R2] + CMP R1,R2 + BHI SVC_Done /* Overflow */ + + LDR R4,=SVC_Table-4 + LSLS R1,R1,#2 + LDR R4,[R4,R1] /* Load SVC Function Address */ + MOV LR,R4 + + LDMIA R0,{R0-R3,R4} /* Read R0-R3,R12 from stack */ + MOV R12,R4 + BLX LR /* Call SVC Function */ + + MRS R4,PSP /* Read PSP */ + STMIA R4!,{R0-R3} /* Function return values */ +SVC_Done: + POP {R4,PC} /* RETI */ + + +/*-------------------------- PendSV_Handler ---------------------------------*/ + +; void PendSV_Handler (void); + + PUBLIC PendSV_Handler +PendSV_Handler: + + BL rt_pop_req + +Sys_Switch: + LDR R3,=os_tsk + LDMIA R3!,{R1,R2} /* os_tsk.run, os_tsk.new */ + CMP R1,R2 + BEQ Sys_Exit /* no task switch */ + + SUBS R3,#8 + + MRS R0,PSP /* Read PSP */ + SUBS R0,R0,#32 /* Adjust Start Address */ + STR R0,[R1,#TCB_TSTACK] /* Update os_tsk.run->tsk_stack */ + STMIA R0!,{R4-R7} /* Save old context (R4-R7) */ + MOV R4,R8 + MOV R5,R9 + MOV R6,R10 + MOV R7,R11 + STMIA R0!,{R4-R7} /* Save old context (R8-R11) */ + + PUSH {R2,R3} + BL rt_stk_check /* Check for Stack overflow */ + POP {R2,R3} + + STR R2,[R3] /* os_tsk.run = os_tsk.new */ + + LDR R0,[R2,#TCB_TSTACK] /* os_tsk.new->tsk_stack */ + ADDS R0,R0,#16 /* Adjust Start Address */ + LDMIA R0!,{R4-R7} /* Restore new Context (R8-R11) */ + MOV R8,R4 + MOV R9,R5 + MOV R10,R6 + MOV R11,R7 + MSR PSP,R0 /* Write PSP */ + SUBS R0,R0,#32 /* Adjust Start Address */ + LDMIA R0!,{R4-R7} /* Restore new Context (R4-R7) */ + +Sys_Exit: + MOVS R0,#~0xFFFFFFFD /* Set EXC_RETURN value */ + MVNS R0,R0 + BX R0 /* RETI to Thread Mode, use PSP */ + + +/*-------------------------- SysTick_Handler --------------------------------*/ + +; void SysTick_Handler (void); + + PUBLIC SysTick_Handler +SysTick_Handler: + + BL rt_systick + B Sys_Switch + + +/*-------------------------- OS_Tick_Handler --------------------------------*/ + +; void OS_Tick_Handler (void); + + PUBLIC OS_Tick_Handler +OS_Tick_Handler: + + BL os_tick_irqack + BL rt_systick + B Sys_Switch + + + END + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_IAR/SVC_Table.s b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_IAR/SVC_Table.s new file mode 100644 index 0000000000..269f4605b1 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_IAR/SVC_Table.s @@ -0,0 +1,58 @@ +;/*---------------------------------------------------------------------------- +; * CMSIS-RTOS - RTX +; *---------------------------------------------------------------------------- +; * Name: SVC_TABLE.S +; * Purpose: Pre-defined SVC Table for Cortex-M +; * Rev.: V4.70 +; *---------------------------------------------------------------------------- +; * +; * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH +; * All rights reserved. +; * Redistribution and use in source and binary forms, with or without +; * modification, are permitted provided that the following conditions are met: +; * - Redistributions of source code must retain the above copyright +; * notice, this list of conditions and the following disclaimer. +; * - Redistributions in binary form must reproduce the above copyright +; * notice, this list of conditions and the following disclaimer in the +; * documentation and/or other materials provided with the distribution. +; * - Neither the name of ARM nor the names of its contributors may be used +; * to endorse or promote products derived from this software without +; * specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; * POSSIBILITY OF SUCH DAMAGE. +; *---------------------------------------------------------------------------*/ + + + NAME SVC_TABLE + SECTION .text:CONST (2) + + PUBLIC SVC_Count + +SVC_Cnt EQU (SVC_End-SVC_Table)/4 +SVC_Count DCD SVC_Cnt + +; Import user SVC functions here. +; IMPORT __SVC_1 + + PUBLIC SVC_Table +SVC_Table +; Insert user SVC functions here. SVC 0 used by RTL Kernel. +; DCD __SVC_1 ; user SVC function + +SVC_End + + END + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/libraries/rtos/rtx/TARGET_ARM7/HAL_CM.c b/libraries/rtos/rtx/TARGET_ARM7/HAL_CM.c new file mode 100644 index 0000000000..249d95deaf --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/HAL_CM.c @@ -0,0 +1,161 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: HAL_CM.C + * Purpose: Hardware Abstraction Layer for Cortex-M + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Conf.h" +#include "rt_HAL_CM.h" + + +/*---------------------------------------------------------------------------- + * Global Variables + *---------------------------------------------------------------------------*/ + +#ifdef DBG_MSG +BIT dbg_msg; +#endif + +/*---------------------------------------------------------------------------- + * Functions + *---------------------------------------------------------------------------*/ + + +/*--------------------------- rt_init_stack ---------------------------------*/ + +void rt_init_stack (P_TCB p_TCB, FUNCP task_body) { + /* Prepare TCB and saved context for a first time start of a task. */ + U32 *stk,i,size; + + /* Prepare a complete interrupt frame for first task start */ + size = p_TCB->priv_stack >> 2; + + /* Write to the top of stack. */ + stk = &p_TCB->stack[size]; + + /* Auto correct to 8-byte ARM stack alignment. */ + if ((U32)stk & 0x04) { + stk--; + } + + stk -= 16; + + /* Default xPSR and initial PC */ + stk[15] = (U32)task_body + 4; /* add 4 byte offset because SUB PC, LR - 4 */ + stk[0] = INITIAL_xPSR; + + /* Clear R0-R13/LR registers. */ + for (i = 1; i < 14; i++) { + stk[i] = 0; + } + + /* Assign a void pointer to R0. */ + stk[TCB_STACK_R0_OFFSET_DWORDS] = (U32)p_TCB->msg; + + /* Initial Task stack pointer. */ + p_TCB->tsk_stack = (U32)stk; + + /* Task entry point. */ + p_TCB->ptask = task_body; + + /* Set a magic word for checking of stack overflow. + For the main thread (ID: 0x01) the stack is in a memory area shared with the + heap, therefore the last word of the stack is a moving target. + We want to do stack/heap collision detection instead. + */ + if (p_TCB->task_id != 0x01) + p_TCB->stack[0] = MAGIC_WORD; +} + + +/*--------------------------- rt_ret_val ----------------------------------*/ + +static __inline U32 *rt_ret_regs (P_TCB p_TCB) { + /* Get pointer to task return value registers (R0..R3) in Stack */ + + /* Stack Frame: CPSR,R0-R13,PC */ + return (U32 *)(p_TCB->tsk_stack + TCB_STACK_R0_OFFSET_BYTES); +} + +void rt_ret_val (P_TCB p_TCB, U32 v0) { + U32 *ret; + + ret = rt_ret_regs(p_TCB); + ret[0] = v0; +} + +void rt_ret_val2(P_TCB p_TCB, U32 v0, U32 v1) { + U32 *ret; + + ret = rt_ret_regs(p_TCB); + ret[0] = v0; + ret[1] = v1; +} + + +/*--------------------------- dbg_init --------------------------------------*/ + +#ifdef DBG_MSG +void dbg_init (void) { + if ((DEMCR & DEMCR_TRCENA) && + (ITM_CONTROL & ITM_ITMENA) && + (ITM_ENABLE & (1UL << 31))) { + dbg_msg = __TRUE; + } +} +#endif + +/*--------------------------- dbg_task_notify -------------------------------*/ + +#ifdef DBG_MSG +void dbg_task_notify (P_TCB p_tcb, BOOL create) { + while (ITM_PORT31_U32 == 0); + ITM_PORT31_U32 = (U32)p_tcb->ptask; + while (ITM_PORT31_U32 == 0); + ITM_PORT31_U16 = (create << 8) | p_tcb->task_id; +} +#endif + +/*--------------------------- dbg_task_switch -------------------------------*/ + +#ifdef DBG_MSG +void dbg_task_switch (U32 task_id) { + while (ITM_PORT31_U32 == 0); + ITM_PORT31_U8 = task_id; +} +#endif + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/RTX_CM_lib.h b/libraries/rtos/rtx/TARGET_ARM7/RTX_CM_lib.h new file mode 100755 index 0000000000..bf31afe66f --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/RTX_CM_lib.h @@ -0,0 +1,467 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RTX_CM_LIB.H + * Purpose: RTX Kernel System Configuration + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +#include "mbed_error.h" + +#if defined (__CC_ARM) +#pragma O3 +#define __USED __attribute__((used)) +#elif defined (__GNUC__) +#pragma GCC optimize ("O3") +#define __USED __attribute__((used)) +#elif defined (__ICCARM__) +#define __USED __root +#endif + + +/*---------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ + +#define _declare_box(pool,size,cnt) uint32_t pool[(((size)+3)/4)*(cnt) + 3] +#define _declare_box8(pool,size,cnt) uint64_t pool[(((size)+7)/8)*(cnt) + 2] + +#define OS_TCB_SIZE 48 +#define OS_TMR_SIZE 8 + +#if defined (__CC_ARM) && !defined (__MICROLIB) + +typedef void *OS_ID; +typedef uint32_t OS_TID; +typedef uint32_t OS_MUT[3]; +typedef uint32_t OS_RESULT; + +#define runtask_id() rt_tsk_self() +#define mutex_init(m) rt_mut_init(m) +#define mutex_wait(m) os_mut_wait(m,0xFFFF) +#define mutex_rel(m) os_mut_release(m) + +extern OS_TID rt_tsk_self (void); +extern void rt_mut_init (OS_ID mutex); +extern OS_RESULT rt_mut_release (OS_ID mutex); +extern OS_RESULT rt_mut_wait (OS_ID mutex, uint16_t timeout); + +#define os_mut_wait(mutex,timeout) _os_mut_wait((uint32_t)rt_mut_wait,mutex,timeout) +#define os_mut_release(mutex) _os_mut_release((uint32_t)rt_mut_release,mutex) + +OS_RESULT _os_mut_release (uint32_t p, OS_ID mutex) __svc_indirect(0); +OS_RESULT _os_mut_wait (uint32_t p, OS_ID mutex, uint16_t timeout) __svc_indirect(0); + +#endif + + +/*---------------------------------------------------------------------------- + * Global Variables + *---------------------------------------------------------------------------*/ + +#if (OS_TIMERS != 0) +#define OS_TASK_CNT (OS_TASKCNT + 1) +#else +#define OS_TASK_CNT OS_TASKCNT +#endif + +uint16_t const os_maxtaskrun = OS_TASK_CNT; +uint32_t const os_rrobin = (OS_ROBIN << 16) | OS_ROBINTOUT; +uint32_t const os_trv = OS_TRV; +uint8_t const os_flags = OS_RUNPRIV; + +/* Export following defines to uVision debugger. */ +__USED uint32_t const os_clockrate = OS_TICK; +__USED uint32_t const os_timernum = 0; + +/* Stack for the os_idle_demon */ +unsigned int idle_task_stack[OS_IDLESTKSIZE]; +unsigned short const idle_task_stack_size = OS_IDLESTKSIZE; + +#ifndef OS_FIFOSZ + #define OS_FIFOSZ 16 +#endif + +/* Fifo Queue buffer for ISR requests.*/ +uint32_t os_fifo[OS_FIFOSZ*2+1]; +uint8_t const os_fifo_size = OS_FIFOSZ; + +/* An array of Active task pointers. */ +void *os_active_TCB[OS_TASK_CNT]; + +/* User Timers Resources */ +#if (OS_TIMERS != 0) +extern void osTimerThread (void const *argument); +osThreadDef(osTimerThread, (osPriority)(OS_TIMERPRIO-3), 4*OS_TIMERSTKSZ); +osThreadId osThreadId_osTimerThread; +osMessageQDef(osTimerMessageQ, OS_TIMERCBQS, void *); +osMessageQId osMessageQId_osTimerMessageQ; +#else +osThreadDef_t os_thread_def_osTimerThread = { NULL }; +osThreadId osThreadId_osTimerThread; +osMessageQDef(osTimerMessageQ, 0, void *); +osMessageQId osMessageQId_osTimerMessageQ; +#endif + + +/*---------------------------------------------------------------------------- + * RTX Optimizations (empty functions) + *---------------------------------------------------------------------------*/ + +#if OS_ROBIN == 0 + void rt_init_robin (void) {;} + void rt_chk_robin (void) {;} +#endif + +#if OS_STKCHECK == 0 + void rt_stk_check (void) {;} +#endif + + +/*---------------------------------------------------------------------------- + * Standard Library multithreading interface + *---------------------------------------------------------------------------*/ + +#if defined (__CC_ARM) && !defined (__MICROLIB) + static OS_MUT std_libmutex[OS_MUTEXCNT]; + static uint32_t nr_mutex; + + /*--------------------------- _mutex_initialize -----------------------------*/ + +int _mutex_initialize (OS_ID *mutex) { + /* Allocate and initialize a system mutex. */ + + if (nr_mutex >= OS_MUTEXCNT) { + /* If you are here, you need to increase the number OS_MUTEXCNT. */ + error("Not enough stdlib mutexes\n"); + } + *mutex = &std_libmutex[nr_mutex++]; + mutex_init (*mutex); + return (1); +} + + +/*--------------------------- _mutex_acquire --------------------------------*/ + +__attribute__((used)) void _mutex_acquire (OS_ID *mutex) { + /* Acquire a system mutex, lock stdlib resources. */ + if (runtask_id ()) { + /* RTX running, acquire a mutex. */ + mutex_wait (*mutex); + } +} + + +/*--------------------------- _mutex_release --------------------------------*/ + +__attribute__((used)) void _mutex_release (OS_ID *mutex) { + /* Release a system mutex, unlock stdlib resources. */ + if (runtask_id ()) { + /* RTX running, release a mutex. */ + mutex_rel (*mutex); + } +} + +#endif + + +/*---------------------------------------------------------------------------- + * RTX Startup + *---------------------------------------------------------------------------*/ + +/* Main Thread definition */ +extern int main (void); +osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL}; + +// This define should be probably moved to the CMSIS layer +#if defined(TARGET_LPC1768) +#define INITIAL_SP (0x10008000UL) + +#elif defined(TARGET_LPC11U24) +#define INITIAL_SP (0x10002000UL) + +#elif defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) +#define INITIAL_SP (0x10002000UL) + +#elif defined(TARGET_LPC1114) +#define INITIAL_SP (0x10001000UL) + +#elif defined(TARGET_LPC812) +#define INITIAL_SP (0x10001000UL) + +#elif defined(TARGET_LPC824) +#define INITIAL_SP (0x10002000UL) + +#elif defined(TARGET_KL25Z) +#define INITIAL_SP (0x20003000UL) + +#elif defined(TARGET_K64F) +#define INITIAL_SP (0x20030000UL) + +#elif defined(TARGET_K22F) +#define INITIAL_SP (0x20010000UL) + +#elif defined(TARGET_KL46Z) +#define INITIAL_SP (0x20006000UL) + +#elif defined(TARGET_KL43Z) +#define INITIAL_SP (0x20006000UL) + +#elif defined(TARGET_KL05Z) +#define INITIAL_SP (0x20000C00UL) + +#elif defined(TARGET_LPC4088) +#define INITIAL_SP (0x10010000UL) + +#elif defined(TARGET_LPC4337) +#define INITIAL_SP (0x10008000UL) + +#elif defined(TARGET_LPC1347) +#define INITIAL_SP (0x10002000UL) + +#elif defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) +#define INITIAL_SP (0x20002000UL) + +#elif defined(TARGET_DISCO_F303VC) +#define INITIAL_SP (0x2000A000UL) + +#elif defined(TARGET_STM32F407) || defined(TARGET_F407VG) +#define INITIAL_SP (0x20020000UL) + +#elif defined(TARGET_STM32F401RE) +#define INITIAL_SP (0x20018000UL) + +#elif defined(TARGET_LPC1549) +#define INITIAL_SP (0x02009000UL) + +#elif defined(TARGET_LPC11U68) +#define INITIAL_SP (0x10004000UL) + +#elif defined(TARGET_NRF51822) +#define INITIAL_SP (0x20004000UL) + +#elif defined(TARGET_STM32F411RE) +#define INITIAL_SP (0x20020000UL) + +#elif defined(TARGET_STM32F103RB) +#define INITIAL_SP (0x20005000UL) + +#elif defined(TARGET_STM32F302R8) +#define INITIAL_SP (0x20004000UL) + +#elif defined(TARGET_STM32F334R8) +#define INITIAL_SP (0x20003000UL) + +#elif defined(TARGET_STM32F334C8) +#define INITIAL_SP (0x20003000UL) + +#elif defined(TARGET_STM32F405RG) +#define INITIAL_SP (0x20020000UL) + +#elif defined(TARGET_LPC2460) +extern unsigned char __usr_stack_top__[]; +#define INITIAL_SP (__usr_stack_top__) + +#else +#error "no target defined" + +#endif + +#ifdef __CC_ARM +extern unsigned char Image$$RW_IRAM1$$ZI$$Limit[]; +#define HEAP_START (Image$$RW_IRAM1$$ZI$$Limit) +#elif defined(__GNUC__) +extern unsigned char __end__[]; +#define HEAP_START (__end__) +#elif defined(__ICCARM__) +#pragma section="HEAP" +#define HEAP_START (void *)__section_begin("HEAP") +#endif + +void set_main_stack(void) { + // That is the bottom of the main stack block: no collision detection + os_thread_def_main.stack_pointer = HEAP_START; + + // Leave OS_SCHEDULERSTKSIZE words for the scheduler and interrupts + os_thread_def_main.stacksize = (INITIAL_SP - (unsigned int)HEAP_START) - (OS_SCHEDULERSTKSIZE * 4); +} + +#if defined (__CC_ARM) +#ifdef __MICROLIB +void _main_init (void) __attribute__((section(".ARM.Collect$$$$000000FF"))); +void _main_init (void) { + osKernelInitialize(); + set_main_stack(); + osThreadCreate(&os_thread_def_main, NULL); + osKernelStart(); + for (;;); +} +#else + +/* The single memory model is checking for stack collision at run time, verifing + that the heap pointer is underneath the stack pointer. + + With the RTOS there is not only one stack above the heap, there are multiple + stacks and some of them are underneath the heap pointer. +*/ +#pragma import(__use_two_region_memory) + +__asm void __rt_entry (void) { + + IMPORT __user_setup_stackheap + IMPORT __rt_lib_init + IMPORT os_thread_def_main + IMPORT osKernelInitialize + IMPORT set_main_stack + IMPORT osKernelStart + IMPORT osThreadCreate + IMPORT exit + + BL __user_setup_stackheap + MOV R1,R2 + BL __rt_lib_init + BL osKernelInitialize + BL set_main_stack + LDR R0,=os_thread_def_main + MOVS R1,#0 + BL osThreadCreate + BL osKernelStart + BL exit + + ALIGN +} +#endif + +#elif defined (__GNUC__) + +#ifdef __CS3__ + +/* CS3 start_c routine. + * + * Copyright (c) 2006, 2007 CodeSourcery Inc + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +#include "cs3.h" + +extern void __libc_init_array (void); + +__attribute ((noreturn)) void __cs3_start_c (void){ + unsigned regions = __cs3_region_num; + const struct __cs3_region *rptr = __cs3_regions; + + /* Initialize memory */ + for (regions = __cs3_region_num, rptr = __cs3_regions; regions--; rptr++) { + long long *src = (long long *)rptr->init; + long long *dst = (long long *)rptr->data; + unsigned limit = rptr->init_size; + unsigned count; + + if (src != dst) + for (count = 0; count != limit; count += sizeof (long long)) + *dst++ = *src++; + else + dst = (long long *)((char *)dst + limit); + limit = rptr->zero_size; + for (count = 0; count != limit; count += sizeof (long long)) + *dst++ = 0; + } + + /* Run initializers. */ + __libc_init_array (); + + osKernelInitialize(); + set_main_stack(); + osThreadCreate(&os_thread_def_main, NULL); + osKernelStart(); + for (;;); +} + +#else + +__attribute__((naked)) void software_init_hook (void) { + __asm ( + ".syntax unified\n" + ".thumb\n" + "movs r0,#0\n" + "movs r1,#0\n" + "mov r8,r0\n" + "mov r9,r1\n" + "ldr r0,= __libc_fini_array\n" + "bl atexit\n" + "bl __libc_init_array\n" + "mov r0,r8\n" + "mov r1,r9\n" + "bl osKernelInitialize\n" + "bl set_main_stack\n" + "ldr r0,=os_thread_def_main\n" + "movs r1,#0\n" + "bl osThreadCreate\n" + "bl osKernelStart\n" + "bl exit\n" + ); +} + +#endif + +#elif defined (__ICCARM__) + +extern int __low_level_init(void); +extern void __iar_data_init3(void); +extern void exit(int arg); + +__noreturn __stackless void __cmain(void) { + int a; + + if (__low_level_init() != 0) { + __iar_data_init3(); + } + osKernelInitialize(); + set_main_stack(); + osThreadCreate(&os_thread_def_main, NULL); + a = osKernelStart(); + exit(a); +} + +#endif + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + + diff --git a/libraries/rtos/rtx/TARGET_ARM7/RTX_Conf.h b/libraries/rtos/rtx/TARGET_ARM7/RTX_Conf.h new file mode 100644 index 0000000000..0b0d4613cd --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/RTX_Conf.h @@ -0,0 +1,72 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RTX_CONFIG.H + * Purpose: Exported functions of RTX_Config.c + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + + +/* Error Codes */ +#define OS_ERR_STK_OVF 1 +#define OS_ERR_FIFO_OVF 2 +#define OS_ERR_MBX_OVF 3 + +/* Definitions */ +#define BOX_ALIGN_8 0x80000000 +#define _declare_box(pool,size,cnt) U32 pool[(((size)+3)/4)*(cnt) + 3] +#define _declare_box8(pool,size,cnt) U64 pool[(((size)+7)/8)*(cnt) + 2] +#define _init_box8(pool,size,bsize) _init_box (pool,size,(bsize) | BOX_ALIGN_8) + +/* Variables */ +extern U32 idle_task_stack[]; +extern U32 os_fifo[]; +extern void *os_active_TCB[]; + +/* Constants */ +extern U16 const os_maxtaskrun; +extern U32 const os_trv; +extern U8 const os_flags; +extern U32 const os_rrobin; +extern U32 const os_clockrate; +extern U32 const os_timernum; +extern U16 const idle_task_stack_size; + +extern U8 const os_fifo_size; + +/* Functions */ +extern void os_idle_demon (void); +extern int os_tick_init (void); +extern void os_tick_irqack (void); +extern void os_tmr_call (U16 info); +extern void os_error (U32 err_code); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/libraries/rtos/rtx/TARGET_ARM7/RTX_Conf_CM.c b/libraries/rtos/rtx/TARGET_ARM7/RTX_Conf_CM.c new file mode 100755 index 0000000000..54e91aca96 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/RTX_Conf_CM.c @@ -0,0 +1,293 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RTX_Conf_CM.C + * Purpose: Configuration of CMSIS RTX Kernel for Cortex-M + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "cmsis_os.h" + + +/*---------------------------------------------------------------------------- + * RTX User configuration part BEGIN + *---------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// Thread Configuration +// ======================= +// +// Number of concurrent running threads <0-250> +// Defines max. number of threads that will run at the same time. +// counting "main", but not counting "osTimerThread" +// Default: 6 +#ifndef OS_TASKCNT +# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ + || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) || defined(TARGET_NRF51822) || defined(TARGET_STM32F411RE) \ + || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_LPC2460) +# define OS_TASKCNT 14 +# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ + || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ + || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) +# define OS_TASKCNT 6 +# else +# error "no target defined" +# endif +#endif + +// Scheduler (+ interrupts) stack size [bytes] <64-4096:8><#/4> +#ifndef OS_SCHEDULERSTKSIZE +# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ + || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) || defined(TARGET_NRF51822) || defined(TARGET_STM32F411RE) \ + || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) +# define OS_SCHEDULERSTKSIZE 256 +# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ + || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ + || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) +# define OS_SCHEDULERSTKSIZE 128 +# elif defined(TARGET_LPC2460) +# define OS_SCHEDULERSTKSIZE (136*2) +# else +# error "no target defined" +# endif +#endif + +// Idle stack size [bytes] <64-4096:8><#/4> +// Defines default stack size for the Idle thread. +#ifndef OS_IDLESTKSIZE + #define OS_IDLESTKSIZE 136 +#endif + +// Timer Thread stack size [bytes] <64-4096:8><#/4> +// Defines stack size for Timer thread. +// Default: 200 +#ifndef OS_TIMERSTKSZ + #define OS_TIMERSTKSZ WORDS_STACK_SIZE +#endif + +// Check for stack overflow +// Includes the stack checking code for stack overflow. +// Note that additional code reduces the Kernel performance. +#ifndef OS_STKCHECK + #define OS_STKCHECK 1 +#endif + +// Processor mode for thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_RUNPRIV + #define OS_RUNPRIV 1 +#endif + +// +// SysTick Timer Configuration +// ============================== +// +// Timer clock value [Hz] <1-1000000000> +// Defines the timer clock value. +// Default: 6000000 (6MHz) +#ifndef OS_CLOCK +# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) +# define OS_CLOCK 96000000 + +# elif defined(TARGET_LPC1347) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) || defined(TARGET_LPC2460) +# define OS_CLOCK 72000000 + +# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F051R8) || defined(TARGET_LPC11U68) +# define OS_CLOCK 48000000 + +# elif defined(TARGET_LPC812) +# define OS_CLOCK 36000000 + +# elif defined(TARGET_LPC824) +# define OS_CLOCK 30000000 + +# elif defined(TARGET_STM32F100RB) +# define OS_CLOCK 24000000 + +# elif defined(TARGET_LPC4088) || defined(TARGET_K64F) || defined(TARGET_K22F) +# define OS_CLOCK 120000000 + +# elif defined(TARGET_LPC4337) +# define OS_CLOCK 204000000 + +# elif defined(TARGET_STM32F407) || defined(TARGET_F407VG) +# define OS_CLOCK 168000000 + +# elif defined(TARGET_NRF51822) +# define OS_CLOCK 16000000 + +# elif defined(TARGET_STM32F401RE) +# define OS_CLOCK 84000000 + +# elif defined(TARGET_STM32F411RE) +# define OS_CLOCK 100000000 + +#elif defined(TARGET_STM32F103RB) +# define OS_CLOCK 72000000 + +# else +# error "no target defined" +# endif +#endif + +// Timer tick value [us] <1-1000000> +// Defines the timer tick value. +// Default: 1000 (1ms) +#ifndef OS_TICK + #define OS_TICK 1000 +#endif + +// + +// System Configuration +// ======================= +// +// Round-Robin Thread switching +// =============================== +// +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN + #define OS_ROBIN 1 +#endif + +// Round-Robin Timeout [ticks] <1-1000> +// Defines how long a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBINTOUT + #define OS_ROBINTOUT 5 +#endif + +// + +// User Timers +// ============== +// Enables user Timers +#ifndef OS_TIMERS + #define OS_TIMERS 1 +#endif + +// Timer Thread Priority +// <1=> Low +// <2=> Below Normal +// <3=> Normal +// <4=> Above Normal +// <5=> High +// <6=> Realtime (highest) +// Defines priority for Timer Thread +// Default: High +#ifndef OS_TIMERPRIO + #define OS_TIMERPRIO 5 +#endif + +// Timer Callback Queue size <1-32> +// Number of concurrent active timer callback functions. +// Default: 4 +#ifndef OS_TIMERCBQSZ + #define OS_TIMERCBQS 4 +#endif + +// + +// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries +// <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries +// <48=> 48 entries <64=> 64 entries +// <96=> 96 entries +// ISR functions store requests to this buffer, +// when they are called from the interrupt handler. +// Default: 16 entries +#ifndef OS_FIFOSZ + #define OS_FIFOSZ 16 +#endif + +// + +//------------- <<< end of configuration section >>> ----------------------- + +// Standard library system mutexes +// =============================== +// Define max. number system mutexes that are used to protect +// the arm standard runtime library. For microlib they are not used. +#ifndef OS_MUTEXCNT + #define OS_MUTEXCNT 12 +#endif + +/*---------------------------------------------------------------------------- + * RTX User configuration part END + *---------------------------------------------------------------------------*/ + +#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) + + +/*---------------------------------------------------------------------------- + * OS Idle daemon + *---------------------------------------------------------------------------*/ +void os_idle_demon (void) { + /* The idle demon is a system thread, running when no other thread is */ + /* ready to run. */ + + /* Sleep: ideally, we should put the chip to sleep. + Unfortunately, this usually requires disconnecting the interface chip (debugger). + This can be done, but it would break the local file system. + */ + for (;;) { + // sleep(); + } +} + +/*---------------------------------------------------------------------------- + * RTX Errors + *---------------------------------------------------------------------------*/ +extern void mbed_die(void); + +void os_error (uint32_t err_code) { + /* This function is called when a runtime error is detected. Parameter */ + /* 'err_code' holds the runtime error code (defined in RTX_Conf.h). */ + mbed_die(); +} + +void sysThreadError(osStatus status) { + if (status != osOK) { + mbed_die(); + } +} + +/*---------------------------------------------------------------------------- + * RTX Configuration Functions + *---------------------------------------------------------------------------*/ + +#include "RTX_CM_lib.h" + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h b/libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h new file mode 100644 index 0000000000..9f90ace987 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h @@ -0,0 +1,774 @@ +/* ---------------------------------------------------------------------- + * Copyright (C) 2012 ARM Limited. All rights reserved. + * + * $Date: 5. June 2012 + * $Revision: V1.01 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h RTX header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedef's + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + * -------------------------------------------------------------------- */ + +/** +\page cmsis_os_h Header File Template: cmsis_os.h + +The file \b cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS). +Each RTOS that is compliant with CMSIS-RTOS shall provide a specific \b cmsis_os.h header file that represents +its implementation. + +The file cmsis_os.h contains: + - CMSIS-RTOS API function definitions + - struct definitions for parameters and return types + - status and priority values used by CMSIS-RTOS API functions + - macros for defining threads and other kernel objects + + +Name conventions and header file modifications + +All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions. +Definitions that are prefixed \b os_ are not used in the application code but local to this header file. +All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread. + +Definitions that are marked with CAN BE CHANGED can be adapted towards the needs of the actual CMSIS-RTOS implementation. +These definitions can be specific to the underlying RTOS kernel. + +Definitions that are marked with MUST REMAIN UNCHANGED cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer +compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation. + + +Function calls from interrupt service routines + +The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR): + - \ref osSignalSet + - \ref osSemaphoreRelease + - \ref osPoolAlloc, \ref osPoolCAlloc, \ref osPoolFree + - \ref osMessagePut, \ref osMessageGet + - \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree + +Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called +from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector. + +Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time. +If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code \b osErrorISRRecursive. + + +Define and reference object definitions + +With \#define osObjectsExternal objects are defined as external symbols. This allows to create a consistent header file +that is used throughout a project as shown below: + +Header File +\code +#include // CMSIS RTOS header file + +// Thread definition +extern void thread_sample (void const *argument); // function prototype +osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100); + +// Pool definition +osPoolDef(MyPool, 10, long); +\endcode + + +This header file defines all objects when included in a C/C++ source file. When \#define osObjectsExternal is +present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be +used throughout the whole project. + +Example +\code +#include "osObjects.h" // Definition of the CMSIS-RTOS objects +\endcode + +\code +#define osObjectExternal // Objects will be defined as external symbols +#include "osObjects.h" // Reference to the CMSIS-RTOS objects +\endcode + +*/ + +#ifndef _CMSIS_OS_H +#define _CMSIS_OS_H + +/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version. +#define osCMSIS 0x10001 ///< API version (main [31:16] .sub [15:0]) + +/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. +#define osCMSIS_RTX ((4<<16)|61) ///< RTOS identification and version (main [31:16] .sub [15:0]) + +/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS. +#define osKernelSystemId "RTX V4.61" ///< RTOS identification string + + +#define CMSIS_OS_RTX + +// The stack space occupied is mainly dependent on the underling C standard library +#if defined(TOOLCHAIN_GCC) || defined(TOOLCHAIN_ARM_STD) || defined(TOOLCHAIN_IAR) +# define WORDS_STACK_SIZE 512 +#elif defined(TOOLCHAIN_ARM_MICRO) +# define WORDS_STACK_SIZE 128 +#endif + +#define DEFAULT_STACK_SIZE (WORDS_STACK_SIZE*4) + + +/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS. +#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_Signals 16 ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 65535 ///< maximum count for \ref osSemaphoreCreate function +#define osFeature_Wait 0 ///< osWait function: 1=available, 0=not available + +#if defined (__CC_ARM) +#define os_InRegs __value_in_regs // Compiler specific: force struct in registers +#elif defined (__ICCARM__) +#define os_InRegs __value_in_regs // Compiler specific: force struct in registers +#else +#define os_InRegs +#endif + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "os_tcb.h" + +// ==== Enumeration, structures, defines ==== + +/// Priority used for thread control. +/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS. +typedef enum { + osPriorityIdle = -3, ///< priority: idle (lowest) + osPriorityLow = -2, ///< priority: low + osPriorityBelowNormal = -1, ///< priority: below normal + osPriorityNormal = 0, ///< priority: normal (default) + osPriorityAboveNormal = +1, ///< priority: above normal + osPriorityHigh = +2, ///< priority: high + osPriorityRealtime = +3, ///< priority: realtime (highest) + osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority +} osPriority; + +/// Timeout value. +/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS. +#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value + +/// Status code values returned by CMSIS-RTOS functions. +/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS. +typedef enum { + osOK = 0, ///< function completed; no error or event occurred. + osEventSignal = 0x08, ///< function completed; signal event occurred. + osEventMessage = 0x10, ///< function completed; message event occurred. + osEventMail = 0x20, ///< function completed; mail event occurred. + osEventTimeout = 0x40, ///< function completed; timeout occurred. + osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< value of a parameter is out of range. + osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits. + os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization. +} osStatus; + + +/// Timer type value for the timer definition. +/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS. +typedef enum { + osTimerOnce = 0, ///< one-shot timer + osTimerPeriodic = 1 ///< repeating timer +} os_timer_type; + +/// Entry point of a thread. +/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. +typedef void (*os_ptimer) (void const *argument); + +// >>> the following data type definitions may shall adapted towards a specific RTOS + +/// Thread ID identifies the thread (pointer to a thread control block). +/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_cb *osThreadId; + +/// Timer ID identifies the timer (pointer to a timer control block). +/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_cb *osTimerId; + +/// Mutex ID identifies the mutex (pointer to a mutex control block). +/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_cb *osMutexId; + +/// Semaphore ID identifies the semaphore (pointer to a semaphore control block). +/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_cb *osSemaphoreId; + +/// Pool ID identifies the memory pool (pointer to a memory pool control block). +/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_cb *osPoolId; + +/// Message ID identifies the message queue (pointer to a message queue control block). +/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_cb *osMessageQId; + +/// Mail ID identifies the mail queue (pointer to a mail queue control block). +/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_cb *osMailQId; + + +/// Thread Definition structure contains startup information of a thread. +/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t stacksize; ///< stack size requirements in bytes + unsigned char *stack_pointer; ///< pointer to the stack memory block + struct OS_TCB tcb; +} osThreadDef_t; + +/// Timer Definition structure contains timer parameters. +/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function + void *timer; ///< pointer to internal data +} osTimerDef_t; + +/// Mutex Definition structure contains setup information for a mutex. +/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_def { + void *mutex; ///< pointer to internal data +} osMutexDef_t; + +/// Semaphore Definition structure contains setup information for a semaphore. +/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_def { + void *semaphore; ///< pointer to internal data +} osSemaphoreDef_t; + +/// Definition structure for memory block allocation. +/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; + +/// Definition structure for message queue. +/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + void *pool; ///< memory array for messages +} osMessageQDef_t; + +/// Definition structure for mail queue. +/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for mail +} osMailQDef_t; + +/// Event structure contains detailed information about an event. +/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS. +/// However the struct may be extended at the end. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Control Functions ==== + +/// Initialize the RTOS Kernel for creating objects. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS. +osStatus osKernelInitialize (void); + +/// Start the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +osStatus osKernelStart (void); + +/// Check if the RTOS kernel is already started. +/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. +/// \return 0 RTOS is not started, 1 RTOS is started. +int32_t osKernelRunning(void); + + +// ==== Thread Management ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param stacksz stack size (in bytes) requirements for the thread function. +/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, priority, stacksz) \ +extern osThreadDef_t os_thread_def_##name +#else // define the object +#define osThreadDef(name, priority, stacksz) \ +unsigned char os_thread_def_stack_##name [stacksz]; \ +osThreadDef_t os_thread_def_##name = \ +{ (name), (priority), (stacksz), (os_thread_def_stack_##name)} +#endif + +/// Access a Thread definition. +/// \param name name of the thread definition object. +/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osThread(name) \ +&os_thread_def_##name + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +osThreadId osThreadCreate (osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS. +osThreadId osThreadGetId (void); + +/// Terminate execution of a thread and remove it from Active Threads. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS. +osStatus osThreadTerminate (osThreadId thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS. +osStatus osThreadYield (void); + +/// Change priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS. +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); + +/// Get current priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the thread function. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS. +osPriority osThreadGetPriority (osThreadId thread_id); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] millisec time delay value +/// \return status code that indicates the execution status of the function. +osStatus osDelay (uint32_t millisec); + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS. +os_InRegs osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern osTimerDef_t os_timer_def_##name +#else // define the object +#define osTimerDef(name, function) \ +uint32_t os_timer_cb_##name[5]; \ +osTimerDef_t os_timer_def_##name = \ +{ (function), (os_timer_cb_##name) } +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS. +osTimerId osTimerCreate (osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec time delay value of the timer. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS. +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); + +/// Stop the timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS. +osStatus osTimerStop (osTimerId timer_id); + +/// Delete a timer that was created by \ref osTimerCreate. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS. +osStatus osTimerDelete (osTimerId timer_id); + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. +int32_t osSignalSet (osThreadId thread_id, int32_t signals); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS. +int32_t osSignalClear (osThreadId thread_id, int32_t signals); + +/// Get Signal Flags status of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalGet shall be consistent in every CMSIS-RTOS. +int32_t osSignalGet (osThreadId thread_id); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return event flag information or error code. +/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS. +os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Mutex Management ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern osMutexDef_t os_mutex_def_##name +#else // define the object +#define osMutexDef(name) \ +uint32_t os_mutex_cb_##name[3]; \ +osMutexDef_t os_mutex_def_##name = { (os_mutex_cb_##name) } +#endif + +/// Access a Mutex definition. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object. +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. +osMutexId osMutexCreate (osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); + +/// Release a Mutex that was obtained by \ref osMutexWait. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. +osStatus osMutexRelease (osMutexId mutex_id); + +/// Delete a Mutex that was created by \ref osMutexCreate. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS. +osStatus osMutexDelete (osMutexId mutex_id); + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern osSemaphoreDef_t os_semaphore_def_##name +#else // define the object +#define osSemaphoreDef(name) \ +uint32_t os_semaphore_cb_##name[2]; \ +osSemaphoreDef_t os_semaphore_def_##name = { (os_semaphore_cb_##name) } +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object used for managing resources. +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count number of available resources. +/// \return semaphore ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS. +osSemaphoreId osSemaphoreCreate (osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); + +/// Delete a Semaphore that was created by \ref osSemaphoreCreate. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); + +#endif // Semaphore available + + +// ==== Memory Pool Management Functions ==== + +#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of blocks (objects) in the memory pool. +/// \param type data type of a single block (object). +/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern osPoolDef_t os_pool_def_##name +#else // define the object +#define osPoolDef(name, no, type) \ +uint32_t os_pool_m_##name[3+((sizeof(type)+3)/4)*(no)]; \ +osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), (os_pool_m_##name) } +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a memory pool. +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS. +osPoolId osPoolCreate (osPoolDef_t *pool_def); + +/// Allocate a memory block from a memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a memory pool and set memory block to zero. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a specific memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block that is returned to the memory pool. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool Management available + + +// ==== Message Queue Management Functions ==== + +#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern osMessageQDef_t os_messageQ_def_##name +#else // define the object +#define osMessageQDef(name, queue_sz, type) \ +uint32_t os_messageQ_q_##name[4+(queue_sz)]; \ +osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), (os_messageQ_q_##name) } +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue. +/// \param[in] queue_def queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. +osMessageQId osMessageCreate (osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message or Wait for a Message from a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return event information that includes status code. +/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. +os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queues available + + +// ==== Mail Queue Management Functions ==== + +#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available + +/// \brief Create a Mail Queue Definition. +/// \param name name of the queue +/// \param queue_sz maximum number of messages in queue +/// \param type data type of a single message element +/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern osMailQDef_t os_mailQ_def_##name +#else // define the object +#define osMailQDef(name, queue_sz, type) \ +uint32_t os_mailQ_q_##name[4+(queue_sz)]; \ +uint32_t os_mailQ_m_##name[3+((sizeof(type)+3)/4)*(queue_sz)]; \ +void * os_mailQ_p_##name[2] = { (os_mailQ_q_##name), os_mailQ_m_##name }; \ +osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof(type), (os_mailQ_p_##name) } +#endif + +/// \brief Access a Mail Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize mail queue. +/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS. +osMailQId osMailCreate (osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block from a mail and set memory block to zero. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a mail to a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS. +osStatus osMailPut (osMailQId queue_id, void *mail); + +/// Get a mail from a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return event that contains mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS. +os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queues available + + +#ifdef __cplusplus +} +#endif + +#endif // _CMSIS_OS_H diff --git a/libraries/rtos/rtx/TARGET_ARM7/os_tcb.h b/libraries/rtos/rtx/TARGET_ARM7/os_tcb.h new file mode 100644 index 0000000000..8d9ceb8575 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/os_tcb.h @@ -0,0 +1,54 @@ +#ifndef OS_TCB_H +#define OS_TCB_H + +/* Types */ +typedef char S8; +typedef unsigned char U8; +typedef short S16; +typedef unsigned short U16; +typedef int S32; +typedef unsigned int U32; +typedef long long S64; +typedef unsigned long long U64; +typedef unsigned char BIT; +typedef unsigned int BOOL; +typedef void (*FUNCP)(void); +#define TCB_STACK_LR_OFFSET_BYTES (14*4) // prelast DWORD +#define TCB_STACK_LR_OFFSET_DWORDS (14) // prelast DWORD +#define TCB_STACK_R0_OFFSET_BYTES (1*4) // second DWORD +#define TCB_STACK_R0_OFFSET_DWORDS (1) // second DWORD + +typedef struct OS_TCB { + /* General part: identical for all implementations. */ + U8 cb_type; /* Control Block Type */ + U8 state; /* Task state */ + U8 prio; /* Execution priority */ + U8 task_id; /* Task ID value for optimized TCB access */ + struct OS_TCB *p_lnk; /* Link pointer for ready/sem. wait list */ + struct OS_TCB *p_rlnk; /* Link pointer for sem./mbx lst backwards */ + struct OS_TCB *p_dlnk; /* Link pointer for delay list */ + struct OS_TCB *p_blnk; /* Link pointer for delay list backwards */ + U16 delta_time; /* Time until time out */ + U16 interval_time; /* Time interval for periodic waits */ + U16 events; /* Event flags */ + U16 waits; /* Wait flags */ + void **msg; /* Direct message passing when task waits */ + + /* Hardware dependant part: specific for CM processor */ + U8 stack_frame; /* Stack frame: 0=Basic, 1=Extended */ + U8 reserved; + U16 priv_stack; /* Private stack size in bytes */ + U32 tsk_stack; /* Current task Stack pointer (R13) */ + U32 *stack; /* Pointer to Task Stack memory block */ + + /* Library dependant part */ +#if defined (__CC_ARM) && !defined (__MICROLIB) + /* A memory space for arm standard library. */ + U32 std_libspace[96/4]; +#endif + + /* Task entry point used for uVision debugger */ + FUNCP ptask; /* Task entry address */ +} *P_TCB; + +#endif diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_CMSIS.c b/libraries/rtos/rtx/TARGET_ARM7/rt_CMSIS.c new file mode 100644 index 0000000000..303b434edb --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_CMSIS.c @@ -0,0 +1,1852 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: rt_CMSIS.c + * Purpose: CMSIS RTOS API + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#define __CMSIS_GENERIC + +#include "core_arm7.h" + +#include "rt_TypeDef.h" +#include "RTX_Conf.h" +#include "rt_System.h" +#include "rt_Task.h" +#include "rt_Event.h" +#include "rt_List.h" +#include "rt_Time.h" +#include "rt_Mutex.h" +#include "rt_Semaphore.h" +#include "rt_Mailbox.h" +#include "rt_MemBox.h" +#include "rt_HAL_CM.h" + +#define os_thread_cb OS_TCB + +#include "cmsis_os.h" + +#if (osFeature_Signals != 16) +#error Invalid "osFeature_Signals" value! +#endif +#if (osFeature_Semaphore > 65535) +#error Invalid "osFeature_Semaphore" value! +#endif +#if (osFeature_Wait != 0) +#error osWait not supported! +#endif + + +// ==== Enumeration, structures, defines ==== + +// Service Calls defines + +#if defined (__CC_ARM) /* ARM Compiler */ + +#define __NO_RETURN __declspec(noreturn) + +#define osEvent_type osEvent +#define osEvent_ret_status ret +#define osEvent_ret_value ret +#define osEvent_ret_msg ret +#define osEvent_ret_mail ret + +#define osCallback_type osCallback +#define osCallback_ret ret + +#define SVC_0_1(f,t,...) \ +__svc_indirect(0) t _##f (t(*)()); \ + t f (void); \ +__attribute__((always_inline)) \ +static __inline t __##f (void) { \ + return _##f(f); \ +} + +#define SVC_1_1(f,t,t1,...) \ +__svc_indirect(0) t _##f (t(*)(t1),t1); \ + t f (t1 a1); \ +__attribute__((always_inline)) \ +static __inline t __##f (t1 a1) { \ + return _##f(f,a1); \ +} + +#define SVC_2_1(f,t,t1,t2,...) \ +__svc_indirect(0) t _##f (t(*)(t1,t2),t1,t2); \ + t f (t1 a1, t2 a2); \ +__attribute__((always_inline)) \ +static __inline t __##f (t1 a1, t2 a2) { \ + return _##f(f,a1,a2); \ +} + +#define SVC_3_1(f,t,t1,t2,t3,...) \ +__svc_indirect(0) t _##f (t(*)(t1,t2,t3),t1,t2,t3); \ + t f (t1 a1, t2 a2, t3 a3); \ +__attribute__((always_inline)) \ +static __inline t __##f (t1 a1, t2 a2, t3 a3) { \ + return _##f(f,a1,a2,a3); \ +} + +#define SVC_4_1(f,t,t1,t2,t3,t4,...) \ +__svc_indirect(0) t _##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4); \ + t f (t1 a1, t2 a2, t3 a3, t4 a4); \ +__attribute__((always_inline)) \ +static __inline t __##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ + return _##f(f,a1,a2,a3,a4); \ +} + +#define SVC_1_2 SVC_1_1 +#define SVC_1_3 SVC_1_1 +#define SVC_2_3 SVC_2_1 + +#elif defined (__GNUC__) /* GNU Compiler */ + +#define __NO_RETURN __attribute__((noreturn)) + +typedef uint32_t __attribute__((vector_size(8))) ret64; +typedef uint32_t __attribute__((vector_size(16))) ret128; + +#define RET_pointer __r0 +#define RET_int32_t __r0 +#define RET_osStatus __r0 +#define RET_osPriority __r0 +#define RET_osEvent {(osStatus)__r0, {(uint32_t)__r1}, {(void *)__r2}} +#define RET_osCallback {(void *)__r0, (void *)__r1} + +#define osEvent_type ret128 +#define osEvent_ret_status (ret128){ret.status} +#define osEvent_ret_value (ret128){ret.status, ret.value.v} +#define osEvent_ret_msg (ret128){ret.status, ret.value.v, (uint32_t)ret.def.message_id} +#define osEvent_ret_mail (ret128){ret.status, ret.value.v, (uint32_t)ret.def.mail_id} + +#define osCallback_type ret64 +#define osCallback_ret (ret64) {(uint32_t)ret.fp, (uint32_t)ret.arg} + +#define SVC_ArgN(n) \ + register int __r##n __asm("r"#n); + +#define SVC_ArgR(n,t,a) \ + register t __r##n __asm("r"#n) = a; + +#define SVC_Arg0() \ + SVC_ArgN(0) \ + SVC_ArgN(1) \ + SVC_ArgN(2) \ + SVC_ArgN(3) + +#define SVC_Arg1(t1) \ + SVC_ArgR(0,t1,a1) \ + SVC_ArgN(1) \ + SVC_ArgN(2) \ + SVC_ArgN(3) + +#define SVC_Arg2(t1,t2) \ + SVC_ArgR(0,t1,a1) \ + SVC_ArgR(1,t2,a2) \ + SVC_ArgN(2) \ + SVC_ArgN(3) + +#define SVC_Arg3(t1,t2,t3) \ + SVC_ArgR(0,t1,a1) \ + SVC_ArgR(1,t2,a2) \ + SVC_ArgR(2,t3,a3) \ + SVC_ArgN(3) + +#define SVC_Arg4(t1,t2,t3,t4) \ + SVC_ArgR(0,t1,a1) \ + SVC_ArgR(1,t2,a2) \ + SVC_ArgR(2,t3,a3) \ + SVC_ArgR(3,t4,a4) + +#if (defined (__CORTEX_M0)) || defined (__CORTEX_M0PLUS) +#define SVC_Call(f) \ + __asm volatile \ + ( \ + "ldr r7,="#f"\n\t" \ + "mov r12,r7\n\t" \ + "svc 0" \ + : "=r" (__r0), "=r" (__r1), "=r" (__r2), "=r" (__r3) \ + : "r" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) \ + : "r7", "r12", "lr", "cc" \ + ); +#else +#define SVC_Call(f) \ + __asm volatile \ + ( \ + "ldr r12,="#f"\n\t" \ + "svc 0" \ + : "=r" (__r0), "=r" (__r1), "=r" (__r2), "=r" (__r3) \ + : "r" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) \ + : "r12", "lr", "cc" \ + ); +#endif + +#define SVC_0_1(f,t,rv) \ +__attribute__((always_inline)) \ +static inline t __##f (void) { \ + SVC_Arg0(); \ + SVC_Call(f); \ + return (t) rv; \ +} + +#define SVC_1_1(f,t,t1,rv) \ +__attribute__((always_inline)) \ +static inline t __##f (t1 a1) { \ + SVC_Arg1(t1); \ + SVC_Call(f); \ + return (t) rv; \ +} + +#define SVC_2_1(f,t,t1,t2,rv) \ +__attribute__((always_inline)) \ +static inline t __##f (t1 a1, t2 a2) { \ + SVC_Arg2(t1,t2); \ + SVC_Call(f); \ + return (t) rv; \ +} + +#define SVC_3_1(f,t,t1,t2,t3,rv) \ +__attribute__((always_inline)) \ +static inline t __##f (t1 a1, t2 a2, t3 a3) { \ + SVC_Arg3(t1,t2,t3); \ + SVC_Call(f); \ + return (t) rv; \ +} + +#define SVC_4_1(f,t,t1,t2,t3,t4,rv) \ +__attribute__((always_inline)) \ +static inline t __##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ + SVC_Arg4(t1,t2,t3,t4); \ + SVC_Call(f); \ + return (t) rv; \ +} + +#define SVC_1_2 SVC_1_1 +#define SVC_1_3 SVC_1_1 +#define SVC_2_3 SVC_2_1 + +#elif defined (__ICCARM__) /* IAR Compiler */ + +#define __NO_RETURN __noreturn + +#define osEvent_type osEvent +#define osEvent_ret_status ret +#define osEvent_ret_value ret +#define osEvent_ret_msg ret +#define osEvent_ret_mail ret + +#define osCallback_type osCallback +#define osCallback_ret ret + +#define RET_osEvent osEvent +#define RET_osCallback osCallback + +#define SVC_Setup(f) \ + __asm( \ + "mov r12,%0\n" \ + :: "r"(&f): "r12" \ + ); + + +#define SVC_0_1(f,t,...) \ +t f (void); \ +_Pragma("swi_number=0") __swi t _##f (void); \ +static inline t __##f (void) { \ + SVC_Setup(f); \ + return _##f(); \ +} + +#define SVC_1_1(f,t,t1,...) \ +t f (t1 a1); \ +_Pragma("swi_number=0") __swi t _##f (t1 a1); \ +static inline t __##f (t1 a1) { \ + SVC_Setup(f); \ + return _##f(a1); \ +} + +#define SVC_2_1(f,t,t1,t2,...) \ +t f (t1 a1, t2 a2); \ +_Pragma("swi_number=0") __swi t _##f (t1 a1, t2 a2); \ +static inline t __##f (t1 a1, t2 a2) { \ + SVC_Setup(f); \ + return _##f(a1,a2); \ +} + +#define SVC_3_1(f,t,t1,t2,t3,...) \ +t f (t1 a1, t2 a2, t3 a3); \ +_Pragma("swi_number=0") __swi t _##f (t1 a1, t2 a2, t3 a3); \ +static inline t __##f (t1 a1, t2 a2, t3 a3) { \ + SVC_Setup(f); \ + return _##f(a1,a2,a3); \ +} + +#define SVC_4_1(f,t,t1,t2,t3,t4,...) \ +t f (t1 a1, t2 a2, t3 a3, t4 a4); \ +_Pragma("swi_number=0") __swi t _##f (t1 a1, t2 a2, t3 a3, t4 a4); \ +static inline t __##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ + SVC_Setup(f); \ + return _##f(a1,a2,a3,a4); \ +} + +#define SVC_1_2 SVC_1_1 +#define SVC_1_3 SVC_1_1 +#define SVC_2_3 SVC_2_1 + +#endif + + +// Callback structure +typedef struct { + void *fp; // Function pointer + void *arg; // Function argument +} osCallback; + + +// OS Section definitions +#ifdef OS_SECTIONS_LINK_INFO +extern const uint32_t os_section_id$$Base; +extern const uint32_t os_section_id$$Limit; +#endif + +// OS Timers external resources +extern osThreadDef_t os_thread_def_osTimerThread; +extern osThreadId osThreadId_osTimerThread; +extern osMessageQDef_t os_messageQ_def_osTimerMessageQ; +extern osMessageQId osMessageQId_osTimerMessageQ; + + +// ==== Helper Functions ==== + +/// Convert timeout in millisec to system ticks +static uint32_t rt_ms2tick (uint32_t millisec) { + uint32_t tick; + + if (millisec == osWaitForever) return 0xFFFF; // Indefinite timeout + if (millisec > 4000000) return 0xFFFE; // Max ticks supported + + tick = ((1000 * millisec) + os_clockrate - 1) / os_clockrate; + if (tick > 0xFFFE) return 0xFFFE; + + return tick; +} + +/// Convert Thread ID to TCB pointer +static P_TCB rt_tid2ptcb (osThreadId thread_id) { + P_TCB ptcb; + + if (thread_id == NULL) return NULL; + + if ((uint32_t)thread_id & 3) return NULL; + +#ifdef OS_SECTIONS_LINK_INFO + if ((os_section_id$$Base != 0) && (os_section_id$$Limit != 0)) { + if (thread_id < (osThreadId)os_section_id$$Base) return NULL; + if (thread_id >= (osThreadId)os_section_id$$Limit) return NULL; + } +#endif + + ptcb = thread_id; + + if (ptcb->cb_type != TCB) return NULL; + + return ptcb; +} + +/// Convert ID pointer to Object pointer +static void *rt_id2obj (void *id) { + + if ((uint32_t)id & 3) return NULL; + +#ifdef OS_SECTIONS_LINK_INFO + if ((os_section_id$$Base != 0) && (os_section_id$$Limit != 0)) { + if (id < (void *)os_section_id$$Base) return NULL; + if (id >= (void *)os_section_id$$Limit) return NULL; + } +#endif + + return id; +} + + +// ==== Kernel Control ==== + +uint8_t os_initialized; // Kernel Initialized flag +uint8_t os_running; // Kernel Running flag + +// Kernel Control Service Calls declarations +SVC_0_1(svcKernelInitialize, osStatus, RET_osStatus) +SVC_0_1(svcKernelStart, osStatus, RET_osStatus) +SVC_0_1(svcKernelRunning, int32_t, RET_int32_t) + +extern void sysThreadError (osStatus status); +osThreadId svcThreadCreate (osThreadDef_t *thread_def, void *argument); +osMessageQId svcMessageCreate (osMessageQDef_t *queue_def, osThreadId thread_id); + +// Kernel Control Service Calls + +/// Initialize the RTOS Kernel for creating objects +osStatus svcKernelInitialize (void) { + if (os_initialized) return osOK; + + rt_sys_init(); // RTX System Initialization + os_tsk.run->prio = 255; // Highest priority + + sysThreadError(osOK); + + os_initialized = 1; + + return osOK; +} + +/// Start the RTOS Kernel +osStatus svcKernelStart (void) { + + if (os_running) return osOK; + + // Create OS Timers resources (Message Queue & Thread) + osMessageQId_osTimerMessageQ = svcMessageCreate (&os_messageQ_def_osTimerMessageQ, NULL); + osThreadId_osTimerThread = svcThreadCreate(&os_thread_def_osTimerThread, NULL); + + rt_tsk_prio(0, 0); // Lowest priority +// __set_SP(os_tsk.run->tsk_stack + 8*4); // New context + os_tsk.run = NULL; // Force context switch + + rt_sys_start(); + + os_running = 1; + + return osOK; +} + +/// Check if the RTOS kernel is already started +int32_t svcKernelRunning(void) { + return os_running; +} + +// Kernel Control Public API + +/// Initialize the RTOS Kernel for creating objects +osStatus osKernelInitialize (void) { + if (__get_CONTROL() == MODE_IRQ) return osErrorISR; // Not allowed in ISR + if (__get_CONTROL() == MODE_SUPERVISOR) { // Privileged mode + return svcKernelInitialize(); + } else { + return __svcKernelInitialize(); + } +} + +/// Start the RTOS Kernel +osStatus osKernelStart (void) { + + if (__get_CONTROL() == MODE_IRQ) return osErrorISR; // Not allowed in ISR + switch (__get_CONTROL()) { + case MODE_SUPERVISOR: // Privileged mode + break; + case MODE_USER: + case MODE_SYSTEM: // Unprivileged mode + return osErrorOS; + default: // Other invalid modes + return osErrorOS; + break; + } + return svcKernelStart(); +} + +/// Check if the RTOS kernel is already started +int32_t osKernelRunning(void) { + if ((__get_CONTROL() == MODE_IRQ) || (__get_CONTROL() == MODE_SUPERVISOR)) { + // in ISR or Privileged + return os_running; + } else { + return __svcKernelRunning(); + } +} + + +// ==== Thread Management ==== + +__NO_RETURN void osThreadExit (void); + +// Thread Service Calls declarations +SVC_2_1(svcThreadCreate, osThreadId, osThreadDef_t *, void *, RET_pointer) +SVC_0_1(svcThreadGetId, osThreadId, RET_pointer) +SVC_1_1(svcThreadTerminate, osStatus, osThreadId, RET_osStatus) +SVC_0_1(svcThreadYield, osStatus, RET_osStatus) +SVC_2_1(svcThreadSetPriority, osStatus, osThreadId, osPriority, RET_osStatus) +SVC_1_1(svcThreadGetPriority, osPriority, osThreadId, RET_osPriority) + +// Thread Service Calls +extern OS_TID rt_get_TID (void); +extern void rt_init_context (P_TCB p_TCB, U8 priority, FUNCP task_body); + +/// Create a thread and add it to Active Threads and set it to state READY +osThreadId svcThreadCreate (osThreadDef_t *thread_def, void *argument) { + P_TCB ptcb; + + if ((thread_def == NULL) || + (thread_def->pthread == NULL) || + (thread_def->tpriority < osPriorityIdle) || + (thread_def->tpriority > osPriorityRealtime) || + (thread_def->stacksize == 0) || + (thread_def->stack_pointer == NULL) ) { + sysThreadError(osErrorParameter); + return NULL; + } + + U8 priority = thread_def->tpriority - osPriorityIdle + 1; + P_TCB task_context = &thread_def->tcb; + + /* If "size != 0" use a private user provided stack. */ + task_context->stack = (U32*)thread_def->stack_pointer; + task_context->priv_stack = thread_def->stacksize; + /* Pass parameter 'argv' to 'rt_init_context' */ + task_context->msg = argument; + /* For 'size == 0' system allocates the user stack from the memory pool. */ + rt_init_context (task_context, priority, (FUNCP)thread_def->pthread); + + /* Find a free entry in 'os_active_TCB' table. */ + OS_TID tsk = rt_get_TID (); + os_active_TCB[tsk-1] = task_context; + task_context->task_id = tsk; + DBG_TASK_NOTIFY(task_context, __TRUE); + rt_dispatch (task_context); + + ptcb = (P_TCB)os_active_TCB[tsk - 1]; // TCB pointer + + *((uint32_t *)ptcb->tsk_stack + TCB_STACK_LR_OFFSET_DWORDS) = (uint32_t)osThreadExit; /* LR = osThreadExit */ + + return ptcb; +} + +/// Return the thread ID of the current running thread +osThreadId svcThreadGetId (void) { + OS_TID tsk; + + tsk = rt_tsk_self(); + if (tsk == 0) return NULL; + return (P_TCB)os_active_TCB[tsk - 1]; +} + +/// Terminate execution of a thread and remove it from ActiveThreads +osStatus svcThreadTerminate (osThreadId thread_id) { + OS_RESULT res; + P_TCB ptcb; + + ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer + if (ptcb == NULL) return osErrorParameter; + + res = rt_tsk_delete(ptcb->task_id); // Delete task + + if (res == OS_R_NOK) return osErrorResource; // Delete task failed + + return osOK; +} + +/// Pass control to next thread that is in state READY +osStatus svcThreadYield (void) { + rt_tsk_pass(); // Pass control to next task + return osOK; +} + +/// Change priority of an active thread +osStatus svcThreadSetPriority (osThreadId thread_id, osPriority priority) { + OS_RESULT res; + P_TCB ptcb; + + ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer + if (ptcb == NULL) return osErrorParameter; + + if ((priority < osPriorityIdle) || (priority > osPriorityRealtime)) { + return osErrorValue; + } + + res = rt_tsk_prio( // Change task priority + ptcb->task_id, // Task ID + priority - osPriorityIdle + 1 // New task priority + ); + + if (res == OS_R_NOK) return osErrorResource; // Change task priority failed + + return osOK; +} + +/// Get current priority of an active thread +osPriority svcThreadGetPriority (osThreadId thread_id) { + P_TCB ptcb; + + ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer + if (ptcb == NULL) return osPriorityError; + + return (osPriority)(ptcb->prio - 1 + osPriorityIdle); +} + + +// Thread Public API + +/// Create a thread and add it to Active Threads and set it to state READY +osThreadId osThreadCreate (osThreadDef_t *thread_def, void *argument) { + if (__get_CONTROL() == MODE_IRQ) return NULL; // Not allowed in ISR + if ((__get_CONTROL() == MODE_SUPERVISOR) && (os_running == 0)) { + // Privileged and not running + return svcThreadCreate(thread_def, argument); + } else { + return __svcThreadCreate(thread_def, argument); + } +} + +/// Return the thread ID of the current running thread +osThreadId osThreadGetId (void) { + if (__get_CONTROL() == MODE_IRQ) return NULL; // Not allowed in ISR + return __svcThreadGetId(); +} + +/// Terminate execution of a thread and remove it from ActiveThreads +osStatus osThreadTerminate (osThreadId thread_id) { + if (__get_CONTROL() == MODE_IRQ) return osErrorISR; // Not allowed in ISR + return __svcThreadTerminate(thread_id); +} + +/// Pass control to next thread that is in state READY +osStatus osThreadYield (void) { + if (__get_CONTROL() == MODE_IRQ) return osErrorISR; // Not allowed in ISR + return __svcThreadYield(); +} + +/// Change priority of an active thread +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority) { + if (__get_CONTROL() == MODE_IRQ) return osErrorISR; // Not allowed in ISR + return __svcThreadSetPriority(thread_id, priority); +} + +/// Get current priority of an active thread +osPriority osThreadGetPriority (osThreadId thread_id) { + if (__get_CONTROL() == MODE_IRQ) return osPriorityError;// Not allowed in ISR + return __svcThreadGetPriority(thread_id); +} + +/// INTERNAL - Not Public +/// Auto Terminate Thread on exit (used implicitly when thread exists) +__NO_RETURN void osThreadExit (void) { + __svcThreadTerminate(__svcThreadGetId()); + for (;;); // Should never come here +} + + +// ==== Generic Wait Functions ==== + +// Generic Wait Service Calls declarations +SVC_1_1(svcDelay, osStatus, uint32_t, RET_osStatus) +#if osFeature_Wait != 0 +SVC_1_3(svcWait, os_InRegs osEvent, uint32_t, RET_osEvent) +#endif + +// Generic Wait Service Calls + +/// Wait for Timeout (Time Delay) +osStatus svcDelay (uint32_t millisec) { + if (millisec == 0) return osOK; + rt_dly_wait(rt_ms2tick(millisec)); + return osEventTimeout; +} + +/// Wait for Signal, Message, Mail, or Timeout +#if osFeature_Wait != 0 +os_InRegs osEvent_type svcWait (uint32_t millisec) { + osEvent ret; + + if (millisec == 0) { + ret.status = osOK; + return osEvent_ret_status; + } + + /* To Do: osEventSignal, osEventMessage, osEventMail */ + rt_dly_wait(rt_ms2tick(millisec)); + ret.status = osEventTimeout; + + return osEvent_ret_status; +} +#endif + + +// Generic Wait API + +/// Wait for Timeout (Time Delay) +osStatus osDelay (uint32_t millisec) { + if (__get_CONTROL() == MODE_IRQ) return osErrorISR; // Not allowed in ISR + return __svcDelay(millisec); +} + +/// Wait for Signal, Message, Mail, or Timeout +os_InRegs osEvent osWait (uint32_t millisec) { + osEvent ret; + +#if osFeature_Wait == 0 + ret.status = osErrorOS; + return ret; +#else + if (__get_CONTROL() == MODE_IRQ) { // Not allowed in ISR + ret.status = osErrorISR; + return ret; + } + return __svcWait(millisec); +#endif +} + + +// ==== Timer Management ==== + +// Timer definitions +#define osTimerInvalid 0 +#define osTimerStopped 1 +#define osTimerRunning 2 + +// Timer structures + +typedef struct os_timer_cb_ { // Timer Control Block + struct os_timer_cb_ *next; // Pointer to next active Timer + uint8_t state; // Timer State + uint8_t type; // Timer Type (Periodic/One-shot) + uint16_t reserved; // Reserved + uint16_t tcnt; // Timer Delay Count + uint16_t icnt; // Timer Initial Count + void *arg; // Timer Function Argument + osTimerDef_t *timer; // Pointer to Timer definition +} os_timer_cb; + +// Timer variables +os_timer_cb *os_timer_head; // Pointer to first active Timer + + +// Timer Helper Functions + +// Insert Timer into the list sorted by time +static void rt_timer_insert (os_timer_cb *pt, uint32_t tcnt) { + os_timer_cb *p, *prev; + + prev = NULL; + p = os_timer_head; + while (p != NULL) { + if (tcnt < p->tcnt) break; + tcnt -= p->tcnt; + prev = p; + p = p->next; + } + pt->next = p; + pt->tcnt = (uint16_t)tcnt; + if (p != NULL) { + p->tcnt -= pt->tcnt; + } + if (prev != NULL) { + prev->next = pt; + } else { + os_timer_head = pt; + } +} + +// Remove Timer from the list +static int rt_timer_remove (os_timer_cb *pt) { + os_timer_cb *p, *prev; + + prev = NULL; + p = os_timer_head; + while (p != NULL) { + if (p == pt) break; + prev = p; + p = p->next; + } + if (p == NULL) return -1; + if (prev != NULL) { + prev->next = pt->next; + } else { + os_timer_head = pt->next; + } + if (pt->next != NULL) { + pt->next->tcnt += pt->tcnt; + } + + return 0; +} + + +// Timer Service Calls declarations +SVC_3_1(svcTimerCreate, osTimerId, osTimerDef_t *, os_timer_type, void *, RET_pointer) +SVC_2_1(svcTimerStart, osStatus, osTimerId, uint32_t, RET_osStatus) +SVC_1_1(svcTimerStop, osStatus, osTimerId, RET_osStatus) +SVC_1_1(svcTimerDelete, osStatus, osTimerId, RET_osStatus) +SVC_1_2(svcTimerCall, os_InRegs osCallback, osTimerId, RET_osCallback) + +// Timer Management Service Calls + +/// Create timer +osTimerId svcTimerCreate (osTimerDef_t *timer_def, os_timer_type type, void *argument) { + os_timer_cb *pt; + + if ((timer_def == NULL) || (timer_def->ptimer == NULL)) { + sysThreadError(osErrorParameter); + return NULL; + } + + pt = timer_def->timer; + if (pt == NULL) { + sysThreadError(osErrorParameter); + return NULL; + } + + if ((type != osTimerOnce) && (type != osTimerPeriodic)) { + sysThreadError(osErrorValue); + return NULL; + } + + if (osThreadId_osTimerThread == NULL) { + sysThreadError(osErrorResource); + return NULL; + } + + if (pt->state != osTimerInvalid){ + sysThreadError(osErrorResource); + return NULL; + } + + pt->state = osTimerStopped; + pt->type = (uint8_t)type; + pt->arg = argument; + pt->timer = timer_def; + + return (osTimerId)pt; +} + +/// Start or restart timer +osStatus svcTimerStart (osTimerId timer_id, uint32_t millisec) { + os_timer_cb *pt; + uint32_t tcnt; + + pt = rt_id2obj(timer_id); + if (pt == NULL) return osErrorParameter; + + tcnt = rt_ms2tick(millisec); + if (tcnt == 0) return osErrorValue; + + switch (pt->state) { + case osTimerRunning: + if (rt_timer_remove(pt) != 0) { + return osErrorResource; + } + break; + case osTimerStopped: + pt->state = osTimerRunning; + pt->icnt = (uint16_t)tcnt; + break; + default: + return osErrorResource; + } + + rt_timer_insert(pt, tcnt); + + return osOK; +} + +/// Stop timer +osStatus svcTimerStop (osTimerId timer_id) { + os_timer_cb *pt; + + pt = rt_id2obj(timer_id); + if (pt == NULL) return osErrorParameter; + + if (pt->state != osTimerRunning) return osErrorResource; + + pt->state = osTimerStopped; + + if (rt_timer_remove(pt) != 0) { + return osErrorResource; + } + + return osOK; +} + +/// Delete timer +osStatus svcTimerDelete (osTimerId timer_id) { + os_timer_cb *pt; + + pt = rt_id2obj(timer_id); + if (pt == NULL) return osErrorParameter; + + switch (pt->state) { + case osTimerRunning: + rt_timer_remove(pt); + break; + case osTimerStopped: + break; + default: + return osErrorResource; + } + + pt->state = osTimerInvalid; + + return osOK; +} + +/// Get timer callback parameters +os_InRegs osCallback_type svcTimerCall (osTimerId timer_id) { + os_timer_cb *pt; + osCallback ret; + + pt = rt_id2obj(timer_id); + if (pt == NULL) { + ret.fp = NULL; + ret.arg = NULL; + return osCallback_ret; + } + + ret.fp = (void *)pt->timer->ptimer; + ret.arg = pt->arg; + + return osCallback_ret; +} + +static __INLINE osStatus isrMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Timer Tick (called each SysTick) +void sysTimerTick (void) { + os_timer_cb *pt, *p; + + p = os_timer_head; + if (p == NULL) return; + + p->tcnt--; + while ((p != NULL) && (p->tcnt == 0)) { + pt = p; + p = p->next; + os_timer_head = p; + isrMessagePut(osMessageQId_osTimerMessageQ, (uint32_t)pt, 0); + if (pt->type == osTimerPeriodic) { + rt_timer_insert(pt, pt->icnt); + } else { + pt->state = osTimerStopped; + } + } +} + + +// Timer Management Public API + +/// Create timer +osTimerId osTimerCreate (osTimerDef_t *timer_def, os_timer_type type, void *argument) { + if (__get_CONTROL() == MODE_IRQ) return NULL; // Not allowed in ISR + if ((__get_CONTROL() == MODE_SUPERVISOR) && (os_running == 0)) { + // Privileged and not running + return svcTimerCreate(timer_def, type, argument); + } else { + return __svcTimerCreate(timer_def, type, argument); + } +} + +/// Start or restart timer +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec) { + if (__get_CONTROL() == MODE_IRQ) return osErrorISR; // Not allowed in ISR + return __svcTimerStart(timer_id, millisec); +} + +/// Stop timer +osStatus osTimerStop (osTimerId timer_id) { + if (__get_CONTROL() == MODE_IRQ) return osErrorISR; // Not allowed in ISR + return __svcTimerStop(timer_id); +} + +/// Delete timer +osStatus osTimerDelete (osTimerId timer_id) { + if (__get_CONTROL() == MODE_IRQ) return osErrorISR; // Not allowed in ISR + return __svcTimerDelete(timer_id); +} + +/// INTERNAL - Not Public +/// Get timer callback parameters (used by OS Timer Thread) +os_InRegs osCallback osTimerCall (osTimerId timer_id) { + return __svcTimerCall(timer_id); +} + + +// Timer Thread +__NO_RETURN void osTimerThread (void const *argument) { + osCallback cb; + osEvent evt; + + for (;;) { + evt = osMessageGet(osMessageQId_osTimerMessageQ, osWaitForever); + if (evt.status == osEventMessage) { + cb = osTimerCall(evt.value.p); + if (cb.fp != NULL) { + (*(os_ptimer)cb.fp)(cb.arg); + } + } + } +} + + +// ==== Signal Management ==== + +// Signal Service Calls declarations +SVC_2_1(svcSignalSet, int32_t, osThreadId, int32_t, RET_int32_t) +SVC_2_1(svcSignalClear, int32_t, osThreadId, int32_t, RET_int32_t) +SVC_1_1(svcSignalGet, int32_t, osThreadId, RET_int32_t) +SVC_2_3(svcSignalWait, os_InRegs osEvent, int32_t, uint32_t, RET_osEvent) + +// Signal Service Calls + +/// Set the specified Signal Flags of an active thread +int32_t svcSignalSet (osThreadId thread_id, int32_t signals) { + P_TCB ptcb; + int32_t sig; + + ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer + if (ptcb == NULL) return 0x80000000; + + if (signals & (0xFFFFFFFF << osFeature_Signals)) return 0x80000000; + + sig = ptcb->events; // Previous signal flags + + rt_evt_set(signals, ptcb->task_id); // Set event flags + + return sig; +} + +/// Clear the specified Signal Flags of an active thread +int32_t svcSignalClear (osThreadId thread_id, int32_t signals) { + P_TCB ptcb; + int32_t sig; + + ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer + if (ptcb == NULL) return 0x80000000; + + if (signals & (0xFFFFFFFF << osFeature_Signals)) return 0x80000000; + + sig = ptcb->events; // Previous signal flags + + rt_evt_clr(signals, ptcb->task_id); // Clear event flags + + return sig; +} + +/// Get Signal Flags status of an active thread +int32_t svcSignalGet (osThreadId thread_id) { + P_TCB ptcb; + + ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer + if (ptcb == NULL) return 0x80000000; + + return ptcb->events; // Return event flags +} + +/// Wait for one or more Signal Flags to become signaled for the current RUNNING thread +os_InRegs osEvent_type svcSignalWait (int32_t signals, uint32_t millisec) { + OS_RESULT res; + osEvent ret; + + if (signals & (0xFFFFFFFF << osFeature_Signals)) { + ret.status = osErrorValue; + return osEvent_ret_status; + } + + if (signals != 0) { // Wait for all specified signals + res = rt_evt_wait(signals, rt_ms2tick(millisec), __TRUE); + } else { // Wait for any signal + res = rt_evt_wait(0xFFFF, rt_ms2tick(millisec), __FALSE); + } + + if (res == OS_R_EVT) { + ret.status = osEventSignal; + ret.value.signals = signals ? signals : os_tsk.run->waits; + } else { + ret.status = millisec ? osEventTimeout : osOK; + ret.value.signals = 0; + } + + return osEvent_ret_value; +} + + +// Signal ISR Calls + +/// Set the specified Signal Flags of an active thread +static __INLINE int32_t isrSignalSet (osThreadId thread_id, int32_t signals) { + P_TCB ptcb; + int32_t sig; + + ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer + if (ptcb == NULL) return 0x80000000; + + if (signals & (0xFFFFFFFF << osFeature_Signals)) return 0x80000000; + + sig = ptcb->events; // Previous signal flags + + isr_evt_set(signals, ptcb->task_id); // Set event flags + + return sig; +} + + +// Signal Public API + +/// Set the specified Signal Flags of an active thread +int32_t osSignalSet (osThreadId thread_id, int32_t signals) { + if (__get_CONTROL() == MODE_IRQ) { // in ISR + return isrSignalSet(thread_id, signals); + } else { // in Thread + return __svcSignalSet(thread_id, signals); + } +} + +/// Clear the specified Signal Flags of an active thread +int32_t osSignalClear (osThreadId thread_id, int32_t signals) { + if (__get_CONTROL() == MODE_IRQ) return osErrorISR; // Not allowed in ISR + return __svcSignalClear(thread_id, signals); +} + +/// Get Signal Flags status of an active thread +int32_t osSignalGet (osThreadId thread_id) { + if (__get_CONTROL() == MODE_IRQ) return osErrorISR; // Not allowed in ISR + return __svcSignalGet(thread_id); +} + +/// Wait for one or more Signal Flags to become signaled for the current RUNNING thread +os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec) { + osEvent ret; + + if (__get_CONTROL() == MODE_IRQ) { // Not allowed in ISR + ret.status = osErrorISR; + return ret; + } + return __svcSignalWait(signals, millisec); +} + + +// ==== Mutex Management ==== + +// Mutex Service Calls declarations +SVC_1_1(svcMutexCreate, osMutexId, osMutexDef_t *, RET_pointer) +SVC_2_1(svcMutexWait, osStatus, osMutexId, uint32_t, RET_osStatus) +SVC_1_1(svcMutexRelease, osStatus, osMutexId, RET_osStatus) +SVC_1_1(svcMutexDelete, osStatus, osMutexId, RET_osStatus) + +// Mutex Service Calls + +/// Create and Initialize a Mutex object +osMutexId svcMutexCreate (osMutexDef_t *mutex_def) { + OS_ID mut; + + if (mutex_def == NULL) { + sysThreadError(osErrorParameter); + return NULL; + } + + mut = mutex_def->mutex; + if (mut == NULL) { + sysThreadError(osErrorParameter); + return NULL; + } + + if (((P_MUCB)mut)->cb_type != 0) { + sysThreadError(osErrorParameter); + return NULL; + } + + rt_mut_init(mut); // Initialize Mutex + + return mut; +} + +/// Wait until a Mutex becomes available +osStatus svcMutexWait (osMutexId mutex_id, uint32_t millisec) { + OS_ID mut; + OS_RESULT res; + + mut = rt_id2obj(mutex_id); + if (mut == NULL) return osErrorParameter; + + if (((P_MUCB)mut)->cb_type != MUCB) return osErrorParameter; + + res = rt_mut_wait(mut, rt_ms2tick(millisec)); // Wait for Mutex + + if (res == OS_R_TMO) { + return (millisec ? osErrorTimeoutResource : osErrorResource); + } + + return osOK; +} + +/// Release a Mutex that was obtained with osMutexWait +osStatus svcMutexRelease (osMutexId mutex_id) { + OS_ID mut; + OS_RESULT res; + + mut = rt_id2obj(mutex_id); + if (mut == NULL) return osErrorParameter; + + if (((P_MUCB)mut)->cb_type != MUCB) return osErrorParameter; + + res = rt_mut_release(mut); // Release Mutex + + if (res == OS_R_NOK) return osErrorResource; // Thread not owner or Zero Counter + + return osOK; +} + +/// Delete a Mutex that was created by osMutexCreate +osStatus svcMutexDelete (osMutexId mutex_id) { + OS_ID mut; + + mut = rt_id2obj(mutex_id); + if (mut == NULL) return osErrorParameter; + + if (((P_MUCB)mut)->cb_type != MUCB) return osErrorParameter; + + rt_mut_delete(mut); // Release Mutex + + return osOK; +} + + +// Mutex Public API + +/// Create and Initialize a Mutex object +osMutexId osMutexCreate (osMutexDef_t *mutex_def) { + if (__get_CONTROL() == MODE_IRQ) return NULL; // Not allowed in ISR + if ((__get_CONTROL() == MODE_SUPERVISOR) && (os_running == 0)) { + // Privileged and not running + return svcMutexCreate(mutex_def); + } else { + return __svcMutexCreate(mutex_def); + } +} + +/// Wait until a Mutex becomes available +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec) { + if (__get_CONTROL() == MODE_IRQ) return osErrorISR; // Not allowed in ISR + return __svcMutexWait(mutex_id, millisec); +} + +/// Release a Mutex that was obtained with osMutexWait +osStatus osMutexRelease (osMutexId mutex_id) { + if (__get_CONTROL() == MODE_IRQ) return osErrorISR; // Not allowed in ISR + return __svcMutexRelease(mutex_id); +} + +/// Delete a Mutex that was created by osMutexCreate +osStatus osMutexDelete (osMutexId mutex_id) { + if (__get_CONTROL() == MODE_IRQ) return osErrorISR; // Not allowed in ISR + return __svcMutexDelete(mutex_id); +} + + +// ==== Semaphore Management ==== + +// Semaphore Service Calls declarations +SVC_2_1(svcSemaphoreCreate, osSemaphoreId, const osSemaphoreDef_t *, int32_t, RET_pointer) +SVC_2_1(svcSemaphoreWait, int32_t, osSemaphoreId, uint32_t, RET_int32_t) +SVC_1_1(svcSemaphoreRelease, osStatus, osSemaphoreId, RET_osStatus) +SVC_1_1(svcSemaphoreDelete, osStatus, osSemaphoreId, RET_osStatus) + +// Semaphore Service Calls + +/// Create and Initialize a Semaphore object +osSemaphoreId svcSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) { + OS_ID sem; + + if (semaphore_def == NULL) { + sysThreadError(osErrorParameter); + return NULL; + } + + sem = semaphore_def->semaphore; + if (sem == NULL) { + sysThreadError(osErrorParameter); + return NULL; + } + + if (((P_SCB)sem)->cb_type != 0) { + sysThreadError(osErrorParameter); + return NULL; + } + + if (count > osFeature_Semaphore) { + sysThreadError(osErrorValue); + return NULL; + } + + rt_sem_init(sem, count); // Initialize Semaphore + + return sem; +} + +/// Wait until a Semaphore becomes available +int32_t svcSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) { + OS_ID sem; + OS_RESULT res; + + sem = rt_id2obj(semaphore_id); + if (sem == NULL) return -1; + + if (((P_SCB)sem)->cb_type != SCB) return -1; + + res = rt_sem_wait(sem, rt_ms2tick(millisec)); // Wait for Semaphore + + if (res == OS_R_TMO) return 0; // Timeout + + return (((P_SCB)sem)->tokens + 1); +} + +/// Release a Semaphore +osStatus svcSemaphoreRelease (osSemaphoreId semaphore_id) { + OS_ID sem; + + sem = rt_id2obj(semaphore_id); + if (sem == NULL) return osErrorParameter; + + if (((P_SCB)sem)->cb_type != SCB) return osErrorParameter; + + if (((P_SCB)sem)->tokens == osFeature_Semaphore) return osErrorResource; + + rt_sem_send(sem); // Release Semaphore + + return osOK; +} + +/// Delete a Semaphore that was created by osSemaphoreCreate +osStatus svcSemaphoreDelete (osSemaphoreId semaphore_id) { + OS_ID sem; + + sem = rt_id2obj(semaphore_id); + if (sem == NULL) return osErrorParameter; + + if (((P_SCB)sem)->cb_type != SCB) return osErrorParameter; + + rt_sem_delete(sem); // Delete Semaphore + + return osOK; +} + + +// Semaphore ISR Calls + +/// Release a Semaphore +static __INLINE osStatus isrSemaphoreRelease (osSemaphoreId semaphore_id) { + OS_ID sem; + + sem = rt_id2obj(semaphore_id); + if (sem == NULL) return osErrorParameter; + + if (((P_SCB)sem)->cb_type != SCB) return osErrorParameter; + + if (((P_SCB)sem)->tokens == osFeature_Semaphore) return osErrorResource; + + isr_sem_send(sem); // Release Semaphore + + return osOK; +} + + +// Semaphore Public API + +/// Create and Initialize a Semaphore object +osSemaphoreId osSemaphoreCreate (osSemaphoreDef_t *semaphore_def, int32_t count) { + if (__get_CONTROL() == MODE_IRQ) return NULL; // Not allowed in ISR + if ((__get_CONTROL() == MODE_SUPERVISOR) && (os_running == 0)) { + // Privileged and not running + return svcSemaphoreCreate(semaphore_def, count); + } else { + return __svcSemaphoreCreate(semaphore_def, count); + } +} + +/// Wait until a Semaphore becomes available +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) { + if (__get_CONTROL() == MODE_IRQ) return -1; // Not allowed in ISR + return __svcSemaphoreWait(semaphore_id, millisec); +} + +/// Release a Semaphore +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id) { + if (__get_CONTROL() == MODE_IRQ) { // in ISR + return isrSemaphoreRelease(semaphore_id); + } else { // in Thread + return __svcSemaphoreRelease(semaphore_id); + } +} + +/// Delete a Semaphore that was created by osSemaphoreCreate +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id) { + if (__get_CONTROL() == MODE_IRQ) return osErrorISR; // Not allowed in ISR + return __svcSemaphoreDelete(semaphore_id); +} + + +// ==== Memory Management Functions ==== + +// Memory Management Helper Functions + +// Clear Memory Box (Zero init) +static void rt_clr_box (void *box_mem, void *box) { + uint32_t *p, n; + + if (box) { + p = box; + for (n = ((P_BM)box_mem)->blk_size; n; n -= 4) { + *p++ = 0; + } + } +} + +// Memory Management Service Calls declarations +SVC_1_1(svcPoolCreate, osPoolId, const osPoolDef_t *, RET_pointer) +SVC_2_1(sysPoolAlloc, void *, osPoolId, uint32_t, RET_pointer) +SVC_2_1(sysPoolFree, osStatus, osPoolId, void *, RET_osStatus) + +// Memory Management Service & ISR Calls + +/// Create and Initialize memory pool +osPoolId svcPoolCreate (const osPoolDef_t *pool_def) { + uint32_t blk_sz; + + if ((pool_def == NULL) || + (pool_def->pool_sz == 0) || + (pool_def->item_sz == 0) || + (pool_def->pool == NULL)) { + sysThreadError(osErrorParameter); + return NULL; + } + + blk_sz = (pool_def->item_sz + 3) & ~3; + + _init_box(pool_def->pool, sizeof(struct OS_BM) + pool_def->pool_sz * blk_sz, blk_sz); + + return pool_def->pool; +} + +/// Allocate a memory block from a memory pool +void *sysPoolAlloc (osPoolId pool_id, uint32_t clr) { + void *ptr; + + if (pool_id == NULL) return NULL; + + ptr = rt_alloc_box(pool_id); + if (clr) { + rt_clr_box(pool_id, ptr); + } + + return ptr; +} + +/// Return an allocated memory block back to a specific memory pool +osStatus sysPoolFree (osPoolId pool_id, void *block) { + int32_t res; + + if (pool_id == NULL) return osErrorParameter; + + res = rt_free_box(pool_id, block); + if (res != 0) return osErrorValue; + + return osOK; +} + + +// Memory Management Public API + +/// Create and Initialize memory pool +osPoolId osPoolCreate (osPoolDef_t *pool_def) { + if (__get_CONTROL() == MODE_IRQ) return NULL; // Not allowed in ISR + if ((__get_CONTROL() == MODE_SUPERVISOR) && (os_running == 0)) { + // Privileged and not running + return svcPoolCreate(pool_def); + } else { + return __svcPoolCreate(pool_def); + } +} + +/// Allocate a memory block from a memory pool +void *osPoolAlloc (osPoolId pool_id) { + if ((__get_CONTROL() == MODE_IRQ) || (__get_CONTROL() == MODE_SUPERVISOR)) { // in ISR or Privileged + return sysPoolAlloc(pool_id, 0); + } else { // in Thread + return __sysPoolAlloc(pool_id, 0); + } +} + +/// Allocate a memory block from a memory pool and set memory block to zero +void *osPoolCAlloc (osPoolId pool_id) { + if ((__get_CONTROL() == MODE_IRQ) || (__get_CONTROL() == MODE_SUPERVISOR)) { // in ISR or Privileged + return sysPoolAlloc(pool_id, 1); + } else { // in Thread + return __sysPoolAlloc(pool_id, 1); + } +} + +/// Return an allocated memory block back to a specific memory pool +osStatus osPoolFree (osPoolId pool_id, void *block) { + if ((__get_CONTROL() == MODE_IRQ) || (__get_CONTROL() == MODE_SUPERVISOR)) { // in ISR or Privileged + return sysPoolFree(pool_id, block); + } else { // in Thread + return __sysPoolFree(pool_id, block); + } +} + + +// ==== Message Queue Management Functions ==== + +// Message Queue Management Service Calls declarations +SVC_2_1(svcMessageCreate, osMessageQId, osMessageQDef_t *, osThreadId, RET_pointer) +SVC_3_1(svcMessagePut, osStatus, osMessageQId, uint32_t, uint32_t, RET_osStatus) +SVC_2_3(svcMessageGet, os_InRegs osEvent, osMessageQId, uint32_t, RET_osEvent) + +// Message Queue Service Calls + +/// Create and Initialize Message Queue +osMessageQId svcMessageCreate (osMessageQDef_t *queue_def, osThreadId thread_id) { + + if ((queue_def == NULL) || + (queue_def->queue_sz == 0) || + (queue_def->pool == NULL)) { + sysThreadError(osErrorParameter); + return NULL; + } + + if (((P_MCB)queue_def->pool)->cb_type != 0) { + sysThreadError(osErrorParameter); + return NULL; + } + + rt_mbx_init(queue_def->pool, 4*(queue_def->queue_sz + 4)); + + return queue_def->pool; +} + +/// Put a Message to a Queue +osStatus svcMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) { + OS_RESULT res; + + if (queue_id == NULL) return osErrorParameter; + + if (((P_MCB)queue_id)->cb_type != MCB) return osErrorParameter; + + res = rt_mbx_send(queue_id, (void *)info, rt_ms2tick(millisec)); + + if (res == OS_R_TMO) { + return (millisec ? osErrorTimeoutResource : osErrorResource); + } + + return osOK; +} + +/// Get a Message or Wait for a Message from a Queue +os_InRegs osEvent_type svcMessageGet (osMessageQId queue_id, uint32_t millisec) { + OS_RESULT res; + osEvent ret; + + if (queue_id == NULL) { + ret.status = osErrorParameter; + return osEvent_ret_status; + } + + if (((P_MCB)queue_id)->cb_type != MCB) { + ret.status = osErrorParameter; + return osEvent_ret_status; + } + + res = rt_mbx_wait(queue_id, &ret.value.p, rt_ms2tick(millisec)); + + if (res == OS_R_TMO) { + ret.status = millisec ? osEventTimeout : osOK; + return osEvent_ret_value; + } + + ret.status = osEventMessage; + + return osEvent_ret_value; +} + + +// Message Queue ISR Calls + +/// Put a Message to a Queue +static __INLINE osStatus isrMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) { + + if ((queue_id == NULL) || (millisec != 0)) { + return osErrorParameter; + } + + if (((P_MCB)queue_id)->cb_type != MCB) return osErrorParameter; + + if (rt_mbx_check(queue_id) == 0) { // Check if Queue is full + return osErrorResource; + } + + isr_mbx_send(queue_id, (void *)info); + + return osOK; +} + +/// Get a Message or Wait for a Message from a Queue +static __INLINE os_InRegs osEvent isrMessageGet (osMessageQId queue_id, uint32_t millisec) { + OS_RESULT res; + osEvent ret; + + if ((queue_id == NULL) || (millisec != 0)) { + ret.status = osErrorParameter; + return ret; + } + + if (((P_MCB)queue_id)->cb_type != MCB) { + ret.status = osErrorParameter; + return ret; + } + + res = isr_mbx_receive(queue_id, &ret.value.p); + + if (res != OS_R_MBX) { + ret.status = osOK; + return ret; + } + + ret.status = osEventMessage; + + return ret; +} + + +// Message Queue Management Public API + +/// Create and Initialize Message Queue +osMessageQId osMessageCreate (osMessageQDef_t *queue_def, osThreadId thread_id) { + if (__get_CONTROL() == MODE_IRQ) return NULL; // Not allowed in ISR + if ((__get_CONTROL() == MODE_SUPERVISOR) && (os_running == 0)) { + // Privileged and not running + return svcMessageCreate(queue_def, thread_id); + } else { + return __svcMessageCreate(queue_def, thread_id); + } +} + +/// Put a Message to a Queue +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) { + if (__get_CONTROL() == MODE_IRQ) { // in ISR + return isrMessagePut(queue_id, info, millisec); + } else { // in Thread + return __svcMessagePut(queue_id, info, millisec); + } +} + +/// Get a Message or Wait for a Message from a Queue +os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) { + if (__get_CONTROL() == MODE_IRQ) { // in ISR + return isrMessageGet(queue_id, millisec); + } else { // in Thread + return __svcMessageGet(queue_id, millisec); + } +} + + +// ==== Mail Queue Management Functions ==== + +// Mail Queue Management Service Calls declarations +SVC_2_1(svcMailCreate, osMailQId, osMailQDef_t *, osThreadId, RET_pointer) +SVC_4_1(sysMailAlloc, void *, osMailQId, uint32_t, uint32_t, uint32_t, RET_pointer) +SVC_3_1(sysMailFree, osStatus, osMailQId, void *, uint32_t, RET_osStatus) + +// Mail Queue Management Service & ISR Calls + +/// Create and Initialize mail queue +osMailQId svcMailCreate (osMailQDef_t *queue_def, osThreadId thread_id) { + uint32_t blk_sz; + P_MCB pmcb; + void *pool; + + if ((queue_def == NULL) || + (queue_def->queue_sz == 0) || + (queue_def->item_sz == 0) || + (queue_def->pool == NULL)) { + sysThreadError(osErrorParameter); + return NULL; + } + + pmcb = *(((void **)queue_def->pool) + 0); + pool = *(((void **)queue_def->pool) + 1); + + if ((pool == NULL) || (pmcb == NULL) || (pmcb->cb_type != 0)) { + sysThreadError(osErrorParameter); + return NULL; + } + + blk_sz = (queue_def->item_sz + 3) & ~3; + + _init_box(pool, sizeof(struct OS_BM) + queue_def->queue_sz * blk_sz, blk_sz); + + rt_mbx_init(pmcb, 4*(queue_def->queue_sz + 4)); + + + return queue_def->pool; +} + +/// Allocate a memory block from a mail +void *sysMailAlloc (osMailQId queue_id, uint32_t millisec, uint32_t isr, uint32_t clr) { + P_MCB pmcb; + void *pool; + void *mem; + + if (queue_id == NULL) return NULL; + + pmcb = *(((void **)queue_id) + 0); + pool = *(((void **)queue_id) + 1); + + if ((pool == NULL) || (pmcb == NULL)) return NULL; + + if (isr && (millisec != 0)) return NULL; + + mem = rt_alloc_box(pool); + if (clr) { + rt_clr_box(pool, mem); + } + + if ((mem == NULL) && (millisec != 0)) { + // Put Task to sleep when Memory not available + if (pmcb->p_lnk != NULL) { + rt_put_prio((P_XCB)pmcb, os_tsk.run); + } else { + pmcb->p_lnk = os_tsk.run; + os_tsk.run->p_lnk = NULL; + os_tsk.run->p_rlnk = (P_TCB)pmcb; + // Task is waiting to allocate a message + pmcb->state = 3; + } + rt_block(rt_ms2tick(millisec), WAIT_MBX); + } + + return mem; +} + +/// Free a memory block from a mail +osStatus sysMailFree (osMailQId queue_id, void *mail, uint32_t isr) { + P_MCB pmcb; + P_TCB ptcb; + void *pool; + void *mem; + int32_t res; + + if (queue_id == NULL) return osErrorParameter; + + pmcb = *(((void **)queue_id) + 0); + pool = *(((void **)queue_id) + 1); + + if ((pmcb == NULL) || (pool == NULL)) return osErrorParameter; + + res = rt_free_box(pool, mail); + + if (res != 0) return osErrorValue; + + if (pmcb->state == 3) { + // Task is waiting to allocate a message + if (isr) { + rt_psq_enq (pmcb, (U32)pool); + rt_psh_req (); + } else { + mem = rt_alloc_box(pool); + if (mem != NULL) { + ptcb = rt_get_first((P_XCB)pmcb); + if (pmcb->p_lnk == NULL) { + pmcb->state = 0; + } + rt_ret_val(ptcb, (U32)mem); + rt_rmv_dly(ptcb); + rt_dispatch(ptcb); + } + } + } + + return osOK; +} + + +// Mail Queue Management Public API + +/// Create and Initialize mail queue +osMailQId osMailCreate (osMailQDef_t *queue_def, osThreadId thread_id) { + if (__get_CONTROL() == MODE_IRQ) return NULL; // Not allowed in ISR + if ((__get_CONTROL() == MODE_SUPERVISOR) && (os_running == 0)) { + // Privileged and not running + return svcMailCreate(queue_def, thread_id); + } else { + return __svcMailCreate(queue_def, thread_id); + } +} + +/// Allocate a memory block from a mail +void *osMailAlloc (osMailQId queue_id, uint32_t millisec) { + if (__get_CONTROL() == MODE_IRQ) { // in ISR + return sysMailAlloc(queue_id, millisec, 1, 0); + } else { // in Thread + return __sysMailAlloc(queue_id, millisec, 0, 0); + } +} + +/// Allocate a memory block from a mail and set memory block to zero +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) { + if (__get_CONTROL() == MODE_IRQ) { // in ISR + return sysMailAlloc(queue_id, millisec, 1, 1); + } else { // in Thread + return __sysMailAlloc(queue_id, millisec, 0, 1); + } +} + +/// Free a memory block from a mail +osStatus osMailFree (osMailQId queue_id, void *mail) { + if (__get_CONTROL() == MODE_IRQ) { // in ISR + return sysMailFree(queue_id, mail, 1); + } else { // in Thread + return __sysMailFree(queue_id, mail, 0); + } +} + +/// Put a mail to a queue +osStatus osMailPut (osMailQId queue_id, void *mail) { + if (queue_id == NULL) return osErrorParameter; + if (mail == NULL) return osErrorValue; + return osMessagePut(*((void **)queue_id), (uint32_t)mail, 0); +} + +/// Get a mail from a queue +os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) { + osEvent ret; + + if (queue_id == NULL) { + ret.status = osErrorParameter; + return ret; + } + + ret = osMessageGet(*((void **)queue_id), millisec); + if (ret.status == osEventMessage) ret.status = osEventMail; + + return ret; +} diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_Event.c b/libraries/rtos/rtx/TARGET_ARM7/rt_Event.c new file mode 100644 index 0000000000..acd8ccc205 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_Event.c @@ -0,0 +1,190 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_EVENT.C + * Purpose: Implements waits and wake-ups for event flags + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Conf.h" +#include "rt_System.h" +#include "rt_Event.h" +#include "rt_List.h" +#include "rt_Task.h" +#include "rt_HAL_CM.h" + + +/*---------------------------------------------------------------------------- + * Functions + *---------------------------------------------------------------------------*/ + + +/*--------------------------- rt_evt_wait -----------------------------------*/ + +OS_RESULT rt_evt_wait (U16 wait_flags, U16 timeout, BOOL and_wait) { + /* Wait for one or more event flags with optional time-out. */ + /* "wait_flags" identifies the flags to wait for. */ + /* "timeout" is the time-out limit in system ticks (0xffff if no time-out) */ + /* "and_wait" specifies the AND-ing of "wait_flags" as condition to be met */ + /* to complete the wait. (OR-ing if set to 0). */ + U32 block_state; + + if (and_wait) { + /* Check for AND-connected events */ + if ((os_tsk.run->events & wait_flags) == wait_flags) { + os_tsk.run->events &= ~wait_flags; + return (OS_R_EVT); + } + block_state = WAIT_AND; + } + else { + /* Check for OR-connected events */ + if (os_tsk.run->events & wait_flags) { + os_tsk.run->waits = os_tsk.run->events & wait_flags; + os_tsk.run->events &= ~wait_flags; + return (OS_R_EVT); + } + block_state = WAIT_OR; + } + /* Task has to wait */ + os_tsk.run->waits = wait_flags; + rt_block (timeout, (U8)block_state); + return (OS_R_TMO); +} + + +/*--------------------------- rt_evt_set ------------------------------------*/ + +void rt_evt_set (U16 event_flags, OS_TID task_id) { + /* Set one or more event flags of a selectable task. */ + P_TCB p_tcb; + + p_tcb = os_active_TCB[task_id-1]; + if (p_tcb == NULL) { + return; + } + p_tcb->events |= event_flags; + event_flags = p_tcb->waits; + /* If the task is not waiting for an event, it should not be put */ + /* to ready state. */ + if (p_tcb->state == WAIT_AND) { + /* Check for AND-connected events */ + if ((p_tcb->events & event_flags) == event_flags) { + goto wkup; + } + } + if (p_tcb->state == WAIT_OR) { + /* Check for OR-connected events */ + if (p_tcb->events & event_flags) { + p_tcb->waits &= p_tcb->events; +wkup: p_tcb->events &= ~event_flags; + rt_rmv_dly (p_tcb); + p_tcb->state = READY; +#ifdef __CMSIS_RTOS + rt_ret_val2(p_tcb, 0x08/*osEventSignal*/, p_tcb->waits); +#else + rt_ret_val (p_tcb, OS_R_EVT); +#endif + rt_dispatch (p_tcb); + } + } +} + + +/*--------------------------- rt_evt_clr ------------------------------------*/ + +void rt_evt_clr (U16 clear_flags, OS_TID task_id) { + /* Clear one or more event flags (identified by "clear_flags") of a */ + /* selectable task (identified by "task"). */ + P_TCB task = os_active_TCB[task_id-1]; + + if (task == NULL) { + return; + } + task->events &= ~clear_flags; +} + + +/*--------------------------- isr_evt_set -----------------------------------*/ + +void isr_evt_set (U16 event_flags, OS_TID task_id) { + /* Same function as "os_evt_set", but to be called by ISRs. */ + P_TCB p_tcb = os_active_TCB[task_id-1]; + + if (p_tcb == NULL) { + return; + } + rt_psq_enq (p_tcb, event_flags); + rt_psh_req (); +} + + +/*--------------------------- rt_evt_get ------------------------------------*/ + +U16 rt_evt_get (void) { + /* Get events of a running task after waiting for OR connected events. */ + return (os_tsk.run->waits); +} + + +/*--------------------------- rt_evt_psh ------------------------------------*/ + +void rt_evt_psh (P_TCB p_CB, U16 set_flags) { + /* Check if task has to be waken up */ + U16 event_flags; + + p_CB->events |= set_flags; + event_flags = p_CB->waits; + if (p_CB->state == WAIT_AND) { + /* Check for AND-connected events */ + if ((p_CB->events & event_flags) == event_flags) { + goto rdy; + } + } + if (p_CB->state == WAIT_OR) { + /* Check for OR-connected events */ + if (p_CB->events & event_flags) { + p_CB->waits &= p_CB->events; +rdy: p_CB->events &= ~event_flags; + rt_rmv_dly (p_CB); + p_CB->state = READY; +#ifdef __CMSIS_RTOS + rt_ret_val2(p_CB, 0x08/*osEventSignal*/, p_CB->waits); +#else + rt_ret_val (p_CB, OS_R_EVT); +#endif + rt_put_prio (&os_rdy, p_CB); + } + } +} + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_Event.h b/libraries/rtos/rtx/TARGET_ARM7/rt_Event.h new file mode 100644 index 0000000000..8b92f3c4c4 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_Event.h @@ -0,0 +1,46 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_EVENT.H + * Purpose: Implements waits and wake-ups for event flags + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Functions */ +extern OS_RESULT rt_evt_wait (U16 wait_flags, U16 timeout, BOOL and_wait); +extern void rt_evt_set (U16 event_flags, OS_TID task_id); +extern void rt_evt_clr (U16 clear_flags, OS_TID task_id); +extern void isr_evt_set (U16 event_flags, OS_TID task_id); +extern U16 rt_evt_get (void); +extern void rt_evt_psh (P_TCB p_CB, U16 set_flags); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h b/libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h new file mode 100644 index 0000000000..f17972c7f8 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h @@ -0,0 +1,227 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_HAL_CM.H + * Purpose: Hardware Abstraction Layer for Cortex-M definitions + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "cmsis.h" +/* Definitions */ +#define INITIAL_xPSR 0x00000010 +#define DEMCR_TRCENA 0x01000000 +#define ITM_ITMENA 0x00000001 +#define MAGIC_WORD 0xE25A2EA5 + +#define SYS_TICK_IRQn TIMER0_IRQn + +extern void rt_set_PSP (U32 stack); +extern U32 rt_get_PSP (void); +extern void os_set_env (void); +extern void SysTick_Handler (void); +extern void *_alloc_box (void *box_mem); +extern int _free_box (void *box_mem, void *box); + +extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body); +extern void rt_ret_val (P_TCB p_TCB, U32 v0); +extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1); + +extern void dbg_init (void); +extern void dbg_task_notify (P_TCB p_tcb, BOOL create); +extern void dbg_task_switch (U32 task_id); + + +#if defined (__CC_ARM) /* ARM Compiler */ + +#if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS) + #define __USE_EXCLUSIVE_ACCESS +#else + #undef __USE_EXCLUSIVE_ACCESS +#endif + +#elif defined (__GNUC__) /* GNU Compiler */ + +#undef __USE_EXCLUSIVE_ACCESS + +#if defined (__CORTEX_M0) || defined (__CORTEX_M0PLUS) +#define __TARGET_ARCH_6S_M 1 +#else +#define __TARGET_ARCH_6S_M 0 +#endif + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#define __TARGET_FPU_VFP 1 +#else +#define __TARGET_FPU_VFP 0 +#endif + +#define __inline inline +#define __weak __attribute__((weak)) + + +#elif defined (__ICCARM__) /* IAR Compiler */ + +#undef __USE_EXCLUSIVE_ACCESS + +#if (__CORE__ == __ARM6M__) +#define __TARGET_ARCH_6S_M 1 +#else +#define __TARGET_ARCH_6S_M 0 +#endif + +#if defined __ARMVFP__ +#define __TARGET_FPU_VFP 1 +#else +#define __TARGET_FPU_VFP 0 +#endif + +#define __inline inline + +#endif + + +/* NVIC registers */ + +#define OS_PEND_IRQ() NVIC_PendIRQ(SYS_TICK_IRQn) +#define OS_PENDING NVIC_PendingIRQ(SYS_TICK_IRQn) +#define OS_UNPEND(fl) NVIC_UnpendIRQ(SYS_TICK_IRQn) +#define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26 +#define OS_LOCK() NVIC_DisableIRQ(SYS_TICK_IRQn) +#define OS_UNLOCK() NVIC_EnableIRQ(SYS_TICK_IRQn) + +#define OS_X_PENDING NVIC_PendingIRQ(SYS_TICK_IRQn) +#define OS_X_UNPEND(fl) NVIC_UnpendIRQ(SYS_TICK_IRQn) +#define OS_X_PEND(fl,p) NVIC_PendIRQ(p) + +#define OS_X_INIT(n) NVIC_EnableIRQ(n) +#define OS_X_LOCK(n) NVIC_DisableIRQ(n) +#define OS_X_UNLOCK(n) NVIC_EnableIRQ(n) + +/* Core Debug registers */ +//#define DEMCR (*((volatile U32 *)0xE000EDFC)) + +/* ITM registers */ +//#define ITM_CONTROL (*((volatile U32 *)0xE0000E80)) +//#define ITM_ENABLE (*((volatile U32 *)0xE0000E00)) +//#define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078)) +//#define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C)) +//#define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C)) +//#define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C)) + +/* Variables */ +extern BIT dbg_msg; + +/* Functions */ +#ifdef __USE_EXCLUSIVE_ACCESS + #define rt_inc(p) while(__strex((__ldrex(p)+1),p)) + #define rt_dec(p) while(__strex((__ldrex(p)-1),p)) +#else + #define rt_inc(p) __disable_irq();(*p)++;__enable_irq(); + #define rt_dec(p) __disable_irq();(*p)--;__enable_irq(); +#endif + +__inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) { + U32 cnt,c2; +#ifdef __USE_EXCLUSIVE_ACCESS + do { + if ((cnt = __ldrex(count)) == size) { + __clrex(); + return (cnt); } + } while (__strex(cnt+1, count)); + do { + c2 = (cnt = __ldrex(first)) + 1; + if (c2 == size) c2 = 0; + } while (__strex(c2, first)); +#else + __disable_irq(); + if ((cnt = *count) < size) { + *count = cnt+1; + c2 = (cnt = *first) + 1; + if (c2 == size) c2 = 0; + *first = c2; + } + __enable_irq (); +#endif + return (cnt); +} + +__inline static void rt_systick_init (void) { +#if SYS_TICK_IRQn == TIMER0_IRQn + #define SYS_TICK_TIMER LPC_TIM0 + LPC_SC->PCONP |= PCTIM0; + LPC_SC->PCLKSEL0 = (LPC_SC->PCLKSEL0 & (~(1<<3))) | (1<<2); //PCLK == CPUCLK +#elif SYS_TICK_IRQn == TIMER1_IRQn + #define SYS_TICK_TIMER LPC_TIM1 + LPC_SC->PCONP |= PCTIM1; + LPC_SC->PCLKSEL0 = (LPC_SC->PCLKSEL0 & (~(1<<5))) | (1<<4); //PCLK == CPUCLK +#elif SYS_TICK_IRQn == TIMER2_IRQn + #define SYS_TICK_TIMER LPC_TIM2 + LPC_SC->PCONP |= PCTIM2; + LPC_SC->PCLKSEL1 = (LPC_SC->PCLKSEL1 & (~(1<<13))) | (1<<12); //PCLK == CPUCLK +#else + #define SYS_TICK_TIMER LPC_TIM3 + LPC_SC->PCONP |= PCTIM3; + LPC_SC->PCLKSEL1 = (LPC_SC->PCLKSEL1 & (~(1<<15))) | (1<<14); //PCLK == CPUCLK +#endif + + // setup Timer to count forever + //interrupt_reg + SYS_TICK_TIMER->TCR = 2; // reset & disable timer 0 + SYS_TICK_TIMER->TC = os_trv; + SYS_TICK_TIMER->PR = 0; // set the prescale divider + //Reset of TC and Interrupt when MR3 MR2 matches TC + SYS_TICK_TIMER->MCR = (1 << 6) |(1 << 7); //TMCR_MR3_R_Msk | TMCR_MR3_I_Msk + SYS_TICK_TIMER->MR3 = os_trv; // match registers + SYS_TICK_TIMER->CCR = 0; // disable compare registers + SYS_TICK_TIMER->EMR = 0; // disable external match register + // initialize the interrupt vector + NVIC_SetVector(SYS_TICK_IRQn, (uint32_t)&SysTick_Handler); + SYS_TICK_TIMER->TCR = 1; // enable timer 0 +} + +__inline static void rt_svc_init (void) { +// TODO: add svcInit + +} + +#ifdef DBG_MSG +#define DBG_INIT() dbg_init() +#define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create) +#define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk != os_tsk.run)) \ + dbg_task_switch(task_id) +#else +#define DBG_INIT() +#define DBG_TASK_NOTIFY(p_tcb,create) +#define DBG_TASK_SWITCH(task_id) +#endif + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_List.c b/libraries/rtos/rtx/TARGET_ARM7/rt_List.c new file mode 100644 index 0000000000..2134d14b38 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_List.c @@ -0,0 +1,320 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_LIST.C + * Purpose: Functions for the management of different lists + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Conf.h" +#include "rt_System.h" +#include "rt_List.h" +#include "rt_Task.h" +#include "rt_Time.h" +#include "rt_HAL_CM.h" + +/*---------------------------------------------------------------------------- + * Global Variables + *---------------------------------------------------------------------------*/ + +/* List head of chained ready tasks */ +struct OS_XCB os_rdy; +/* List head of chained delay tasks */ +struct OS_XCB os_dly; + + +/*---------------------------------------------------------------------------- + * Functions + *---------------------------------------------------------------------------*/ + + +/*--------------------------- rt_put_prio -----------------------------------*/ + +void rt_put_prio (P_XCB p_CB, P_TCB p_task) { + /* Put task identified with "p_task" into list ordered by priority. */ + /* "p_CB" points to head of list; list has always an element at end with */ + /* a priority less than "p_task->prio". */ + P_TCB p_CB2; + U32 prio; + BOOL sem_mbx = __FALSE; + + if (p_CB->cb_type == SCB || p_CB->cb_type == MCB || p_CB->cb_type == MUCB) { + sem_mbx = __TRUE; + } + prio = p_task->prio; + p_CB2 = p_CB->p_lnk; + /* Search for an entry in the list */ + while (p_CB2 != NULL && prio <= p_CB2->prio) { + p_CB = (P_XCB)p_CB2; + p_CB2 = p_CB2->p_lnk; + } + /* Entry found, insert the task into the list */ + p_task->p_lnk = p_CB2; + p_CB->p_lnk = p_task; + if (sem_mbx) { + if (p_CB2 != NULL) { + p_CB2->p_rlnk = p_task; + } + p_task->p_rlnk = (P_TCB)p_CB; + } + else { + p_task->p_rlnk = NULL; + } +} + + +/*--------------------------- rt_get_first ----------------------------------*/ + +P_TCB rt_get_first (P_XCB p_CB) { + /* Get task at head of list: it is the task with highest priority. */ + /* "p_CB" points to head of list. */ + P_TCB p_first; + + p_first = p_CB->p_lnk; + p_CB->p_lnk = p_first->p_lnk; + if (p_CB->cb_type == SCB || p_CB->cb_type == MCB || p_CB->cb_type == MUCB) { + if (p_first->p_lnk != NULL) { + p_first->p_lnk->p_rlnk = (P_TCB)p_CB; + p_first->p_lnk = NULL; + } + p_first->p_rlnk = NULL; + } + else { + p_first->p_lnk = NULL; + } + return (p_first); +} + + +/*--------------------------- rt_put_rdy_first ------------------------------*/ + +void rt_put_rdy_first (P_TCB p_task) { + /* Put task identified with "p_task" at the head of the ready list. The */ + /* task must have at least a priority equal to highest priority in list. */ + p_task->p_lnk = os_rdy.p_lnk; + p_task->p_rlnk = NULL; + os_rdy.p_lnk = p_task; +} + + +/*--------------------------- rt_get_same_rdy_prio --------------------------*/ + +P_TCB rt_get_same_rdy_prio (void) { + /* Remove a task of same priority from ready list if any exists. Other- */ + /* wise return NULL. */ + P_TCB p_first; + + p_first = os_rdy.p_lnk; + if (p_first->prio == os_tsk.run->prio) { + os_rdy.p_lnk = os_rdy.p_lnk->p_lnk; + return (p_first); + } + return (NULL); +} + + +/*--------------------------- rt_resort_prio --------------------------------*/ + +void rt_resort_prio (P_TCB p_task) { + /* Re-sort ordered lists after the priority of 'p_task' has changed. */ + P_TCB p_CB; + + if (p_task->p_rlnk == NULL) { + if (p_task->state == READY) { + /* Task is chained into READY list. */ + p_CB = (P_TCB)&os_rdy; + goto res; + } + } + else { + p_CB = p_task->p_rlnk; + while (p_CB->cb_type == TCB) { + /* Find a header of this task chain list. */ + p_CB = p_CB->p_rlnk; + } +res:rt_rmv_list (p_task); + rt_put_prio ((P_XCB)p_CB, p_task); + } +} + + +/*--------------------------- rt_put_dly ------------------------------------*/ + +void rt_put_dly (P_TCB p_task, U16 delay) { + /* Put a task identified with "p_task" into chained delay wait list using */ + /* a delay value of "delay". */ + P_TCB p; + U32 delta,idelay = delay; + + p = (P_TCB)&os_dly; + if (p->p_dlnk == NULL) { + /* Delay list empty */ + delta = 0; + goto last; + } + delta = os_dly.delta_time; + while (delta < idelay) { + if (p->p_dlnk == NULL) { + /* End of list found */ +last: p_task->p_dlnk = NULL; + p->p_dlnk = p_task; + p_task->p_blnk = p; + p->delta_time = (U16)(idelay - delta); + p_task->delta_time = 0; + return; + } + p = p->p_dlnk; + delta += p->delta_time; + } + /* Right place found */ + p_task->p_dlnk = p->p_dlnk; + p->p_dlnk = p_task; + p_task->p_blnk = p; + if (p_task->p_dlnk != NULL) { + p_task->p_dlnk->p_blnk = p_task; + } + p_task->delta_time = (U16)(delta - idelay); + p->delta_time -= p_task->delta_time; +} + + +/*--------------------------- rt_dec_dly ------------------------------------*/ + +void rt_dec_dly (void) { + /* Decrement delta time of list head: remove tasks having a value of zero.*/ + P_TCB p_rdy; + + if (os_dly.p_dlnk == NULL) { + return; + } + os_dly.delta_time--; + while ((os_dly.delta_time == 0) && (os_dly.p_dlnk != NULL)) { + p_rdy = os_dly.p_dlnk; + if (p_rdy->p_rlnk != NULL) { + /* Task is really enqueued, remove task from semaphore/mailbox */ + /* timeout waiting list. */ + p_rdy->p_rlnk->p_lnk = p_rdy->p_lnk; + if (p_rdy->p_lnk != NULL) { + p_rdy->p_lnk->p_rlnk = p_rdy->p_rlnk; + p_rdy->p_lnk = NULL; + } + p_rdy->p_rlnk = NULL; + } + rt_put_prio (&os_rdy, p_rdy); + os_dly.delta_time = p_rdy->delta_time; + if (p_rdy->state == WAIT_ITV) { + /* Calculate the next time for interval wait. */ + p_rdy->delta_time = p_rdy->interval_time + (U16)os_time; + } + p_rdy->state = READY; + os_dly.p_dlnk = p_rdy->p_dlnk; + if (p_rdy->p_dlnk != NULL) { + p_rdy->p_dlnk->p_blnk = (P_TCB)&os_dly; + p_rdy->p_dlnk = NULL; + } + p_rdy->p_blnk = NULL; + } +} + + +/*--------------------------- rt_rmv_list -----------------------------------*/ + +void rt_rmv_list (P_TCB p_task) { + /* Remove task identified with "p_task" from ready, semaphore or mailbox */ + /* waiting list if enqueued. */ + P_TCB p_b; + + if (p_task->p_rlnk != NULL) { + /* A task is enqueued in semaphore / mailbox waiting list. */ + p_task->p_rlnk->p_lnk = p_task->p_lnk; + if (p_task->p_lnk != NULL) { + p_task->p_lnk->p_rlnk = p_task->p_rlnk; + } + return; + } + + p_b = (P_TCB)&os_rdy; + while (p_b != NULL) { + /* Search the ready list for task "p_task" */ + if (p_b->p_lnk == p_task) { + p_b->p_lnk = p_task->p_lnk; + return; + } + p_b = p_b->p_lnk; + } +} + + +/*--------------------------- rt_rmv_dly ------------------------------------*/ + +void rt_rmv_dly (P_TCB p_task) { + /* Remove task identified with "p_task" from delay list if enqueued. */ + P_TCB p_b; + + p_b = p_task->p_blnk; + if (p_b != NULL) { + /* Task is really enqueued */ + p_b->p_dlnk = p_task->p_dlnk; + if (p_task->p_dlnk != NULL) { + /* 'p_task' is in the middle of list */ + p_b->delta_time += p_task->delta_time; + p_task->p_dlnk->p_blnk = p_b; + p_task->p_dlnk = NULL; + } + else { + /* 'p_task' is at the end of list */ + p_b->delta_time = 0; + } + p_task->p_blnk = NULL; + } +} + + +/*--------------------------- rt_psq_enq ------------------------------------*/ + +void rt_psq_enq (OS_ID entry, U32 arg) { + /* Insert post service request "entry" into ps-queue. */ + U32 idx; + + idx = rt_inc_qi (os_psq->size, &os_psq->count, &os_psq->first); + if (idx < os_psq->size) { + os_psq->q[idx].id = entry; + os_psq->q[idx].arg = arg; + } + else { + os_error (OS_ERR_FIFO_OVF); + } +} + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_List.h b/libraries/rtos/rtx/TARGET_ARM7/rt_List.h new file mode 100644 index 0000000000..cb3008e713 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_List.h @@ -0,0 +1,67 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_LIST.H + * Purpose: Functions for the management of different lists + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Definitions */ + +/* Values for 'cb_type' */ +#define TCB 0 +#define MCB 1 +#define SCB 2 +#define MUCB 3 +#define HCB 4 + +/* Variables */ +extern struct OS_XCB os_rdy; +extern struct OS_XCB os_dly; + +/* Functions */ +extern void rt_put_prio (P_XCB p_CB, P_TCB p_task); +extern P_TCB rt_get_first (P_XCB p_CB); +extern void rt_put_rdy_first (P_TCB p_task); +extern P_TCB rt_get_same_rdy_prio (void); +extern void rt_resort_prio (P_TCB p_task); +extern void rt_put_dly (P_TCB p_task, U16 delay); +extern void rt_dec_dly (void); +extern void rt_rmv_list (P_TCB p_task); +extern void rt_rmv_dly (P_TCB p_task); +extern void rt_psq_enq (OS_ID entry, U32 arg); + +/* This is a fast macro generating in-line code */ +#define rt_rdy_prio(void) (os_rdy.p_lnk->prio) + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_Mailbox.c b/libraries/rtos/rtx/TARGET_ARM7/rt_Mailbox.c new file mode 100644 index 0000000000..ef28b7639c --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_Mailbox.c @@ -0,0 +1,292 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_MAILBOX.C + * Purpose: Implements waits and wake-ups for mailbox messages + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Conf.h" +#include "rt_System.h" +#include "rt_List.h" +#include "rt_Mailbox.h" +#include "rt_MemBox.h" +#include "rt_Task.h" +#include "rt_HAL_CM.h" + + +/*---------------------------------------------------------------------------- + * Functions + *---------------------------------------------------------------------------*/ + + +/*--------------------------- rt_mbx_init -----------------------------------*/ + +void rt_mbx_init (OS_ID mailbox, U16 mbx_size) { + /* Initialize a mailbox */ + P_MCB p_MCB = mailbox; + + p_MCB->cb_type = MCB; + p_MCB->state = 0; + p_MCB->isr_st = 0; + p_MCB->p_lnk = NULL; + p_MCB->first = 0; + p_MCB->last = 0; + p_MCB->count = 0; + p_MCB->size = (mbx_size + sizeof(void *) - sizeof(struct OS_MCB)) / + (U32)sizeof (void *); +} + + +/*--------------------------- rt_mbx_send -----------------------------------*/ + +OS_RESULT rt_mbx_send (OS_ID mailbox, void *p_msg, U16 timeout) { + /* Send message to a mailbox */ + P_MCB p_MCB = mailbox; + P_TCB p_TCB; + + if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 1)) { + /* A task is waiting for message */ + p_TCB = rt_get_first ((P_XCB)p_MCB); +#ifdef __CMSIS_RTOS + rt_ret_val2(p_TCB, 0x10/*osEventMessage*/, (U32)p_msg); +#else + *p_TCB->msg = p_msg; + rt_ret_val (p_TCB, OS_R_MBX); +#endif + rt_rmv_dly (p_TCB); + rt_dispatch (p_TCB); + } + else { + /* Store message in mailbox queue */ + if (p_MCB->count == p_MCB->size) { + /* No free message entry, wait for one. If message queue is full, */ + /* then no task is waiting for message. The 'p_MCB->p_lnk' list */ + /* pointer can now be reused for send message waits task list. */ + if (timeout == 0) { + return (OS_R_TMO); + } + if (p_MCB->p_lnk != NULL) { + rt_put_prio ((P_XCB)p_MCB, os_tsk.run); + } + else { + p_MCB->p_lnk = os_tsk.run; + os_tsk.run->p_lnk = NULL; + os_tsk.run->p_rlnk = (P_TCB)p_MCB; + /* Task is waiting to send a message */ + p_MCB->state = 2; + } + os_tsk.run->msg = p_msg; + rt_block (timeout, WAIT_MBX); + return (OS_R_TMO); + } + /* Yes, there is a free entry in a mailbox. */ + p_MCB->msg[p_MCB->first] = p_msg; + rt_inc (&p_MCB->count); + if (++p_MCB->first == p_MCB->size) { + p_MCB->first = 0; + } + } + return (OS_R_OK); +} + + +/*--------------------------- rt_mbx_wait -----------------------------------*/ + +OS_RESULT rt_mbx_wait (OS_ID mailbox, void **message, U16 timeout) { + /* Receive a message; possibly wait for it */ + P_MCB p_MCB = mailbox; + P_TCB p_TCB; + + /* If a message is available in the fifo buffer */ + /* remove it from the fifo buffer and return. */ + if (p_MCB->count) { + *message = p_MCB->msg[p_MCB->last]; + if (++p_MCB->last == p_MCB->size) { + p_MCB->last = 0; + } + if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 2)) { + /* A task is waiting to send message */ + p_TCB = rt_get_first ((P_XCB)p_MCB); +#ifdef __CMSIS_RTOS + rt_ret_val(p_TCB, 0/*osOK*/); +#else + rt_ret_val(p_TCB, OS_R_OK); +#endif + p_MCB->msg[p_MCB->first] = p_TCB->msg; + if (++p_MCB->first == p_MCB->size) { + p_MCB->first = 0; + } + rt_rmv_dly (p_TCB); + rt_dispatch (p_TCB); + } + else { + rt_dec (&p_MCB->count); + } + return (OS_R_OK); + } + /* No message available: wait for one */ + if (timeout == 0) { + return (OS_R_TMO); + } + if (p_MCB->p_lnk != NULL) { + rt_put_prio ((P_XCB)p_MCB, os_tsk.run); + } + else { + p_MCB->p_lnk = os_tsk.run; + os_tsk.run->p_lnk = NULL; + os_tsk.run->p_rlnk = (P_TCB)p_MCB; + /* Task is waiting to receive a message */ + p_MCB->state = 1; + } + rt_block(timeout, WAIT_MBX); +#ifndef __CMSIS_RTOS + os_tsk.run->msg = message; +#endif + return (OS_R_TMO); +} + + +/*--------------------------- rt_mbx_check ----------------------------------*/ + +OS_RESULT rt_mbx_check (OS_ID mailbox) { + /* Check for free space in a mailbox. Returns the number of messages */ + /* that can be stored to a mailbox. It returns 0 when mailbox is full. */ + P_MCB p_MCB = mailbox; + + return (p_MCB->size - p_MCB->count); +} + + +/*--------------------------- isr_mbx_send ----------------------------------*/ + +void isr_mbx_send (OS_ID mailbox, void *p_msg) { + /* Same function as "os_mbx_send", but to be called by ISRs. */ + P_MCB p_MCB = mailbox; + + rt_psq_enq (p_MCB, (U32)p_msg); + rt_psh_req (); +} + + +/*--------------------------- isr_mbx_receive -------------------------------*/ + +OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message) { + /* Receive a message in the interrupt function. The interrupt function */ + /* should not wait for a message since this would block the rtx os. */ + P_MCB p_MCB = mailbox; + + if (p_MCB->count) { + /* A message is available in the fifo buffer. */ + *message = p_MCB->msg[p_MCB->last]; + if (p_MCB->state == 2) { + /* A task is locked waiting to send message */ + rt_psq_enq (p_MCB, 0); + rt_psh_req (); + } + rt_dec (&p_MCB->count); + if (++p_MCB->last == p_MCB->size) { + p_MCB->last = 0; + } + return (OS_R_MBX); + } + return (OS_R_OK); +} + + +/*--------------------------- rt_mbx_psh ------------------------------------*/ + +void rt_mbx_psh (P_MCB p_CB, void *p_msg) { + /* Store the message to the mailbox queue or pass it to task directly. */ + P_TCB p_TCB; + void *mem; + + if (p_CB->p_lnk != NULL) switch (p_CB->state) { +#ifdef __CMSIS_RTOS + case 3: + /* Task is waiting to allocate memory, remove it from the waiting list */ + mem = rt_alloc_box(p_msg); + if (mem == NULL) break; + p_TCB = rt_get_first ((P_XCB)p_CB); + rt_ret_val(p_TCB, (U32)mem); + p_TCB->state = READY; + rt_rmv_dly (p_TCB); + rt_put_prio (&os_rdy, p_TCB); + break; +#endif + case 2: + /* Task is waiting to send a message, remove it from the waiting list */ + p_TCB = rt_get_first ((P_XCB)p_CB); +#ifdef __CMSIS_RTOS + rt_ret_val(p_TCB, 0/*osOK*/); +#else + rt_ret_val(p_TCB, OS_R_OK); +#endif + p_CB->msg[p_CB->first] = p_TCB->msg; + rt_inc (&p_CB->count); + if (++p_CB->first == p_CB->size) { + p_CB->first = 0; + } + p_TCB->state = READY; + rt_rmv_dly (p_TCB); + rt_put_prio (&os_rdy, p_TCB); + break; + case 1: + /* Task is waiting for a message, pass the message to the task directly */ + p_TCB = rt_get_first ((P_XCB)p_CB); +#ifdef __CMSIS_RTOS + rt_ret_val2(p_TCB, 0x10/*osEventMessage*/, (U32)p_msg); +#else + *p_TCB->msg = p_msg; + rt_ret_val (p_TCB, OS_R_MBX); +#endif + p_TCB->state = READY; + rt_rmv_dly (p_TCB); + rt_put_prio (&os_rdy, p_TCB); + break; + } else { + /* No task is waiting for a message, store it to the mailbox queue */ + if (p_CB->count < p_CB->size) { + p_CB->msg[p_CB->first] = p_msg; + rt_inc (&p_CB->count); + if (++p_CB->first == p_CB->size) { + p_CB->first = 0; + } + } + else { + os_error (OS_ERR_MBX_OVF); + } + } +} + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_Mailbox.h b/libraries/rtos/rtx/TARGET_ARM7/rt_Mailbox.h new file mode 100644 index 0000000000..0c8e2f39b2 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_Mailbox.h @@ -0,0 +1,48 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_MAILBOX.H + * Purpose: Implements waits and wake-ups for mailbox messages + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Functions */ +extern void rt_mbx_init (OS_ID mailbox, U16 mbx_size); +extern OS_RESULT rt_mbx_send (OS_ID mailbox, void *p_msg, U16 timeout); +extern OS_RESULT rt_mbx_wait (OS_ID mailbox, void **message, U16 timeout); +extern OS_RESULT rt_mbx_check (OS_ID mailbox); +extern void isr_mbx_send (OS_ID mailbox, void *p_msg); +extern OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message); +extern void rt_mbx_psh (P_MCB p_CB, void *p_msg); + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_MemBox.c b/libraries/rtos/rtx/TARGET_ARM7/rt_MemBox.c new file mode 100644 index 0000000000..5b96ae0e65 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_MemBox.c @@ -0,0 +1,166 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_MEMBOX.C + * Purpose: Interface functions for fixed memory block management system + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Conf.h" +#include "rt_System.h" +#include "rt_MemBox.h" +#include "rt_HAL_CM.h" + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + + +/*--------------------------- _init_box -------------------------------------*/ + +int _init_box (void *box_mem, U32 box_size, U32 blk_size) { + /* Initialize memory block system, returns 0 if OK, 1 if fails. */ + void *end; + void *blk; + void *next; + U32 sizeof_bm; + + /* Create memory structure. */ + if (blk_size & BOX_ALIGN_8) { + /* Memory blocks 8-byte aligned. */ + blk_size = ((blk_size & ~BOX_ALIGN_8) + 7) & ~7; + sizeof_bm = (sizeof (struct OS_BM) + 7) & ~7; + } + else { + /* Memory blocks 4-byte aligned. */ + blk_size = (blk_size + 3) & ~3; + sizeof_bm = sizeof (struct OS_BM); + } + if (blk_size == 0) { + return (1); + } + if ((blk_size + sizeof_bm) > box_size) { + return (1); + } + /* Create a Memory structure. */ + blk = ((U8 *) box_mem) + sizeof_bm; + ((P_BM) box_mem)->free = blk; + end = ((U8 *) box_mem) + box_size; + ((P_BM) box_mem)->end = end; + ((P_BM) box_mem)->blk_size = blk_size; + + /* Link all free blocks using offsets. */ + end = ((U8 *) end) - blk_size; + while (1) { + next = ((U8 *) blk) + blk_size; + if (next > end) break; + *((void **)blk) = next; + blk = next; + } + /* end marker */ + *((void **)blk) = 0; + return (0); +} + +/*--------------------------- rt_alloc_box ----------------------------------*/ + +void *rt_alloc_box (void *box_mem) { + /* Allocate a memory block and return start address. */ + void **free; +#ifndef __USE_EXCLUSIVE_ACCESS + int irq_dis; + + irq_dis = __disable_irq (); + free = ((P_BM) box_mem)->free; + if (free) { + ((P_BM) box_mem)->free = *free; + } + if (!irq_dis) __enable_irq (); +#else + do { + if ((free = (void **)__ldrex(&((P_BM) box_mem)->free)) == 0) { + __clrex(); + break; + } + } while (__strex((U32)*free, &((P_BM) box_mem)->free)); +#endif + return (free); +} + + +/*--------------------------- _calloc_box -----------------------------------*/ + +void *_calloc_box (void *box_mem) { + /* Allocate a 0-initialized memory block and return start address. */ + void *free; + U32 *p; + U32 i; + + free = _alloc_box (box_mem); + if (free) { + p = free; + for (i = ((P_BM) box_mem)->blk_size; i; i -= 4) { + *p = 0; + p++; + } + } + return (free); +} + + +/*--------------------------- rt_free_box -----------------------------------*/ + +int rt_free_box (void *box_mem, void *box) { + /* Free a memory block, returns 0 if OK, 1 if box does not belong to box_mem */ +#ifndef __USE_EXCLUSIVE_ACCESS + int irq_dis; +#endif + + if (box < box_mem || box >= ((P_BM) box_mem)->end) { + return (1); + } + +#ifndef __USE_EXCLUSIVE_ACCESS + irq_dis = __disable_irq (); + *((void **)box) = ((P_BM) box_mem)->free; + ((P_BM) box_mem)->free = box; + if (!irq_dis) __enable_irq (); +#else + do { + *((void **)box) = (void *)__ldrex(&((P_BM) box_mem)->free); + } while (__strex ((U32)box, &((P_BM) box_mem)->free)); +#endif + return (0); +} + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_MemBox.h b/libraries/rtos/rtx/TARGET_ARM7/rt_MemBox.h new file mode 100644 index 0000000000..c10a1cbe70 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_MemBox.h @@ -0,0 +1,46 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_MEMBOX.H + * Purpose: Interface functions for fixed memory block management system + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Functions */ +#define rt_init_box _init_box +#define rt_calloc_box _calloc_box +extern int _init_box (void *box_mem, U32 box_size, U32 blk_size); +extern void *rt_alloc_box (void *box_mem); +extern void * _calloc_box (void *box_mem); +extern int rt_free_box (void *box_mem, void *box); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_Mutex.c b/libraries/rtos/rtx/TARGET_ARM7/rt_Mutex.c new file mode 100644 index 0000000000..c7a996bb50 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_Mutex.c @@ -0,0 +1,197 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_MUTEX.C + * Purpose: Implements mutex synchronization objects + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Conf.h" +#include "rt_List.h" +#include "rt_Task.h" +#include "rt_Mutex.h" +#include "rt_HAL_CM.h" + + +/*---------------------------------------------------------------------------- + * Functions + *---------------------------------------------------------------------------*/ + + +/*--------------------------- rt_mut_init -----------------------------------*/ + +void rt_mut_init (OS_ID mutex) { + /* Initialize a mutex object */ + P_MUCB p_MCB = mutex; + + p_MCB->cb_type = MUCB; + p_MCB->prio = 0; + p_MCB->level = 0; + p_MCB->p_lnk = NULL; + p_MCB->owner = NULL; +} + + +/*--------------------------- rt_mut_delete ---------------------------------*/ + +#ifdef __CMSIS_RTOS +OS_RESULT rt_mut_delete (OS_ID mutex) { + /* Delete a mutex object */ + P_MUCB p_MCB = mutex; + P_TCB p_TCB; + + /* Restore owner task's priority. */ + if (p_MCB->level != 0) { + p_MCB->owner->prio = p_MCB->prio; + if (p_MCB->owner != os_tsk.run) { + rt_resort_prio (p_MCB->owner); + } + } + + while (p_MCB->p_lnk != NULL) { + /* A task is waiting for mutex. */ + p_TCB = rt_get_first ((P_XCB)p_MCB); + rt_ret_val(p_TCB, 0/*osOK*/); + rt_rmv_dly(p_TCB); + p_TCB->state = READY; + rt_put_prio (&os_rdy, p_TCB); + } + + if (os_rdy.p_lnk && (os_rdy.p_lnk->prio > os_tsk.run->prio)) { + /* preempt running task */ + rt_put_prio (&os_rdy, os_tsk.run); + os_tsk.run->state = READY; + rt_dispatch (NULL); + } + + p_MCB->cb_type = 0; + + return (OS_R_OK); +} +#endif + + +/*--------------------------- rt_mut_release --------------------------------*/ + +OS_RESULT rt_mut_release (OS_ID mutex) { + /* Release a mutex object */ + P_MUCB p_MCB = mutex; + P_TCB p_TCB; + + if (p_MCB->level == 0 || p_MCB->owner != os_tsk.run) { + /* Unbalanced mutex release or task is not the owner */ + return (OS_R_NOK); + } + if (--p_MCB->level != 0) { + return (OS_R_OK); + } + /* Restore owner task's priority. */ + os_tsk.run->prio = p_MCB->prio; + if (p_MCB->p_lnk != NULL) { + /* A task is waiting for mutex. */ + p_TCB = rt_get_first ((P_XCB)p_MCB); +#ifdef __CMSIS_RTOS + rt_ret_val(p_TCB, 0/*osOK*/); +#else + rt_ret_val(p_TCB, OS_R_MUT); +#endif + rt_rmv_dly (p_TCB); + /* A waiting task becomes the owner of this mutex. */ + p_MCB->level = 1; + p_MCB->owner = p_TCB; + p_MCB->prio = p_TCB->prio; + /* Priority inversion, check which task continues. */ + if (os_tsk.run->prio >= rt_rdy_prio()) { + rt_dispatch (p_TCB); + } + else { + /* Ready task has higher priority than running task. */ + rt_put_prio (&os_rdy, os_tsk.run); + rt_put_prio (&os_rdy, p_TCB); + os_tsk.run->state = READY; + p_TCB->state = READY; + rt_dispatch (NULL); + } + } + else { + /* Check if own priority raised by priority inversion. */ + if (rt_rdy_prio() > os_tsk.run->prio) { + rt_put_prio (&os_rdy, os_tsk.run); + os_tsk.run->state = READY; + rt_dispatch (NULL); + } + } + return (OS_R_OK); +} + + +/*--------------------------- rt_mut_wait -----------------------------------*/ + +OS_RESULT rt_mut_wait (OS_ID mutex, U16 timeout) { + /* Wait for a mutex, continue when mutex is free. */ + P_MUCB p_MCB = mutex; + + if (p_MCB->level == 0) { + p_MCB->owner = os_tsk.run; + p_MCB->prio = os_tsk.run->prio; + goto inc; + } + if (p_MCB->owner == os_tsk.run) { + /* OK, running task is the owner of this mutex. */ +inc:p_MCB->level++; + return (OS_R_OK); + } + /* Mutex owned by another task, wait until released. */ + if (timeout == 0) { + return (OS_R_TMO); + } + /* Raise the owner task priority if lower than current priority. */ + /* This priority inversion is called priority inheritance. */ + if (p_MCB->prio < os_tsk.run->prio) { + p_MCB->owner->prio = os_tsk.run->prio; + rt_resort_prio (p_MCB->owner); + } + if (p_MCB->p_lnk != NULL) { + rt_put_prio ((P_XCB)p_MCB, os_tsk.run); + } + else { + p_MCB->p_lnk = os_tsk.run; + os_tsk.run->p_lnk = NULL; + os_tsk.run->p_rlnk = (P_TCB)p_MCB; + } + rt_block(timeout, WAIT_MUT); + return (OS_R_TMO); +} + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_Mutex.h b/libraries/rtos/rtx/TARGET_ARM7/rt_Mutex.h new file mode 100644 index 0000000000..bf15c4d56c --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_Mutex.h @@ -0,0 +1,44 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_MUTEX.H + * Purpose: Implements mutex synchronization objects + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Functions */ +extern void rt_mut_init (OS_ID mutex); +extern OS_RESULT rt_mut_delete (OS_ID mutex); +extern OS_RESULT rt_mut_release (OS_ID mutex); +extern OS_RESULT rt_mut_wait (OS_ID mutex, U16 timeout); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_Robin.c b/libraries/rtos/rtx/TARGET_ARM7/rt_Robin.c new file mode 100644 index 0000000000..d693dc6524 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_Robin.c @@ -0,0 +1,84 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_ROBIN.C + * Purpose: Round Robin Task switching + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Conf.h" +#include "rt_List.h" +#include "rt_Task.h" +#include "rt_Time.h" +#include "rt_Robin.h" +#include "rt_HAL_CM.h" + +/*---------------------------------------------------------------------------- + * Global Variables + *---------------------------------------------------------------------------*/ + +struct OS_ROBIN os_robin; + + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +/*--------------------------- rt_init_robin ---------------------------------*/ + +__weak void rt_init_robin (void) { + /* Initialize Round Robin variables. */ + os_robin.task = NULL; + os_robin.tout = (U16)os_rrobin; +} + +/*--------------------------- rt_chk_robin ----------------------------------*/ + +__weak void rt_chk_robin (void) { + /* Check if Round Robin timeout expired and switch to the next ready task.*/ + P_TCB p_new; + + if (os_robin.task != os_rdy.p_lnk) { + /* New task was suspended, reset Round Robin timeout. */ + os_robin.task = os_rdy.p_lnk; + os_robin.time = (U16)os_time + os_robin.tout - 1; + } + if (os_robin.time == (U16)os_time) { + /* Round Robin timeout has expired, swap Robin tasks. */ + os_robin.task = NULL; + p_new = rt_get_first (&os_rdy); + rt_put_prio ((P_XCB)&os_rdy, p_new); + } +} + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_Robin.h b/libraries/rtos/rtx/TARGET_ARM7/rt_Robin.h new file mode 100644 index 0000000000..3ccbffcffd --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_Robin.h @@ -0,0 +1,45 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_ROBIN.H + * Purpose: Round Robin Task switching definitions + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Variables */ +extern struct OS_ROBIN os_robin; + +/* Functions */ +extern void rt_init_robin (void); +extern void rt_chk_robin (void); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_Semaphore.c b/libraries/rtos/rtx/TARGET_ARM7/rt_Semaphore.c new file mode 100644 index 0000000000..93ff2bf083 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_Semaphore.c @@ -0,0 +1,183 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_SEMAPHORE.C + * Purpose: Implements binary and counting semaphores + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Conf.h" +#include "rt_System.h" +#include "rt_List.h" +#include "rt_Task.h" +#include "rt_Semaphore.h" +#include "rt_HAL_CM.h" + + +/*---------------------------------------------------------------------------- + * Functions + *---------------------------------------------------------------------------*/ + + +/*--------------------------- rt_sem_init -----------------------------------*/ + +void rt_sem_init (OS_ID semaphore, U16 token_count) { + /* Initialize a semaphore */ + P_SCB p_SCB = semaphore; + + p_SCB->cb_type = SCB; + p_SCB->p_lnk = NULL; + p_SCB->tokens = token_count; +} + + +/*--------------------------- rt_sem_delete ---------------------------------*/ + +#ifdef __CMSIS_RTOS +OS_RESULT rt_sem_delete (OS_ID semaphore) { + /* Delete semaphore */ + P_SCB p_SCB = semaphore; + P_TCB p_TCB; + + while (p_SCB->p_lnk != NULL) { + /* A task is waiting for token */ + p_TCB = rt_get_first ((P_XCB)p_SCB); + rt_ret_val(p_TCB, 0); + rt_rmv_dly(p_TCB); + p_TCB->state = READY; + rt_put_prio (&os_rdy, p_TCB); + } + + if (os_rdy.p_lnk && (os_rdy.p_lnk->prio > os_tsk.run->prio)) { + /* preempt running task */ + rt_put_prio (&os_rdy, os_tsk.run); + os_tsk.run->state = READY; + rt_dispatch (NULL); + } + + p_SCB->cb_type = 0; + + return (OS_R_OK); +} +#endif + + +/*--------------------------- rt_sem_send -----------------------------------*/ + +OS_RESULT rt_sem_send (OS_ID semaphore) { + /* Return a token to semaphore */ + P_SCB p_SCB = semaphore; + P_TCB p_TCB; + + if (p_SCB->p_lnk != NULL) { + /* A task is waiting for token */ + p_TCB = rt_get_first ((P_XCB)p_SCB); +#ifdef __CMSIS_RTOS + rt_ret_val(p_TCB, 1); +#else + rt_ret_val(p_TCB, OS_R_SEM); +#endif + rt_rmv_dly (p_TCB); + rt_dispatch (p_TCB); + } + else { + /* Store token. */ + p_SCB->tokens++; + } + return (OS_R_OK); +} + + +/*--------------------------- rt_sem_wait -----------------------------------*/ + +OS_RESULT rt_sem_wait (OS_ID semaphore, U16 timeout) { + /* Obtain a token; possibly wait for it */ + P_SCB p_SCB = semaphore; + + if (p_SCB->tokens) { + p_SCB->tokens--; + return (OS_R_OK); + } + /* No token available: wait for one */ + if (timeout == 0) { + return (OS_R_TMO); + } + if (p_SCB->p_lnk != NULL) { + rt_put_prio ((P_XCB)p_SCB, os_tsk.run); + } + else { + p_SCB->p_lnk = os_tsk.run; + os_tsk.run->p_lnk = NULL; + os_tsk.run->p_rlnk = (P_TCB)p_SCB; + } + rt_block(timeout, WAIT_SEM); + return (OS_R_TMO); +} + + +/*--------------------------- isr_sem_send ----------------------------------*/ + +void isr_sem_send (OS_ID semaphore) { + /* Same function as "os_sem"send", but to be called by ISRs */ + P_SCB p_SCB = semaphore; + + rt_psq_enq (p_SCB, 0); + rt_psh_req (); +} + + +/*--------------------------- rt_sem_psh ------------------------------------*/ + +void rt_sem_psh (P_SCB p_CB) { + /* Check if task has to be waken up */ + P_TCB p_TCB; + + if (p_CB->p_lnk != NULL) { + /* A task is waiting for token */ + p_TCB = rt_get_first ((P_XCB)p_CB); + rt_rmv_dly (p_TCB); + p_TCB->state = READY; +#ifdef __CMSIS_RTOS + rt_ret_val(p_TCB, 1); +#else + rt_ret_val(p_TCB, OS_R_SEM); +#endif + rt_put_prio (&os_rdy, p_TCB); + } + else { + /* Store token */ + p_CB->tokens++; + } +} + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_Semaphore.h b/libraries/rtos/rtx/TARGET_ARM7/rt_Semaphore.h new file mode 100644 index 0000000000..ec4548000b --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_Semaphore.h @@ -0,0 +1,46 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_SEMAPHORE.H + * Purpose: Implements binary and counting semaphores + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Functions */ +extern void rt_sem_init (OS_ID semaphore, U16 token_count); +extern OS_RESULT rt_sem_delete(OS_ID semaphore); +extern OS_RESULT rt_sem_send (OS_ID semaphore); +extern OS_RESULT rt_sem_wait (OS_ID semaphore, U16 timeout); +extern void isr_sem_send (OS_ID semaphore); +extern void rt_sem_psh (P_SCB p_CB); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_System.c b/libraries/rtos/rtx/TARGET_ARM7/rt_System.c new file mode 100644 index 0000000000..97a3bab4d7 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_System.c @@ -0,0 +1,293 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_SYSTEM.C + * Purpose: System Task Manager + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Conf.h" +#include "rt_Task.h" +#include "rt_System.h" +#include "rt_Event.h" +#include "rt_List.h" +#include "rt_Mailbox.h" +#include "rt_Semaphore.h" +#include "rt_Time.h" +#include "rt_Robin.h" +#include "rt_HAL_CM.h" + +/*---------------------------------------------------------------------------- + * Global Variables + *---------------------------------------------------------------------------*/ + +int os_tick_irqn; + +/*---------------------------------------------------------------------------- + * Local Variables + *---------------------------------------------------------------------------*/ + +static volatile BIT os_lock; +static volatile BIT os_psh_flag; +static U8 pend_flags; + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +#if defined (__CC_ARM) +__asm void $$RTX$$version (void) { + /* Export a version number symbol for a version control. */ + + EXPORT __RL_RTX_VER + +__RL_RTX_VER EQU 0x450 +} +#endif + + +/*--------------------------- rt_suspend ------------------------------------*/ +U32 rt_suspend (void) { + /* Suspend OS scheduler */ + U32 delta = 0xFFFF; + + rt_tsk_lock(); + + if (os_dly.p_dlnk) { + delta = os_dly.delta_time; + } +#ifndef __CMSIS_RTOS + if (os_tmr.next) { + if (os_tmr.tcnt < delta) delta = os_tmr.tcnt; + } +#endif + + return (delta); +} + + +/*--------------------------- rt_resume -------------------------------------*/ +void rt_resume (U32 sleep_time) { + /* Resume OS scheduler after suspend */ + P_TCB next; + U32 delta; + + os_tsk.run->state = READY; + rt_put_rdy_first (os_tsk.run); + + os_robin.task = NULL; + + /* Update delays. */ + if (os_dly.p_dlnk) { + delta = sleep_time; + if (delta >= os_dly.delta_time) { + delta -= os_dly.delta_time; + os_time += os_dly.delta_time; + os_dly.delta_time = 1; + while (os_dly.p_dlnk) { + rt_dec_dly(); + if (delta == 0) break; + delta--; + os_time++; + } + } else { + os_time += delta; + os_dly.delta_time -= delta; + } + } else { + os_time += sleep_time; + } + +#ifndef __CMSIS_RTOS + /* Check the user timers. */ + if (os_tmr.next) { + delta = sleep_time; + if (delta >= os_tmr.tcnt) { + delta -= os_tmr.tcnt; + os_tmr.tcnt = 1; + while (os_tmr.next) { + rt_tmr_tick(); + if (delta == 0) break; + delta--; + } + } else { + os_tmr.tcnt -= delta; + } + } +#endif + + /* Switch back to highest ready task */ + next = rt_get_first (&os_rdy); + rt_switch_req (next); + + rt_tsk_unlock(); +} + + +/*--------------------------- rt_tsk_lock -----------------------------------*/ + +void rt_tsk_lock (void) { + /* Prevent task switching by locking out scheduler */ + OS_X_LOCK(os_tick_irqn); + os_lock = __TRUE; + OS_X_UNPEND (&pend_flags); +} + + +/*--------------------------- rt_tsk_unlock ---------------------------------*/ + +void rt_tsk_unlock (void) { + /* Unlock scheduler and re-enable task switching */ + OS_X_UNLOCK(os_tick_irqn); + os_lock = __FALSE; + OS_X_PEND (pend_flags, os_psh_flag); + os_psh_flag = __FALSE; +} + + +/*--------------------------- rt_psh_req ------------------------------------*/ + +void rt_psh_req (void) { + /* Initiate a post service handling request if required. */ + if (os_lock == __FALSE) { + OS_PEND_IRQ (); + } + else { + os_psh_flag = __TRUE; + } +} + + +/*--------------------------- rt_pop_req ------------------------------------*/ + +void rt_pop_req (void) { + /* Process an ISR post service requests. */ + struct OS_XCB *p_CB; + P_TCB next; + U32 idx; + + os_tsk.run->state = READY; + rt_put_rdy_first (os_tsk.run); + + idx = os_psq->last; + while (os_psq->count) { + p_CB = os_psq->q[idx].id; + if (p_CB->cb_type == TCB) { + /* Is of TCB type */ + rt_evt_psh ((P_TCB)p_CB, (U16)os_psq->q[idx].arg); + } + else if (p_CB->cb_type == MCB) { + /* Is of MCB type */ + rt_mbx_psh ((P_MCB)p_CB, (void *)os_psq->q[idx].arg); + } + else { + /* Must be of SCB type */ + rt_sem_psh ((P_SCB)p_CB); + } + if (++idx == os_psq->size) idx = 0; + rt_dec (&os_psq->count); + } + os_psq->last = idx; + + next = rt_get_first (&os_rdy); + rt_switch_req (next); +} + + +/*--------------------------- os_tick_init ----------------------------------*/ + +__weak int os_tick_init (void) { + /* Initialize SysTick timer as system tick timer. */ + rt_systick_init (); + return (SYS_TICK_IRQn); /* Return IRQ number of SysTick timer */ +} + + +/*--------------------------- os_tick_irqack --------------------------------*/ + +__weak void os_tick_irqack (void) { + /* Acknowledge timer interrupt. */ +} + + +/*--------------------------- rt_systick ------------------------------------*/ + +extern void sysTimerTick(void); + +void rt_systick (void) { + if(NVIC_Pending(SYS_TICK_IRQn)){ + rt_pop_req(); + NVIC_UnpendIRQ(SYS_TICK_IRQn); + SYS_TICK_TIMER->IR = 0xF; // clear timer interrupt + return; + } + /* Check for system clock update, suspend running task. */ + P_TCB next; + + os_tsk.run->state = READY; + rt_put_rdy_first (os_tsk.run); + + /* Check Round Robin timeout. */ + rt_chk_robin (); + + /* Update delays. */ + os_time++; + rt_dec_dly (); + + /* Check the user timers. */ +#ifdef __CMSIS_RTOS + sysTimerTick(); +#else + rt_tmr_tick (); +#endif + + /* Switch back to highest ready task */ + next = rt_get_first (&os_rdy); + rt_switch_req (next); + SYS_TICK_TIMER->IR = 0xF; // clear timer interrupt +} + +/*--------------------------- rt_stk_check ----------------------------------*/ +__weak void rt_stk_check (void) { + /* Check for stack overflow. */ + if (os_tsk.run->task_id == 0x01) { + // TODO: For the main thread the check should be done against the main heap pointer + } else { + if ((os_tsk.run->tsk_stack < (U32)os_tsk.run->stack) || + (os_tsk.run->stack[0] != MAGIC_WORD)) { + os_error (OS_ERR_STK_OVF); + } + } +} + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_System.h b/libraries/rtos/rtx/TARGET_ARM7/rt_System.h new file mode 100644 index 0000000000..91db6487e0 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_System.h @@ -0,0 +1,52 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_SYSTEM.H + * Purpose: System Task Manager definitions + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Variables */ +#define os_psq ((P_PSQ)&os_fifo) +extern int os_tick_irqn; + +/* Functions */ +extern U32 rt_suspend (void); +extern void rt_resume (U32 sleep_time); +extern void rt_tsk_lock (void); +extern void rt_tsk_unlock (void); +extern void rt_psh_req (void); +extern void rt_pop_req (void); +extern void rt_systick (void); +extern void rt_stk_check (void); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_Task.c b/libraries/rtos/rtx/TARGET_ARM7/rt_Task.c new file mode 100644 index 0000000000..76281b1331 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_Task.c @@ -0,0 +1,341 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_TASK.C + * Purpose: Task functions and system start up. + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Conf.h" +#include "rt_System.h" +#include "rt_Task.h" +#include "rt_List.h" +#include "rt_MemBox.h" +#include "rt_Robin.h" +#include "rt_HAL_CM.h" + +/*---------------------------------------------------------------------------- + * Global Variables + *---------------------------------------------------------------------------*/ + +/* Running and next task info. */ +struct OS_TSK os_tsk; + +/* Task Control Blocks of idle demon */ +struct OS_TCB os_idle_TCB; + + +/*---------------------------------------------------------------------------- + * Local Functions + *---------------------------------------------------------------------------*/ + +OS_TID rt_get_TID (void) { + U32 tid; + + for (tid = 1; tid <= os_maxtaskrun; tid++) { + if (os_active_TCB[tid-1] == NULL) { + return ((OS_TID)tid); + } + } + return (0); +} + +#if defined (__CC_ARM) && !defined (__MICROLIB) +/*--------------------------- __user_perthread_libspace ---------------------*/ +extern void *__libspace_start; + +void *__user_perthread_libspace (void) { + /* Provide a separate libspace for each task. */ + if (os_tsk.run == NULL) { + /* RTX not running yet. */ + return (&__libspace_start); + } + return (void *)(os_tsk.run->std_libspace); +} +#endif + +/*--------------------------- rt_init_context -------------------------------*/ + +void rt_init_context (P_TCB p_TCB, U8 priority, FUNCP task_body) { + /* Initialize general part of the Task Control Block. */ + p_TCB->cb_type = TCB; + p_TCB->state = READY; + p_TCB->prio = priority; + p_TCB->p_lnk = NULL; + p_TCB->p_rlnk = NULL; + p_TCB->p_dlnk = NULL; + p_TCB->p_blnk = NULL; + p_TCB->delta_time = 0; + p_TCB->interval_time = 0; + p_TCB->events = 0; + p_TCB->waits = 0; + p_TCB->stack_frame = 0; + + rt_init_stack (p_TCB, task_body); +} + + +/*--------------------------- rt_switch_req ---------------------------------*/ + +void rt_switch_req (P_TCB p_new) { + /* Switch to next task (identified by "p_new"). */ + os_tsk.new_tsk = p_new; + p_new->state = RUNNING; + DBG_TASK_SWITCH(p_new->task_id); +} + + +/*--------------------------- rt_dispatch -----------------------------------*/ + +void rt_dispatch (P_TCB next_TCB) { + /* Dispatch next task if any identified or dispatch highest ready task */ + /* "next_TCB" identifies a task to run or has value NULL (=no next task) */ + if (next_TCB == NULL) { + /* Running task was blocked: continue with highest ready task */ + next_TCB = rt_get_first (&os_rdy); + rt_switch_req (next_TCB); + } + else { + /* Check which task continues */ + if (next_TCB->prio > os_tsk.run->prio) { + /* preempt running task */ + rt_put_rdy_first (os_tsk.run); + os_tsk.run->state = READY; + rt_switch_req (next_TCB); + } + else { + /* put next task into ready list, no task switch takes place */ + next_TCB->state = READY; + rt_put_prio (&os_rdy, next_TCB); + } + } +} + + +/*--------------------------- rt_block --------------------------------------*/ + +void rt_block (U16 timeout, U8 block_state) { + /* Block running task and choose next ready task. */ + /* "timeout" sets a time-out value or is 0xffff (=no time-out). */ + /* "block_state" defines the appropriate task state */ + P_TCB next_TCB; + + if (timeout) { + if (timeout < 0xffff) { + rt_put_dly (os_tsk.run, timeout); + } + os_tsk.run->state = block_state; + next_TCB = rt_get_first (&os_rdy); + rt_switch_req (next_TCB); + } +} + + +/*--------------------------- rt_tsk_pass -----------------------------------*/ + +void rt_tsk_pass (void) { + /* Allow tasks of same priority level to run cooperatively.*/ + P_TCB p_new; + + p_new = rt_get_same_rdy_prio(); + if (p_new != NULL) { + rt_put_prio ((P_XCB)&os_rdy, os_tsk.run); + os_tsk.run->state = READY; + rt_switch_req (p_new); + } +} + + +/*--------------------------- rt_tsk_self -----------------------------------*/ + +OS_TID rt_tsk_self (void) { + /* Return own task identifier value. */ + if (os_tsk.run == NULL) { + return (0); + } + return (os_tsk.run->task_id); +} + + +/*--------------------------- rt_tsk_prio -----------------------------------*/ + +OS_RESULT rt_tsk_prio (OS_TID task_id, U8 new_prio) { + /* Change execution priority of a task to "new_prio". */ + P_TCB p_task; + + if (task_id == 0) { + /* Change execution priority of calling task. */ + os_tsk.run->prio = new_prio; +run:if (rt_rdy_prio() > new_prio) { + rt_put_prio (&os_rdy, os_tsk.run); + os_tsk.run->state = READY; + rt_dispatch (NULL); + } + return (OS_R_OK); + } + + /* Find the task in the "os_active_TCB" array. */ + if (task_id > os_maxtaskrun || os_active_TCB[task_id-1] == NULL) { + /* Task with "task_id" not found or not started. */ + return (OS_R_NOK); + } + p_task = os_active_TCB[task_id-1]; + p_task->prio = new_prio; + if (p_task == os_tsk.run) { + goto run; + } + rt_resort_prio (p_task); + if (p_task->state == READY) { + /* Task enqueued in a ready list. */ + p_task = rt_get_first (&os_rdy); + rt_dispatch (p_task); + } + return (OS_R_OK); +} + +/*--------------------------- rt_tsk_delete ---------------------------------*/ + +OS_RESULT rt_tsk_delete (OS_TID task_id) { + /* Terminate the task identified with "task_id". */ + P_TCB task_context; + + if (task_id == 0 || task_id == os_tsk.run->task_id) { + /* Terminate itself. */ + os_tsk.run->state = INACTIVE; + os_tsk.run->tsk_stack = 0; + rt_stk_check (); + os_active_TCB[os_tsk.run->task_id-1] = NULL; + + os_tsk.run->stack = NULL; + DBG_TASK_NOTIFY(os_tsk.run, __FALSE); + os_tsk.run = NULL; + rt_dispatch (NULL); + /* The program should never come to this point. */ + } + else { + /* Find the task in the "os_active_TCB" array. */ + if (task_id > os_maxtaskrun || os_active_TCB[task_id-1] == NULL) { + /* Task with "task_id" not found or not started. */ + return (OS_R_NOK); + } + task_context = os_active_TCB[task_id-1]; + rt_rmv_list (task_context); + rt_rmv_dly (task_context); + os_active_TCB[task_id-1] = NULL; + + task_context->stack = NULL; + DBG_TASK_NOTIFY(task_context, __FALSE); + } + return (OS_R_OK); +} + + +/*--------------------------- rt_sys_init -----------------------------------*/ + +#ifdef __CMSIS_RTOS +void rt_sys_init (void) { +#else +void rt_sys_init (FUNCP first_task, U32 prio_stksz, void *stk) { +#endif + /* Initialize system and start up task declared with "first_task". */ + U32 i; + + DBG_INIT(); + + /* Initialize dynamic memory and task TCB pointers to NULL. */ + for (i = 0; i < os_maxtaskrun; i++) { + os_active_TCB[i] = NULL; + } + + /* Set up TCB of idle demon */ + os_idle_TCB.task_id = 255; + os_idle_TCB.priv_stack = idle_task_stack_size; + os_idle_TCB.stack = idle_task_stack; + rt_init_context (&os_idle_TCB, 0, os_idle_demon); + + /* Set up ready list: initially empty */ + os_rdy.cb_type = HCB; + os_rdy.p_lnk = NULL; + /* Set up delay list: initially empty */ + os_dly.cb_type = HCB; + os_dly.p_dlnk = NULL; + os_dly.p_blnk = NULL; + os_dly.delta_time = 0; + + /* Fix SP and systemvariables to assume idle task is running */ + /* Transform main program into idle task by assuming idle TCB */ +#ifndef __CMSIS_RTOS + rt_set_PSP (os_idle_TCB.tsk_stack); +#endif + os_tsk.run = &os_idle_TCB; + os_tsk.run->state = RUNNING; + + /* Initialize ps queue */ + os_psq->first = 0; + os_psq->last = 0; + os_psq->size = os_fifo_size; + + rt_init_robin (); + + /* Intitialize SVC and PendSV */ + rt_svc_init (); + +#ifndef __CMSIS_RTOS + /* Intitialize and start system clock timer */ + os_tick_irqn = os_tick_init (); + if (os_tick_irqn >= 0) { + OS_X_INIT(os_tick_irqn); + } + + /* Start up first user task before entering the endless loop */ + rt_tsk_create (first_task, prio_stksz, stk, NULL); +#endif +} + + +/*--------------------------- rt_sys_start ----------------------------------*/ + +#ifdef __CMSIS_RTOS +void rt_sys_start (void) { + /* Start system */ + + /* Intitialize and start system clock timer */ + os_tick_irqn = os_tick_init (); + if (os_tick_irqn >= 0) { + OS_X_INIT(os_tick_irqn); + } + extern void RestoreContext(); + RestoreContext(); // Start the first task +} +#endif + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_Task.h b/libraries/rtos/rtx/TARGET_ARM7/rt_Task.h new file mode 100644 index 0000000000..9d3727b5a6 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_Task.h @@ -0,0 +1,73 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_TASK.H + * Purpose: Task functions and system start up. + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Definitions */ +#define __CMSIS_RTOS 1 + +/* Values for 'state' */ +#define INACTIVE 0 +#define READY 1 +#define RUNNING 2 +#define WAIT_DLY 3 +#define WAIT_ITV 4 +#define WAIT_OR 5 +#define WAIT_AND 6 +#define WAIT_SEM 7 +#define WAIT_MBX 8 +#define WAIT_MUT 9 + +/* Return codes */ +#define OS_R_TMO 0x01 +#define OS_R_EVT 0x02 +#define OS_R_SEM 0x03 +#define OS_R_MBX 0x04 +#define OS_R_MUT 0x05 + +#define OS_R_OK 0x00 +#define OS_R_NOK 0xff + +/* Variables */ +extern struct OS_TSK os_tsk; +extern struct OS_TCB os_idle_TCB; + +/* Functions */ +extern void rt_switch_req (P_TCB p_new); +extern void rt_dispatch (P_TCB next_TCB); +extern void rt_block (U16 timeout, U8 block_state); +extern void rt_tsk_pass (void); +extern OS_TID rt_tsk_self (void); +extern OS_RESULT rt_tsk_prio (OS_TID task_id, U8 new_prio); +extern OS_RESULT rt_tsk_delete (OS_TID task_id); +extern void rt_sys_init (void); +extern void rt_sys_start (void); diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_Time.c b/libraries/rtos/rtx/TARGET_ARM7/rt_Time.c new file mode 100644 index 0000000000..b02ccebbad --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_Time.c @@ -0,0 +1,94 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_TIME.C + * Purpose: Delay and interval wait functions + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Conf.h" +#include "rt_Task.h" +#include "rt_Time.h" + +/*---------------------------------------------------------------------------- + * Global Variables + *---------------------------------------------------------------------------*/ + +/* Free running system tick counter */ +U32 os_time; + + +/*---------------------------------------------------------------------------- + * Functions + *---------------------------------------------------------------------------*/ + + +/*--------------------------- rt_time_get -----------------------------------*/ + +U32 rt_time_get (void) { + /* Get system time tick */ + return (os_time); +} + + +/*--------------------------- rt_dly_wait -----------------------------------*/ + +void rt_dly_wait (U16 delay_time) { + /* Delay task by "delay_time" */ + rt_block (delay_time, WAIT_DLY); +} + + +/*--------------------------- rt_itv_set ------------------------------------*/ + +void rt_itv_set (U16 interval_time) { + /* Set interval length and define start of first interval */ + os_tsk.run->interval_time = interval_time; + os_tsk.run->delta_time = interval_time + (U16)os_time; +} + + +/*--------------------------- rt_itv_wait -----------------------------------*/ + +void rt_itv_wait (void) { + /* Wait for interval end and define start of next one */ + U16 delta; + + delta = os_tsk.run->delta_time - (U16)os_time; + os_tsk.run->delta_time += os_tsk.run->interval_time; + if ((delta & 0x8000) == 0) { + rt_block (delta, WAIT_ITV); + } +} + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_Time.h b/libraries/rtos/rtx/TARGET_ARM7/rt_Time.h new file mode 100644 index 0000000000..27706373d5 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_Time.h @@ -0,0 +1,47 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_TIME.H + * Purpose: Delay and interval wait functions definitions + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Variables */ +extern U32 os_time; + +/* Functions */ +extern U32 rt_time_get (void); +extern void rt_dly_wait (U16 delay_time); +extern void rt_itv_set (U16 interval_time); +extern void rt_itv_wait (void); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_TypeDef.h b/libraries/rtos/rtx/TARGET_ARM7/rt_TypeDef.h new file mode 100644 index 0000000000..2adbe88cd8 --- /dev/null +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_TypeDef.h @@ -0,0 +1,128 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_TYPEDEF.H + * Purpose: Type Definitions + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +#ifndef RT_TYPE_DEF_H +#define RT_TYPE_DEF_H + +#include "os_tcb.h" + +typedef U32 OS_TID; +typedef void *OS_ID; +typedef U32 OS_RESULT; + +#define TCB_STACKF 32 /* 'stack_frame' offset */ +#define TCB_TSTACK 36 /* 'tsk_stack' offset */ + +typedef struct OS_PSFE { /* Post Service Fifo Entry */ + void *id; /* Object Identification */ + U32 arg; /* Object Argument */ +} *P_PSFE; + +typedef struct OS_PSQ { /* Post Service Queue */ + U8 first; /* FIFO Head Index */ + U8 last; /* FIFO Tail Index */ + U8 count; /* Number of stored items in FIFO */ + U8 size; /* FIFO Size */ + struct OS_PSFE q[1]; /* FIFO Content */ +} *P_PSQ; + +typedef struct OS_TSK { + P_TCB run; /* Current running task */ + P_TCB new_tsk; /* Scheduled task to run */ +} *P_TSK; + +typedef struct OS_ROBIN { /* Round Robin Control */ + P_TCB task; /* Round Robin task */ + U16 time; /* Round Robin switch time */ + U16 tout; /* Round Robin timeout */ +} *P_ROBIN; + +typedef struct OS_XCB { + U8 cb_type; /* Control Block Type */ + struct OS_TCB *p_lnk; /* Link pointer for ready/sem. wait list */ + struct OS_TCB *p_rlnk; /* Link pointer for sem./mbx lst backwards */ + struct OS_TCB *p_dlnk; /* Link pointer for delay list */ + struct OS_TCB *p_blnk; /* Link pointer for delay list backwards */ + U16 delta_time; /* Time until time out */ +} *P_XCB; + +typedef struct OS_MCB { + U8 cb_type; /* Control Block Type */ + U8 state; /* State flag variable */ + U8 isr_st; /* State flag variable for isr functions */ + struct OS_TCB *p_lnk; /* Chain of tasks waiting for message */ + U16 first; /* Index of the message list begin */ + U16 last; /* Index of the message list end */ + U16 count; /* Actual number of stored messages */ + U16 size; /* Maximum number of stored messages */ + void *msg[1]; /* FIFO for Message pointers 1st element */ +} *P_MCB; + +typedef struct OS_SCB { + U8 cb_type; /* Control Block Type */ + U8 mask; /* Semaphore token mask */ + U16 tokens; /* Semaphore tokens */ + struct OS_TCB *p_lnk; /* Chain of tasks waiting for tokens */ +} *P_SCB; + +typedef struct OS_MUCB { + U8 cb_type; /* Control Block Type */ + U8 prio; /* Owner task default priority */ + U16 level; /* Call nesting level */ + struct OS_TCB *p_lnk; /* Chain of tasks waiting for mutex */ + struct OS_TCB *owner; /* Mutex owner task */ +} *P_MUCB; + +typedef struct OS_XTMR { + struct OS_TMR *next; + U16 tcnt; +} *P_XTMR; + +typedef struct OS_TMR { + struct OS_TMR *next; /* Link pointer to Next timer */ + U16 tcnt; /* Timer delay count */ + U16 info; /* User defined call info */ +} *P_TMR; + +typedef struct OS_BM { + void *free; /* Pointer to first free memory block */ + void *end; /* Pointer to memory block end */ + U32 blk_size; /* Memory block size */ +} *P_BM; + +/* Definitions */ +#define __TRUE 1 +#define __FALSE 0 +#define NULL ((void *) 0) + +#endif From e81663306b2f4e1d79223fdcc87513e493867942 Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Thu, 19 Feb 2015 16:05:09 +0400 Subject: [PATCH 003/139] bugfix of SysTickTimer --- libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h b/libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h index f17972c7f8..56dff947fd 100644 --- a/libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h @@ -174,19 +174,19 @@ __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) { __inline static void rt_systick_init (void) { #if SYS_TICK_IRQn == TIMER0_IRQn #define SYS_TICK_TIMER LPC_TIM0 - LPC_SC->PCONP |= PCTIM0; + LPC_SC->PCONP |= (1 << PCTIM0); LPC_SC->PCLKSEL0 = (LPC_SC->PCLKSEL0 & (~(1<<3))) | (1<<2); //PCLK == CPUCLK #elif SYS_TICK_IRQn == TIMER1_IRQn #define SYS_TICK_TIMER LPC_TIM1 - LPC_SC->PCONP |= PCTIM1; + LPC_SC->PCONP |= (1 << PCTIM1); LPC_SC->PCLKSEL0 = (LPC_SC->PCLKSEL0 & (~(1<<5))) | (1<<4); //PCLK == CPUCLK #elif SYS_TICK_IRQn == TIMER2_IRQn #define SYS_TICK_TIMER LPC_TIM2 - LPC_SC->PCONP |= PCTIM2; + LPC_SC->PCONP |= (1 << PCTIM2); LPC_SC->PCLKSEL1 = (LPC_SC->PCLKSEL1 & (~(1<<13))) | (1<<12); //PCLK == CPUCLK #else #define SYS_TICK_TIMER LPC_TIM3 - LPC_SC->PCONP |= PCTIM3; + LPC_SC->PCONP |= (1 << PCTIM3); LPC_SC->PCLKSEL1 = (LPC_SC->PCLKSEL1 & (~(1<<15))) | (1<<14); //PCLK == CPUCLK #endif @@ -196,7 +196,7 @@ __inline static void rt_systick_init (void) { SYS_TICK_TIMER->TC = os_trv; SYS_TICK_TIMER->PR = 0; // set the prescale divider //Reset of TC and Interrupt when MR3 MR2 matches TC - SYS_TICK_TIMER->MCR = (1 << 6) |(1 << 7); //TMCR_MR3_R_Msk | TMCR_MR3_I_Msk + SYS_TICK_TIMER->MCR = (1 << 9) |(1 << 10); //TMCR_MR3_R_Msk | TMCR_MR3_I_Msk SYS_TICK_TIMER->MR3 = os_trv; // match registers SYS_TICK_TIMER->CCR = 0; // disable compare registers SYS_TICK_TIMER->EMR = 0; // disable external match register From 70fad08a4c52371061e53b114a6d90496e7be354 Mon Sep 17 00:00:00 2001 From: sg- Date: Fri, 10 Apr 2015 00:38:27 -0500 Subject: [PATCH 004/139] Update SPI API documentation for hardware driven SS. Modify all target spi_api.c implementations. spi_init ssel parameter was used incorrectly to determine master/slave mode rather than enable hardware driven SS (seems to be due to legacy copy paste). Remove duplicate copy paste code of initialization in spi_init that is done by constructor (SPI and SPISlave) --- libraries/mbed/api/SPI.h | 17 ++++++++++++---- libraries/mbed/api/SPISlave.h | 4 ---- libraries/mbed/common/SPI.cpp | 4 ++-- .../TARGET_Freescale/TARGET_K20XX/spi_api.c | 8 -------- .../TARGET_KLXX/TARGET_KL05Z/spi_api.c | 8 -------- .../TARGET_KLXX/TARGET_KL25Z/spi_api.c | 8 -------- .../TARGET_KLXX/TARGET_KL43Z/spi_api.c | 8 -------- .../TARGET_KLXX/TARGET_KL46Z/spi_api.c | 8 -------- .../TARGET_KPSDK_MCUS/spi_api.c | 7 ------- .../TARGET_Maxim/TARGET_MAX32610/spi_api.c | 4 ---- .../hal/TARGET_NXP/TARGET_LPC11U6X/spi_api.c | 11 ---------- .../hal/TARGET_NXP/TARGET_LPC11UXX/spi_api.c | 11 ---------- .../TARGET_NXP/TARGET_LPC11XX_11CXX/spi_api.c | 11 ---------- .../hal/TARGET_NXP/TARGET_LPC13XX/spi_api.c | 11 ---------- .../hal/TARGET_NXP/TARGET_LPC15XX/spi_api.c | 11 ---------- .../hal/TARGET_NXP/TARGET_LPC176X/spi_api.c | 11 ---------- .../hal/TARGET_NXP/TARGET_LPC23XX/spi_api.c | 11 ---------- .../TARGET_LPC408X/TARGET_LPC4088/spi_api.c | 11 ---------- .../TARGET_LPC4088_DM/spi_api.c | 11 ---------- .../hal/TARGET_NXP/TARGET_LPC43XX/spi_api.c | 11 ---------- .../hal/TARGET_NXP/TARGET_LPC81X/spi_api.c | 11 ---------- .../hal/TARGET_NXP/TARGET_LPC82X/spi_api.c | 10 ---------- .../TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c | 8 -------- .../hal/TARGET_STM/TARGET_STM32F0/spi_api.c | 20 ++++++++----------- .../hal/TARGET_STM/TARGET_STM32F1/spi_api.c | 20 ++++++++----------- .../hal/TARGET_STM/TARGET_STM32F3/spi_api.c | 20 ++++++++----------- .../hal/TARGET_STM/TARGET_STM32F3XX/spi_api.c | 20 ++++++++----------- .../hal/TARGET_STM/TARGET_STM32F4/spi_api.c | 20 ++++++++----------- .../hal/TARGET_STM/TARGET_STM32F4XX/spi_api.c | 17 +++++----------- .../hal/TARGET_STM/TARGET_STM32L0/spi_api.c | 20 ++++++++----------- .../hal/TARGET_STM/TARGET_STM32L1/spi_api.c | 20 ++++++++----------- 31 files changed, 76 insertions(+), 296 deletions(-) diff --git a/libraries/mbed/api/SPI.h b/libraries/mbed/api/SPI.h index 7fa1a6be8e..f6ec5345db 100644 --- a/libraries/mbed/api/SPI.h +++ b/libraries/mbed/api/SPI.h @@ -37,10 +37,21 @@ namespace mbed { * * #include "mbed.h" * + * // hardware ssel (where applicable) + * //SPI device(p5, p6, p7, p8); // mosi, miso, sclk, ssel + * + * // software ssel * SPI device(p5, p6, p7); // mosi, miso, sclk + * DigitalOut cs(p8); // ssel * * int main() { + * // hardware ssel (where applicable) + * //int response = device.write(0xFF); + * + * // software ssel + * cs = 0; * int response = device.write(0xFF); + * cs = 1; * } * @endcode */ @@ -49,17 +60,15 @@ class SPI { public: /** Create a SPI master connected to the specified pins - * - * Pin Options: - * (5, 6, 7) or (11, 12, 13) * * mosi or miso can be specfied as NC if not used * * @param mosi SPI Master Out, Slave In pin * @param miso SPI Master In, Slave Out pin * @param sclk SPI Clock pin + * @param ssel SPI chip select pin */ - SPI(PinName mosi, PinName miso, PinName sclk, PinName _unused=NC); + SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel=NC); /** Configure the data transmission format * diff --git a/libraries/mbed/api/SPISlave.h b/libraries/mbed/api/SPISlave.h index d06c7e1b44..1875ff69bb 100644 --- a/libraries/mbed/api/SPISlave.h +++ b/libraries/mbed/api/SPISlave.h @@ -53,9 +53,6 @@ class SPISlave { public: /** Create a SPI slave connected to the specified pins - * - * Pin Options: - * (5, 6, 7i, 8) or (11, 12, 13, 14) * * mosi or miso can be specfied as NC if not used * @@ -63,7 +60,6 @@ public: * @param miso SPI Master In, Slave Out pin * @param sclk SPI Clock pin * @param ssel SPI chip select pin - * @param name (optional) A string to identify the object */ SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel); diff --git a/libraries/mbed/common/SPI.cpp b/libraries/mbed/common/SPI.cpp index 4bca2b69ce..c69006ca1c 100644 --- a/libraries/mbed/common/SPI.cpp +++ b/libraries/mbed/common/SPI.cpp @@ -19,12 +19,12 @@ namespace mbed { -SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName _unused) : +SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) : _spi(), _bits(8), _mode(0), _hz(1000000) { - spi_init(&_spi, mosi, miso, sclk, NC); + spi_init(&_spi, mosi, miso, sclk, ssel); spi_format(&_spi, _bits, _mode, 0); spi_frequency(&_spi, _hz); } diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/spi_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/spi_api.c index 5f1313b131..1b13ec19ff 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/spi_api.c @@ -41,14 +41,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel obj->spi->MCR &= ~(SPI_MCR_MDIS_MASK | SPI_MCR_HALT_MASK); //obj->spi->MCR |= SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK; - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - // not halt in the debug mode obj->spi->SR |= SPI_SR_EOQF_MASK; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/spi_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/spi_api.c index 5f948a5d91..599d903a5f 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/spi_api.c @@ -60,14 +60,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel break; } - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - // enable SPI obj->spi->C1 |= SPI_C1_SPE_MASK; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/spi_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/spi_api.c index e9f13ecbf1..28e926bc8b 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/spi_api.c @@ -40,14 +40,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel case SPI_1: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 23; break; } - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - // enable SPI obj->spi->C1 |= SPI_C1_SPE_MASK; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/spi_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/spi_api.c index f58fc17703..128ea7f37a 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/spi_api.c @@ -81,14 +81,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel case SPI_1: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 23; break; } - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - // enable SPI obj->spi->C1 |= SPI_C1_SPE_MASK; obj->spi->C2 &= ~SPI_C2_SPIMODE_MASK; //8bit diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/spi_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/spi_api.c index f4b699e8d7..86c88d9ddd 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/spi_api.c @@ -98,14 +98,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel case SPI_1: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 23; break; } - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - // enable SPI obj->spi->C1 |= SPI_C1_SPE_MASK; obj->spi->C2 &= ~SPI_C2_SPIMODE_MASK; //8bit diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/spi_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/spi_api.c index 0826cd43db..24a9d633cd 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/spi_api.c @@ -43,14 +43,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel uint32_t spi_address[] = SPI_BASE_ADDRS; DSPI_HAL_Init(spi_address[obj->instance]); DSPI_HAL_Disable(spi_address[obj->instance]); - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } DSPI_HAL_SetDelay(spi_address[obj->instance], kDspiCtar0, 0, 0, kDspiPcsToSck); - spi_frequency(obj, 1000000); DSPI_HAL_Enable(spi_address[obj->instance]); DSPI_HAL_StartTransfer(spi_address[obj->instance]); diff --git a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/spi_api.c b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/spi_api.c index 85e39db333..21cf45875b 100644 --- a/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/spi_api.c @@ -88,10 +88,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel obj->spi->gen_ctrl = (MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN | MXC_F_SPI_GEN_CTRL_TX_FIFO_EN | MXC_F_SPI_GEN_CTRL_RX_FIFO_EN ); - - // Give instance the default settings - spi_format(obj, DEFAULT_CHAR, DEFAULT_MODE, 0); - spi_frequency(obj, DEFAULT_FREQ); } //****************************************************************************** diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/spi_api.c index d152794f8d..15e869a547 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/spi_api.c @@ -85,17 +85,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel break; } - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - - // enable the ssp channel - ssp_enable(obj); - // pin out the spi pins pinmap_pinout(mosi, PinMap_SPI_MOSI); pinmap_pinout(miso, PinMap_SPI_MISO); diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/spi_api.c index 594f1f086b..8c1a8efd12 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/spi_api.c @@ -50,17 +50,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel break; } - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - - // enable the ssp channel - ssp_enable(obj); - // pin out the spi pins pinmap_pinout(mosi, PinMap_SPI_MOSI); pinmap_pinout(miso, PinMap_SPI_MISO); diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/spi_api.c index 314ed1b922..879bfc6d87 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/spi_api.c @@ -87,17 +87,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel break; } - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - - // enable the ssp channel - ssp_enable(obj); - // pin out the spi pins pinmap_pinout(mosi, PinMap_SPI_MOSI); pinmap_pinout(miso, PinMap_SPI_MISO); diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC13XX/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC13XX/spi_api.c index 4581b07706..971e508b7f 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC13XX/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC13XX/spi_api.c @@ -79,17 +79,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel break; } - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - - // enable the ssp channel - ssp_enable(obj); - // pin out the spi pins pinmap_pinout(mosi, PinMap_SPI_MOSI); pinmap_pinout(miso, PinMap_SPI_MISO); diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/spi_api.c index 79d1d2aeef..d7b3ecc8aa 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/spi_api.c @@ -158,17 +158,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel LPC_SYSCON->SYSAHBCLKCTRL1 |= (0x1 << (obj->spi_n + 9)); LPC_SYSCON->PRESETCTRL1 |= (0x1 << (obj->spi_n + 9)); LPC_SYSCON->PRESETCTRL1 &= ~(0x1 << (obj->spi_n + 9)); - - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - - // enable the spi channel - spi_enable(obj); } void spi_free(spi_t *obj) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/spi_api.c index aee389df5e..8ffbb86fef 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/spi_api.c @@ -72,17 +72,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel case SPI_0: LPC_SC->PCONP |= 1 << 21; break; case SPI_1: LPC_SC->PCONP |= 1 << 10; break; } - - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - - // enable the ssp channel - ssp_enable(obj); // pin out the spi pins pinmap_pinout(mosi, PinMap_SPI_MOSI); diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC23XX/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC23XX/spi_api.c index b658769889..7768e11046 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC23XX/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC23XX/spi_api.c @@ -73,17 +73,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel case SPI_1: LPC_SC->PCONP |= 1 << 10; break; } - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - - // enable the ssp channel - ssp_enable(obj); - // pin out the spi pins pinmap_pinout(mosi, PinMap_SPI_MOSI); pinmap_pinout(miso, PinMap_SPI_MISO); diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c index c88e8edd4f..ae9838c59b 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c @@ -93,17 +93,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel case SPI_2: LPC_SC->PCONP |= 1 << 20; break; } - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - - // enable the ssp channel - ssp_enable(obj); - // pin out the spi pins pinmap_pinout(mosi, PinMap_SPI_MOSI); pinmap_pinout(miso, PinMap_SPI_MISO); diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/spi_api.c index 203404d0a4..ad4bdcd611 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/spi_api.c @@ -73,17 +73,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel case SPI_2: LPC_SC->PCONP |= 1 << 20; break; } - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - - // enable the ssp channel - ssp_enable(obj); - // pin out the spi pins pinmap_pinout(mosi, PinMap_SPI_MOSI); pinmap_pinout(miso, PinMap_SPI_MISO); diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC43XX/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC43XX/spi_api.c index 90be127a0f..74e7c8d70e 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC43XX/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC43XX/spi_api.c @@ -91,17 +91,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel case SPI_0: LPC_CGU->BASE_CLK[CLK_BASE_SSP0] = (1 << 11) | (CLKIN_MAINPLL << 24); break; case SPI_1: LPC_CGU->BASE_CLK[CLK_BASE_SSP1] = (1 << 11) | (CLKIN_MAINPLL << 24); break; } - - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - - // enable the ssp channel - ssp_enable(obj); // pin out the spi pins pinmap_pinout(mosi, PinMap_SPI_MOSI); diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/spi_api.c index 21a6432c0e..50ee0bc122 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/spi_api.c @@ -100,17 +100,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel LPC_SYSCON->PRESETCTRL |= (0x1<<1); break; } - - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - - // enable the ssp channel - ssp_enable(obj); } void spi_free(spi_t *obj) {} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/spi_api.c index 9b9b29103d..28da481e35 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/spi_api.c @@ -103,17 +103,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel LPC_SYSCON->PRESETCTRL &= ~(1 << obj->spi_n); LPC_SYSCON->PRESETCTRL |= (1 << obj->spi_n); - // set default format and frequency - if (ssel == (PinName)NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); obj->spi->DLY = 2; // 2 SPI clock times pre-delay - - // enable the ssp channel - spi_enable(obj); } void spi_free(spi_t *obj) diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c index 6758ebe976..b1e6727266 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c @@ -96,14 +96,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel obj->spi->SPBFCR = 0xf0; // and set trigger count: read 1, write 1 obj->spi->SPBFCR = 0x30; // and reset buffer - // set default format and frequency - if ((int)ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - // pin out the spi pins pinmap_pinout(mosi, PinMap_SPI_MOSI); pinmap_pinout(miso, PinMap_SPI_MISO); diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/spi_api.c index e979892e77..66117600b4 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/spi_api.c @@ -100,13 +100,11 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel obj->pin_sclk = sclk; obj->pin_ssel = ssel; - if (ssel == NC) { // SW NSS Master mode - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { // Slave + if (ssel != NC) { pinmap_pinout(ssel, PinMap_SPI_SSEL); - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; + } + else { + obj->nss = SPI_NSS_SOFT; } init_spi(obj); @@ -162,14 +160,12 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) break; } - if (slave == 0) { - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; + if (obj->nss != SPI_NSS_SOFT) { + obj->nss = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT; } + obj->mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER; + init_spi(obj); } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/spi_api.c index 73e920e1b6..73da9f9a40 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/spi_api.c @@ -100,13 +100,11 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel obj->pin_sclk = sclk; obj->pin_ssel = ssel; - if (ssel == NC) { // SW NSS Master mode - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { // Slave + if (ssel != NC) { pinmap_pinout(ssel, PinMap_SPI_SSEL); - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; + } + else { + obj->nss = SPI_NSS_SOFT; } init_spi(obj); @@ -162,14 +160,12 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) break; } - if (slave == 0) { - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; + if (obj->nss != SPI_NSS_SOFT) { + obj->nss = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT; } + obj->mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER; + init_spi(obj); } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c index af0e058e35..b2725fb937 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c @@ -115,13 +115,11 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel obj->pin_sclk = sclk; obj->pin_ssel = ssel; - if (ssel == NC) { // SW NSS Master mode - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { // Slave + if (ssel != NC) { pinmap_pinout(ssel, PinMap_SPI_SSEL); - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; + } + else { + obj->nss = SPI_NSS_SOFT; } init_spi(obj); @@ -189,14 +187,12 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) break; } - if (slave == 0) { - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; + if (obj->nss != SPI_NSS_SOFT) { + obj->nss = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT; } + obj->mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER; + init_spi(obj); } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/spi_api.c index 5bae376b15..0812487363 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/spi_api.c @@ -123,13 +123,11 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel obj->cpha = SPI_CPHA_1Edge; obj->br_presc = SPI_BaudRatePrescaler_256; - if (ssel == NC) { // Master - obj->mode = SPI_Mode_Master; - obj->nss = SPI_NSS_Soft; - } else { // Slave + if (ssel != NC) { pinmap_pinout(ssel, PinMap_SPI_SSEL); - obj->mode = SPI_Mode_Slave; - obj->nss = SPI_NSS_Soft; + } + else { + obj->nss = SPI_NSS_SOFT; } init_spi(obj); @@ -167,14 +165,12 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) { break; } - if (slave == 0) { - obj->mode = SPI_Mode_Master; - obj->nss = SPI_NSS_Soft; - } else { - obj->mode = SPI_Mode_Slave; - obj->nss = SPI_NSS_Hard; + if (obj->nss != SPI_NSS_SOFT) { + obj->nss = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT; } + obj->mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER; + init_spi(obj); } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/spi_api.c index 828e41426c..aa50219ce9 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/spi_api.c @@ -117,13 +117,11 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel obj->pin_sclk = sclk; obj->pin_ssel = ssel; - if (ssel == NC) { // SW NSS Master mode - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { // Slave + if (ssel != NC) { pinmap_pinout(ssel, PinMap_SPI_SSEL); - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; + } + else { + obj->nss = SPI_NSS_SOFT; } init_spi(obj); @@ -201,14 +199,12 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) break; } - if (slave == 0) { - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; + if (obj->nss != SPI_NSS_SOFT) { + obj->nss = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT; } + obj->mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER; + init_spi(obj); } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/spi_api.c index ae6bbc52fc..c01edad935 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/spi_api.c @@ -92,18 +92,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel RCC->APB1ENR |= RCC_APB1ENR_SPI3EN; break; } - - - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - - // enable the ssp channel - ssp_enable(obj); // pin out the spi pins pinmap_pinout(mosi, PinMap_SPI_MOSI); @@ -133,6 +121,11 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) { ((slave) ? 0: 1) << 2 | ((bits == 16) ? 1 : 0) << 11; + if (slave) { + // Use software slave management + obj->spi->CR1 |= SPI_CR1_SSM | SPI_CR1_SSI; + } + if (obj->spi->SR & SPI_SR_MODF) { obj->spi->CR1 = obj->spi->CR1; } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/spi_api.c index 3bca3770cb..b6639ba291 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/spi_api.c @@ -100,13 +100,11 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel obj->pin_sclk = sclk; obj->pin_ssel = ssel; - if (ssel == NC) { // SW NSS Master mode - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { // Slave + if (ssel != NC) { pinmap_pinout(ssel, PinMap_SPI_SSEL); - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; + } + else { + obj->nss = SPI_NSS_SOFT; } init_spi(obj); @@ -162,14 +160,12 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) break; } - if (slave == 0) { - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; + if (obj->nss != SPI_NSS_SOFT) { + obj->nss = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT; } + obj->mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER; + init_spi(obj); } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/spi_api.c index 45aafba51c..8c8b65ae7e 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/spi_api.c @@ -103,13 +103,11 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel obj->pin_sclk = sclk; obj->pin_ssel = ssel; - if (ssel == NC) { // SW NSS Master mode - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { // Slave + if (ssel != NC) { pinmap_pinout(ssel, PinMap_SPI_SSEL); - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; + } + else { + obj->nss = SPI_NSS_SOFT; } init_spi(obj); @@ -171,14 +169,12 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) break; } - if (slave == 0) { - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; + if (obj->nss != SPI_NSS_SOFT) { + obj->nss = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT; } + obj->mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER; + init_spi(obj); } From c74b9d61261236d830a8e642915a444f910ade6c Mon Sep 17 00:00:00 2001 From: sg- Date: Fri, 10 Apr 2015 15:19:42 -0500 Subject: [PATCH 005/139] Update if/else formatting to K&R --- .../mbed/targets/hal/TARGET_STM/TARGET_STM32F0/spi_api.c | 5 ++--- .../mbed/targets/hal/TARGET_STM/TARGET_STM32F1/spi_api.c | 5 ++--- .../mbed/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c | 5 ++--- .../mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/spi_api.c | 5 ++--- .../mbed/targets/hal/TARGET_STM/TARGET_STM32F4/spi_api.c | 5 ++--- .../mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/spi_api.c | 3 +-- .../mbed/targets/hal/TARGET_STM/TARGET_STM32L0/spi_api.c | 5 ++--- .../mbed/targets/hal/TARGET_STM/TARGET_STM32L1/spi_api.c | 5 ++--- 8 files changed, 15 insertions(+), 23 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/spi_api.c index 66117600b4..3aa5eb402d 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/spi_api.c @@ -102,9 +102,8 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel if (ssel != NC) { pinmap_pinout(ssel, PinMap_SPI_SSEL); - } - else { - obj->nss = SPI_NSS_SOFT; + } else { + obj->nss = SPI_NSS_SOFT; } init_spi(obj); diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/spi_api.c index 73da9f9a40..90aa5cced2 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F1/spi_api.c @@ -102,9 +102,8 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel if (ssel != NC) { pinmap_pinout(ssel, PinMap_SPI_SSEL); - } - else { - obj->nss = SPI_NSS_SOFT; + } else { + obj->nss = SPI_NSS_SOFT; } init_spi(obj); diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c index b2725fb937..c215b501af 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c @@ -117,9 +117,8 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel if (ssel != NC) { pinmap_pinout(ssel, PinMap_SPI_SSEL); - } - else { - obj->nss = SPI_NSS_SOFT; + } else { + obj->nss = SPI_NSS_SOFT; } init_spi(obj); diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/spi_api.c index 0812487363..1eedb88dac 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/spi_api.c @@ -125,9 +125,8 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel if (ssel != NC) { pinmap_pinout(ssel, PinMap_SPI_SSEL); - } - else { - obj->nss = SPI_NSS_SOFT; + } else { + obj->nss = SPI_NSS_SOFT; } init_spi(obj); diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/spi_api.c index aa50219ce9..260162d5a8 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/spi_api.c @@ -119,9 +119,8 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel if (ssel != NC) { pinmap_pinout(ssel, PinMap_SPI_SSEL); - } - else { - obj->nss = SPI_NSS_SOFT; + } else { + obj->nss = SPI_NSS_SOFT; } init_spi(obj); diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/spi_api.c index c01edad935..b88b3af709 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/spi_api.c @@ -99,8 +99,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel pinmap_pinout(sclk, PinMap_SPI_SCLK); if (ssel != NC) { pinmap_pinout(ssel, PinMap_SPI_SSEL); - } - else { + } else { // Use software slave management obj->spi->CR1 |= SPI_CR1_SSM | SPI_CR1_SSI; } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/spi_api.c index b6639ba291..baa4e6e2bf 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/spi_api.c @@ -102,9 +102,8 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel if (ssel != NC) { pinmap_pinout(ssel, PinMap_SPI_SSEL); - } - else { - obj->nss = SPI_NSS_SOFT; + } else { + obj->nss = SPI_NSS_SOFT; } init_spi(obj); diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/spi_api.c index 8c8b65ae7e..a0429ac21d 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/spi_api.c @@ -105,9 +105,8 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel if (ssel != NC) { pinmap_pinout(ssel, PinMap_SPI_SSEL); - } - else { - obj->nss = SPI_NSS_SOFT; + } else { + obj->nss = SPI_NSS_SOFT; } init_spi(obj); From ac5a462946a4fb07b07f10b8732b62aa55b08520 Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Thu, 23 Apr 2015 18:57:41 +0400 Subject: [PATCH 006/139] bug fix of SVC handler --- .../TARGET_ARM7/ARM7/TOOLCHAIN_ARM/HAL_CM0.c | 301 ----------------- .../ARM7/TOOLCHAIN_ARM/SVC_Table.s | 57 ---- .../TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s | 21 +- .../TARGET_ARM7/ARM7/TOOLCHAIN_IAR/HAL_CM0.s | 312 ------------------ .../ARM7/TOOLCHAIN_IAR/SVC_Table.s | 58 ---- libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h | 2 +- libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h | 7 +- 7 files changed, 9 insertions(+), 749 deletions(-) delete mode 100644 libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_ARM/HAL_CM0.c delete mode 100644 libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_ARM/SVC_Table.s delete mode 100644 libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_IAR/HAL_CM0.s delete mode 100644 libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_IAR/SVC_Table.s diff --git a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_ARM/HAL_CM0.c b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_ARM/HAL_CM0.c deleted file mode 100644 index 492e94a197..0000000000 --- a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_ARM/HAL_CM0.c +++ /dev/null @@ -1,301 +0,0 @@ -/*---------------------------------------------------------------------------- - * RL-ARM - RTX - *---------------------------------------------------------------------------- - * Name: HAL_CM0.C - * Purpose: Hardware Abstraction Layer for Cortex-M0 - * Rev.: V4.60 - *---------------------------------------------------------------------------- - * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH - * All rights reserved. - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - *---------------------------------------------------------------------------*/ - -#include "rt_TypeDef.h" -#include "RTX_Conf.h" -#include "rt_System.h" -#include "rt_HAL_CM.h" -#include "rt_Task.h" -#include "rt_MemBox.h" - - -/*---------------------------------------------------------------------------- - * Functions - *---------------------------------------------------------------------------*/ - - -/*--------------------------- rt_set_PSP ------------------------------------*/ - -__asm void rt_set_PSP (U32 stack) { - MSR PSP,R0 - BX LR -} - - -/*--------------------------- rt_get_PSP ------------------------------------*/ - -__asm U32 rt_get_PSP (void) { - MRS R0,PSP - BX LR -} - - -/*--------------------------- os_set_env ------------------------------------*/ - -__asm void os_set_env (void) { - /* Switch to Unprivileged/Privileged Thread mode, use PSP. */ - MOV R0,SP ; PSP = MSP - MSR PSP,R0 - LDR R0,=__cpp(&os_flags) - LDRB R0,[R0] - LSLS R0,#31 - BNE PrivilegedE - MOVS R0,#0x03 ; Unprivileged Thread mode, use PSP - MSR CONTROL,R0 - BX LR -PrivilegedE - MOVS R0,#0x02 ; Privileged Thread mode, use PSP - MSR CONTROL,R0 - BX LR - - ALIGN -} - - -/*--------------------------- _alloc_box ------------------------------------*/ - -__asm void *_alloc_box (void *box_mem) { - /* Function wrapper for Unprivileged/Privileged mode. */ - LDR R3,=__cpp(rt_alloc_box) - MOV R12,R3 - MRS R3,IPSR - LSLS R3,#24 - BNE PrivilegedA - MRS R3,CONTROL - LSLS R3,#31 - BEQ PrivilegedA - SVC 0 - BX LR -PrivilegedA - BX R12 - - ALIGN -} - - -/*--------------------------- _free_box -------------------------------------*/ - -__asm int _free_box (void *box_mem, void *box) { - /* Function wrapper for Unprivileged/Privileged mode. */ - LDR R3,=__cpp(rt_free_box) - MOV R12,R3 - MRS R3,IPSR - LSLS R3,#24 - BNE PrivilegedF - MRS R3,CONTROL - LSLS R3,#31 - BEQ PrivilegedF - SVC 0 - BX LR -PrivilegedF - BX R12 - - ALIGN -} - - -/*-------------------------- SVC_Handler ------------------------------------*/ - -__asm void SVC_Handler (void) { - PRESERVE8 - - IMPORT SVC_Count - IMPORT SVC_Table - IMPORT rt_stk_check - - MRS R0,PSP ; Read PSP - LDR R1,[R0,#24] ; Read Saved PC from Stack - SUBS R1,R1,#2 ; Point to SVC Instruction - LDRB R1,[R1] ; Load SVC Number - CMP R1,#0 - BNE SVC_User ; User SVC Number > 0 - - MOV LR,R4 - LDMIA R0,{R0-R3,R4} ; Read R0-R3,R12 from stack - MOV R12,R4 - MOV R4,LR - BLX R12 ; Call SVC Function - - MRS R3,PSP ; Read PSP - STMIA R3!,{R0-R2} ; Store return values - - LDR R3,=__cpp(&os_tsk) - LDMIA R3!,{R1,R2} ; os_tsk.run, os_tsk.new - CMP R1,R2 - BEQ SVC_Exit ; no task switch - - SUBS R3,#8 - CMP R1,#0 ; Runtask deleted? - BEQ SVC_Next - - MRS R0,PSP ; Read PSP - SUBS R0,R0,#32 ; Adjust Start Address - STR R0,[R1,#TCB_TSTACK] ; Update os_tsk.run->tsk_stack - STMIA R0!,{R4-R7} ; Save old context (R4-R7) - MOV R4,R8 - MOV R5,R9 - MOV R6,R10 - MOV R7,R11 - STMIA R0!,{R4-R7} ; Save old context (R8-R11) - - PUSH {R2,R3} - BL rt_stk_check ; Check for Stack overflow - POP {R2,R3} - -SVC_Next - STR R2,[R3] ; os_tsk.run = os_tsk.new - - LDR R0,[R2,#TCB_TSTACK] ; os_tsk.new->tsk_stack - ADDS R0,R0,#16 ; Adjust Start Address - LDMIA R0!,{R4-R7} ; Restore new Context (R8-R11) - MOV R8,R4 - MOV R9,R5 - MOV R10,R6 - MOV R11,R7 - MSR PSP,R0 ; Write PSP - SUBS R0,R0,#32 ; Adjust Start Address - LDMIA R0!,{R4-R7} ; Restore new Context (R4-R7) - -SVC_Exit - MOVS R0,#:NOT:0xFFFFFFFD ; Set EXC_RETURN value - MVNS R0,R0 - BX R0 ; RETI to Thread Mode, use PSP - - /*------------------- User SVC ------------------------------*/ - -SVC_User - PUSH {R4,LR} ; Save Registers - LDR R2,=SVC_Count - LDR R2,[R2] - CMP R1,R2 - BHI SVC_Done ; Overflow - - LDR R4,=SVC_Table-4 - LSLS R1,R1,#2 - LDR R4,[R4,R1] ; Load SVC Function Address - MOV LR,R4 - - LDMIA R0,{R0-R3,R4} ; Read R0-R3,R12 from stack - MOV R12,R4 - BLX LR ; Call SVC Function - - MRS R4,PSP ; Read PSP - STMIA R4!,{R0-R3} ; Function return values -SVC_Done - POP {R4,PC} ; RETI - - ALIGN -} - - -/*-------------------------- PendSV_Handler ---------------------------------*/ - -__asm void PendSV_Handler (void) { - PRESERVE8 - - BL __cpp(rt_pop_req) - -Sys_Switch - LDR R3,=__cpp(&os_tsk) - LDMIA R3!,{R1,R2} ; os_tsk.run, os_tsk.new - CMP R1,R2 - BEQ Sys_Exit ; no task switch - - SUBS R3,#8 - - MRS R0,PSP ; Read PSP - SUBS R0,R0,#32 ; Adjust Start Address - STR R0,[R1,#TCB_TSTACK] ; Update os_tsk.run->tsk_stack - STMIA R0!,{R4-R7} ; Save old context (R4-R7) - MOV R4,R8 - MOV R5,R9 - MOV R6,R10 - MOV R7,R11 - STMIA R0!,{R4-R7} ; Save old context (R8-R11) - - PUSH {R2,R3} - BL rt_stk_check ; Check for Stack overflow - POP {R2,R3} - - STR R2,[R3] ; os_tsk.run = os_tsk.new - - LDR R0,[R2,#TCB_TSTACK] ; os_tsk.new->tsk_stack - ADDS R0,R0,#16 ; Adjust Start Address - LDMIA R0!,{R4-R7} ; Restore new Context (R8-R11) - MOV R8,R4 - MOV R9,R5 - MOV R10,R6 - MOV R11,R7 - MSR PSP,R0 ; Write PSP - SUBS R0,R0,#32 ; Adjust Start Address - LDMIA R0!,{R4-R7} ; Restore new Context (R4-R7) - -Sys_Exit - MOVS R0,#:NOT:0xFFFFFFFD ; Set EXC_RETURN value - MVNS R0,R0 - BX R0 ; RETI to Thread Mode, use PSP - - ALIGN -} - - -/*-------------------------- SysTick_Handler --------------------------------*/ - -__asm void SysTick_Handler (void) { - PRESERVE8 - - BL __cpp(rt_systick) - B Sys_Switch - - ALIGN -} - - -/*-------------------------- OS_Tick_Handler --------------------------------*/ - -__asm void OS_Tick_Handler (void) { - PRESERVE8 - - BL __cpp(os_tick_irqack) - BL __cpp(rt_systick) - B Sys_Switch - - ALIGN -} - - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ - diff --git a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_ARM/SVC_Table.s b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_ARM/SVC_Table.s deleted file mode 100644 index 817f024883..0000000000 --- a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_ARM/SVC_Table.s +++ /dev/null @@ -1,57 +0,0 @@ -;/*---------------------------------------------------------------------------- -; * RL-ARM - RTX -; *---------------------------------------------------------------------------- -; * Name: SVC_TABLE.S -; * Purpose: Pre-defined SVC Table for Cortex-M -; * Rev.: V4.60 -; *---------------------------------------------------------------------------- -; * -; * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH -; * All rights reserved. -; * Redistribution and use in source and binary forms, with or without -; * modification, are permitted provided that the following conditions are met: -; * - Redistributions of source code must retain the above copyright -; * notice, this list of conditions and the following disclaimer. -; * - Redistributions in binary form must reproduce the above copyright -; * notice, this list of conditions and the following disclaimer in the -; * documentation and/or other materials provided with the distribution. -; * - Neither the name of ARM nor the names of its contributors may be used -; * to endorse or promote products derived from this software without -; * specific prior written permission. -; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; * POSSIBILITY OF SUCH DAMAGE. -; *---------------------------------------------------------------------------*/ - - - AREA SVC_TABLE, CODE, READONLY - - EXPORT SVC_Count - -SVC_Cnt EQU (SVC_End-SVC_Table)/4 -SVC_Count DCD SVC_Cnt - -; Import user SVC functions here. -; IMPORT __SVC_1 - - EXPORT SVC_Table -SVC_Table -; Insert user SVC functions here. SVC 0 used by RTL Kernel. -; DCD __SVC_1 ; user SVC function - -SVC_End - - END - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ diff --git a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s index 91fb1668fb..a7592987eb 100644 --- a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s +++ b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s @@ -229,7 +229,7 @@ SVC_Handler: ISR return code can be used in both cases. */ STMFD SP!, {R0,LR} /* Store registers. */ - ADD LR, LR, #4 + ADD LR, LR, #4 /* Align LR with IRQ handler */ SaveContext MOV R11, LR /* Save Task Stack Pointer */ LDMFD SP!, {R0,LR} /* Restore registers and return. */ @@ -242,17 +242,10 @@ SVC_Handler: BNE SVC_User /* User SVC Number > 0 */ MOV LR, PC /* set LR to return address */ BX R12 /* Call SVC Function */ - STMFD SP!, {R0-R3} /* Store return values */ - LDR R3, =os_tsk - LDMIA R3!, {R1,R2} /* os_tsk.run, os_tsk.new */ - CMP R1,0 - LDMFD SP!, {R0-R3} /* Restore return values */ LDMFD SP!, {R11} /* Load Task Stack Pointer */ - BEQ SVC_Exit /* no need in return values */ + STMIB R11!, {R0-R3} /* Store return values to Task stack */ - ADD R11, 4 /* Offset to R0 in the Task Stack */ - STMDB R11, {R0-R3} /* Save return values in the Task Stack */ SVC_Exit: B RestoreContext /* return to the task */ @@ -275,7 +268,7 @@ SVC_User: LDMFD SP!, {R11} /* Load Task Stack Pointer */ BEQ SVC_Exit /* no need in return values */ - STMDB R11, {R0-R3} /* Save return values in the Task Stack */ + STMIB R11!, {R0-R3} /* Store return values to Task stack */ SVC_Done: B RestoreContext /* return to the task */ @@ -309,12 +302,6 @@ IRQ_Handler: .fnend .size IRQ_Handler, .-IRQ_Handler -/*-------------------------- PendSV_Handler ---------------------------------*/ -PendSV_Handler: - BL rt_pop_req - B RestoreContext - - /*-------------------------- SysTick_Handler --------------------------------*/ # void SysTick_Handler (void); @@ -328,7 +315,7 @@ SysTick_Handler: PUSH {LR} BL rt_systick POP {LR} - BX LR + BX LR /* return to IRQ handler */ /*-------------------------- End --------------------------------*/ .fnend diff --git a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_IAR/HAL_CM0.s b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_IAR/HAL_CM0.s deleted file mode 100644 index 5aa21f38c2..0000000000 --- a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_IAR/HAL_CM0.s +++ /dev/null @@ -1,312 +0,0 @@ -/*---------------------------------------------------------------------------- - * CMSIS-RTOS - RTX - *---------------------------------------------------------------------------- - * Name: HAL_CM0.S - * Purpose: Hardware Abstraction Layer for Cortex-M0 - * Rev.: V4.70 - *---------------------------------------------------------------------------- - * - * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH - * All rights reserved. - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - *---------------------------------------------------------------------------*/ - - NAME HAL_CM0.S - - #define TCB_TSTACK 36 - - EXTERN os_flags - EXTERN os_tsk - EXTERN rt_alloc_box - EXTERN rt_free_box - EXTERN rt_stk_check - EXTERN rt_pop_req - EXTERN rt_systick - EXTERN os_tick_irqack - EXTERN SVC_Table - EXTERN SVC_Count - -/*---------------------------------------------------------------------------- - * Functions - *---------------------------------------------------------------------------*/ - - SECTION .text:CODE:NOROOT(2) - THUMB - -/*--------------------------- rt_set_PSP ------------------------------------*/ - -; void rt_set_PSP (U32 stack); - - PUBLIC rt_set_PSP -rt_set_PSP: - - MSR PSP,R0 - BX LR - - -/*--------------------------- rt_get_PSP ------------------------------------*/ - -; U32 rt_get_PSP (void); - - PUBLIC rt_get_PSP -rt_get_PSP: - - MRS R0,PSP - BX LR - - -/*--------------------------- os_set_env ------------------------------------*/ - -; void os_set_env (void); - /* Switch to Unprivileged/Privileged Thread mode, use PSP. */ - - PUBLIC os_set_env -os_set_env: - - MOV R0,SP /* PSP = MSP */ - MSR PSP,R0 - LDR R0,=os_flags - LDRB R0,[R0] - LSLS R0,#31 - BNE PrivilegedE - MOVS R0,#0x03 /* Unprivileged Thread mode, use PSP */ - MSR CONTROL,R0 - BX LR -PrivilegedE: - MOVS R0,#0x02 /* Privileged Thread mode, use PSP */ - MSR CONTROL,R0 - BX LR - - -/*--------------------------- _alloc_box ------------------------------------*/ - -; void *_alloc_box (void *box_mem); - /* Function wrapper for Unprivileged/Privileged mode. */ - - PUBLIC _alloc_box -_alloc_box: - - LDR R3,=rt_alloc_box - MOV R12,R3 - MRS R3,IPSR - LSLS R3,#24 - BNE PrivilegedA - MRS R3,CONTROL - LSLS R3,#31 - BEQ PrivilegedA - SVC 0 - BX LR -PrivilegedA: - BX R12 - - -/*--------------------------- _free_box -------------------------------------*/ - -; int _free_box (void *box_mem, void *box); - /* Function wrapper for Unprivileged/Privileged mode. */ - - PUBLIC _free_box -_free_box: - - LDR R3,=rt_free_box - MOV R12,R3 - MRS R3,IPSR - LSLS R3,#24 - BNE PrivilegedF - MRS R3,CONTROL - LSLS R3,#31 - BEQ PrivilegedF - SVC 0 - BX LR -PrivilegedF: - BX R12 - - -/*-------------------------- SVC_Handler ------------------------------------*/ - -; void SVC_Handler (void); - - PUBLIC SVC_Handler -SVC_Handler: - - MRS R0,PSP /* Read PSP */ - LDR R1,[R0,#24] /* Read Saved PC from Stack */ - SUBS R1,R1,#2 /* Point to SVC Instruction */ - LDRB R1,[R1] /* Load SVC Number */ - CMP R1,#0 - BNE SVC_User /* User SVC Number > 0 */ - - MOV LR,R4 - LDMIA R0,{R0-R3,R4} /* Read R0-R3,R12 from stack */ - MOV R12,R4 - MOV R4,LR - BLX R12 /* Call SVC Function */ - - MRS R3,PSP /* Read PSP */ - STMIA R3!,{R0-R2} /* Store return values */ - - LDR R3,=os_tsk - LDMIA R3!,{R1,R2} /* os_tsk.run, os_tsk.new */ - CMP R1,R2 - BEQ SVC_Exit /* no task switch */ - - SUBS R3,#8 - CMP R1,#0 /* Runtask deleted? */ - BEQ SVC_Next - - MRS R0,PSP /* Read PSP */ - SUBS R0,R0,#32 /* Adjust Start Address */ - STR R0,[R1,#TCB_TSTACK] /* Update os_tsk.run->tsk_stack */ - STMIA R0!,{R4-R7} /* Save old context (R4-R7) */ - MOV R4,R8 - MOV R5,R9 - MOV R6,R10 - MOV R7,R11 - STMIA R0!,{R4-R7} /* Save old context (R8-R11) */ - - PUSH {R2,R3} - BL rt_stk_check /* Check for Stack overflow */ - POP {R2,R3} - -SVC_Next: - STR R2,[R3] /* os_tsk.run = os_tsk.new */ - - LDR R0,[R2,#TCB_TSTACK] /* os_tsk.new->tsk_stack */ - ADDS R0,R0,#16 /* Adjust Start Address */ - LDMIA R0!,{R4-R7} /* Restore new Context (R8-R11) */ - MOV R8,R4 - MOV R9,R5 - MOV R10,R6 - MOV R11,R7 - MSR PSP,R0 /* Write PSP */ - SUBS R0,R0,#32 /* Adjust Start Address */ - LDMIA R0!,{R4-R7} /* Restore new Context (R4-R7) */ - -SVC_Exit: - MOVS R0,#~0xFFFFFFFD /* Set EXC_RETURN value */ - MVNS R0,R0 - BX R0 /* RETI to Thread Mode, use PSP */ - - /*------------------- User SVC ------------------------------*/ - -SVC_User: - PUSH {R4,LR} /* Save Registers */ - LDR R2,=SVC_Count - LDR R2,[R2] - CMP R1,R2 - BHI SVC_Done /* Overflow */ - - LDR R4,=SVC_Table-4 - LSLS R1,R1,#2 - LDR R4,[R4,R1] /* Load SVC Function Address */ - MOV LR,R4 - - LDMIA R0,{R0-R3,R4} /* Read R0-R3,R12 from stack */ - MOV R12,R4 - BLX LR /* Call SVC Function */ - - MRS R4,PSP /* Read PSP */ - STMIA R4!,{R0-R3} /* Function return values */ -SVC_Done: - POP {R4,PC} /* RETI */ - - -/*-------------------------- PendSV_Handler ---------------------------------*/ - -; void PendSV_Handler (void); - - PUBLIC PendSV_Handler -PendSV_Handler: - - BL rt_pop_req - -Sys_Switch: - LDR R3,=os_tsk - LDMIA R3!,{R1,R2} /* os_tsk.run, os_tsk.new */ - CMP R1,R2 - BEQ Sys_Exit /* no task switch */ - - SUBS R3,#8 - - MRS R0,PSP /* Read PSP */ - SUBS R0,R0,#32 /* Adjust Start Address */ - STR R0,[R1,#TCB_TSTACK] /* Update os_tsk.run->tsk_stack */ - STMIA R0!,{R4-R7} /* Save old context (R4-R7) */ - MOV R4,R8 - MOV R5,R9 - MOV R6,R10 - MOV R7,R11 - STMIA R0!,{R4-R7} /* Save old context (R8-R11) */ - - PUSH {R2,R3} - BL rt_stk_check /* Check for Stack overflow */ - POP {R2,R3} - - STR R2,[R3] /* os_tsk.run = os_tsk.new */ - - LDR R0,[R2,#TCB_TSTACK] /* os_tsk.new->tsk_stack */ - ADDS R0,R0,#16 /* Adjust Start Address */ - LDMIA R0!,{R4-R7} /* Restore new Context (R8-R11) */ - MOV R8,R4 - MOV R9,R5 - MOV R10,R6 - MOV R11,R7 - MSR PSP,R0 /* Write PSP */ - SUBS R0,R0,#32 /* Adjust Start Address */ - LDMIA R0!,{R4-R7} /* Restore new Context (R4-R7) */ - -Sys_Exit: - MOVS R0,#~0xFFFFFFFD /* Set EXC_RETURN value */ - MVNS R0,R0 - BX R0 /* RETI to Thread Mode, use PSP */ - - -/*-------------------------- SysTick_Handler --------------------------------*/ - -; void SysTick_Handler (void); - - PUBLIC SysTick_Handler -SysTick_Handler: - - BL rt_systick - B Sys_Switch - - -/*-------------------------- OS_Tick_Handler --------------------------------*/ - -; void OS_Tick_Handler (void); - - PUBLIC OS_Tick_Handler -OS_Tick_Handler: - - BL os_tick_irqack - BL rt_systick - B Sys_Switch - - - END - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ diff --git a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_IAR/SVC_Table.s b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_IAR/SVC_Table.s deleted file mode 100644 index 269f4605b1..0000000000 --- a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_IAR/SVC_Table.s +++ /dev/null @@ -1,58 +0,0 @@ -;/*---------------------------------------------------------------------------- -; * CMSIS-RTOS - RTX -; *---------------------------------------------------------------------------- -; * Name: SVC_TABLE.S -; * Purpose: Pre-defined SVC Table for Cortex-M -; * Rev.: V4.70 -; *---------------------------------------------------------------------------- -; * -; * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH -; * All rights reserved. -; * Redistribution and use in source and binary forms, with or without -; * modification, are permitted provided that the following conditions are met: -; * - Redistributions of source code must retain the above copyright -; * notice, this list of conditions and the following disclaimer. -; * - Redistributions in binary form must reproduce the above copyright -; * notice, this list of conditions and the following disclaimer in the -; * documentation and/or other materials provided with the distribution. -; * - Neither the name of ARM nor the names of its contributors may be used -; * to endorse or promote products derived from this software without -; * specific prior written permission. -; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; * POSSIBILITY OF SUCH DAMAGE. -; *---------------------------------------------------------------------------*/ - - - NAME SVC_TABLE - SECTION .text:CONST (2) - - PUBLIC SVC_Count - -SVC_Cnt EQU (SVC_End-SVC_Table)/4 -SVC_Count DCD SVC_Cnt - -; Import user SVC functions here. -; IMPORT __SVC_1 - - PUBLIC SVC_Table -SVC_Table -; Insert user SVC functions here. SVC 0 used by RTL Kernel. -; DCD __SVC_1 ; user SVC function - -SVC_End - - END - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ diff --git a/libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h b/libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h index 9f90ace987..ae92bfd548 100644 --- a/libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h +++ b/libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h @@ -337,7 +337,7 @@ int32_t osKernelRunning(void); extern osThreadDef_t os_thread_def_##name #else // define the object #define osThreadDef(name, priority, stacksz) \ -unsigned char os_thread_def_stack_##name [stacksz]; \ +unsigned char os_thread_def_stack_##name [stacksz] __attribute__((aligned (4))); \ osThreadDef_t os_thread_def_##name = \ { (name), (priority), (stacksz), (os_thread_def_stack_##name)} #endif diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h b/libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h index 56dff947fd..25d2973c72 100644 --- a/libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h @@ -34,7 +34,8 @@ #include "cmsis.h" /* Definitions */ -#define INITIAL_xPSR 0x00000010 +//#define INITIAL_xPSR 0x00000010 +#define INITIAL_xPSR 0x10000000 #define DEMCR_TRCENA 0x01000000 #define ITM_ITMENA 0x00000001 #define MAGIC_WORD 0xE25A2EA5 @@ -111,13 +112,13 @@ extern void dbg_task_switch (U32 task_id); #define OS_PEND_IRQ() NVIC_PendIRQ(SYS_TICK_IRQn) #define OS_PENDING NVIC_PendingIRQ(SYS_TICK_IRQn) #define OS_UNPEND(fl) NVIC_UnpendIRQ(SYS_TICK_IRQn) -#define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26 +#define OS_PEND(fl,p) NVIC_PendIRQ(SYS_TICK_IRQn) #define OS_LOCK() NVIC_DisableIRQ(SYS_TICK_IRQn) #define OS_UNLOCK() NVIC_EnableIRQ(SYS_TICK_IRQn) #define OS_X_PENDING NVIC_PendingIRQ(SYS_TICK_IRQn) #define OS_X_UNPEND(fl) NVIC_UnpendIRQ(SYS_TICK_IRQn) -#define OS_X_PEND(fl,p) NVIC_PendIRQ(p) +#define OS_X_PEND(fl,p) NVIC_PendIRQ(SYS_TICK_IRQn) #define OS_X_INIT(n) NVIC_EnableIRQ(n) #define OS_X_LOCK(n) NVIC_DisableIRQ(n) From e14a85321686cf3090465d78d84c53c1771f154b Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Tue, 5 May 2015 17:37:54 +0400 Subject: [PATCH 007/139] CMSIS and RTOS are both compalible separately now, remove ARM and GCC_CR toolchain as not compatible --- .../TOOLCHAIN_GCC_ARM/vector_functions.s | 44 ++++++++++++++----- workspace_tools/targets.py | 2 +- 2 files changed, 34 insertions(+), 12 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_functions.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_functions.s index 3c9a11a125..8afac4c300 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_functions.s +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_functions.s @@ -15,8 +15,8 @@ .weak __mbed_dcc_irq .weak __mbed_reset .global __mbed_init_realmonitor -.extern SVC_Handler -.extern IRQ_Handler +.weak SVC_Handler +.weak IRQ_Handler /* .global __mbed_init */ @@ -31,8 +31,18 @@ __mbed_prefetch_abort: __mbed_data_abort: LDR PC, =0x7fffffc0 __mbed_irq: - B IRQ_Handler -/* MSR CPSR_c, #0x1F|0x80|0x40 +/* + If RTOS is enabled then goto RTOS IRQ handler +*/ + PUSH {R0} + LDR R0, =IRQ_Handler + CMP R0, #0 + POP {R0} + BNE IRQ_Handler +/* + else use CMSIS IRQ handler +*/ + MSR CPSR_c, #0x1F|0x80|0x40 STMDB sp!, {r0-r3,r12,lr} @@ -50,16 +60,26 @@ __mbed_irq: MSR CPSR_c, #0x12|0x80|0x40 SUBS pc, lr, #4 -*/ + __mbed_swi: - B SVC_Handler -/* STMFD sp!, {a4, r4, ip, lr} +/* + If RTOS is enabled then goto RTOS SVC handler +*/ + PUSH {R0} + LDR R0, =SVC_Handler + CMP R0, #0 + POP {R0} + BNE SVC_Handler +/* + else use CMSIS SVC handler +*/ + STMFD sp!, {a4, r4, ip, lr} LDR r4, =0x40000040 LDR a4, =0x00940000 LDR PC, =0x7ffff820 -*/ + __mbed_dcc_irq: LDMFD sp!,{r0-r3,r12,lr} @@ -83,7 +103,7 @@ __mbed_dcc_irq: Reset_Handler: .extern __libc_init_array .extern SystemInit - .extern software_init_hook + .weak software_init_hook LDR R0, =SystemInit MOV LR, PC BX R0 @@ -130,7 +150,8 @@ __mbed_reset: MOV SP, R0 SUB R0, R0, #0x00000040 -/* MSR CPSR_c, #0x10|0x80|0x40 +/* + MSR CPSR_c, #0x10|0x80|0x40 MOV SP, R0 */ MSR CPSR_c, #0x1F|0x80|0x40 @@ -163,7 +184,8 @@ BSSIsEmpty: /* Init realmonitor */ -/* LDR R0, =__mbed_init_realmonitor +/* + LDR R0, =__mbed_init_realmonitor MOV LR, PC BX R0 */ diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 48c1f3ce3b..4b6ea6bd5b 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -222,7 +222,7 @@ class LPC2460(LPCTarget): LPCTarget.__init__(self) self.core = "ARM7TDMI-S" self.extra_labels = ['NXP', 'LPC2460'] - self.supported_toolchains = ["ARM", "GCC_ARM", "GCC_CR"] + self.supported_toolchains = ["GCC_ARM"] class LPC810(LPCTarget): def __init__(self): From c064a71ca72fa90d8e205fd88d57e553f074e171 Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Tue, 5 May 2015 20:42:53 +0400 Subject: [PATCH 008/139] fix SPI bus --- .../mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/spi_api.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/spi_api.c index b658769889..912cfee07e 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/spi_api.c @@ -47,7 +47,7 @@ static const PinMap PinMap_SPI_MISO[] = { static const PinMap PinMap_SPI_SSEL[] = { {P0_6 , SPI_1, 2}, - {P0_11, SPI_1, 2}, + {P0_14, SPI_1, 3}, {P0_16, SPI_0, 2}, {P1_21, SPI_0, 3}, {NC , NC , 0} @@ -69,8 +69,8 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel // enable power and clocking switch ((int)obj->spi) { - case SPI_0: LPC_SC->PCONP |= 1 << 21; break; - case SPI_1: LPC_SC->PCONP |= 1 << 10; break; + case SPI_0: LPC_SC->PCONP |= 1 << PCSSP0; break; + case SPI_1: LPC_SC->PCONP |= 1 << PCSSP1; break; } // set default format and frequency From d41b74e8981a86e9c72df49020be2214a92c1401 Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Tue, 5 May 2015 21:27:39 +0400 Subject: [PATCH 009/139] backport of Issue: Fix stack aligment. #812 --- libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h b/libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h index ae92bfd548..314a5788c1 100644 --- a/libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h +++ b/libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h @@ -243,7 +243,7 @@ typedef struct os_thread_def { os_pthread pthread; ///< start address of thread function osPriority tpriority; ///< initial thread priority uint32_t stacksize; ///< stack size requirements in bytes - unsigned char *stack_pointer; ///< pointer to the stack memory block + uint32_t *stack_pointer; ///< pointer to the stack memory block struct OS_TCB tcb; } osThreadDef_t; @@ -337,7 +337,7 @@ int32_t osKernelRunning(void); extern osThreadDef_t os_thread_def_##name #else // define the object #define osThreadDef(name, priority, stacksz) \ -unsigned char os_thread_def_stack_##name [stacksz] __attribute__((aligned (4))); \ +uint32_t os_thread_def_stack_##name [stacksz / sizeof(uint32_t)]; \ osThreadDef_t os_thread_def_##name = \ { (name), (priority), (stacksz), (os_thread_def_stack_##name)} #endif From 1e76565b028897c2ba008b4697d9b431b31e56c8 Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Thu, 7 May 2015 15:07:23 +0400 Subject: [PATCH 010/139] port PulseWaveModulator --- .../mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/pwmout_api.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/pwmout_api.c index 3773d7e6b7..dc316450c7 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/pwmout_api.c @@ -35,8 +35,12 @@ static const PinMap PinMap_PWM[] = { {P2_3 , PWM_4, 1}, {P2_4 , PWM_5, 1}, {P2_5 , PWM_6, 1}, + {P3_24, PWM_1, 3}, {P3_25, PWM_2, 3}, {P3_26, PWM_3, 3}, + {P3_27, PWM_4, 3}, + {P3_28, PWM_5, 3}, + {P3_29, PWM_6, 3}, {NC, NC, 0} }; From d56b34022d92703cf0ebedc14e092e017b9d1a80 Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Fri, 8 May 2015 19:43:34 +0400 Subject: [PATCH 011/139] code cleanup --- .../cmsis/TARGET_NXP/TARGET_LPC2460/LPC24xx.h | 4 +- .../TARGET_LPC2460/system_LPC24xx.c | 2 +- .../TARGET_LPC2460/PeripheralNames.h | 2 +- .../TARGET_NXP/TARGET_LPC2460/analogin_api.c | 6 +- .../hal/TARGET_NXP/TARGET_LPC2460/can_api.c | 8 +- .../hal/TARGET_NXP/TARGET_LPC2460/i2c_api.c | 12 ++- .../hal/TARGET_NXP/TARGET_LPC2460/rtc_api.c | 2 +- .../hal/TARGET_NXP/TARGET_LPC2460/us_ticker.c | 2 +- .../TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s | 6 +- libraries/rtos/rtx/TARGET_ARM7/HAL_CM.c | 6 +- libraries/rtos/rtx/TARGET_ARM7/RTX_CM_lib.h | 85 +------------------ libraries/rtos/rtx/TARGET_ARM7/RTX_Conf_CM.c | 61 ++----------- libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h | 2 +- libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h | 12 --- 14 files changed, 37 insertions(+), 173 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/LPC24xx.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/LPC24xx.h index 77b247a179..e73f0b17ff 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/LPC24xx.h +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/LPC24xx.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - LPC24xx CMSIS-like structs - * Copyright (C) 2014 Mera NN. All rights reserved. + * Copyright (C) 2009-2015 ARM Limited. All rights reserved. * * An LPC24xx header file, based on LPC23xx.h */ @@ -180,7 +180,7 @@ typedef struct #define PCRTC 9 #define PCSSP1 10 #define PCEMC 11 -#define PCAD 12 +#define PCADC 12 #define PCAN1 13 #define PCAN2 14 #define PCI2C1 19 diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/system_LPC24xx.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/system_LPC24xx.c index ad285b69ba..5fb2fe54bf 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/system_LPC24xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC2460/system_LPC24xx.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (C) 2008-2009 ARM Limited. All rights reserved. + * Copyright (C) 2008-20015 ARM Limited. All rights reserved. * * ARM7 version of CMSIS-like functionality - not advised for use outside mbed! */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PeripheralNames.h index addae6382f..492c225759 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PeripheralNames.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/analogin_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/analogin_api.c index 9a660de266..6293c3f5a4 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/analogin_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -47,7 +47,7 @@ void analogin_init(analogin_t *obj, PinName pin) { MBED_ASSERT(obj->adc != (ADCName)NC); // ensure power is turned on - LPC_SC->PCONP |= (1 << 12); + LPC_SC->PCONP |= (1 << PCADC); // set PCLK of ADC to /1 LPC_SC->PCLKSEL0 &= ~(0x3 << 24); @@ -56,7 +56,7 @@ void analogin_init(analogin_t *obj, PinName pin) { // calculate minimum clock divider // clkdiv = divider - 1 - uint32_t MAX_ADC_CLK = 13000000; + uint32_t MAX_ADC_CLK = 4500000; uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1; // Set the generic software-controlled ADC settings diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/can_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/can_api.c index a3170acc1d..f97e387acc 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/can_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/can_api.c @@ -164,8 +164,8 @@ void can_init(can_t *obj, PinName rd, PinName td) { MBED_ASSERT((int)obj->dev != NC); switch ((int)obj->dev) { - case CAN_1: LPC_SC->PCONP |= 1 << 13; break; - case CAN_2: LPC_SC->PCONP |= 1 << 14; break; + case CAN_1: LPC_SC->PCONP |= 1 << PCAN1; break; + case CAN_2: LPC_SC->PCONP |= 1 << PCAN2; break; } pinmap_pinout(rd, PinMap_CAN_RD); @@ -180,8 +180,8 @@ void can_init(can_t *obj, PinName rd, PinName td) { void can_free(can_t *obj) { switch ((int)obj->dev) { - case CAN_1: LPC_SC->PCONP &= ~(1 << 13); break; - case CAN_2: LPC_SC->PCONP &= ~(1 << 14); break; + case CAN_1: LPC_SC->PCONP &= ~(1 << PCAN1); break; + case CAN_2: LPC_SC->PCONP &= ~(1 << PCAN2); break; } } diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/i2c_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/i2c_api.c index f4bceb4969..57a29d64ae 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/i2c_api.c @@ -22,6 +22,9 @@ static const PinMap PinMap_I2C_SDA[] = { {P0_10, I2C_2, 2}, {P0_19, I2C_1, 3}, {P0_27, I2C_0, 1}, + {P2_14, I2C_1, 3}, + {P2_30, I2C_2, 3}, + {P4_20, I2C_2, 2}, {NC , NC , 0} }; @@ -30,6 +33,9 @@ static const PinMap PinMap_I2C_SCL[] = { {P0_11, I2C_2, 2}, {P0_20, I2C_1, 3}, {P0_28, I2C_0, 1}, + {P2_15, I2C_1, 3}, + {P2_31, I2C_2, 3}, + {P4_21, I2C_2, 2}, {NC , NC, 0} }; @@ -84,9 +90,9 @@ static inline void i2c_interface_enable(i2c_t *obj) { static inline void i2c_power_enable(i2c_t *obj) { switch ((int)obj->i2c) { - case I2C_0: LPC_SC->PCONP |= 1 << 7; break; - case I2C_1: LPC_SC->PCONP |= 1 << 19; break; - case I2C_2: LPC_SC->PCONP |= 1 << 26; break; + case I2C_0: LPC_SC->PCONP |= 1 << PCI2C0; break; + case I2C_1: LPC_SC->PCONP |= 1 << PCI2C1; break; + case I2C_2: LPC_SC->PCONP |= 1 << PCI2C2; break; } } diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/rtc_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/rtc_api.c index a4e7b96a61..ef51fef7c1 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/rtc_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/rtc_api.c @@ -34,7 +34,7 @@ * without impacting if it is the case */ void rtc_init(void) { - LPC_SC->PCONP |= 0x200; // Ensure power is on + LPC_SC->PCONP |= (1 << PCRTC); // Ensure power is on LPC_RTC->CCR = 0x00; // clock source on 2368 is special test mode on 1768! diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/us_ticker.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/us_ticker.c index b46d75e6bc..505a16d6b8 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/us_ticker.c @@ -26,7 +26,7 @@ void us_ticker_init(void) { if (us_ticker_inited) return; us_ticker_inited = 1; - LPC_SC->PCONP |= 1 << 23; // Clock TIMER_3 + LPC_SC->PCONP |= 1 << PCTIM3; // Clock TIMER_3 US_TICKER_TIMER->CTCR = 0x0; // timer mode uint32_t PCLK = SystemCoreClock / 4; diff --git a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s index a7592987eb..ed8f90987b 100644 --- a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s +++ b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s @@ -80,8 +80,8 @@ /* Store the new top of stack for the task. */ LDR R0,=os_tsk - LDR R0, [R0] /* R0 = (tcb) os_tsk.run */ - STR LR, [R0, 36] /* tcb.tsk_stack = SP(user) */ + LDR R0, [R0] /* R0 = (tcb) os_tsk.run */ + STR LR, [R0, TCB_TSTACK] /* tcb.tsk_stack = SP(user) */ .endm /*-------------------------- Restore Context --------------------------------*/ @@ -94,7 +94,7 @@ RestoreContext: LDR R0,=os_tsk LDR R1, [R0, 4] /* R1 = (tcb) os_tsk.new */ STR R1, [R0] /* os_tsk.run = os_tsk_newk */ - LDR LR, [R1, 36] /* LR = tcb.tsk_stack */ + LDR LR, [R1, TCB_TSTACK] /* LR = tcb.tsk_stack */ /* Get the SPSR from the stack. */ LDMFD LR!, {R0} /* SPSR */ diff --git a/libraries/rtos/rtx/TARGET_ARM7/HAL_CM.c b/libraries/rtos/rtx/TARGET_ARM7/HAL_CM.c index 249d95deaf..071fd73d83 100644 --- a/libraries/rtos/rtx/TARGET_ARM7/HAL_CM.c +++ b/libraries/rtos/rtx/TARGET_ARM7/HAL_CM.c @@ -2,11 +2,11 @@ * RL-ARM - RTX *---------------------------------------------------------------------------- * Name: HAL_CM.C - * Purpose: Hardware Abstraction Layer for Cortex-M - * Rev.: V4.60 + * Purpose: Hardware Abstraction Layer for ARM7TDMI + * Rev.: V1.0 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_ARM7/RTX_CM_lib.h b/libraries/rtos/rtx/TARGET_ARM7/RTX_CM_lib.h index bf31afe66f..ff177b991b 100755 --- a/libraries/rtos/rtx/TARGET_ARM7/RTX_CM_lib.h +++ b/libraries/rtos/rtx/TARGET_ARM7/RTX_CM_lib.h @@ -199,91 +199,8 @@ extern int main (void); osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL}; // This define should be probably moved to the CMSIS layer -#if defined(TARGET_LPC1768) -#define INITIAL_SP (0x10008000UL) -#elif defined(TARGET_LPC11U24) -#define INITIAL_SP (0x10002000UL) - -#elif defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) -#define INITIAL_SP (0x10002000UL) - -#elif defined(TARGET_LPC1114) -#define INITIAL_SP (0x10001000UL) - -#elif defined(TARGET_LPC812) -#define INITIAL_SP (0x10001000UL) - -#elif defined(TARGET_LPC824) -#define INITIAL_SP (0x10002000UL) - -#elif defined(TARGET_KL25Z) -#define INITIAL_SP (0x20003000UL) - -#elif defined(TARGET_K64F) -#define INITIAL_SP (0x20030000UL) - -#elif defined(TARGET_K22F) -#define INITIAL_SP (0x20010000UL) - -#elif defined(TARGET_KL46Z) -#define INITIAL_SP (0x20006000UL) - -#elif defined(TARGET_KL43Z) -#define INITIAL_SP (0x20006000UL) - -#elif defined(TARGET_KL05Z) -#define INITIAL_SP (0x20000C00UL) - -#elif defined(TARGET_LPC4088) -#define INITIAL_SP (0x10010000UL) - -#elif defined(TARGET_LPC4337) -#define INITIAL_SP (0x10008000UL) - -#elif defined(TARGET_LPC1347) -#define INITIAL_SP (0x10002000UL) - -#elif defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) -#define INITIAL_SP (0x20002000UL) - -#elif defined(TARGET_DISCO_F303VC) -#define INITIAL_SP (0x2000A000UL) - -#elif defined(TARGET_STM32F407) || defined(TARGET_F407VG) -#define INITIAL_SP (0x20020000UL) - -#elif defined(TARGET_STM32F401RE) -#define INITIAL_SP (0x20018000UL) - -#elif defined(TARGET_LPC1549) -#define INITIAL_SP (0x02009000UL) - -#elif defined(TARGET_LPC11U68) -#define INITIAL_SP (0x10004000UL) - -#elif defined(TARGET_NRF51822) -#define INITIAL_SP (0x20004000UL) - -#elif defined(TARGET_STM32F411RE) -#define INITIAL_SP (0x20020000UL) - -#elif defined(TARGET_STM32F103RB) -#define INITIAL_SP (0x20005000UL) - -#elif defined(TARGET_STM32F302R8) -#define INITIAL_SP (0x20004000UL) - -#elif defined(TARGET_STM32F334R8) -#define INITIAL_SP (0x20003000UL) - -#elif defined(TARGET_STM32F334C8) -#define INITIAL_SP (0x20003000UL) - -#elif defined(TARGET_STM32F405RG) -#define INITIAL_SP (0x20020000UL) - -#elif defined(TARGET_LPC2460) +#if defined(TARGET_LPC2460) extern unsigned char __usr_stack_top__[]; #define INITIAL_SP (__usr_stack_top__) diff --git a/libraries/rtos/rtx/TARGET_ARM7/RTX_Conf_CM.c b/libraries/rtos/rtx/TARGET_ARM7/RTX_Conf_CM.c index 54e91aca96..8293e3a607 100755 --- a/libraries/rtos/rtx/TARGET_ARM7/RTX_Conf_CM.c +++ b/libraries/rtos/rtx/TARGET_ARM7/RTX_Conf_CM.c @@ -2,11 +2,11 @@ * RL-ARM - RTX *---------------------------------------------------------------------------- * Name: RTX_Conf_CM.C - * Purpose: Configuration of CMSIS RTX Kernel for Cortex-M - * Rev.: V4.60 + * Purpose: Configuration of CMSIS RTX Kernel for ARM7TDMI + * Rev.: V1.0 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -49,14 +49,8 @@ // counting "main", but not counting "osTimerThread" // Default: 6 #ifndef OS_TASKCNT -# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ - || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) || defined(TARGET_NRF51822) || defined(TARGET_STM32F411RE) \ - || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_LPC2460) +# if defined(TARGET_LPC2368) || defined(TARGET_LPC2460) # define OS_TASKCNT 14 -# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ - || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ - || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) -# define OS_TASKCNT 6 # else # error "no target defined" # endif @@ -64,15 +58,7 @@ // Scheduler (+ interrupts) stack size [bytes] <64-4096:8><#/4> #ifndef OS_SCHEDULERSTKSIZE -# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ - || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) || defined(TARGET_NRF51822) || defined(TARGET_STM32F411RE) \ - || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) -# define OS_SCHEDULERSTKSIZE 256 -# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ - || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ - || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) -# define OS_SCHEDULERSTKSIZE 128 -# elif defined(TARGET_LPC2460) +# if defined(TARGET_LPC2368) || defined(TARGET_LPC2460) # define OS_SCHEDULERSTKSIZE (136*2) # else # error "no target defined" @@ -115,43 +101,10 @@ // Defines the timer clock value. // Default: 6000000 (6MHz) #ifndef OS_CLOCK -# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) +# if defined(TARGET_LPC2368) # define OS_CLOCK 96000000 -# elif defined(TARGET_LPC1347) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) || defined(TARGET_LPC2460) -# define OS_CLOCK 72000000 - -# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F051R8) || defined(TARGET_LPC11U68) -# define OS_CLOCK 48000000 - -# elif defined(TARGET_LPC812) -# define OS_CLOCK 36000000 - -# elif defined(TARGET_LPC824) -# define OS_CLOCK 30000000 - -# elif defined(TARGET_STM32F100RB) -# define OS_CLOCK 24000000 - -# elif defined(TARGET_LPC4088) || defined(TARGET_K64F) || defined(TARGET_K22F) -# define OS_CLOCK 120000000 - -# elif defined(TARGET_LPC4337) -# define OS_CLOCK 204000000 - -# elif defined(TARGET_STM32F407) || defined(TARGET_F407VG) -# define OS_CLOCK 168000000 - -# elif defined(TARGET_NRF51822) -# define OS_CLOCK 16000000 - -# elif defined(TARGET_STM32F401RE) -# define OS_CLOCK 84000000 - -# elif defined(TARGET_STM32F411RE) -# define OS_CLOCK 100000000 - -#elif defined(TARGET_STM32F103RB) +# elif defined(TARGET_LPC2460) # define OS_CLOCK 72000000 # else diff --git a/libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h b/libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h index 314a5788c1..9bfa1535cb 100644 --- a/libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h +++ b/libraries/rtos/rtx/TARGET_ARM7/cmsis_os.h @@ -1,5 +1,5 @@ /* ---------------------------------------------------------------------- - * Copyright (C) 2012 ARM Limited. All rights reserved. + * Copyright (C) 2015 ARM Limited. All rights reserved. * * $Date: 5. June 2012 * $Revision: V1.01 diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h b/libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h index 25d2973c72..e396db7cf0 100644 --- a/libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_HAL_CM.h @@ -34,7 +34,6 @@ #include "cmsis.h" /* Definitions */ -//#define INITIAL_xPSR 0x00000010 #define INITIAL_xPSR 0x10000000 #define DEMCR_TRCENA 0x01000000 #define ITM_ITMENA 0x00000001 @@ -124,17 +123,6 @@ extern void dbg_task_switch (U32 task_id); #define OS_X_LOCK(n) NVIC_DisableIRQ(n) #define OS_X_UNLOCK(n) NVIC_EnableIRQ(n) -/* Core Debug registers */ -//#define DEMCR (*((volatile U32 *)0xE000EDFC)) - -/* ITM registers */ -//#define ITM_CONTROL (*((volatile U32 *)0xE0000E80)) -//#define ITM_ENABLE (*((volatile U32 *)0xE0000E00)) -//#define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078)) -//#define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C)) -//#define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C)) -//#define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C)) - /* Variables */ extern BIT dbg_msg; From f3a03cacc10836559b73c60258f93a58c1a9ca7f Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Fri, 8 May 2015 19:53:07 +0400 Subject: [PATCH 012/139] Backport of Issue: RTX: Support stacks larger than 64k #826 --- .../rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s | 8 ++++---- libraries/rtos/rtx/TARGET_ARM7/os_tcb.h | 5 +++-- libraries/rtos/rtx/TARGET_ARM7/rt_TypeDef.h | 2 +- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s index ed8f90987b..48c0ab0aa5 100644 --- a/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s +++ b/libraries/rtos/rtx/TARGET_ARM7/ARM7/TOOLCHAIN_GCC/HAL_CM0.s @@ -2,11 +2,11 @@ * RL-ARM - RTX *---------------------------------------------------------------------------- * Name: HAL_CM0.S - * Purpose: Hardware Abstraction Layer for Cortex-M0 - * Rev.: V4.60 + * Purpose: Hardware Abstraction Layer for ARM7TDMI + * Rev.: V1.0 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -35,7 +35,7 @@ .file "HAL_CM0.S" .syntax unified - .equ TCB_TSTACK, 36 + .equ TCB_TSTACK, 40 /*---------------------------------------------------------------------------- diff --git a/libraries/rtos/rtx/TARGET_ARM7/os_tcb.h b/libraries/rtos/rtx/TARGET_ARM7/os_tcb.h index 8d9ceb8575..7a8c5c379e 100644 --- a/libraries/rtos/rtx/TARGET_ARM7/os_tcb.h +++ b/libraries/rtos/rtx/TARGET_ARM7/os_tcb.h @@ -36,8 +36,9 @@ typedef struct OS_TCB { /* Hardware dependant part: specific for CM processor */ U8 stack_frame; /* Stack frame: 0=Basic, 1=Extended */ - U8 reserved; - U16 priv_stack; /* Private stack size in bytes */ + U8 reserved1; + U16 reserved2; + U32 priv_stack; /* Private stack size in bytes */ U32 tsk_stack; /* Current task Stack pointer (R13) */ U32 *stack; /* Pointer to Task Stack memory block */ diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_TypeDef.h b/libraries/rtos/rtx/TARGET_ARM7/rt_TypeDef.h index 2adbe88cd8..27416c502c 100644 --- a/libraries/rtos/rtx/TARGET_ARM7/rt_TypeDef.h +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_TypeDef.h @@ -41,7 +41,7 @@ typedef void *OS_ID; typedef U32 OS_RESULT; #define TCB_STACKF 32 /* 'stack_frame' offset */ -#define TCB_TSTACK 36 /* 'tsk_stack' offset */ +#define TCB_TSTACK 40 /* 'tsk_stack' offset */ typedef struct OS_PSFE { /* Post Service Fifo Entry */ void *id; /* Object Identification */ From 6d0c61a6ad2eb7d06116b16b371f7d004bb78024 Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Fri, 8 May 2015 19:58:12 +0400 Subject: [PATCH 013/139] Backport of Issue: RTX: Main thread should not write MAGIC_WORD to stack #827 --- libraries/rtos/rtx/TARGET_ARM7/rt_CMSIS.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/libraries/rtos/rtx/TARGET_ARM7/rt_CMSIS.c b/libraries/rtos/rtx/TARGET_ARM7/rt_CMSIS.c index 303b434edb..86250779ad 100644 --- a/libraries/rtos/rtx/TARGET_ARM7/rt_CMSIS.c +++ b/libraries/rtos/rtx/TARGET_ARM7/rt_CMSIS.c @@ -522,18 +522,19 @@ osThreadId svcThreadCreate (osThreadDef_t *thread_def, void *argument) { U8 priority = thread_def->tpriority - osPriorityIdle + 1; P_TCB task_context = &thread_def->tcb; - /* If "size != 0" use a private user provided stack. */ + /* Utilize the user provided stack. */ task_context->stack = (U32*)thread_def->stack_pointer; task_context->priv_stack = thread_def->stacksize; + /* Find a free entry in 'os_active_TCB' table. */ + OS_TID tsk = rt_get_TID (); + os_active_TCB[tsk-1] = task_context; + task_context->task_id = tsk; /* Pass parameter 'argv' to 'rt_init_context' */ task_context->msg = argument; /* For 'size == 0' system allocates the user stack from the memory pool. */ rt_init_context (task_context, priority, (FUNCP)thread_def->pthread); - /* Find a free entry in 'os_active_TCB' table. */ - OS_TID tsk = rt_get_TID (); - os_active_TCB[tsk-1] = task_context; - task_context->task_id = tsk; + /* Dispatch this task to the scheduler for execution. */ DBG_TASK_NOTIFY(task_context, __TRUE); rt_dispatch (task_context); From fa210942845ca223db9dd8027c0ec88a3c84cfca Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Fri, 8 May 2015 20:21:14 +0400 Subject: [PATCH 014/139] backport of Issue: Pinology #808 --- .../mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_api.c | 3 +++ .../mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_object.h | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_api.c index fd9c29b528..2678dfdaa5 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_api.c @@ -29,6 +29,9 @@ void gpio_init(gpio_t *obj, PinName pin) { if (pin == (PinName)NC) return; obj->pin = pin; + if (pin == (PinName)NC) + return; + obj->mask = gpio_set(pin); LPC_GPIO_TypeDef *port_reg = (LPC_GPIO_TypeDef *) ((int)pin & ~0x1F); diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_object.h index f149950b16..291dfb848e 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_object.h @@ -48,6 +48,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif From cba8ef5dab0b5d510ffc904715e74b2b7b78e3c2 Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Fri, 8 May 2015 20:46:42 +0400 Subject: [PATCH 015/139] revert change in workspace_tools/settings.py --- workspace_tools/settings.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/workspace_tools/settings.py b/workspace_tools/settings.py index cd0b83a7ff..3444f86ff0 100644 --- a/workspace_tools/settings.py +++ b/workspace_tools/settings.py @@ -39,7 +39,7 @@ if armcc == "keil": ARM_LIB = join(ARM_PATH, "RV31", "LIB") elif armcc == "standalone": - ARM_PATH = "/" + ARM_PATH = "C:/Program Files/ARM/armcc_4.1_791" ARM_BIN = join(ARM_PATH, "bin") ARM_INC = join(ARM_PATH, "include") ARM_LIB = join(ARM_PATH, "lib") From e673c3cea871bd20b005834d48116fc1575afa03 Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Fri, 8 May 2015 20:54:40 +0400 Subject: [PATCH 016/139] revert changes in workspace_tools/export_test.py --- workspace_tools/export_test.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/workspace_tools/export_test.py b/workspace_tools/export_test.py index 5b918a3f0f..46a70c180b 100755 --- a/workspace_tools/export_test.py +++ b/workspace_tools/export_test.py @@ -27,7 +27,7 @@ from workspace_tools.utils import mkdir, cmd from workspace_tools.export import export, setup_user_prj -USR_PRJ_NAME = "myapp" +USR_PRJ_NAME = "usr_prj" USER_PRJ = join(EXPORT_WORKSPACE, USR_PRJ_NAME) USER_SRC = join(USER_PRJ, "src") @@ -75,7 +75,8 @@ def test_export(toolchain, target, expected_error=None): if __name__ == '__main__': setup_test_user_prj() - exportlist = [ + + for toolchain, target in [ ('zip', 'LPC1768'), ('emblocks', 'LPC1768'), @@ -206,10 +207,9 @@ if __name__ == '__main__': # Removed following item to avoid script error #(None, None), - test_export('gcc_arm', 'LPC2460') - for (toolchain, target) in exportlist : - print '\n=== Exporting to "%s::%s" ===' % (toolchain, target) - test_export(toolchain, target) + ]: + print '\n=== Exporting to "%s::%s" ===' % (toolchain, target) + test_export(toolchain, target) print "\n=== Test error messages ===" test_export('lpcxpresso', 'LPC11U24', expected_error='lpcxpresso') From dbbacdcbaf388cd272d549e3440850519da94aa7 Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Fri, 8 May 2015 20:58:38 +0400 Subject: [PATCH 017/139] remove ARM toolchain as not supported for LPC2460 --- workspace_tools/build_release.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 63d7a1f0a7..ede554796d 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -34,7 +34,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('UBLOX_C027', ('ARM', 'GCC_ARM', 'GCC_CR', 'GCC_CS', 'IAR')), ('ARCH_PRO', ('ARM', 'GCC_ARM', 'GCC_CR', 'GCC_CS', 'IAR')), ('LPC2368', ('ARM', 'GCC_ARM')), - ('LPC2460', ('ARM', 'GCC_ARM')), + ('LPC2460', ('GCC_ARM')), ('LPC812', ('uARM','IAR')), ('LPC824', ('uARM', 'GCC_ARM', 'IAR', 'GCC_CR')), ('SSCI824', ('uARM','GCC_ARM')), From a098a8d34c0955ca2503a04e20e6273235e17a5f Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Tue, 12 May 2015 12:55:15 +0400 Subject: [PATCH 018/139] add LPC2460 in USB Host library --- libraries/USBHost/USBHost/USBHALHost_LPC17.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/USBHost/USBHost/USBHALHost_LPC17.cpp b/libraries/USBHost/USBHost/USBHALHost_LPC17.cpp index c1eadf3896..462c5f2a59 100644 --- a/libraries/USBHost/USBHost/USBHALHost_LPC17.cpp +++ b/libraries/USBHost/USBHost/USBHALHost_LPC17.cpp @@ -14,7 +14,7 @@ * limitations under the License. */ -#if defined(TARGET_LPC1768) +#if defined(TARGET_LPC1768) || defined(TARGET_LPC2460) #include "mbed.h" #include "USBHALHost.h" From c8ef00561255c533317556ec63159170bc473225 Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Thu, 14 May 2015 16:46:10 +0900 Subject: [PATCH 019/139] add WIZNET TARGET --- .../TOOLCHAIN_ARM_MICRO/W7500.sct | 15 + .../TOOLCHAIN_ARM_MICRO/startup_W7500x.s | 213 +++ .../TOOLCHAIN_ARM_MICRO/sys.cpp | 31 + .../TOOLCHAIN_GCC_ARM/W7500.ld | 152 +++ .../TOOLCHAIN_GCC_ARM/startup_W7500.s | 259 ++++ .../TARGET_WIZwiki_W7500/W7500x.h | 1148 +++++++++++++++++ .../TARGET_WIZwiki_W7500/cmsis.h | 38 + .../TARGET_WIZwiki_W7500/cmsis_nvic.c | 47 + .../TARGET_WIZwiki_W7500/cmsis_nvic.h | 51 + .../TARGET_WIZwiki_W7500/system_W7500x.c | 104 ++ .../TARGET_WIZwiki_W7500/system_W7500x.h | 84 ++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_adc.c | 54 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_adc.h | 59 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_conf.h | 15 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_crg.c | 276 ++++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_crg.h | 145 +++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_exti.c | 157 +++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_exti.h | 86 ++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.c | 288 +++++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.h | 134 ++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.c | 563 ++++++++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.h | 231 ++++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.c | 905 +++++++++++++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.h | 289 +++++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_uart.c | 370 ++++++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_uart.h | 289 +++++ .../TARGET_W7500x/PeripheralPins.h | 26 + .../TARGET_WIZwiki_W7500/PeripheralNames.h | 77 ++ .../TARGET_WIZwiki_W7500/PeripheralPins.c | 106 ++ .../TARGET_WIZwiki_W7500/PinNames.h | 197 +++ .../TARGET_WIZwiki_W7500/PortNames.h | 48 + .../TARGET_WIZwiki_W7500/device.h | 74 ++ .../TARGET_WIZwiki_W7500/objects.h | 98 ++ .../TARGET_W7500x/analogin_api.c | 102 ++ .../TARGET_W7500x/analogout_api.c | 64 + .../TARGET_WIZNET/TARGET_W7500x/gpio_api.c | 62 + .../TARGET_W7500x/gpio_irq_api.c | 148 +++ .../TARGET_WIZNET/TARGET_W7500x/gpio_object.h | 86 ++ .../hal/TARGET_WIZNET/TARGET_W7500x/i2c_api.c | 316 +++++ .../TARGET_W7500x/mbed_overrides.c | 24 + .../hal/TARGET_WIZNET/TARGET_W7500x/pinmap.c | 139 ++ .../TARGET_WIZNET/TARGET_W7500x/port_api.c | 96 ++ .../TARGET_WIZNET/TARGET_W7500x/pwmout_api.c | 0 .../hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c | 0 .../TARGET_WIZNET/TARGET_W7500x/serial_api.c | 280 ++++ .../hal/TARGET_WIZNET/TARGET_W7500x/sleep.c | 43 + .../hal/TARGET_WIZNET/TARGET_W7500x/spi_api.c | 187 +++ .../TARGET_WIZNET/TARGET_W7500x/us_ticker.c | 121 ++ 48 files changed, 8297 insertions(+) create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/W7500.sct create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/W7500.ld create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/startup_W7500.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/W7500x.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_conf.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_exti.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_exti.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.h create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PinNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PortNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/objects.h create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogout_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_object.h create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/i2c_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/mbed_overrides.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pinmap.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/port_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/sleep.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/spi_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/W7500.sct b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/W7500.sct new file mode 100644 index 0000000000..f9ead04667 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/W7500.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00020000 { ; load region size_region + ER_IROM1 0x00000000 0x00020000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00004000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s new file mode 100644 index 0000000000..1cbb5d3f56 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s @@ -0,0 +1,213 @@ +;/**************************************************************************//** +; * @file startup_CMSDK_CM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File for +; * Device CMSDK_CM0 +; * @version V3.01 +; * @date 06. March 2012 +; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER + +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000100 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + DCD SSP0_Handler ; 16+ 0: SSP 0 Handler + DCD SSP1_Handler ; 16+ 1: SSP 1 Handler + DCD UART0_Handler ; 16+ 2: UART 0 Handler + DCD UART1_Handler ; 16+ 3: UART 1 Handler + DCD UART2_Handler ; 16+ 4: UART 2 Handler + DCD I2C0_Handler ; 16+ 5: I2C 0 Handler + DCD I2C1_Handler ; 16+ 6: I2C 1 Handler + DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler + DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler + DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler + DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler + DCD DMA_Handler ; 16+11: DMA Combined Handler + DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler + DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler + DCD PWM0_Handler ; 16+14: PWM0 Handler + DCD PWM1_Handler ; 16+15: PWM1 Handler + DCD PWM2_Handler ; 16+16: PWM2 Handler + DCD PWM3_Handler ; 16+17: PWM3 Handler + DCD PWM4_Handler ; 16+18: PWM4 Handler + DCD PWM5_Handler ; 16+19: PWM5 Handler + DCD PWM6_Handler ; 16+20: PWM6 Handler + DCD PWM7_Handler ; 16+21: PWM7 Handler + DCD RTC_Handler ; 16+22: RTC Handler + DCD ADC_Handler ; 16+23: ADC Handler + DCD WZTOE_Handler ; 16+24: WZTOE_Handler + DCD EXTI_Handler ; 16+25: EXTI_Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Default_Handler PROC + EXPORT SSP0_Handler [WEAK] + EXPORT SSP1_Handler [WEAK] + EXPORT UART0_Handler [WEAK] + EXPORT UART1_Handler [WEAK] + EXPORT UART2_Handler [WEAK] + EXPORT I2C0_Handler [WEAK] + EXPORT I2C1_Handler [WEAK] + EXPORT PORT0_Handler [WEAK] + EXPORT PORT1_Handler [WEAK] + EXPORT PORT2_Handler [WEAK] + EXPORT PORT3_Handler [WEAK] + EXPORT DMA_Handler [WEAK] + EXPORT DUALTIMER0_Handler [WEAK] + EXPORT DUALTIMER1_Handler [WEAK] + EXPORT PWM0_Handler [WEAK] + EXPORT PWM1_Handler [WEAK] + EXPORT PWM2_Handler [WEAK] + EXPORT PWM3_Handler [WEAK] + EXPORT PWM4_Handler [WEAK] + EXPORT PWM5_Handler [WEAK] + EXPORT PWM6_Handler [WEAK] + EXPORT PWM7_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT WZTOE_Handler [WEAK] + EXPORT EXTI_Handler [WEAK] +SSP0_Handler +SSP1_Handler +UART0_Handler +UART1_Handler +UART2_Handler +I2C0_Handler +I2C1_Handler +PORT0_Handler +PORT1_Handler +PORT2_Handler +PORT3_Handler +DMA_Handler +DUALTIMER0_Handler +DUALTIMER1_Handler +PWM0_Handler +PWM1_Handler +PWM2_Handler +PWM3_Handler +PWM4_Handler +PWM5_Handler +PWM6_Handler +PWM7_Handler +RTC_Handler +ADC_Handler +WZTOE_Handler +EXTI_Handler + B . + ENDP + + + ALIGN + + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/sys.cpp new file mode 100644 index 0000000000..2f1024ace8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/sys.cpp @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library - stackheap + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/W7500.ld b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/W7500.ld new file mode 100644 index 0000000000..0d53146fc5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/W7500.ld @@ -0,0 +1,152 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 /* 16K */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/startup_W7500.s b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/startup_W7500.s new file mode 100644 index 0000000000..2808b2ad57 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/startup_W7500.s @@ -0,0 +1,259 @@ +/* File: startup_W7500.s + * Purpose: startup file for Cortex-M0 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.4 + * Date: 20 Dezember 2012 + * + */ +/* Copyright (c) 2011 - 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x200 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + +/* Vector Table */ + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long SSP0_Handler /* 16+ 0: SSP 0 Handler */ + .long SSP1_Handler /* 16+ 1: SSP 1 Handler */ + .long UART0_Handler /* 16+ 2: UART 0 Handler */ + .long UART1_Handler /* 16+ 3: UART 1 Handler */ + .long UART2_Handler /* 16+ 4: UART 2 Handler */ + .long I2C0_Handler /* 16+ 5: I2C 0 Handler */ + .long I2C1_Handler /* 16+ 6: I2C 1 Handler */ + .long PORT0_Handler /* 16+ 7: GPIO Port 0 Combined Handler */ + .long PORT1_Handler /* 16+ 8: GPIO Port 1 Combined Handler */ + .long PORT2_Handler /* 16+ 9: GPIO Port 2 Combined Handler */ + .long PORT3_Handler /* 16+10: GPIO Port 3 Combined Handler */ + .long DMA_Handler /* 16+11: DMA Combined Handler */ + .long DUALTIMER0_Handler /* 16+12: Dual timer 0 handler */ + .long DUALTIMER1_Handler /* 16+ 13: Dual timer 1 Handler */ + .long PWM0_Handler /* 16+ 14: PWM0 Handler */ + .long PWM1_Handler /* 16+ 15: PWM1 Handler */ + .long PWM2_Handler /* 16+ 16: PWM2 Handler */ + .long PWM3_Handler /* 16+ 17: PWM3 Handler */ + .long PWM4_Handler /* 16+ 18: PWM4 Handler */ + .long PWM5_Handler /* 16+ 19: PWM5 Handler */ + .long PWM6_Handler /* 16+ 20: PWM6 Handler */ + .long PWM7_Handler /* 16+ 21: PWM7 Handler */ + .long RTC_Handler /* 16+ 22: RTC Handler */ + .long ADC_Handler /* 16+ 23: ADC Handler */ + .long WZTOE_Handler /* 16+ 24: WZTOE Handler */ + .long EXTI_Handler /* 16+ 25: EXTI Handler */ + + .size __isr_vector, . - __isr_vector +/* Reset Handler */ + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + subs r2, r1 + ble .LC3 + + movs r0, 0 +.LC2: + str r0, [r1, r2] + subs r2, 4 + bge .LC2 +.LC3: +#endif /* __STARTUP_CLEAR_BSS */ + + /*bl _start*/ + bl main + + .pool + .size Reset_Handler, . - Reset_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + +/* System Exception Handlers */ + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + +/* IRQ Handlers */ + + def_default_handler SSP0_Handler + def_default_handler SSP1_Handler + def_default_handler UART0_Handler + def_default_handler UART1_Handler + def_default_handler UART2_Handler + def_default_handler I2C0_Handler + def_default_handler I2C1_Handler + def_default_handler PORT0_Handler + def_default_handler PORT1_Handler + def_default_handler PORT2_Handler + def_default_handler PORT3_Handler + + def_default_handler DMA_Handler + def_default_handler DUALTIMER0_Handler + def_default_handler DUALTIMER1_Handler + def_default_handler PWM0_Handler + def_default_handler PWM1_Handler + def_default_handler PWM2_Handler + def_default_handler PWM3_Handler + def_default_handler PWM4_Handler + def_default_handler PWM5_Handler + def_default_handler PWM6_Handler + def_default_handler PWM7_Handler + def_default_handler RTC_Handler + def_default_handler ADC_Handler + def_default_handler WZTOE_Handler + def_default_handler EXTI_Handler + + /* + def_default_handler Default_Handler + .weak DEF_IRQHandler + .set DEF_IRQHandler, Default_Handler + */ + + .end + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/W7500x.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/W7500x.h new file mode 100644 index 0000000000..ff519c60ce --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/W7500x.h @@ -0,0 +1,1148 @@ +/**************************************************************************//** + * @file W7500x.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for + * Device W7500x + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2010-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef W7500x_H +#define W7500x_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup W7500x_Definitions W7500x Definitions + This file defines all structures and symbols for W7500x: + - registers and bitfields + - peripheral base address + - peripheral ID + - Peripheral definitions + @{ +*/ + + +/******************************************************************************/ +/* Processor and Core Peripherals */ +/******************************************************************************/ +/** @addtogroup W7500x_CMSIS Device CMSIS Definitions + Configuration of the Cortex-M0 Processor and Core Peripherals + @{ +*/ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers **************************************************/ + +/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ +/****** W7500x Specific Interrupt Numbers *********************************************************/ + SSP0_IRQn = 0, /*!< SSP 0 Interrupt */ + SSP1_IRQn = 1, /*!< SSP 1 Interrupt */ + UART0_IRQn = 2, /*!< UART 0 Interrupt */ + UART1_IRQn = 3, /*!< UART 1 Interrupt */ + UART2_IRQn = 4, /*!< UART 2 Interrupt */ + I2C0_IRQn = 5, /*!< I2C 0 Interrupt */ + I2C1_IRQn = 6, /*!< I2C 1 Interrupt */ + PORT0_IRQn = 7, /*!< Port 1 combined Interrupt */ + PORT1_IRQn = 8, /*!< Port 2 combined Interrupt */ + PORT2_IRQn = 9, /*!< Port 2 combined Interrupt */ + PORT3_IRQn = 10, /*!< Port 2 combined Interrupt */ + DMA_IRQn = 11, /*!< DMA combined Interrupt */ + DUALTIMER0_IRQn = 12, /*!< Dual Timer 0 Interrupt */ + DUALTIMER1_IRQn = 13, /*!< Dual Timer 1 Interrupt */ + PWM0_IRQn = 14, /*!< PWM 0 Interrupt */ + PWM1_IRQn = 15, /*!< PWM 1 Interrupt */ + PWM2_IRQn = 16, /*!< PWM 2 Interrupt */ + PWM3_IRQn = 17, /*!< PWM 3 Interrupt */ + PWM4_IRQn = 18, /*!< PWM 4 Interrupt */ + PWM5_IRQn = 19, /*!< PWM 5 Interrupt */ + PWM6_IRQn = 20, /*!< PWM 6 Interrupt */ + PWM7_IRQn = 21, /*!< PWM 7 Interrupt */ + RTC_IRQn = 22, /*!< RTC Interrupt */ + ADC_IRQn = 23, /*!< ADC Interrupt */ + WZTOE_IRQn = 24, /*!< WZTOE Interrupt */ + EXTI_IRQn = 25 /*!< EXTI Interrupt */ +} IRQn_Type; + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M0 Processor and Core Peripherals */ +#define __CM0_REV 0x0000 /*!< Core Revision r0p0 */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ + +/*@}*/ /* end of group W7500x_CMSIS */ + + +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#include "system_W7500x.h" /* W7500x System include file */ + + +/** @addtogroup Exported_types + * @{ + */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + + + + + +/** + * @} + */ + + + + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Clock Reset Generator + */ +typedef struct +{ + __IO uint32_t OSC_PDR; /*!< Oscillator power down register, Address offset : 0x00 */ + uint32_t RESERVED0[3]; + __IO uint32_t PLL_PDR; /*!< PLL power down register, Address offset : 0x10 */ + __IO uint32_t PLL_FCR; /*!< PLL frequency calculating register, Address offset : 0x14 */ + __IO uint32_t PLL_OER; /*!< PLL output enable register, Address offset : 0x18 */ + __IO uint32_t PLL_BPR; /*!< PLL bypass register, Address offset : 0x1c */ + __IO uint32_t PLL_IFSR; /*!< PLL input frequency select register, Address offset : 0x20 */ + uint32_t RESERVED1[3]; + __IO uint32_t FCLK_SSR; /*!< FCLK source select register, Address offset : 0x30 */ + __IO uint32_t FCLK_PVSR; /*!< FCLK prescale value select register, Address offset : 0x34 */ + uint32_t RESERVED2[2]; + __IO uint32_t SSPCLK_SSR; /*!< SSPCLK source select register, Address offset : 0x40 */ + __IO uint32_t SSPCLK_PVSR; /*!< SSPCLK prescale value select register, Address offset : 0x44 */ + uint32_t RESERVED3[6]; + __IO uint32_t ADCCLK_SSR; /*!< ADCCLK source select register, Address offset : 0x60 */ + __IO uint32_t ADCCLK_PVSR; /*!< ADCCLK prescale value select register, Address offset : 0x64 */ + uint32_t RESERVED4[2]; + __IO uint32_t TIMER0CLK_SSR; /*!< TIMER0CLK source select register, Address offset : 0x70 */ + __IO uint32_t TIMER0CLK_PVSR; /*!< TIMER0CLK prescale value select register, Address offset : 0x74 */ + uint32_t RESERVED5[2]; + __IO uint32_t TIMER1CLK_SSR; /*!< TIMER1CLK source select register, Address offset : 0x80 */ + __IO uint32_t TIMER1CLK_PVSR; /*!< TIMER1CLK prescale value select register, Address offset : 0x84 */ + uint32_t RESERVED6[10]; + __IO uint32_t PWM0CLK_SSR; /*!< PWM0CLK source select register, Address offset : 0xb0 */ + __IO uint32_t PWM0CLK_PVSR; /*!< PWM0CLK prescale value select register, Address offset : 0xb4 */ + uint32_t RESERVED7[2]; + __IO uint32_t PWM1CLK_SSR; /*!< PWM1CLK source select register, Address offset : 0xc0 */ + __IO uint32_t PWM1CLK_PVSR; /*!< PWM1CLK prescale value select register, Address offset : 0xc4 */ + uint32_t RESERVED8[2]; + __IO uint32_t PWM2CLK_SSR; /*!< PWM2CLK source select register, Address offset : 0xd0 */ + __IO uint32_t PWM2CLK_PVSR; /*!< PWM2CLK prescale value select register, Address offset : 0xd4 */ + uint32_t RESERVED9[2]; + __IO uint32_t PWM3CLK_SSR; /*!< PWM3CLK source select register, Address offset : 0xe0 */ + __IO uint32_t PWM3CLK_PVSR; /*!< PWM3CLK prescale value select register, Address offset : 0xe4 */ + uint32_t RESERVED10[2]; + __IO uint32_t PWM4CLK_SSR; /*!< PWM4CLK source select register, Address offset : 0xf0 */ + __IO uint32_t PWM4CLK_PVSR; /*!< PWM4CLK prescale value select register, Address offset : 0xf4 */ + uint32_t RESERVED11[2]; + __IO uint32_t PWM5CLK_SSR; /*!< PWM5CLK source select register, Address offset : 0x100 */ + __IO uint32_t PWM5LK_PVSR; /*!< PWM5CLK prescale value select register, Address offset : 0x104 */ + uint32_t RESERVED12[2]; + __IO uint32_t PWM6CLK_SSR; /*!< PWM6CLK source select register, Address offset : 0x110 */ + __IO uint32_t PWM6CLK_PVSR; /*!< PWM6CLK prescale value select register, Address offset : 0x114 */ + uint32_t RESERVED13[2]; + __IO uint32_t PWM7CLK_SSR; /*!< PWM7CLK source select register, Address offset : 0x120 */ + __IO uint32_t PWM7CLK_PVSR; /*!< PWM7CLK prescale value select register, Address offset : 0x124 */ + uint32_t RESERVED14[2]; + __IO uint32_t RTC_HS_SSR; /*!< RTC High Speed source select register, Address offset : 0x130 */ + __IO uint32_t RTC_HS_PVSR; /*!< RTC High Speed prescale value select register, Address offset : 0x134 */ + uint32_t RESERVED15; + __IO uint32_t RTC_SSR; /*!< RTC source select register, Address offset : 0x13c */ + + __IO uint32_t WDOGCLK_HS_SSR; /*!< WDOGCLK High Speed source select register, Address offset : 0x140 */ + __IO uint32_t WDOGCLK_HS_PVSR; /*!< WDOGCLK High Speed prescale value select register, Address offset : 0x144 */ + uint32_t RESERVED16; + __IO uint32_t WDOGCLK_SSR; /*!< WDOGCLK source select register, Address offset : 0x14c */ + + __IO uint32_t UARTCLK_SSR; /*!< UARTCLK source select register, Address offset : 0x150 */ + __IO uint32_t UARTCLK_PVSR; /*!< UARTCLK prescale value select register, Address offset : 0x154 */ + uint32_t RESERVED17[2]; + __IO uint32_t MIICLK_ECR; /*!< MII clock enable control register, Address offset : 0x160 */ + uint32_t RESERVED18[3]; + __IO uint32_t MONCLK_SSR; /*!< Monitoring clock source select I found Treasure was IoT Base Station in March.register, Address offset : 0x170 */ +}CRG_TypeDef; + + +/** + * @brief UART + */ +typedef struct +{ + __IO uint32_t DR; /*!< Data, Address offset : 0x00 */ + union { + __I uint32_t RSR; /*!< Receive Status, Address offset : 0x04 */ + __O uint32_t ECR; /*!< Error Clear, Address offset : 0x04 */ + } STATUS; + uint32_t RESERVED0[4]; + __IO uint32_t FR; /*!< Flags, Address offset : 0x18 */ + uint32_t RESERVED1; + __IO uint32_t ILPR; /*!< IrDA Low-power Counter, Address offset : 0x20 */ + __IO uint32_t IBRD; /*!< Integer Baud Rate, Address offset : 0x24 */ + __IO uint32_t FBRD; /*!< Fractional Baud Rate, Address offset : 0x28 */ + __IO uint32_t LCR_H; /*!< Line Control, Address offset : 0x2C */ + __IO uint32_t CR; /*!< Control, Address offset : 0x30 */ + __IO uint32_t IFLS; /*!< Interrupt FIFO Level Select, Address offset : 0x34 */ + __IO uint32_t IMSC; /*!< Interrupt Mask Set / Clear, Address offset : 0x38 */ + __IO uint32_t RIS; /*!< Raw Interrupt Status , Address offset : 0x3C */ + __IO uint32_t MIS; /*!< Masked Interrupt Status , Address offset : 0x40 */ + __O uint32_t ICR; /*!< Interrupt Clear, Address offset : 0x44 */ + __IO uint32_t DMACR; /*!< DMA Control, Address offset : 0x48 */ +} UART_TypeDef; + + +/** + * @brief Simple UART + */ +typedef struct +{ + __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */ + __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */ + __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */ + union { + __I uint32_t STATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */ + __O uint32_t CLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */ + }INT; + __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */ + +} S_UART_TypeDef; + +/** + * @brief Analog Digital Converter + */ + +typedef struct +{ + __IO uint32_t ADC_CTR; /* ADC control register, Address offset : 0x000 */ + __IO uint32_t ADC_CHSEL; /* ADC channel select register, Address offset : 0x004 */ + __IO uint32_t ADC_START; /* ADC start register, Address offset : 0x008 */ + __I uint32_t ADC_DATA; /* ADC conversion data register, Address offset : 0x00c */ + __IO uint32_t ADC_INT; /* ADC interrupt register, Address offset : 0x010 */ + uint32_t RESERVED0[2]; + __IO uint32_t ADC_INTCLR; /* ADC interrupt clear register, Address offset : 0x01c */ +}ADC_TypeDef; + +/** + * @brief dualtimer + */ +typedef struct +{ + __IO uint32_t TimerLoad; // Timer Load + __I uint32_t TimerValue; // Timer Counter Current Value + __IO uint32_t TimerControl; // Timer Control + // TimerEn: Timer Enable + // TimerMode: Timer Mode + // <0=> Freerunning-mode + // <1=> Periodic mode + // IntEnable: Interrupt Enable + // TimerPre: Timer Prescale + // <0=> / 1 + // <1=> / 16 + // <2=> / 256 + // <3=> Undefined! + // TimerSize: Timer Size + // <0=> 16-bit counter + // <1=> 32-bit counter + // OneShot: One-shoot mode + // <0=> Wrapping mode + // <1=> One-shot mode + // + __O uint32_t TimerIntClr; // Timer Interrupt Clear + __I uint32_t TimerRIS; // Timer Raw Interrupt Status + __I uint32_t TimerMIS; // Timer Masked Interrupt Status + __IO uint32_t TimerBGLoad; // Background Load Register +} DUALTIMER_TypeDef; + +/** + * @brief GPIO + */ +typedef struct +{ + __IO uint32_t DATA; /* DATA Register (R/W), offset : 0x000 */ + __IO uint32_t DATAOUT; /* Data Output Latch Register (R/W), offset : 0x004 */ + uint32_t RESERVED0[2]; + __IO uint32_t OUTENSET; /* Output Enable Set Register (R/W) offset : 0x010 */ + __IO uint32_t OUTENCLR; /* Output Enable Clear Register (R/W) offset : 0x014 */ + __IO uint32_t RESERVED1; /* Alternate Function Set Register (R/W) offset : 0x018 */ + __IO uint32_t RESERVED2; /* Alternate Function Clear Register (R/W) offset : 0x01C */ + __IO uint32_t INTENSET; /* Interrupt Enable Set Register (R/W) offset : 0x020 */ + __IO uint32_t INTENCLR; /* Interrupt Enable Clear Register (R/W) offset : 0x024 */ + __IO uint32_t INTTYPESET; /* Interrupt Type Set Register (R/W) offset : 0x028 */ + __IO uint32_t INTTYPECLR; /* Interrupt Type Clear Register (R/W) offset : 0x02C */ + __IO uint32_t INTPOLSET; /* Interrupt Polarity Set Register (R/W) offset : 0x030 */ + __IO uint32_t INTPOLCLR; /* Interrupt Polarity Clear Register (R/W) offset : 0x034 */ + union { + __I uint32_t INTSTATUS; /* Interrupt Status Register (R/ ) offset : 0x038 */ + __O uint32_t INTCLEAR; /* Interrupt Clear Register ( /W) offset : 0x038 */ + }Interrupt; + uint32_t RESERVED3[241]; + __IO uint32_t LB_MASKED[256]; /* Lower byte Masked Access Register (R/W) offset : 0x400 - 0x7FC */ + __IO uint32_t UB_MASKED[256]; /* Upper byte Masked Access Register (R/W) offset : 0x800 - 0xBFC */ +} GPIO_TypeDef; + +typedef struct +{ + __IO uint32_t Port[16]; /* Port_00, offset : 0x00 */ + /* Port_01, offset : 0x04 */ + /* Port_02, offset : 0x08 */ + /* Port_03, offset : 0x0C */ + /* Port_04, offset : 0x10 */ + /* Port_05, offset : 0x14 */ + /* Port_06, offset : 0x18 */ + /* Port_07, offset : 0x1C */ + /* Port_08, offset : 0x20 */ + /* Port_09, offset : 0x24 */ + /* Port_10, offset : 0x28 */ + /* Port_11, offset : 0x2C */ + /* Port_12, offset : 0x30 */ + /* Port_13, offset : 0x34 */ + /* Port_14, offset : 0x38 */ + /* Port_15, offset : 0x3C */ +} P_Port_Def; + +typedef struct +{ + __IO uint32_t Port[5]; /* Port_00, offset : 0x00 */ + /* Port_01, offset : 0x04 */ + /* Port_02, offset : 0x08 */ + /* Port_03, offset : 0x0C */ + /* Port_04, offset : 0x10 */ +} P_Port_D_Def; + +/** + * @brief I2C Register structure definition + */ +typedef struct +{ + __IO uint32_t PRER; //0x00 + __IO uint32_t CTR; //0x04 + __IO uint32_t CMDR; //0x08 + __I uint32_t SR; //0x0C + __IO uint32_t TSR; //0x10 + __IO uint32_t SADDR; //0x14 + __IO uint32_t TXR; //0x18 + __I uint32_t RXR; //0x1C + __I uint32_t ISR; //0x20 + __IO uint32_t ISCR; //0x24 + __IO uint32_t ISMR; //0x28 +}I2C_TypeDef; + +/** + * @brief PWM Register structure definition + */ +typedef struct +{ + __IO uint32_t IER; //Interrupt enable register + // <7> IE7 : Channel 7 interrupt enable + // <6> IE6 : Channel 6 interrupt enable + // <5> IE5 : Channel 5 interrupt enable + // <4> IE4 : Channel 4 interrupt enable + // <3> IE3 : Channel 3 interrupt enable + // <2> IE2 : Channel 2 interrupt enable + // <1> IE1 : Channel 1 interrupt enable + // <0> IE0 : Channel 0 interrupt enable + + __IO uint32_t SSR; //Start Stop register + // <7> SS7 : Channel 7 TC start or stop + // <6> SS6 : Channel 6 TC start or stop + // <5> SS5 : Channel 5 TC start or stop + // <4> SS4 : Channel 4 TC start or stop + // <3> SS3 : Channel 3 TC start or stop + // <2> SS2 : Channel 2 TC start or stop + // <1> SS1 : Channel 1 TC start or stop + // <0> SS0 : Channel 0 TC start or stop + + __IO uint32_t PSR; //Pause register + // <7> PS7 : Channel 7 TC pasue + // <6> PS6 : Channel 6 TC pasue + // <5> PS5 : Channel 5 TC pasue + // <4> PS4 : Channel 4 TC pasue + // <3> PS3 : Channel 3 TC pasue + // <2> PS2 : Channel 2 TC pasue + // <1> PS1 : Channel 1 TC pasue + // <0> PS0 : Channel 0 TC pasue +} PWM_TypeDef; + +typedef struct +{ + __I uint32_t IR; //Interrupt register + // <2> CI : Capture interrupt + // <1> OI : Overflow interrupt + // <0> MI : Match interrupt + + __IO uint32_t IER; //Interrupt enable register + // <2> CIE : Capture interrupt enable + // <1> OIE : Overflow interrupt enable + // <0> MIE : Match interrupt enable + + __O uint32_t ICR; //Interrupt clear register + // <2> CIC : Capture interrupt clear + // <1> OIC : Overflow interrupt clear + // <0> MIC : Match interrupt clear + + __I uint32_t TCR; //Timer/Counter register + // <0..31> TCR : Timer/Counter register + + __I uint32_t PCR; //Prescale counter register + // <0..5> PCR : Prescale Counter register + + __IO uint32_t PR; //Prescale register + // <0..5> PR : prescale register + + __IO uint32_t MR; //Match register + // <0..31> MR : Match register + + __IO uint32_t LR; //Limit register + // <0..31> LR : Limit register + __IO uint32_t UDMR; //Up-Down mode register + // <0> UDM : Up-down mode + + __IO uint32_t TCMR; //Timer/Counter mode register + // <0> TCM : Timer/Counter mode + + __IO uint32_t PEEER; //PWM output enable and external input enable register + // <0..1> PEEE : PWM output enable and external input enable + + __IO uint32_t CMR; //Capture mode register + // <0> CM : Capture mode + + __IO uint32_t CR; //Capture register + // <0..31> CR : Capture register + + __IO uint32_t PDMR; //Periodic mode register + // <0> PDM : Periodic mode + + __IO uint32_t DZER; //Dead-zone enable register + // <0> DZE : Dead-zone enable + + __IO uint32_t DZCR; //Dead-zone counter register + // <0..9> DZC : Dead-zone counter +} PWM_CHn_TypeDef; + +typedef struct +{ + __IO uint32_t PWM_CHn_PR; //Prescale register + // <0..5> PR : prescale register + __IO uint32_t PWM_CHn_MR; //Match register + // <0..31> MR : Match register + __IO uint32_t PWM_CHn_LR; //Limit register + // <0..31> LR : Limit register + __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register + // <0> UDM : Up-down mode + __IO uint32_t PWM_CHn_PDMR; //Periodic mode register + // <0> PDM : Periodic mode +}PWM_TimerModeInitTypeDef; + +typedef struct +{ + __IO uint32_t PWM_CHn_PR; //Prescale register + // <0..5> PR : prescale register + __IO uint32_t PWM_CHn_MR; //Match register + // <0..31> MR : Match register + __IO uint32_t PWM_CHn_LR; //Limit register + // <0..31> LR : Limit register + __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register + // <0> UDM : Up-down mode + __IO uint32_t PWM_CHn_PDMR; //Periodic mode register + // <0> PDM : Peiodic mode + __IO uint32_t PWM_CHn_CMR; //Capture mode register + // <0> CM : Capture mode +}PWM_CaptureModeInitTypeDef; + +typedef struct +{ + __IO uint32_t PWM_CHn_MR; + __IO uint32_t PWM_CHn_LR; + __IO uint32_t PWM_CHn_UDMR; + __IO uint32_t PWM_CHn_PDMR; + __IO uint32_t PWM_CHn_TCMR; +}PWM_CounterModeInitTypeDef; + + +/** + * @brief Random Number generator + */ +typedef struct +{ + __IO uint32_t RNG_RUN; /* RNG run register, Address offset : 0x000 */ + __IO uint32_t RNG_SEED; /* RNG seed value register, Address offset : 0x004 */ + __IO uint32_t RNG_CLKSEL; /* RNG Clock source select register, Address offset : 0x008 */ + __IO uint32_t RNG_MODE; /* RNG MODE select register, Address offset : 0x00c */ + __I uint32_t RNG_RN; /* RNG random number value register, Address offset : 0x010 */ + __IO uint32_t RNG_POLY; /* RNG polynomial register, Address offset : 0x014 */ +}RNG_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR0; + __IO uint32_t CR1; + __IO uint32_t DR; + __IO uint32_t SR; + __IO uint32_t CPSR; + __IO uint32_t IMSC; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t ICR; + __IO uint32_t DMACR; +} SSP_TypeDef; + +typedef struct +{ + __IO uint32_t WatchdogLoad; // Watchdog Load Register + __I uint32_t WatchdogValue; // Watchdog Value Register + __IO uint32_t WatchdogControl; // Watchdog Control Register + // RESEN: Reset enable + // INTEN: Interrupt enable + // + __O uint32_t WatchdogIntClr; // Watchdog Clear Interrupt Register + __I uint32_t WatchdogRIS; // Watchdog Raw Interrupt Status Register + __I uint32_t WatchdogMIS; // Watchdog Interrupt Status Register + uint32_t RESERVED[762]; + __IO uint32_t WatchdogLock; // Watchdog Lock Register +}WATCHDOG_TypeDef; + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +/* Peripheral and SRAM base address */ +#define W7500x_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */ +#define W7500x_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */ +#define W7500x_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */ + +#define W7500x_RAM_BASE (0x20000000UL) +#define W7500x_APB1_BASE (0x40000000UL) +#define W7500x_APB2_BASE (0x41000000UL) +#define W7500x_AHB_BASE (0x42000000UL) + +#define W7500x_UART0_BASE (W7500x_APB1_BASE + 0x0000C000UL) +#define W7500x_UART1_BASE (W7500x_APB1_BASE + 0x0000D000UL) +#define W7500x_UART2_BASE (W7500x_APB1_BASE + 0x00006000UL) + +#define W7500x_CRG_BASE (W7500x_APB2_BASE + 0x00001000UL) +#define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL) + +#define W7500x_INFO_BGT (0x0003FDB8) +#define W7500x_INFO_OSC (0x0003FDBC) + +#define W7500x_TRIM_BGT (0x41001210) +#define W7500x_TRIM_OSC (0x41001004) + +#define W7500x_DUALTIMER0_BASE (W7500x_APB1_BASE + 0x00001000ul) +#define W7500x_DUALTIMER1_BASE (W7500x_APB1_BASE + 0x00002000ul) + +#define EXTI_Px_BASE (W7500x_APB2_BASE + 0x00002200UL) + +#define GPIOA_BASE (W7500x_AHB_BASE + 0x00000000UL) // W7500x_AHB_BASE : 0x42000000UL +#define GPIOB_BASE (W7500x_AHB_BASE + 0x01000000UL) +#define GPIOC_BASE (W7500x_AHB_BASE + 0x02000000UL) +#define GPIOD_BASE (W7500x_AHB_BASE + 0x03000000UL) + +#define P_AFSR_BASE (W7500x_APB2_BASE + 0x00002000UL) + +#define P_PCR_BASE (W7500x_APB2_BASE + 0x00003000UL) + +#define I2C0_BASE (W7500x_APB1_BASE + 0x8000) +#define I2C1_BASE (W7500x_APB1_BASE + 0x9000) + +#define W7500x_PWM_BASE (W7500x_APB1_BASE + 0x00005000UL) + +#define W7500x_RNG_BASE (W7500x_APB1_BASE + 0x00007000UL) + +#define SSP0_BASE (0x4000A000) +#define SSP1_BASE (0x4000B000) + +#define W7500x_WATCHDOG_BASE (W7500x_APB1_BASE + 0x0000UL) + +/** + * @} + */ + + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define CRG ((CRG_TypeDef *) W7500x_CRG_BASE) + +#define UART0 ((UART_TypeDef *) W7500x_UART0_BASE) +#define UART1 ((UART_TypeDef *) W7500x_UART1_BASE) +#define UART2 ((S_UART_TypeDef *) W7500x_UART2_BASE) + +#define ADC ((ADC_TypeDef *) W7500x_ADC_BASE) + +#define DUALTIMER0_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE) ) +#define DUALTIMER0_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE + 0x20ul)) +#define DUALTIMER1_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE) ) +#define DUALTIMER1_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE + 0x20ul)) + +#define EXTI_PA ((P_Port_Def *) (EXTI_Px_BASE + 0x00000000UL)) /* PA_XX External interrupt Enable Register */ +#define EXTI_PB ((P_Port_Def *) (EXTI_Px_BASE + 0x00000040UL)) /* PB_XX External interrupt Enable Register */ +#define EXTI_PC ((P_Port_Def *) (EXTI_Px_BASE + 0x00000080UL)) /* PC_XX External interrupt Enable Register */ +#define EXTI_PD ((P_Port_D_Def *) (EXTI_Px_BASE + 0x000000C0UL)) /* PD_XX External interrupt Enable Register */ + +#define GPIOA ((GPIO_TypeDef *) (GPIOA_BASE) ) +#define GPIOB ((GPIO_TypeDef *) (GPIOB_BASE) ) +#define GPIOC ((GPIO_TypeDef *) (GPIOC_BASE) ) +#define GPIOD ((GPIO_TypeDef *) (GPIOD_BASE) ) + +#define PA_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000000UL)) /* PA_XX Pad Alternate Function Select Register */ +#define PB_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000040UL)) /* PB_XX Pad Alternate Function Select Register */ +#define PC_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000080UL)) /* PC_XX Pad Alternate Function Select Register */ +#define PD_AFSR ((P_Port_D_Def *) (P_AFSR_BASE + 0x000000C0UL)) /* PD_XX Pad Alternate Function Select Register */ + +#define PA_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000000UL)) /* PA_XX Pad Control Register */ +#define PB_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000040UL)) /* PB_XX Pad Control Register */ +#define PC_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000080UL)) /* PC_XX Pad Control Register */ +#define PD_PCR ((P_Port_D_Def *) (P_PCR_BASE + 0x000000C0UL)) /* PD_XX Pad Control Register */ + +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) + + +#define TIMCLKEN0_0 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0x80ul) +#define TIMCLKEN0_1 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0xA0ul) +#define TIMCLKEN1_0 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0x80ul) +#define TIMCLKEN1_1 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0xA0ul) + +#define PWM ((PWM_TypeDef *) (W7500x_PWM_BASE + 0x800UL )) +#define PWM_CH0 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE)) +#define PWM_CH1 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x100UL)) +#define PWM_CH2 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x200UL)) +#define PWM_CH3 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x300UL)) +#define PWM_CH4 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x400UL)) +#define PWM_CH5 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x500UL)) +#define PWM_CH6 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x600UL)) +#define PWM_CH7 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x700UL)) + +#define RNG ((RNG_TypeDef *) W7500x_RNG_BASE) + +#define SSP0 ((SSP_TypeDef*) (SSP0_BASE)) +#define SSP1 ((SSP_TypeDef*) (SSP1_BASE)) + +#define WATCHDOG ((WATCHDOG_TypeDef *) W7500x_WATCHDOG_BASE) + +/** + * @} + */ + + + +/******************************************************************************/ +/* */ +/* Clock Reset Generator */ +/* */ +/******************************************************************************/ +/**************** Bit definition for CRG_OSC_PDR **************************/ +#define CRG_OSC_PDR_NRMLOP (0x0ul) // Normal Operation +#define CRG_OSC_PDR_PD (0x1ul) // Power Down +/**************** Bit definition for CRG_PLL_PDR **************************/ +#define CRG_PLL_PDR_PD (0x0ul) // Power Down +#define CRG_PLL_PDR_NRMLOP (0x1ul) // Normal Operation +/**************** Bit definition for CRG_PLL_FCR **************************/ +//ToDo +/**************** Bit definition for CRG_PLL_OER **************************/ +#define CRG_PLL_OER_DIS (0x0ul) // Clock out is disable +#define CRG_PLL_OER_EN (0x1ul) // Clock out is enable +/**************** Bit definition for CRG_PLL_BPR **************************/ +#define CRG_PLL_BPR_DIS (0x0ul) // Bypass disable. Normal operation +#define CRG_PLL_BPR_EN (0x1ul) // Bypass enable. Clock will be set to external clock +/**************** Bit definition for CRG_PLL_IFSR **************************/ +#define CRG_PLL_IFSR_RCLK (0x0ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_PLL_IFSR_OCLK (0x1ul) // External oscillator clock (OCLK, 8MHz ~ 24MHz) +/**************** Bit definition for CRG_FCLK_SSR **************************/ +#define CRG_FCLK_SSR_MCLK (0x01ul) // 00,01 Output clock of PLL(MCLK) +#define CRG_FCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_FCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) +/**************** Bit definition for CRG_FCLK_PVSR **************************/ +#define CRG_FCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass) +#define CRG_FCLK_PVSR_DIV2 (0x01ul) // 1/2 +#define CRG_FCLK_PVSR_DIV4 (0x02ul) // 1/4 +#define CRG_FCLK_PVSR_DIV8 (0x03ul) // 1/8 +/**************** Bit definition for CRG_SSPCLK_SSR **************************/ +#define CRG_SSPCLK_SSR_DIS (0x00ul) // Disable clock +#define CRG_SSPCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK) +#define CRG_SSPCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_SSPCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) +/**************** Bit definition for CRG_SSPCLK_PVSR **************************/ +#define CRG_SSPCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass) +#define CRG_SSPCLK_PVSR_DIV2 (0x01ul) // 1/2 +#define CRG_SSPCLK_PVSR_DIV4 (0x02ul) // 1/4 +#define CRG_SSPCLK_PVSR_DIV8 (0x03ul) // 1/8 +/**************** Bit definition for CRG_ADCCLK_SSR **************************/ +#define CRG_ADCCLK_SSR_DIS (0x00ul) // Disable clock +#define CRG_ADCCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK) +#define CRG_ADCCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_ADCCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) +/**************** Bit definition for CRG_ADCCLK_PVSR **************************/ +#define CRG_ADCCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass) +#define CRG_ADCCLK_PVSR_DIV2 (0x01ul) // 1/2 +#define CRG_ADCCLK_PVSR_DIV4 (0x02ul) // 1/4 +#define CRG_ADCCLK_PVSR_DIV8 (0x03ul) // 1/8 +/**************** Bit definition for CRG_TIMER0/1CLK_SSR **************************/ +#define CRG_TIMERCLK_SSR_DIS (0x00ul) // Disable clock +#define CRG_TIMERCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK) +#define CRG_TIMERCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_TIMERCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) +/**************** Bit definition for CRG_TIMER0/1CLK_PVSR **************************/ +#define CRG_TIMERCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass) +#define CRG_TIMERCLK_PVSR_DIV2 (0x01ul) // 1/2 +#define CRG_TIMERCLK_PVSR_DIV4 (0x02ul) // 1/4 +#define CRG_TIMERCLK_PVSR_DIV8 (0x03ul) // 1/8 +#define CRG_TIMERCLK_PVSR_DIV16 (0x04ul) // 1/16 +#define CRG_TIMERCLK_PVSR_DIV32 (0x05ul) // 1/32 +#define CRG_TIMERCLK_PVSR_DIV64 (0x06ul) // 1/64 +#define CRG_TIMERCLK_PVSR_DIV128 (0x07ul) // 1/128 +/**************** Bit definition for CRG_PWMnCLK_SSR **************************/ +#define CRG_PWMCLK_SSR_DIS (0x00ul) // Disable clock +#define CRG_PWMCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK) +#define CRG_PWMCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_PWMCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) +/**************** Bit definition for CRG_PWMnCLK_PVSR **************************/ +#define CRG_PWMCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass) +#define CRG_PWMCLK_PVSR_DIV2 (0x01ul) // 1/2 +#define CRG_PWMCLK_PVSR_DIV4 (0x02ul) // 1/4 +#define CRG_PWMCLK_PVSR_DIV8 (0x03ul) // 1/8 +#define CRG_PWMCLK_PVSR_DIV16 (0x04ul) // 1/16 +#define CRG_PWMCLK_PVSR_DIV32 (0x05ul) // 1/32 +#define CRG_PWMCLK_PVSR_DIV64 (0x06ul) // 1/64 +#define CRG_PWMCLK_PVSR_DIV128 (0x07ul) // 1/128 +/**************** Bit definition for CRG_RTC_HS_SSR **************************/ +#define CRG_RTC_HS_SSR_DIS (0x00ul) // Disable clock +#define CRG_RTC_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK) +#define CRG_RTC_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_RTC_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) +/**************** Bit definition for CRG_RTC_HS_PVSR **************************/ +#define CRG_RTC_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass) +#define CRG_RTC_HS_PVSR_DIV2 (0x01ul) // 1/2 +#define CRG_RTC_HS_PVSR_DIV4 (0x02ul) // 1/4 +#define CRG_RTC_HS_PVSR_DIV8 (0x03ul) // 1/8 +#define CRG_RTC_HS_PVSR_DIV16 (0x04ul) // 1/16 +#define CRG_RTC_HS_PVSR_DIV32 (0x05ul) // 1/32 +#define CRG_RTC_HS_PVSR_DIV64 (0x06ul) // 1/64 +#define CRG_RTC_HS_PVSR_DIV128 (0x07ul) // 1/128 +/**************** Bit definition for CRG_RTC_SSR **************************/ +#define CRG_RTC_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock) +#define CRG_RTC_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock) +/**************** Bit definition for CRG_WDOGCLK_HS_SSR **************************/ +#define CRG_WDOGCLK_HS_SSR_DIS (0x00ul) // Disable clock +#define CRG_WDOGCLK_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK) +#define CRG_WDOGCLK_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_WDOGCLK_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) +/**************** Bit definition for CRG_WDOGCLK_HS_PVSR **************************/ +#define CRG_WDOGCLK_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass) +#define CRG_WDOGCLK_HS_PVSR_DIV2 (0x01ul) // 1/2 +#define CRG_WDOGCLK_HS_PVSR_DIV4 (0x02ul) // 1/4 +#define CRG_WDOGCLK_HS_PVSR_DIV8 (0x03ul) // 1/8 +#define CRG_WDOGCLK_HS_PVSR_DIV16 (0x04ul) // 1/16 +#define CRG_WDOGCLK_HS_PVSR_DIV32 (0x05ul) // 1/32 +#define CRG_WDOGCLK_HS_PVSR_DIV64 (0x06ul) // 1/64 +#define CRG_WDOGCLK_HS_PVSR_DIV128 (0x07ul) // 1/128 +/**************** Bit definition for CRG_WDOGCLK_SSR **************************/ +#define CRG_WDOGCLK_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock) +#define CRG_WDOGCLK_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock) +/**************** Bit definition for CRG_UARTCLK_SSR **************************/ +#define CRG_UARTCLK_SSR_DIS (0x00ul) // Disable clock +#define CRG_UARTCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK) +#define CRG_UARTCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_UARTCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) +/**************** Bit definition for CRG_UARTCLK_PVSR **************************/ +#define CRG_UARTCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass) +#define CRG_UARTCLK_PVSR_DIV2 (0x01ul) // 1/2 +#define CRG_UARTCLK_PVSR_DIV4 (0x02ul) // 1/4 +#define CRG_UARTCLK_PVSR_DIV8 (0x03ul) // 1/8 +/**************** Bit definition for CRG_MIICLK_ECR **************************/ +#define CRG_MIICLK_ECR_EN_RXCLK (0x01ul << 0) // Enable MII_RCK and MII_RCK_N +#define CRG_MIICLK_ECR_EN_TXCLK (0x01ul << 1) // Enable MII_TCK and MII_TCK_N +/**************** Bit definition for CRG_MONCLK_SSR **************************/ +#define CRG_MONCLK_SSR_MCLK (0x00ul) // PLL output clock (MCLK) +#define CRG_MONCLK_SSR_FCLK (0x01ul) // FCLK +#define CRG_MONCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_MONCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) +#define CRG_MONCLK_SSR_ADCCLK (0x04ul) // ADCCLK +#define CRG_MONCLK_SSR_SSPCLK (0x05ul) // SSPCLK +#define CRG_MONCLK_SSR_TIMCLK0 (0x06ul) // TIMCLK0 +#define CRG_MONCLK_SSR_TIMCLK1 (0x07ul) // TIMCLK1 +#define CRG_MONCLK_SSR_PWMCLK0 (0x08ul) // PWMCLK0 +#define CRG_MONCLK_SSR_PWMCLK1 (0x09ul) // PWMCLK1 +#define CRG_MONCLK_SSR_PWMCLK2 (0x0Aul) // PWMCLK2 +#define CRG_MONCLK_SSR_PWMCLK3 (0x0Bul) // PWMCLK3 +#define CRG_MONCLK_SSR_PWMCLK4 (0x0Cul) // PWMCLK4 +#define CRG_MONCLK_SSR_PWMCLK5 (0x0Dul) // PWMCLK5 +#define CRG_MONCLK_SSR_PWMCLK6 (0x0Eul) // PWMCLK6 +#define CRG_MONCLK_SSR_PWMCLK7 (0x0Ful) // PWMCLK7 +#define CRG_MONCLK_SSR_UARTCLK (0x10ul) // UARTCLK +#define CRG_MONCLK_SSR_MII_RXCLK (0x11ul) // MII_RXCLK +#define CRG_MONCLK_SSR_MII_TXCLK (0x12ul) // MII_TXCLK +#define CRG_MONCLK_SSR_RTCCLK (0x13ul) // RTCCLK + +/******************************************************************************/ +/* */ +/* UART */ +/* */ +/******************************************************************************/ +/****************** Bit definition for UART Data(UARTDR) register *************************/ +#define UART_DR_OE (0x01ul << 11) // Overrun Error +#define UART_DR_BE (0x01ul << 10) // Break Error +#define UART_DR_PE (0x01ul << 9) // Parity Error +#define UART_DR_FE (0x01ul << 8) // Framing Error +//#define UART_DR_DR // ToDo +/***************** Bit definition for UART Receive Status(UARTRSR) register ***************/ +#define UARTR_SR_OE (0x01ul << 3) // Overrun Error +#define UARTR_SR_BE (0x01ul << 2) // Break Error +#define UARTR_SR_PE (0x01ul << 1) // Parity Error +#define UARTR_SR_FE (0x01ul << 0) // Framing Error +/***************** Bit definition for UART Error Clear(UARTECR) register ******************/ +#define UARTE_CR_OE (0x01ul << 3) // Overrun Error +#define UARTE_CR_BE (0x01ul << 2) // Break Error +#define UARTE_CR_PE (0x01ul << 1) // Parity Error +#define UARTE_CR_FE (0x01ul << 0) // Framing Error +/****************** Bit definition for UART Flags(UARTFR) register ************************/ +#define UART_FR_RI (0x01ul << 8) // Ring indicator +#define UART_FR_TXFE (0x01ul << 7) // Transmit FIFO empty +#define UART_FR_RXFF (0x01ul << 6) // Receive FIFO full +#define UART_FR_TXFF (0x01ul << 5) // Transmit FIFO full +#define UART_FR_RXFE (0x01ul << 4) // Receive FIFO empty +#define UART_FR_BUSY (0x01ul << 3) // UART busy +#define UART_FR_DCD (0x01ul << 2) // Data carrier detect +#define UART_FR_DSR (0x01ul << 1) // Data set ready +#define UART_FR_CTS (0x01ul << 0) // Clear to send +/********** Bit definition for UART Low-power Counter(UARTILPR) register *******************/ +#define UARTILPR_COUNTER (0xFFul << 0) // 8-bit low-power divisor value (0..255) +/********************* Bit definition for Line Control(UARTLCR_H) register *****************/ +#define UART_LCR_H_SPS (0x1ul << 7) // Stick parity select +#define UART_LCR_H_WLEN(n) ((n & 0x3ul) << 5) // Word length ( 0=5bits, 1=6bits, 2=7bits, 3=8bits ) +#define UART_LCR_H_FEN (0x1ul << 4) // Enable FIFOs +#define UART_LCR_H_STP2 (0x1ul << 3) // Two stop bits select +#define UART_LCR_H_EPS (0x1ul << 2) // Even parity select +#define UART_LCR_H_PEN (0x1ul << 1) // Parity enable +#define UART_LCR_H_BRK (0x1ul << 0) // Send break +/********************* Bit definition for Contro(UARTCR) register *************************/ +#define UART_CR_CTSEn (0x1ul << 15) // CTS hardware flow control enable +#define UART_CR_RTSEn (0x1ul << 14) // RTS hardware flow control enable +#define UART_CR_Out2 (0x1ul << 13) // Complement of Out2 modem status output +#define UART_CR_Out1 (0x1ul << 12) // Complement of Out1 modem status output +#define UART_CR_RTS (0x1ul << 11) // Request to send +#define UART_CR_DTR (0x1ul << 10) // Data transmit ready +#define UART_CR_RXE (0x1ul << 9) // Receive enable +#define UART_CR_TXE (0x1ul << 8) // Transmit enable +#define UART_CR_LBE (0x1ul << 7) // Loop-back enable +#define UART_CR_SIRLP (0x1ul << 2) // IrDA SIR low power mode +#define UART_CR_SIREN (0x1ul << 1) // SIR enable +#define UART_CR_UARTEN (0x1ul << 0) // UART enable +/******* Bit definition for Interrupt FIFO Level Select(UARTIFLS) register *****************/ +#define UART_IFLS_RXIFLSEL(n) ((n & 0x7ul) << 3) // Receive interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full) +#define UART_IFLS_TXIFLSEL(n) ((n & 0x7ul) << 0) // Transmit interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full) +/******* Bit definition for Interrupt Mask Set/Clear(UARTIMSC) register ********************/ +#define UART_IMSC_OEIM (0x1ul << 10) // Overrun error interrupt mask +#define UART_IMSC_BEIM (0x1ul << 9) // Break error interrupt mask +#define UART_IMSC_PEIM (0x1ul << 8) // Parity error interrupt mask +#define UART_IMSC_FEIM (0x1ul << 7) // Framing error interrupt mask +#define UART_IMSC_RTIM (0x1ul << 6) // Receive interrupt mask +#define UART_IMSC_TXIM (0x1ul << 5) // Transmit interrupt mask +#define UART_IMSC_RXIM (0x1ul << 4) // Receive interrupt mask +#define UART_IMSC_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt mask +#define UART_IMSC_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt mask +#define UART_IMSC_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt mask +#define UART_IMSC_RIMIM (0x1ul << 0) // nUARTRI modem interrupt mask +/*************** Bit definition for Raw Interrupt Status(UARTRIS) register *****************/ +#define UART_RIS_OEIM (0x1ul << 10) // Overrun error interrupt status +#define UART_RIS_BEIM (0x1ul << 9) // Break error interrupt status +#define UART_RIS_PEIM (0x1ul << 8) // Parity error interrupt status +#define UART_RIS_FEIM (0x1ul << 7) // Framing error interrupt status +#define UART_RIS_RTIM (0x1ul << 6) // Receive interrupt status +#define UART_RIS_TXIM (0x1ul << 5) // Transmit interrupt status +#define UART_RIS_RXIM (0x1ul << 4) // Receive interrupt status +#define UART_RIS_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt status +#define UART_RIS_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt status +#define UART_RIS_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt status +#define UART_RIS_RIMIM (0x1ul << 0) // nUARTRI modem interrupt status +/************** Bit definition for Masked Interrupt Status(UARTMIS) register ****************/ +#define UART_MIS_OEIM (0x1ul << 10) // Overrun error masked interrupt status +#define UART_MIS_BEIM (0x1ul << 9) // Break error masked interrupt status +#define UART_MIS_PEIM (0x1ul << 8) // Parity error masked interrupt status +#define UART_MIS_FEIM (0x1ul << 7) // Framing error masked interrupt status +#define UART_MIS_RTIM (0x1ul << 6) // Receive masked interrupt status +#define UART_MIS_TXIM (0x1ul << 5) // Transmit masked interrupt status +#define UART_MIS_RXIM (0x1ul << 4) // Receive masked interrupt status +#define UART_MIS_DSRMIM (0x1ul << 3) // nUARTDSR modem masked interrupt status +#define UART_MIS_DCDMIM (0x1ul << 2) // nUARTDCD modem masked interrupt status +#define UART_MIS_CTSMIM (0x1ul << 1) // nUARTCTS modem masked interrupt status +#define UART_MIS_RIMIM (0x1ul << 0) // nUARTRI modem masked interrupt status +/*************** Bit definition for Interrupt Clear(UARTICR) register ************************/ +#define UART_ICR_OEIM (0x1ul << 10) // Overrun error interrupt clear +#define UART_ICR_BEIM (0x1ul << 9) // Break error interrupt clear +#define UART_ICR_PEIM (0x1ul << 8) // Parity error interrupt clear +#define UART_ICR_FEIM (0x1ul << 7) // Framing error interrupt clear +#define UART_ICR_RTIM (0x1ul << 6) // Receive interrupt clear +#define UART_ICR_TXIM (0x1ul << 5) // Transmit interrupt clear +#define UART_ICR_RXIM (0x1ul << 4) // Receive interrupt clear +#define UART_ICR_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt clear +#define UART_ICR_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt clear +#define UART_ICR_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt clear +#define UART_ICR_RIMIM (0x1ul << 0) // nUARTRI modem interrupt clear +/***************** Bit definition for DMA Control(UARTDMACR) register ************************/ +#define UART_DMACR_DMAONERR (0x1ul << 2) // DMA on error +#define UART_DMACR_TXDMAE (0x1ul << 1) // Transmit DMA enable +#define UART_DMACR_RXDMAE (0x1ul << 0) // Receive DMA enable + +/******************************************************************************/ +/* */ +/* Simple UART */ +/* */ +/******************************************************************************/ +/***************** Bit definition for S_UART Data () register ************************/ +#define S_UART_DATA (0xFFul << 0) +/***************** Bit definition for S_UART State() register ************************/ +#define S_UART_STATE_TX_BUF_OVERRUN (0x01ul << 2) // TX buffer overrun, wirte 1 to clear. +#define S_UART_STATE_RX_BUF_FULL (0x01ul << 1) // RX buffer full, read only. +#define S_UART_STATE_TX_BUF_FULL (0x01ul << 0) // TX buffer full, read only. +/***************** Bit definition for S_UART Control() register ************************/ +#define S_UART_CTRL_HIGH_SPEED_TEST (0x01ul << 6) // High-speed test mode for TX only. +#define S_UART_CTRL_RX_OVERRUN_EN (0x01ul << 5) // RX overrun interrupt enable. +#define S_UART_CTRL_TX_OVERRUN_EN (0x01ul << 4) // TX overrun interrupt enable. +#define S_UART_CTRL_RX_INT_EN (0x01ul << 3) // RX interrupt enable. +#define S_UART_CTRL_TX_INT_EN (0x01ul << 2) // TX interrupt enable. +#define S_UART_CTRL_RX_EN (0x01ul << 1) // RX enable. +#define S_UART_CTRL_TX_EN (0x01ul << 0) // TX enable. +/***************** Bit definition for S_UART Interrupt() register ************************/ +#define S_UART_INT_RX_OVERRUN (0x01ul << 3) // RX overrun interrupt. Wirte 1 to clear +#define S_UART_INT_TX_OVERRUN (0x01ul << 2) // TX overrun interrupt. Write 1 to clear +#define S_UART_INT_RX (0x01ul << 1) // RX interrupt. Write 1 to clear +#define S_UART_INT_TX (0x01ul << 0) // TX interrupt. Write 1 to clear + +/******************************************************************************/ +/* */ +/* Analog Digital Register */ +/* */ +/******************************************************************************/ + +/*********************** Bit definition for ADC_CTR ***********************/ +//#define ADC_CTR_SAMSEL_ABNORMAL (0x0ul) // Abnormal Operation +//#define ADC_CTR_SAMSEL_NORMAL (0x1ul) // Normal Operation +#define ADC_CTR_PWD_NRMOP (0x1ul) // Active Operation +#define ADC_CTR_PWD_PD (0x3ul) // Power down +/*********************** Bit definition for ADC_CHSEL ***********************/ +#define ADC_CHSEL_CH0 (0x0ul) // Channel 0 +#define ADC_CHSEL_CH1 (0x1ul) // Channel 1 +#define ADC_CHSEL_CH2 (0x2ul) // Channel 2 +#define ADC_CHSEL_CH3 (0x3ul) // Channel 3 +#define ADC_CHSEL_CH4 (0x4ul) // Channel 4 +#define ADC_CHSEL_CH5 (0x5ul) // Channel 5 +#define ADC_CHSEL_CH6 (0x6ul) // Channel 6 +#define ADC_CHSEL_CH7 (0x7ul) // Channel 7 +#define ADC_CHSEL_CH15 (0xful) // LDO output(1.5V) +/*********************** Bit definition for ADC_START ***********************/ +#define ADC_START_START (0x1ul) // ADC conversion start +/*********************** Bit definition for ADC_DATA ***********************/ +//ToDo (Readonly) + +/*********************** Bit definition for ADC_INT ***********************/ +#define ADC_INT_MASK_DIS (0x0ul << 1) // Interrupt disable +#define ADC_INT_MASK_ENA (0x1ul << 1) // Interrupt enable +//ToDo (Readonly) + +/*********************** Bit definition for ADC_INTCLR ***********************/ +#define ADC_INTCLEAR (0x1ul) // ADC Interrupt clear + +#define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL) +#define ADC ((ADC_TypeDef *) W7500x_ADC_BASE) + +/******************************************************************************/ +/* */ +/* Dual Timer */ +/* */ +/******************************************************************************/ + +/*********************** Bit definition for dualtimer ***********************/ +#define DUALTIMER_TimerControl_TimerDIsable (0x0ul << 7) +#define DUALTIMER_TimerControl_TimerEnable (0x1ul << 7) +#define DUALTIMER_TimerControl_FreeRunning (0x0ul << 6) +#define DUALTIMER_TimerControl_Periodic (0x1ul << 6) +#define DUALTIMER_TimerControl_IntDisable (0x0ul << 5) +#define DUALTIMER_TimerControl_IntEnable (0x1ul << 5) +#define DUALTIMER_TimerControl_Pre_1 (0x0ul << 2) +#define DUALTIMER_TimerControl_Pre_16 (0x1ul << 2) +#define DUALTIMER_TimerControl_Pre_256 (0x2ul << 2) +#define DUALTIMER_TimerControl_Size_16 (0x0ul << 1) +#define DUALTIMER_TimerControl_Size_32 (0x1ul << 1) +#define DUALTIMER_TimerControl_Wrapping (0x0ul << 0) +#define DUALTIMER_TimerControl_OneShot (0x1ul << 0) + +/******************************************************************************/ +/* */ +/* External Interrupt */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for Px_IER **************************/ +#define EXTI_Px_INTPOR_RISING_EDGE (0x00ul << 0) +#define EXTI_Px_INTPOR_FALLING_EDGE (0x01ul << 0) +#define EXTI_Px_INTEN_DISABLE (0x00ul << 1) +#define EXTI_Px_INTEN_ENABLE (0x01ul << 1) + +/******************************************************************************/ +/* */ +/* GPIO */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for Px_AFSR **************************/ +#define Px_AFSR_AF0 (0x00ul) +#define Px_AFSR_AF1 (0x01ul) +#define Px_AFSR_AF2 (0x02ul) +#define Px_AFSR_AF3 (0x03ul) +/**************** Bit definition for Px_PCR **************************/ +#define Px_PCR_PUPD_DOWN (0x01ul << 0) // Pull Down +#define Px_PCR_PUPD_UP (0x01ul << 1) // Pull Up +#define Px_PCR_DS_HIGH (0x01ul << 2) // High Driving +#define Px_PCR_OD (0x01ul << 3) // Open Drain +#define Px_PCR_IE (0x01ul << 5) // Input Buffer Enable +#define Px_PCR_CS_SUMMIT (0x01ul << 6) // Use Summit Trigger Input Buffer + +/******************************************************************************/ +/* */ +/* I2C */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for I2C_CTR **************************/ +#define I2C_CTR_COREEN (0x01ul << 7 ) // 0x80 +#define I2C_CTR_INTEREN (0x01ul << 6 ) // 0x40 +#define I2C_CTR_MODE (0x01ul << 5 ) // 0x20 +#define I2C_CTR_ADDR10 (0x01ul << 4 ) // 0x10 +#define I2C_CTR_CTRRWN (0x01ul << 3 ) // 0x08 +#define I2C_CTR_CTEN (0x01ul << 2 ) // 0x04 + +/**************** Bit definition for I2C_CMDR **************************/ +#define I2C_CMDR_STA (0x01ul << 7 ) // 0x80 +#define I2C_CMDR_STO (0x01ul << 6 ) // 0x40 +#define I2C_CMDR_ACK (0x01ul << 5 ) // 0x20 +#define I2C_CMDR_RESTA (0x01ul << 4 ) // 0x10 + +/**************** Bit definition for I2C_ISCR **************************/ +#define I2C_ISCR_RST (0x01ul << 1) // 0x01 + +/**************** Bit definition for I2C_SR **************************/ +#define I2C_SR_TX (0x01ul << 9 ) // 0x200 +#define I2C_SR_RX (0x01ul << 8 ) // 0x100 +#define I2C_SR_ACKT (0x01ul << 7 ) // 0x080 +#define I2C_SR_BT (0x01ul << 6 ) // 0x040 +#define I2C_SR_SA (0x01ul << 5 ) // 0x020 +#define I2C_SR_SB (0x01ul << 4 ) // 0x010 +#define I2C_SR_AL (0x01ul << 3 ) // 0x008 +#define I2C_SR_TO (0x01ul << 2 ) // 0x004 +#define I2C_SR_SRW (0x01ul << 1 ) // 0x002 +#define I2C_SR_ACKR (0x01ul << 0 ) // 0x001 + +/**************** Bit definition for I2C_ISR **************************/ +#define I2C_ISR_STAE (0x01ul << 4 ) // 0x010 +#define I2C_ISR_STOE (0x01ul << 3 ) // 0x008 +#define I2C_ISR_TOE (0x01ul << 2 ) // 0x004 +#define I2C_ISR_ACK_RXE (0x01ul << 1 ) // 0x002 +#define I2C_ISR_ACK_TXE (0x01ul << 0 ) // 0x001 + +/**************** Bit definition for I2C_ISMR **************************/ +#define I2C_ISR_STAEM (0x01ul << 4 ) // 0x010 +#define I2C_ISR_STOEM (0x01ul << 3 ) // 0x008 +#define I2C_ISR_TOEM (0x01ul << 2 ) // 0x004 +#define I2C_ISR_ACK_RXEM (0x01ul << 1 ) // 0x002 +#define I2C_ISR_ACK_TXEM (0x01ul << 0 ) // 0x001 + +/******************************************************************************/ +/* */ +/* PWM */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Random number generator Register */ +/* */ +/******************************************************************************/ + +/*********************** Bit definition for RNG_RUN ***********************/ +#define RNG_RUN_STOP (0x0ul) // STOP RNG shift register +#define RNG_RUN_RUN (0x1ul) // RUN RNG shift register +/*********************** Bit definition for RNG_SEED ***********************/ +//ToDo + +/*********************** Bit definition for RNG_CLKSEL ***********************/ +#define RNG_CLKSEL_RNGCLK (0x0ul) // RNGCLK is source clock for rng shift register +#define RNG_CLKSEL_APBCLK (0x1ul) // APBCLK is source clock for rng shift register +/*********************** Bit definition for RNG_ENABLE ***********************/ +#define RNG_MANUAL_DISABLE (0x0ul) // RNG disble +#define RNG_MANUAL_ENABLE (0x1ul) // RNG enable +/*********************** Bit definition for RNG_RN ***********************/ +//ToDo + +/*********************** Bit definition for RNG_POLY ***********************/ +//ToDo + + + +#if !defined (USE_HAL_DRIVER) +#define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + + + +#if defined (USE_HAL_DRIVER) + #include "W7500x_conf.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* W7500x_H */ + + + +/************************ (C) COPYRIGHT Wiznet *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis.h new file mode 100644 index 0000000000..59a30a998a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "W7500x.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.c new file mode 100644 index 0000000000..71da98cf15 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.c @@ -0,0 +1,47 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash + + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS; + + vectors[IRQn + 16] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + // Return the vector + return vectors[IRQn + 16]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.h new file mode 100644 index 0000000000..3d1e0ed80f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.h @@ -0,0 +1,51 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS 41 +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.c b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.c new file mode 100644 index 0000000000..46193b12b0 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.c @@ -0,0 +1,104 @@ +/**************************************************************************//** + * @file system_CMSDK_CM0.c + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for + * Device CMSDK + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2010-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#include "system_W7500x.h" + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ +//#define SYSCLK_EXTERN_OSC + + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemFrequency = 0; /*!< System Clock Frequency (Core Clock) */ +uint32_t SystemCoreClock = 0; /*!< Processor Clock Frequency */ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + uint8_t M,N,OD; + +#ifdef SYSCLK_EXTERN_OSC + CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK; +#else + CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK; +#endif + OD = (1 << (CRG->PLL_FCR & 0x01)) * (1 << ((CRG->PLL_FCR & 0x02) >> 1)); + N = (CRG->PLL_FCR >> 8 ) & 0x3F; + M = (CRG->PLL_FCR >> 16) & 0x3F; + +#ifdef SYSCLK_EXTERN_OSC + SystemCoreClock = EXTERN_XTAL * M / N * 1 / OD; +#else + SystemCoreClock = INTERN_XTAL * M / N * 1 / OD; +#endif +} + +uint32_t GetSystemClock() +{ + return SystemCoreClock; +} + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + uint8_t M,N,OD; + + (*((volatile uint32_t *)(W7500x_TRIM_BGT))) = (*((volatile uint32_t *)(W7500x_INFO_BGT))); + (*((volatile uint32_t *)(W7500x_TRIM_OSC))) = (*((volatile uint32_t *)(W7500x_INFO_OSC))); + + + // Set PLL input frequency +#ifdef SYSCLK_EXTERN_OSC + CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK; +#else + CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK; +#endif + OD = (1 << (CRG->PLL_FCR & 0x01)) * (1 << ((CRG->PLL_FCR & 0x02) >> 1)); + N = (CRG->PLL_FCR >> 8 ) & 0x3F; + M = (CRG->PLL_FCR >> 16) & 0x3F; + +#ifdef SYSCLK_EXTERN_OSC + SystemCoreClock = EXTERN_XTAL * M / N * 1 / OD; +#else + SystemCoreClock = INTERN_XTAL * M / N * 1 / OD; +#endif +} diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.h new file mode 100644 index 0000000000..74af23d9d8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.h @@ -0,0 +1,84 @@ +/**************************************************************************//** + * @file system_W7500x.h + * @brief CMSIS Cortex-M# Device Peripheral Access Layer Header File for + * Device W7500x + * @version V3.10 + * @date 23. November 2012 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef SYSTEM_W7500x_H /* ToDo: replace '' with your device name */ +#define SYSTEM_W7500x_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "W7500x.h" + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t GetSystemClock(void); /*!< Get System Clock Frequency */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define EXTERN_XTAL (8000000UL) /* External Oscillator Frequency */ +#define INTERN_XTAL (8000000UL) /* Internal Oscillator Frequency */ + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_W7500x_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.c b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.c new file mode 100644 index 0000000000..cd473752b5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.c @@ -0,0 +1,54 @@ +#include "W7500x.h" + +void ADC_PowerDownEnable (FunctionalState NewState) +{ + if (NewState != DISABLE) ADC->ADC_CTR = ADC_CTR_PWD_PD; + else ADC->ADC_CTR = ADC_CTR_PWD_NRMOP; +} + +void ADC_ChannelSelect (ADC_CH num) +{ + assert_param(IS_ADC_CH_NUM(num)); + ADC->ADC_CHSEL = num; +} + +void ADC_Start (void) +{ + ADC->ADC_START = ADC_START_START; +} + +uint16_t ADC_ReadData (void) +{ + return ((uint16_t)ADC->ADC_DATA); +} + +void ADC_InterruptMask (FunctionalState NewState) +{ + if (NewState != DISABLE) ADC->ADC_INT = ADC_INT_MASK_ENA; + else ADC->ADC_INT = ADC_INT_MASK_DIS; +} + +uint8_t ADC_IsInterrupt (void) +{ + return (((uint8_t)ADC->ADC_INT && 0x01ul)); +} + +void ADC_InterruptClear (void) +{ + ADC->ADC_INT = ADC_INTCLEAR; +} + +void ADC_Init (void) +{ + // ADC_CLK on + ADC_PowerDownEnable(DISABLE); + //ADC_ChannelSelect(num); +} + +void ADC_DeInit (void) +{ + // ADC_CLK off + ADC_PowerDownEnable(ENABLE); + ADC_InterruptMask(DISABLE); +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.h new file mode 100644 index 0000000000..7985370e33 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.h @@ -0,0 +1,59 @@ +/** + ****************************************************************************** + * @file + * @author + * @version + * @date + * @brief This file contains all the functions prototypes for the ADC + * firmware library. + ****************************************************************************** + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __W7500X_ADC_H +#define __W7500X_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "W7500x.h" + +typedef enum { ADC_CH0 = 0, + ADC_CH1 = 1, + ADC_CH2 = 2, + ADC_CH3 = 3, + ADC_CH4 = 4, + ADC_CH5 = 5, + ADC_CH6 = 6, + ADC_CH7 = 7, + ADC_CH15 = 15} ADC_CH; + +#define IS_ADC_CH_NUM(NUM) (((NUM) == ADC_CH0) || \ + ((NUM) == ADC_CH1) || \ + ((NUM) == ADC_CH2) || \ + ((NUM) == ADC_CH3) || \ + ((NUM) == ADC_CH4) || \ + ((NUM) == ADC_CH5) || \ + ((NUM) == ADC_CH6) || \ + ((NUM) == ADC_CH7) || \ + ((NUM) == ADC_CH15)) + +void ADC_Init(void); +void ADC_DeInit(void); +void ADC_PowerDownEnable (FunctionalState NewState); +void ADC_ChannelSelect (ADC_CH num); +void ADC_Start (void); +uint16_t ADC_ReadData (void); +void ADC_InterruptMask (FunctionalState NewState); +uint8_t ADC_IsInterrupt (void); +void ADC_InterruptClear (void); + +#ifdef __cplusplus + } +#endif + +#endif //__W7500X_ADC_H diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_conf.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_conf.h new file mode 100644 index 0000000000..cbc6929c1a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_conf.h @@ -0,0 +1,15 @@ +#include "W7500x_gpio.h" +#include "W7500x_exti.h" +#include "W7500x_pwm.h" +#include "W7500x_uart.h" +#include "W7500x_i2c.h" +#include "W7500x_adc.h" +#include "system_W7500x.h" + + +#ifdef USE_FULL_ASSERT + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__,__LINE__)) +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.c b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.c new file mode 100644 index 0000000000..f533e1d2ba --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.c @@ -0,0 +1,276 @@ +#include "W7500x_crg.h" + +void CRG_DeInit(void) +{ +//To Do +} + +void CRG_OSC_PowerDownEnable(FunctionalState NewState) +{ + if(NewState != DISABLE) CRG->OSC_PDR = CRG_OSC_PDR_PD; + else CRG->OSC_PDR = CRG_OSC_PDR_NRMLOP; +} + +void CRG_PLL_PowerDownEnable(FunctionalState NewState) +{ + if(NewState != DISABLE) CRG->PLL_PDR = CRG_PLL_PDR_PD; + else CRG->PLL_PDR = CRG_PLL_PDR_NRMLOP; +} + +void CRG_PLL_OutputEnable(FunctionalState NewState) +{ + if(NewState != DISABLE) CRG->PLL_OER = CRG_PLL_OER_EN; + else CRG->PLL_OER = CRG_PLL_OER_DIS; +} + +void CRG_PLL_BypassEnable(FunctionalState NewState) +{ + if(NewState != DISABLE) CRG->PLL_BPR = CRG_PLL_BPR_EN; + else CRG->PLL_BPR = CRG_PLL_BPR_DIS; +} + +void CRG_PLL_InputFrequencySelect(CRG_CLK_SOURCE src) +{ + assert_param(IS_CRG_PLL_SRC(src)); + + if( src == CRG_RCLK ) CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK; + else CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK; +} + +void CRG_FCLK_SourceSelect(CRG_CLK_SOURCE src) +{ + assert_param(IS_CRG_FCLK_SRC(src)); + + if ( src == CRG_RCLK ) CRG->FCLK_SSR = CRG_FCLK_SSR_RCLK; + else if ( src == CRG_OCLK ) CRG->FCLK_SSR = CRG_FCLK_SSR_OCLK; + else CRG->FCLK_SSR = CRG_FCLK_SSR_MCLK; +} + +void CRG_FCLK_SetPrescale(CRG_PREDIV prediv) +{ + assert_param(IS_CRG_FCLK_PREDIV(prediv)); + + if ( prediv == CRG_PREDIV1 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV1; + else if ( prediv == CRG_PREDIV2 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV2; + else if ( prediv == CRG_PREDIV4 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV4; + else CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV8; +} + +void CRG_SSPCLK_SourceSelect(CRG_CLK_SOURCE src) +{ + assert_param(IS_CRG_SSPCLK_SRC(src)); + + if ( src == CRG_CLK_DIS ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_DIS; + else if ( src == CRG_MCLK ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK; + else if ( src == CRG_RCLK ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_RCLK; + else CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_OCLK; +} + +void CRG_SSPCLK_SetPrescale(CRG_PREDIV prediv) +{ + assert_param(IS_CRG_SSPCLK_PREDIV(prediv)); + + if ( prediv == CRG_PREDIV1 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1; + else if ( prediv == CRG_PREDIV2 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV2; + else if ( prediv == CRG_PREDIV4 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV4; + else CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV8; +} + +void CRG_ADCCLK_SourceSelect(CRG_CLK_SOURCE src) +{ + assert_param(IS_CRG_ADCCLK_SRC(src)); + + if ( src == CRG_CLK_DIS ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_DIS; + else if ( src == CRG_MCLK ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_MCLK; + else if ( src == CRG_RCLK ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_RCLK; + else CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_OCLK; +} + +void CRG_ADCCLK_SetPrescale(CRG_PREDIV prediv) +{ + assert_param(IS_CRG_ADCCLK_PREDIV(prediv)); + + if ( prediv == CRG_PREDIV1 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV1; + else if ( prediv == CRG_PREDIV2 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV2; + else if ( prediv == CRG_PREDIV4 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV4; + else CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV8; +} + +void CRG_TIMERCLK_SourceSelect(CRG_TIMER num, CRG_CLK_SOURCE src) +{ + assert_param(IS_CRG_TIMERCLK_NUM(num)); + assert_param(IS_CRG_TIMERCLK_SRC(src)); + + if ( src == CRG_CLK_DIS ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_DIS); + else if ( src == CRG_MCLK ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_MCLK); + else if ( src == CRG_RCLK ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_RCLK); + else CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_OCLK); +} + +void CRG_TIMERCLK_SetPrescale(CRG_TIMER num, CRG_PREDIV prediv) +{ + assert_param(IS_CRG_TIMERCLK_NUM(num)); + assert_param(IS_CRG_TIMERCLK_PREDIV(prediv)); + + if ( prediv == CRG_PREDIV1 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV1); + else if ( prediv == CRG_PREDIV2 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV2); + else if ( prediv == CRG_PREDIV4 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV4); + else if ( prediv == CRG_PREDIV8 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV8); + else if ( prediv == CRG_PREDIV16 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV16); + else if ( prediv == CRG_PREDIV32 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV32); + else if ( prediv == CRG_PREDIV64 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV64); + else CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV128); +} + +void CRG_PWMCLK_SourceSelect(CRG_PWM num, CRG_CLK_SOURCE src) +{ + assert_param(IS_CRG_PWMCLK_NUM(num)); + assert_param(IS_CRG_PWMCLK_SRC(src)); + + if ( src == CRG_CLK_DIS ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_DIS); + else if ( src == CRG_MCLK ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_MCLK); + else if ( src == CRG_RCLK ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_RCLK); + else CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_OCLK); +} + +void CRG_PWMCLK_SetPrescale(CRG_PWM num, CRG_PREDIV prediv) +{ + assert_param(IS_CRG_PWMCLK_NUM(num)); + assert_param(IS_CRG_PWMCLK_PREDIV(prediv)); + + if ( prediv == CRG_PREDIV1 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV1); + else if ( prediv == CRG_PREDIV2 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV2); + else if ( prediv == CRG_PREDIV4 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV4); + else if ( prediv == CRG_PREDIV8 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV8); + else if ( prediv == CRG_PREDIV16 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV16); + else if ( prediv == CRG_PREDIV32 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV32); + else if ( prediv == CRG_PREDIV64 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV64); + else CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV128); +} + +void CRG_RTC_HS_SourceSelect(CRG_CLK_SOURCE src) +{ + assert_param(IS_CRG_RTC_HS_SRC(src)); + + if ( src == CRG_CLK_DIS ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_DIS; + else if ( src == CRG_MCLK ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_MCLK; + else if ( src == CRG_RCLK ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_RCLK; + else CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_OCLK; + + if ( src != CRG_CLK_DIS ) CRG_RTC_SourceSelect(CRG_CLK_HIGH); +} + +void CRG_RTC_HS_SetPrescale(CRG_PREDIV prediv) +{ + assert_param(IS_CRG_RTC_HS_PREDIV(prediv)); + + if ( prediv == CRG_PREDIV1 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV1; + else if ( prediv == CRG_PREDIV2 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV2; + else if ( prediv == CRG_PREDIV4 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV4; + else if ( prediv == CRG_PREDIV8 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV8; + else if ( prediv == CRG_PREDIV16 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV16; + else if ( prediv == CRG_PREDIV32 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV32; + else if ( prediv == CRG_PREDIV64 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV64; + else CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV128; +} + +void CRG_RTC_SourceSelect(CRG_CLK_LOW_SOURCE src) +{ + assert_param(IS_CRG_RTC_LOW_SRC(src)); + + if (src == CRG_CLK_LOW) + { + CRG_RTC_HS_SourceSelect(CRG_CLK_DIS); + CRG->RTC_SSR = CRG_RTC_SSR_LW; + } + else + { + CRG->RTC_SSR = CRG_RTC_SSR_HS; + } +} + +void CRG_WDOGCLK_HS_SourceSelect(CRG_CLK_SOURCE src) +{ + assert_param(IS_CRG_WDOGCLK_HS_SRC(src)); + + if ( src == CRG_CLK_DIS ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_DIS; + else if ( src == CRG_MCLK ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_MCLK; + else if ( src == CRG_RCLK ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_RCLK; + else CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_OCLK; + + if ( src != CRG_CLK_DIS ) CRG_WDOGCLK_SourceSelect(CRG_CLK_HIGH); +} + +void CRG_WDOGCLK_HS_SetPrescale(CRG_PREDIV prediv) +{ + assert_param(IS_CRG_WDOGCLK_HS_PREDIV(prediv)); + + if ( prediv == CRG_PREDIV1 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV1; + else if ( prediv == CRG_PREDIV2 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV2; + else if ( prediv == CRG_PREDIV4 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV4; + else if ( prediv == CRG_PREDIV8 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV8; + else if ( prediv == CRG_PREDIV16 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV16; + else if ( prediv == CRG_PREDIV32 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV32; + else if ( prediv == CRG_PREDIV64 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV64; + else CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV128; +} + +void CRG_WDOGCLK_SourceSelect(CRG_CLK_LOW_SOURCE src) +{ + assert_param(IS_CRG_WDOGCLK_LOW_SRC(src)); + + if (src == CRG_CLK_LOW) + { + CRG_WDOGCLK_HS_SourceSelect(CRG_CLK_DIS); + CRG->WDOGCLK_SSR = CRG_WDOGCLK_SSR_LW; + } + else + { + CRG->WDOGCLK_SSR = CRG_WDOGCLK_SSR_HS; + } +} + +void CRG_UARTCLK_SourceSelect(CRG_CLK_SOURCE src) +{ + assert_param(IS_CRG_UARTCLK_SRC(src)); + + if ( src == CRG_CLK_DIS ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_DIS; + else if ( src == CRG_MCLK ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_MCLK; + else if ( src == CRG_RCLK ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_RCLK; + else CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_OCLK; +} + +void CRG_UARTCLK_SetPrescale(CRG_PREDIV prediv) +{ + assert_param(IS_CRG_UARTCLK_PREDIV(prediv)); + + if ( prediv == CRG_PREDIV1 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV1; + else if ( prediv == CRG_PREDIV2 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV2; + else if ( prediv == CRG_PREDIV4 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV4; + else CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV8; +} + +void CRG_MII_Enable(FunctionalState rx_clk, FunctionalState tx_clk) +{ + assert_param(IS_FUNCTIONAL_STATE(rx_clk)); + assert_param(IS_FUNCTIONAL_STATE(tx_clk)); + + if ( rx_clk != DISABLE ) CRG->MIICLK_ECR |= CRG_MIICLK_ECR_EN_RXCLK; + else CRG->MIICLK_ECR &= ~(CRG_MIICLK_ECR_EN_RXCLK); + + if ( tx_clk != DISABLE ) CRG->MIICLK_ECR |= CRG_MIICLK_ECR_EN_TXCLK; + else CRG->MIICLK_ECR &= ~(CRG_MIICLK_ECR_EN_TXCLK); +} + +void CRG_SetMonitoringClock(uint32_t value) +{ + assert_param(IS_CRG_MONCLK_SSR(value)); + + CRG->MONCLK_SSR = value; +} + +uint32_t CRG_GetMonitoringClock(void) +{ + return (uint8_t)CRG->MONCLK_SSR; +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.h new file mode 100644 index 0000000000..28a60d1e45 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.h @@ -0,0 +1,145 @@ +/** + ****************************************************************************** + * @file + * @author + * @version + * @date + * @brief This file contains all the functions prototypes for the Clock Reset Generator + * firmware library. + ****************************************************************************** + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __W7500X_CRG_H +#define __W7500X_CRG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "W7500x.h" + +// It will be in W7500x_crg.h +typedef enum { CRG_CLK_DIS = 0, CRG_MCLK, CRG_RCLK, CRG_OCLK } CRG_CLK_SOURCE; +typedef enum { CRG_CLK_HIGH = 0, CRG_CLK_LOW } CRG_CLK_LOW_SOURCE; +typedef enum { CRG_PREDIV1 = 0, CRG_PREDIV2, CRG_PREDIV4, CRG_PREDIV8, CRG_PREDIV16, \ + CRG_PREDIV32, CRG_PREDIV64, CRG_PREDIV128 } CRG_PREDIV; +typedef enum { CRG_TIMER0 = 0, CRG_TIMER1 } CRG_TIMER; +typedef enum { CRG_PWM0 = 0, CRG_PWM1, CRG_PWM2, CRG_PWM3, CRG_PWM4, CRG_PWM5, CRG_PWM6, CRG_PWM7 } CRG_PWM; + + + +#define IS_CRG_PLL_SRC(SRC) (((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK)) +#define IS_CRG_FCLK_SRC(SRC) (((SRC) == CRG_MCLK) || ((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK)) + +#define CRG_CLK_SRC_DEFAULT(SRC) (((SRC) == CRG_CLK_DIS) || ((SRC) == CRG_MCLK) || \ + ((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK)) +#define CRG_CLK_SRC_LOW(SRC) (((SRC) == CRG_CLK_HIGH) || ((SRC) == CRG_CLK_LOW)) + +#define CRG_CLK_PREDIV_DEFAULT(DIV) (((DIV) == CRG_PREDIV1) || ((DIV) == CRG_PREDIV2) || \ + ((DIV) == CRG_PREDIV4) || ((DIV) == CRG_PREDIV8)) +#define CRG_CLK_PREDIV_ADVANCE(DIV) (((DIV) == CRG_PREDIV1) || ((DIV) == CRG_PREDIV2) || \ + ((DIV) == CRG_PREDIV4) || ((DIV) == CRG_PREDIV8) || \ + ((DIV) == CRG_PREDIV16) || ((DIV) == CRG_PREDIV32) || \ + ((DIV) == CRG_PREDIV64) || ((DIV) == CRG_PREDIV128)) + + +#define IS_CRG_FCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV) + +#define IS_CRG_SSPCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) +#define IS_CRG_SSPCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV) + +#define IS_CRG_ADCCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV) +#define IS_CRG_ADCCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) + + + + + +#define IS_CRG_TIMERCLK_NUM(NUM) (((NUM) == CRG_TIMER0) || ((NUM) == CRG_TIMER1)) +#define IS_CRG_TIMERCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) +#define IS_CRG_TIMERCLK_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV) + +#define CRG_SET_TIMERCLK_SSR(NUM,VALUE) \ + (*((volatile uint32_t *)(CRG->TIMER0CLK_SSR) + (0x10ul * NUM)) = VALUE) +#define CRG_SET_TIMERCLK_PREDIV(NUM,VALUE) \ + (*((volatile uint32_t *)(CRG->TIMER0CLK_PVSR) + (0x10ul * NUM)) = VALUE) +//#define CRG_SET_TIMERCLK_SSR(num,value) CRG->TIMER##num##CLK_SSR = value +//#define CRG_SET_TIMERCLK_PREDIV(num,value) CRG->TIMER##num##CLK_PVSR = value + + +#define IS_CRG_PWMCLK_NUM(NUM) (((NUM) == CRG_PWM0) || ((NUM) == CRG_PWM1) || \ + ((NUM) == CRG_PWM2) || ((NUM) == CRG_PWM3) || \ + ((NUM) == CRG_PWM4) || ((NUM) == CRG_PWM5) || \ + ((NUM) == CRG_PWM6) || ((NUM) == CRG_PWM7) ) +#define IS_CRG_PWMCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) +#define IS_CRG_PWMCLK_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV) + +#define CRG_SET_PWMCLK_SSR(NUM,VALUE) \ + (*((volatile uint32_t *)(CRG->PWM0CLK_SSR) + (0x10ul * NUM)) = VALUE) +#define CRG_SET_PWMCLK_PREDIV(NUM,VALUE) \ + (*((volatile uint32_t *)(CRG->PWM0CLK_PVSR) + (0x10ul * NUM)) = VALUE) +//#define CRG_SET_PWMCLK_SSR(num,value) CRG->PWM##num##CLK_SSR = value +//#define CRG_SET_PWMCLK_PREDIV(num,value) CRG->PWM##num##CLK_PVSR = value + +#define IS_CRG_RTC_HS_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) +#define IS_CRG_RTC_HS_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV) +#define IS_CRG_RTC_LOW_SRC(SRC) CRG_CLK_SRC_LOW(SRC) + +#define IS_CRG_WDOGCLK_HS_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) +#define IS_CRG_WDOGCLK_HS_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV) +#define IS_CRG_WDOGCLK_LOW_SRC(SRC) CRG_CLK_SRC_LOW(SRC) + +#define IS_CRG_UARTCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) +#define IS_CRG_UARTCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV) + +#define IS_CRG_MONCLK_SSR(value) (((value) >= 0x00ul) || ((value) <= 0x13ul)) + +void CRG_DeInit(void); +void CRG_OSC_PowerDownEnable (FunctionalState NewState); +void CRG_PLL_PowerDownEnable (FunctionalState NewState); +void CRG_PLL_OutputEnable (FunctionalState NewState); +void CRG_PLL_BypassEnable (FunctionalState NewState); +void CRG_PLL_InputFrequencySelect (CRG_CLK_SOURCE src); + +void CRG_FCLK_SourceSelect (CRG_CLK_SOURCE src); +void CRG_FCLK_SetPrescale (CRG_PREDIV prediv); + +void CRG_SSPCLK_SourceSelect (CRG_CLK_SOURCE src); +void CRG_SSPCLK_SetPrescale (CRG_PREDIV prediv); + +void CRG_ADCCLK_SourceSelect (CRG_CLK_SOURCE src); +void CRG_ADCCLK_SetPrescale (CRG_PREDIV prediv); + +void CRG_TIMERCLK_SourceSelect (CRG_TIMER num, CRG_CLK_SOURCE src); +void CRG_TIMERCLK_SetPrescale (CRG_TIMER num, CRG_PREDIV prediv); + +void CRG_PWMCLK_SourceSelect (CRG_PWM num, CRG_CLK_SOURCE src); +void CRG_PWMCLK_SetPrescale (CRG_PWM num, CRG_PREDIV prediv); + +void CRG_RTC_HS_SourceSelect (CRG_CLK_SOURCE src); +void CRG_RTC_HS_SetPrescale (CRG_PREDIV prediv); +void CRG_RTC_SourceSelect (CRG_CLK_LOW_SOURCE src); + +void CRG_WDOGCLK_HS_SourceSelect (CRG_CLK_SOURCE src); +void CRG_WDOGCLK_HS_SetPrescale (CRG_PREDIV prediv); +void CRG_WDOGCLK_SourceSelect (CRG_CLK_LOW_SOURCE src); + +void CRG_UARTCLK_SourceSelect (CRG_CLK_SOURCE src); +void CRG_UARTCLK_SetPrescale (CRG_PREDIV prediv); + +void CRG_MII_Enable (FunctionalState rx_clk, FunctionalState tx_clk); + +void CRG_SetMonitoringClock (uint32_t value); +uint32_t CRG_GetMonitoringClock (void); + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_exti.c b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_exti.c new file mode 100644 index 0000000000..ab6b1e4948 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_exti.c @@ -0,0 +1,157 @@ +#include "W7500x.h" + + + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset values. + * @param None + * @retval None + */ +void EXTI_DeInit(void) +{ + uint32_t i, loop =16; + for(i=0; iPort[i] = 0x00; + EXTI_PB->Port[i] = 0x00; + EXTI_PC->Port[i] = 0x00; + } + for(i=0; i<5; i++) + { + EXTI_PD->Port[i] = 0x00; + } +} + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * that contains the configuration information for the EXTI peripheral. + * @retval None + */ +void EXTI_Init(PAD_Type Px, EXTI_InitTypeDef* EXTI_InitStruct) +{ + uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16; + P_Port_Def *px_exti; + + assert_param(IS_PAD_TYPE(Px)); + + if (Px == PAD_PA) px_exti = EXTI_PA; + else if (Px == PAD_PB) px_exti = EXTI_PB; + else if (Px == PAD_PC) px_exti = EXTI_PC; + else + { + px_exti = (P_Port_Def*)EXTI_PD; + loop = 5; + } + + for(pinpos = 0x00; pinpos < loop; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + + currentpin = (EXTI_InitStruct->EXTI_Line) & pos; + if(currentpin == pos) + { + px_exti->Port[pinpos] |= EXTI_Px_INTEN_ENABLE; + + if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising) + px_exti->Port[pinpos] |= EXTI_Px_INTPOR_RISING_EDGE; + else + px_exti->Port[pinpos] |= EXTI_Px_INTPOR_FALLING_EDGE; + } + } + +} + +void EXTI_Polarity_Set(PAD_Type Px, uint16_t GPIO_Pin, uint16_t Polarity ) +{ + uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16; + P_Port_Def *px_exti; + + assert_param(IS_PAD_TYPE(Px)); + + if (Px == PAD_PA) px_exti = EXTI_PA; + else if (Px == PAD_PB) px_exti = EXTI_PB; + else if (Px == PAD_PC) px_exti = EXTI_PC; + else + { + px_exti = (P_Port_Def*)EXTI_PD; + loop = 5; + } + + for(pinpos = 0x00; pinpos < loop; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + + currentpin = GPIO_Pin & pos; + if(currentpin == pos) + { + if(Polarity == EXTI_Trigger_Rising) + px_exti->Port[pinpos] |= EXTI_Px_INTPOR_RISING_EDGE; + else + px_exti->Port[pinpos] |= EXTI_Px_INTPOR_FALLING_EDGE; + } + } + +} + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = 0xFF; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; +} + +uint16_t EXTI_Px_GetEXTEN(PAD_Type Px) +{ + uint32_t i, loop = 16; + uint16_t ret=0; + P_Port_Def *px_exti; + + assert_param(IS_PAD_TYPE(Px)); + + if (Px == PAD_PA) px_exti = EXTI_PA; + else if (Px == PAD_PB) px_exti = EXTI_PB; + else if (Px == PAD_PC) px_exti = EXTI_PC; + else + { + px_exti = (P_Port_Def*)EXTI_PD; + loop = 5; + } + + for(i = 0x00; i < loop; i++) + { + ret |= (((px_exti->Port[i]&0x2)>>1)<Port[i]&0x1)<DATA = 0x0000; + GPIOx->DATAOUT = 0x0000; + //GPIOx->OUTENSET = 0x0000; + GPIOx->OUTENCLR = 0xFFFF; + //GPIOx->INTENSET = 0x0000; + GPIOx->INTENCLR = 0xFFFF; + //GPIOx->INTTYPESET = 0x0000; + GPIOx->INTTYPECLR = 0xFFFF; + //GPIOx->INTPOLSET = 0x0000; + GPIOx->INTPOLCLR = 0xFFFF; + + + /* DeInit GPIOx + * Pad Control Register + * Pad Extern interrupt Enable Register + * Pad Alternate Function Select Register + */ + if (GPIOx == GPIOA) + { + px_pcr = PA_PCR; + px_afsr = PA_AFSR; + } + else if (GPIOx == GPIOB) + { + px_pcr = PB_PCR; + px_afsr = PB_AFSR; + } + else if (GPIOx == GPIOC) + { + px_pcr = PC_PCR; + px_afsr = PC_AFSR; + } + else // if (GPIOx == GPIOD) + { + px_pcr = (P_Port_Def*)PD_PCR; + px_afsr = (P_Port_Def*)PD_AFSR; + loop = 5; + } + + for(i=0; iPort[i] = 0x60; + px_afsr->Port[i] = PAD_AF0; + + } +} + +void HAL_GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16; + P_Port_Def *px_pcr; + + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); +// assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); + + if (GPIOx == GPIOA) px_pcr = PA_PCR; + else if (GPIOx == GPIOB) px_pcr = PB_PCR; + else if (GPIOx == GPIOC) px_pcr = PC_PCR; + else + { + px_pcr = (P_Port_Def*)PD_PCR; + loop = 5; + } + + for(pinpos = 0x00; pinpos < loop; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if(currentpin == pos) + { + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) + { + GPIOx->OUTENSET |= pos; + } + else // GPIO_Mode_In + { + GPIOx->OUTENCLR = pos; + } + + // Configure pull-up pull-down bits + if(GPIO_InitStruct->GPIO_Pad & Px_PCR_PUPD_UP) + { + px_pcr->Port[pinpos] &= ~(Px_PCR_PUPD_UP | Px_PCR_PUPD_DOWN); + px_pcr->Port[pinpos] |= Px_PCR_PUPD_UP; + } + else + { + px_pcr->Port[pinpos] &= ~(Px_PCR_PUPD_UP | Px_PCR_PUPD_DOWN); + px_pcr->Port[pinpos] |= Px_PCR_PUPD_DOWN; + } + + // Configure Driving stregnth selections bit + if(GPIO_InitStruct->GPIO_Pad & Px_PCR_DS_HIGH) + { + px_pcr->Port[pinpos] |= Px_PCR_DS_HIGH; + } + else + { + px_pcr->Port[pinpos] &= ~(Px_PCR_DS_HIGH); + } + + // Configure Open Drain selections bit + if(GPIO_InitStruct->GPIO_Pad & Px_PCR_OD) + { + px_pcr->Port[pinpos] |= Px_PCR_OD; + } + else + { + px_pcr->Port[pinpos] &= ~(Px_PCR_OD); + } + + // Configure Input buffer enable selection bit + if(GPIO_InitStruct->GPIO_Pad & Px_PCR_IE) + { + px_pcr->Port[pinpos] |= Px_PCR_IE; + } + else + { + px_pcr->Port[pinpos] &= ~(Px_PCR_IE); + } + + // Configure input type (CMOS input or Summit trigger input) select bit + if(GPIO_InitStruct->GPIO_Pad & Px_PCR_CS_SUMMIT) + { + px_pcr->Port[pinpos] |= Px_PCR_CS_SUMMIT; + } + else + { + px_pcr->Port[pinpos] &= ~(Px_PCR_CS_SUMMIT); + } + } + } +} + +void HAL_GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStruct->GPIO_Pad = (GPIOPad_TypeDef)(GPIO_PuPd_UP); +} + + +uint8_t HAL_GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if((GPIOx->DATA & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +uint8_t HAL_GPIO_ReadInputData(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + return ((uint16_t)GPIOx->DATA); +} + +uint8_t HAL_GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + + + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if((GPIOx->DATAOUT & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} +uint16_t HAL_GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALLPERIPH(GPIOx)); + return ((uint16_t)GPIOx->DATAOUT); +} + +void HAL_GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + (GPIOx->LB_MASKED[(uint8_t)(GPIO_Pin)]) = GPIO_Pin; + (GPIOx->UB_MASKED[(uint8_t)((GPIO_Pin)>>8)]) = GPIO_Pin; +} + +void HAL_GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + (GPIOx->LB_MASKED[(uint8_t)(GPIO_Pin)]) = ~(GPIO_Pin); + (GPIOx->UB_MASKED[(uint8_t)(GPIO_Pin>>8)]) = ~(GPIO_Pin); +} + +void HAL_GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + (GPIOx->LB_MASKED[(uint8_t)(GPIO_Pin)]) = BitVal; + (GPIOx->UB_MASKED[(uint8_t)((GPIO_Pin)>>8)]) = BitVal; +} + +void HAL_GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->DATAOUT = PortVal; +} + +void HAL_PAD_AFConfig(PAD_Type Px, uint16_t GPIO_Pin, PAD_AF_TypeDef P_AF) +{ + int i; + uint16_t idx =0x1; + assert_param(IS_PAD_Type(Px)); + + for(i=0;i<16;i++) + { + if(GPIO_Pin & (idx<Port[i] &= ~(0x03ul); + PA_AFSR->Port[i] |= P_AF; + } + else if(Px == PAD_PB) + { + assert_param(IS_PB_NUM(i)); + PB_AFSR->Port[i] &= ~(0x03ul); + PB_AFSR->Port[i] |= P_AF; + } + else if(Px == PAD_PC) + { + assert_param(IS_PC_NUM(i)); + PC_AFSR->Port[i] &= ~(0x03ul); + PC_AFSR->Port[i] |= P_AF; + } + else + { + assert_param(IS_PD_NUM(i)); + PD_AFSR->Port[i] &= ~(0x03ul); + PD_AFSR->Port[i] |= P_AF; + } + } + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.h new file mode 100644 index 0000000000..31586c4a72 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.h @@ -0,0 +1,134 @@ +/** + ****************************************************************************** + * @file + * @author + * @version + * @date + * @brief This file contains all the functions prototypes for the GPIO + * firmware library. + ****************************************************************************** + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __W7500X_HAL_GPIO_H +#define __W7500X_HAL_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "W7500x.h" + +#define GPIO_Pin_0 (uint16_t)(0x01 << 0) // Pin 0 Selected +#define GPIO_Pin_1 (uint16_t)(0x01 << 1) // Pin 1 Selected +#define GPIO_Pin_2 (uint16_t)(0x01 << 2) // Pin 2 Selected +#define GPIO_Pin_3 (uint16_t)(0x01 << 3) // Pin 3 Selected +#define GPIO_Pin_4 (uint16_t)(0x01 << 4) // Pin 4 Selected +#define GPIO_Pin_5 (uint16_t)(0x01 << 5) // Pin 5 Selected +#define GPIO_Pin_6 (uint16_t)(0x01 << 6) // Pin 6 Selected +#define GPIO_Pin_7 (uint16_t)(0x01 << 7) // Pin 7 Selected +#define GPIO_Pin_8 (uint16_t)(0x01 << 8) // Pin 8 Selected +#define GPIO_Pin_9 (uint16_t)(0x01 << 9) // Pin 9 Selected +#define GPIO_Pin_10 (uint16_t)(0x01 << 10) // Pin 10 Selected +#define GPIO_Pin_11 (uint16_t)(0x01 << 11) // Pin 11 Selected +#define GPIO_Pin_12 (uint16_t)(0x01 << 12) // Pin 12 Selected +#define GPIO_Pin_13 (uint16_t)(0x01 << 13) // Pin 13 Selected +#define GPIO_Pin_14 (uint16_t)(0x01 << 14) // Pin 14 Selected +#define GPIO_Pin_15 (uint16_t)(0x01 << 15) // Pin 15 Selected +#define GPIO_Pin_All (uint16_t)(0xFFFF) // All pins Selected + + +#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00) +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || ((PIN) == GPIO_Pin_1) || \ + (((PIN) == GPIO_Pin_2) || ((PIN) == GPIO_Pin_3) || \ + (((PIN) == GPIO_Pin_4) || ((PIN) == GPIO_Pin_5) || \ + (((PIN) == GPIO_Pin_6) || ((PIN) == GPIO_Pin_7) || \ + (((PIN) == GPIO_Pin_8) || ((PIN) == GPIO_Pin_9) || \ + (((PIN) == GPIO_Pin_10) || ((PIN) == GPIO_Pin_11) || \ + (((PIN) == GPIO_Pin_12) || ((PIN) == GPIO_Pin_13) || \ + (((PIN) == GPIO_Pin_14) || ((PIN) == GPIO_Pin_15) ) + + +#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || \ + ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD) ) + +typedef enum +{ + GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ + GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ + GPIO_Mode_AF = 0x02 /*!< GPIO Alternate function Mode */ +}GPIOMode_TypeDef; + +typedef enum +{ + GPIO_NO_PUPD = 0x0ul, + GPIO_PuPd_UP = Px_PCR_PUPD_UP, + GPIO_PuPd_DOWN = Px_PCR_PUPD_DOWN, + GPIO_OD = Px_PCR_OD, +}GPIOPad_TypeDef; + +typedef struct +{ + uint32_t GPIO_Pin; + GPIOMode_TypeDef GPIO_Mode; + GPIOPad_TypeDef GPIO_Pad; +}GPIO_InitTypeDef; + +typedef enum +{ + Bit_RESET = 0, + Bit_SET +}BitAction; + +typedef enum +{ + PAD_PA = 0, + PAD_PB, + PAD_PC, + PAD_PD +}PAD_Type; + +typedef enum +{ + PAD_AF0 = Px_AFSR_AF0, + PAD_AF1 = Px_AFSR_AF1, + PAD_AF2 = Px_AFSR_AF2, + PAD_AF3 = Px_AFSR_AF3 +}PAD_AF_TypeDef; + +#define IS_PAD_TYPE(Px) (((Px) == PAD_PA) || ((Px) == PAD_PB) \ + ((Px) == PAD_PC) || ((Px) == PAD_PD)) + +#define IS_PA_NUM(NUM) (((NUM)>=0) && ((NUM)<16)) +#define IS_PB_NUM(NUM) (((NUM)>=0) && ((NUM)<16)) +#define IS_PC_NUM(NUM) (((NUM)>=0) && ((NUM)<16)) +#define IS_PD_NUM(NUM) (((NUM)>=0) && ((NUM)< 5)) + +#define IS_PAD_AF(AF) (((AF) == PAD_AF0) || ((AF) == PAD_AF1) || \ + ((AF) == PAD_AF2) || ((AF) == PAD_AF3)) + + +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION_ == Bit_RESET) || (ACTION) ==Bit_SET)) + +void HAL_GPIO_DeInit(GPIO_TypeDef* GPIOx); +void HAL_GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void HAL_GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +uint8_t HAL_GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint8_t HAL_GPIO_ReadInputData(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint8_t HAL_GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t HAL_GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void HAL_GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void HAL_GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void HAL_PAD_AFConfig(PAD_Type Px, uint16_t Pnum, PAD_AF_TypeDef P_AF); + + +#ifdef __cplusplus +} +#endif + +#endif // __W7500X_HAL_GPIO_H diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.c b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.c new file mode 100644 index 0000000000..0d23d46774 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.c @@ -0,0 +1,563 @@ +#include "W7500x.h" + +/** @defgroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * @retval None + */ +void I2C_Delay(uint32_t nCount) +{ + for(; nCount != 0; nCount--); +} + +uint32_t I2C_Init(I2C_TypeDef* I2Cx, I2C_ConfigStruct conf) +{ + uint32_t mode; + uint8_t prescale; + uint16_t timeout; + uint16_t slave_address; + + + mode = conf.mode; + slave_address = conf.slave_address; + if(mode == I2C_Master) + { + prescale = conf.master.prescale; + timeout = conf.master.timeout; + + I2C_CoreEn(I2Cx,ENABLE); + I2C_MasterSlave(I2Cx,ENABLE); + + I2C_Prescale(I2Cx,prescale); // 0x61 //When PLL clk is 20MHz and Prescale value set 0x61, SCL is 100KHz + I2C_TimeoutSet(I2Cx,timeout); // 0xFFFF + + I2C_CoreEn(I2Cx,DISABLE); + } + else if(conf.mode == I2C_Slave) + { + I2C_AcknowledgeConfig(I2Cx,ENABLE); + I2C_SetSlavAddress(I2Cx,slave_address); + } + else + return ERROR; + + + I2C_AcknowledgeConfig(I2Cx,ENABLE); + + return SUCCESS; +} + + +void I2C_DeInit(I2C_TypeDef* I2Cx) +{ + I2C_InterRst(I2Cx,ENABLE); + I2C_CoreEn(I2Cx, ENABLE); + I2C_InterRst(I2Cx,DISABLE); + I2C_CoreEn(I2Cx, DISABLE); +} + + +ErrorStatus I2C_Start(I2C_TypeDef* I2Cx, uint16_t slave_address, I2C_CTR ctr) +{ + ErrorStatus ret; + + I2C_GenerateSTART(I2Cx,ENABLE); + I2C_SendSlaveAddress(I2Cx,slave_address,(I2C_CTR)ctr); + I2C_GenerateSTART(I2Cx,DISABLE); + + ret=I2C_CheckEvent(I2Cx,I2C_ACKR); + + return ret; +} + +void I2C_Stop(I2C_TypeDef* I2Cx) +{ + I2C_GenerateSTOP(I2Cx,ENABLE); + I2C_GenerateSTOP(I2Cx,DISABLE); +} + +void I2C_Reset(I2C_TypeDef* I2Cx) +{ + I2C_CoreEn(I2Cx,ENABLE); + // Maybe, it needs a little delay + I2C_CoreEn(I2Cx,DISABLE); +} + +void I2C_SendData(I2C_TypeDef* I2Cx,uint16_t Data) +{ + I2Cx -> TXR = (uint16_t)Data; +} + +int8_t I2C_SendDataAck(I2C_TypeDef* I2Cx,uint16_t Data) +{ + I2Cx -> TXR = (uint16_t)Data; + if(I2C_CheckEvent(I2Cx,I2C_ACKR) == ERROR) + { + return ERROR; + } + return SUCCESS; +} + +int I2C_ReceiveData(I2C_TypeDef* I2Cx, int last) +{ + if( I2C_CheckEvent(I2Cx,I2C_ACKT) == ERROR ) + return -1; + + if(last) + { + I2C_AcknowledgeConfig(I2Cx,DISABLE); + if( I2C_CheckEvent(I2Cx,I2C_ACKT) == ERROR ) + return -1; + + I2C_Stop(I2Cx); + } + + + return (uint8_t)I2Cx -> RXR; +} + + +int I2C_Burst_Read(I2C_TypeDef* I2Cx, uint16_t address, uint8_t *data, int length, int stop) +{ + int recv_cnt; + + if( I2C_Start(I2Cx,address,I2C_READ_SA7) == ERROR){ + return -1; + } + + for(recv_cnt=0;recv_cntCMDR = I2C_CMDR_STA; + else I2Cx->CMDR = I2C_CMDR_STA; + } +/** + * @brief Generates I2Cx communication STOP condition. + * @param I2Cx: where x can be 0 or 1 to select the I2C peripheral. + * @param NewState: NewState of the I2C STOP condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) I2Cx->CMDR = I2C_CMDR_STO; + else I2Cx->CMDR = I2C_CMDR_STO; +} + +/** + * @brief Enables or disables the specified I2C acknowledge feature. + * @param I2Cx: where x can be 0 or 1 to select the I2C peripheral. + * @param NewState: NewState of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) I2Cx -> CMDR = I2C_CMDR_ACK; + else I2Cx -> CMDR = I2C_CMDR_ACK; +} + +/** + * @brief Generates I2Cx communication REGenerateSTART condition + * @param I2Cx: where x can be 0 or 1 to select the I2C peripheral. + * @param NewState: NewState of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_RESTART(I2C_TypeDef * I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) I2Cx->CMDR = I2C_CMDR_RESTA; + else I2Cx->CMDR = I2C_CMDR_RESTA; +} + +/** + * @brief Enable or disable the specified I2C Core_en feature + * @param I2Cx: where x can be 0 or 1 to select the I2C peripheral. + * @param NewState: NewState of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_CoreEn(I2C_TypeDef* I2Cx,FunctionalState NewState) +{ + /*Control*/ + if(NewState != DISABLE) I2Cx -> CTR = I2C_CTR_COREEN; + else I2Cx -> CTR = I2C_CTR_COREEN; +} + + +void I2C_InterEn(I2C_TypeDef* I2Cx,FunctionalState NewState) +{ + /*Control Interrupt Enable*/ + if(NewState != DISABLE) I2Cx -> CTR = I2C_CTR_INTEREN; + else I2Cx -> CTR = I2C_CTR_INTEREN; +} + + +void I2C_MasterSlave(I2C_TypeDef* I2Cx,FunctionalState NewState) +{ + /*Control MasterSlave select*/ + if(NewState == ENABLE) + { + if( (I2Cx->CTR & I2C_CTR_MODE) != I2C_CTR_MODE ) + { + I2Cx->CTR = I2C_CTR_MODE; + } + } + else // DISABLE + { + if( (I2Cx->CTR & I2C_CTR_MODE) == I2C_CTR_MODE ) + { + I2Cx->CTR = I2C_CTR_MODE; + } + } +} + + +void I2C_ControlRW(I2C_TypeDef* I2Cx,FunctionalState NewState) +{ + /*Control Read(receive)*/ + if(NewState == ENABLE) + { + if( (I2Cx->CTR & I2C_CTR_CTRRWN) != I2C_CTR_CTRRWN ) + { + I2Cx->CTR = I2C_CTR_CTRRWN; + } + } + else // DISABLE + { + if( (I2Cx->CTR & I2C_CTR_CTRRWN) == I2C_CTR_CTRRWN ) + { + I2Cx->CTR = I2C_CTR_CTRRWN; + } + } +} + + +void I2C_ControlEn(I2C_TypeDef* I2Cx,FunctionalState NewState) +{ + /*Control*/ + if(NewState == ENABLE) + { + if( (I2Cx->CTR & I2C_CTR_CTEN) != I2C_CTR_CTEN ) + { + I2Cx->CTR = I2C_CTR_CTEN; + } + } + else // DISABLE + { + if( (I2Cx->CTR & I2C_CTR_CTEN) == I2C_CTR_CTEN ) + { + I2Cx->CTR = I2C_CTR_CTEN; + } + } +} + + +void I2C_InterRst(I2C_TypeDef* I2Cx,FunctionalState NewState) +{ + /*Control*/ + if(NewState == ENABLE) + { + if( (I2Cx->ISCR & I2C_ISCR_RST) != I2C_ISCR_RST ) + { + I2Cx->ISCR = I2C_ISCR_RST; + } + } + else // DISABLE + { + if( (I2Cx->ISCR & I2C_ISCR_RST) == I2C_ISCR_RST ) + { + I2Cx->ISCR = I2C_ISCR_RST; + } + } +} + +void I2C_Prescale(I2C_TypeDef* I2Cx,uint16_t Data) +{ + I2Cx -> PRER = (uint16_t)Data; +} + +void I2C_TimeoutSet(I2C_TypeDef* I2Cx,uint16_t Data) +{ + I2Cx -> TSR = (uint16_t)Data; +} +void I2C_SetSlavAddress(I2C_TypeDef* I2Cx,uint16_t Data) +{ + I2Cx -> SADDR = (uint16_t)Data; +} + + +uint8_t I2C_StatusRead(I2C_TypeDef* I2Cx) +{ + return (uint8_t)I2Cx -> SR; +} + + +ErrorStatus WaitEvent(I2C_TypeDef* I2Cx, uint32_t flag, FlagStatus status) +{ + int Timeout=0,loopcnt=0; + + Timeout = I2Cx->TSR; + if(status == SET) + { + for(loopcnt=Timeout; loopcnt>0; loopcnt--) + { + if( ((I2Cx->SR) & flag) == flag ) + return SUCCESS; + } + } + else + { + for(loopcnt=Timeout; loopcnt>0; loopcnt--) + { + if( ((I2Cx->SR) & flag) != flag ) + return SUCCESS; + } + } + + + return ERROR; +} + + +/** + * @brief Checks whether the specified I2C flag is set or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_EVENT: specifies the event to be checked. + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx,I2C_SR sr) +{ + switch(sr) + { + case(I2C_ACKR): + if( WaitEvent(I2Cx, I2C_SR_ACKR, SET) == ERROR) return ERROR; + if( WaitEvent(I2Cx, I2C_SR_ACKR, RESET) == ERROR) return ERROR; + break; + + case(I2C_ACKT ): + if( WaitEvent(I2Cx, I2C_SR_ACKT, SET) == ERROR) return ERROR; + if( WaitEvent(I2Cx, I2C_SR_ACKT, RESET) == ERROR) return ERROR; + break; + + case(I2C_OACKR): + if( WaitEvent(I2Cx, I2C_SR_ACKR, SET) == ERROR) return ERROR; + break; + + case(I2C_SACKR ): + if( WaitEvent(I2Cx, I2C_SR_ACKR, RESET) == ERROR) return ERROR; + break; + + case(I2C_BT ): + if( WaitEvent(I2Cx, I2C_SR_BT, RESET) == ERROR) return ERROR; + break; + + default: + return ERROR; + } + + return SUCCESS; +} + + +/* +void I2C_MasterInit(I2C_TypeDef * I2Cx,uint8_t Prescale,uint16_t Timeout,I2C_CTR Ctr) +{ + switch(Ctr) + { + case(I2C_WRITE_SA7): //000 + case(I2C_READ_SA7): //001 + I2C_CoreEn(I2Cx,ENABLE); + break; + + case(I2C_WRITE_SA10): //010 + case(I2C_READ_SA10): //011 + I2C_CoreEn(I2Cx,ENABLE); + I2C_SlaveAddressLength(I2Cx,ENABLE); + break; + + case(I2C_CTRWRITE_SA7): //100 + I2C_CoreEn(I2Cx,ENABLE); + I2C_ControlEn(I2Cx,ENABLE); + break; + + case(I2C_CTRREAD_SA7): //101 + I2C_CoreEn(I2Cx,ENABLE); + I2C_ControlRW(I2Cx,ENABLE); + I2C_ControlEn(I2Cx,ENABLE); + break; + + case(I2C_CTRWRITE_SA10): //110 + I2C_CoreEn(I2Cx,ENABLE); + I2C_ControlRW(I2Cx,DISABLE); + I2C_ControlEn(I2Cx,ENABLE); + I2C_SlaveAddressLength(I2Cx,ENABLE); + break; + case(I2C_CTRREAD_SA10): //111 + I2C_CoreEn(I2Cx,ENABLE); + I2C_ControlRW(I2Cx,ENABLE); + I2C_ControlEn(I2Cx,ENABLE); + I2C_SlaveAddressLength(I2Cx,ENABLE); + break; + + default: + return; + + } + + I2C_MasterSlave(I2Cx,ENABLE); + I2C_MasterSlave(I2Cx,DISABLE); + I2C_MasterSlave(I2Cx,ENABLE); + + I2C_Prescale(I2Cx,Prescale); // 0x61 //When PLL clk is 20MHz and Prescale value set 0x61, SCL is 100KHz + I2C_TimeoutSet(I2Cx,Timeout); // 0xFFFF + +#if defined(I2C_INT) + I2C_CoreEn(I2Cx,DISABLE); + I2C_InterEn(I2Cx,ENABLE); +#else + I2C_CoreEn(I2Cx,DISABLE); + +#endif + +} + +void I2C_SlaveInit(I2C_TypeDef * I2Cx, FunctionalState NewState,uint16_t data) +{ + if(NewState != DISABLE) + { + I2C_SlaveAddressLength(I2Cx,ENABLE); + } + else + I2C_AcknowledgeConfig(I2Cx,ENABLE); + + I2C_SetSlavAddress(I2Cx,data); +} +*/ + +void I2C_SendSlaveAddress(I2C_TypeDef* I2Cx, uint8_t SlaveAddress,I2C_CTR Ctr) +{ + switch(Ctr) + { + case(I2C_READ_SA7): + I2C_SendData(I2Cx,SlaveAddress|I2C_READ); + break; + + + case(I2C_WRITE_SA7): + I2C_SendData(I2Cx,SlaveAddress|I2C_WRITE); + break; + +// case(I2C_READ_SA10): +// I2C_SendData(I2Cx,SlaveAddress|I2C_READ); +// break; +// +// case(I2C_WRITE_SA10): +// I2C_SendData(I2Cx,SlaveAddress|I2C_WRITE); +// break; + + case(I2C_CTRWRITE_SA7): + case(I2C_CTRREAD_SA7): +// case(I2C_CTRWRITE_SA10): +// case(I2C_CTRREAD_SA10): + I2C_SendData(I2Cx,SlaveAddress); + break; + + default: + return; + + } +} + + int8_t I2C_Restart_Structure(I2C_TypeDef * I2Cx,uint32_t SlaveAddress,I2C_CTR Ctr) +{ + + I2C_RESTART(I2Cx,ENABLE); + I2C_SendSlaveAddress(I2Cx,SlaveAddress,Ctr); + if((I2C_CheckEvent(I2Cx,I2C_OACKR)) == ERROR ) + { + return 0; + } + I2C_RESTART(I2Cx,DISABLE); + if((I2C_CheckEvent(I2Cx,I2C_SACKR)) == ERROR) + { + return 0; + } + return 1; +} + +/** + * @brief Reads the specified I2C register and returns its value. + * @param I2C_Register: specifies the register to read. + * This parameter can be one of the following values: + * @arg I2C_Register_CR1: CR1 register. + * @arg I2C_Register_CR2: CR2 register. + * @arg I2C_Register_OAR1: OAR1 register. + * @arg I2C_Register_OAR2: OAR2 register. + * @arg I2C_Register_DR: DR register. + * @arg I2C_Register_SR1: SR1 register. + * @arg I2C_Register_SR2: SR2 register. + * @arg I2C_Register_CCR: CCR register. + * @arg I2C_Register_TRISE: TRISE register. + * @retval The value of the read register. + */ +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + + tmp = (uint32_t) I2Cx; + tmp += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint16_t *) tmp); +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.h new file mode 100644 index 0000000000..683dee9296 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.h @@ -0,0 +1,231 @@ +#include "W7500x.h" + +/** +* @defgroup I2C_Public_Types I2X Public Types +*/ +typedef enum +{ + I2C_WRITE_SA7=0, + I2C_READ_SA7, + //I2C_WRITE_SA10, + //I2C_READ_SA10, + I2C_CTRWRITE_SA7, + I2C_CTRREAD_SA7, + //I2C_CTRWRITE_SA10, + //I2C_CTRREAD_SA10, +} I2C_CTR; + +typedef enum +{ + I2C_ACKR=0, + I2C_ACKT, + I2C_OACKR, + I2C_SACKR, + I2C_BT, +} I2C_SR; + + +typedef enum +{ + INT_ACKR=-1, + INT_ACKT=-2, + INT_NACKR=-3, + INT_NACKT=-4, + INT_BT=-5, +} I2C_ERROR; + + +/** +*@ +*/ +/** @defgroup I2C_registers + * @{ + */ + +#define I2C_Register_PRER ((uint8_t)0x00) +#define I2C_Register_CTR ((uint8_t)0x04) +#define I2C_Register_CMDR ((uint8_t)0x08) +#define I2C_Register_SR ((uint8_t)0x0C) +#define I2C_Register_TSR ((uint8_t)0x10) +#define I2C_Register_SADDR ((uint8_t)0x14) +#define I2C_Register_TXR ((uint8_t)0x18) +#define I2C_Register_RXR ((uint8_t)0x1C) +#define I2C_Register_ISR ((uint8_t)0x20) +#define I2C_Register_ISCR ((uint8_t)0x24) +#define I2C_Register_ISMR ((uint8_t)0x28) +#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_PRER) || \ + ((REGISTER) == I2C_Register_CTR) || \ + ((REGISTER) == I2C_Register_CMDR) || \ + ((REGISTER) == I2C_Register_SR) || \ + ((REGISTER) == I2C_Register_TSR) || \ + ((REGISTER) == I2C_Register_SADDR) || \ + ((REGISTER) == I2C_Register_TXR) || \ + ((REGISTER) == I2C_Register_RXR) || \ + ((REGISTER) == I2C_Register_ISR)|| \ + ((REGISTER) == I2C_Register_ISCR)| \ + ((REGISTER) == I2C_Register_ISMR)) +/** + * @} + */ +/** @addtogroup Peripheral_registers_structures + * @{ + */ + + + + + + +/** + * @} + */ + +/** + * @brief I2C Interrput Status Register Mask flags + */ +//------------------------------------------------ +// I2C_ISMR_BIT +//------------------------------------------------ + +/** + * @} + */ + +/** @defgroup I2C_Private_Defines + * @{ + */ +/* I2C COREEN mask */ +#define I2C_CTR_COREEN_DIS ((uint16_t)0xFF7F) + +/* I2C INTEREN mask */ +#define I2C_CTR_INTEREN_DIS ((uint16_t)0xFFBF) + +/* I2C MODE(M/SN) mask */ +#define I2C_CTR_MODE_SLAVE ((uint16_t)0xFFDF) + +/* I2C ADDR10(10/7N) mask */ +#define I2C_CTR_ADDR10_7BIT ((uint16_t)0xFFEF) + +/* I2C CTRRWN(R/WN) mask */ +#define I2C_CTR_CTRRWN_DIS ((uint16_t)0xFFF7) + +/* I2C CTREN mask */ +#define I2C_CTR_CTEN_DIS ((uint16_t)0xFFFB) + + +/* I2C START mask */ +#define I2C_CMDR_START_DIS ((uint16_t)0xFF7F) + +/* I2C STOP mask */ +#define I2C_CMDR_STOP_DIS ((uint16_t)0xFFBF) + +/* I2C ACK mask */ +#define I2C_CMDR_ACK_NAK ((uint16_t)0xFFDF) + +/* I2C RESTART mask */ +#define I2C_CMDR_RESTA_DIS ((uint16_t)0xFFEF) + +/* I2C INTERRUPT RESET mask */ +#define I2C_ISCR_RST_DIS ((uint16_t)0xFFFE) +/** + * @} + */ + + + +#define I2C_WRITE 0 +#define I2C_READ 1 +#define I2C_RWSEL(NewState) (((NewState) == I2C_WRITE)|| \ + ((NewState) == I2C_READ)) + + +#define I2C_Ack_Enable (0x01ul << 5) +#define I2C_Ack_Disable (0x00ul << 5) +#define IS_I2C_ACK_NewState(NewState) (((NewState) == I2C_Ack_Enable) || \ + ((NewState) == I2C_Ack_Disable)) + +#define I2C_MASTER_MODE (0x01ul << 5 ) // 0x20 +#define I2C_SLAVE_MODE (0x00ul << 5 ) // 0x20 +#define IS_I2C_MODE(MODE) ((MODE) == I2C_MASTER_MODE)|| \ + (MODE) == I2C_SLAVE_MODE)) + +#define I2C_CTR_MODE (0x01ul << 5 ) // 0x20 + +#define SLAVE_ADDR10 0x208 + + +typedef enum + { + I2C_Master = I2C_MASTER_MODE, + I2C_Slave = I2C_SLAVE_MODE + }I2C_MODE; + + +typedef struct +{ + uint8_t prescale; + uint16_t timeout; + I2C_CTR control; +}I2C_MasterConfStruct; + + +typedef struct +{ + uint32_t mode; + uint16_t slave_address; // only on slave mode + I2C_MasterConfStruct master; +}I2C_ConfigStruct; + + +/** @defgroup I2C_Exported_Functions + * @{ + */ + +uint32_t I2C_Init (I2C_TypeDef* I2Cx, I2C_ConfigStruct conf); +void setFrequency (I2C_TypeDef* I2Cx, uint8_t prescale); +void I2C_DeInit (I2C_TypeDef* I2Cx); + +ErrorStatus I2C_Start (I2C_TypeDef* I2Cx, uint16_t slave_address, I2C_CTR ctr); +void I2C_Stop (I2C_TypeDef* I2Cx); +void I2C_Reset (I2C_TypeDef* I2Cx); + +void I2C_SendData (I2C_TypeDef* I2Cx,uint16_t Data); +int8_t I2C_SendDataAck (I2C_TypeDef* I2Cx,uint16_t Data); +int I2C_ReceiveData (I2C_TypeDef* I2Cx, int last); + +int I2C_Burst_Read (I2C_TypeDef* I2Cx, uint16_t address, uint8_t *data, int length, int stop); +int I2C_Burst_Write (I2C_TypeDef* I2Cx, uint16_t address, uint8_t *data, int length, int stop); + +void I2C_Delay (uint32_t nCount); + +void I2C_GenerateSTART (I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP (I2C_TypeDef* I2Cx, FunctionalState NewState); + +void I2C_AcknowledgeConfig (I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_RESTART (I2C_TypeDef * I2Cx, FunctionalState NewState); + +void I2C_CoreEn (I2C_TypeDef* I2Cx,FunctionalState NewState); +void I2C_InterEn (I2C_TypeDef* I2Cx,FunctionalState NewState); +void I2C_MasterSlave(I2C_TypeDef* I2Cx,FunctionalState NewState); +void I2C_ControlRW (I2C_TypeDef* I2Cx,FunctionalState NewState); +void I2C_ControlEn (I2C_TypeDef* I2Cx,FunctionalState NewState); + +void I2C_InterRst (I2C_TypeDef* I2Cx,FunctionalState NewState); +void I2C_Prescale (I2C_TypeDef* I2Cx,uint16_t Data); +void I2C_TimeoutSet (I2C_TypeDef* I2Cx,uint16_t Data); +void I2C_SetSlavAddress (I2C_TypeDef* I2Cx,uint16_t Data); +uint8_t I2C_StatusRead (I2C_TypeDef* I2Cx); + +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx,I2C_SR sr); + +void I2C_MasterInit (I2C_TypeDef * I2Cx,uint8_t Prescale,uint16_t Timeout,I2C_CTR Ctr); +void I2C_SlaveInit (I2C_TypeDef * I2Cx,FunctionalState NewState, uint16_t data); +void I2C_SendSlaveAddress (I2C_TypeDef* I2Cx, uint8_t SlaveAddress,I2C_CTR Ctr); + +int8_t I2C_Restart_Structure(I2C_TypeDef * I2Cx,uint32_t SlaveAddress,I2C_CTR Ctr); +uint16_t I2C_ReadRegister (I2C_TypeDef* I2Cx, uint8_t I2C_Register); + +/** + * @} + */ + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.c b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.c new file mode 100644 index 0000000000..d364279a3a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.c @@ -0,0 +1,905 @@ +/** + ****************************************************************************** + * @file + * @author + * @version + * @date + * @brief This file contains all the functions prototypes for the UART + * firmware library. + ****************************************************************************** + * + ****************************************************************************** + */ + +/* Includes -------------------------------------------*/ +#include "W7500x.h" + +void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn) +{ + if( PWM_CHn == PWM_CH0 ) + { + PWM->IER &= PWM_IER_IE0_Disable; ///< Interrupt enable register + PWM->SSR &= PWM_SSR_SS0_Stop; ///< Start Stop register + PWM->PSR &= PWM_PSR_PS0_Restart; ///< Pause register + PWM_CH0->IER = 0; ///< Interrupt enable register + PWM_CH0->ICR = PWM_CHn_ICR_MatchInterruptClear | + PWM_CHn_ICR_OverflowInterruptClear | + PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register + PWM_CH0->PR = 0; ///< Prescale register + PWM_CH0->MR = 0; ///< Match register + PWM_CH0->LR = 0xFFFFFFFF; ///< Limit register + PWM_CH0->UDMR = 0; ///< Up Dowm mode register + PWM_CH0->TCMR = 0; ///< Timer Counter mode register + PWM_CH0->PEEER = 0; ///< PWM output Enable and External input Enable register + PWM_CH0->CMR = 0; ///< Capture mode register + PWM_CH0->PDMR = 0; ///< Periodic Mode register + PWM_CH0->DZER = 0; ///< Dead Zone Enable register + PWM_CH0->DZCR = 0; ///< Dead Zone Counter register + } + else if( PWM_CHn == PWM_CH1 ) + { + PWM->IER &= PWM_IER_IE1_Disable; ///< Reset Interrupt enable register + PWM->SSR &= PWM_SSR_SS1_Stop; ///< Reset Start Stop register + PWM->PSR &= PWM_PSR_PS1_Restart; ///< Reset Pause register + PWM_CH1->IER = 0; ///< Interrupt enable register + PWM_CH1->ICR = PWM_CHn_ICR_MatchInterruptClear | + PWM_CHn_ICR_OverflowInterruptClear | + PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register + PWM_CH1->PR = 0; ///< Prescale register + PWM_CH1->MR = 0; ///< Match register + PWM_CH1->LR = 0xFFFFFFFF; ///< Limit register + PWM_CH1->UDMR = 0; ///< Up Dowm mode register + PWM_CH1->TCMR = 0; ///< Timer Counter mode register + PWM_CH1->PEEER = 0; ///< PWM output Enable and External input Enable register + PWM_CH1->CMR = 0; ///< Capture mode register + PWM_CH1->PDMR = 0; ///< Periodic Mode register + PWM_CH1->DZER = 0; ///< Dead Zone Enable register + PWM_CH1->DZCR = 0; ///< Dead Zone Counter register + } + else if( PWM_CHn == PWM_CH2) + { + PWM->IER &= PWM_IER_IE2_Disable; ///< Interrupt enable register + PWM->SSR &= PWM_SSR_SS2_Stop; ///< Start Stop register + PWM->PSR &= PWM_PSR_PS2_Restart; ///< Pause register + PWM_CH2->IER = 0; ///< Interrupt enable register + PWM_CH2->ICR = PWM_CHn_ICR_MatchInterruptClear | + PWM_CHn_ICR_OverflowInterruptClear | + PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register + PWM_CH2->PR = 0; ///< Prescale register + PWM_CH2->MR = 0; ///< Match register + PWM_CH2->LR = 0xFFFFFFFF; ///< Limit register + PWM_CH2->UDMR = 0; ///< Up Dowm mode register + PWM_CH2->TCMR = 0; ///< Timer Counter mode register + PWM_CH2->PEEER = 0; ///< PWM output Enable and External input Enable register + PWM_CH2->CMR = 0; ///< Capture mode register + PWM_CH2->PDMR = 0; ///< Periodic Mode register + PWM_CH2->DZER = 0; ///< Dead Zone Enable register + PWM_CH2->DZCR = 0; ///< Dead Zone Counter register + } + else if( PWM_CHn == PWM_CH3 ) + { + PWM->IER &= PWM_IER_IE3_Disable; ///< Interrupt enable register + PWM->SSR &= PWM_SSR_SS3_Stop; ///< Start Stop register + PWM->PSR &= PWM_PSR_PS3_Restart; ///< Pause register + PWM_CH3->IER = 0; ///< Interrupt enable register + PWM_CH3->ICR = PWM_CHn_ICR_MatchInterruptClear | + PWM_CHn_ICR_OverflowInterruptClear | + PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register + PWM_CH3->MR = 0; ///< Match register + PWM_CH3->LR = 0xFFFFFFFF; ///< Limit register + PWM_CH3->UDMR = 0; ///< Up Dowm mode register + PWM_CH3->TCMR = 0; ///< Timer Counter mode register + PWM_CH3->PEEER = 0; ///< PWM output Enable and External input Enable register + PWM_CH3->CMR = 0; ///< Capture mode register + PWM_CH3->PDMR = 0; ///< Periodic Mode register + PWM_CH3->DZER = 0; ///< Dead Zone Enable register + PWM_CH3->DZCR = 0; ///< Dead Zone Counter register + } + else if( PWM_CHn == PWM_CH4 ) + { + PWM->SSR &= PWM_IER_IE4_Disable; ///< Start Stop register + PWM->PSR &= PWM_SSR_SS4_Stop; ///< Pause register + PWM->IER &= PWM_PSR_PS4_Restart; ///< Interrupt enable register + PWM_CH4->IER = 0; ///< Interrupt enable register + PWM_CH4->ICR = PWM_CHn_ICR_MatchInterruptClear | + PWM_CHn_ICR_OverflowInterruptClear | + PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register + PWM_CH4->PR = 0; ///< Prescale register + PWM_CH4->MR = 0; ///< Match register + PWM_CH4->LR = 0xFFFF; ///< Limit register + PWM_CH4->UDMR = 0; ///< Up Dowm mode register + PWM_CH4->TCMR = 0; ///< Timer Counter mode register + PWM_CH4->PEEER = 0; ///< PWM output Enable and External input Enable register + PWM_CH4->CMR = 0; ///< Capture mode register + PWM_CH4->PDMR = 0; ///< Periodic Mode register + PWM_CH4->DZER = 0; ///< Dead Zone Enable register + PWM_CH4->DZCR = 0; ///< Dead Zone Counter register + } + else if( PWM_CHn == PWM_CH5 ) + { + PWM->SSR &= PWM_IER_IE5_Disable; ///< Start Stop register + PWM->PSR &= PWM_SSR_SS5_Stop; ///< Pause register + PWM->IER &= PWM_PSR_PS5_Restart; ///< Interrupt enable register + PWM_CH5->IER = 0; ///< Interrupt enable register + PWM_CH5->ICR = PWM_CHn_ICR_MatchInterruptClear | + PWM_CHn_ICR_OverflowInterruptClear | + PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register + PWM_CH5->PR = 0; ///< Prescale register + PWM_CH5->MR = 0; ///< Match register + PWM_CH5->LR = 0xFFFFFFFF; ///< Limit register + PWM_CH5->UDMR = 0; ///< Up Dowm mode register + PWM_CH5->TCMR = 0; ///< Timer Counter mode register + PWM_CH5->PEEER = 0; ///< PWM output Enable and External input Enable register + PWM_CH5->CMR = 0; ///< Capture mode register + PWM_CH5->PDMR = 0; ///< Periodic Mode register + PWM_CH5->DZER = 0; ///< Dead Zone Enable register + PWM_CH5->DZCR = 0; ///< Dead Zone Counter register + } + else if( PWM_CHn == PWM_CH6 ) + { + PWM->SSR &= PWM_IER_IE6_Disable; ///< Start Stop register + PWM->PSR &= PWM_SSR_SS6_Stop; ///< Pause register + PWM->IER &= PWM_PSR_PS6_Restart; ///< Interrupt enable register + PWM_CH6->IER = 0; ///< Interrupt enable register + PWM_CH6->ICR = PWM_CHn_ICR_MatchInterruptClear | + PWM_CHn_ICR_OverflowInterruptClear | + PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register + PWM_CH6->PR = 0; ///< Prescale register + PWM_CH6->MR = 0; ///< Match register + PWM_CH6->LR = 0xFFFFFFFF; ///< Limit register + PWM_CH6->UDMR = 0; ///< Up Dowm mode register + PWM_CH6->TCMR = 0; ///< Timer Counter mode register + PWM_CH6->PEEER = 0; ///< PWM output Enable and External input Enable register + PWM_CH6->CMR = 0; ///< Capture mode register + PWM_CH6->PDMR = 0; ///< Periodic Mode register + PWM_CH6->DZER = 0; ///< Dead Zone Enable register + PWM_CH6->DZCR = 0; ///< Dead Zone Counter register + } + else if( PWM_CHn == PWM_CH7 ) + { + PWM->SSR &= PWM_IER_IE7_Disable; ///< Start Stop register + PWM->PSR &= PWM_SSR_SS7_Stop; ///< Pause register + PWM->IER &= PWM_PSR_PS7_Restart; ///< Interrupt enable register + PWM_CH7->IER = 0; ///< Interrupt enable register + PWM_CH7->ICR = PWM_CHn_ICR_MatchInterruptClear | + PWM_CHn_ICR_OverflowInterruptClear | + PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register + PWM_CH7->PR = 0; ///< Prescale register + PWM_CH7->MR = 0; ///< Match register + PWM_CH7->LR = 0xFFFFFFFF; ///< Limit register + PWM_CH7->UDMR = 0; ///< Up Dowm mode register + PWM_CH7->TCMR = 0; ///< Timer Counter mode register + PWM_CH7->PEEER = 0; ///< PWM output Enable and External input Enable register + PWM_CH7->CMR = 0; ///< Capture mode register + PWM_CH7->PDMR = 0; ///< Periodic Mode register + PWM_CH7->DZER = 0; ///< Dead Zone Enable register + PWM_CH7->DZCR = 0; ///< Dead Zone Counter register + } +} + + +void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct) //complet +{ + /* Stop PWM_CHn */ + PWM_CHn_Stop(PWM_CHn); + /* Select Timer/Counter mode as Timer mode */ + PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode; + /* Set Prescale register value */ + PWM_CHn->PR = PWM_TimerModeInitStruct->PWM_CHn_PR; + /* Set Match register value */ + PWM_CHn->MR = PWM_TimerModeInitStruct->PWM_CHn_MR; + /* Set Limit register value */ + PWM_CHn->LR = PWM_TimerModeInitStruct->PWM_CHn_LR; + /* Select Up-down mode */ + PWM_CHn->UDMR = PWM_TimerModeInitStruct->PWM_CHn_UDMR; + /* Select Periodic mode */ + PWM_CHn->PDMR = PWM_TimerModeInitStruct->PWM_CHn_PDMR; +} + +void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_PR_FILTER(PWM_CaptureModeInitStruct->PWM_CHn_PR)); + assert_param(IS_PWM_MR_FILTER(PWM_CHn, PWM_CaptureModeInitStruct->PWM_CHn_MR)); + assert_param(IS_PWM_LR_FILTER(PWM_CHn, PWM_CaptureModeInitStruct->PWM_CHn_LR)); + assert_param(IS_PWM_CHn_UDMR(PWM_CaptureModeInitStruct->PWM_CHn_UDMR)); + assert_param(IS_PWM_CHn_PDMR(PWM_CaptureModeInitStruct->PWM_CHn_PDMR)); + assert_param(IS_PWM_CHn_CMR(PWM_CaptureModeInitStruct->PWM_CHn_CMR)); + + /* Stop PWM_CHn */ + PWM_CHn_Stop(PWM_CHn); + /* Select Timer/Counter mode as Timer mode */ + PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode; + /* Set Prescale register value */ + PWM_CHn->PR = PWM_CaptureModeInitStruct->PWM_CHn_PR; + /* Set Match register value */ + PWM_CHn->MR = PWM_CaptureModeInitStruct->PWM_CHn_MR; + /* Set Limit register value */ + PWM_CHn->LR = PWM_CaptureModeInitStruct->PWM_CHn_LR; + /* Select Up-down mode */ + PWM_CHn->UDMR = PWM_CaptureModeInitStruct->PWM_CHn_UDMR; + /* Select Periodic mode */ + PWM_CHn->PDMR = PWM_CaptureModeInitStruct->PWM_CHn_PDMR; + /* Select Capture mode */ + PWM_CHn->CMR = PWM_CaptureModeInitStruct->PWM_CHn_CMR; + /* External input enable */ + PWM_CHn->PEEER = PWM_CHn_PEEER_ExtEnable; +} + +void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + /* Stop PWM_CHn */ + PWM_CHn_Stop(PWM_CHn); + /* Select Timer/Counter mode as Timer mode */ + PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode; + /* Set Match register value */ + PWM_CHn->MR = PWM_CounterModeInitStruct->PWM_CHn_MR; + /* Set Limit register value */ + PWM_CHn->LR = PWM_CounterModeInitStruct->PWM_CHn_LR; + /* Select Up-down mode */ + PWM_CHn->UDMR = PWM_CounterModeInitStruct->PWM_CHn_UDMR; + /* Select Periodic mode */ + PWM_CHn->PDMR = PWM_CounterModeInitStruct->PWM_CHn_PDMR; + /* Select Counter mode */ + PWM_CHn->TCMR = PWM_CounterModeInitStruct->PWM_CHn_TCMR; + /* Enable external input */ + PWM_CHn->PEEER = PWM_CHn_PEEER_ExtEnable; +} + +void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_PR_FILTER(PWM_DeadzoneModeInitStruct->PWM_CHn_PR)); + assert_param(IS_PWM_MR_FILTER(PWM_CHn, PWM_DeadzoneModeInitStruct->PWM_CHn_MR)); + assert_param(IS_PWM_LR_FILTER(PWM_CHn, PWM_DeadzoneModeInitStruct->PWM_CHn_LR)); + assert_param(IS_PWM_CHn_UDMR(PWM_DeadzoneModeInitStruct->PWM_CHn_UDMR)); + assert_param(IS_PWM_CHn_PDMR(PWM_DeadzoneModeInitStruct->PWM_CHn_PDMR)); + assert_param(IS_PWM_Deadznoe(PWM_CHn)); + + /* Stop PWM_CHn */ + PWM_CHn_Stop(PWM_CHn); + /* Select Timer/Counter mode as Timer mode */ + PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode; + /* Set Prescale register value */ + PWM_CHn->PR = PWM_DeadzoneModeInitStruct->PWM_CHn_PR; + /* Set Match register value */ + PWM_CHn->MR = PWM_DeadzoneModeInitStruct->PWM_CHn_MR; + /* Set Limit register value */ + PWM_CHn->LR = PWM_DeadzoneModeInitStruct->PWM_CHn_LR; + /* Select Up-down mode */ + PWM_CHn->UDMR = PWM_DeadzoneModeInitStruct->PWM_CHn_UDMR; + /* Select Periodic mode */ + PWM_CHn->PDMR = PWM_DeadzoneModeInitStruct->PWM_CHn_PDMR; + /* Enable Dead Zone generation */ + PWM_CHn->DZER = PWM_CHn_DZER_Enable; + /* Set Dead Zone Counter */ + PWM_CHn->DZCR = PWM_DeadzoneModeInitStruct->PWM_CHn_DZCR; +} + +void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable ) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_Output(outputEnDisable)); + if( PWM_CHn->DZER ) + assert_param(IS_PWM_Deadznoe(PWM_CHn)); + + /* Stop PWM_CHn */ + PWM_CHn_Stop(PWM_CHn); + /*Config PWM output and External input */ + PWM_CHn->PEEER = outputEnDisable; +} + +void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn) +{ + PWM_CtrlPWMOutput(PWM_CHn, PWM_CHn_PEEER_PWMEnable); +} + +void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn) +{ + PWM_CtrlPWMOutput(PWM_CHn, PWM_CHn_PEEER_Disable); +} + +void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + /* Stop PWM_CHn */ + PWM_CHn_Stop(PWM_CHn); + + if(state == ENABLE) + { + if(PWM_CHn == PWM_CH0) { + PWM->IER |= PWM_IER_IE0_Enable; + } + else if(PWM_CHn == PWM_CH1) { + PWM->IER |= PWM_IER_IE1_Enable; + } + else if(PWM_CHn == PWM_CH2) { + PWM->IER |= PWM_IER_IE2_Enable; + } + else if(PWM_CHn == PWM_CH3) { + PWM->IER |= PWM_IER_IE3_Enable; + } + else if(PWM_CHn == PWM_CH4) { + PWM->IER |= PWM_IER_IE4_Enable; + } + else if(PWM_CHn == PWM_CH5) { + PWM->IER |= PWM_IER_IE5_Enable; + } + else if(PWM_CHn == PWM_CH6) { + PWM->IER |= PWM_IER_IE6_Enable; + } + else if(PWM_CHn == PWM_CH7) { + PWM->IER |= PWM_IER_IE7_Enable; + } + } + else + { + if(PWM_CHn == PWM_CH0) { + PWM->IER &= PWM_IER_IE0_Disable; + } + else if(PWM_CHn == PWM_CH1) { + PWM->IER &= PWM_IER_IE1_Disable; + } + else if(PWM_CHn == PWM_CH2) { + PWM->IER &= PWM_IER_IE2_Disable; + } + else if(PWM_CHn == PWM_CH3) { + PWM->IER &= PWM_IER_IE3_Disable; + } + else if(PWM_CHn == PWM_CH4) { + PWM->IER &= PWM_IER_IE4_Disable; + } + else if(PWM_CHn == PWM_CH5) { + PWM->IER &= PWM_IER_IE5_Disable; + } + else if(PWM_CHn == PWM_CH6) { + PWM->IER &= PWM_IER_IE6_Disable; + } + else if(PWM_CHn == PWM_CH7) { + PWM->IER &= PWM_IER_IE7_Disable; + } + } +} + +FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn) +{ + FlagStatus ret_val = RESET; + + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + if(PWM_CHn == PWM_CH0) { + ret_val = (FlagStatus)((PWM->IER & 0x01) >> 0); + } + else if(PWM_CHn == PWM_CH1) { + ret_val = (FlagStatus)((PWM->IER & 0x02) >> 1); + } + else if(PWM_CHn == PWM_CH2) { + ret_val = (FlagStatus)((PWM->IER & 0x04) >> 2); + } + else if(PWM_CHn == PWM_CH3) { + ret_val = (FlagStatus)((PWM->IER & 0x08) >> 3); + } + else if(PWM_CHn == PWM_CH4) { + ret_val = (FlagStatus)((PWM->IER & 0x10) >> 4); + } + else if(PWM_CHn == PWM_CH5) { + ret_val = (FlagStatus)((PWM->IER & 0x20) >> 5); + } + else if(PWM_CHn == PWM_CH6) { + ret_val = (FlagStatus)((PWM->IER & 0x40) >> 6); + } + else if(PWM_CHn == PWM_CH7) { + ret_val = (FlagStatus)((PWM->IER & 0x80) >> 7); + } + + return ret_val; +} + +void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + + assert_param(IS_PWM_CHn_IER(PWM_CHn_IER)); + + /* Stop PWM_CHn */ + PWM_CHn_Stop(PWM_CHn); + + if(state == ENABLE) + PWM_CHn->IER |= PWM_CHn_IER; + else + PWM_CHn->IER &= ~PWM_CHn_IER; +} + +uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->IER; +} + +uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->IR; +} + +void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR) +{ + /* Check the parameters */ + + PWM_CHn->ICR = PWM_CHn_ICR; +} + +void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + /* Set Start Stop register */ + if(PWM_CHn == PWM_CH0) { + PWM->SSR |= PWM_SSR_SS0_Start; + } + else if(PWM_CHn == PWM_CH1) { + PWM->SSR |= PWM_SSR_SS1_Start; + } + else if(PWM_CHn == PWM_CH2) { + PWM->SSR |= PWM_SSR_SS2_Start; + } + else if(PWM_CHn == PWM_CH3) { + PWM->SSR |= PWM_SSR_SS3_Start; + } + else if(PWM_CHn == PWM_CH4) { + PWM->SSR |= PWM_SSR_SS4_Start; + } + else if(PWM_CHn == PWM_CH5) { + PWM->SSR |= PWM_SSR_SS5_Start; + } + else if(PWM_CHn == PWM_CH6) { + PWM->SSR |= PWM_SSR_SS6_Start; + } + else if(PWM_CHn == PWM_CH7) { + PWM->SSR |= PWM_SSR_SS7_Start; + } +} + +void PWM_Multi_Start(uint32_t ssr_bit_flag) //complete +{ + /* Set Start Stop register */ + PWM->SSR |= ssr_bit_flag; +} + +void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Reset Start Stop register */ + if(PWM_CHn == PWM_CH0) { + PWM->SSR &= PWM_SSR_SS0_Stop; + } + else if(PWM_CHn == PWM_CH1) { + PWM->SSR &= PWM_SSR_SS1_Stop; + } + else if(PWM_CHn == PWM_CH2) { + PWM->SSR &= PWM_SSR_SS2_Stop; + } + else if(PWM_CHn == PWM_CH3) { + PWM->SSR &= PWM_SSR_SS3_Stop; + } + else if(PWM_CHn == PWM_CH4) { + PWM->SSR &= PWM_SSR_SS4_Stop; + } + else if(PWM_CHn == PWM_CH5) { + PWM->SSR &= PWM_SSR_SS5_Stop; + } + else if(PWM_CHn == PWM_CH6) { + PWM->SSR &= PWM_SSR_SS6_Stop; + } + else if(PWM_CHn == PWM_CH7) { + PWM->SSR &= PWM_SSR_SS7_Stop; + } +} + +void PWM_Multi_Stop(uint32_t ssr_bit_flag) //complete +{ + /* Reset Start Stop register */ + PWM->SSR &= ~ssr_bit_flag; +} + +void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn) +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + /* Set Pause register */ + if(PWM_CHn == PWM_CH0) { + PWM->PSR |= PWM_PSR_PS0_Pause; + } + else if(PWM_CHn == PWM_CH1) { + PWM->PSR |= PWM_PSR_PS1_Pause; + } + else if(PWM_CHn == PWM_CH2) { + PWM->PSR |= PWM_PSR_PS2_Pause; + } + else if(PWM_CHn == PWM_CH3) { + PWM->PSR |= PWM_PSR_PS3_Pause; + } + else if(PWM_CHn == PWM_CH4) { + PWM->PSR |= PWM_PSR_PS4_Pause; + } + else if(PWM_CHn == PWM_CH5) { + PWM->PSR |= PWM_PSR_PS5_Pause; + } + else if(PWM_CHn == PWM_CH6) { + PWM->PSR |= PWM_PSR_PS6_Pause; + } + else if(PWM_CHn == PWM_CH7) { + PWM->PSR |= PWM_PSR_PS7_Pause; + } +} + +void PWM_Multi_Pause(uint32_t psr_bit_flag) +{ + PWM->PSR |= psr_bit_flag; +} + +void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn) +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + /* Reset Pause register */ + if(PWM_CHn == PWM_CH0) { + PWM->PSR &= PWM_PSR_PS0_Restart; + } + else if(PWM_CHn == PWM_CH1) { + PWM->PSR &= PWM_PSR_PS1_Restart; + } + else if(PWM_CHn == PWM_CH2) { + PWM->PSR &= PWM_PSR_PS2_Restart; + } + else if(PWM_CHn == PWM_CH3) { + PWM->PSR &= PWM_PSR_PS3_Restart; + } + else if(PWM_CHn == PWM_CH4) { + PWM->PSR &= PWM_PSR_PS4_Restart; + } + else if(PWM_CHn == PWM_CH5) { + PWM->PSR &= PWM_PSR_PS5_Restart; + } + else if(PWM_CHn == PWM_CH6) { + PWM->PSR &= PWM_PSR_PS6_Restart; + } + else if(PWM_CHn == PWM_CH7) { + PWM->PSR &= PWM_PSR_PS7_Restart; + } +} + +void PWM_Multi_Restart(uint32_t psr_bit_flag) +{ + PWM->PSR &= ~psr_bit_flag; +} + + +uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->TCR; +} + +uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->PCR; +} + +uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->PR; +} + +void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_PR_FILTER(PR)); + + PWM_CHn->PR = PR; +} + +uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->MR; +} + +void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + PWM_CHn->MR = MR; +} + +uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->LR; +} + +void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + PWM_CHn->LR = LR; +} + +uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->UDMR; +} + +void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_CHn_UDMR(UDMR)); + + PWM_CHn->UDMR = UDMR; +} + +uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->TCMR; +} + +void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_CHn_TCMR(TCMR)); + + PWM_CHn->TCMR = TCMR; +} + +uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->PEEER; +} + +void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_CHn_PEEER(PEEER)); + + PWM_CHn->PEEER = PEEER; +} + +uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->CMR; +} + +void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_CHn_CMR(CMR)); + + PWM_CHn->CMR = CMR; +} + +uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn) +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->CR; +} + +uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->PDMR; +} + +void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_CHn_PDMR(PDMR)); + + PWM_CHn->PDMR = PDMR; +} + +uint32_t PWM_CHn_GetDZER(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->DZER; +} + +void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_CHn_DZER(DZER)); + + PWM_CHn->DZER = DZER; +} + +uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->DZCR; +} + +void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_CHn_DZCR_FILTER(DZCR)); + + PWM_CHn->DZCR = DZCR; +} + +void PWM_CH0_ClearMatchInt(void) +{ + PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_MatchInterruptClear); +} + +void PWM_CH0_ClearOverflowInt(void) +{ + PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_OverflowInterruptClear); +} + +void PWM_CH0_ClearCaptureInt(void) +{ + PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_CaptureInterruptClear); +} + +void PWM_CH1_ClearMatchInt(void) +{ + PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_MatchInterruptClear); +} + +void PWM_CH1_ClearOverflowInt(void) +{ + PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_OverflowInterruptClear); +} + +void PWM_CH1_ClearCaptureInt(void) +{ + PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_CaptureInterruptClear); +} + +void PWM_CH2_ClearMatchInt(void) +{ + PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_MatchInterruptClear); +} + +void PWM_CH2_ClearOverflowInt(void) +{ + PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_OverflowInterruptClear); +} + +void PWM_CH2_ClearCaptureInt(void) +{ + PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_CaptureInterruptClear); +} + +void PWM_CH3_ClearMatchInt(void) +{ + PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_MatchInterruptClear); +} + +void PWM_CH3_ClearOverflowInt(void) +{ + PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_OverflowInterruptClear); +} + +void PWM_CH3_ClearCaptureInt(void) +{ + PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_CaptureInterruptClear); +} + +void PWM_CH4_ClearMatchInt(void) +{ + PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_MatchInterruptClear); +} + +void PWM_CH4_ClearOverflowInt(void) +{ + PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_OverflowInterruptClear); +} + +void PWM_CH4_ClearCaptureInt(void) +{ + PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_CaptureInterruptClear); +} + +void PWM_CH5_ClearMatchInt(void) +{ + PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_MatchInterruptClear); +} + +void PWM_CH5_ClearOverflowInt(void) +{ + PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_OverflowInterruptClear); +} + +void PWM_CH5_ClearCaptureInt(void) +{ + PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_CaptureInterruptClear); +} + +void PWM_CH6_ClearMatchInt(void) +{ + PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_MatchInterruptClear); +} + +void PWM_CH6_ClearOverflowInt(void) +{ + PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_OverflowInterruptClear); +} + +void PWM_CH6_ClearCaptureInt(void) +{ + PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_CaptureInterruptClear); +} + +void PWM_CH7_ClearMatchInt(void) +{ + PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_MatchInterruptClear); +} + +void PWM_CH7_ClearOverflowInt(void) +{ + PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_OverflowInterruptClear); +} + +void PWM_CH7_ClearCaptureInt(void) +{ + PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_CaptureInterruptClear); +} diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.h new file mode 100644 index 0000000000..d3d44c376c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.h @@ -0,0 +1,289 @@ +/** + ****************************************************************************** + * @file + * @author + * @version + * @date + * @brief This file contains all the functions prototypes for the UART + * firmware library. + ****************************************************************************** + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __W7500X_PWM_H +#define __W7500X_PWM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "W7500x.h" + +/**********************************************************************************************/ +/**********************************************************************************************/ +// This structure and define must be in W7500x.h +/**********************************************************************************************/ +/**********************************************************************************************/ + +typedef struct +{ + uint32_t PWM_CHn_PEEER; +}PWM_CtrlPWMOutputTypeDef; + +typedef struct +{ + uint32_t PWM_CHn_PR; + uint32_t PWM_CHn_MR; + uint32_t PWM_CHn_LR; + uint32_t PWM_CHn_UDMR; + uint32_t PWM_CHn_PDMR; + uint32_t PWM_CHn_DZCR; +}PWM_DeadzoneModeInitTypDef; + +#define IS_PWM_ALL_CH(CHn) ((CHn == PWM_CH0) || \ + (CHn == PWM_CH1) || \ + (CHn == PWM_CH2) || \ + (CHn == PWM_CH3) || \ + (CHn == PWM_CH4) || \ + (CHn == PWM_CH5) || \ + (CHn == PWM_CH6) || \ + (CHn == PWM_CH7)) + +#define PWM_IER_IE0_Enable (0x1ul << 0) +#define PWM_IER_IE1_Enable (0x1ul << 1) +#define PWM_IER_IE2_Enable (0x1ul << 2) +#define PWM_IER_IE3_Enable (0x1ul << 3) +#define PWM_IER_IE4_Enable (0x1ul << 4) +#define PWM_IER_IE5_Enable (0x1ul << 5) +#define PWM_IER_IE6_Enable (0x1ul << 6) +#define PWM_IER_IE7_Enable (0x1ul << 7) + +#define PWM_IER_IE0_Disable ~PWM_IER_IE0_Enable +#define PWM_IER_IE1_Disable ~PWM_IER_IE1_Enable +#define PWM_IER_IE2_Disable ~PWM_IER_IE2_Enable +#define PWM_IER_IE3_Disable ~PWM_IER_IE3_Enable +#define PWM_IER_IE4_Disable ~PWM_IER_IE4_Enable +#define PWM_IER_IE5_Disable ~PWM_IER_IE5_Enable +#define PWM_IER_IE6_Disable ~PWM_IER_IE6_Enable +#define PWM_IER_IE7_Disable ~PWM_IER_IE7_Enable + +#define PWM_SSR_SS0_Start (0x1ul << 0) +#define PWM_SSR_SS1_Start (0x1ul << 1) +#define PWM_SSR_SS2_Start (0x1ul << 2) +#define PWM_SSR_SS3_Start (0x1ul << 3) +#define PWM_SSR_SS4_Start (0x1ul << 4) +#define PWM_SSR_SS5_Start (0x1ul << 5) +#define PWM_SSR_SS6_Start (0x1ul << 6) +#define PWM_SSR_SS7_Start (0x1ul << 7) + +#define PWM_SSR_SS0_Stop ~PWM_SSR_SS0_Start +#define PWM_SSR_SS1_Stop ~PWM_SSR_SS1_Start +#define PWM_SSR_SS2_Stop ~PWM_SSR_SS2_Start +#define PWM_SSR_SS3_Stop ~PWM_SSR_SS3_Start +#define PWM_SSR_SS4_Stop ~PWM_SSR_SS4_Start +#define PWM_SSR_SS5_Stop ~PWM_SSR_SS5_Start +#define PWM_SSR_SS6_Stop ~PWM_SSR_SS6_Start +#define PWM_SSR_SS7_Stop ~PWM_SSR_SS7_Start + +#define IS_SSR_BIT_FLAG(FLAG) (FLAG <= 0xFF) + +#define PWM_PSR_PS0_Pause (0x1ul << 0) +#define PWM_PSR_PS1_Pause (0x1ul << 1) +#define PWM_PSR_PS2_Pause (0x1ul << 2) +#define PWM_PSR_PS3_Pause (0x1ul << 3) +#define PWM_PSR_PS4_Pause (0x1ul << 4) +#define PWM_PSR_PS5_Pause (0x1ul << 5) +#define PWM_PSR_PS6_Pause (0x1ul << 6) +#define PWM_PSR_PS7_Pause (0x1ul << 7) + +#define PWM_PSR_PS0_Restart ~PWM_PSR_PS0_Pause +#define PWM_PSR_PS1_Restart ~PWM_PSR_PS1_Pause +#define PWM_PSR_PS2_Restart ~PWM_PSR_PS2_Pause +#define PWM_PSR_PS3_Restart ~PWM_PSR_PS3_Pause +#define PWM_PSR_PS4_Restart ~PWM_PSR_PS4_Pause +#define PWM_PSR_PS5_Restart ~PWM_PSR_PS5_Pause +#define PWM_PSR_PS6_Restart ~PWM_PSR_PS6_Pause +#define PWM_PSR_PS7_Restart ~PWM_PSR_PS7_Pause + +#define IS_PWM_PSR_BIT_FLAG(FLAG) (FLAG <= 0xFF) + +#define PWM_CHn_IER_MIE (0x1ul << 0) ///< Match Interrupt Enable +#define PWM_CHn_IER_OIE (0x1ul << 1) ///< Overflow Interrupt Enable +#define PWM_CHn_IER_CIE (0x1ul << 2) ///< Capture Interrupt Enable +#define IS_PWM_CHn_IER(FLAG) (FLAG <= 0x7) + +#define PWM_CHn_IER_MI_Msk (0x1ul << 0) ///< Match Interrupt Enable Mask +#define PWM_CHn_IER_OI_Msk (0x1ul << 1) ///< Overflow Interrupt Enable Mask +#define PWM_CHn_IER_CI_Msk (0x1ul << 2) ///< Capture Interrupt Enable Mask + +#define PWM_CHn_ICR_MatchInterruptClear (0x1ul << 0) +#define PWM_CHn_ICR_OverflowInterruptClear (0x1ul << 1) +#define PWM_CHn_ICR_CaptureInterruptClear (0x1ul << 2) +#define IS_PWM_CHn_IntClearFlag(FLAG) FLAG <= 0x7 + +/* +#define IS_PWM_STOP(CHn) (((CHn == PWM_CH0) && (PWM->SSR & PWM_SSR_SS0)) || \ + ((CHn == PWM_CH1) && (PWM->SSR & PWM_SSR_SS1)) || \ + ((CHn == PWM_CH2) && (PWM->SSR & PWM_SSR_SS2)) || \ + ((CHn == PWM_CH3) && (PWM->SSR & PWM_SSR_SS3)) || \ + ((CHn == PWM_CH4) && (PWM->SSR & PWM_SSR_SS4)) || \ + ((CHn == PWM_CH5) && (PWM->SSR & PWM_SSR_SS5)) || \ + ((CHn == PWM_CH6) && (PWM->SSR & PWM_SSR_SS6)) || \ + ((CHn == PWM_CH7) && (PWM->SSR & PWM_SSR_SS7))) +*/ + + +#define IS_PWM_PR_FILTER(MAXVAL) (MAXVAL <= 0x1F) + + +#define PWM_CHn_UDMR_UpCount (0x0ul) +#define PWM_CHn_UDMR_DownCount (0x1ul) +#define IS_PWM_CHn_UDMR(MODE) ((MODE == PWM_CHn_UDMR_UpCount) || \ + (MODE == PWM_CHn_UDMR_DownCount)) + +#define PWM_CHn_TCMR_TimerMode (0x0ul) +#define PWM_CHn_TCMR_RisingCounterMode (0x1ul) +#define PWM_CHn_TCMR_FallingCounterMode (0x2ul) +#define PWM_CHn_TCMR_BothCounterMode (0x3ul) +#define IS_PWM_CHn_TCMR(MODE) ((MODE == PWM_CHn_TCMR_RisingCounterMode) || \ + (MODE == PWM_CHn_TCMR_FallingCounterMode) || \ + (MODE == PWM_CHn_TCMR_BothCounterMode)) + +#define PWM_CHn_PEEER_Disable (0x0ul) +#define PWM_CHn_PEEER_ExtEnable (0x1ul) +#define PWM_CHn_PEEER_PWMEnable (0x2ul) +#define IS_PWM_CHn_PEEER(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \ + (ENABLE == PWM_CHn_PEEER_ExtEnable) || \ + (ENABLE == PWM_CHn_PEEER_PWMEnable)) + +#define IS_PWM_Output(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \ + (ENABLE == PWM_CHn_PEEER_PWMEnable)) + +#define PWM_CHn_CMR_RisingEdge 0x0ul +#define PWM_CHn_CMR_FallingEdge 0x1ul +#define IS_PWM_CHn_CMR(MODE) ((MODE == PWM_CHn_CMR_RisingEdge) || \ + (MODE == PWM_CHn_CMR_FallingEdge)) + +#define PWM_CHn_PDMR_Oneshot (0x0ul) +#define PWM_CHn_PDMR_Periodic (0x1ul) +#define IS_PWM_CHn_PDMR(MODE) ((MODE == PWM_CHn_PDMR_Periodic) || \ + (MODE == PWM_CHn_PDMR_Oneshot)) + +#define PWM_CHn_DZER_Enable (0x1ul) +#define PWM_CHn_DZER_Disable (0x0ul) +#define PWM_CHn_DZER(ENABLE) ((ENABLE == PWM_CHn_DZER_Enable) || \ + (ENABLE == PWM_CHn_DZER_Disable)) + +#define IS_PWM_Deadznoe(CHn) (((CHn == PWM_CH0) && (PWM_CH1->DZER == PWM_CHn_DZER_Disable)) || \ + ((CHn == PWM_CH1) && (PWM_CH0->DZER == PWM_CHn_DZER_Disable)) || \ + ((CHn == PWM_CH2) && (PWM_CH3->DZER == PWM_CHn_DZER_Disable)) || \ + ((CHn == PWM_CH3) && (PWM_CH2->DZER == PWM_CHn_DZER_Disable)) || \ + ((CHn == PWM_CH4) && (PWM_CH5->DZER == PWM_CHn_DZER_Disable)) || \ + ((CHn == PWM_CH5) && (PWM_CH4->DZER == PWM_CHn_DZER_Disable)) || \ + ((CHn == PWM_CH6) && (PWM_CH7->DZER == PWM_CHn_DZER_Disable)) || \ + ((CHn == PWM_CH7) && (PWM_CH6->DZER == PWM_CHn_DZER_Disable))) + +#define IS_PWM_CHn_DZCR_FILTER(MAXVAL) (MAXVAL <= 0x3FF) + + + + + + +void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn); +void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct); +void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct); +void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct); +void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct); +void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable ); +void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn) ; +void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn) ; +void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state); +FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state); +void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn); +void PWM_Multi_Start(uint32_t ssr_bit_flag); +void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn); +void PWM_Multi_Stop(uint32_t ssr_bit_flag); +void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn); +void PWM_Multi_Pause(uint32_t psr_bit_flag); +void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn); +void PWM_Multi_Restart(uint32_t psr_bit_flag); +uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn); +uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR); +uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn); +uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn); +uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR); +uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR); +uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR); +uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR); +uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR); +uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER); +uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR); +uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn); +uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR); +void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER); +uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR); +void PWM_CH0_ClearMatchInt(void); +void PWM_CH0_ClearOverflowInt(void); +void PWM_CH0_ClearCaptureInt(void); +void PWM_CH1_ClearMatchInt(void); +void PWM_CH1_ClearOverflowInt(void); +void PWM_CH1_ClearCaptureInt(void); +void PWM_CH2_ClearMatchInt(void); +void PWM_CH2_ClearOverflowInt(void); +void PWM_CH2_ClearCaptureInt(void); +void PWM_CH3_ClearMatchInt(void); +void PWM_CH3_ClearOverflowInt(void); +void PWM_CH3_ClearCaptureInt(void); +void PWM_CH4_ClearMatchInt(void); +void PWM_CH4_ClearOverflowInt(void); +void PWM_CH4_ClearCaptureInt(void); +void PWM_CH5_ClearMatchInt(void); +void PWM_CH5_ClearOverflowInt(void); +void PWM_CH5_ClearCaptureInt(void); +void PWM_CH6_ClearMatchInt(void); +void PWM_CH6_ClearOverflowInt(void); +void PWM_CH6_ClearCaptureInt(void); +void PWM_CH7_ClearMatchInt(void); +void PWM_CH7_ClearOverflowInt(void); +void PWM_CH7_ClearCaptureInt(void); + + +void PWM0_Handler(void); +void PWM1_Handler(void); +void PWM2_Handler(void); +void PWM3_Handler(void); +void PWM4_Handler(void); +void PWM5_Handler(void); +void PWM6_Handler(void); +void PWM7_Handler(void); + + + + +//Temporary macro======= +#define PWM_CH(N) ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + (N * 0x100UL))) +//====================== + + +#ifdef __cplusplus +} +#endif + + +#endif //__W7500X_PWM_H + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.c b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.c new file mode 100644 index 0000000000..67eba2e88d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.c @@ -0,0 +1,370 @@ +/** + ****************************************************************************** + * @file W7500x_uart.c + * @author + * @version + * @date + * @brief + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "W7500x.h" + +void UART_StructInit(UART_InitTypeDef* UART_InitStruct) +{ + /* UART_InitStruct members default value */ + UART_InitStruct->UART_BaudRate = 115200; + UART_InitStruct->UART_WordLength = UART_WordLength_8b ; + UART_InitStruct->UART_StopBits = UART_StopBits_1; + UART_InitStruct->UART_Parity = UART_Parity_No ; + UART_InitStruct->UART_Mode = UART_Mode_Rx | UART_Mode_Tx; + UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None ; +} + +void UART_DeInit(UART_TypeDef *UARTx) +{ + +} + +uint32_t UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct) +{ + float baud_divisor; + uint32_t tmpreg=0x00, uartclock=0x00; + uint32_t integer_baud = 0x00, fractional_baud = 0x00; + + assert_param(IS_UART_01_PERIPH(UARTx)); + assert_param(IS_UART_WORD_LENGTH(UART_InitStruct->UART_WordLength)); + assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity)); + assert_param(IS_UART_STOPBITS(UART_InitStruct->UART_StopBits)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(UART_InitStruct->UART_HardwareFlowControl)); + assert_param(IS_UART_MODE(UART_InitStruct->UART_Mode)); + + + UARTx->CR &= ~(UART_CR_UARTEN); + + // Set baudrate + CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_RCLK; // Set UART Clock using internal Oscilator ( 8MHz ) + uartclock = (8000000UL) / (1 << CRG->UARTCLK_PVSR); + + baud_divisor = ((float)uartclock / (16 * UART_InitStruct->UART_BaudRate)); + integer_baud = (uint32_t)baud_divisor; + fractional_baud = (uint32_t)((baud_divisor - integer_baud) * 64 + 0.5); + + UARTx->IBRD = integer_baud; + UARTx->FBRD = fractional_baud; + + + tmpreg = UARTx->LCR_H; + tmpreg &= ~(0x00EE); + tmpreg |= (UART_InitStruct->UART_WordLength | UART_InitStruct->UART_StopBits | UART_InitStruct->UART_Parity); + UARTx->LCR_H |= tmpreg; + + tmpreg = UARTx->CR; + tmpreg &= ~(UART_CR_CTSEn | UART_CR_RTSEn | UART_CR_RXE | UART_CR_TXE | UART_CR_UARTEN); + tmpreg |= (UART_InitStruct->UART_Mode | UART_InitStruct->UART_HardwareFlowControl); + UARTx->CR |= tmpreg; + + UARTx->CR |= UART_CR_UARTEN; + + return 0; +} + + +void UART_SendData(UART_TypeDef* UARTx, uint16_t Data) +{ + assert_param(IS_UART_01_PERIPH(UARTx)); + + UARTx->DR = Data; +} + + +uint16_t UART_ReceiveData(UART_TypeDef* UARTx) +{ + assert_param(IS_UART_01_PERIPH(UARTx)); + + return (uint16_t)(UARTx->DR); +} + + +void UART_SendBreak(UART_TypeDef* UARTx) +{ + assert_param(IS_UART_01_PERIPH(UARTx)); + + UARTx->LCR_H |= UART_LCR_H_BRK; +} + + +FlagStatus UART_GetRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS) +{ + FlagStatus bitstatus = RESET; + + assert_param(IS_UART_01_PERIPH(UARTx)); + assert_param(IS_UART_RECV_STATUS(UART_RECV_STATUS)); + + if( (UARTx->STATUS.RSR & UART_RECV_STATUS) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + +void UART_ClearRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS) +{ + assert_param(IS_UART_01_PERIPH(UARTx)); + assert_param(IS_UART_RECV_STATUS(UART_RECV_STATUS)); + + UARTx->STATUS.ECR = (uint16_t)UART_RECV_STATUS; +} + + +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG) +{ + FlagStatus bitstatus = RESET; + + assert_param(IS_UART_01_PERIPH(UARTx)); + assert_param(IS_UART_FLAG(UART_FLAG)); + + if ((UARTx->FR & UART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; + +} + +/* +void UART_ClearFlag(UART_TypeDef* UARTx, uint16_t UART_FLAG) +{ + +} +*/ + +void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState) +{ + assert_param(IS_UART_01_PERIPH(UARTx)); + assert_param(IS_UART_IT_FLAG(UART_IT)); + + if ( NewState != DISABLE ) + { + UARTx->IMSC |= UART_IT; + } + else + { + UARTx->ICR |= UART_IT; + } +} + + +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT) +{ + ITStatus bitstatus = RESET; + + assert_param(IS_UART_01_PERIPH(UARTx)); + assert_param(IS_UART_IT_FLAG(UART_IT)); + + if ((UARTx->MIS & UART_IT) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT) +{ + assert_param(IS_UART_01_PERIPH(UARTx)); + assert_param(IS_UART_IT_FLAG(UART_IT)); + + UARTx->ICR |= UART_IT; +} + + +void S_UART_DeInit() +{ + +} + +uint32_t S_UART_Init(uint32_t baud) +{ + uint32_t tmpreg=0x00; + uint32_t uartclock = 0x00, integer_baud = 0x00; + + assert_param(IS_UART_MODE(S_UART_InitStruct->UART_Mode)); + + if(CRG->FCLK_SSR == CRG_FCLK_SSR_RCLK) + { + uartclock = INTERN_XTAL; + } + else if(CRG->FCLK_SSR == CRG_FCLK_SSR_OCLK) + { + uartclock = EXTERN_XTAL; + } + else + { + uartclock = GetSystemClock(); + } + + integer_baud = (uint32_t)(uartclock / baud); + UART2->BAUDDIV = integer_baud; + + tmpreg = UART2->CTRL; + tmpreg &= ~(S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN); + tmpreg |= (S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN); + UART2->CTRL = tmpreg; + + return 0; +} + +void S_UART_SendData(uint16_t Data) +{ + while(UART2->STATE & S_UART_STATE_TX_BUF_FULL); + UART2->DATA = Data; +} + +uint16_t S_UART_ReceiveData() +{ + return (uint16_t)(UART2->DATA); +} + + +FlagStatus S_UART_GetFlagStatus(uint16_t S_UART_FLAG) +{ + FlagStatus bitstatus = RESET; + + assert_param(IS_S_UART_FLAG(S_UART_FLAG)); + + if ((UART2->STATE & S_UART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + +void S_UART_ITConfig(uint16_t S_UART_IT, FunctionalState NewState) +{ + assert_param(IS_S_UART_IT_FLAG(S_UART_IT)); + + if ( NewState != DISABLE ) + { + UART2->CTRL |= S_UART_IT; + } + else + { + UART2->CTRL &= ~(S_UART_IT); + } +} + +ITStatus S_UART_GetITStatus(uint16_t S_UART_IT) +{ + ITStatus bitstatus = RESET; + + assert_param(IS_S_UART_IT_FLAG(S_UART_IT)); + + if ((UART2->INT.STATUS & (S_UART_IT >> 2)) != (uint16_t) RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +void S_UART_ClearITPendingBit(uint16_t S_UART_IT) +{ + assert_param(IS_S_UART_IT_FLAG(S_UART_IT)); + + UART2->INT.CLEAR |= (S_UART_IT >> 2); +} + + +/**************************************************/ +// It will be moved to application board's driver */ +/**************************************************/ +uint8_t UartPutc(UART_TypeDef* UARTx, uint8_t ch) +{ + UART_SendData(UARTx,ch); + + while(UARTx->FR & UART_FR_BUSY); + + return (ch); +} + +void UartPuts(UART_TypeDef* UARTx, uint8_t *str) +{ + uint8_t ch; + + do{ + ch = *str; + if(ch != (uint8_t)0x0) + { + UartPutc(UARTx, ch); + } + *str++; + }while(ch != 0); +} + +uint8_t UartGetc(UART_TypeDef* UARTx) +{ + while(UARTx->FR & UART_FR_RXFE); + + return (UARTx->DR & 0xFF); +} + + +uint8_t S_UartPutc(uint8_t ch) +{ + S_UART_SendData(ch); + + return (ch); +} + +void S_UartPuts(uint8_t *str) +{ + uint8_t ch; + + do{ + ch = *str; + if(ch != (uint8_t)0x0) + { + S_UART_SendData(ch); + } + *str++; + }while(ch != 0); +} + +uint8_t S_UartGetc() +{ + while( (UART2->STATE & S_UART_STATE_RX_BUF_FULL) == 0 ); + return (uint8_t)S_UART_ReceiveData(); +} + + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.h new file mode 100644 index 0000000000..791978b237 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.h @@ -0,0 +1,289 @@ +/** + ****************************************************************************** + * @file + * @author + * @version + * @date + * @brief This file contains all the functions prototypes for the UART + * firmware library. + ****************************************************************************** + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __W7500X_UART_H +#define __W7500X_UART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "W7500x.h" + + +/** + * @brief UART Init Structure definition + */ + +typedef struct +{ + uint32_t UART_BaudRate; + uint16_t UART_WordLength; + uint16_t UART_StopBits; + uint16_t UART_Parity; + uint16_t UART_Mode; + uint16_t UART_HardwareFlowControl; +} UART_InitTypeDef; + +/** + * @} + */ + + +/** @defgroup UART_Exported_Constants + * @{ + */ + +#define IS_UART_01_PERIPH(PERIPH) (((PERIPH) == UART0) || ((PERIPH) == UART1)) +#define IS_UART_2_PERIPH(PERIPH) ((PERIPH) == UART2) + +/** + * @} + */ + + + +/** @addtogroup UART_Word_Length + * @{ + */ + +#define UART_WordLength_8b ((uint16_t)UART_LCR_H_WLEN(3)) +#define UART_WordLength_7b ((uint16_t)UART_LCR_H_WLEN(2)) +#define UART_WordLength_6b ((uint16_t)UART_LCR_H_WLEN(1)) +#define UART_WordLength_5b ((uint16_t)UART_LCR_H_WLEN(0)) +#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WordLength_8b) || \ + ((LENGTH) == UART_WordLength_7b) || \ + ((LENGTH) == UART_WordLength_6b) || \ + ((LENGTH) == UART_WordLength_5b) ) +/** + * @} + */ + + +/** @addtogroup UART_Parity + * @{ + */ + +#define UART_Parity_No ((uint16_t)0x0000) +#define UART_Parity_Even ((uint16_t)(UART_LCR_H_PEN | UART_LCR_H_EPS)) +#define UART_Parity_Odd ((uint16_t)(UART_LCR_H_PEN)) +#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_No) || \ + ((PARITY) == UART_Parity_Even) || \ + ((PARITY) == UART_Parity_Odd)) + +/** + * @} + */ + + +/** @addtogroup UART_Stop_Bits + * @{ + */ + +#define UART_StopBits_1 ((uint16_t)0x0000) +#define UART_StopBits_2 ((uint16_t)(UART_LCR_H_STP2)) +#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_StopBits_1) || \ + ((STOPBITS) == UART_StopBits_2)) +/** + * @} + */ + + +/** @addtogroup UART_Mode + * @{ + */ + +#define UART_Mode_Rx ((uint16_t)(UART_CR_RXE)) +#define UART_Mode_Tx ((uint16_t)(UART_CR_TXE)) +#define IS_UART_MODE(MODE) (((MODE) == UART_Mode_Rx) || \ + ((MODE) == UART_Mode_Tx)) + +/** + * @} + */ + + +/** @addtogroup UART_Hardware_Flow_Control + * @{ + */ + +#define UART_HardwareFlowControl_None ((uint16_t)0x0000) +#define UART_HardwareFlowControl_RTS ((uint16_t)UART_CR_RTSEn) +#define UART_HardwareFlowControl_CTS ((uint16_t)UART_CR_CTSEn) +#define UART_HardwareFlowControl_RTS_CTS ((uint16_t)(UART_CR_RTSEn | UART_CR_CTSEn)) +#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL) \ + (((CONTROL) == UART_HardwareFlowControl_None) || \ + ((CONTROL) == UART_HardwareFlowControl_RTS) || \ + ((CONTROL) == UART_HardwareFlowControl_CTS) || \ + ((CONTROL) == UART_HardwareFlowControl_RTS_CTS)) +/** + * @} + */ + + +/** @addtogroup UART_Receive Status + * @{ + */ + +#define UART_RECV_STATUS_OE ((uint16_t)0x01UL << 3) /*!< Overrun error */ +#define UART_RECV_STATUS_BE ((uint16_t)0x01UL << 2) /*!< Break error */ +#define UART_RECV_STATUS_PE ((uint16_t)0x01UL << 1) /*!< Parity error */ +#define UART_RECV_STATUS_FE ((uint16_t)0x01UL << 0) /*!< Framing error */ +#define IS_UART_RECV_STATUS(FLAG) (((FLAG) == UART_RECV_STATUS_OE) || ((FLAG) == UART_RECV_STATUS_BE) || \ + ((FLAG) == UART_RECV_STATUS_PE) || ((FLAG) == UART_RECV_STATUS_FE)) +/** + * @} + */ + + + +/** @addtogroup UART_Flags + * @{ + */ + +#define UART_FLAG_RI ((uint16_t)0x01UL << 8) /*!< Ring indicator */ +#define UART_FLAG_TXFE ((uint16_t)0x01UL << 7) /*!< Transmit FIFO empty */ +#define UART_FLAG_RXFF ((uint16_t)0x01UL << 6) /*!< Receive FIFO full */ +#define UART_FLAG_TXFF ((uint16_t)0x01UL << 5) /*!< Transmit FIFO full */ +#define UART_FLAG_RXFE ((uint16_t)0x01UL << 4) /*!< Receive FIFO empty */ +#define UART_FLAG_BUSY ((uint16_t)0x01UL << 3) /*!< UART busy */ +#define UART_FLAG_DCD ((uint16_t)0x01UL << 2) /*!< Data carrier detect */ +#define UART_FLAG_DSR ((uint16_t)0x01UL << 1) /*!< Data set ready */ +#define UART_FLAG_CTS ((uint16_t)0x01UL << 0) /*!< Clear to send */ +#define IS_UART_FLAG(FLAG) (((FLAG) == UART_FLAG_RI) || ((FLAG) == UART_FLAG_TXFE) || \ + ((FLAG) == UART_FLAG_RXFF) || ((FLAG) == UART_FLAG_TXFF) || \ + ((FLAG) == UART_FLAG_RXFE) || ((FLAG) == UART_FLAG_BUSY) || \ + ((FLAG) == UART_FLAG_DCD) || ((FLAG) == UART_FLAG_DSR) || \ + ((FLAG) == UART_FLAG_CTS)) + +/** + * @} + */ + + +/** @addtogroup UART_IT_Flags + * @{ + */ + +#define UART_IT_FLAG_OEI ((uint16_t)0x01UL << 10) /*!< Overrun error interrupt */ +#define UART_IT_FLAG_BEI ((uint16_t)0x01UL << 9) /*!< Break error interrupt */ +#define UART_IT_FLAG_PEI ((uint16_t)0x01UL << 8) /*!< Parity error interrupt */ +#define UART_IT_FLAG_FEI ((uint16_t)0x01UL << 7) /*!< Framing error interrupt */ +#define UART_IT_FLAG_RTI ((uint16_t)0x01UL << 6) /*!< Receive timeout interrupt */ +#define UART_IT_FLAG_TXI ((uint16_t)0x01UL << 5) /*!< Transmit interrupt */ +#define UART_IT_FLAG_RXI ((uint16_t)0x01UL << 4) /*!< Receive interrupt */ +#define UART_IT_FLAG_DSRMI ((uint16_t)0x01UL << 3) /*!< UARTDSR modem interrupt */ +#define UART_IT_FLAG_DCDMI ((uint16_t)0x01UL << 2) /*!< UARTDCD modem interrupt */ +#define UART_IT_FLAG_CTSMI ((uint16_t)0x01UL << 1) /*!< UARTCTS modem interrupt */ +#define UART_IT_FLAG_RIMI ((uint16_t)0x01UL << 0) /*!< UARTRI modem interrupt */ +#define IS_UART_IT_FLAG(FLAG) (((FLAG) == UART_IT_FLAG_OEI) || ((FLAG) == UART_IT_FLAG_BEI) || \ + ((FLAG) == UART_IT_FLAG_PEI) || ((FLAG) == UART_IT_FLAG_FEI) || \ + ((FLAG) == UART_IT_FLAG_RTI) || ((FLAG) == UART_IT_FLAG_TXI) || \ + ((FLAG) == UART_IT_FLAG_RXI) || ((FLAG) == UART_IT_FLAG_DSRMI) || \ + ((FLAG) == UART_IT_FLAG_DCDMI)|| ((FLAG) == UART_IT_FLAG_CTSMI) || \ + ((FLAG) == UART_IT_FLAG_RIMI)) +/** + * @} + */ +/** @addtogroup UART_FIFO_Level Select + * @{ + */ + +#define UART_IFLS_RXIFLSEL7_8 ((uint16_t)(UART_IFLS_RXIFLSEL(4))) +#define UART_IFLS_RXIFLSEL3_4 ((uint16_t)(UART_IFLS_RXIFLSEL(3))) +#define UART_IFLS_RXIFLSEL1_2 ((uint16_t)(UART_IFLS_RXIFLSEL(2))) +#define UART_IFLS_RXIFLSEL1_4 ((uint16_t)(UART_IFLS_RXIFLSEL(1))) +#define UART_IFLS_RXIFLSEL1_8 ((uint16_t)(UART_IFLS_RXIFLSEL(0))) +#define UART_IFLS_TXIFLSEL7_8 ((uint16_t)(UART_IFLS_TXIFLSEL(4))) +#define UART_IFLS_TXIFLSEL3_4 ((uint16_t)(UART_IFLS_TXIFLSEL(3))) +#define UART_IFLS_TXIFLSEL1_2 ((uint16_t)(UART_IFLS_TXIFLSEL(2))) +#define UART_IFLS_TXIFLSEL1_4 ((uint16_t)(UART_IFLS_TXIFLSEL(1))) +#define UART_IFLS_TXIFLSEL1_8 ((uint16_t)(UART_IFLS_TXIFLSEL(0))) + +#define IS_UART_FIFO_Level(FLAG) (((FLAG) == UART_IFLS_RXIFLSEL7_8) || ((FLAG) == UART_IFLS_RXIFLSEL3_4)|| \ + ((FLAG) == UART_IFLS_RXIFLSEL1_2)|| ((FLAG) == UART_IFLS_RXIFLSEL1_4)|| ((FLAG) == UART_IFLS_RXIFLSEL1_8)||\ + ((FLAG) == UART_IFLS_TXIFLSEL7_8)|| ((FLAG) == UART_IFLS_TXIFLSEL3_4)|| \ + ((FLAG) == UART_IFLS_TXIFLSEL1_2)|| ((FLAG) == UART_IFLS_TXIFLSEL1_4)||((FLAG) == UART_IFLS_TXIFLSEL1_8)) + +/** + * @} + */ + +/** @addtogroup S_UART_Flags + * @{ + */ +#define S_UART_FLAG_RXO ((uint16_t)0x01UL << 3) /*!< RX buffer Overrun */ +#define S_UART_FLAG_TXO ((uint16_t)0x01UL << 2) /*!< TX buffer Overrun */ +#define S_UART_FLAG_RXF ((uint16_t)0x01UL << 1) /*!< RX buffer Full */ +#define S_UART_FLAG_TXF ((uint16_t)0x01UL << 0) /*!< TX buffer Full */ +#define IS_S_UART_FLAG(FLAG) (((FLAG) == S_UART_FLAG_RXO) || ((FLAG) == S_UART_FLAG_TXO) || \ + ((FLAG) == S_UART_FLAG_RXF) || ((FLAG) == S_UART_FLAG_TXF)) +/** + * @} + */ + + +/** @addtogroup S_UART_IT_Flags + * @{ + */ + +#define S_UART_IT_FLAG_RXOI ((uint16_t)0x01UL << 5) /*!< RX overrun interrupt */ +#define S_UART_IT_FLAG_TXOI ((uint16_t)0x01UL << 4) /*!< TX overrun interrupt */ +#define S_UART_IT_FLAG_RXI ((uint16_t)0x01UL << 3) /*!< RX interrupt */ +#define S_UART_IT_FLAG_TXI ((uint16_t)0x01UL << 2) /*!< TX interrupt */ +#define IS_S_UART_IT_FLAG(FLAG) (((FLAG) == S_UART_IT_FLAG_RXOI) || ((FLAG) == S_UART_IT_FLAG_TXOI) || \ + ((FLAG) == S_UART_IT_FLAG_RXI) || ((FLAG) == S_UART_IT_FLAG_TXI)) + +/** + * @} + */ + + +void UART_StructInit (UART_InitTypeDef* UART_InitStruct); + +uint32_t UART_Init (UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct); +void UART_SendData (UART_TypeDef* UARTx, uint16_t Data); +uint16_t UART_ReceiveData (UART_TypeDef* UARTx); +void UART_SendBreak (UART_TypeDef* UARTx); +void UART_ClearRecvStatus (UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS); +FlagStatus UART_GetFlagStatus (UART_TypeDef* UARTx, uint16_t UART_FLAG); +void UART_ITConfig (UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState); +ITStatus UART_GetITStatus (UART_TypeDef* UARTx, uint16_t UART_IT); +void UART_ClearITPendingBit (UART_TypeDef* UARTx, uint16_t UART_IT); + + +void S_UART_DeInit(void); +uint32_t S_UART_Init(uint32_t baud); +void S_UART_SendData(uint16_t Data); +uint16_t S_UART_ReceiveData(void); + + + +uint8_t UartPutc (UART_TypeDef* UARTx, uint8_t ch); +void UartPuts (UART_TypeDef* UARTx, uint8_t *str); +uint8_t UartGetc (UART_TypeDef* UARTx); + +uint8_t S_UartPutc(uint8_t ch); +void S_UartPuts(uint8_t *str); +uint8_t S_UartGetc(void); + + +#ifdef __cplusplus +} +#endif + + +#endif // __W7500X_UART_H + diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h new file mode 100644 index 0000000000..9a5d507fa7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h @@ -0,0 +1,26 @@ +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + + +//*** ADC *** +extern const PinMap PinMap_ADC[]; + +//*** SERIAL *** +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +//*** I2C *** +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + + +//*** SPI *** + +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralNames.h new file mode 100644 index 0000000000..e0bacfc987 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralNames.h @@ -0,0 +1,77 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PinNames.h" +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_0 = (int)W7500x_ADC_BASE +} ADCName; + +typedef enum { + UART_0 = (int)W7500x_UART0_BASE, + UART_1 = (int)W7500x_UART1_BASE +} UARTName; + +#define STDIO_UART_TX PC_2 +#define STDIO_UART_RX PC_3 +#define STDIO_UART UART_1 + +typedef enum { + SPI_0 = (int)SSP0_BASE, + SPI_1 = (int)SSP1_BASE +} SPIName; + +typedef enum { + I2C_0 = (int)I2C0_BASE, + I2C_1 = (int)I2C1_BASE +} I2CName; + +typedef enum { + PWM_1 = 0 +// PWM_1 = (int)TIM1_BASE, +// PWM_3 = (int)TIM3_BASE, +// PWM_14 = (int)TIM14_BASE, +// PWM_15 = (int)TIM15_BASE, +// PWM_16 = (int)TIM16_BASE, +// PWM_17 = (int)TIM17_BASE +} PWMName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c new file mode 100644 index 0000000000..136a93f8cb --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c @@ -0,0 +1,106 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" +#include "PeripheralNames.h" +#include "pinmap.h" + + +//*** ADC *** +const PinMap PinMap_ADC[] = { + {PC_15, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN0 + {PC_14, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN1 + {PC_13, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN2 + {PC_12, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN3 + {PC_11, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN4 + {PC_10, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN5 + {NC, NC, 0} +}; + + +//*** SERIAL *** +const PinMap PinMap_UART_TX[] = { + {PA_14, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {PC_2, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_13, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {PC_3, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {NC, NC, 0} +}; + +//*** I2C *** +const PinMap PinMap_I2C_SDA[] = { + {PA_10, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_SCLK[] = { + {PA_6 , SPI_0, 0}, + {PB_1 , SPI_1, 0}, + {PC_12, SPI_0, 3}, + {PA_12, SPI_1, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {PA_8 , SPI_0, 0}, + {PB_3 , SPI_1, 0}, + {PC_10, SPI_0, 3}, + {PA_14, SPI_1, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_7 , SPI_0, 0}, + {PB_2 , SPI_1, 0}, + {PC_11, SPI_0, 3}, + {PA_13, SPI_1, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_5 , SPI_0, 0}, + {PB_0 , SPI_1, 0}, + {PC_13, SPI_0, 3}, + {PA_11, SPI_1, 3}, + {NC , NC , 0} +}; + diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PinNames.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PinNames.h new file mode 100644 index 0000000000..5233ccec2d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PinNames.h @@ -0,0 +1,197 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +// See W7500x_hal_gpio.h for values of MODE, PUPD and AFNUM +#define WIZ_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 8) | ((PUPD) << 4) | ((MODE) << 0))) +#define WIZ_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define WIZ_PIN_PUPD(X) (((X) >> 4) & 0x0F) +#define WIZ_PIN_AFNUM(X) (((X) >> 8) & 0x0F) +#define WIZ_MODE_INPUT (0) +#define WIZ_MODE_OUTPUT (1) +#define WIZ_MODE_AF (2) + +#define WIZ_GPIO_NOPULL (0) /*!< No Pull-up or Pull-down activation */ +#define WIZ_GPIO_PULLDOWN (1) /*!< Pull-down activation */ +#define WIZ_GPIO_PULLUP (2) /*!< Pull-up activation */ +#define WIZ_GPIO_OPEN_DRAIN (3) /*!< Open Drain activation */ + + +#define WIZ_AFNUM(X)(((uint32_t)(X) >> 8) & 0xF) // AF number (0=AF0, 1=AF1, 2=AF2, 3=AF3) +#define WIZ_PORT(X) (((uint32_t)(X) >> 4) & 0xF) // port number (0=A, 1=B, 2=C, 3=D) +#define WIZ_PIN(X) ((uint32_t)(X) & 0xF) // pin number + + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + + +typedef enum { + // W7500x Pin Names (AF[9:8] + PORT[5:4] + PIN[3:0]) + + PA_0 = 0x000, + PA_1 = 0x001, + PA_2 = 0x002, + PA_3 = 0x003, + PA_4 = 0x004, + PA_5 = 0x005, + PA_6 = 0x006, + PA_7 = 0x007, + PA_8 = 0x008, + PA_9 = 0x009, + PA_10 = 0x00A, + PA_11 = 0x00B, + PA_12 = 0x00C, + PA_13 = 0x00D, + PA_14 = 0x00E, + PA_15 = 0x00F, + + PB_0 = 0x010, //SSEL1/SD_SEL + PB_1 = 0x011, //SCLK1/SD_CLK + PB_2 = 0x012, //MISO1/SD_MISO + PB_3 = 0x013, //MOSI1/SD_MOSI + PB_4 = 0x014, + PB_5 = 0x015, + PB_6 = 0x016, + PB_7 = 0x017, + PB_8 = 0x018, + PB_9 = 0x019, + PB_10 = 0x01A, + PB_11 = 0x01B, + PB_12 = 0x01C, + PB_13 = 0x01D, + PB_14 = 0x01E, + PB_15 = 0x01F, + + PC_0 = 0x120, // 0xx:U_CTS1, 1xx:GPIOC_0, 2xx:PWM0 + PC_1 = 0x121, // 0xx:U_RTS1, 1xx:GPIOC_1, 2xx:PWM1 + PC_2 = 0x022, + PC_3 = 0x023, + PC_4 = 0x124, // 0xx:SDA1, 1xx:GPIOC_4, 2xx:PWM4 + PC_5 = 0x025, + PC_6 = 0x026, + PC_7 = 0x027, + PC_8 = 0x128, // 0xx:PWM0, 1xx:GPIOC_8, 2xx:SCL0, 3xx:AIN7 + PC_9 = 0x129, // 0xx:PWM1, 1xx:GPIOC_9, 2xx:SDA0, 3xx:AIN6 + + PC_10 = 0x32A, // 0xx:U_TXD2, 1xx:GPIOC_10, 2xx:PWM2, 3xx:AIN5 + PC_11 = 0x32B, // 0xx:U_RXD2, 1xx:GPIOC_11, 2xx:PWM3, 3xx:AIN4 + PC_12 = 0x32C, // 0xx:AIN3, 1xx:GPIOC_12, 2xx:SSEL0, 3xx:AIN3 + PC_13 = 0x32D, // 0xx:AIN2, 1xx:GPIOC_13, 2xx:SCLK0, 3xx:AIN2 + PC_14 = 0x32E, // 0xx:AIN1, 1xx:GPIOC_14, 2xx:MISO0, 3xx:AIN1 + PC_15 = 0x32F, // 0xx:AIN0, 1xx:GPIOC_15, 2xx:MOSI0, 3xx:AIN0 + + PD_0 = 0x030, + PD_1 = 0x031, + PD_2 = 0x032, + PD_3 = 0x033, + PD_4 = 0x034, + + + // Arduino connector namings + A0 = PC_15, // AIN0 + A1 = PC_14, // AIN1 + A2 = PC_13, // AIN2 + A3 = PC_12, // AIN3 + A4 = PC_11, // AIN4 + A5 = PC_10, // AIN5 + D0 = PA_14, // U_TXD0 + D1 = PA_13, // U_RXD0 + D2 = PC_1, // GPIOC_1, EXTI + D3 = PC_0, // GPIOC_0, EXTI + D4 = PA_2, // GPIOA_2, + D5 = PA_1, // GPIOA_1, + D6 = PA_0, // GPIOA_0, + D7 = PC_6, // GPIOC_6, EXTI + D8 = PC_7, // GPIOC_7, EXTI + D9 = PC_4, // GPIOC_4, EXTI + D10 = PA_5, // SSEL0 + D11 = PA_8, // MOSI0 + D12 = PA_7, // MISO0 + D13 = PA_6, // SCLK0 + D14 = PA_10, // SDA0 + D15 = PA_9, // SCL0 + + // Generic signals namings + LED_RED = PC_8, + LED_GREEN = PC_9, + LED_BLUE = PC_5, + + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + LED4 = LED_BLUE, + +// USER_BUTTON = PC_13, + SERIAL_TX = PC_2, // U_TXD1 + SERIAL_RX = PC_3, // U_RXD1 + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + I2C_SCL = PA_9, // SCL0 + I2C_SDA = PA_10, // SDA0 + SPI_MOSI = PA_8, // MISO0 + SPI_MISO = PA_7, // MOSI0 + SPI_SCK = PA_9, // SCL0 + SPI_CS = PA_5, // SSEL0 + SD_SEL = PB_0, // SSEL1 + SD_CLK = PB_1, // SCL1 + SD_MISO = PB_2, // MOSI1 + SD_MOSI = PB_3, // MISO1 +// PWM_OUT = PC_7, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + OpenDrain = 3, + PullDefault = PullNone +} PinMode; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PortNames.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PortNames.h new file mode 100644 index 0000000000..0eb8287078 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PortNames.h @@ -0,0 +1,48 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h new file mode 100644 index 0000000000..9973c40578 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h @@ -0,0 +1,74 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 // Not present on this device + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +#define DEVICE_ETHERNET 0 + + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/objects.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/objects.h new file mode 100644 index 0000000000..7a3b8967ba --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/objects.h @@ -0,0 +1,98 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "PortNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct analogin_s { + ADCName adc; + PinName pin; +}; + +struct serial_s { + UARTName uart; + int index; // Used by irq + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + PinName pin_tx; + PinName pin_rx; +}; + +struct spi_s { + SSP_TypeDef *spi; +}; + +struct i2c_s { + I2CName i2c; + uint16_t ADDRESS; + uint16_t is_setAddress; +}; + +struct pwmout_s { + PWMName pwm; + PinName pin; + uint32_t period; + uint32_t pulse; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c new file mode 100644 index 0000000000..af28f7924e --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c @@ -0,0 +1,102 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed_assert.h" +#include "analogin_api.h" + +#if DEVICE_ANALOGIN + +#include "wait_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" + + +ADC_TypeDef * AdcHandle; + +int adc_inited = 0; + +void analogin_init(analogin_t *obj, PinName pin) +{ + // Get the peripheral name from the pin and assign it to the object + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + + MBED_ASSERT(obj->adc != (ADCName)NC); + + // Configure GPIO + pinmap_pinout(pin, PinMap_ADC); + + // Save pin number for the read function + obj->pin = pin; + + // The ADC initialization is done once + if (adc_inited == 0) { + adc_inited = 1; + + ADC_Init(); + } +} + +static inline uint16_t adc_read(analogin_t *obj) +{ + ADC_CH adc_ch; + + switch (obj->pin) { + case PC_15: + adc_ch = ADC_CH0; + break; + case PC_14: + adc_ch = ADC_CH1; + break; + case PC_13: + adc_ch = ADC_CH2; + break; + case PC_12: + adc_ch = ADC_CH3; + break; + case PC_11: + adc_ch = ADC_CH4; + break; + case PC_10: + adc_ch = ADC_CH5; + break; + default: + return 0; + } + + ADC_ChannelSelect(adc_ch); + ADC_Start(); + + // Wait end of conversion and get value + while(ADC_IsInterrupt()); + return ADC_ReadData(); +} + +uint16_t analogin_read_u16(analogin_t *obj) +{ + uint16_t value = adc_read(obj); + // 12-bit to 16-bit conversion + return value; +} + +float analogin_read(analogin_t *obj) +{ + uint16_t value = adc_read(obj); + + return (float)value * (1.0f / (float)0xFFF); // 12 bits range +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogout_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogout_api.c new file mode 100644 index 0000000000..5b77b3febe --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogout_api.c @@ -0,0 +1,64 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed_assert.h" +#include "analogout_api.h" + +#if DEVICE_ANALOGOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "PeripheralPins.h" + +#define DAC_RANGE (0xFFF) // 12 bits + +static DAC_HandleTypeDef DacHandle; + +void analogout_init(dac_t *obj, PinName pin) +{ + +} + +void analogout_free(dac_t *obj) +{ +} + +static inline void dac_write(dac_t *obj, uint16_t value) +{ +} + +static inline int dac_read(dac_t *obj) +{ +} + +void analogout_write(dac_t *obj, float value) +{ +} + +void analogout_write_u16(dac_t *obj, uint16_t value) +{ +} + +float analogout_read(dac_t *obj) +{ +} + +uint16_t analogout_read_u16(dac_t *obj) +{ +} + +#endif // DEVICE_ANALOGOUT diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_api.c new file mode 100644 index 0000000000..635a73c176 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_api.c @@ -0,0 +1,62 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "gpio_api.h" +#include "pinmap.h" + +extern uint32_t Get_GPIO_BaseAddress(uint32_t port_idx); + +uint32_t gpio_set(PinName pin) +{ + MBED_ASSERT(pin != (PinName)NC); + + pin_function(pin, WIZ_PIN_DATA(WIZ_MODE_INPUT, WIZ_GPIO_NOPULL, 0)); + + return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask +} + +void gpio_init(gpio_t *obj, PinName pin) +{ + obj->pin = pin; + if (pin == (PinName)NC) { + return; + } + + uint32_t port_index = WIZ_PORT(pin); + + GPIO_TypeDef *gpio = (GPIO_TypeDef *)Get_GPIO_BaseAddress(port_index); + + // Fill GPIO object structure for future use + obj->mask = gpio_set(pin); + obj->reg_data_in = &gpio->DATA; +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + pin_mode(obj->pin, mode); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + MBED_ASSERT(obj->pin != (PinName)NC); + obj->direction = direction; + + if (direction == PIN_OUTPUT) { + pin_function(obj->pin, WIZ_PIN_DATA(WIZ_MODE_OUTPUT, WIZ_GPIO_NOPULL, 0)); + } else { // PIN_INPUT + pin_function(obj->pin, WIZ_PIN_DATA(WIZ_MODE_INPUT, WIZ_GPIO_NOPULL, 0)); + } +} diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c new file mode 100644 index 0000000000..57a8e004f9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c @@ -0,0 +1,148 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "cmsis.h" +#include "gpio_irq_api.h" +#include "pinmap.h" +#include "mbed_error.h" + +#define EDGE_NONE (0) +#define EDGE_RISE (1) +#define EDGE_FALL (2) +#define EDGE_BOTH (3) + +static gpio_irq_handler irq_handler; + + +typedef struct gpio_channel { + uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts + uint32_t channel_ids; // mbed "gpio_irq_t gpio_irq" field of instance + uint32_t channel_pin; // pin number in port group + gpio_irq_t * obj; +} gpio_channel_t; + +static gpio_channel_t channel; + +#ifdef __cplusplus +extern "C"{ +#endif +void EXTI_Handler() +{ + // To Do + //irq_handler(channel.channel_ids); +} +#ifdef __cplusplus +} +#endif + + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + IRQn_Type irq_n = (IRQn_Type)0; + uint32_t gpio_pin; + + if (pin == NC) return -1; + + uint32_t port_index = WIZ_PORT(pin); + uint32_t pin_index = WIZ_PIN(pin); + + // If port_index is not GPIOC, return -1 + if (port_index != 2 ) { + error("InterruptIn error: pin not supported.\n"); + return -1; + } + + // Select irq number and interrupt routine + if ((pin_index == 0) || (pin_index == 1) || (pin_index == 4) || (pin_index == 6) || (pin_index == 7)) { + irq_n = EXTI_IRQn; + gpio_pin = 1 << pin_index; + } else { + error("InterruptIn error: pin not supported.\n"); + return -1; + } + + // Enable GPIO clock + uint32_t gpio_add = Get_GPIO_BaseAddress(port_index); + + // Configure GPIO + EXTI_InitTypeDef EXTI_InitDef; + EXTI_InitDef.EXTI_Line = gpio_pin; + EXTI_InitDef.EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_Init(gpio_add, &EXTI_InitDef); + + // Enable EXTI interrupt + NVIC_ClearPendingIRQ(irq_n); // Pending bit Clear + NVIC_EnableIRQ(irq_n); + + obj->irq_n = irq_n; +// obj->irq_index = irq_index; + obj->event = EDGE_FALL; + obj->pin = pin; + + channel.channel_pin = pin_index; + channel.pin_mask = gpio_pin; + channel.channel_ids = id; + channel.obj = obj; + + irq_handler = handler; + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + // Disable EXTI line + NVIC_ClearPendingIRQ(obj->irq_n); + EXTI_DeInit(); + pin_function(obj->pin, WIZ_PIN_DATA(WIZ_MODE_INPUT, WIZ_GPIO_NOPULL, 0)); + obj->event = EDGE_NONE; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + uint16_t porarity; + + if (enable) { + if (event == IRQ_RISE) { + porarity = EXTI_Trigger_Rising; + obj->event = EDGE_RISE; + } + if (event == IRQ_FALL) { + porarity = EXTI_Trigger_Falling; + obj->event = EDGE_FALL; + } + + uint32_t port_index = WIZ_PORT(obj->pin); + uint32_t pin_index = WIZ_PIN(obj->pin); + + // Enable GPIO clock + uint32_t gpio_add = Get_GPIO_BaseAddress(port_index); + EXTI_Polarity_Set(port_index,(1<irq_n); +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ + NVIC_DisableIRQ(obj->irq_n); + obj->event = EDGE_NONE; +} diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_object.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_object.h new file mode 100644 index 0000000000..42472bead6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_object.h @@ -0,0 +1,86 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; + uint32_t mask; + uint32_t direction; + __IO uint32_t *reg_data_in; +} gpio_t; + + +extern uint32_t Get_GPIO_BaseAddress(uint32_t port_idx); + + +static inline void gpio_write(gpio_t *obj, int value) { + MBED_ASSERT(obj->pin != (PinName)NC); + + uint32_t port_index = WIZ_PORT(obj->pin); + uint32_t pin_index = WIZ_PIN(obj->pin); + + uint32_t gpio_add = Get_GPIO_BaseAddress(port_index); + GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; + + + if (value) + { + HAL_GPIO_SetBits(gpio,(0x01 << pin_index)); + } + else + { + HAL_GPIO_ResetBits(gpio,(0x01 << pin_index)); + } +} + +static inline int gpio_read(gpio_t *obj) { + int ret; + + MBED_ASSERT(obj->pin != (PinName)NC); + + uint32_t port_index = WIZ_PORT(obj->pin); + + uint32_t gpio_add = Get_GPIO_BaseAddress(port_index); + GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; + + if(obj->direction == PIN_OUTPUT) + { + ret = ( HAL_GPIO_ReadOutputData(gpio) & obj->mask ) ? 1 : 0; + } + else + { + ret = ((*obj->reg_data_in & obj->mask) ? 1 : 0); + } + + return ret; +} + +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/i2c_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/i2c_api.c new file mode 100644 index 0000000000..0e6bb4f04b --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/i2c_api.c @@ -0,0 +1,316 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "mbed_assert.h" +#include "i2c_api.h" + +#if DEVICE_I2C + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" + +/* Timeout values for flags and events waiting loops. These timeouts are + not based on accurate values, they just guarantee that the application will + not remain stuck if the I2C communication is corrupted. */ +#define FLAG_TIMEOUT ((int)0x1000) +#define LONG_TIMEOUT ((int)0xFFFF) + +I2C_TypeDef * I2cHandle; + +int i2c0_inited = 0; +int i2c1_inited = 0; + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + // Determine the I2C to use + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + + obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT(obj->i2c != (I2CName)NC); + + // Enable I2C1 clock and pinout if not done + if ((obj->i2c == I2C_0) && !i2c0_inited) { + i2c0_inited = 1; + // Configure I2C pins + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + pin_mode(sda, OpenDrain); + pin_mode(scl, OpenDrain); + } + + // Enable I2C2 clock and pinout if not done + if ((obj->i2c == I2C_1) && !i2c1_inited) { + i2c1_inited = 1; + // Configure I2C pins + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + pin_mode(sda, OpenDrain); + pin_mode(scl, OpenDrain); + } + + // Reset to clear pending flags if any + i2c_reset(obj); + + // I2C configuration + i2c_frequency(obj, 100000); // 100 kHz per default + obj->is_setAddress = 0; +} + +void i2c_frequency(i2c_t *obj, int hz) +{ + MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); + I2cHandle = (I2C_TypeDef *)(obj->i2c); + + // wait before init + I2C_ConfigStruct conf; + + conf.mode = I2C_Master; + conf.master.timeout = LONG_TIMEOUT; + + // Common settings: I2C clock = 48 MHz, Analog filter = ON, Digital filter coefficient = 0 + switch (hz) { + case 100000: + conf.master.prescale = 0x61; // Standard mode with Rise Time = 400ns and Fall Time = 100ns + break; + case 400000: + break; + case 1000000: + break; + default: + break; + } + + // I2C configuration + I2C_Init(I2cHandle, conf); +} + +inline int i2c_start(i2c_t *obj) +{ + obj->is_setAddress = 0; + + return 0; +} + +inline int i2c_stop(i2c_t *obj) +{ + I2cHandle = (I2C_TypeDef *)(obj->i2c); + + // Generate the STOP condition + I2C_Stop(I2cHandle); + I2C_Reset(I2cHandle); + obj->is_setAddress = 0; + + return 0; +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + I2cHandle = (I2C_TypeDef *)(obj->i2c); + int count; + int value; + + if(!obj->is_setAddress) + { + if( I2C_Start(I2cHandle, address, I2C_READ_SA7) == ERROR ) + { + return -1; + } + obj->is_setAddress = 1; + obj->ADDRESS = address; + } + else + { + I2C_Restart_Structure(I2cHandle, address, I2C_READ_SA7); + obj->ADDRESS = address; + } + + // Read all bytes + for (count = 0; count < (length-1); count++) { + if( (value = i2c_byte_read(obj, 0)) == -1) return value; + data[count] = (char)value; + } + + if(stop){ + if( (value = i2c_byte_read(obj, 1)) == -1) return value; + data[count] = (char)value; + } + else{ + if( (value = i2c_byte_read(obj, 0)) == -1) return value; + data[count] = (char)value; + } + + return count; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + I2cHandle = (I2C_TypeDef *)(obj->i2c); + int count; + + if(!obj->is_setAddress) + { + if( I2C_Start(I2cHandle, address, I2C_WRITE_SA7) == ERROR ) + { + return -1; + } + obj->is_setAddress = 1; + obj->ADDRESS = address; + } + else + { + I2C_Restart_Structure(I2cHandle, address, I2C_WRITE_SA7); + obj->ADDRESS = address; + } + + for (count = 0; count < length; count++) { + i2c_byte_write(obj, data[count]); + } + + // If not repeated start, send stop + if (stop) { + i2c_stop(obj); + } + + return count; +} + +int i2c_byte_read(i2c_t *obj, int last) +{ + I2cHandle = (I2C_TypeDef *)(obj->i2c); + + return I2C_ReceiveData(I2cHandle, last); +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + I2cHandle = (I2C_TypeDef *)(obj->i2c); + return I2C_SendDataAck(I2cHandle,(uint8_t)data); +} + +void i2c_reset(i2c_t *obj) +{ + I2cHandle = (I2C_TypeDef *)(obj->i2c); + + I2C_Reset(I2cHandle); +} + +//#if DEVICE_I2CSLAVE +// +//void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +//{ +// I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); +// uint16_t tmpreg = 0; +// +// // disable +// i2c->OAR1 &= (uint32_t)(~I2C_OAR1_OA1EN); +// // Get the old register value +// tmpreg = i2c->OAR1; +// // Reset address bits +// tmpreg &= 0xFC00; +// // Set new address +// tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits +// // Store the new register value +// i2c->OAR1 = tmpreg; +// // enable +// i2c->OAR1 |= I2C_OAR1_OA1EN; +//} +// +//void i2c_slave_mode(i2c_t *obj, int enable_slave) +//{ +// I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); +// uint16_t tmpreg; +// +// // Get the old register value +// tmpreg = i2c->OAR1; +// +// // Enable / disable slave +// if (enable_slave == 1) { +// tmpreg |= I2C_OAR1_OA1EN; +// } else { +// tmpreg &= (uint32_t)(~I2C_OAR1_OA1EN); +// } +// +// // Set new mode +// i2c->OAR1 = tmpreg; +//} +// +//// See I2CSlave.h +//#define NoData 0 // the slave has not been addressed +//#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) +//#define WriteGeneral 2 // the master is writing to all slave +//#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) +// +//int i2c_slave_receive(i2c_t *obj) +//{ +// I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); +// int retValue = NoData; +// +// if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) { +// if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) { +// if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_DIR) == 1) +// retValue = ReadAddressed; +// else +// retValue = WriteAddressed; +// +// __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR); +// } +// } +// +// return (retValue); +//} +// +//int i2c_slave_read(i2c_t *obj, char *data, int length) +//{ +// char size = 0; +// +// while (size < length) data[size++] = (char)i2c_byte_read(obj, 0); +// +// return size; +//} +// +//int i2c_slave_write(i2c_t *obj, const char *data, int length) +//{ +// char size = 0; +// I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); +// +// do { +// i2c_byte_write(obj, data[size]); +// size++; +// } while (size < length); +// +// return size; +//} +// +// +//#endif // DEVICE_I2CSLAVE + +#endif // DEVICE_I2C diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/mbed_overrides.c new file mode 100644 index 0000000000..3e7b4fb61a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/mbed_overrides.c @@ -0,0 +1,24 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "cmsis.h" + +// This function is called after RAM initialization and before main. +void mbed_sdk_init() +{ + // Update the SystemCoreClock variable. + SystemInit(); +} diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pinmap.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pinmap.c new file mode 100644 index 0000000000..dd37dec726 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pinmap.c @@ -0,0 +1,139 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pinmap.h" +#include "PortNames.h" + + +// GPIO mode look-up table +// It have to same with PinMode index in "PinNames.h" +static const uint32_t gpio_pupd[4] = { + GPIO_NO_PUPD, // PullNone + GPIO_PuPd_DOWN, // PullDown + GPIO_PuPd_UP, // PullUp + GPIO_OD // OpenDrain +}; + +uint32_t Get_GPIO_BaseAddress(uint32_t port_idx) +{ + uint32_t gpio_add = 0; + switch(port_idx) { + case PortA: + gpio_add = GPIOA_BASE; + break; + case PortB: + gpio_add = GPIOB_BASE; + break; + case PortC: + gpio_add = GPIOC_BASE; + break; + case PortD: + gpio_add = GPIOD_BASE; + break; + default: + error("Pinmap error: wrong port number."); + break; + } + return gpio_add; +} + + +/** + * Configure pin (input, output, alternate function or analog) + output speed + AF + */ + +void pin_function(PinName pin, int data) { + MBED_ASSERT(pin != (PinName)NC); + // Get the pin informations + uint32_t mode = WIZ_PIN_MODE(data); + uint32_t pupd = WIZ_PIN_PUPD(data); + uint32_t afnum; + + if( mode == WIZ_MODE_AF ) + afnum = WIZ_PIN_AFNUM(data); + else + afnum = WIZ_AFNUM(pin); + + uint32_t port_index = WIZ_PORT(pin); + uint32_t pin_index = WIZ_PIN(pin); + + + uint32_t gpio_add = Get_GPIO_BaseAddress(port_index); + GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; + + // Configure Alternate Function + // Warning: Must be done before the GPIO is initialized + switch (afnum) { + case 0: + HAL_PAD_AFConfig(port_index,(uint32_t)(1 << pin_index),Px_AFSR_AF0); + break; + case 1: + HAL_PAD_AFConfig(port_index,(uint32_t)(1 << pin_index),Px_AFSR_AF1); + break; + case 2: + HAL_PAD_AFConfig(port_index,(uint32_t)(1 << pin_index),Px_AFSR_AF2); + break; + case 3: + HAL_PAD_AFConfig(port_index,(uint32_t)(1 << pin_index),Px_AFSR_AF3); + break; + default: + break; + } + + if(mode == WIZ_MODE_AF) + return; + + // Configure GPIO + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = (uint32_t)(1 << pin_index); + GPIO_InitStructure.GPIO_Mode = mode; + GPIO_InitStructure.GPIO_Pad = gpio_pupd[pupd]; + HAL_GPIO_Init(gpio, &GPIO_InitStructure); +} + +/** + * Configure pin pull-up/pull-down + */ +void pin_mode(PinName pin, PinMode pupd) +{ + MBED_ASSERT(pin != (PinName)NC); + + P_Port_Def *px_pcr; + + uint32_t port_index = WIZ_PORT(pin); + + switch(port_index) { + case PortA: + px_pcr = PA_PCR; + break; + case PortB: + px_pcr = PB_PCR; + break; + case PortC: + px_pcr = PC_PCR; + break; + case PortD: + px_pcr = (P_Port_Def*)PD_PCR; + break; + default: + error("Pinmap error: wrong port number."); + return; + } + + px_pcr->Port[port_index] &= ~(Px_PCR_PUPD_DOWN|Px_PCR_PUPD_UP|Px_PCR_DS_HIGH| \ + Px_PCR_OD | Px_PCR_IE | Px_PCR_CS_SUMMIT); + px_pcr->Port[port_index] |= gpio_pupd[pupd]; +} diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/port_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/port_api.c new file mode 100644 index 0000000000..3680a48b2d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/port_api.c @@ -0,0 +1,96 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" +#include "pinmap.h" +#include "gpio_api.h" +#include "mbed_error.h" + +#if DEVICE_PORTIN || DEVICE_PORTOUT + +extern uint32_t Get_GPIO_BaseAddress(uint32_t port_idx); + +//port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...) +PinName port_pin(PortName port, int pin_n) +{ + int af_num = 0; + + if( (port == 2) && ((pin_n == 0) || (pin_n == 1) || (pin_n == 4) || (pin_n == 8) || (pin_n == 9)) ) + { + af_num = 1; + } + + + return (PinName)(pin_n + (port << 4) + (af_num << 8)); +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ + uint32_t port_index = (uint32_t)port; + + // Enable GPIO clock + uint32_t gpio_add = Get_GPIO_BaseAddress(port_index); + GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; + + // Fill PORT object structure for future use + obj->port = port; + obj->mask = mask; + obj->direction = dir; + obj->reg_in = &gpio->DATA; + obj->reg_out = &gpio->DATAOUT; + + port_dir(obj, dir); +} + +void port_dir(port_t *obj, PinDirection dir) +{ + uint32_t i; + obj->direction = dir; + for (i = 0; i < 16; i++) { // Process all pins + if (obj->mask & (1 << i)) { // If the pin is used + if (dir == PIN_OUTPUT) { + pin_function(port_pin(obj->port, i), WIZ_PIN_DATA(WIZ_MODE_OUTPUT, WIZ_GPIO_NOPULL, 0)); + } else { // PIN_INPUT + pin_function(port_pin(obj->port, i), WIZ_PIN_DATA(WIZ_MODE_INPUT, WIZ_GPIO_NOPULL, 0)); + } + } + } +} + +void port_mode(port_t *obj, PinMode mode) +{ + uint32_t i; + for (i = 0; i < 16; i++) { // Process all pins + if (obj->mask & (1 << i)) { // If the pin is used + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_write(port_t *obj, int value) +{ + *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); +} + +int port_read(port_t *obj) +{ + if (obj->direction == PIN_OUTPUT) { + return (*obj->reg_out & obj->mask); + } else { // PIN_INPUT + return (*obj->reg_in & obj->mask); + } +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c new file mode 100644 index 0000000000..110b46a20e --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c @@ -0,0 +1,280 @@ +#include "mbed_assert.h" +#include "serial_api.h" + +#if DEVICE_SERIAL + +#include "cmsis.h" +#include "pinmap.h" +#include +#include "PeripheralPins.h" + +#define UART_NUM (2) + +static uint32_t serial_irq_ids[UART_NUM] = {0, 0}; + + +static uart_irq_handler irq_handler; +static UART_TypeDef *UART; + + +UART_InitTypeDef UART_InitStructure; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +static void init_uart(serial_t *obj) +{ + UART = (UART_TypeDef *)(obj->uart); + UART_InitStructure.UART_BaudRate = obj->baudrate; + UART_InitStructure.UART_WordLength = obj->databits; + UART_InitStructure.UART_StopBits = obj->stopbits; + UART_InitStructure.UART_Parity = obj->parity; + UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; + + + if (obj->pin_rx == NC) { + UART_InitStructure.UART_Mode = UART_Mode_Tx; + } else if (obj->pin_tx == NC) { + UART_InitStructure.UART_Mode = UART_Mode_Rx; + } else { + UART_InitStructure.UART_Mode = (UART_Mode_Rx | UART_Mode_Tx); + } + + UART_Init(UART,&UART_InitStructure); +} + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + // Determine the UART to use (UART_1, UART_2, ...) + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + + // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object + obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + + MBED_ASSERT(obj->uart != (UARTName)NC); + + // Enable USART clock + if (obj->uart == UART_0) { + obj->index = 0; + } + + if (obj->uart == UART_1) { + obj->index = 1; + } + + // Configure the UART pins + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + if (tx != NC) { + pin_mode(tx, PullUp); + } + if (rx != NC) { + pin_mode(rx, PullUp); + } + + // Configure UART + obj->baudrate = 9600; + obj->databits = UART_WordLength_8b; + obj->stopbits = UART_StopBits_1; + obj->parity = UART_Parity_No; + + obj->pin_tx = tx; + obj->pin_rx = rx; + + + init_uart(obj); + + // For stdio management + if (obj->uart == STDIO_UART) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) +{ + // Reset UART and disable clock + if (obj->uart == UART_0) { + } + + if (obj->uart == UART_1) { + } + + + // Configure GPIOs +// pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); +// pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + + serial_irq_ids[obj->index] = 0; +} + +void serial_baud(serial_t *obj, int baudrate) +{ + obj->baudrate = baudrate; + init_uart(obj); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + if (data_bits == 7) { + obj->databits = UART_WordLength_7b; + } else { + obj->databits = UART_WordLength_8b; + } + + switch (parity) { + case ParityOdd: + case ParityForced0: + obj->parity = UART_Parity_Odd; + break; + case ParityEven: + case ParityForced1: + obj->parity = UART_Parity_Even; + break; + default: // ParityNone + obj->parity = UART_Parity_No; + break; + } + + if (stop_bits == 2) { + obj->stopbits = UART_StopBits_2; + } else { + obj->stopbits = UART_StopBits_1; + } + + init_uart(obj); +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ + +static void uart_irq(UARTName name, int id) +{ + UART = (UART_TypeDef *)name; + if (serial_irq_ids[id] != 0) { + if( UART_GetITStatus(UART,UART_IT_FLAG_TXI) != RESET ){ + irq_handler(serial_irq_ids[id], TxIrq); + UART_ClearITPendingBit(UART,UART_IT_FLAG_TXI); + } + if( UART_GetITStatus(UART,UART_IT_FLAG_RXI) != RESET ){ + irq_handler(serial_irq_ids[id], RxIrq); + } + } +} + +#ifdef __cplusplus +extern "C"{ +#endif +void UART0_Handler() +{ + uart_irq(UART_0, 0); +} + +void UART1_Handler() +{ + uart_irq(UART_1, 1); +} +#ifdef __cplusplus +} +#endif + + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + IRQn_Type irq_n = (IRQn_Type)0; + + UART = (UART_TypeDef *)(obj->uart); + + if (obj->uart == UART_0) { + irq_n = UART0_IRQn; + } + + if (obj->uart == UART_1) { + irq_n = UART1_IRQn; + } + + if (enable) { + if (irq == RxIrq) { + UART_ITConfig(UART,UART_IT_FLAG_RXI,ENABLE); + } else { // TxIrq + UART_ITConfig(UART,UART_IT_FLAG_TXI,ENABLE); + } + + NVIC_ClearPendingIRQ(irq_n); + NVIC_EnableIRQ(irq_n); + } else { // disable + UART_ITConfig(UART,(UART_IT_FLAG_RXI|UART_IT_FLAG_TXI),DISABLE); + NVIC_DisableIRQ(irq_n); + } +} + +/****************************************************************************** + * READ/WRITE + ******************************************************************************/ + +int serial_getc(serial_t *obj) +{ + UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); +// while(!serial_readable(obj)); + while(uart->FR & UART_FR_RXFE); + + return (uart->DR & 0xFF); +} + +void serial_putc(serial_t *obj, int c) +{ + UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); + + uart->DR = (uint32_t)(c & (uint16_t)0xFF); + while(uart->FR & UART_FR_BUSY); +} + +int serial_readable(serial_t *obj) +{ + int status; + UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); + // Check if data is received + status = ((uart->FR & UART_FR_RXFE) ? 0: 1); + return status; +} + +int serial_writable(serial_t *obj) +{ + int status; + UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); + // Check if data is transmitted + status = ((uart->FR & UART_FR_BUSY) ? 0: 1); + return status; +} + +void serial_clear(serial_t *obj) +{ +// UartHandle.Instance = (USART_TypeDef *)(obj->uart); +// __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); +// __HAL_UART_SEND_REQ(&UartHandle, UART_RXDATA_FLUSH_REQUEST); +} + +void serial_pinout_tx(PinName tx) +{ + //pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) +{ + // [TODO] +} + +void serial_break_clear(serial_t *obj) +{ + // [TODO] +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/sleep.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/sleep.c new file mode 100644 index 0000000000..81ed6b36d6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/sleep.c @@ -0,0 +1,43 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "sleep_api.h" +#include "cmsis.h" +#include "mbed_interface.h" + +void sleep(void) +{ + // To Do +} + +void deepsleep(void) +{ + // To Do +} diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/spi_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/spi_api.c new file mode 100644 index 0000000000..c37942b73e --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/spi_api.c @@ -0,0 +1,187 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include + +#include "spi_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "PeripheralPins.h" + +static inline int ssp_disable(spi_t *obj); +static inline int ssp_enable(spi_t *obj); + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { + // determine the SPI to use + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + obj->spi = (SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj->spi != NC); + + // enable power and clocking + switch ((int)obj->spi) { + case SPI_0: CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK; break; //PLL output clock + case SPI_1: CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK; break; + } + + // set default format and frequency + if (ssel == NC) { + spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master + } else { + spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave + } + spi_frequency(obj, 1000000); + + // enable the ssp channel + ssp_enable(obj); + + // pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } +} + +void spi_free(spi_t *obj) {} + +void spi_format(spi_t *obj, int bits, int mode, int slave) { + ssp_disable(obj); + MBED_ASSERT(((bits >= 4) && (bits <= 16)) && (mode >= 0 && mode <= 3)); + + int polarity = (mode & 0x2) ? 1 : 0; + int phase = (mode & 0x1) ? 1 : 0; + + // set it up + int DSS = bits - 1; // DSS (data select size) + int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity + int SPH = (phase) ? 1 : 0; // SPH - clock out phase + + int FRF = 0; // FRF (frame format) = SPI + uint32_t tmp = obj->spi->CR0; + tmp &= ~(0xFFFF); + tmp |= DSS << 0 + | FRF << 4 + | SPO << 6 + | SPH << 7; + obj->spi->CR0 = tmp; + + tmp = obj->spi->CR1; + tmp &= ~(0xD); + tmp |= 0 << 0 // LBM - loop back mode - off + | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave + | 0 << 3; // SOD - slave output disable - na + obj->spi->CR1 = tmp; + + ssp_enable(obj); +} + +void spi_frequency(spi_t *obj, int hz) { + ssp_disable(obj); + + // setup the spi clock diveder to /1 + switch ((int)obj->spi) { + case SPI_0: + CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1; //1/1 (bypass) + break; + case SPI_1: + CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1; //1/1 (bypass) + break; + } + + uint32_t HCLK = SystemCoreClock; + + int prescaler; + + for (prescaler = 2; prescaler <= 254; prescaler += 2) { + int prescale_hz = HCLK / prescaler; + + // calculate the divider + int divider = floor(((float)prescale_hz / (float)hz) + 0.5f); + + // check we can support the divider + if (divider < 256) { + // prescaler + obj->spi->CPSR = prescaler; + + // divider + obj->spi->CR0 &= ~(0xFFFF << 8); + obj->spi->CR0 |= (divider - 1) << 8; + ssp_enable(obj); + return; + } + } + error("Couldn't setup requested SPI frequency"); +} + +static inline int ssp_disable(spi_t *obj) { + return obj->spi->CR1 &= ~(1 << 1); +} + +static inline int ssp_enable(spi_t *obj) { + return obj->spi->CR1 |= (1 << 1); +} + +static inline int ssp_readable(spi_t *obj) { + return obj->spi->SR & (1 << 2); +} + +static inline int ssp_writeable(spi_t *obj) { + return obj->spi->SR & (1 << 1); +} + +static inline void ssp_write(spi_t *obj, int value) { + while (!ssp_writeable(obj)); + obj->spi->DR = value; +} + +static inline int ssp_read(spi_t *obj) { + while (!ssp_readable(obj)); + return obj->spi->DR; +} + +static inline int ssp_busy(spi_t *obj) { + return (obj->spi->SR & (1 << 4)) ? (1) : (0); +} + +int spi_master_write(spi_t *obj, int value) { + ssp_write(obj, value); + return ssp_read(obj); +} + +int spi_slave_receive(spi_t *obj) { + return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); +} + +int spi_slave_read(spi_t *obj) { + return obj->spi->DR; +} + +void spi_slave_write(spi_t *obj, int value) { + while (ssp_writeable(obj) == 0) ; + obj->spi->DR = value; +} + +int spi_busy(spi_t *obj) { + return ssp_busy(obj); +} + diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c new file mode 100644 index 0000000000..5320ed3da9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c @@ -0,0 +1,121 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "us_ticker_api.h" +#include "PeripheralNames.h" +#include "system_W7500x.h" + +// 32-bit timer selection +#define TIM_MST7 PWM_CH7 +#define TIM_MST6 PWM_CH6 +#define IRQn_PWM6 PWM6_IRQn + +static PWM_TimerModeInitTypeDef TimMasterHandle_CH7; +static PWM_TimerModeInitTypeDef TimMasterHandle_CH6; + +static int us_ticker_inited = 0; + + +#ifdef __cplusplus +extern "C"{ +#endif +void PWM6_Handler(void) +{ + uint32_t IntFlag = 0; + + IntFlag = PWM_CHn_GetIntFlagStatus(TIM_MST6); + + /* If overflow interrupt is occurred */ + if( (IntFlag & PWM_CHn_IER_OI_Msk) != 0 ) + { + /* Clear overflow interrupt */ + PWM_CH6_ClearOverflowInt(); + us_ticker_irq_handler(); + } +} + +#ifdef __cplusplus +} +#endif + +void us_ticker_init(void) +{ + if (us_ticker_inited) return; + us_ticker_inited = 1; + + SystemCoreClockUpdate(); + TimMasterHandle_CH7.PWM_CHn_PR = (GetSystemClock() / 1000000) -1; + TimMasterHandle_CH7.PWM_CHn_LR = 0xFFFFFFFF; + TimMasterHandle_CH7.PWM_CHn_PDMR = 1; + + PWM_TimerModeInit(TIM_MST7, &TimMasterHandle_CH7); + PWM_CHn_Start(TIM_MST7); +} + + +uint32_t us_ticker_read() +{ + if (!us_ticker_inited) us_ticker_init(); + + return (TIM_MST7->TCR); +} + + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + int32_t dev = 0; + if (!us_ticker_inited) + { + us_ticker_init(); + } + + dev = (timestamp - us_ticker_read() + 0x5153); + if(dev <= 0) + { + us_ticker_irq_handler(); + return; + } + + PWM_CHn_Stop(TIM_MST6); + + TimMasterHandle_CH6.PWM_CHn_PR = (GetSystemClock() / 1000000) -1; + TimMasterHandle_CH6.PWM_CHn_LR = dev; + + TimMasterHandle_CH6.PWM_CHn_UDMR = 0; + TimMasterHandle_CH6.PWM_CHn_PDMR = 0; + + NVIC_EnableIRQ(IRQn_PWM6); + + PWM_CHn_IntConfig(TIM_MST6, PWM_CHn_IER_OIE, ENABLE); + PWM_IntConfig(TIM_MST6, ENABLE); + PWM_TimerModeInit(TIM_MST6, &TimMasterHandle_CH6); + + PWM_CHn_Start(TIM_MST6); +} + +void us_ticker_disable_interrupt(void) +{ + NVIC_DisableIRQ(IRQn_PWM6); + + PWM_CHn_IntConfig(TIM_MST6, PWM_CHn_IER_OIE, DISABLE); + PWM_IntConfig(TIM_MST6, DISABLE); +} + +void us_ticker_clear_interrupt(void) +{ + PWM_CHn_ClearInt(TIM_MST6, PWM_CHn_IER_OIE); +} From 2f751039fc06f77134b4ad38763468a25c498a4a Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Fri, 15 May 2015 11:28:46 +0900 Subject: [PATCH 020/139] add some files --- workspace_tools/muts_all.json | 7 +++++++ workspace_tools/targets.py | 16 +++++++++++++++- workspace_tools/test_spec.json | 5 +++++ 3 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 workspace_tools/muts_all.json create mode 100644 workspace_tools/test_spec.json diff --git a/workspace_tools/muts_all.json b/workspace_tools/muts_all.json new file mode 100644 index 0000000000..ea7cb6e0e0 --- /dev/null +++ b/workspace_tools/muts_all.json @@ -0,0 +1,7 @@ +{ + "1" : {"mcu": "WIZwiki_W7500", + "port":"COM29", + "disk":"E:\\", + "peripherals": [] + } +} diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 4de30c80a9..93c8b630ec 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -69,8 +69,19 @@ class Target: def init_hooks(self, hook, toolchain_name): pass +##WIZnet - +class WIZwiki_W7500(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['WIZNET', 'W7500x', 'WIZwiki_W7500'] + self.supported_toolchains = ["ARM", "uARM",] + self.default_toolchain = "ARM" + self.supported_form_factors = ["ARDUINO"] + + + ### NXP ### # This class implements the post-link patching step needed by LPC targets @@ -1201,6 +1212,9 @@ class EFM32HG_STK3400(Target): # Get a single instance for each target TARGETS = [ + ### WIZnet ### + WIZwiki_W7500(), + ### NXP ### LPC11C24(), LPC11U24(), diff --git a/workspace_tools/test_spec.json b/workspace_tools/test_spec.json new file mode 100644 index 0000000000..a4818818ae --- /dev/null +++ b/workspace_tools/test_spec.json @@ -0,0 +1,5 @@ +{ + "targets": { + "WIZwiki_W7500" : ["ARM", "uARM"] + } +} From c452befc0aded41bcbad41c4297f276e1c752ae7 Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Mon, 18 May 2015 09:32:49 +0900 Subject: [PATCH 021/139] Delete json files --- workspace_tools/muts_all.json | 7 ------- workspace_tools/test_spec.json | 5 ----- 2 files changed, 12 deletions(-) delete mode 100644 workspace_tools/muts_all.json delete mode 100644 workspace_tools/test_spec.json diff --git a/workspace_tools/muts_all.json b/workspace_tools/muts_all.json deleted file mode 100644 index ea7cb6e0e0..0000000000 --- a/workspace_tools/muts_all.json +++ /dev/null @@ -1,7 +0,0 @@ -{ - "1" : {"mcu": "WIZwiki_W7500", - "port":"COM29", - "disk":"E:\\", - "peripherals": [] - } -} diff --git a/workspace_tools/test_spec.json b/workspace_tools/test_spec.json deleted file mode 100644 index a4818818ae..0000000000 --- a/workspace_tools/test_spec.json +++ /dev/null @@ -1,5 +0,0 @@ -{ - "targets": { - "WIZwiki_W7500" : ["ARM", "uARM"] - } -} From 7d82bcacaa3e2480f6a728f147a57cc19a8eb0ff Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Mon, 18 May 2015 14:31:19 +0900 Subject: [PATCH 022/139] Remove rtc_api.c and pwmout_api.c And change define in device.h about RTC and pwmout. --- .../TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h | 4 ++-- .../mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c | 0 .../mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c | 0 3 files changed, 2 insertions(+), 2 deletions(-) delete mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h index 9973c40578..f94476da70 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h @@ -48,9 +48,9 @@ #define DEVICE_SPI 1 #define DEVICE_SPISLAVE 1 -#define DEVICE_RTC 1 +#define DEVICE_RTC 0 -#define DEVICE_PWMOUT 1 +#define DEVICE_PWMOUT 0 #define DEVICE_SLEEP 1 diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c deleted file mode 100644 index e69de29bb2..0000000000 From 8ab2a956185b8c6dccd14ec776e7f86464412773 Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Mon, 18 May 2015 13:31:10 +0400 Subject: [PATCH 023/139] make some tests compilable --- .../tests/mbed/interrupt_chaining/main.cpp | 4 ++-- libraries/tests/mbed/portout/main.cpp | 2 +- libraries/tests/mbed/pwm/main.cpp | 2 +- workspace_tools/tests.py | 18 +++++++++--------- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/libraries/tests/mbed/interrupt_chaining/main.cpp b/libraries/tests/mbed/interrupt_chaining/main.cpp index 65bc3ef699..f2afb920a1 100644 --- a/libraries/tests/mbed/interrupt_chaining/main.cpp +++ b/libraries/tests/mbed/interrupt_chaining/main.cpp @@ -9,7 +9,7 @@ #define TIMER_IRQ TIMER_32_1_IRQn #elif defined(TARGET_KL25Z) #define TIMER_IRQ LPTimer_IRQn -#elif defined(TARGET_LPC2368) +#elif defined(TARGET_LPC2368) || defined(TARGET_LPC2460) #define TIMER_IRQ TIMER3_IRQn #else #error This test can't run on this target. @@ -40,7 +40,7 @@ Ticker flipper_2; Sender s1(pc, '1'); Sender s2(pc, '2'); -#if defined(TARGET_LPC1768) || defined(TARGET_LPC11U24) || defined(TARGET_LPC4088) || defined(TARGET_LPC2368) || defined(TARGET_LPC1114) +#if defined(TARGET_LPC1768) || defined(TARGET_LPC11U24) || defined(TARGET_LPC4088) || defined(TARGET_LPC2368) || defined(TARGET_LPC1114) || defined(TARGET_LPC2460) # define LED_NAME LED2 #elif defined(TARGET_KL05Z) # define LED_NAME LED2 diff --git a/libraries/tests/mbed/portout/main.cpp b/libraries/tests/mbed/portout/main.cpp index cf8f4d2ba6..c875dd0bbb 100644 --- a/libraries/tests/mbed/portout/main.cpp +++ b/libraries/tests/mbed/portout/main.cpp @@ -1,6 +1,6 @@ #include "mbed.h" -# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) +# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC2460) # define LED_PORT Port1 # define LED1 (1 << 18) // P1.18 # define LED2 (1 << 20) // P1.20 diff --git a/libraries/tests/mbed/pwm/main.cpp b/libraries/tests/mbed/pwm/main.cpp index b7b3550098..fc4edc61b4 100644 --- a/libraries/tests/mbed/pwm/main.cpp +++ b/libraries/tests/mbed/pwm/main.cpp @@ -28,7 +28,7 @@ int main() { notify_completion(result == value ? true : false); -#elif defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC11U24) || defined(TARGET_LPC4088) +#elif defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC11U24) || defined(TARGET_LPC4088) || defined(TARGET_LPC2460) PwmOut pwm_p25(p25); PwmOut pwm_p26(p26); diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py index e860c65d1a..e4e86b26d5 100644 --- a/workspace_tools/tests.py +++ b/workspace_tools/tests.py @@ -143,7 +143,7 @@ TESTS = [ "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB], "automated": True, "peripherals": ["analog_loop"], - "mcu": ["LPC1768", "LPC2368", "KL25Z", "K64F", "K22F", "LPC4088", "LPC1549", + "mcu": ["LPC1768", "LPC2368", "LPC2460", "KL25Z", "K64F", "K22F", "LPC4088", "LPC1549", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_F302R8", "NUCLEO_F303RE", "NUCLEO_F334R8", "NUCLEO_L053R8", "NUCLEO_L073RZ", "NUCLEO_L152RE", "NUCLEO_F411RE", "DISCO_F407VG", "ARCH_MAX", "MAX32600MBED"] @@ -635,7 +635,7 @@ TESTS = [ "duration": 15, "automated": True, #"host_test": "wait_us_auto", - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", @@ -648,7 +648,7 @@ TESTS = [ "dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB], "duration": 20, "automated": True, - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", @@ -661,7 +661,7 @@ TESTS = [ "dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB], "duration": 20, "automated": True, - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", @@ -673,7 +673,7 @@ TESTS = [ "source_dir": join(TEST_DIR, "rtos", "mbed", "signals"), "dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB], "automated": True, - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", @@ -685,7 +685,7 @@ TESTS = [ "source_dir": join(TEST_DIR, "rtos", "mbed", "queue"), "dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB], "automated": True, - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", @@ -697,7 +697,7 @@ TESTS = [ "source_dir": join(TEST_DIR, "rtos", "mbed", "mail"), "dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB], "automated": True, - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", @@ -711,7 +711,7 @@ TESTS = [ "duration": 15, "automated": True, #"host_test": "wait_us_auto", - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", @@ -723,7 +723,7 @@ TESTS = [ "source_dir": join(TEST_DIR, "rtos", "mbed", "isr"), "dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB], "automated": True, - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", From 035a3b8f561258cad03f69b46fde039614416b5d Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Mon, 18 May 2015 13:37:41 +0400 Subject: [PATCH 024/139] fix typo --- libraries/USBDevice/USBDevice/USBHAL_LPC17.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/USBDevice/USBDevice/USBHAL_LPC17.cpp b/libraries/USBDevice/USBDevice/USBHAL_LPC17.cpp index 9734b1f356..61dc87e0aa 100644 --- a/libraries/USBDevice/USBDevice/USBHAL_LPC17.cpp +++ b/libraries/USBDevice/USBDevice/USBHAL_LPC17.cpp @@ -16,7 +16,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC2560) +#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC2460) #include "USBHAL.h" From 8ca60d1d2dfd9d4dffd6925ef11874a51138433a Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Mon, 18 May 2015 14:19:37 +0400 Subject: [PATCH 025/139] Assign PinNames to peripherals --- .../TARGET_LPC2460/PeripheralNames.h | 44 ++++++++++++------- .../hal/TARGET_NXP/TARGET_LPC2460/PinNames.h | 37 +++++++++------- 2 files changed, 48 insertions(+), 33 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PeripheralNames.h index 492c225759..653aa9ea7c 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PeripheralNames.h @@ -75,33 +75,43 @@ typedef enum { // Default peripherals #define MBED_SPI0 p5, p6, p7, p8 -#define MBED_SPI1 p11, p12, p13, p14 +//#define MBED_SPI1 p11, p12, p13, p14 #define MBED_UART0 p9, p10 #define MBED_UART1 p13, p14 -#define MBED_UART2 p27, p28 +#define MBED_UART2 p15, p16 #define MBED_UARTUSB USBTX, USBRX -#define MBED_I2C0 p28, p27 -#define MBED_I2C1 p9, p10 +#define MBED_I2C0 p17, p18 +//#define MBED_I2C1 p9, p10 -#define MBED_CAN0 p30, p29 +#define MBED_CAN0 p19, p20 -#define MBED_ANALOGOUT0 p18 +#define MBED_ANALOGOUT0 p21 -#define MBED_ANALOGIN0 p15 -#define MBED_ANALOGIN1 p16 -#define MBED_ANALOGIN2 p17 -#define MBED_ANALOGIN3 p18 -#define MBED_ANALOGIN4 p19 -#define MBED_ANALOGIN5 p20 +#define MBED_ANALOGIN0 p22 +#define MBED_ANALOGIN1 p23 +//#define MBED_ANALOGIN2 p17 +//#define MBED_ANALOGIN3 p18 +//#define MBED_ANALOGIN4 p19 +//#define MBED_ANALOGIN5 p20 -#define MBED_PWMOUT0 p26 +#define MBED_PWMOUT0 p24 #define MBED_PWMOUT1 p25 -#define MBED_PWMOUT2 p24 -#define MBED_PWMOUT3 p23 -#define MBED_PWMOUT4 p22 -#define MBED_PWMOUT5 p21 +#define MBED_PWMOUT2 p26 +#define MBED_PWMOUT3 p27 +//#define MBED_PWMOUT4 p22 +//#define MBED_PWMOUT5 p21 + +#define MBED_USB_D_PLUS p28 +#define MBED_USB_D_MINUS p29 + +#define MBED_MCICLK p30 +#define MBED_MCICMD p31 +#define MBED_MCIDAT0 p32 +#define MBED_MCIDAT1 p33 +#define MBED_MCIDAT2 p34 +#define MBED_MCIDAT3 p35 #ifdef __cplusplus } diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PinNames.h index 727c6089e9..27194e0918 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/PinNames.h @@ -51,22 +51,27 @@ typedef enum { p12 = P0_17, p13 = P2_0, p14 = P2_1, - p15 = P0_23, - p16 = P0_24, - p17 = P0_25, - p18 = P0_26, - p19 = P1_30, - p20 = P1_31, - p21 = P2_5, - p22 = P2_4, - p23 = P2_3, - p24 = P2_2, - p25 = P2_1, - p26 = P2_0, - p27 = P2_8, - p28 = P2_9, - p29 = P0_5, - p30 = P0_4, + p15 = P4_28, + p16 = P4_29, + p17 = P2_30, + p18 = P2_31, + p19 = P0_0, + p20 = P0_1, + p21 = P0_26, + p22 = P0_12, + p23 = P0_13, + p24 = P1_20, + p25 = P1_21, + p26 = P1_23, + p27 = P1_24, + p28 = P0_29, + p29 = P0_30, + p30 = P1_2, + p31 = P1_3, + p32 = P1_6, + p33 = P1_7, + p34 = P1_11, + p35 = P1_12, // Other mbed Pin Names LED1 = P1_19, From 63bd6bf17b50425c99c1a445fa13abd2f7881a9b Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Mon, 18 May 2015 16:48:58 +0400 Subject: [PATCH 026/139] remove local file system and semihost from the LPC2460 device capabilities --- libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/device.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/device.h index 9a20ae4a36..1f0f00f8ee 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/device.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC2460/device.h @@ -41,8 +41,8 @@ #define DEVICE_PWMOUT 1 -#define DEVICE_SEMIHOST 1 -#define DEVICE_LOCALFILESYSTEM 1 +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 #define DEVICE_ID_LENGTH 32 #define DEVICE_MAC_OFFSET 20 From 7c671670a93356889ccc84c2f0a890fe909ae52f Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Mon, 18 May 2015 17:01:59 +0400 Subject: [PATCH 027/139] add LPC2460 to README file --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index d8afa8c8e6..c42f681137 100644 --- a/README.md +++ b/README.md @@ -30,6 +30,7 @@ NXP: * [mbed LPC11U24](http://developer.mbed.org/platforms/mbed-LPC11U24/) (Cortex-M0) * [EA LPC11U35](http://developer.mbed.org/platforms/EA-LPC11U35/) (Cortex-M0) * mbed LPC2368 (ARM7TDMI-S) +* LPC2460 (ARM7TDMI-S) * LPC810 (Cortex-M0+) * [LPC812](http://developer.mbed.org/platforms/NXP-LPC800-MAX/) (Cortex-M0+) * [EA LPC4088](http://developer.mbed.org/platforms/EA-LPC4088/) (Cortex-M4F) From 8122f63861791f47e01a5ef76c340e3d33e5ee39 Mon Sep 17 00:00:00 2001 From: Dmitry Bogdanov Date: Mon, 18 May 2015 20:34:53 +0400 Subject: [PATCH 028/139] add Travis build target for LPC2460 --- workspace_tools/build_travis.py | 1 + 1 file changed, 1 insertion(+) diff --git a/workspace_tools/build_travis.py b/workspace_tools/build_travis.py index 46e7e6c3e8..9baa832bd6 100644 --- a/workspace_tools/build_travis.py +++ b/workspace_tools/build_travis.py @@ -29,6 +29,7 @@ import sys build_list = ( { "target": "LPC1768", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "eth", "usb_host", "usb", "ublox", "fat"] }, { "target": "LPC2368", "toolchains": "GCC_ARM", "libs": ["fat"] }, + { "target": "LPC2460", "toolchains": "GCC_ARM", "libs": ["rtos", "usb_host", "usb", "fat"] }, { "target": "LPC11U24", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "OC_MBUINO", "toolchains": "GCC_ARM", "libs": ["fat"] }, From 9c329b93573127e6bc28d0de3510ab0e87953edb Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Wed, 20 May 2015 10:50:45 +0900 Subject: [PATCH 029/139] Remove analogout_api.c Remove toolchain ARM at targets.py --- .../TARGET_W7500x/analogout_api.c | 64 ------------------- workspace_tools/targets.py | 4 +- 2 files changed, 2 insertions(+), 66 deletions(-) delete mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogout_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogout_api.c deleted file mode 100644 index 5b77b3febe..0000000000 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogout_api.c +++ /dev/null @@ -1,64 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "mbed_assert.h" -#include "analogout_api.h" - -#if DEVICE_ANALOGOUT - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" - -#define DAC_RANGE (0xFFF) // 12 bits - -static DAC_HandleTypeDef DacHandle; - -void analogout_init(dac_t *obj, PinName pin) -{ - -} - -void analogout_free(dac_t *obj) -{ -} - -static inline void dac_write(dac_t *obj, uint16_t value) -{ -} - -static inline int dac_read(dac_t *obj) -{ -} - -void analogout_write(dac_t *obj, float value) -{ -} - -void analogout_write_u16(dac_t *obj, uint16_t value) -{ -} - -float analogout_read(dac_t *obj) -{ -} - -uint16_t analogout_read_u16(dac_t *obj) -{ -} - -#endif // DEVICE_ANALOGOUT diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 93c8b630ec..0b148f35c2 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -76,8 +76,8 @@ class WIZwiki_W7500(Target): Target.__init__(self) self.core = "Cortex-M0" self.extra_labels = ['WIZNET', 'W7500x', 'WIZwiki_W7500'] - self.supported_toolchains = ["ARM", "uARM",] - self.default_toolchain = "ARM" + self.supported_toolchains = ["uARM",] + self.default_toolchain = "uARM" self.supported_form_factors = ["ARDUINO"] From 0551f6e8b955bd081d69afd121ef2e84f17a0189 Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Thu, 21 May 2015 15:17:17 -0500 Subject: [PATCH 030/139] Added tests for the WFI instruction --- libraries/tests/mbed/wfi/main.cpp | 18 +++++++++++++ workspace_tools/host_tests/__init__.py | 2 ++ workspace_tools/host_tests/wfi_auto.py | 37 ++++++++++++++++++++++++++ workspace_tools/tests.py | 9 +++++-- 4 files changed, 64 insertions(+), 2 deletions(-) create mode 100644 libraries/tests/mbed/wfi/main.cpp create mode 100644 workspace_tools/host_tests/wfi_auto.py diff --git a/libraries/tests/mbed/wfi/main.cpp b/libraries/tests/mbed/wfi/main.cpp new file mode 100644 index 0000000000..775872c650 --- /dev/null +++ b/libraries/tests/mbed/wfi/main.cpp @@ -0,0 +1,18 @@ +#include "mbed.h" +#include "test_env.h" + +int main(void) +{ + MBED_HOSTTEST_TIMEOUT(15); + MBED_HOSTTEST_SELECT(wfi_auto); + MBED_HOSTTEST_DESCRIPTION(WFI correct behavior); + MBED_HOSTTEST_START("MBED_36"); + + + int count = 0; + + while(1) { + printf("%d\r\n", count++); + __WFI(); + } +} diff --git a/workspace_tools/host_tests/__init__.py b/workspace_tools/host_tests/__init__.py index cae0e20908..3e3f10f55c 100644 --- a/workspace_tools/host_tests/__init__.py +++ b/workspace_tools/host_tests/__init__.py @@ -30,6 +30,7 @@ from tcpecho_server_auto import TCPEchoServerTest from udpecho_server_auto import UDPEchoServerTest from tcpecho_client_auto import TCPEchoClientTest from udpecho_client_auto import UDPEchoClientTest +from wfi_auto import WFITest # Populate registry with supervising objects HOSTREGISTRY = HostRegistry() @@ -46,6 +47,7 @@ HOSTREGISTRY.register_host_test("tcpecho_server_auto", TCPEchoServerTest()) HOSTREGISTRY.register_host_test("udpecho_server_auto", UDPEchoServerTest()) HOSTREGISTRY.register_host_test("tcpecho_client_auto", TCPEchoClientTest()) HOSTREGISTRY.register_host_test("udpecho_client_auto", UDPEchoClientTest()) +HOSTREGISTRY.register_host_test("wfi_auto", WFITest()) ############################################################################### # Functional interface for test supervisor registry diff --git a/workspace_tools/host_tests/wfi_auto.py b/workspace_tools/host_tests/wfi_auto.py new file mode 100644 index 0000000000..b51beca13f --- /dev/null +++ b/workspace_tools/host_tests/wfi_auto.py @@ -0,0 +1,37 @@ +""" +mbed SDK +Copyright (c) 2011-2013 ARM Limited + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" + +import sys +import uuid +import time +from sys import stdout + +class WFITest(): + + def test(self, selftest): + result = True + c = selftest.mbed.serial_readline() + if c is None or c.strip() != "0": + return selftest.RESULT_IO_SERIAL + + # Wait 10 seconds to allow serial prints (indicating failure) + selftest.mbed.set_serial_timeout(10) + + # If no characters received, pass the test + result = not selftest.mbed.serial_readline() + + return selftest.RESULT_SUCCESS if result else selftest.RESULT_FAILURE diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py index 815c292035..1f8060f4d3 100644 --- a/workspace_tools/tests.py +++ b/workspace_tools/tests.py @@ -66,7 +66,7 @@ Wiring: * analog_pot (AnalogIn): * Arduino headers: (A0, A1) - + * SD (SPI): * LPC1*: (mosi=p11 , miso=p12 , sclk=p13 , cs=p14 ) * KL25Z: (mosi=PTD2, miso=PTD3, sclk=PTD1, cs=PTD0) @@ -579,7 +579,12 @@ TESTS = [ "automated": True, "duration": 10, }, - + { + "id": "MBED_36", "description": "WFI correct behavior", + "source_dir": join(TEST_DIR, "mbed", "wfi"), + "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB], + "automated": True + }, # CMSIS RTOS tests { From 5fb844ce8701e585254cec2d7ae19965d5fb03b7 Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Fri, 22 May 2015 08:04:37 +0900 Subject: [PATCH 031/139] Change startup code for toolchain ARM Add possible toolchain ARM at targets.py --- .../TOOLCHAIN_ARM_MICRO/startup_W7500x.s | 6 +++--- workspace_tools/targets.py | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s index 1cbb5d3f56..410655e1f7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s @@ -31,18 +31,18 @@ ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Stack_Size EQU 0x00000200 +Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size -__initial_sp +__initial_sp EQU 0x20004000 ; Top of RAM (8 KB for STM32F030R8) ; Heap Configuration ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Heap_Size EQU 0x00000100 +Heap_Size EQU 0x00000400 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 0b148f35c2..47e38db303 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -76,8 +76,8 @@ class WIZwiki_W7500(Target): Target.__init__(self) self.core = "Cortex-M0" self.extra_labels = ['WIZNET', 'W7500x', 'WIZwiki_W7500'] - self.supported_toolchains = ["uARM",] - self.default_toolchain = "uARM" + self.supported_toolchains = ["uARM", "ARM"] + self.default_toolchain = "ARM" self.supported_form_factors = ["ARDUINO"] From feb9f51e2c6e572ca8adf57ed3ba18548b1e0444 Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Fri, 22 May 2015 09:34:46 +0900 Subject: [PATCH 032/139] Now, we support toolchain ARM. So Add the files. --- .../TOOLCHAIN_ARM_STD/W7500.sct | 15 ++ .../TOOLCHAIN_ARM_STD/startup_W7500x.s | 186 ++++++++++++++++++ .../TOOLCHAIN_ARM_STD/sys.cpp | 31 +++ .../TARGET_WIZwiki_W7500/device.h | 2 +- 4 files changed, 233 insertions(+), 1 deletion(-) create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/W7500.sct create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/startup_W7500x.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/sys.cpp diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/W7500.sct b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/W7500.sct new file mode 100644 index 0000000000..f9ead04667 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/W7500.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00020000 { ; load region size_region + ER_IROM1 0x00000000 0x00020000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00004000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/startup_W7500x.s b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/startup_W7500x.s new file mode 100644 index 0000000000..5b161ed02e --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/startup_W7500x.s @@ -0,0 +1,186 @@ +;/**************************************************************************//** +; * @file startup_CMSDK_CM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File for +; * Device CMSDK_CM0 +; * @version V3.01 +; * @date 06. March 2012 +; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER + +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +__initial_sp EQU 0x20004000 ; Top of RAM (16 KB for WIZwiki_W7500) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + DCD SSP0_Handler ; 16+ 0: SSP 0 Handler + DCD SSP1_Handler ; 16+ 1: SSP 1 Handler + DCD UART0_Handler ; 16+ 2: UART 0 Handler + DCD UART1_Handler ; 16+ 3: UART 1 Handler + DCD UART2_Handler ; 16+ 4: UART 2 Handler + DCD I2C0_Handler ; 16+ 5: I2C 0 Handler + DCD I2C1_Handler ; 16+ 6: I2C 1 Handler + DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler + DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler + DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler + DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler + DCD DMA_Handler ; 16+11: DMA Combined Handler + DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler + DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler + DCD PWM0_Handler ; 16+14: PWM0 Handler + DCD PWM1_Handler ; 16+15: PWM1 Handler + DCD PWM2_Handler ; 16+16: PWM2 Handler + DCD PWM3_Handler ; 16+17: PWM3 Handler + DCD PWM4_Handler ; 16+18: PWM4 Handler + DCD PWM5_Handler ; 16+19: PWM5 Handler + DCD PWM6_Handler ; 16+20: PWM6 Handler + DCD PWM7_Handler ; 16+21: PWM7 Handler + DCD RTC_Handler ; 16+22: RTC Handler + DCD ADC_Handler ; 16+23: ADC Handler + DCD WZTOE_Handler ; 16+24: WZTOE_Handler + DCD EXTI_Handler ; 16+25: EXTI_Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Default_Handler PROC + EXPORT SSP0_Handler [WEAK] + EXPORT SSP1_Handler [WEAK] + EXPORT UART0_Handler [WEAK] + EXPORT UART1_Handler [WEAK] + EXPORT UART2_Handler [WEAK] + EXPORT I2C0_Handler [WEAK] + EXPORT I2C1_Handler [WEAK] + EXPORT PORT0_Handler [WEAK] + EXPORT PORT1_Handler [WEAK] + EXPORT PORT2_Handler [WEAK] + EXPORT PORT3_Handler [WEAK] + EXPORT DMA_Handler [WEAK] + EXPORT DUALTIMER0_Handler [WEAK] + EXPORT DUALTIMER1_Handler [WEAK] + EXPORT PWM0_Handler [WEAK] + EXPORT PWM1_Handler [WEAK] + EXPORT PWM2_Handler [WEAK] + EXPORT PWM3_Handler [WEAK] + EXPORT PWM4_Handler [WEAK] + EXPORT PWM5_Handler [WEAK] + EXPORT PWM6_Handler [WEAK] + EXPORT PWM7_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT WZTOE_Handler [WEAK] + EXPORT EXTI_Handler [WEAK] +SSP0_Handler +SSP1_Handler +UART0_Handler +UART1_Handler +UART2_Handler +I2C0_Handler +I2C1_Handler +PORT0_Handler +PORT1_Handler +PORT2_Handler +PORT3_Handler +DMA_Handler +DUALTIMER0_Handler +DUALTIMER1_Handler +PWM0_Handler +PWM1_Handler +PWM2_Handler +PWM3_Handler +PWM4_Handler +PWM5_Handler +PWM6_Handler +PWM7_Handler +RTC_Handler +ADC_Handler +WZTOE_Handler +EXTI_Handler + B . + ENDP + + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..2f1024ace8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library - stackheap + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h index f94476da70..aae25ad347 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h @@ -52,7 +52,7 @@ #define DEVICE_PWMOUT 0 -#define DEVICE_SLEEP 1 +#define DEVICE_SLEEP 0 #define DEVICE_ETHERNET 0 From 82dd920c7e12db5fb2e9372fa100bb75173aacfd Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Fri, 22 May 2015 09:44:03 +0900 Subject: [PATCH 033/139] Change Stack size and heap size to 0x400 --- .../TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s index 410655e1f7..124a5e65c8 100644 --- a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s @@ -35,7 +35,7 @@ Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20004000 ; Top of RAM (8 KB for STM32F030R8) +__initial_sp EQU 0x20004000 ; Top of RAM (16 KB for WIZwiki_W7500) ; Heap Configuration From 446bcdd7dfc185cc4ec1677d19bfce97a3d255aa Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Fri, 22 May 2015 10:05:40 +0900 Subject: [PATCH 034/139] Change header scripts about PeripheralPins.c and PeripheralPins.h --- .../TARGET_W7500x/PeripheralPins.h | 30 ++++++++++++++++ .../TARGET_WIZwiki_W7500/PeripheralPins.c | 36 ++++++------------- 2 files changed, 40 insertions(+), 26 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h index 9a5d507fa7..2a42b0b568 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h @@ -1,3 +1,33 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ #ifndef MBED_PERIPHERALPINS_H #define MBED_PERIPHERALPINS_H diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c index 136a93f8cb..85d7195dea 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c @@ -1,34 +1,18 @@ /* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. + * Copyright (c) 2006-2013 ARM Limited * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * http://www.apache.org/licenses/LICENSE-2.0 * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ - #include "PeripheralPins.h" #include "PeripheralNames.h" #include "pinmap.h" From 8fae6b7a85f39a28f9fc75ee862fbce1a06d35d3 Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Fri, 22 May 2015 10:42:56 +0900 Subject: [PATCH 035/139] Change to static. --- .../mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c index af28f7924e..1a2c52af9f 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c @@ -27,7 +27,7 @@ ADC_TypeDef * AdcHandle; -int adc_inited = 0; +static int adc_inited = 0; void analogin_init(analogin_t *obj, PinName pin) { From fef219f493d2f4957ff86c2c501b38714cfc1ace Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Fri, 22 May 2015 14:08:01 +0900 Subject: [PATCH 036/139] Disable I2C slave --- .../TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h index aae25ad347..8299147f84 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h @@ -43,7 +43,7 @@ #define DEVICE_SERIAL 1 #define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 +#define DEVICE_I2CSLAVE 0 #define DEVICE_SPI 1 #define DEVICE_SPISLAVE 1 From 1cb4afc60b8e4260e20617b35d5811e934117bb5 Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Fri, 22 May 2015 10:16:05 -0500 Subject: [PATCH 037/139] Returns IO_FAIL when inital output is incorrect instead of IO_SERIAL --- workspace_tools/host_tests/wfi_auto.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/workspace_tools/host_tests/wfi_auto.py b/workspace_tools/host_tests/wfi_auto.py index b51beca13f..5f9e211548 100644 --- a/workspace_tools/host_tests/wfi_auto.py +++ b/workspace_tools/host_tests/wfi_auto.py @@ -25,9 +25,13 @@ class WFITest(): def test(self, selftest): result = True c = selftest.mbed.serial_readline() - if c is None or c.strip() != "0": + + if c is None return selftest.RESULT_IO_SERIAL + if c.strip() != "0": + return selftest.RESULT_IO_FAIL + # Wait 10 seconds to allow serial prints (indicating failure) selftest.mbed.set_serial_timeout(10) From f0861ccda50495de472219e8ebbd3ec19d964233 Mon Sep 17 00:00:00 2001 From: Marcus Chang Date: Fri, 22 May 2015 17:30:08 +0100 Subject: [PATCH 038/139] SPI transfers larger than what the DMA can handle are split up in multiple transfers. --- .../TARGET_EFM32/spi_api.c | 33 ++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c index bc1bc5738e..0a3dbd6e93 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c @@ -767,8 +767,26 @@ static void spi_activate_dma(spi_t *obj, void* rxdata, void* txdata, int tx_leng DMA_CfgDescr_TypeDef rxDescrCfg; DMA_CfgDescr_TypeDef txDescrCfg; + /* Split up transfers if the tx length is larger than what the DMA supports. */ + const int DMA_MAX_TRANSFER = (_DMA_CTRL_N_MINUS_1_MASK >> _DMA_CTRL_N_MINUS_1_SHIFT); + + if (tx_length > DMA_MAX_TRANSFER) + { + uint32_t max_length = DMA_MAX_TRANSFER; + + /* Make sure only an even amount of bytes are transferred + if the width is larger than 8 bits. */ + if (obj->spi.bits > 8) + { + max_length = DMA_MAX_TRANSFER - (DMA_MAX_TRANSFER & 0x01); + } + + /* Update length for current transfer. */ + tx_length = max_length; + } + /* Save amount of TX done by DMA */ - obj->tx_buff.pos = tx_length; + obj->tx_buff.pos += tx_length; if(obj->spi.bits != 9) { /* Only activate RX DMA if a receive buffer is specified */ @@ -966,6 +984,19 @@ uint32_t spi_irq_handler_asynch(spi_t* obj) if (obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_ALLOCATED || obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { /* DMA implementation */ + /* If there is still data in the TX buffer, setup a new transfer. */ + if (obj->tx_buff.pos < obj->tx_buff.length) + { + /* Find position and remaining length without modifying tx_buff. */ + void* tx_pointer = obj->tx_buff.buffer + obj->tx_buff.pos; + uint32_t tx_length = obj->tx_buff.length - obj->tx_buff.pos; + + /* Begin transfer. Rely on spi_activate_dma to split up the transfer further. */ + spi_activate_dma(obj, obj->rx_buff.buffer, tx_pointer, tx_length, obj->rx_buff.length); + + return 0; + } + /* If there is an RX transfer ongoing, wait for it to finish */ if (DMA_ChannelEnabled(obj->spi.dmaOptionsRX.dmaChannel)) { /* Check if we need to kick off TX transfer again to force more incoming data. */ From 8edb20bed6b9481d434315693ebd8278d458adab Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Sun, 26 Apr 2015 02:28:24 +0200 Subject: [PATCH 039/139] [NUCLEO_F446RE] create the new target Create the new target - mbed_blinky is runnning --- .../TOOLCHAIN_GCC_ARM/STM32F411XE.ld | 153 + .../TOOLCHAIN_GCC_ARM/startup_stm32f411xe.s | 459 + .../TARGET_NUCLEO_F446RE/cmsis.h | 38 + .../TARGET_NUCLEO_F446RE/cmsis_nvic.c | 55 + .../TARGET_NUCLEO_F446RE/cmsis_nvic.h | 55 + .../TARGET_NUCLEO_F446RE/hal_tick.c | 122 + .../TARGET_NUCLEO_F446RE/hal_tick.h | 60 + .../TARGET_NUCLEO_F446RE/stm32f446xx.h | 8217 +++++++++++++++++ .../TARGET_NUCLEO_F446RE/stm32f4xx.h | 232 + .../TARGET_NUCLEO_F446RE/stm32f4xx_hal_conf.h | 405 + .../TARGET_NUCLEO_F446RE/system_stm32f4xx.c | 706 ++ .../TARGET_NUCLEO_F446RE/system_stm32f4xx.h | 123 + .../TARGET_NUCLEO_F446RE/PeripheralNames.h | 87 + .../TARGET_NUCLEO_F446RE/PeripheralPins.c | 200 + .../TARGET_NUCLEO_F446RE/PinNames.h | 185 + .../TARGET_NUCLEO_F446RE/PortNames.h | 51 + .../TARGET_NUCLEO_F446RE/device.h | 70 + .../TARGET_NUCLEO_F446RE/objects.h | 108 + workspace_tools/export/coide.py | 1 + .../export/coide_nucleo_f446re.coproj.tmpl | 90 + .../export/gcc_arm_nucleo_f446re.tmpl | 78 + workspace_tools/export/gccarm.py | 1 + workspace_tools/targets.py | 10 + 23 files changed, 11506 insertions(+) create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/TOOLCHAIN_GCC_ARM/STM32F411XE.ld create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/cmsis.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/cmsis_nvic.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/cmsis_nvic.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/hal_tick.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/hal_tick.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f446xx.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f4xx.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f4xx_hal_conf.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.h create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PeripheralNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PeripheralPins.c create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PinNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PortNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/device.h create mode 100644 libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/objects.h create mode 100644 workspace_tools/export/coide_nucleo_f446re.coproj.tmpl create mode 100644 workspace_tools/export/gcc_arm_nucleo_f446re.tmpl diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/TOOLCHAIN_GCC_ARM/STM32F411XE.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/TOOLCHAIN_GCC_ARM/STM32F411XE.ld new file mode 100644 index 0000000000..c028371d60 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/TOOLCHAIN_GCC_ARM/STM32F411XE.ld @@ -0,0 +1,153 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K + RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.s new file mode 100644 index 0000000000..8950a21b6b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.s @@ -0,0 +1,459 @@ +/** + ****************************************************************************** + * @file startup_stm32f411xe.s + * @author MCD Application Team + * @version V2.3.0 + * @date 02-March-2015 + * @brief STM32F411xExx Devices vector table for Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word 0 /* Reserved */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/cmsis.h new file mode 100644 index 0000000000..f0c2b2a907 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/cmsis_nvic.c new file mode 100644 index 0000000000..2da63fc9af --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/cmsis_nvic.c @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t *)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/cmsis_nvic.h new file mode 100644 index 0000000000..a98d56f154 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/cmsis_nvic.h @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F411RE +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 86 vectors = 344 bytes from 0x40 to 0x197 +// Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM +#define NVIC_NUM_VECTORS 102 +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/hal_tick.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/hal_tick.c new file mode 100644 index 0000000000..bd400d4379 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/hal_tick.c @@ -0,0 +1,122 @@ +/** + ****************************************************************************** + * @file hal_tick.c + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "hal_tick.h" + +TIM_HandleTypeDef TimMasterHandle; +uint32_t PreviousVal = 0; + +void us_ticker_irq_handler(void); + +void timer_irq_handler(void) { + // Channel 1 for mbed timeout + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) { + us_ticker_irq_handler(); + } + + // Channel 2 for HAL tick + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2); + uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle); + if ((val - PreviousVal) >= HAL_TICK_DELAY) { + // Increment HAL variable + HAL_IncTick(); + // Prepare next interrupt + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY); + PreviousVal = val; +#if 0 // For DEBUG only + HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6); +#endif + } + } +} + +// Reconfigure the HAL tick using a standard timer instead of systick. +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + // Enable timer clock + TIM_MST_RCC; + + // Reset timer + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; + + // Update the SystemCoreClock variable + SystemCoreClockUpdate(); + + // Configure time base + TimMasterHandle.Instance = TIM_MST; + TimMasterHandle.Init.Period = 0xFFFFFFFF; + TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick + TimMasterHandle.Init.ClockDivision = 0; + TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + TimMasterHandle.Init.RepetitionCounter = 0; + HAL_TIM_OC_Init(&TimMasterHandle); + + NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler); + NVIC_EnableIRQ(TIM_MST_IRQ); + + // Channel 1 for mbed timeout + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1); + + // Channel 2 for HAL tick + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); + PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); + +#if 0 // For DEBUG only + __GPIOB_CLK_ENABLE(); + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FAST; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/hal_tick.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/hal_tick.h new file mode 100644 index 0000000000..2e6f01b8a6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/hal_tick.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM5 +#define TIM_MST_IRQ TIM5_IRQn +#define TIM_MST_RCC __TIM5_CLK_ENABLE() + +#define TIM_MST_RESET_ON __TIM5_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f446xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f446xx.h new file mode 100644 index 0000000000..162c73b566 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f446xx.h @@ -0,0 +1,8217 @@ +/** + ****************************************************************************** + * @file stm32f446xx.h + * @author MCD Application Team + * @version V2.3.0 + * @date 02-March-2015 + * @brief CMSIS STM32F446xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f446xx + * @{ + */ + +#ifndef __STM32F446xx_H +#define __STM32F446xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */ + CEC_IRQn = 93, /*!< CEC global Interrupt */ + SPDIF_RX_IRQn = 94, /*!< SPDIF-RX global Interrupt */ + FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */ + FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ +} FLASH_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5_6 + */ + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */ + __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ + __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ +} I2C_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */ +} FMPI2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ + __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ + __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */ + __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief SPDIFRX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + uint16_t RESERVED0; /*!< Reserved, 0x06 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + uint16_t RESERVED1; /*!< Reserved, 0x0E */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ + uint16_t RESERVED2; /*!< Reserved, 0x1A */ +} SPDIFRX_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ +#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ +#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ +#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ +#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */ +#define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< QuadSPI registers base address */ + +#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) +#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define CEC_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x004) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x024) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) + +/*!< FMC Bankx registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) + +/*!< Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t )0xE0042000) + +/*!< USB registers base address */ +#define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000) +#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000) + +#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000) +#define USB_OTG_DEVICE_BASE ((uint32_t )0x800) +#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900) +#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00) +#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20) +#define USB_OTG_HOST_BASE ((uint32_t )0x400) +#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440) +#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500) +#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20) +#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00) +#define USB_OTG_FIFO_BASE ((uint32_t )0x1000) +#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint32_t)0x00000001) /*!
© COPYRIGHT(c) 2015 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx + * @{ + */ + +#ifndef __STM32F4xx_H +#define __STM32F4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F4) +#define STM32F4 +#endif /* STM32F4 */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ +#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ + !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ + !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx) + /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ + /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ + /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ + /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ + /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */ + /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */ + /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, + STM32F439NI, STM32F429IG and STM32F429II Devices */ + /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, + STM32F439NI, STM32F439IG and STM32F439II Devices */ + /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ + /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ + /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */ + #define STM32F446xx /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, + and STM32F446ZE Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + #define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V2.3.0 + */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ + |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\ + |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\ + |(__STM32F4xx_CMSIS_DEVICE_VERSION)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F405xx) + #include "stm32f405xx.h" +#elif defined(STM32F415xx) + #include "stm32f415xx.h" +#elif defined(STM32F407xx) + #include "stm32f407xx.h" +#elif defined(STM32F417xx) + #include "stm32f417xx.h" +#elif defined(STM32F427xx) + #include "stm32f427xx.h" +#elif defined(STM32F437xx) + #include "stm32f437xx.h" +#elif defined(STM32F429xx) + #include "stm32f429xx.h" +#elif defined(STM32F439xx) + #include "stm32f439xx.h" +#elif defined(STM32F401xC) + #include "stm32f401xc.h" +#elif defined(STM32F401xE) + #include "stm32f401xe.h" +#elif defined(STM32F411xE) + #include "stm32f411xe.h" +#elif defined(STM32F446xx) + #include "stm32f446xx.h" +#else + #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macro + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f4xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F4xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f4xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f4xx_hal_conf.h new file mode 100644 index 0000000000..f44a1df529 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f4xx_hal_conf.h @@ -0,0 +1,405 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 26-December-2014 + * @brief HAL configuration file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_CAN_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +#define HAL_CRYP_MODULE_ENABLED +#define HAL_DAC_MODULE_ENABLED +#define HAL_DCMI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_DMA2D_MODULE_ENABLED +#define HAL_ETH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_NAND_MODULE_ENABLED +#define HAL_NOR_MODULE_ENABLED +#define HAL_PCCARD_MODULE_ENABLED +#define HAL_SRAM_MODULE_ENABLED +#define HAL_SDRAM_MODULE_ENABLED +#define HAL_HASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +#define HAL_LTDC_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_SAI_MODULE_ENABLED +#define HAL_SD_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +#define HAL_IRDA_MODULE_ENABLED +#define HAL_SMARTCARD_MODULE_ENABLED +#define HAL_WWDG_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED + + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */ +#define USE_RTOS 0 +#define PREFETCH_ENABLE 1 +#define INSTRUCTION_CACHE_ENABLE 1 +#define DATA_CACHE_ENABLE 1 + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1 */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2 +#define MAC_ADDR1 0 +#define MAC_ADDR2 0 +#define MAC_ADDR3 0 +#define MAC_ADDR4 0 +#define MAC_ADDR5 0 + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848 PHY Address*/ +#define DP83848_PHY_ADDRESS 0x01 +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FF) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) + +#define PHY_READ_TO ((uint32_t)0x0000FFFF) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFF) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ + +#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */ +#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */ +#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */ + +#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ + +#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ +#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ + +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.c new file mode 100644 index 0000000000..d09a7dc7fc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.c @@ -0,0 +1,706 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @version V2.1.0 + * @date 19-June-2014 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI + * | (external 8 MHz clock) | (internal 16 MHz) + * | 2- PLL_HSE_XTAL | + * | (external 8 MHz xtal) | + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 96 | 96 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 96 | 96 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 48 | 48 + *----------------------------------------------------------------------------- + * APB2CLK (MHz) | 96 | 96 + *----------------------------------------------------------------------------- + * USB capable (48 MHz precise clock) | YES | YES + *----------------------------------------------------------------------------- + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" +#include "hal_tick.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted + on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) + #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ +#define USE_PLL_HSE_EXTC (1) /* Use external clock */ +#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif + +uint8_t SetSysClock_PLL_HSI(void); + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + + /* Configure the Cube driver */ + SystemCoreClock = 16000000; // At this stage the HSI is used as system clock + HAL_Init(); + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings */ + SetSysClock(); + + /* Reset the timer to avoid issues after the RAM initialization */ + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration ------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + + /* Configure and enable SDRAM bank1 */ + FMC_Bank5_6->SDCR[0] = 0x000019E0; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +} +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + /* 1- Try to start with HSE and external clock */ +#if USE_PLL_HSE_EXTC != 0 + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { + /* 2- If fail try to start with HSE and external xtal */ + #if USE_PLL_HSE_XTAL != 0 + if (SetSysClock_PLL_HSE(0) == 0) + #endif + { + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) + { + while(1) + { + // [TODO] Put something here to tell the user that a problem occured... + } + } + } + } + + /* Output clock on MCO2 pin(PC9) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz +} + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + + /* Enable HSE oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) + { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ + } + else + { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ + } + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) + //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384) + RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4) + RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4) + RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) + { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + + //if (bypass == 0) + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal + //else + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock + + return 1; // OK +} +#endif + +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + + /* Enable HSI oscillator and activate PLL with HSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) + //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384) + RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) + RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4) + RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) + { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz + + return 1; // OK +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.h new file mode 100644 index 0000000000..ea2f070a6b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.h @@ -0,0 +1,123 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.h + * @author MCD Application Team + * @version V2.3.0 + * @date 02-March-2015 + * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F4XX_H +#define __SYSTEM_STM32F4XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F4xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F4xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F4XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PeripheralNames.h new file mode 100644 index 0000000000..2d8197e594 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PeripheralNames.h @@ -0,0 +1,87 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE +} ADCName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE, + UART_6 = (int)USART6_BASE +} UARTName; + +#define STDIO_UART_TX PA_2 +#define STDIO_UART_RX PA_3 +#define STDIO_UART UART_2 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE, + SPI_4 = (int)SPI4_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, + PWM_9 = (int)TIM9_BASE, + PWM_10 = (int)TIM10_BASE, + PWM_11 = (int)TIM11_BASE, + PWM_13 = (int)TIM13_BASE, + PWM_14 = (int)TIM14_BASE +} PWMName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PeripheralPins.c new file mode 100644 index 0000000000..a748b48316 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PeripheralPins.c @@ -0,0 +1,200 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { +//OH {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, +//OH {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, +// {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, // Warning: also on SCL + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO +// {PB_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 +// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 1, 0)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 +// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO +// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO + {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, +// {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO +// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, +// {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Warning: also on NSS + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, +// {PB_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, +// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, +// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Warning: also on SCLK +// {PB_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, // Warning: also on SCLK + {NC, NC, 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PinNames.h new file mode 100644 index 0000000000..60718d7a8d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PinNames.h @@ -0,0 +1,185 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) +#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_MODE_INPUT (0) +#define STM_MODE_OUTPUT_PP (1) +#define STM_MODE_OUTPUT_OD (2) +#define STM_MODE_AF_PP (3) +#define STM_MODE_AF_OD (4) +#define STM_MODE_ANALOG (5) +#define STM_MODE_IT_RISING (6) +#define STM_MODE_IT_FALLING (7) +#define STM_MODE_IT_RISING_FALLING (8) +#define STM_MODE_EVT_RISING (9) +#define STM_MODE_EVT_FALLING (10) +#define STM_MODE_EVT_RISING_FALLING (11) +#define STM_MODE_IT_EVT_RESET (12) + +// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H) +// Low nibble = pin number +#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF) +#define STM_PIN(X) ((uint32_t)(X) & 0xF) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_2 = 0x12, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_15 = 0x1F, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_9 = 0x29, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_2 = 0x32, + + PH_0 = 0x70, + PH_1 = 0x71, + + // Arduino connector namings + A0 = PA_0, + A1 = PA_1, + A2 = PA_4, + A3 = PB_0, + A4 = PC_1, + A5 = PC_0, + D0 = PA_3, + D1 = PA_2, + D2 = PA_10, + D3 = PB_3, + D4 = PB_5, + D5 = PB_4, + D6 = PB_10, + D7 = PA_8, + D8 = PA_9, + D9 = PC_7, + D10 = PB_6, + D11 = PA_7, + D12 = PA_6, + D13 = PA_5, + D14 = PB_9, + D15 = PB_8, + + // Generic signals namings + LED1 = PA_5, + LED2 = PA_5, + LED3 = PA_5, + LED4 = PA_5, + USER_BUTTON = PC_13, + SERIAL_TX = PA_2, + SERIAL_RX = PA_3, + USBTX = PA_2, + USBRX = PA_3, + I2C_SCL = PB_8, + I2C_SDA = PB_9, + SPI_MOSI = PA_7, + SPI_MISO = PA_6, + SPI_SCK = PA_5, + SPI_CS = PB_6, + PWM_OUT = PB_3, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + OpenDrain = 3, + PullDefault = PullNone +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PortNames.h new file mode 100644 index 0000000000..4f9af48f2c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PortNames.h @@ -0,0 +1,51 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, + PortE = 4, + PortF = 5, + PortG = 6, + PortH = 7 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/device.h new file mode 100644 index 0000000000..57a7aa227d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/device.h @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 // Not present on this device + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/objects.h new file mode 100644 index 0000000000..d8b93568f7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/objects.h @@ -0,0 +1,108 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct analogin_s { + ADCName adc; + PinName pin; + uint8_t channel; +}; + +struct serial_s { + UARTName uart; + int index; // Used by irq + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + PinName pin_tx; + PinName pin_rx; +}; + +struct spi_s { + SPIName spi; + uint32_t bits; + uint32_t cpol; + uint32_t cpha; + uint32_t mode; + uint32_t nss; + uint32_t br_presc; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; +}; + +struct i2c_s { + I2CName i2c; + uint32_t slave; +}; + +struct pwmout_s { + PWMName pwm; + PinName pin; + uint32_t period; + uint32_t pulse; + uint8_t channel; + uint8_t inverted; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/workspace_tools/export/coide.py b/workspace_tools/export/coide.py index 7070394e27..4e6471da62 100755 --- a/workspace_tools/export/coide.py +++ b/workspace_tools/export/coide.py @@ -41,6 +41,7 @@ class CoIDE(Exporter): 'NUCLEO_F334R8', 'NUCLEO_F401RE', 'NUCLEO_F411RE', + 'NUCLEO_F446RE', 'DISCO_L053C8', 'DISCO_F051R8', 'DISCO_F100RB', diff --git a/workspace_tools/export/coide_nucleo_f446re.coproj.tmpl b/workspace_tools/export/coide_nucleo_f446re.coproj.tmpl new file mode 100644 index 0000000000..8b4bdf5568 --- /dev/null +++ b/workspace_tools/export/coide_nucleo_f446re.coproj.tmpl @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + {% for file in source_files %} + + {% endfor %} + {% for file in header_files %} + + {% endfor %} + + diff --git a/workspace_tools/export/gcc_arm_nucleo_f446re.tmpl b/workspace_tools/export/gcc_arm_nucleo_f446re.tmpl new file mode 100644 index 0000000000..224ceb2fae --- /dev/null +++ b/workspace_tools/export/gcc_arm_nucleo_f446re.tmpl @@ -0,0 +1,78 @@ +# This file was automagically generated by mbed.org. For more information, +# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded + +GCC_BIN = +PROJECT = {{name}} +OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %} +SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %} +INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %} +LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %} +LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %} +LINKER_SCRIPT = {{linker_script}} + +############################################################################### +AS = $(GCC_BIN)arm-none-eabi-as +CC = $(GCC_BIN)arm-none-eabi-gcc +CPP = $(GCC_BIN)arm-none-eabi-g++ +LD = $(GCC_BIN)arm-none-eabi-gcc +OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy +OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump +SIZE = $(GCC_BIN)arm-none-eabi-size + +CPU = -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=$(FLOAT_ABI) +CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer +CC_FLAGS += -MMD -MP +CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %} + +LD_FLAGS = $(CPU) -Wl,--gc-sections --specs=nano.specs -u _printf_float -u _scanf_float -Wl,--wrap,main +LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref +LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys + +ifeq ($(HARDFP),1) + FLOAT_ABI = hard +else + FLOAT_ABI = softfp +endif + +ifeq ($(DEBUG), 1) + CC_FLAGS += -DDEBUG -O0 +else + CC_FLAGS += -DNDEBUG -Os +endif + +all: $(PROJECT).bin $(PROJECT).hex + +clean: + rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS) + +.s.o: + $(AS) $(CPU) -o $@ $< + +.c.o: + $(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $< + +.cpp.o: + $(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 -fno-rtti $(INCLUDE_PATHS) -o $@ $< + + +$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS) + $(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS) + $(SIZE) $@ + +$(PROJECT).bin: $(PROJECT).elf + @$(OBJCOPY) -O binary $< $@ + +$(PROJECT).hex: $(PROJECT).elf + @$(OBJCOPY) -O ihex $< $@ + +$(PROJECT).lst: $(PROJECT).elf + @$(OBJDUMP) -Sdh $< > $@ + +lst: $(PROJECT).lst + +size: + $(SIZE) $(PROJECT).elf + +DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d) +-include $(DEPS) + diff --git a/workspace_tools/export/gccarm.py b/workspace_tools/export/gccarm.py index 2f9865e045..61f1f68375 100755 --- a/workspace_tools/export/gccarm.py +++ b/workspace_tools/export/gccarm.py @@ -59,6 +59,7 @@ class GccArm(Exporter): 'ARCH_MAX', 'NUCLEO_F401RE', 'NUCLEO_F411RE', + 'NUCLEO_F446RE', 'ARCH_MAX', 'DISCO_F429ZI', 'NUCLEO_F030R8', diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index b7d59ce3e7..a15ac51b71 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -587,6 +587,15 @@ class NUCLEO_F411RE(Target): self.supported_form_factors = ["ARDUINO", "MORPHO"] self.detect_code = ["0740"] +class NUCLEO_F446RE(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['STM', 'STM32F4', 'STM32F446RE'] + self.supported_toolchains = ["GCC_ARM"] + self.default_toolchain = "uARM" + self.supported_form_factors = ["ARDUINO", "MORPHO"] + class NUCLEO_L053R8(Target): def __init__(self): Target.__init__(self) @@ -1265,6 +1274,7 @@ TARGETS = [ NUCLEO_F334R8(), NUCLEO_F401RE(), NUCLEO_F411RE(), + NUCLEO_F446RE(), NUCLEO_L053R8(), NUCLEO_L073RZ(), NUCLEO_L152RE(), From 455b417b8f3d9fd1c09eefaffec416a286de3ce0 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Sun, 26 Apr 2015 21:04:49 +0200 Subject: [PATCH 040/139] [NUCLEO_F446RE] create new target - part 2 Update system_stm32f4xx to new version, generated by STM32CubeMX Add target name to digital_loop test Update coide export template --- .../TARGET_NUCLEO_F446RE/hal_tick.c | 2 +- .../TARGET_NUCLEO_F446RE/system_stm32f4xx.c | 88 ++++++++++--------- .../tests/mbed/digitalin_digitalout/main.cpp | 1 + libraries/tests/mbed/digitalinout/main.cpp | 1 + .../export/coide_nucleo_f446re.coproj.tmpl | 82 ++++++++++++++++- 5 files changed, 130 insertions(+), 44 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/hal_tick.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/hal_tick.c index bd400d4379..9f28a210c3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/hal_tick.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/hal_tick.c @@ -77,7 +77,7 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { // Configure time base TimMasterHandle.Instance = TIM_MST; TimMasterHandle.Init.Period = 0xFFFFFFFF; - TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick + TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 2 / 1000000) - 1; // 1 µs tick TimMasterHandle.Init.ClockDivision = 0; TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; TimMasterHandle.Init.RepetitionCounter = 0; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.c index d09a7dc7fc..ee83a3efcf 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f4xx.c * @author MCD Application Team - * @version V2.1.0 - * @date 19-June-2014 + * @version V2.3.0 + * @date 02-March-2015 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * * This file provides two functions and one global variable to be called from @@ -27,20 +27,20 @@ * | 2- PLL_HSE_XTAL | * | (external 8 MHz xtal) | *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 96 | 96 + * SYSCLK(MHz) | 180 | 16 *----------------------------------------------------------------------------- - * AHBCLK (MHz) | 96 | 96 + * AHBCLK (MHz) | 180 | 16 *----------------------------------------------------------------------------- - * APB1CLK (MHz) | 48 | 48 + * APB1CLK (MHz) | 45 | 4 *----------------------------------------------------------------------------- - * APB2CLK (MHz) | 96 | 96 + * APB2CLK (MHz) | 90 | 8 *----------------------------------------------------------------------------- - * USB capable (48 MHz precise clock) | YES | YES + * USB capable (48 MHz precise clock) | YES | NO *----------------------------------------------------------------------------- ****************************************************************************** * @attention * - *

© COPYRIGHT 2014 STMicroelectronics

+ *

© COPYRIGHT 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -108,15 +108,17 @@ */ /************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted - on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) /* #define DATA_IN_ExtSRAM */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F446xx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) /* #define DATA_IN_ExtSDRAM */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " @@ -139,7 +141,7 @@ /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ #define USE_PLL_HSE_EXTC (1) /* Use external clock */ -#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ +#define USE_PLL_HSE_XTAL (0) /* Use external xtal */ /** * @} @@ -156,8 +158,8 @@ is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ -uint32_t SystemCoreClock = 16000000; -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + uint32_t SystemCoreClock = 18000000; + __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} @@ -229,7 +231,7 @@ void SystemInit(void) #endif /* Configure the Cube driver */ - SystemCoreClock = 16000000; // At this stage the HSI is used as system clock + SystemCoreClock = 18000000; // At this stage the HSI is used as system clock HAL_Init(); /* Configure the System clock source, PLL Multiplier and Divider factors, @@ -336,7 +338,7 @@ void SystemCoreClockUpdate(void) */ void SystemInit_ExtMemCtl(void) { -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) #if defined (DATA_IN_ExtSDRAM) register uint32_t tmpreg = 0, timeout = 0xFFFF; register uint32_t index; @@ -422,7 +424,7 @@ void SystemInit_ExtMemCtl(void) RCC->AHB3ENR |= 0x00000001; /* Configure and enable SDRAM bank1 */ - FMC_Bank5_6->SDCR[0] = 0x000019E0; + FMC_Bank5_6->SDCR[0] = 0x000019E4; FMC_Bank5_6->SDTR[0] = 0x01115351; /* SDRAM initialization sequence */ @@ -469,9 +471,12 @@ void SystemInit_ExtMemCtl(void) tmpreg = FMC_Bank5_6->SDCR[0]; FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); #endif /* DATA_IN_ExtSDRAM */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) #if defined(DATA_IN_ExtSRAM) /*-- GPIOs Configuration -----------------------------------------------------*/ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ @@ -529,12 +534,12 @@ void SystemInit_ExtMemCtl(void) /* Enable the FMC/FSMC interface clock */ RCC->AHB3ENR |= 0x00000001; -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F446xx) /* Configure and enable Bank1_SRAM2 */ FMC_Bank1->BTCR[2] = 0x00001011; FMC_Bank1->BTCR[3] = 0x00000201; FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx */ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) /* Configure and enable Bank1_SRAM2 */ @@ -544,7 +549,7 @@ void SystemInit_ExtMemCtl(void) #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ #endif /* DATA_IN_ExtSRAM */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ } #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ @@ -596,7 +601,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) clocked below the maximum system frequency, to update the voltage scaling value regarding system frequency refer to product datasheet. */ __PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); /* Enable HSE oscillator and activate PLL with HSE as source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; @@ -608,26 +613,27 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) { RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ } - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) - //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384) - RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4) - RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192) - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4) - RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 360; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + RCC_OscInitStruct.PLL.PLLR = 4; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } - + + HAL_PWREx_ActivateOverDrive(); + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { return 0; // FAIL } diff --git a/libraries/tests/mbed/digitalin_digitalout/main.cpp b/libraries/tests/mbed/digitalin_digitalout/main.cpp index 08fc12b784..68cca82a98 100644 --- a/libraries/tests/mbed/digitalin_digitalout/main.cpp +++ b/libraries/tests/mbed/digitalin_digitalout/main.cpp @@ -20,6 +20,7 @@ DigitalIn in(D2); defined(TARGET_NUCLEO_F334R8) || \ defined(TARGET_NUCLEO_F401RE) || \ defined(TARGET_NUCLEO_F411RE) || \ + defined(TARGET_NUCLEO_F446RE) || \ defined(TARGET_NUCLEO_L053R8) || \ defined(TARGET_NUCLEO_L073RZ) || \ defined(TARGET_NUCLEO_L152RE) diff --git a/libraries/tests/mbed/digitalinout/main.cpp b/libraries/tests/mbed/digitalinout/main.cpp index 9335651769..5efaa5cbef 100644 --- a/libraries/tests/mbed/digitalinout/main.cpp +++ b/libraries/tests/mbed/digitalinout/main.cpp @@ -20,6 +20,7 @@ DigitalInOut d2(D7); defined(TARGET_NUCLEO_F334R8) || \ defined(TARGET_NUCLEO_F401RE) || \ defined(TARGET_NUCLEO_F411RE) || \ + defined(TARGET_NUCLEO_F446RE) || \ defined(TARGET_NUCLEO_L053R8) || \ defined(TARGET_NUCLEO_L073RZ) || \ defined(TARGET_NUCLEO_L152RE) diff --git a/workspace_tools/export/coide_nucleo_f446re.coproj.tmpl b/workspace_tools/export/coide_nucleo_f446re.coproj.tmpl index 8b4bdf5568..91bbd30446 100644 --- a/workspace_tools/export/coide_nucleo_f446re.coproj.tmpl +++ b/workspace_tools/export/coide_nucleo_f446re.coproj.tmpl @@ -1,6 +1,84 @@ - + + + + + + + + + + + + @@ -24,7 +102,7 @@