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F2 CUBE V1.6.0 

This PR updates STM32 Cube SDK to
- HAL V1.2.1
- LL V1.2.1
- CMSIS 2.2.0
pull/4402/head
Laurent MEUNIER 2017-05-24 10:36:21 +02:00
parent 3122abee84
commit 5b510a35a6
138 changed files with 65439 additions and 12307 deletions
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17812
targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/stm32f207xx.h
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12
targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/stm32f2xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx.h
* @author MCD Application Team
* @version V2.1.2
* @date 29-June-2016
* @version V2.2.0
* @date 17-March-2017
* @brief CMSIS STM32F2xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -99,11 +99,11 @@ extern "C" {
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.1.2
* @brief CMSIS Device version number V2.2.0
*/
#define __STM32F2xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F2xx_CMSIS_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
#define __STM32F2xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32F2xx_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
#define __STM32F2xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F2xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F2xx_CMSIS_VERSION ((__STM32F2xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F2xx_CMSIS_VERSION_SUB1 << 16)\

261
targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/system_stm32f2xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f2xx.c
* @author MCD Application Team
* @version V2.1.2
* @date 29-June-2016
* @version V2.2.0
* @date 17-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -39,7 +39,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -127,18 +127,18 @@
/** @addtogroup STM32F2xx_System_Private_Variables
* @{
*/
/* This variable can be updated in Three ways :
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 120000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/* This variable can be updated in Three ways :
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -148,7 +148,7 @@ const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8,
*/
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
@ -166,41 +166,41 @@ uint8_t SetSysClock_PLL_HSI(void);
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
/* Configure the Vector Table location add offset address ------------------*/
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
@ -224,24 +224,83 @@ void SystemInit(void)
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (its value
* depends on the application requirements), user has to ensure that HSE_VALUE
* is same as the real frequency of the crystal used. Otherwise, this function
* may have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
SystemCoreClock = HAL_RCC_GetSysClockFreq();
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
#ifdef DATA_IN_ExtSRAM
@ -255,71 +314,71 @@ void SystemCoreClockUpdate(void)
*/
void SystemInit_ExtMemCtl(void)
{
__IO uint32_t tmp = 0x00;
__IO uint32_t tmp = 0x00;
/*-- GPIOs Configuration -----------------------------------------------------*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR |= 0x00000078;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
(void)(tmp);
/*-- GPIOs Configuration -----------------------------------------------------*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR |= 0x00000078;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
(void)(tmp);
/* Connect PDx pins to FSMC Alternate function */
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PDx pins to FSMC Alternate function */
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FSMC Alternate function */
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PEx pins to FSMC Alternate function */
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FSMC Alternate function */
GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCC0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA000AAA;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xFF000FFF;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PFx pins to FSMC Alternate function */
GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCC0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA000AAA;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xFF000FFF;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FSMC Alternate function */
GPIOG->AFR[0] = 0x00CCCCCC;
GPIOG->AFR[1] = 0x000000C0;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00085AAA;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000CAFFF;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/* Connect PGx pins to FSMC Alternate function */
GPIOG->AFR[0] = 0x00CCCCCC;
GPIOG->AFR[1] = 0x000000C0;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00085AAA;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000CAFFF;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/*--FSMC Configuration -------------------------------------------------------*/
/* Enable the FSMC interface clock */
RCC->AHB3ENR |= 0x00000001;
/*--FSMC Configuration -------------------------------------------------------*/
/* Enable the FSMC interface clock */
RCC->AHB3ENR |= 0x00000001;
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001011;
FSMC_Bank1->BTCR[3] = 0x00000201;
FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001011;
FSMC_Bank1->BTCR[3] = 0x00000201;
FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
}
#endif /* DATA_IN_ExtSRAM */

8
targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/system_stm32f2xx.h
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@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f2xx.h
* @author MCD Application Team
* @version V2.1.2
* @date 29-June-2016
* @version V2.2.0
* @date 17-March-2017
* @brief CMSIS Cortex-M3 Device System Source File for STM32F2xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -75,6 +75,8 @@ extern "C" {
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

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targets/TARGET_STM/TARGET_STM32F2/device/Release_Notes_stm32f2xx_hal.html
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240
targets/TARGET_STM/TARGET_STM32F2/device/stm32_hal_legacy.h
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@ -2,14 +2,14 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
* @version $VERSION$
* @date $DATE$
* @version V1.2.1
* @date 14-April-2017
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -241,9 +241,9 @@
#define DAC1_CHANNEL_1 DAC_CHANNEL_1
#define DAC1_CHANNEL_2 DAC_CHANNEL_2
#define DAC2_CHANNEL_1 DAC_CHANNEL_1
#define DAC_WAVE_NONE ((uint32_t)0x00000000U)
#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
#define DAC_WAVE_NONE 0x00000000U
#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
@ -356,6 +356,7 @@
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
/**
* @}
*/
@ -381,7 +382,7 @@
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{
*/
#if defined(STM32L4) || defined(STM32F7)
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
@ -456,6 +457,25 @@
* @}
*/
/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
* @{
*/
#if defined(STM32H7)
#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
#endif /* STM32H7 */
/**
* @}
*/
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
* @{
*/
@ -895,9 +915,9 @@
#define CAN_IT_RQCP2 CAN_IT_TME
#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
#define CAN_TXSTATUS_OK ((uint8_t)0x01)
#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
/**
* @}
@ -916,48 +936,45 @@
#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
#define ETH_MMCCR ((uint32_t)0x00000100U)
#define ETH_MMCRIR ((uint32_t)0x00000104U)
#define ETH_MMCTIR ((uint32_t)0x00000108U)
#define ETH_MMCRIMR ((uint32_t)0x0000010CU)
#define ETH_MMCTIMR ((uint32_t)0x00000110U)
#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
#define ETH_MMCTGFCR ((uint32_t)0x00000168U)
#define ETH_MMCRFCECR ((uint32_t)0x00000194U)
#define ETH_MMCRFAECR ((uint32_t)0x00000198U)
#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
#define ETH_MMCCR 0x00000100U
#define ETH_MMCRIR 0x00000104U
#define ETH_MMCTIR 0x00000108U
#define ETH_MMCRIMR 0x0000010CU
#define ETH_MMCTIMR 0x00000110U
#define ETH_MMCTGFSCCR 0x0000014CU
#define ETH_MMCTGFMSCCR 0x00000150U
#define ETH_MMCTGFCR 0x00000168U
#define ETH_MMCRFCECR 0x00000194U
#define ETH_MMCRFAECR 0x00000198U
#define ETH_MMCRGUFCR 0x000001C4U
#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
#endif
#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
/**
* @}
@ -979,7 +996,7 @@
* @}
*/
#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
* @{
@ -1004,7 +1021,7 @@
/**
* @}
*/
#endif /* STM32L4xx || STM32F7*/
#endif /* STM32L4 || STM32F7*/
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{
@ -1189,6 +1206,9 @@
* @{
*/
#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
#define HAL_LTDC_Relaod HAL_LTDC_Reload
#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
/**
* @}
*/
@ -1230,6 +1250,7 @@
#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
@ -1624,7 +1645,11 @@
#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
#if defined(STM32F1)
#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
#else
#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
#endif /* STM32F1 */
#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
@ -2230,26 +2255,26 @@
#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
@ -2633,6 +2658,30 @@
#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
#endif
#if defined(STM32H7)
#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
#endif
#if defined(STM32F7)
#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
@ -2651,10 +2700,22 @@
#define RCC_IT_HSI14 RCC_IT_HSI14RDY
#if defined(STM32L0)
#define RCC_IT_LSECSS RCC_IT_CSSLSE
#define RCC_IT_CSS RCC_IT_CSSHSE
#endif
#define RCC_IT_CSSLSE RCC_IT_LSECSS
#define RCC_IT_CSSHSE RCC_IT_CSS
#define RCC_PLLMUL_3 RCC_PLL_MUL3
#define RCC_PLLMUL_4 RCC_PLL_MUL4
#define RCC_PLLMUL_6 RCC_PLL_MUL6
#define RCC_PLLMUL_8 RCC_PLL_MUL8
#define RCC_PLLMUL_12 RCC_PLL_MUL12
#define RCC_PLLMUL_16 RCC_PLL_MUL16
#define RCC_PLLMUL_24 RCC_PLL_MUL24
#define RCC_PLLMUL_32 RCC_PLL_MUL32
#define RCC_PLLMUL_48 RCC_PLL_MUL48
#define RCC_PLLDIV_2 RCC_PLL_DIV2
#define RCC_PLLDIV_3 RCC_PLL_DIV3
#define RCC_PLLDIV_4 RCC_PLL_DIV4
#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
@ -2771,10 +2832,22 @@
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
#define DfsdmClockSelection Dfsdm1ClockSelection
#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
/**
* @}
@ -2854,7 +2927,7 @@
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
#if defined(STM32F4)
#if defined(STM32F4) || defined(STM32F2)
#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
@ -2905,6 +2978,14 @@
#define SDIO_IRQn SDMMC1_IRQn
#define SDIO_IRQHandler SDMMC1_IRQHandler
#endif
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif
/**
* @}
*/
@ -3093,6 +3174,7 @@
* @{
*/
#define __HAL_LTDC_LAYER LTDC_LAYER
#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
/**
* @}
*/

45
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@ -23,7 +23,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -68,18 +68,18 @@
* @{
*/
/**
* @brief STM32F2xx HAL Driver version number V1.1.3
* @brief STM32F2xx HAL Driver version number V1.2.1
*/
#define __STM32F2xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F2xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
#define __STM32F2xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
#define __STM32F2xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F2xx_HAL_VERSION_MAIN 0x01U /*!< [31:24] main version */
#define __STM32F2xx_HAL_VERSION_SUB1 0x02U /*!< [23:16] sub1 version */
#define __STM32F2xx_HAL_VERSION_SUB2 0x01U /*!< [15:8] sub2 version */
#define __STM32F2xx_HAL_VERSION_RC 0x00U /*!< [7:0] release candidate */
#define __STM32F2xx_HAL_VERSION ((__STM32F2xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F2xx_HAL_VERSION_SUB1 << 16U)\
|(__STM32F2xx_HAL_VERSION_SUB2 << 8U) \
|(__STM32F2xx_HAL_VERSION_RC))
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFFU)
#define IDCODE_DEVID_MASK 0x00000FFFU
/* ------------ RCC registers bit address in the alias region ----------- */
#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
@ -325,7 +325,7 @@ __weak uint32_t HAL_GetTick(void)
}
/**
* @brief This function provides accurate delay (in milliseconds) based
* @brief This function provides minimum delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
@ -337,9 +337,16 @@ __weak uint32_t HAL_GetTick(void)
*/
__weak void HAL_Delay(__IO uint32_t Delay)
{
uint32_t tickstart = 0U;
tickstart = HAL_GetTick();
while((HAL_GetTick() - tickstart) < Delay)
uint32_t tickstart = HAL_GetTick();
uint32_t wait = Delay;
/* Add a period to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
{
wait++;
}
while((HAL_GetTick() - tickstart) < wait)
{
}
}
@ -479,6 +486,18 @@ void HAL_DisableCompensationCell(void)
*(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE;
}
/**
* @brief Return the unique device identifier (UID based on 96 bits)
* @param UID: pointer to 3 words array.
* @retval Device identifier
*/
void HAL_GetUID(uint32_t *UID)
{
UID[0] = (uint32_t)(READ_REG(*((uint32_t *)UID_BASE)));
UID[1] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
UID[2] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
}
/**
* @}
*/

7
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal.h
View File

@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f2xx_hal.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -174,6 +174,7 @@ void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void);
void HAL_EnableCompensationCell(void);
void HAL_DisableCompensationCell(void);
void HAL_GetUID(uint32_t *UID);
/**
* @}
*/

6
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_adc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_adc.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* + Initialization and de-initialization functions
@ -164,7 +164,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

92
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_adc.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_adc.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of ADC HAL extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -172,29 +172,29 @@ typedef struct
* @brief HAL ADC state machine: ADC states definition (bitfields)
*/
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /*!< TimeOut occurrence */
#define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */
/* States of ADC errors */
#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error occurrence */
#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */
/* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /*!< Overrun occurrence */
#define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Overrun occurrence */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /*!< Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
#define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */
/**
* @brief ADC handle Structure definition
@ -227,11 +227,11 @@ typedef struct
/** @defgroup ADC_Error_Code ADC Error Code
* @{
*/
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking,
#define HAL_ADC_ERROR_NONE 0x00U /*!< No error */
#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking,
enable/disable, erroneous state */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */
#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */
#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */
/**
* @}
*/
@ -240,7 +240,7 @@ typedef struct
/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
* @{
*/
#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U)
#define ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U
#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
@ -251,7 +251,7 @@ typedef struct
/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
* @{
*/
#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U)
#define ADC_TWOSAMPLINGDELAY_5CYCLES 0x00000000U
#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
@ -274,7 +274,7 @@ typedef struct
/** @defgroup ADC_Resolution ADC Resolution
* @{
*/
#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U)
#define ADC_RESOLUTION_12B 0x00000000U
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
@ -285,7 +285,7 @@ typedef struct
/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
* @{
*/
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
@ -298,7 +298,7 @@ typedef struct
*/
/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
/* compatibility with other STM32 devices. */
#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGCONV_T1_CC1 0x00000000U
#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
@ -322,7 +322,7 @@ typedef struct
/** @defgroup ADC_Data_align ADC Data Align
* @{
*/
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
#define ADC_DATAALIGN_RIGHT 0x00000000U
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
/**
* @}
@ -331,7 +331,7 @@ typedef struct
/** @defgroup ADC_channels ADC Common Channels
* @{
*/
#define ADC_CHANNEL_0 ((uint32_t)0x00000000U)
#define ADC_CHANNEL_0 0x00000000U
#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
@ -360,7 +360,7 @@ typedef struct
/** @defgroup ADC_sampling_times ADC Sampling Times
* @{
*/
#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U)
#define ADC_SAMPLETIME_3CYCLES 0x00000000U
#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
@ -375,9 +375,9 @@ typedef struct
/** @defgroup ADC_EOCSelection ADC EOC Selection
* @{
*/
#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U)
#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U)
#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U) /*!< reserved for future use */
#define ADC_EOC_SEQ_CONV 0x00000000U
#define ADC_EOC_SINGLE_CONV 0x00000001U
#define ADC_EOC_SINGLE_SEQ_CONV 0x00000002U /*!< reserved for future use */
/**
* @}
*/
@ -400,7 +400,7 @@ typedef struct
#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U)
#define ADC_ANALOGWATCHDOG_NONE 0x00000000U
/**
* @}
*/
@ -432,9 +432,9 @@ typedef struct
/** @defgroup ADC_channels_type ADC Channels Type
* @{
*/
#define ADC_ALL_CHANNELS ((uint32_t)0x00000001U)
#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U) /*!< reserved for future use */
#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */
#define ADC_ALL_CHANNELS 0x00000001U
#define ADC_REGULAR_CHANNELS 0x00000002U /*!< reserved for future use */
#define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */
/**
* @}
*/
@ -591,11 +591,11 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/* Delay for ADC stabilization time. */
/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
/* Unit: us */
#define ADC_STAB_DELAY_US ((uint32_t) 3U)
#define ADC_STAB_DELAY_US 3U
/* Delay for temperature sensor stabilization time. */
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
/* Unit: us */
#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U)
#define ADC_TEMPSENSOR_DELAY_US 10U
/**
* @}
*/
@ -723,23 +723,23 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFFU))
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU)
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)16U)))
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)16U)))
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1U)) && ((NUMBER) <= ((uint32_t)8U)))
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= ((uint32_t)16)))
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= ((uint32_t)16)))
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFFU))) || \
(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FFU))) || \
(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FFU))) || \
(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003FU))))
((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \
(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \
(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= 0x00FFU)) || \
(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= 0x003FU)))
/**
* @brief Set ADC Regular channel sequence length.
* @param _NbrOfConversion_: Regular channel sequence length.
* @retval None
*/
#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U)
#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20U)
/**
* @brief Set the ADC's sample time for channel numbers between 10 and 18.

12
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_adc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_adc_ex.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the ADC extension peripheral:
* + Extended features functions
@ -86,7 +86,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -319,7 +319,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
/* Enable end of conversion interrupt for injected channels */
__HAL_ADC_ENABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_OVR));
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
@ -508,7 +508,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Disable ADC end of conversion interrupt for injected channels */
__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_OVR));
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
@ -756,6 +756,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
*/
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* Return the multi mode conversion value */
return ADC->CDR;
}

24
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_adc_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_adc_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of ADC HAL extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -152,7 +152,7 @@ typedef struct
/** @defgroup ADCEx_Common_mode ADC Common Mode
* @{
*/
#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000U)
#define ADC_MODE_INDEPENDENT 0x00000000U
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)
#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
@ -172,7 +172,7 @@ typedef struct
/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
* @{
*/
#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000U) /*!< DMA mode disabled */
#define ADC_DMAACCESSMODE_DISABLED 0x00000000U /*!< DMA mode disabled */
#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
@ -183,7 +183,7 @@ typedef struct
/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
* @{
*/
#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE 0x00000000U
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
@ -194,7 +194,7 @@ typedef struct
/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
* @{
*/
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 0x00000000U
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0)
#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1)
#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
@ -218,10 +218,10 @@ typedef struct
/** @defgroup ADCEx_injected_rank ADC Injected Rank
* @{
*/
#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001U)
#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002U)
#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003U)
#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004U)
#define ADC_INJECTED_RANK_1 0x00000001U
#define ADC_INJECTED_RANK_2 0x00000002U
#define ADC_INJECTED_RANK_3 0x00000003U
#define ADC_INJECTED_RANK_4 0x00000004U
/**
* @}
*/
@ -342,7 +342,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
* @brief Set the selected injected Channel rank.
* @param _CHANNELNB_: Channel number.
* @param _RANKNB_: Rank number.
* @param _JSQR_JL_: Sequence length.
* @param _JSQR_JL_: Sequence length.
* @retval None
*/
#define ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_))))

663
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_can.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_can.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
* + Initialization and de-initialization functions
@ -72,7 +72,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -163,7 +163,7 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
*/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
{
uint32_t InitStatus = 3U;
uint32_t InitStatus = CAN_INITSTATUS_FAILED;
uint32_t tickstart = 0U;
/* Check CAN handle */
@ -188,7 +188,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
if(hcan->State == HAL_CAN_STATE_RESET)
{
{
/* Allocate lock resource and initialize it */
hcan->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
@ -220,11 +220,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
}
/* Check acknowledge */
if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
{
InitStatus = CAN_INITSTATUS_FAILED;
}
else
if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
{
/* Set the time triggered communication mode */
if (hcan->Init.TTCM == ENABLE)
@ -312,11 +308,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
}
/* Check acknowledged */
if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
{
InitStatus = CAN_INITSTATUS_FAILED;
}
else
if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
{
InitStatus = CAN_INITSTATUS_SUCCESS;
}
@ -355,7 +347,10 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
{
uint32_t filternbrbitpos = 0U;
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* Check the parameters */
assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
@ -364,7 +359,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy
assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
filternbrbitpos = ((uint32_t)1U) << sFilterConfig->FilterNumber;
filternbrbitpos = 1U << sFilterConfig->FilterNumber;
/* Initialisation mode for the filter */
CAN1->FMR |= (uint32_t)CAN_FMR_FINIT;
@ -540,7 +535,7 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
*/
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
{
uint32_t transmitmailbox = 5U;
uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
uint32_t tickstart = 0U;
/* Check the parameters */
@ -555,29 +550,35 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
/* Process locked */
__HAL_LOCK(hcan);
if(hcan->State == HAL_CAN_STATE_BUSY_RX)
/* Change CAN state */
switch(hcan->State)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX;
case(HAL_CAN_STATE_BUSY_RX0):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
break;
case(HAL_CAN_STATE_BUSY_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
break;
case(HAL_CAN_STATE_BUSY_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
break;
default: /* HAL_CAN_STATE_READY */
hcan->State = HAL_CAN_STATE_BUSY_TX;
break;
}
/* Select one empty transmit mailbox */
if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
{
transmitmailbox = 0U;
transmitmailbox = CAN_TXMAILBOX_0;
}
else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
{
transmitmailbox = 1U;
transmitmailbox = CAN_TXMAILBOX_1;
}
else
{
transmitmailbox = 2U;
transmitmailbox = CAN_TXMAILBOX_2;
}
/* Set up the Id */
@ -597,8 +598,8 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
}
/* Set up the DLC */
hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
/* Set up the data field */
@ -625,21 +626,29 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
hcan->State = HAL_CAN_STATE_TIMEOUT;
__HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
/* Process unlocked */
__HAL_UNLOCK(hcan);
return HAL_TIMEOUT;
}
}
}
if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
/* Change CAN state */
switch(hcan->State)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_RX;
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_READY;
case(HAL_CAN_STATE_BUSY_TX_RX0):
hcan->State = HAL_CAN_STATE_BUSY_RX0;
break;
case(HAL_CAN_STATE_BUSY_TX_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX1;
break;
case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
break;
default: /* HAL_CAN_STATE_BUSY_TX */
hcan->State = HAL_CAN_STATE_READY;
break;
}
/* Process unlocked */
@ -666,8 +675,8 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
*/
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
{
uint32_t transmitmailbox = 5U;
uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
/* Check the parameters */
assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
@ -679,19 +688,19 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
{
/* Process Locked */
__HAL_LOCK(hcan);
/* Select one empty transmit mailbox */
if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
{
transmitmailbox = 0U;
transmitmailbox = CAN_TXMAILBOX_0;
}
else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
{
transmitmailbox = 1U;
transmitmailbox = CAN_TXMAILBOX_1;
}
else
{
transmitmailbox = 2U;
transmitmailbox = CAN_TXMAILBOX_2;
}
/* Set up the Id */
@ -711,8 +720,8 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
}
/* Set up the DLC */
hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
/* Set up the data field */
@ -724,16 +733,21 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
((uint32_t)hcan->pTxMsg->Data[4U]));
if(hcan->State == HAL_CAN_STATE_BUSY_RX)
/* Change CAN state */
switch(hcan->State)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX;
case(HAL_CAN_STATE_BUSY_RX0):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
break;
case(HAL_CAN_STATE_BUSY_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
break;
case(HAL_CAN_STATE_BUSY_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
break;
default: /* HAL_CAN_STATE_READY */
hcan->State = HAL_CAN_STATE_BUSY_TX;
break;
}
/* Set CAN error code to none */
@ -741,27 +755,18 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
/* Process Unlocked */
__HAL_UNLOCK(hcan);
/* Enable Error warning Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
/* Enable Error passive Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
/* Enable Bus-off Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
/* Enable Last error code Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
/* Enable Error Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
/* Enable Transmit mailbox empty Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME);
/* Request transmission */
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
/* Enable Error warning, Error passive, Bus-off,
Last error and Error Interrupts */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
CAN_IT_EPV |
CAN_IT_BOF |
CAN_IT_LEC |
CAN_IT_ERR |
CAN_IT_TME);
}
else
{
@ -786,22 +791,68 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
{
uint32_t tickstart = 0U;
CanRxMsgTypeDef* pRxMsg = NULL;
/* Check the parameters */
assert_param(IS_CAN_FIFO(FIFONumber));
/* Check if CAN state is not busy for RX FIFO0 */
if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
(hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
{
return HAL_BUSY;
}
/* Check if CAN state is not busy for RX FIFO1 */
if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
(hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
{
return HAL_BUSY;
}
/* Process locked */
__HAL_LOCK(hcan);
if(hcan->State == HAL_CAN_STATE_BUSY_TX)
/* Change CAN state */
if (FIFONumber == CAN_FIFO0)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
switch(hcan->State)
{
case(HAL_CAN_STATE_BUSY_TX):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
break;
case(HAL_CAN_STATE_BUSY_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
break;
case(HAL_CAN_STATE_BUSY_TX_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
break;
default: /* HAL_CAN_STATE_READY */
hcan->State = HAL_CAN_STATE_BUSY_RX0;
break;
}
}
else
else /* FIFONumber == CAN_FIFO1 */
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_RX;
switch(hcan->State)
{
case(HAL_CAN_STATE_BUSY_TX):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
break;
case(HAL_CAN_STATE_BUSY_RX0):
hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
break;
case(HAL_CAN_STATE_BUSY_TX_RX0):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
break;
default: /* HAL_CAN_STATE_READY */
hcan->State = HAL_CAN_STATE_BUSY_RX1;
break;
}
}
/* Get tick */
@ -822,32 +873,44 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u
}
}
}
/* Set RxMsg pointer */
if(FIFONumber == CAN_FIFO0)
{
pRxMsg = hcan->pRxMsg;
}
else /* FIFONumber == CAN_FIFO1 */
{
pRxMsg = hcan->pRx1Msg;
}
/* Get the Id */
hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
if (hcan->pRxMsg->IDE == CAN_ID_STD)
{
hcan->pRxMsg->StdId = (uint32_t)0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
}
else
{
hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
}
hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
/* Get the DLC */
hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
/* Get the FMI */
hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
/* Get the FIFONumber */
pRxMsg->FIFONumber = FIFONumber;
/* Get the data field */
hcan->pRxMsg->Data[0U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
hcan->pRxMsg->Data[1U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
hcan->pRxMsg->Data[2U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
hcan->pRxMsg->Data[3U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
hcan->pRxMsg->Data[4U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
hcan->pRxMsg->Data[5U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
hcan->pRxMsg->Data[6U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
hcan->pRxMsg->Data[7U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
/* Release the FIFO */
if(FIFONumber == CAN_FIFO0)
@ -861,23 +924,47 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u
__HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
}
if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
/* Change CAN state */
if (FIFONumber == CAN_FIFO0)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX;
/* Process unlocked */
__HAL_UNLOCK(hcan);
switch(hcan->State)
{
case(HAL_CAN_STATE_BUSY_TX_RX0):
hcan->State = HAL_CAN_STATE_BUSY_TX;
break;
case(HAL_CAN_STATE_BUSY_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX1;
break;
case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
break;
default: /* HAL_CAN_STATE_BUSY_RX0 */
hcan->State = HAL_CAN_STATE_READY;
break;
}
}
else
else /* FIFONumber == CAN_FIFO1 */
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcan);
switch(hcan->State)
{
case(HAL_CAN_STATE_BUSY_TX_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX;
break;
case(HAL_CAN_STATE_BUSY_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX0;
break;
case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
break;
default: /* HAL_CAN_STATE_BUSY_RX1 */
hcan->State = HAL_CAN_STATE_READY;
break;
}
}
/* Process unlocked */
__HAL_UNLOCK(hcan);
/* Return function status */
return HAL_OK;
}
@ -891,64 +978,93 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u
*/
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
{
uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_CAN_FIFO(FIFONumber));
tmp = hcan->State;
if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_TX))
/* Check if CAN state is not busy for RX FIFO0 */
if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
(hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
{
/* Process locked */
__HAL_LOCK(hcan);
if(hcan->State == HAL_CAN_STATE_BUSY_TX)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_RX;
}
/* Set CAN error code to none */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
/* Enable Error warning Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
/* Enable Error passive Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
/* Enable Bus-off Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
/* Enable Last error code Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
/* Enable Error Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
return HAL_BUSY;
}
/* Process unlocked */
__HAL_UNLOCK(hcan);
/* Check if CAN state is not busy for RX FIFO1 */
if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
(hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
{
return HAL_BUSY;
}
if(FIFONumber == CAN_FIFO0)
/* Process locked */
__HAL_LOCK(hcan);
/* Change CAN state */
if(FIFONumber == CAN_FIFO0)
{
switch(hcan->State)
{
/* Enable FIFO 0 message pending Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
case(HAL_CAN_STATE_BUSY_TX):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
break;
case(HAL_CAN_STATE_BUSY_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
break;
case(HAL_CAN_STATE_BUSY_TX_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
break;
default: /* HAL_CAN_STATE_READY */
hcan->State = HAL_CAN_STATE_BUSY_RX0;
break;
}
else
}
else /* FIFONumber == CAN_FIFO1 */
{
switch(hcan->State)
{
/* Enable FIFO 1 message pending Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
case(HAL_CAN_STATE_BUSY_TX):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
break;
case(HAL_CAN_STATE_BUSY_RX0):
hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
break;
case(HAL_CAN_STATE_BUSY_TX_RX0):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
break;
default: /* HAL_CAN_STATE_READY */
hcan->State = HAL_CAN_STATE_BUSY_RX1;
break;
}
}
/* Set CAN error code to none */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
/* Enable interrupts: */
/* - Enable Error warning Interrupt */
/* - Enable Error passive Interrupt */
/* - Enable Bus-off Interrupt */
/* - Enable Last error code Interrupt */
/* - Enable Error Interrupt */
/* - Enable Transmit mailbox empty Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
CAN_IT_EPV |
CAN_IT_BOF |
CAN_IT_LEC |
CAN_IT_ERR |
CAN_IT_TME);
/* Process unlocked */
__HAL_UNLOCK(hcan);
if(FIFONumber == CAN_FIFO0)
{
/* Enable FIFO 0 overrun and message pending Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
}
else
{
return HAL_BUSY;
/* Enable FIFO 1 overrun and message pending Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
}
/* Return function status */
@ -1071,6 +1187,31 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
{
uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
uint32_t errorcode = HAL_CAN_ERROR_NONE;
/* Check Overrun flag for FIFO0 */
tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0);
tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0);
if(tmp1 && tmp2)
{
/* Set CAN error code to FOV0 error */
errorcode |= HAL_CAN_ERROR_FOV0;
/* Clear FIFO0 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
}
/* Check Overrun flag for FIFO1 */
tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1);
tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1);
if(tmp1 && tmp2)
{
/* Set CAN error code to FOV1 error */
errorcode |= HAL_CAN_ERROR_FOV1;
/* Clear FIFO1 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
}
/* Check End of transmission flag */
if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
@ -1080,8 +1221,24 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
if(tmp1 || tmp2 || tmp3)
{
/* Call transmit function */
CAN_Transmit_IT(hcan);
tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0);
tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1);
tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2);
/* Check Transmit success */
if(tmp1 || tmp2 || tmp3)
{
/* Call transmit function */
CAN_Transmit_IT(hcan);
}
else /* Transmit failure */
{
/* Set CAN error code to TXFAIL error */
errorcode |= HAL_CAN_ERROR_TXFAIL;
}
/* Clear transmission status flags (RQCPx and TXOKx) */
SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
}
}
@ -1113,6 +1270,9 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
}
/* Set error code in handle */
hcan->ErrorCode |= errorcode;
tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
@ -1181,6 +1341,29 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
hcan->Instance->MSR = CAN_MSR_ERRI;
/* Set the CAN state ready to be able to start again the process */
hcan->State = HAL_CAN_STATE_READY;
/* Disable interrupts: */
/* - Disable Error warning Interrupt */
/* - Disable Error passive Interrupt */
/* - Disable Bus-off Interrupt */
/* - Disable Last error code Interrupt */
/* - Disable Error Interrupt */
/* - Disable FIFO 0 message pending Interrupt */
/* - Disable FIFO 0 Overrun Interrupt */
/* - Disable FIFO 1 message pending Interrupt */
/* - Disable FIFO 1 Overrun Interrupt */
/* - Disable Transmit mailbox empty Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
CAN_IT_EPV |
CAN_IT_BOF |
CAN_IT_LEC |
CAN_IT_ERR |
CAN_IT_FMP0|
CAN_IT_FOV0|
CAN_IT_FMP1|
CAN_IT_FOV1|
CAN_IT_TME);
/* Call Error callback function */
HAL_CAN_ErrorCallback(hcan);
}
@ -1290,33 +1473,31 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
if(hcan->State == HAL_CAN_STATE_BUSY_TX)
{
/* Disable Error warning Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
/* Disable Error passive Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
/* Disable Bus-off Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
/* Disable Last error code Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
/* Disable Error Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
/* Disable Error warning, Error passive, Bus-off, Last error code
and Error Interrupts */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
CAN_IT_EPV |
CAN_IT_BOF |
CAN_IT_LEC |
CAN_IT_ERR );
}
if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
/* Change CAN state */
switch(hcan->State)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_RX;
case(HAL_CAN_STATE_BUSY_TX_RX0):
hcan->State = HAL_CAN_STATE_BUSY_RX0;
break;
case(HAL_CAN_STATE_BUSY_TX_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX1;
break;
case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
break;
default: /* HAL_CAN_STATE_BUSY_TX */
hcan->State = HAL_CAN_STATE_READY;
break;
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_READY;
}
/* Transmission complete callback */
HAL_CAN_TxCpltCallback(hcan);
@ -1333,76 +1514,112 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
*/
static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
{
/* Get the Id */
hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
if (hcan->pRxMsg->IDE == CAN_ID_STD)
uint32_t tmp1 = 0U;
CanRxMsgTypeDef* pRxMsg = NULL;
/* Set RxMsg pointer */
if(FIFONumber == CAN_FIFO0)
{
hcan->pRxMsg->StdId = (uint32_t)0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
pRxMsg = hcan->pRxMsg;
}
else /* FIFONumber == CAN_FIFO1 */
{
pRxMsg = hcan->pRx1Msg;
}
/* Get the Id */
pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
if (pRxMsg->IDE == CAN_ID_STD)
{
pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
}
else
{
hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
}
hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
/* Get the DLC */
hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
/* Get the FIFONumber */
pRxMsg->FIFONumber = FIFONumber;
/* Get the FMI */
hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
/* Get the data field */
hcan->pRxMsg->Data[0U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
hcan->pRxMsg->Data[1U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
hcan->pRxMsg->Data[2U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
hcan->pRxMsg->Data[3U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
hcan->pRxMsg->Data[4U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
hcan->pRxMsg->Data[5U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
hcan->pRxMsg->Data[6U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
hcan->pRxMsg->Data[7U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
/* Release the FIFO */
/* Release FIFO0 */
if (FIFONumber == CAN_FIFO0)
{
__HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
/* Disable FIFO 0 message pending Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
/* Disable FIFO 0 overrun and message pending Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
}
/* Release FIFO1 */
else /* FIFONumber == CAN_FIFO1 */
{
__HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
/* Disable FIFO 1 message pending Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
/* Disable FIFO 1 overrun and message pending Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
}
if(hcan->State == HAL_CAN_STATE_BUSY_RX)
tmp1 = hcan->State;
if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1))
{
/* Disable Error warning Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
/* Disable Error passive Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
/* Disable Bus-off Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
/* Disable Last error code Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
/* Disable Error Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
/* Disable Error warning, Error passive, Bus-off, Last error code
and Error Interrupts */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
CAN_IT_EPV |
CAN_IT_BOF |
CAN_IT_LEC |
CAN_IT_ERR);
}
if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
/* Change CAN state */
if (FIFONumber == CAN_FIFO0)
{
/* Disable CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX;
switch(hcan->State)
{
case(HAL_CAN_STATE_BUSY_TX_RX0):
hcan->State = HAL_CAN_STATE_BUSY_TX;
break;
case(HAL_CAN_STATE_BUSY_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX1;
break;
case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
break;
default: /* HAL_CAN_STATE_BUSY_RX0 */
hcan->State = HAL_CAN_STATE_READY;
break;
}
}
else
else /* FIFONumber == CAN_FIFO1 */
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_READY;
switch(hcan->State)
{
case(HAL_CAN_STATE_BUSY_TX_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX;
break;
case(HAL_CAN_STATE_BUSY_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX0;
break;
case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
break;
default: /* HAL_CAN_STATE_BUSY_RX1 */
hcan->State = HAL_CAN_STATE_READY;
break;
}
}
/* Receive complete callback */

169
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_can.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_can.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -68,9 +68,13 @@ typedef enum
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX = 0x22U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX = 0x32U, /*!< CAN process is ongoing */
HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
}HAL_CAN_StateTypeDef;
@ -226,7 +230,9 @@ typedef struct
CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */
CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
@ -249,16 +255,19 @@ typedef struct
/** @defgroup CAN_Error_Code CAN Error Code
* @{
*/
#define HAL_CAN_ERROR_NONE 0x00U /*!< No error */
#define HAL_CAN_ERROR_EWG 0x01U /*!< EWG error */
#define HAL_CAN_ERROR_EPV 0x02U /*!< EPV error */
#define HAL_CAN_ERROR_BOF 0x04U /*!< BOF error */
#define HAL_CAN_ERROR_STF 0x08U /*!< Stuff error */
#define HAL_CAN_ERROR_FOR 0x10U /*!< Form error */
#define HAL_CAN_ERROR_ACK 0x20U /*!< Acknowledgment error */
#define HAL_CAN_ERROR_BR 0x40U /*!< Bit recessive */
#define HAL_CAN_ERROR_BD 0x80U /*!< LEC dominant */
#define HAL_CAN_ERROR_CRC 0x100U /*!< LEC transfer error */
#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */
#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */
#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */
#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */
#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */
#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */
#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */
#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */
#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */
#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */
#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */
#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */
/**
* @}
*/
@ -266,8 +275,8 @@ typedef struct
/** @defgroup CAN_InitStatus CAN InitStatus
* @{
*/
#define CAN_INITSTATUS_FAILED ((uint8_t)0x00U) /*!< CAN initialization failed */
#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01U) /*!< CAN initialization OK */
#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */
#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */
/**
* @}
*/
@ -275,7 +284,7 @@ typedef struct
/** @defgroup CAN_operating_mode CAN Operating Mode
* @{
*/
#define CAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
@ -286,7 +295,7 @@ typedef struct
/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
* @{
*/
#define CAN_SJW_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
@ -297,7 +306,7 @@ typedef struct
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
* @{
*/
#define CAN_BS1_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
@ -320,7 +329,7 @@ typedef struct
/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
* @{
*/
#define CAN_BS2_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
@ -335,8 +344,8 @@ typedef struct
/** @defgroup CAN_filter_mode CAN Filter Mode
* @{
*/
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
/**
* @}
*/
@ -344,8 +353,8 @@ typedef struct
/** @defgroup CAN_filter_scale CAN Filter Scale
* @{
*/
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
/**
* @}
*/
@ -353,8 +362,8 @@ typedef struct
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
* @{
*/
#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */
#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
/**
* @}
*/
@ -362,8 +371,8 @@ typedef struct
/** @defgroup CAN_Identifier_Type CAN Identifier Type
* @{
*/
#define CAN_ID_STD ((uint32_t)0x00000000U) /*!< Standard Id */
#define CAN_ID_EXT ((uint32_t)0x00000004U) /*!< Extended Id */
#define CAN_ID_STD 0x00000000U /*!< Standard Id */
#define CAN_ID_EXT 0x00000004U /*!< Extended Id */
/**
* @}
*/
@ -371,8 +380,8 @@ typedef struct
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
* @{
*/
#define CAN_RTR_DATA ((uint32_t)0x00000000U) /*!< Data frame */
#define CAN_RTR_REMOTE ((uint32_t)0x00000002U) /*!< Remote frame */
#define CAN_RTR_DATA 0x00000000U /*!< Data frame */
#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */
/**
* @}
*/
@ -380,8 +389,8 @@ typedef struct
/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
* @{
*/
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
/**
* @}
*/
@ -395,37 +404,37 @@ typedef struct
CAN_GetFlagStatus() function. */
/* Transmit Flags */
#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500U) /*!< Request MailBox0 flag */
#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508U) /*!< Request MailBox1 flag */
#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510U) /*!< Request MailBox2 flag */
#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501U) /*!< Transmission OK MailBox0 flag */
#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509U) /*!< Transmission OK MailBox1 flag */
#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511U) /*!< Transmission OK MailBox2 flag */
#define CAN_FLAG_TME0 ((uint32_t)0x0000051AU) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME1 ((uint32_t)0x0000051BU) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME2 ((uint32_t)0x0000051CU) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_RQCP0 0x00000500U /*!< Request MailBox0 flag */
#define CAN_FLAG_RQCP1 0x00000508U /*!< Request MailBox1 flag */
#define CAN_FLAG_RQCP2 0x00000510U /*!< Request MailBox2 flag */
#define CAN_FLAG_TXOK0 0x00000501U /*!< Transmission OK MailBox0 flag */
#define CAN_FLAG_TXOK1 0x00000509U /*!< Transmission OK MailBox1 flag */
#define CAN_FLAG_TXOK2 0x00000511U /*!< Transmission OK MailBox2 flag */
#define CAN_FLAG_TME0 0x0000051AU /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME1 0x0000051BU /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME2 0x0000051CU /*!< Transmit mailbox 0 empty flag */
/* Receive Flags */
#define CAN_FLAG_FF0 ((uint32_t)0x00000203U) /*!< FIFO 0 Full flag */
#define CAN_FLAG_FOV0 ((uint32_t)0x00000204U) /*!< FIFO 0 Overrun flag */
#define CAN_FLAG_FF0 0x00000203U /*!< FIFO 0 Full flag */
#define CAN_FLAG_FOV0 0x00000204U /*!< FIFO 0 Overrun flag */
#define CAN_FLAG_FF1 ((uint32_t)0x00000403U) /*!< FIFO 1 Full flag */
#define CAN_FLAG_FOV1 ((uint32_t)0x00000404U) /*!< FIFO 1 Overrun flag */
#define CAN_FLAG_FF1 0x00000403U /*!< FIFO 1 Full flag */
#define CAN_FLAG_FOV1 0x00000404U /*!< FIFO 1 Overrun flag */
/* Operating Mode Flags */
#define CAN_FLAG_INAK ((uint32_t)0x00000100U) /*!< Initialization acknowledge flag */
#define CAN_FLAG_SLAK ((uint32_t)0x00000101U) /*!< Sleep acknowledge flag */
#define CAN_FLAG_ERRI ((uint32_t)0x00000102U) /*!< Error flag */
#define CAN_FLAG_WKU ((uint32_t)0x00000103U) /*!< Wake up flag */
#define CAN_FLAG_SLAKI ((uint32_t)0x00000104U) /*!< Sleep acknowledge flag */
#define CAN_FLAG_INAK 0x00000100U /*!< Initialization acknowledge flag */
#define CAN_FLAG_SLAK 0x00000101U /*!< Sleep acknowledge flag */
#define CAN_FLAG_ERRI 0x00000102U /*!< Error flag */
#define CAN_FLAG_WKU 0x00000103U /*!< Wake up flag */
#define CAN_FLAG_SLAKI 0x00000104U /*!< Sleep acknowledge flag */
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
In this case the SLAK bit can be polled.*/
/* Error Flags */
#define CAN_FLAG_EWG ((uint32_t)0x00000300U) /*!< Error warning flag */
#define CAN_FLAG_EPV ((uint32_t)0x00000301U) /*!< Error passive flag */
#define CAN_FLAG_BOF ((uint32_t)0x00000302U) /*!< Bus-Off flag */
#define CAN_FLAG_EWG 0x00000300U /*!< Error warning flag */
#define CAN_FLAG_EPV 0x00000301U /*!< Error passive flag */
#define CAN_FLAG_BOF 0x00000302U /*!< Bus-Off flag */
/**
* @}
*/
@ -433,26 +442,26 @@ typedef struct
/** @defgroup CAN_Interrupts CAN Interrupts
* @{
*/
#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
#define CAN_IT_TME CAN_IER_TMEIE /*!< Transmit mailbox empty interrupt */
/* Receive Interrupts */
#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
#define CAN_IT_FMP0 CAN_IER_FMPIE0 /*!< FIFO 0 message pending interrupt */
#define CAN_IT_FF0 CAN_IER_FFIE0 /*!< FIFO 0 full interrupt */
#define CAN_IT_FOV0 CAN_IER_FOVIE0 /*!< FIFO 0 overrun interrupt */
#define CAN_IT_FMP1 CAN_IER_FMPIE1 /*!< FIFO 1 message pending interrupt */
#define CAN_IT_FF1 CAN_IER_FFIE1 /*!< FIFO 1 full interrupt */
#define CAN_IT_FOV1 CAN_IER_FOVIE1 /*!< FIFO 1 overrun interrupt */
/* Operating Mode Interrupts */
#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
#define CAN_IT_WKU CAN_IER_WKUIE /*!< Wake-up interrupt */
#define CAN_IT_SLK CAN_IER_SLKIE /*!< Sleep acknowledge interrupt */
/* Error Interrupts */
#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
#define CAN_IT_EWG CAN_IER_EWGIE /*!< Error warning interrupt */
#define CAN_IT_EPV CAN_IER_EPVIE /*!< Error passive interrupt */
#define CAN_IT_BOF CAN_IER_BOFIE /*!< Bus-off interrupt */
#define CAN_IT_LEC CAN_IER_LECIE /*!< Last error code interrupt */
#define CAN_IT_ERR CAN_IER_ERRIE /*!< Error Interrupt */
/**
* @}
*/
@ -460,9 +469,9 @@ typedef struct
/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
* @{
*/
#define CAN_TXMAILBOX_0 ((uint8_t)0x00U)
#define CAN_TXMAILBOX_1 ((uint8_t)0x01U)
#define CAN_TXMAILBOX_2 ((uint8_t)0x02U)
#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
/**
* @}
*/
@ -505,7 +514,7 @@ typedef struct
* @retval The number of pending message.
*/
#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03U)))
((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U)))
/** @brief Check whether the specified CAN flag is set or not.
* @param __HANDLE__: CAN Handle
@ -701,8 +710,8 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
#define CAN_FLAG_MASK ((uint32_t)0x000000FFU)
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
#define CAN_FLAG_MASK 0x000000FFU
/**
* @}
*/
@ -729,10 +738,10 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
((FIFO) == CAN_FILTER_FIFO1))
#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FFU))
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFFU))
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08U))
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU)
#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
((IDTYPE) == CAN_ID_EXT))

169
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_conf.h
View File

@ -2,15 +2,15 @@
******************************************************************************
* @file stm32f2xx_hal_conf_template.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32f2xx_hal_conf.h.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -52,41 +52,41 @@
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_CAN_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
#define HAL_CRYP_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
#define HAL_DCMI_MODULE_ENABLED
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_CAN_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
#define HAL_CRYP_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
#define HAL_DCMI_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_ETH_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_ETH_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
#define HAL_PCCARD_MODULE_ENABLED
#define HAL_SRAM_MODULE_ENABLED
#define HAL_HASH_MODULE_ENABLED
#define HAL_HASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_SD_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
#define HAL_SD_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
#define HAL_HCD_MODULE_ENABLED
#define HAL_MMC_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
@ -99,7 +99,7 @@
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
@ -108,26 +108,26 @@
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */
#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/**
@ -136,7 +136,7 @@
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the Internal oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
@ -146,12 +146,12 @@
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x0FU) /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U
#define INSTRUCTION_CACHE_ENABLE 1U
#define DATA_CACHE_ENABLE 1U
#define VDD_VALUE 3300U /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U
#define INSTRUCTION_CACHE_ENABLE 1U
#define DATA_CACHE_ENABLE 1U
/* ########################## Assert Selection ############################## */
/**
@ -165,66 +165,66 @@
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2U
#define MAC_ADDR1 0U
#define MAC_ADDR2 0U
#define MAC_ADDR3 0U
#define MAC_ADDR4 0U
#define MAC_ADDR5 0U
#define MAC_ADDR0 2U
#define MAC_ADDR1 0U
#define MAC_ADDR2 0U
#define MAC_ADDR3 0U
#define MAC_ADDR4 0U
#define MAC_ADDR5 0U
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848 PHY Address*/
#define DP83848_PHY_ADDRESS 0x01U
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FFU)
#define PHY_RESET_DELAY 0x000000FFU
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU)
#define PHY_CONFIG_DELAY 0x00000FFFU
#define PHY_READ_TO ((uint32_t)0x0000FFFFU)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU)
#define PHY_READ_TO 0x0000FFFFU
#define PHY_WRITE_TO 0x0000FFFFU
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */
#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x0010U) /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x0011U) /*!< MII Interrupt Control Register */
#define PHY_MISR ((uint16_t)0x0012U) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* ################## SPI peripheral configuration ########################## */
@ -371,7 +371,10 @@
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f2xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED
#include "stm32f2xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
@ -385,7 +388,7 @@
#include "mbed_assert.h"
#define assert_param(expr) MBED_ASSERT(expr)
#else
#define assert_param(expr) ((void)0)
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */

50
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_cortex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_cortex.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
@ -26,7 +26,7 @@
function according to the following table.
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
(#) please refer to programing manual for details in how to configure priority.
(#) please refer to programming manual for details in how to configure priority.
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
@ -45,7 +45,7 @@
(+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter.
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
(++) Configures the SysTick IRQ priority to the lowest value 0x0F.
(++) Resets the SysTick Counter register.
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
(++) Enables the SysTick Interrupt.
@ -70,7 +70,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -269,6 +269,46 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
*/
#if (__MPU_PRESENT == 1U)
/**
* @brief Disables the MPU
* @retval None
*/
void HAL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable fault exceptions */
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
/* Disable the MPU and clear the control register*/
MPU->CTRL = 0U;
}
/**
* @brief Enable the MPU.
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged access to the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
/* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Ensure MPU setting take effects */
__DSB();
__ISB();
}
/**
* @brief Initializes and configures the Region and the memory to be protected.
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains

221
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_cortex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_cortex.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -54,11 +54,11 @@
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
/** @defgroup CORTEX_Exported_Types Cortex Exported Types
* @{
*/
#if (__MPU_PRESENT == 1)
#if (__MPU_PRESENT == 1U)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure
* @{
@ -105,16 +105,16 @@ typedef struct
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{
*/
#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
0 bits for subpriority */
/**
* @}
*/
@ -122,8 +122,8 @@ typedef struct
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
/**
* @}
@ -133,10 +133,11 @@ typedef struct
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
/**
* @}
*/
@ -144,8 +145,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
#define MPU_REGION_ENABLE ((uint8_t)0x01U)
#define MPU_REGION_DISABLE ((uint8_t)0x00U)
#define MPU_REGION_ENABLE ((uint8_t)0x01)
#define MPU_REGION_DISABLE ((uint8_t)0x00)
/**
* @}
*/
@ -153,8 +154,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
/**
* @}
*/
@ -162,8 +163,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
/**
* @}
*/
@ -171,8 +172,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{
*/
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
/**
* @}
*/
@ -180,8 +181,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{
*/
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
/**
* @}
*/
@ -189,9 +190,9 @@ typedef struct
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
* @{
*/
#define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
/**
* @}
*/
@ -199,47 +200,47 @@ typedef struct
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{
*/
#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
/**
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
/**
* @}
*/
@ -247,14 +248,14 @@ typedef struct
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
#define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
/**
* @}
*/
@ -273,8 +274,8 @@ typedef struct
*/
/** @addtogroup CORTEX_Exported_Functions_Group1
* @{
*/
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
@ -287,12 +288,9 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
*/
/** @addtogroup CORTEX_Exported_Functions_Group2
* @{
*/
* @{
*/
/* Peripheral Control functions ***********************************************/
#if (__MPU_PRESENT == 1U)
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
@ -302,6 +300,12 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
#if (__MPU_PRESENT == 1U)
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
/**
* @}
*/
@ -310,7 +314,7 @@ void HAL_SYSTICK_Callback(void);
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
@ -397,57 +401,14 @@ void HAL_SYSTICK_Callback(void);
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
* @brief CORTEX private functions
* @{
*/
#if (__MPU_PRESENT == 1)
/**
* @brief Disables the MPU
* @retval None
*/
__STATIC_INLINE void HAL_MPU_Disable(void)
{
/* Disable fault exceptions */
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
/* Disable the MPU */
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/**
* @brief Enables the MPU
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged access to the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
/* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
}
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}

6
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_crc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_crc.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@ -32,7 +32,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_crc.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_crc.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

38
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_cryp.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_cryp.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief CRYP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
@ -70,7 +70,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -2347,7 +2347,7 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
hcryp->State = HAL_CRYP_STATE_BUSY;
/* Set CRYP peripheral in DES CBC encryption mode */
CRYP_SetDESCBCMode(hcryp, 0);
CRYP_SetDESCBCMode(hcryp, 0U);
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
@ -2436,7 +2436,7 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
hcryp->State = HAL_CRYP_STATE_BUSY;
/* Set CRYP peripheral in DES ECB encryption mode */
CRYP_SetDESECBMode(hcryp, 0);
CRYP_SetDESECBMode(hcryp, 0U);
/* Enable Interrupts */
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
@ -3710,59 +3710,59 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
{
case CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT:
HAL_CRYP_TDESECB_Encrypt_IT(hcryp, NULL, 0U, NULL);
HAL_CRYP_TDESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
break;
case CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT:
HAL_CRYP_TDESECB_Decrypt_IT(hcryp, NULL, 0U, NULL);
HAL_CRYP_TDESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
break;
case CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT:
HAL_CRYP_TDESCBC_Encrypt_IT(hcryp, NULL, 0U, NULL);
HAL_CRYP_TDESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
break;
case CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT:
HAL_CRYP_TDESCBC_Decrypt_IT(hcryp, NULL, 0U, NULL);
HAL_CRYP_TDESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
break;
case CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT:
HAL_CRYP_DESECB_Encrypt_IT(hcryp, NULL, 0U, NULL);
HAL_CRYP_DESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
break;
case CRYP_CR_ALGOMODE_DES_ECB_DECRYPT:
HAL_CRYP_DESECB_Decrypt_IT(hcryp, NULL, 0U, NULL);
HAL_CRYP_DESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
break;
case CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT:
HAL_CRYP_DESCBC_Encrypt_IT(hcryp, NULL, 0U, NULL);
HAL_CRYP_DESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
break;
case CRYP_CR_ALGOMODE_DES_CBC_DECRYPT:
HAL_CRYP_DESCBC_Decrypt_IT(hcryp, NULL, 0U, NULL);
HAL_CRYP_DESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
break;
case CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT:
HAL_CRYP_AESECB_Encrypt_IT(hcryp, NULL, 0U, NULL);
HAL_CRYP_AESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
break;
case CRYP_CR_ALGOMODE_AES_ECB_DECRYPT:
HAL_CRYP_AESECB_Decrypt_IT(hcryp, NULL, 0U, NULL);
HAL_CRYP_AESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
break;
case CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT:
HAL_CRYP_AESCBC_Encrypt_IT(hcryp, NULL, 0U, NULL);
HAL_CRYP_AESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
break;
case CRYP_CR_ALGOMODE_AES_CBC_DECRYPT:
HAL_CRYP_AESCBC_Decrypt_IT(hcryp, NULL, 0U, NULL);
HAL_CRYP_AESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
break;
case CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT:
HAL_CRYP_AESCTR_Encrypt_IT(hcryp, NULL, 0U, NULL);
HAL_CRYP_AESCTR_Encrypt_IT(hcryp, NULL, 0, NULL);
break;
case CRYP_CR_ALGOMODE_AES_CTR_DECRYPT:
HAL_CRYP_AESCTR_Decrypt_IT(hcryp, NULL, 0U, NULL);
HAL_CRYP_AESCTR_Decrypt_IT(hcryp, NULL, 0, NULL);
break;
default:

60
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_cryp.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_cryp.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -180,42 +180,42 @@ typedef struct
/** @defgroup CRYP_Key_Size CRYP Key Size
* @{
*/
#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000U)
#define CRYP_KEYSIZE_128B 0x00000000U
#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
/**
/**
* @}
*/
/** @defgroup CRYP_Data_Type CRYP Data Type
* @{
*/
#define CRYP_DATATYPE_32B ((uint32_t)0x00000000U)
#define CRYP_DATATYPE_32B 0x00000000U
#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE
/**
/**
* @}
*/
/** @defgroup CRYP_Exported_Constants_Group3 CRYP CRYP_AlgoModeDirection
* @{
*/
#define CRYP_CR_ALGOMODE_DIRECTION ((uint32_t)0x0008003CU)
#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT ((uint32_t)0x00000000U)
#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT ((uint32_t)0x00000004U)
#define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT ((uint32_t)0x00000008U)
#define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT ((uint32_t)0x0000000CU)
#define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT ((uint32_t)0x00000010U)
#define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT ((uint32_t)0x00000014U)
#define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT ((uint32_t)0x00000018U)
#define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT ((uint32_t)0x0000001CU)
#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT ((uint32_t)0x00000020U)
#define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT ((uint32_t)0x00000024U)
#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT ((uint32_t)0x00000028U)
#define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT ((uint32_t)0x0000002CU)
#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT ((uint32_t)0x00000030U)
#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT ((uint32_t)0x00000034U)
#define CRYP_CR_ALGOMODE_DIRECTION 0x0008003CU
#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT 0x00000000U
#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT 0x00000004U
#define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT 0x00000008U
#define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT 0x0000000CU
#define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT 0x00000010U
#define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT 0x00000014U
#define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT 0x00000018U
#define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT 0x0000001CU
#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT 0x00000020U
#define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT 0x00000024U
#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT 0x00000028U
#define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT 0x0000002CU
#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT 0x00000030U
#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT 0x00000034U
/**
* @}
*/
@ -232,17 +232,17 @@ typedef struct
/** @defgroup CRYP_Exported_Constants_Group5 CRYP CRYP_Flags
* @{
*/
#define CRYP_FLAG_BUSY ((uint32_t)0x00000010U) /*!< The CRYP core is currently
#define CRYP_FLAG_BUSY 0x00000010U /*!< The CRYP core is currently
processing a block of data
or a key preparation (for
AES decryption). */
#define CRYP_FLAG_IFEM ((uint32_t)0x00000001U) /*!< Input FIFO is empty */
#define CRYP_FLAG_IFNF ((uint32_t)0x00000002U) /*!< Input FIFO is not Full */
#define CRYP_FLAG_OFNE ((uint32_t)0x00000004U) /*!< Output FIFO is not empty */
#define CRYP_FLAG_OFFU ((uint32_t)0x00000008U) /*!< Output FIFO is Full */
#define CRYP_FLAG_OUTRIS ((uint32_t)0x01000002U) /*!< Output FIFO service raw
#define CRYP_FLAG_IFEM 0x00000001U /*!< Input FIFO is empty */
#define CRYP_FLAG_IFNF 0x00000002U /*!< Input FIFO is not Full */
#define CRYP_FLAG_OFNE 0x00000004U /*!< Output FIFO is not empty */
#define CRYP_FLAG_OFFU 0x00000008U /*!< Output FIFO is Full */
#define CRYP_FLAG_OUTRIS 0x01000002U /*!< Output FIFO service raw
interrupt status */
#define CRYP_FLAG_INRIS ((uint32_t)0x01000001U) /*!< Input FIFO service raw
#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw
interrupt status */
/**
* @}
@ -483,7 +483,7 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
/** @defgroup CRYP_Private_Constants CRYP Private Constants
* @{
*/
#define CRYP_FLAG_MASK ((uint32_t)0x0000001FU)
#define CRYP_FLAG_MASK 0x0000001FU
/**
* @}
*/

8
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_dac.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_dac.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
@ -141,7 +141,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -436,7 +436,7 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param pData: The destination peripheral Buffer address.
* @param pData: The Source memory Buffer address.
* @param Length: The length of data to be transferred from memory to DAC peripheral
* @param Alignment: Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:

24
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_dac.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_dac.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -125,7 +125,7 @@ typedef struct
* @{
*/
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
@ -143,7 +143,7 @@ typedef struct
/** @defgroup DAC_output_buffer DAC Output Buffer
* @{
*/
#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000U)
#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
/**
* @}
@ -152,8 +152,8 @@ typedef struct
/** @defgroup DAC_Channel_selection DAC Channel Selection
* @{
*/
#define DAC_CHANNEL_1 ((uint32_t)0x00000000U)
#define DAC_CHANNEL_2 ((uint32_t)0x00000010U)
#define DAC_CHANNEL_1 0x00000000U
#define DAC_CHANNEL_2 0x00000010U
/**
* @}
*/
@ -161,9 +161,9 @@ typedef struct
/** @defgroup DAC_data_alignment DAC Data Alignment
* @{
*/
#define DAC_ALIGN_12B_R ((uint32_t)0x00000000U)
#define DAC_ALIGN_12B_L ((uint32_t)0x00000004U)
#define DAC_ALIGN_8B_R ((uint32_t)0x00000008U)
#define DAC_ALIGN_12B_R 0x00000000U
#define DAC_ALIGN_12B_L 0x00000004U
#define DAC_ALIGN_8B_R 0x00000008U
/**
* @}
*/
@ -362,7 +362,7 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
* @param __ALIGNMENT__: specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__))
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__))
/** @brief Set DHR12R2 alignment
* @param __ALIGNMENT__: specifies the DAC alignment
@ -374,7 +374,7 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
* @param __ALIGNMENT__: specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__))
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__))
/**
* @}

6
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_dac_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_dac_ex.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DAC extension peripheral:
@ -25,7 +25,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

10
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_dac_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_dac_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -63,7 +63,7 @@
/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude
* @{
*/
#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUNMASK_BIT0 0x00000000U /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
@ -75,7 +75,7 @@
#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000U) /*!< Select max triangle amplitude of 1 */
#define DAC_TRIANGLEAMPLITUDE_1 0x00000000U /*!< Select max triangle amplitude of 1 */
#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */

28
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_dcmi.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_dcmi.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief DCMI HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the Digital Camera Interface (DCMI) peripheral:
@ -63,7 +63,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -106,7 +106,7 @@
#if defined(STM32F207xx) || defined(STM32F217xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)14U) /* Set timeout to 1s */
#define HAL_TIMEOUT_DCMI_STOP 14U /* Set timeout to 1s */
#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE) /*!< Required left shift to set crop window vertical line count */
#define DCMI_POSITION_CWSTRT_VST (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST) /*!< Required left shift to set crop window vertical start line count */
@ -322,8 +322,8 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
hdcmi->DMA_Handle->XferAbortCallback = NULL;
/* Reset transfer counters value */
hdcmi->XferCount = 0;
hdcmi->XferTransferNumber = 0;
hdcmi->XferCount = 0U;
hdcmi->XferTransferNumber = 0U;
if(Length <= 0xFFFFU)
{
@ -391,7 +391,7 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
/* Check if the DCMI capture effectively disabled */
do
{
if (count-- == 0)
if (count-- == 0U)
{
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
@ -399,7 +399,7 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
status = HAL_TIMEOUT;
}
}
while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);
while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
/* Disable the DCMI */
__HAL_DCMI_DISABLE(hdcmi);
@ -420,6 +420,12 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
return status;
}
/**
* @brief Suspend DCMI capture
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
{
__IO uint32_t count = SystemCoreClock / HAL_TIMEOUT_DCMI_STOP;
@ -439,7 +445,7 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
/* Check if the DCMI capture effectively disabled */
do
{
if (count-- == 0)
if (count-- == 0U)
{
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
@ -451,7 +457,7 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
break;
}
}
while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);
while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
}
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
@ -799,7 +805,7 @@ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
if(hdcmi->XferCount != 0)
if(hdcmi->XferCount != 0U)
{
/* Update memory 0 address location */
tmp = ((hdcmi->DMA_Handle->Instance->CR) & DMA_SxCR_CT);

40
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_dcmi.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_dcmi.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of DCMI HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -153,11 +153,11 @@ typedef struct
/** @defgroup DCMI_Error_Code DCMI Error Code
* @{
*/
#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_DCMI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun error */
#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002U) /*!< Synchronization error */
#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
#define HAL_DCMI_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error */
#define HAL_DCMI_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_DCMI_ERROR_OVR 0x00000001U /*!< Overrun error */
#define HAL_DCMI_ERROR_SYNC 0x00000002U /*!< Synchronization error */
#define HAL_DCMI_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
#define HAL_DCMI_ERROR_DMA 0x00000040U /*!< DMA error */
/**
* @}
*/
@ -165,7 +165,7 @@ typedef struct
/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
* @{
*/
#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< The received data are transferred continuously
#define DCMI_MODE_CONTINUOUS 0x00000000U /*!< The received data are transferred continuously
into the destination memory through the DMA */
#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
frame and then transfers a single frame through the DMA */
@ -176,7 +176,7 @@ typedef struct
/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
* @{
*/
#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000U) /*!< Hardware synchronization data capture (frame/line start/stop)
#define DCMI_SYNCHRO_HARDWARE 0x00000000U /*!< Hardware synchronization data capture (frame/line start/stop)
is synchronized with the HSYNC/VSYNC signals */
#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
synchronization codes embedded in the data flow */
@ -188,7 +188,7 @@ typedef struct
/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
* @{
*/
#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000U) /*!< Pixel clock active on Falling edge */
#define DCMI_PCKPOLARITY_FALLING 0x00000000U /*!< Pixel clock active on Falling edge */
#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
/**
@ -198,7 +198,7 @@ typedef struct
/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
* @{
*/
#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Vertical synchronization active Low */
#define DCMI_VSPOLARITY_LOW 0x00000000U /*!< Vertical synchronization active Low */
#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
/**
@ -208,7 +208,7 @@ typedef struct
/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
* @{
*/
#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Horizontal synchronization active Low */
#define DCMI_HSPOLARITY_LOW 0x00000000U /*!< Horizontal synchronization active Low */
#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
/**
@ -218,7 +218,7 @@ typedef struct
/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
* @{
*/
#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000U) /*!< Mode JPEG Disabled */
#define DCMI_JPEG_DISABLE 0x00000000U /*!< Mode JPEG Disabled */
#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */
/**
@ -228,7 +228,7 @@ typedef struct
/** @defgroup DCMI_Capture_Rate DCMI Capture Rate
* @{
*/
#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000U) /*!< All frames are captured */
#define DCMI_CR_ALL_FRAME 0x00000000U /*!< All frames are captured */
#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
@ -239,7 +239,7 @@ typedef struct
/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
* @{
*/
#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000U) /*!< Interface captures 8-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_8B 0x00000000U /*!< Interface captures 8-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
@ -251,7 +251,7 @@ typedef struct
/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
* @{
*/
#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFFU) /*!< Window coordinate */
#define DCMI_WINDOW_COORDINATE 0x3FFFU /*!< Window coordinate */
/**
* @}
@ -260,7 +260,7 @@ typedef struct
/** @defgroup DCMI_Window_Height DCMI Window Height
* @{
*/
#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFFU) /*!< Window Height */
#define DCMI_WINDOW_HEIGHT 0x1FFFU /*!< Window Height */
/**
* @}
@ -499,8 +499,8 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
/** @defgroup DCMI_Private_Constants DCMI Private Constants
* @{
*/
#define DCMI_MIS_INDEX ((uint32_t)0x1000U) /*!< DCMI MIS register index */
#define DCMI_SR_INDEX ((uint32_t)0x2000U) /*!< DCMI SR register index */
#define DCMI_MIS_INDEX 0x1000U /*!< DCMI MIS register index */
#define DCMI_SR_INDEX 0x2000U /*!< DCMI SR register index */
/**
* @}
*/

8
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_def.h
View File

@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f2xx_hal_def.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -84,7 +84,7 @@ typedef enum
} while(0)
#define UNUSED(x) ((void)(x))
/** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:

152
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_dma.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_dma.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@ -76,9 +76,6 @@
(+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
(+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
(+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
(+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
(+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
[..]
@ -88,7 +85,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -142,7 +139,7 @@ typedef struct
/** @addtogroup DMA_Private_Constants
* @{
*/
#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)5) /* 5 ms */
#define HAL_TIMEOUT_DMA_ABORT 5U /* 5 ms */
/**
* @}
*/
@ -158,8 +155,8 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/* Exported functions ---------------------------------------------------------*/
/** @addtogroup DMA_Exported_Functions
* @{
*/
@ -183,7 +180,7 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
*/
/**
* @brief Initializes the DMA according to the specified
* @brief Initialize the DMA according to the specified
* parameters in the DMA_InitTypeDef and create the associated handle.
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
@ -280,21 +277,26 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
/* Prepare the DMA Stream FIFO configuration */
tmp |= hdma->Init.FIFOMode;
/* the FIFO threshold is not used when the FIFO mode is disabled */
/* The FIFO threshold is not used when the FIFO mode is disabled */
if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
{
/* Get the FIFO threshold */
tmp |= hdma->Init.FIFOThreshold;
if(DMA_CheckFifoParam(hdma) != HAL_OK)
/* Check compatibility between FIFO threshold level and size of the memory burst */
/* for INCR4, INCR8, INCR16 bursts */
if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
return HAL_ERROR;
if (DMA_CheckFifoParam(hdma) != HAL_OK)
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
return HAL_ERROR;
}
}
}
@ -340,6 +342,9 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
return HAL_BUSY;
}
/* Check the parameters */
assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
/* Disable the selected DMA Streamx */
__HAL_DMA_DISABLE(hdma);
@ -359,7 +364,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
hdma->Instance->M1AR = 0U;
/* Reset DMA Streamx FIFO control register */
hdma->Instance->FCR = (uint32_t)0x00000021U;
hdma->Instance->FCR = 0x00000021U;
/* Get DMA steam Base Address */
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
@ -446,7 +451,7 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
}
/**
* @brief Starts the DMA Transfer with interrupt enabled.
* @brief Start the DMA Transfer with interrupt enabled.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param SrcAddress: The source memory Buffer address
@ -659,7 +664,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
/* Check for the Timeout (Not applicable in circular mode)*/
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
@ -753,8 +758,8 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
uint32_t tmpisr;
__IO uint32_t count = 0;
uint32_t timeout = SystemCoreClock / 9600;
__IO uint32_t count = 0U;
uint32_t timeout = SystemCoreClock / 9600U;
/* calculate DMA base and stream number */
DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
@ -1210,7 +1215,7 @@ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
}
/**
* @brief Checks compatibility between FIFO threshold level and size of the memory burst
* @brief Check compatibility between FIFO threshold level and size of the memory burst
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
@ -1225,28 +1230,23 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
{
switch (tmp)
{
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
if((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
{
status = HAL_ERROR;
}
break;
case DMA_FIFO_THRESHOLD_HALFFULL:
if(hdma->Init.MemBurst == DMA_MBURST_INC16)
{
status = HAL_ERROR;
}
break;
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
if((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
{
status = HAL_ERROR;
}
break;
case DMA_FIFO_THRESHOLD_FULL:
break;
default:
break;
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
{
status = HAL_ERROR;
}
break;
case DMA_FIFO_THRESHOLD_HALFFULL:
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
{
status = HAL_ERROR;
}
break;
case DMA_FIFO_THRESHOLD_FULL:
break;
default:
break;
}
}
@ -1255,26 +1255,24 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
{
switch (tmp)
{
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
status = HAL_ERROR;
break;
case DMA_FIFO_THRESHOLD_HALFFULL:
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
{
status = HAL_ERROR;
break;
case DMA_FIFO_THRESHOLD_HALFFULL:
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
{
status = HAL_ERROR;
}
break;
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
}
break;
case DMA_FIFO_THRESHOLD_FULL:
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
{
status = HAL_ERROR;
break;
case DMA_FIFO_THRESHOLD_FULL:
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
{
status = HAL_ERROR;
}
break;
default:
break;
}
break;
default:
break;
}
}
@ -1283,19 +1281,19 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
{
switch (tmp)
{
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
case DMA_FIFO_THRESHOLD_HALFFULL:
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
case DMA_FIFO_THRESHOLD_HALFFULL:
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
status = HAL_ERROR;
break;
case DMA_FIFO_THRESHOLD_FULL:
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
{
status = HAL_ERROR;
break;
case DMA_FIFO_THRESHOLD_FULL:
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
{
status = HAL_ERROR;
}
break;
default:
break;
}
break;
default:
break;
}
}

102
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_dma.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_dma.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -201,14 +201,14 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA Error Code
* @{
*/
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U) /*!< FIFO error */
#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U) /*!< Direct Mode error */
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
#define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U) /*!< Parameter error */
#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort requested with no Xfer ongoing */
#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */
#define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */
#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */
#define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
/**
* @}
*/
@ -217,14 +217,14 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA channel selection
* @{
*/
#define DMA_CHANNEL_0 ((uint32_t)0x00000000U) /*!< DMA Channel 0 */
#define DMA_CHANNEL_1 ((uint32_t)0x02000000U) /*!< DMA Channel 1 */
#define DMA_CHANNEL_2 ((uint32_t)0x04000000U) /*!< DMA Channel 2 */
#define DMA_CHANNEL_3 ((uint32_t)0x06000000U) /*!< DMA Channel 3 */
#define DMA_CHANNEL_4 ((uint32_t)0x08000000U) /*!< DMA Channel 4 */
#define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /*!< DMA Channel 5 */
#define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /*!< DMA Channel 6 */
#define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /*!< DMA Channel 7 */
#define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */
#define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */
#define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */
#define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */
#define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */
#define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */
#define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */
#define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */
/**
* @}
*/
@ -233,7 +233,7 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA data transfer direction
* @{
*/
#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
/**
@ -245,7 +245,7 @@ typedef struct __DMA_HandleTypeDef
* @{
*/
#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */
#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */
/**
* @}
*/
@ -255,7 +255,7 @@ typedef struct __DMA_HandleTypeDef
* @{
*/
#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */
#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */
/**
* @}
*/
@ -264,7 +264,7 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA peripheral data size
* @{
*/
#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */
#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
/**
@ -275,7 +275,7 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA memory data size
* @{
*/
#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */
#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
/**
@ -286,7 +286,7 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA mode
* @{
*/
#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
#define DMA_NORMAL 0x00000000U /*!< Normal mode */
#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
/**
@ -297,7 +297,7 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA priority levels
* @{
*/
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */
#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
@ -309,7 +309,7 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA FIFO direct mode
* @{
*/
#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */
#define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
/**
* @}
@ -319,7 +319,7 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA FIFO level
* @{
*/
#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */
#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */
#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
@ -331,7 +331,7 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA memory burst
* @{
*/
#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
#define DMA_MBURST_SINGLE 0x00000000U
#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
@ -343,7 +343,7 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA peripheral burst
* @{
*/
#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
#define DMA_PBURST_SINGLE 0x00000000U
#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
@ -359,7 +359,7 @@ typedef struct __DMA_HandleTypeDef
#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
#define DMA_IT_FE ((uint32_t)0x00000080U)
#define DMA_IT_FE 0x00000080U
/**
* @}
*/
@ -368,26 +368,26 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA flag definitions
* @{
*/
#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)
#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)
#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
#define DMA_FLAG_FEIF0_4 0x00800001U
#define DMA_FLAG_DMEIF0_4 0x00800004U
#define DMA_FLAG_TEIF0_4 0x00000008U
#define DMA_FLAG_HTIF0_4 0x00000010U
#define DMA_FLAG_TCIF0_4 0x00000020U
#define DMA_FLAG_FEIF1_5 0x00000040U
#define DMA_FLAG_DMEIF1_5 0x00000100U
#define DMA_FLAG_TEIF1_5 0x00000200U
#define DMA_FLAG_HTIF1_5 0x00000400U
#define DMA_FLAG_TCIF1_5 0x00000800U
#define DMA_FLAG_FEIF2_6 0x00010000U
#define DMA_FLAG_DMEIF2_6 0x00040000U
#define DMA_FLAG_TEIF2_6 0x00080000U
#define DMA_FLAG_HTIF2_6 0x00100000U
#define DMA_FLAG_TCIF2_6 0x00200000U
#define DMA_FLAG_FEIF3_7 0x00400000U
#define DMA_FLAG_DMEIF3_7 0x01000000U
#define DMA_FLAG_TEIF3_7 0x02000000U
#define DMA_FLAG_HTIF3_7 0x04000000U
#define DMA_FLAG_TCIF3_7 0x08000000U
/**
* @}
*/

6
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_dma_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_dma_ex.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the DMA Extension peripheral:
@ -27,7 +27,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_dma_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_dma_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

21
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_eth.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_eth.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief ETH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Ethernet (ETH) peripheral:
@ -68,7 +68,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -116,9 +116,9 @@
/** @defgroup ETH_Private_Constants ETH Private Constants
* @{
*/
#define ETH_TIMEOUT_SWRESET ((uint32_t)500U)
#define ETH_TIMEOUT_LINKED_STATE ((uint32_t)5000U)
#define ETH_TIMEOUT_AUTONEGO_COMPLETED ((uint32_t)5000U)
#define ETH_TIMEOUT_SWRESET 500U
#define ETH_TIMEOUT_LINKED_STATE 5000U
#define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U
/**
* @}
@ -573,7 +573,7 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc
if(i < (RxBuffCount-1U))
{
/* Set next descriptor address register with next descriptor base address */
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U);
}
else
{
@ -1427,7 +1427,7 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
tmpreg1 = (heth->Instance)->MACCR;
/* Clear FES and DM bits */
tmpreg1 &= ~((uint32_t)0x00004800U);
tmpreg1 &= ~(0x00004800U);
tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
@ -1856,7 +1856,10 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
{
uint32_t tmpreg1;
/* Prevent unused argument(s) compilation warning */
UNUSED(heth);
/* Check the parameters */
assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));

684
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_eth.h
View File

File diff suppressed because it is too large Load Diff

15
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_flash.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_flash.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@ -65,7 +65,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -111,7 +111,7 @@
/** @addtogroup FLASH_Private_Constants
* @{
*/
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */
#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
/**
* @}
*/
@ -584,7 +584,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
}
/* Check FLASH End of Operation flag */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
@ -625,10 +625,11 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
FLASH->CR |= FLASH_CR_PG;
*(__IO uint64_t*)Address = Data;
/* Program the double-word */
*(__IO uint32_t*)Address = (uint32_t)Data;
*(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
}
/**
* @brief Program word (32-bit) at a specified address.
* @note This function must be used when the device voltage range is from

70
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_flash.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_flash.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -105,12 +105,12 @@ typedef struct
* @brief FLASH Error Code
* @{
*/
#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000001U) /*!< Programming Sequence error */
#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000002U) /*!< Programming Parallelism error */
#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000004U) /*!< Programming Alignment error */
#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000008U) /*!< Write protection error */
#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000010U) /*!< Operation Error */
#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_FLASH_ERROR_PGS 0x00000001U /*!< Programming Sequence error */
#define HAL_FLASH_ERROR_PGP 0x00000002U /*!< Programming Parallelism error */
#define HAL_FLASH_ERROR_PGA 0x00000004U /*!< Programming Alignment error */
#define HAL_FLASH_ERROR_WRP 0x00000008U /*!< Write protection error */
#define HAL_FLASH_ERROR_OPERATION 0x00000010U /*!< Operation Error */
/**
* @}
*/
@ -118,10 +118,10 @@ typedef struct
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U) /*!< Program byte (8-bit) at a specified address */
#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!< Program a half-word (16-bit) at a specified address */
#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!< Program a word (32-bit) at a specified address */
#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U) /*!< Program a double word (64-bit) at a specified address */
#define FLASH_TYPEPROGRAM_BYTE 0x00U /*!< Program byte (8-bit) at a specified address */
#define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!< Program a half-word (16-bit) at a specified address */
#define FLASH_TYPEPROGRAM_WORD 0x02U /*!< Program a word (32-bit) at a specified address */
#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x03U /*!< Program a double word (64-bit) at a specified address */
/**
* @}
*/
@ -146,7 +146,7 @@ typedef struct
* @{
*/
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
#define FLASH_IT_ERR ((uint32_t)0x02000000U) /*!< Error Interrupt source */
#define FLASH_IT_ERR 0x02000000U /*!< Error Interrupt source */
/**
* @}
*/
@ -154,11 +154,11 @@ typedef struct
/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
* @{
*/
#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U)
#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100U)
#define FLASH_PSIZE_WORD ((uint32_t)0x00000200U)
#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300U)
#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU)
#define FLASH_PSIZE_BYTE 0x00000000U
#define FLASH_PSIZE_HALF_WORD 0x00000100U
#define FLASH_PSIZE_WORD 0x00000200U
#define FLASH_PSIZE_DOUBLE_WORD 0x00000300U
#define CR_PSIZE_MASK 0xFFFFFCFFU
/**
* @}
*/
@ -166,11 +166,11 @@ typedef struct
/** @defgroup FLASH_Keys FLASH Keys
* @{
*/
#define RDP_KEY ((uint16_t)0x00A5U)
#define FLASH_KEY1 ((uint32_t)0x45670123U)
#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU)
#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU)
#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU)
#define RDP_KEY ((uint16_t)0x00A5)
#define FLASH_KEY1 0x45670123U
#define FLASH_KEY2 0xCDEF89ABU
#define FLASH_OPT_KEY1 0x08192A3BU
#define FLASH_OPT_KEY2 0x4C5D6E7FU
/**
* @}
*/
@ -241,7 +241,7 @@ typedef struct
*/
#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST; \
FLASH->ACR &= ~FLASH_ACR_ICRST; \
}while(0)
}while(0U)
/**
* @brief Resets the FLASH data Cache.
@ -250,7 +250,7 @@ typedef struct
*/
#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST; \
FLASH->ACR &= ~FLASH_ACR_DCRST; \
}while(0)
}while(0U)
/**
* @brief Enable the specified FLASH interrupt.
* @param __INTERRUPT__ : FLASH interrupt
@ -273,8 +273,8 @@ typedef struct
/**
* @brief Get the specified FLASH flag status.
* @param __FLAG__: specifies the FLASH flag to check.
* This parameter can be one of the following values:
* @param __FLAG__: specifies the FLASH flags to check.
* This parameter can be any combination of the following values:
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
* @arg FLASH_FLAG_OPERR : FLASH operation Error flag
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
@ -284,10 +284,10 @@ typedef struct
* @arg FLASH_FLAG_BSY : FLASH Busy flag
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)) == (__FLAG__))
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)))
/**
* @brief Clear the specified FLASH flag.
* @brief Clear the specified FLASH flags.
* @param __FLAG__: specifies the FLASH flags to clear.
* This parameter can be any combination of the following values:
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
@ -369,23 +369,23 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/**
* @brief ACR register byte 0 (Bits[7:0]) base address
*/
#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00U)
#define ACR_BYTE0_ADDRESS 0x40023C00U
/**
* @brief OPTCR register byte 0 (Bits[7:0]) base address
*/
#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14U)
#define OPTCR_BYTE0_ADDRESS 0x40023C14U
/**
* @brief OPTCR register byte 1 (Bits[15:8]) base address
*/
#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15U)
#define OPTCR_BYTE1_ADDRESS 0x40023C15U
/**
* @brief OPTCR register byte 2 (Bits[23:16]) base address
*/
#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16U)
#define OPTCR_BYTE2_ADDRESS 0x40023C16U
/**
* @brief OPTCR register byte 3 (Bits[31:24]) base address
*/
#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17U)
#define OPTCR_BYTE3_ADDRESS 0x40023C17U
/**
* @}

29
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_flash_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_flash_ex.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Extended FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the FLASH extension peripheral:
@ -36,7 +36,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -82,7 +82,7 @@
/** @addtogroup FLASHEx_Private_Constants
* @{
*/
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */
#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
/**
* @}
*/
@ -452,6 +452,9 @@ void FLASH_FlushCaches(void)
*/
static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(Banks);
/* Check the parameters */
assert_param(IS_VOLTAGERANGE(VoltageRange));
assert_param(IS_FLASH_BANK(Banks));
@ -481,7 +484,10 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
{
HAL_StatusTypeDef status = HAL_OK;
/* Prevent unused argument(s) compilation warning */
UNUSED(Banks);
/* Check the parameters */
assert_param(IS_OB_WRP_SECTOR(WRPSector));
assert_param(IS_FLASH_BANK(Banks));
@ -516,7 +522,10 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
{
HAL_StatusTypeDef status = HAL_OK;
/* Prevent unused argument(s) compilation warning */
UNUSED(Banks);
/* Check the parameters */
assert_param(IS_OB_WRP_SECTOR(WRPSector));
assert_param(IS_FLASH_BANK(Banks));
@ -580,7 +589,7 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
*/
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby)
{
uint8_t optiontmp = 0xFFU;
uint8_t optiontmp = 0xFF;
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
@ -594,7 +603,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t
if(status == HAL_OK)
{
/* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1FU);
optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F);
/* Update User Option Byte */
*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = Iwdg | (uint8_t)(Stdby | (uint8_t)(Stop | ((uint8_t)optiontmp)));
@ -634,7 +643,7 @@ static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
static uint8_t FLASH_OB_GetUser(void)
{
/* Return the User Option Byte */
return ((uint8_t)(FLASH->OPTCR & 0xE0U));
return ((uint8_t)(FLASH->OPTCR & 0xE0));
}
/**
@ -686,7 +695,7 @@ static uint8_t FLASH_OB_GetRDP(void)
static uint8_t FLASH_OB_GetBOR(void)
{
/* Return the FLASH BOR level */
return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0CU);
return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
}
/**

131
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_flash_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_flash_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of FLASH HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -68,17 +68,17 @@ typedef struct
This parameter can be a value of @ref FLASHEx_Type_Erase */
uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
This parameter must be a value of @ref FLASHEx_Banks */
This parameter must be a value of @ref FLASHEx_Banks */
uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled
This parameter must be a value of @ref FLASHEx_Sectors */
This parameter must be a value of @ref FLASHEx_Sectors */
uint32_t NbSectors; /*!< Number of sectors to be erased.
This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
This parameter must be a value of @ref FLASHEx_Voltage_Range */
This parameter must be a value of @ref FLASHEx_Voltage_Range */
} FLASH_EraseInitTypeDef;
/**
@ -117,8 +117,8 @@ typedef struct
/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
* @{
*/
#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */
#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */
#define FLASH_TYPEERASE_SECTORS 0x00000000U /*!< Sectors erase only */
#define FLASH_TYPEERASE_MASSERASE 0x00000001U /*!< Flash Mass erase activation */
/**
* @}
*/
@ -126,10 +126,10 @@ typedef struct
/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
* @{
*/
#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Device operating range: 1.8V to 2.1V */
#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) /*!< Device operating range: 2.1V to 2.7V */
#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) /*!< Device operating range: 2.7V to 3.6V */
#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U) /*!< Device operating range: 2.7V to 3.6V + External Vpp */
#define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Device operating range: 1.8V to 2.1V */
#define FLASH_VOLTAGE_RANGE_2 0x00000001U /*!< Device operating range: 2.1V to 2.7V */
#define FLASH_VOLTAGE_RANGE_3 0x00000002U /*!< Device operating range: 2.7V to 3.6V */
#define FLASH_VOLTAGE_RANGE_4 0x00000003U /*!< Device operating range: 2.7V to 3.6V + External Vpp */
/**
* @}
*/
@ -137,8 +137,8 @@ typedef struct
/** @defgroup FLASHEx_WRP_State FLASH WRP State
* @{
*/
#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */
#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */
#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */
#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired bank 1 sectors */
/**
* @}
*/
@ -146,10 +146,10 @@ typedef struct
/** @defgroup FLASHEx_Option_Type FLASH Option Type
* @{
*/
#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */
#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */
#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */
#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */
#define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */
#define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */
#define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */
#define OPTIONBYTE_BOR 0x00000008U /*!< BOR option byte configuration */
/**
* @}
*/
@ -157,10 +157,10 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
* @{
*/
#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
#define OB_RDP_LEVEL_1 ((uint8_t)0x55U)
#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2
it s no more possible to go back to level 1 or 0 */
#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
#define OB_RDP_LEVEL_1 ((uint8_t)0x55)
#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2
it s no more possible to go back to level 1 or 0 */
/**
* @}
*/
@ -168,8 +168,8 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
* @{
*/
#define OB_IWDG_SW ((uint8_t)0x20U) /*!< Software IWDG selected */
#define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware IWDG selected */
#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
/**
* @}
*/
@ -177,8 +177,8 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
* @{
*/
#define OB_STOP_NO_RST ((uint8_t)0x40U) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
#define OB_STOP_NO_RST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
/**
* @}
*/
@ -187,8 +187,8 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
* @{
*/
#define OB_STDBY_NO_RST ((uint8_t)0x80U) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
#define OB_STDBY_NO_RST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
/**
* @}
*/
@ -196,10 +196,10 @@ typedef struct
/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
* @{
*/
#define OB_BOR_LEVEL3 ((uint8_t)0x00U) /*!< Supply voltage ranges from 2.70 to 3.60 V */
#define OB_BOR_LEVEL2 ((uint8_t)0x04U) /*!< Supply voltage ranges from 2.40 to 2.70 V */
#define OB_BOR_LEVEL1 ((uint8_t)0x08U) /*!< Supply voltage ranges from 2.10 to 2.40 V */
#define OB_BOR_OFF ((uint8_t)0x0CU) /*!< Supply voltage ranges from 1.62 to 2.10 V */
#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */
#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */
#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */
#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */
/**
* @}
*/
@ -229,7 +229,7 @@ typedef struct
/** @defgroup FLASHEx_Banks FLASH Banks
* @{
*/
#define FLASH_BANK_1 ((uint32_t)1U) /*!< Bank 1 */
#define FLASH_BANK_1 1U /*!< Bank 1 */
/**
* @}
*/
@ -237,7 +237,7 @@ typedef struct
/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
* @{
*/
#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER Bit */
#define FLASH_MER_BIT FLASH_CR_MER /*!< only 1 MER Bit */
/**
* @}
*/
@ -245,18 +245,18 @@ typedef struct
/** @defgroup FLASHEx_Sectors FLASH Sectors
* @{
*/
#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */
#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */
#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */
#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */
#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */
#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */
#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */
#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */
#define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */
#define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */
#define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */
#define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */
#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */
#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */
#define FLASH_SECTOR_2 2U /*!< Sector Number 2 */
#define FLASH_SECTOR_3 3U /*!< Sector Number 3 */
#define FLASH_SECTOR_4 4U /*!< Sector Number 4 */
#define FLASH_SECTOR_5 5U /*!< Sector Number 5 */
#define FLASH_SECTOR_6 6U /*!< Sector Number 6 */
#define FLASH_SECTOR_7 7U /*!< Sector Number 7 */
#define FLASH_SECTOR_8 8U /*!< Sector Number 8 */
#define FLASH_SECTOR_9 9U /*!< Sector Number 9 */
#define FLASH_SECTOR_10 10U /*!< Sector Number 10 */
#define FLASH_SECTOR_11 11U /*!< Sector Number 11 */
@ -267,19 +267,19 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
* @{
*/
#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001U) /*!< Write protection of Sector0 */
#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002U) /*!< Write protection of Sector1 */
#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004U) /*!< Write protection of Sector2 */
#define OB_WRP_SECTOR_3 ((uint32_t)0x00000008U) /*!< Write protection of Sector3 */
#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010U) /*!< Write protection of Sector4 */
#define OB_WRP_SECTOR_5 ((uint32_t)0x00000020U) /*!< Write protection of Sector5 */
#define OB_WRP_SECTOR_6 ((uint32_t)0x00000040U) /*!< Write protection of Sector6 */
#define OB_WRP_SECTOR_7 ((uint32_t)0x00000080U) /*!< Write protection of Sector7 */
#define OB_WRP_SECTOR_8 ((uint32_t)0x00000100U) /*!< Write protection of Sector8 */
#define OB_WRP_SECTOR_9 ((uint32_t)0x00000200U) /*!< Write protection of Sector9 */
#define OB_WRP_SECTOR_10 ((uint32_t)0x00000400U) /*!< Write protection of Sector10 */
#define OB_WRP_SECTOR_11 ((uint32_t)0x00000800U) /*!< Write protection of Sector11 */
#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFFU) /*!< Write protection of all Sectors */
#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */
#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */
#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */
#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */
#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */
#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */
#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */
#define OB_WRP_SECTOR_8 0x00000100U /*!< Write protection of Sector8 */
#define OB_WRP_SECTOR_9 0x00000200U /*!< Write protection of Sector9 */
#define OB_WRP_SECTOR_10 0x00000400U /*!< Write protection of Sector10 */
#define OB_WRP_SECTOR_11 0x00000800U /*!< Write protection of Sector11 */
#define OB_WRP_SECTOR_All 0x00000FFFU /*!< Write protection of all Sectors */
/**
@ -387,9 +387,10 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \
(((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END)))
#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
/**
* @}

38
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_gpio.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_gpio.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
@ -95,7 +95,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -141,15 +141,15 @@
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
#define GPIO_MODE ((uint32_t)0x00000003U)
#define EXTI_MODE ((uint32_t)0x10000000U)
#define GPIO_MODE_IT ((uint32_t)0x00010000U)
#define GPIO_MODE_EVT ((uint32_t)0x00020000U)
#define RISING_EDGE ((uint32_t)0x00100000U)
#define FALLING_EDGE ((uint32_t)0x00200000U)
#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U)
#define GPIO_MODE 0x00000003U
#define EXTI_MODE 0x10000000U
#define GPIO_MODE_IT 0x00010000U
#define GPIO_MODE_EVT 0x00020000U
#define RISING_EDGE 0x00100000U
#define FALLING_EDGE 0x00200000U
#define GPIO_OUTPUT_TYPE 0x00000010U
#define GPIO_NUMBER ((uint32_t)16U)
#define GPIO_NUMBER 16U
/**
* @}
*/
@ -202,7 +202,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
for(position = 0U; position < GPIO_NUMBER; position++)
{
/* Get the IO position */
ioposition = ((uint32_t)0x01U) << position;
ioposition = 0x01U << position;
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
@ -216,8 +216,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
temp &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U)) ;
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07U) * 4U));
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
GPIOx->AFR[position >> 3U] = temp;
}
@ -260,7 +260,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
__HAL_RCC_SYSCFG_CLK_ENABLE();
temp = SYSCFG->EXTICR[position >> 2U];
temp &= ~(((uint32_t)0x0FU) << (4U * (position & 0x03)));
temp &= ~(0x0FU << (4U * (position & 0x03)));
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
SYSCFG->EXTICR[position >> 2U] = temp;
@ -323,7 +323,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
for(position = 0U; position < GPIO_NUMBER; position++)
{
/* Get the IO position */
ioposition = ((uint32_t)0x01U) << position;
ioposition = 0x01U << position;
/* Get the current IO position */
iocurrent = (GPIO_Pin) & ioposition;
@ -334,7 +334,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3U] &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U)) ;
GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
@ -347,11 +347,11 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/*------------------------- EXTI Mode Configuration --------------------*/
tmp = SYSCFG->EXTICR[position >> 2U];
tmp &= (((uint32_t)0x0FU) << (4U * (position & 0x03U)));
tmp &= (0x0FU << (4U * (position & 0x03U)));
if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))))
{
/* Configure the External Interrupt or event for the current IO */
tmp = ((uint32_t)0x0FU) << (4U * (position & 0x03U));
tmp = 0x0FU << (4U * (position & 0x03U));
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
/* Clear EXTI line configuration */

84
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_gpio.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_gpio.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -101,25 +101,25 @@ typedef enum
/** @defgroup GPIO_pins_define GPIO pins define
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */
#define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */
/**
* @}
*/
@ -134,21 +134,21 @@ typedef enum
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
* @{
*/
#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_INPUT 0x00000000U /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP 0x00000001U /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD 0x00000011U /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP 0x00000002U /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD 0x00000012U /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog Mode */
#define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode */
#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_IT_RISING 0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING 0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING 0x10120000U /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING 0x10220000U /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
@ -156,11 +156,11 @@ typedef enum
/** @defgroup GPIO_speed_define GPIO speed define
* @brief GPIO Output Maximum frequency
* @{
*/
#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< IO works at 2 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */
*/
#define GPIO_SPEED_FREQ_LOW 0x00000000U /*!< IO works at 2 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_MEDIUM 0x00000001U /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_HIGH 0x00000002U /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */
/**
* @}
*/
@ -169,9 +169,9 @@ typedef enum
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */
#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */
#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */
#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */
/**
* @}
*/
@ -280,7 +280,7 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00U)
#define IS_GPIO_PIN(PIN) ((((PIN) & GPIO_PIN_MASK ) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
((MODE) == GPIO_MODE_OUTPUT_OD) ||\

86
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_gpio_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_gpio_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -69,104 +69,104 @@
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */
#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */
#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
/**
* @brief AF 4 selection
*/
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
/**
* @brief AF 7 selection
*/
#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
/**
* @brief AF 8 selection
*/
#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */
#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */
#define GPIO_AF9_CAN2 ((uint8_t)0x09U) /* CAN2 Alternate Function mapping */
#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */
#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */
#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */
#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
/**
* @brief AF 10 selection
*/
#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */
#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */
#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */
#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */
/**
* @brief AF 11 selection
*/
#if defined(STM32F207xx) || defined(STM32F217xx)
#define GPIO_AF11_ETH ((uint8_t)0x0BU) /* ETHERNET Alternate Function mapping */
#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
#endif /* STM32F207xx || STM32F217xx */
/**
* @brief AF 12 selection
*/
#define GPIO_AF12_FSMC ((uint8_t)0xCU) /* FSMC Alternate Function mapping */
#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */
#define GPIO_AF12_SDIO ((uint8_t)0xCU) /* SDIO Alternate Function mapping */
#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FSMC Alternate Function mapping */
#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */
#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */
/**
* @brief AF 13 selection
*/
#if defined(STM32F207xx) || defined(STM32F217xx)
#define GPIO_AF13_DCMI ((uint8_t)0x0DU) /* DCMI Alternate Function mapping */
#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
#endif /* STM32F207xx || STM32F217xx */
/**
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
/**
* @}
@ -264,7 +264,7 @@
((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO) || \
((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT))
#endif /* STM32F207xx || STM32F217xx */
/**
* @}
*/

16
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_hash.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_hash.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral:
@ -68,7 +68,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -1228,7 +1228,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu
}
/* Read the message digest */
HASH_GetDigest(pOutBuffer, 16U);
HASH_GetDigest(pOutBuffer, 16);
/* Change HASH peripheral state */
hhash->State = HAL_HASH_STATE_READY;
@ -1281,7 +1281,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI
hhash->hdmain->XferErrorCallback = HASH_DMAError;
/* Enable the DMA In DMA Stream */
HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4U ? (Size+3U)/4U:Size/4U));
/* Enable DMA requests */
HASH->CR |= (HASH_CR_DMAE);
@ -1642,7 +1642,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
}
}
/* Read the message digest */
HASH_GetDigest(pOutBuffer, 20U);
HASH_GetDigest(pOutBuffer, 20);
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_READY;
@ -1730,7 +1730,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
hhash->hdmain->XferErrorCallback = HASH_DMAError;
/* Enable the DMA In DMA Stream */
HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4U ? (hhash->Init.KeySize+3U)/4U:hhash->Init.KeySize/4U));
/* Enable DMA requests */
HASH->CR |= (HASH_CR_DMAE);
@ -1797,7 +1797,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI
hhash->hdmain->XferErrorCallback = HASH_DMAError;
/* Enable the DMA In DMA Stream */
HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4U ? (hhash->Init.KeySize+3U)/4U:hhash->Init.KeySize/4U));
/* Enable DMA requests */
HASH->CR |= (HASH_CR_DMAE);

14
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_hash.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_hash.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -157,7 +157,7 @@ typedef struct
/** @defgroup HASH_Exported_Constants_Group1 HASH Algorithm Selection
* @{
*/
#define HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000U) /*!< HASH function is SHA1 */
#define HASH_ALGOSELECTION_SHA1 0x00000000U /*!< HASH function is SHA1 */
#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
/**
* @}
@ -166,7 +166,7 @@ typedef struct
/** @defgroup HASH_Exported_Constants_Group2 HASH Algorithm Mode
* @{
*/
#define HASH_ALGOMODE_HASH ((uint32_t)0x00000000U) /*!< Algorithm is HASH */
#define HASH_ALGOMODE_HASH 0x00000000U /*!< Algorithm is HASH */
#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
/**
* @}
@ -175,7 +175,7 @@ typedef struct
/** @defgroup HASH_Data_Type HASH Data Type
* @{
*/
#define HASH_DATATYPE_32B ((uint32_t)0x0000U) /*!< 32-bit data. No swapping */
#define HASH_DATATYPE_32B 0x00000000U /*!< 32-bit data. No swapping */
#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
@ -187,7 +187,7 @@ typedef struct
* @brief HASH HMAC Long key used only for HMAC mode
* @{
*/
#define HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000U) /*!< HMAC Key is <= 64 bytes */
#define HASH_HMAC_KEYTYPE_SHORTKEY 0x00000000U /*!< HMAC Key is <= 64 bytes */
#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */
/**
* @}

57
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_hcd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_hcd.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief HCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -44,7 +44,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -197,8 +197,8 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
hhcd->hc[ch_num].max_packet = mps;
hhcd->hc[ch_num].ch_num = ch_num;
hhcd->hc[ch_num].ep_type = ep_type;
hhcd->hc[ch_num].ep_num = epnum & 0x7FU;
hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80U) == 0x80U);
hhcd->hc[ch_num].ep_num = epnum & 0x7F;
hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);
hhcd->hc[ch_num].speed = speed;
/* reset to 0 */
hhcd->hc[ch_num].toggle_out = 0;
@ -373,15 +373,15 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
switch(ep_type)
{
case EP_TYPE_CTRL:
if((token == 1U) && (direction == 0U)) /*send data */
if((token == 1) && (direction == 0)) /*send data */
{
if ( length == 0U )
if (length == 0)
{ /* For Status OUT stage, Length==0, Status Out PID = 1 */
hhcd->hc[ch_num].toggle_out = 1U;
hhcd->hc[ch_num].toggle_out = 1;
}
/* Set the Data Toggle bit as per the Flag */
if ( hhcd->hc[ch_num].toggle_out == 0U)
if (hhcd->hc[ch_num].toggle_out == 0)
{ /* Put the PID 0 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
@ -409,10 +409,10 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
break;
case EP_TYPE_BULK:
if(direction == 0U)
if(direction == 0)
{
/* Set the Data Toggle bit as per the Flag */
if ( hhcd->hc[ch_num].toggle_out == 0U)
if ( hhcd->hc[ch_num].toggle_out == 0)
{ /* Put the PID 0 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
@ -427,7 +427,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
}
else
{
if( hhcd->hc[ch_num].toggle_in == 0U)
if( hhcd->hc[ch_num].toggle_in == 0)
{
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
@ -439,10 +439,10 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
break;
case EP_TYPE_INTR:
if(direction == 0U)
if(direction == 0)
{
/* Set the Data Toggle bit as per the Flag */
if ( hhcd->hc[ch_num].toggle_out == 0U)
if ( hhcd->hc[ch_num].toggle_out == 0)
{ /* Put the PID 0 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
@ -453,7 +453,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
}
else
{
if( hhcd->hc[ch_num].toggle_in == 0U)
if( hhcd->hc[ch_num].toggle_in == 0)
{
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
@ -471,7 +471,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
hhcd->hc[ch_num].xfer_buff = pbuff;
hhcd->hc[ch_num].xfer_len = length;
hhcd->hc[ch_num].urb_state = URB_IDLE;
hhcd->hc[ch_num].urb_state = URB_IDLE;
hhcd->hc[ch_num].xfer_count = 0U;
hhcd->hc[ch_num].ch_num = ch_num;
hhcd->hc[ch_num].state = HC_IDLE;
@ -634,9 +634,9 @@ __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
* URB_IDLE/
* URB_DONE/
* URB_NOTREADY/
* URB_NYET/
* URB_ERROR/
* URB_STALL/
* URB_NYET/
* URB_ERROR/
* URB_STALL/
* @retval None
*/
__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
@ -957,7 +957,12 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
__HAL_HCD_UNMASK_HALT_HC_INT(chnum);
USB_HC_Halt(hhcd->Instance, chnum);
}
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
/* Clear the NAK flag before re-enabling the channel for new IN request */
hhcd->hc[chnum].state = HC_NAK;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
{
/* re-activate the channel */
@ -966,8 +971,6 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(chnum)->HCCHAR = tmpreg;
}
hhcd->hc[chnum].state = HC_NAK;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
}
}
@ -992,7 +995,7 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
if( hhcd->hc[chnum].do_ping == 1U)
if(hhcd->hc[chnum].do_ping == 1U)
{
hhcd->hc[chnum].state = HC_NYET;
__HAL_HCD_UNMASK_HALT_HC_INT(chnum);
@ -1124,7 +1127,7 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint8_t channelnum = 0U;
uint8_t channelnum = 0;
uint32_t pktsts;
uint32_t pktcnt;
uint32_t temp = 0U;
@ -1155,7 +1158,7 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(channelnum)->HCCHAR = tmpreg;
hhcd->hc[channelnum].toggle_in ^= 1U;
hhcd->hc[channelnum].toggle_in ^= 1;
}
}
break;
@ -1207,7 +1210,7 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
{
if(hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
{
if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17U))
{
USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ );
}
@ -1220,7 +1223,7 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
{
if(hhcd->Init.speed == HCD_SPEED_FULL)
{
USBx_HOST->HFIR = (uint32_t)60000U;
USBx_HOST->HFIR = 60000U;
}
}

12
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_hcd.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_hcd.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of HCD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -87,7 +87,7 @@ typedef struct
{
HCD_TypeDef *Instance; /*!< Register base address */
HCD_InitTypeDef Init; /*!< HCD required parameters */
HCD_HCTypeDef hc[15]; /*!< Host channels parameters */
HCD_HCTypeDef hc[15U]; /*!< Host channels parameters */
HAL_LockTypeDef Lock; /*!< HCD peripheral status */
__IO HCD_StateTypeDef State; /*!< HCD communication state */
void *pData; /*!< Pointer Stack Handler */
@ -109,7 +109,7 @@ typedef struct
* @{
*/
#define HCD_SPEED_HIGH 0U
#define HCD_SPEED_LOW 2U
#define HCD_SPEED_LOW 2U
#define HCD_SPEED_FULL 3U
/**
* @}
@ -181,7 +181,7 @@ void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
* @{
*/
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
uint8_t pipe,
uint8_t ch_num,
uint8_t direction,
uint8_t ep_type,
uint8_t token,

80
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_i2c.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_i2c.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
@ -204,7 +204,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -250,9 +250,9 @@
/** @addtogroup I2C_Private_Define
* @{
*/
#define I2C_TIMEOUT_FLAG ((uint32_t)35U) /*!< Timeout 35 ms */
#define I2C_TIMEOUT_BUSY_FLAG ((uint32_t)25U) /*!< Timeout 25 ms */
#define I2C_NO_OPTION_FRAME ((uint32_t)0xFFFF0000U) /*!< XferOptions default value */
#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */
#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */
#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */
/* Private define for @ref PreviousState usage */
#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */
@ -655,7 +655,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
hi2c->XferCount--;
hi2c->XferSize--;
if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
{
/* Write data to DR */
hi2c->Instance->DR = (*hi2c->pBuffPtr++);
@ -1023,7 +1023,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
hi2c->XferCount--;
hi2c->XferSize--;
if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
{
/* Write data to DR */
hi2c->Instance->DR = (*hi2c->pBuffPtr++);
@ -1076,7 +1076,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -1139,7 +1139,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
hi2c->XferSize--;
hi2c->XferCount--;
if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
{
/* Read data from DR */
(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
@ -1420,7 +1420,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
/* Generate Start */
hi2c->Instance->CR1 |= I2C_CR1_START;
}
else if(Prev_State == I2C_STATE_MASTER_BUSY_RX)
else
{
/* Generate ReStart */
hi2c->Instance->CR1 |= I2C_CR1_START;
@ -1564,7 +1564,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -1644,7 +1644,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -1727,7 +1727,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
if(hi2c->State == HAL_I2C_STATE_LISTEN)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -1793,7 +1793,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u
if(hi2c->State == HAL_I2C_STATE_LISTEN)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -2159,6 +2159,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
*/
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(DevAddress);
/* Abort Master transfer during Receive or Transmit process */
if(hi2c->Mode == HAL_I2C_MODE_MASTER)
{
@ -2209,7 +2212,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -2306,7 +2309,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -2653,7 +2656,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
hi2c->XferCount--;
}
/* Two bytes */
else if(Size == 2U)
else if(hi2c->XferSize == 2U)
{
/* Wait until BTF flag is set */
if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
@ -3804,7 +3807,7 @@ static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
{
if(hi2c->Mode == HAL_I2C_MODE_MEM)
{
if(hi2c->EventCount == 0)
if(hi2c->EventCount == 0U)
{
/* If Memory address size is 8Bit */
if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
@ -3812,7 +3815,7 @@ static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
/* Send Memory Address */
hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
hi2c->EventCount += 2;
hi2c->EventCount += 2U;
}
/* If Memory address size is 16Bit */
else
@ -3823,14 +3826,14 @@ static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
hi2c->EventCount++;
}
}
else if(hi2c->EventCount == 1)
else if(hi2c->EventCount == 1U)
{
/* Send LSB of Memory Address */
hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
hi2c->EventCount++;
}
else if(hi2c->EventCount == 2)
else if(hi2c->EventCount == 2U)
{
if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
@ -3941,7 +3944,7 @@ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
{
/* Disable Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
/* Enable Pos */
hi2c->Instance->CR1 |= I2C_CR1_POS;
@ -3952,7 +3955,7 @@ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
{
/* Disable Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
if(hi2c->XferOptions == I2C_NEXT_FRAME)
{
/* Enable Pos */
@ -3969,6 +3972,7 @@ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
if(hi2c->Mode == HAL_I2C_MODE_MEM)
{
@ -4016,19 +4020,15 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
{
/* Disable Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME))
{
/* Generate Start */
/* Generate ReStart */
hi2c->Instance->CR1 |= I2C_CR1_START;
}
tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
}
else
{
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
/* Generate Stop */
hi2c->Instance->CR1 |= I2C_CR1_STOP;
}
@ -5164,18 +5164,22 @@ static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
static void I2C_DMAError(DMA_HandleTypeDef *hdma)
{
I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
/* Ignore DMA FIFO error */
if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
{
/* Disable Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
/* Disable Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
hi2c->XferCount = 0U;
hi2c->XferCount = 0U;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
HAL_I2C_ErrorCallback(hi2c);
HAL_I2C_ErrorCallback(hi2c);
}
}
/**

106
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_i2c.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_i2c.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -214,13 +214,13 @@ typedef struct
* @brief I2C Error Code
* @{
*/
#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001U) /*!< BERR error */
#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002U) /*!< ARLO error */
#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004U) /*!< AF error */
#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008U) /*!< OVR error */
#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout Error */
#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */
#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */
#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */
#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */
#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */
/**
* @}
*/
@ -228,7 +228,7 @@ typedef struct
/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
* @{
*/
#define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000U)
#define I2C_DUTYCYCLE_2 0x00000000U
#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
/**
* @}
@ -237,8 +237,8 @@ typedef struct
/** @defgroup I2C_addressing_mode I2C addressing mode
* @{
*/
#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000U)
#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000U))
#define I2C_ADDRESSINGMODE_7BIT 0x00004000U
#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U)
/**
* @}
*/
@ -246,7 +246,7 @@ typedef struct
/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
* @{
*/
#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U)
#define I2C_DUALADDRESS_DISABLE 0x00000000U
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
/**
* @}
@ -255,7 +255,7 @@ typedef struct
/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
* @{
*/
#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U)
#define I2C_GENERALCALL_DISABLE 0x00000000U
#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
/**
* @}
@ -264,7 +264,7 @@ typedef struct
/** @defgroup I2C_nostretch_mode I2C nostretch mode
* @{
*/
#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U)
#define I2C_NOSTRETCH_DISABLE 0x00000000U
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
@ -273,8 +273,8 @@ typedef struct
/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
* @{
*/
#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U)
#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010U)
#define I2C_MEMADD_SIZE_8BIT 0x00000001U
#define I2C_MEMADD_SIZE_16BIT 0x00000010U
/**
* @}
*/
@ -282,8 +282,8 @@ typedef struct
/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
* @{
*/
#define I2C_DIRECTION_RECEIVE ((uint32_t)0x00000000U)
#define I2C_DIRECTION_TRANSMIT ((uint32_t)0x00000001U)
#define I2C_DIRECTION_RECEIVE 0x00000000U
#define I2C_DIRECTION_TRANSMIT 0x00000001U
/**
* @}
*/
@ -291,10 +291,10 @@ typedef struct
/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
* @{
*/
#define I2C_FIRST_FRAME ((uint32_t)0x00000001U)
#define I2C_NEXT_FRAME ((uint32_t)0x00000002U)
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)0x00000004U)
#define I2C_LAST_FRAME ((uint32_t)0x00000008U)
#define I2C_FIRST_FRAME 0x00000001U
#define I2C_NEXT_FRAME 0x00000002U
#define I2C_FIRST_AND_LAST_FRAME 0x00000004U
#define I2C_LAST_FRAME 0x00000008U
/**
* @}
*/
@ -313,27 +313,27 @@ typedef struct
/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
#define I2C_FLAG_SMBALERT ((uint32_t)0x00018000U)
#define I2C_FLAG_TIMEOUT ((uint32_t)0x00014000U)
#define I2C_FLAG_PECERR ((uint32_t)0x00011000U)
#define I2C_FLAG_OVR ((uint32_t)0x00010800U)
#define I2C_FLAG_AF ((uint32_t)0x00010400U)
#define I2C_FLAG_ARLO ((uint32_t)0x00010200U)
#define I2C_FLAG_BERR ((uint32_t)0x00010100U)
#define I2C_FLAG_TXE ((uint32_t)0x00010080U)
#define I2C_FLAG_RXNE ((uint32_t)0x00010040U)
#define I2C_FLAG_STOPF ((uint32_t)0x00010010U)
#define I2C_FLAG_ADD10 ((uint32_t)0x00010008U)
#define I2C_FLAG_BTF ((uint32_t)0x00010004U)
#define I2C_FLAG_ADDR ((uint32_t)0x00010002U)
#define I2C_FLAG_SB ((uint32_t)0x00010001U)
#define I2C_FLAG_DUALF ((uint32_t)0x00100080U)
#define I2C_FLAG_SMBHOST ((uint32_t)0x00100040U)
#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00100020U)
#define I2C_FLAG_GENCALL ((uint32_t)0x00100010U)
#define I2C_FLAG_TRA ((uint32_t)0x00100004U)
#define I2C_FLAG_BUSY ((uint32_t)0x00100002U)
#define I2C_FLAG_MSL ((uint32_t)0x00100001U)
#define I2C_FLAG_SMBALERT 0x00018000U
#define I2C_FLAG_TIMEOUT 0x00014000U
#define I2C_FLAG_PECERR 0x00011000U
#define I2C_FLAG_OVR 0x00010800U
#define I2C_FLAG_AF 0x00010400U
#define I2C_FLAG_ARLO 0x00010200U
#define I2C_FLAG_BERR 0x00010100U
#define I2C_FLAG_TXE 0x00010080U
#define I2C_FLAG_RXNE 0x00010040U
#define I2C_FLAG_STOPF 0x00010010U
#define I2C_FLAG_ADD10 0x00010008U
#define I2C_FLAG_BTF 0x00010004U
#define I2C_FLAG_ADDR 0x00010002U
#define I2C_FLAG_SB 0x00010001U
#define I2C_FLAG_DUALF 0x00100080U
#define I2C_FLAG_SMBHOST 0x00100040U
#define I2C_FLAG_SMBDEFAULT 0x00100020U
#define I2C_FLAG_GENCALL 0x00100010U
#define I2C_FLAG_TRA 0x00100004U
#define I2C_FLAG_BUSY 0x00100002U
#define I2C_FLAG_MSL 0x00100001U
/**
* @}
*/
@ -563,7 +563,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{
*/
#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU)
#define I2C_FLAG_MASK 0x0000FFFFU
/**
* @}
*/
@ -584,12 +584,12 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0xF0U))))
#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0xF1U))))
#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7U) | (uint16_t)0xF0)))
#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7U) | (uint16_t)0xF1)))
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
* @{
@ -607,8 +607,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U))
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U)
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \

64
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_i2s.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_i2s.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
@ -109,7 +109,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -323,7 +323,7 @@ __weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
tmp = tmp / 10U;
/* Check the parity of the divider */
i2sodd = (uint32_t)(tmp & (uint32_t)1U);
i2sodd = (uint32_t)(tmp & 1U);
/* Compute the i2sdiv prescaler */
i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
@ -475,7 +475,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tmp1 = 0U;
if((pData == NULL ) || (Size == 0U))
if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@ -486,8 +486,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
{
hi2s->TxXferSize = Size*2U;
hi2s->TxXferCount = Size*2U;
hi2s->TxXferSize = Size*2;
hi2s->TxXferCount = Size*2;
}
else
{
@ -507,7 +507,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
__HAL_I2S_ENABLE(hi2s);
}
while(hi2s->TxXferCount > 0U)
while(hi2s->TxXferCount > 0)
{
hi2s->Instance->DR = (*pData++);
hi2s->TxXferCount--;
@ -561,7 +561,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tmp1 = 0U;
if((pData == NULL ) || (Size == 0U))
if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@ -572,8 +572,8 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
{
hi2s->RxXferSize = Size*2U;
hi2s->RxXferCount = Size*2U;
hi2s->RxXferSize = Size*2;
hi2s->RxXferCount = Size*2;
}
else
{
@ -601,7 +601,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
}
/* Receive data */
while(hi2s->RxXferCount > 0U)
while(hi2s->RxXferCount > 0)
{
/* Wait until RXNE flag is set */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
@ -645,7 +645,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
uint32_t tmp1 = 0U;
if(hi2s->State == HAL_I2S_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -655,8 +655,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
{
hi2s->TxXferSize = Size*2U;
hi2s->TxXferCount = Size*2U;
hi2s->TxXferSize = Size*2;
hi2s->TxXferCount = Size*2;
}
else
{
@ -712,7 +712,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
uint32_t tmp1 = 0U;
if(hi2s->State == HAL_I2S_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -722,8 +722,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
{
hi2s->RxXferSize = Size*2U;
hi2s->RxXferCount = Size*2U;
hi2s->RxXferSize = Size*2;
hi2s->RxXferCount = Size*2;
}
else
{
@ -777,7 +777,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
uint32_t *tmp;
uint32_t tmp1 = 0U;
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -789,8 +789,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
{
hi2s->TxXferSize = Size*2U;
hi2s->TxXferCount = Size*2U;
hi2s->TxXferSize = Size*2;
hi2s->TxXferCount = Size*2;
}
else
{
@ -861,7 +861,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
uint32_t *tmp;
uint32_t tmp1 = 0U;
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -872,8 +872,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
{
hi2s->RxXferSize = Size*2U;
hi2s->RxXferCount = Size*2U;
hi2s->RxXferSize = Size*2;
hi2s->RxXferCount = Size*2;
}
else
{
@ -1247,14 +1247,14 @@ static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
{
hi2s->TxXferCount = 0U;
hi2s->TxXferCount = 0;
/* Disable Tx DMA Request */
hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
{
if(hi2s->RxXferCount == 0U)
if(hi2s->RxXferCount == 0)
{
hi2s->State = HAL_I2S_STATE_READY;
}
@ -1294,10 +1294,10 @@ static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
{
/* Disable Rx DMA Request */
hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
hi2s->RxXferCount = 0U;
hi2s->RxXferCount = 0;
if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
{
if(hi2s->TxXferCount == 0U)
if(hi2s->TxXferCount == 0)
{
hi2s->State = HAL_I2S_STATE_READY;
}
@ -1333,8 +1333,8 @@ static void I2S_DMAError(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
hi2s->TxXferCount = 0U;
hi2s->RxXferCount = 0U;
hi2s->TxXferCount = 0;
hi2s->RxXferCount = 0;
hi2s->State= HAL_I2S_STATE_READY;
@ -1360,7 +1360,7 @@ static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
hi2s->TxXferCount--;
if(hi2s->TxXferCount == 0U)
if(hi2s->TxXferCount == 0)
{
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
@ -1412,7 +1412,7 @@ static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
}
if(hi2s->RxXferCount == 0U)
if(hi2s->RxXferCount == 0)
{
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE | I2S_IT_ERR);

80
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_i2s.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_i2s.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -148,13 +148,13 @@ typedef struct
* @brief I2S Error Code
* @{
*/
#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000001U) /*!< I2S Underrun error */
#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002U) /*!< I2S Overrun error */
#define HAL_I2SEX_ERROR_UDR ((uint32_t)0x00000004U) /*!< I2S extended Underrun error */
#define HAL_I2SEX_ERROR_OVR ((uint32_t)0x00000008U) /*!< I2S extended Overrun error */
#define HAL_I2S_ERROR_FRE ((uint32_t)0x00000010U) /*!< I2S Frame format error */
#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000020U) /*!< DMA transfer error */
#define HAL_I2S_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_I2S_ERROR_UDR 0x00000001U /*!< I2S Underrun error */
#define HAL_I2S_ERROR_OVR 0x00000002U /*!< I2S Overrun error */
#define HAL_I2SEX_ERROR_UDR 0x00000004U /*!< I2S extended Underrun error */
#define HAL_I2SEX_ERROR_OVR 0x00000008U /*!< I2S extended Overrun error */
#define HAL_I2S_ERROR_FRE 0x00000010U /*!< I2S Frame format error */
#define HAL_I2S_ERROR_DMA 0x00000020U /*!< DMA transfer error */
/**
* @}
*/
@ -162,8 +162,8 @@ typedef struct
/** @defgroup I2S_Clock_Source I2S Clock Source
* @{
*/
#define I2S_CLOCK_PLL ((uint32_t)0x00000000U)
#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001U)
#define I2S_CLOCK_PLL 0x00000000U
#define I2S_CLOCK_EXTERNAL 0x00000001U
/**
* @}
*/
@ -171,10 +171,10 @@ typedef struct
/** @defgroup I2S_Mode I2S Mode
* @{
*/
#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U)
#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100U)
#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200U)
#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300U)
#define I2S_MODE_SLAVE_TX 0x00000000U
#define I2S_MODE_SLAVE_RX 0x00000100U
#define I2S_MODE_MASTER_TX 0x00000200U
#define I2S_MODE_MASTER_RX 0x00000300U
/**
* @}
*/
@ -182,11 +182,11 @@ typedef struct
/** @defgroup I2S_Standard I2S Standard
* @{
*/
#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U)
#define I2S_STANDARD_MSB ((uint32_t)0x00000010U)
#define I2S_STANDARD_LSB ((uint32_t)0x00000020U)
#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030U)
#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0U)
#define I2S_STANDARD_PHILIPS 0x00000000U
#define I2S_STANDARD_MSB 0x00000010U
#define I2S_STANDARD_LSB 0x00000020U
#define I2S_STANDARD_PCM_SHORT 0x00000030U
#define I2S_STANDARD_PCM_LONG 0x000000B0U
/**
* @}
*/
@ -194,10 +194,10 @@ typedef struct
/** @defgroup I2S_Data_Format I2S Data Format
* @{
*/
#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000U)
#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001U)
#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003U)
#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005U)
#define I2S_DATAFORMAT_16B 0x00000000U
#define I2S_DATAFORMAT_16B_EXTENDED 0x00000001U
#define I2S_DATAFORMAT_24B 0x00000003U
#define I2S_DATAFORMAT_32B 0x00000005U
/**
* @}
*/
@ -206,7 +206,7 @@ typedef struct
* @{
*/
#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000U)
#define I2S_MCLKOUTPUT_DISABLE 0x00000000U
/**
* @}
*/
@ -214,16 +214,16 @@ typedef struct
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
* @{
*/
#define I2S_AUDIOFREQ_192K ((uint32_t)192000U)
#define I2S_AUDIOFREQ_96K ((uint32_t)96000U)
#define I2S_AUDIOFREQ_48K ((uint32_t)48000U)
#define I2S_AUDIOFREQ_44K ((uint32_t)44100U)
#define I2S_AUDIOFREQ_32K ((uint32_t)32000U)
#define I2S_AUDIOFREQ_22K ((uint32_t)22050U)
#define I2S_AUDIOFREQ_16K ((uint32_t)16000U)
#define I2S_AUDIOFREQ_11K ((uint32_t)11025U)
#define I2S_AUDIOFREQ_8K ((uint32_t)8000U)
#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2U)
#define I2S_AUDIOFREQ_192K 192000U
#define I2S_AUDIOFREQ_96K 96000U
#define I2S_AUDIOFREQ_48K 48000U
#define I2S_AUDIOFREQ_44K 44100U
#define I2S_AUDIOFREQ_32K 32000U
#define I2S_AUDIOFREQ_22K 22050U
#define I2S_AUDIOFREQ_16K 16000U
#define I2S_AUDIOFREQ_11K 11025U
#define I2S_AUDIOFREQ_8K 8000U
#define I2S_AUDIOFREQ_DEFAULT 2U
/**
* @}
*/
@ -231,7 +231,7 @@ typedef struct
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
* @{
*/
#define I2S_CPOL_LOW ((uint32_t)0x00000000U)
#define I2S_CPOL_LOW 0x00000000U
#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
/**
* @}
@ -423,12 +423,12 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
*/
#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
((CLOCK) == I2S_CLOCK_PLL))
#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
((MODE) == I2S_MODE_SLAVE_RX) || \
((MODE) == I2S_MODE_MASTER_TX) || \
((MODE) == I2S_MODE_MASTER_RX))
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
((STANDARD) == I2S_STANDARD_MSB) || \
((STANDARD) == I2S_STANDARD_LSB) || \
@ -442,7 +442,7 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
((FREQ) <= I2S_AUDIOFREQ_192K)) || \
((FREQ) == I2S_AUDIOFREQ_DEFAULT))

657
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_irda.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_irda.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA SIR ENDEC block (IrDA):
@ -90,14 +90,15 @@
(+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag
(+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt
(+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt
[..]
(@) You can refer to the IRDA HAL driver header file for more useful macros
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -162,6 +163,10 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart,uint32_t Timeout);
static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
@ -404,7 +409,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
/* Check that a Tx process is not already ongoing */
if(hirda->gState == HAL_IRDA_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -420,7 +425,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
hirda->TxXferSize = Size;
hirda->TxXferCount = Size;
while(hirda->TxXferCount > 0U)
while(hirda->TxXferCount > 0)
{
hirda->TxXferCount--;
if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
@ -430,14 +435,14 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
return HAL_TIMEOUT;
}
tmp = (uint16_t*) pData;
hirda->Instance->DR = (*tmp & (uint16_t)0x01FFU);
hirda->Instance->DR = (*tmp & (uint16_t)0x01FF);
if(hirda->Init.Parity == IRDA_PARITY_NONE)
{
pData +=2U;
pData +=2;
}
else
{
pData +=1U;
pData +=1;
}
}
else
@ -446,7 +451,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
{
return HAL_TIMEOUT;
}
hirda->Instance->DR = (*pData++ & (uint8_t)0xFFU);
hirda->Instance->DR = (*pData++ & (uint8_t)0xFF);
}
}
@ -486,7 +491,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
/* Check that a Rx process is not already ongoing */
if(hirda->RxState == HAL_IRDA_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -503,7 +508,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
hirda->RxXferSize = Size;
hirda->RxXferCount = Size;
/* Check the remain data to be received */
while(hirda->RxXferCount > 0U)
while(hirda->RxXferCount > 0)
{
hirda->RxXferCount--;
if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
@ -515,13 +520,13 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
tmp = (uint16_t*) pData ;
if(hirda->Init.Parity == IRDA_PARITY_NONE)
{
*tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FFU);
pData +=2U;
*tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FF);
pData +=2;
}
else
{
*tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x00FFU);
pData +=1U;
*tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x00FF);
pData +=1;
}
}
else
@ -532,11 +537,11 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
}
if(hirda->Init.Parity == IRDA_PARITY_NONE)
{
*pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x00FFU);
*pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x00FF);
}
else
{
*pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x007FU);
*pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x007F);
}
}
}
@ -568,7 +573,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData
/* Check that a Tx process is not already ongoing */
if(hirda->gState == HAL_IRDA_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -608,7 +613,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
/* Check that a Rx process is not already ongoing */
if(hirda->RxState == HAL_IRDA_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -624,13 +629,13 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
/* Process Unlocked */
__HAL_UNLOCK(hirda);
/* Enable the IRDA Parity Error and Data Register not empty Interrupts */
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
/* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
return HAL_OK;
}
else
@ -654,7 +659,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
/* Check that a Tx process is not already ongoing */
if(hirda->gState == HAL_IRDA_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -718,7 +723,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
/* Check that a Rx process is not already ongoing */
if(hirda->RxState == HAL_IRDA_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -746,6 +751,9 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
/* Enable the DMA Stream */
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t*)tmp, Size);
/* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
__HAL_IRDA_CLEAR_OREFLAG(hirda);
/* Process Unlocked */
__HAL_UNLOCK(hirda);
@ -885,6 +893,408 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
return HAL_OK;
}
/**
* @brief Abort ongoing transfers (blocking mode).
* @param hirda IRDA handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Disable the IRDA DMA Tx request if enabled */
if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
if(hirda->hdmatx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmatx->XferAbortCallback = NULL;
HAL_DMA_Abort(hirda->hdmatx);
}
}
/* Disable the IRDA DMA Rx request if enabled */
if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
if(hirda->hdmarx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = NULL;
HAL_DMA_Abort(hirda->hdmarx);
}
}
/* Reset Tx and Rx transfer counters */
hirda->TxXferCount = 0x00U;
hirda->RxXferCount = 0x00U;
/* Reset ErrorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
/* Restore hirda->RxState and hirda->gState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
hirda->gState = HAL_IRDA_STATE_READY;
return HAL_OK;
}
/**
* @brief Abort ongoing Transmit transfer (blocking mode).
* @param hirda IRDA handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Disable the IRDA DMA Tx request if enabled */
if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
if(hirda->hdmatx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmatx->XferAbortCallback = NULL;
HAL_DMA_Abort(hirda->hdmatx);
}
}
/* Reset Tx transfer counter */
hirda->TxXferCount = 0x00U;
/* Restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
return HAL_OK;
}
/**
* @brief Abort ongoing Receive transfer (blocking mode).
* @param hirda IRDA handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Disable the IRDA DMA Rx request if enabled */
if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
if(hirda->hdmarx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = NULL;
HAL_DMA_Abort(hirda->hdmarx);
}
}
/* Reset Rx transfer counter */
hirda->RxXferCount = 0x00U;
/* Restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
return HAL_OK;
}
/**
* @brief Abort ongoing transfers (Interrupt mode).
* @param hirda IRDA handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
{
uint32_t AbortCplt = 1U;
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
if(hirda->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
Otherwise, set it to NULL */
if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
}
else
{
hirda->hdmatx->XferAbortCallback = NULL;
}
}
/* DMA Rx Handle is valid */
if(hirda->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
Otherwise, set it to NULL */
if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
}
else
{
hirda->hdmarx->XferAbortCallback = NULL;
}
}
/* Disable the IRDA DMA Tx request if enabled */
if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at IRDA level */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
if(hirda->hdmatx != NULL)
{
/* IRDA Tx DMA Abort callback has already been initialised :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA TX */
if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
{
hirda->hdmatx->XferAbortCallback = NULL;
}
else
{
AbortCplt = 0x00U;
}
}
}
/* Disable the IRDA DMA Rx request if enabled */
if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
if(hirda->hdmarx != NULL)
{
/* IRDA Rx DMA Abort callback has already been initialised :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA RX */
if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
{
hirda->hdmarx->XferAbortCallback = NULL;
AbortCplt = 0x01U;
}
else
{
AbortCplt = 0x00U;
}
}
}
/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
if(AbortCplt == 0x01U)
{
/* Reset Tx and Rx transfer counters */
hirda->TxXferCount = 0x00U;
hirda->RxXferCount = 0x00U;
/* Reset ErrorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
/* Restore hirda->gState and hirda->RxState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
hirda->RxState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
HAL_IRDA_AbortCpltCallback(hirda);
}
return HAL_OK;
}
/**
* @brief Abort ongoing Transmit transfer (Interrupt mode).
* @param hirda IRDA handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Disable the IRDA DMA Tx request if enabled */
if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
if(hirda->hdmatx != NULL)
{
/* Set the IRDA DMA Abort callback :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
/* Abort DMA TX */
if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
{
/* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
}
}
else
{
/* Reset Tx transfer counter */
hirda->TxXferCount = 0x00U;
/* Restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
HAL_IRDA_AbortTransmitCpltCallback(hirda);
}
}
else
{
/* Reset Tx transfer counter */
hirda->TxXferCount = 0x00U;
/* Restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
HAL_IRDA_AbortTransmitCpltCallback(hirda);
}
return HAL_OK;
}
/**
* @brief Abort ongoing Receive transfer (Interrupt mode).
* @param hirda IRDA handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Disable the IRDA DMA Rx request if enabled */
if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
if(hirda->hdmarx != NULL)
{
/* Set the IRDA DMA Abort callback :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
/* Abort DMA RX */
if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
{
/* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
}
}
else
{
/* Reset Rx transfer counter */
hirda->RxXferCount = 0x00U;
/* Restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
HAL_IRDA_AbortReceiveCpltCallback(hirda);
}
}
else
{
/* Reset Rx transfer counter */
hirda->RxXferCount = 0x00U;
/* Restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
HAL_IRDA_AbortReceiveCpltCallback(hirda);
}
return HAL_OK;
}
/**
* @brief This function handles IRDA interrupt request.
* @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
@ -1050,12 +1460,130 @@ static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hirda->RxXferCount = 0x00U;
hirda->TxXferCount = 0x00U;
hirda->RxXferCount = 0x00;
hirda->TxXferCount = 0x00;
HAL_IRDA_ErrorCallback(hirda);
}
/**
* @brief DMA IRDA Tx communication abort callback, when initiated by user
* (To be called at end of DMA Tx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Rx DMA Handle.
* @param hdma DMA handle.
* @retval None
*/
static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hirda->hdmatx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
if(hirda->hdmarx != NULL)
{
if(hirda->hdmarx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
hirda->TxXferCount = 0x00U;
hirda->RxXferCount = 0x00U;
/* Reset ErrorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
/* Restore hirda->gState and hirda->RxState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
hirda->RxState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
HAL_IRDA_AbortCpltCallback(hirda);
}
/**
* @brief DMA IRDA Rx communication abort callback, when initiated by user
* (To be called at end of DMA Rx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Tx DMA Handle.
* @param hdma DMA handle.
* @retval None
*/
static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hirda->hdmarx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
if(hirda->hdmatx != NULL)
{
if(hirda->hdmatx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
hirda->TxXferCount = 0x00U;
hirda->RxXferCount = 0x00U;
/* Reset ErrorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
/* Restore hirda->gState and hirda->RxState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
hirda->RxState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
HAL_IRDA_AbortCpltCallback(hirda);
}
/**
* @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to
* HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
* (This callback is executed at end of DMA Tx Abort procedure following user abort request,
* and leads to user Tx Abort Complete callback execution).
* @param hdma DMA handle.
* @retval None
*/
static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hirda->TxXferCount = 0x00U;
/* Restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
HAL_IRDA_AbortTransmitCpltCallback(hirda);
}
/**
* @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to
* HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
* (This callback is executed at end of DMA Rx Abort procedure following user abort request,
* and leads to user Rx Abort Complete callback execution).
* @param hdma DMA handle.
* @retval None
*/
static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hirda->RxXferCount = 0x00U;
/* Restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
HAL_IRDA_AbortReceiveCpltCallback(hirda);
}
/**
* @brief Tx Transfer complete callbacks.
* @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
@ -1131,6 +1659,51 @@ __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
*/
}
/**
* @brief IRDA Abort Complete callback.
* @param hirda IRDA handle.
* @retval None
*/
__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
*/
}
/**
* @brief IRDA Abort Transmit Complete callback.
* @param hirda IRDA handle.
* @retval None
*/
__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
*/
}
/**
* @brief IRDA Abort ReceiveComplete callback.
* @param hirda IRDA handle.
* @retval None
*/
__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
*/
}
/**
* @}
*/
@ -1193,7 +1766,7 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
/* DMA Normal mode */
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
{
hirda->TxXferCount = 0U;
hirda->TxXferCount = 0;
/* Disable the DMA transfer for transmit request by setting the DMAT bit
in the IRDA CR3 register */
@ -1233,7 +1806,7 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
/* DMA Normal mode */
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
{
hirda->RxXferCount = 0U;
hirda->RxXferCount = 0;
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
@ -1276,7 +1849,7 @@ static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
{
hirda->TxXferCount = 0U;
hirda->TxXferCount = 0;
IRDA_EndTxTransfer(hirda);
}
@ -1284,7 +1857,7 @@ static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
{
hirda->RxXferCount = 0U;
hirda->RxXferCount = 0;
IRDA_EndRxTransfer(hirda);
}
@ -1346,22 +1919,22 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
{
tmp = (uint16_t*) hirda->pTxBuffPtr;
hirda->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FFU);
hirda->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
if(hirda->Init.Parity == IRDA_PARITY_NONE)
{
hirda->pTxBuffPtr += 2U;
hirda->pTxBuffPtr += 2;
}
else
{
hirda->pTxBuffPtr += 1U;
hirda->pTxBuffPtr += 1;
}
}
else
{
hirda->Instance->DR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FFU);
hirda->Instance->DR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FF);
}
if(--hirda->TxXferCount == 0U)
if(--hirda->TxXferCount == 0)
{
/* Disable the IRDA Transmit Data Register Empty Interrupt */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
@ -1420,28 +1993,28 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
tmp = (uint16_t*) hirda->pRxBuffPtr;
if(hirda->Init.Parity == IRDA_PARITY_NONE)
{
*tmp = (uint16_t)(uhdata & (uint16_t)0x01FFU);
hirda->pRxBuffPtr += 2U;
*tmp = (uint16_t)(uhdata & (uint16_t)0x01FF);
hirda->pRxBuffPtr += 2;
}
else
{
*tmp = (uint16_t)(uhdata & (uint16_t)0x00FFU);
hirda->pRxBuffPtr += 1U;
*tmp = (uint16_t)(uhdata & (uint16_t)0x00FF);
hirda->pRxBuffPtr += 1;
}
}
else
{
if(hirda->Init.Parity == IRDA_PARITY_NONE)
{
*hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x00FFU);
*hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x00FF);
}
else
{
*hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x007FU);
*hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x007F);
}
}
if(--hirda->RxXferCount == 0U)
if(--hirda->RxXferCount == 0)
{
/* Disable the IRDA Data Register not empty Interrupt */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);

52
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_irda.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_irda.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -196,12 +196,12 @@ typedef struct
* @brief IRDA Error Code
* @{
*/
#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#define HAL_IRDA_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_IRDA_ERROR_PE 0x00000001U /*!< Parity error */
#define HAL_IRDA_ERROR_NE 0x00000002U /*!< Noise error */
#define HAL_IRDA_ERROR_FE 0x00000004U /*!< Frame error */
#define HAL_IRDA_ERROR_ORE 0x00000008U /*!< Overrun error */
#define HAL_IRDA_ERROR_DMA 0x00000010U /*!< DMA transfer error */
/**
* @}
*/
@ -209,7 +209,7 @@ typedef struct
/** @defgroup IRDA_Word_Length IRDA Word Length
* @{
*/
#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000U)
#define IRDA_WORDLENGTH_8B 0x00000000U
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
/**
* @}
@ -218,7 +218,7 @@ typedef struct
/** @defgroup IRDA_Parity IRDA Parity
* @{
*/
#define IRDA_PARITY_NONE ((uint32_t)0x00000000U)
#define IRDA_PARITY_NONE 0x00000000U
#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
@ -239,7 +239,7 @@ typedef struct
* @{
*/
#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000U)
#define IRDA_POWERMODE_NORMAL 0x00000000U
/**
* @}
*/
@ -249,14 +249,14 @@ typedef struct
* - 0xXXXX : Flag mask in the SR register
* @{
*/
#define IRDA_FLAG_TXE ((uint32_t)0x00000080U)
#define IRDA_FLAG_TC ((uint32_t)0x00000040U)
#define IRDA_FLAG_RXNE ((uint32_t)0x00000020U)
#define IRDA_FLAG_IDLE ((uint32_t)0x00000010U)
#define IRDA_FLAG_ORE ((uint32_t)0x00000008U)
#define IRDA_FLAG_NE ((uint32_t)0x00000004U)
#define IRDA_FLAG_FE ((uint32_t)0x00000002U)
#define IRDA_FLAG_PE ((uint32_t)0x00000001U)
#define IRDA_FLAG_TXE 0x00000080U
#define IRDA_FLAG_TC 0x00000040U
#define IRDA_FLAG_RXNE 0x00000020U
#define IRDA_FLAG_IDLE 0x00000010U
#define IRDA_FLAG_ORE 0x00000008U
#define IRDA_FLAG_NE 0x00000004U
#define IRDA_FLAG_FE 0x00000002U
#define IRDA_FLAG_PE 0x00000001U
/**
* @}
*/
@ -496,6 +496,13 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
@ -503,6 +510,9 @@ void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
/**
* @}
*/
@ -550,7 +560,7 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
((PARITY) == IRDA_PARITY_EVEN) || \
((PARITY) == IRDA_PARITY_ODD))
#define IS_IRDA_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3U) == 0x00U) && ((MODE) != (uint32_t)0x00000000U))
#define IS_IRDA_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U))
#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
((MODE) == IRDA_POWERMODE_NORMAL))
#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)

10
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_iwdg.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_iwdg.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
@ -74,7 +74,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -137,7 +137,7 @@
*/
/** @addtogroup IWDG_Exported_Functions_Group1
* @brief Initialization and Start functions.
* @brief Initialization and Start functions.
*
@verbatim
===============================================================================
@ -210,7 +210,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
*/
/** @addtogroup IWDG_Exported_Functions_Group2
* @brief IO operation functions
* @brief IO operation functions
*
@verbatim
===============================================================================

10
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_iwdg.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_iwdg.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -110,10 +110,6 @@ typedef struct
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
* @{

2593
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_mmc.c Normal file
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716
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_mmc.h Normal file
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@ -0,0 +1,716 @@
/**
******************************************************************************
* @file stm32f2xx_hal_mmc.h
* @author MCD Application Team
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of MMC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F2xx_HAL_MMC_H
#define __STM32F2xx_HAL_MMC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f2xx_ll_sdmmc.h"
/** @addtogroup STM32F2xx_HAL_Driver
* @{
*/
/** @defgroup MMC MMC
* @brief MMC HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup MMC_Exported_Types MMC Exported Types
* @{
*/
/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
* @{
*/
typedef enum
{
HAL_MMC_STATE_RESET = 0x00000000U, /*!< MMC not yet initialized or disabled */
HAL_MMC_STATE_READY = 0x00000001U, /*!< MMC initialized and ready for use */
HAL_MMC_STATE_TIMEOUT = 0x00000002U, /*!< MMC Timeout state */
HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */
HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */
HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */
HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfert State */
HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */
}HAL_MMC_StateTypeDef;
/**
* @}
*/
/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
* @{
*/
typedef enum
{
HAL_MMC_CARD_READY = 0x00000001U, /*!< Card state is ready */
HAL_MMC_CARD_IDENTIFICATION = 0x00000002U, /*!< Card is in identification state */
HAL_MMC_CARD_STANDBY = 0x00000003U, /*!< Card is in standby state */
HAL_MMC_CARD_TRANSFER = 0x00000004U, /*!< Card is in transfer state */
HAL_MMC_CARD_SENDING = 0x00000005U, /*!< Card is sending an operation */
HAL_MMC_CARD_RECEIVING = 0x00000006U, /*!< Card is receiving operation information */
HAL_MMC_CARD_PROGRAMMING = 0x00000007U, /*!< Card is in programming state */
HAL_MMC_CARD_DISCONNECTED = 0x00000008U, /*!< Card is disconnected */
HAL_MMC_CARD_ERROR = 0x000000FFU /*!< Card response Error */
}HAL_MMC_CardStateTypeDef;
/**
* @}
*/
/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
* @{
*/
#define MMC_InitTypeDef SDIO_InitTypeDef
#define MMC_TypeDef SDIO_TypeDef
/**
* @brief MMC Card Information Structure definition
*/
typedef struct
{
uint32_t CardType; /*!< Specifies the card Type */
uint32_t Class; /*!< Specifies the class of the card class */
uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
uint32_t BlockSize; /*!< Specifies one block size in bytes */
uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
}HAL_MMC_CardInfoTypeDef;
/**
* @brief MMC handle Structure definition
*/
typedef struct
{
MMC_TypeDef *Instance; /*!< MMC registers base address */
MMC_InitTypeDef Init; /*!< MMC required parameters */
HAL_LockTypeDef Lock; /*!< MMC locking object */
uint32_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
uint32_t TxXferSize; /*!< MMC Tx Transfer size */
uint32_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
uint32_t RxXferSize; /*!< MMC Rx Transfer size */
__IO uint32_t Context; /*!< MMC transfer context */
__IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
__IO uint32_t ErrorCode; /*!< MMC Card Error codes */
DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */
DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */
HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
uint32_t CSD[4]; /*!< MMC card specific data table */
uint32_t CID[4]; /*!< MMC card identification number table */
}MMC_HandleTypeDef;
/**
* @}
*/
/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
* @{
*/
typedef struct
{
__IO uint8_t CSDStruct; /*!< CSD structure */
__IO uint8_t SysSpecVersion; /*!< System specification version */
__IO uint8_t Reserved1; /*!< Reserved */
__IO uint8_t TAAC; /*!< Data read access time 1 */
__IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
__IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
__IO uint16_t CardComdClasses; /*!< Card command classes */
__IO uint8_t RdBlockLen; /*!< Max. read data block length */
__IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
__IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
__IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
__IO uint8_t DSRImpl; /*!< DSR implemented */
__IO uint8_t Reserved2; /*!< Reserved */
__IO uint32_t DeviceSize; /*!< Device Size */
__IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
__IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
__IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
__IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
__IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
__IO uint8_t EraseGrSize; /*!< Erase group size */
__IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
__IO uint8_t WrProtectGrSize; /*!< Write protect group size */
__IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
__IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
__IO uint8_t WrSpeedFact; /*!< Write speed factor */
__IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
__IO uint8_t Reserved3; /*!< Reserved */
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
__IO uint8_t FileFormatGrouop; /*!< File format group */
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
__IO uint8_t FileFormat; /*!< File format */
__IO uint8_t ECC; /*!< ECC code */
__IO uint8_t CSD_CRC; /*!< CSD CRC */
__IO uint8_t Reserved4; /*!< Always 1 */
}HAL_MMC_CardCSDTypeDef;
/**
* @}
*/
/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
* @{
*/
typedef struct
{
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */
__IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
__IO uint32_t ProdName1; /*!< Product Name part1 */
__IO uint8_t ProdName2; /*!< Product Name part2 */
__IO uint8_t ProdRev; /*!< Product Revision */
__IO uint32_t ProdSN; /*!< Product Serial Number */
__IO uint8_t Reserved1; /*!< Reserved1 */
__IO uint16_t ManufactDate; /*!< Manufacturing Date */
__IO uint8_t CID_CRC; /*!< CID CRC */
__IO uint8_t Reserved2; /*!< Always 1 */
}HAL_MMC_CardCIDTypeDef;
/**
* @}
*/
/** @defgroup MMC_Exported_Types_Group6 MMC Card Status returned by ACMD13
* @{
*/
typedef struct
{
__IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
__IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
__IO uint16_t CardType; /*!< Carries information about card type */
__IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
__IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
__IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
__IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
__IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
__IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
__IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
}HAL_MMC_CardStatusTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup MMC_Exported_Constants Exported Constants
* @{
*/
#define BLOCKSIZE 512U /*!< Block size is 512 bytes */
#define CAPACITY 0x400000U /*!< Log Block Nuumber for 2 G bytes Cards */
/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
* @{
*/
#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
number of transferred bytes does not match the block length */
#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
command or if there was an attempt to access a locked card */
#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
of erase sequence command was received */
#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
/**
* @}
*/
/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration structure
* @{
*/
#define MMC_CONTEXT_NONE 0x00000000U /*!< None */
#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
/**
* @}
*/
/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
* @{
*/
/**
* @brief
*/
#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */
#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */
#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */
#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */
#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
/**
* @}
*/
/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
* @{
*/
#define MMC_HIGH_VOLTAGE_CARD 0x00000000U
#define MMC_DUAL_VOLTAGE_CARD 0x00000001U
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup MMC_Exported_macros MMC Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
/**
* @brief Enable the MMC device.
* @retval None
*/
#define __HAL_MMC_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
/**
* @brief Disable the MMC device.
* @retval None
*/
#define __HAL_MMC_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
/**
* @brief Enable the SDMMC DMA transfer.
* @retval None
*/
#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
/**
* @brief Disable the SDMMC DMA transfer.
* @retval None
*/
#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
/**
* @brief Enable the MMC device interrupt.
* @param __HANDLE__: MMC Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* @retval None
*/
#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Disable the MMC device interrupt.
* @param __HANDLE__: MMC Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* @retval None
*/
#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Check whether the specified MMC flag is set or not.
* @param __HANDLE__: MMC Handle
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
* @arg SDIO_FLAG_TXACT: Data transmit in progress
* @arg SDIO_FLAG_RXACT: Data receive in progress
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
* @retval The new state of MMC FLAG (SET or RESET).
*/
#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Clear the MMC's pending flags.
* @param __HANDLE__: MMC Handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
* @retval None
*/
#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Check whether the specified MMC interrupt has occurred or not.
* @param __HANDLE__: MMC Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* @retval The new state of MMC IT (SET or RESET).
*/
#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Clear the MMC's interrupt pending bits.
* @param __HANDLE__: MMC Handle
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* @retval None
*/
#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup MMC_Exported_Functions MMC Exported Functions
* @{
*/
/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
/**
* @}
*/
/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
/* Non-Blocking mode: IT */
HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
/* Callback in non blocking modes (DMA) */
void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
/**
* @}
*/
/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
/**
* @}
*/
/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
* @{
*/
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
/**
* @}
*/
/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
* @{
*/
HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
/**
* @}
*/
/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management
* @{
*/
HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup MMC_Private_Types MMC Private Types
* @{
*/
/**
* @}
*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup MMC_Private_Defines MMC Private Defines
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup MMC_Private_Variables MMC Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup MMC_Private_Constants MMC Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup MMC_Private_Macros MMC Private Macros
* @{
*/
/**
* @}
*/
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup MMC_Private_Functions MMC Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F2xx_HAL_MMC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_nand.c
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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_nand.h
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@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_nand.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -93,11 +93,11 @@ typedef struct
*/
typedef struct
{
uint16_t Page; /*!< NAND memory Page address */
uint16_t Page; /*!< NAND memory Page address */
uint16_t Zone; /*!< NAND memory Zone address */
uint16_t Plane; /*!< NAND memory Plane address */
uint16_t Block; /*!< NAND memory Block address */
uint16_t Block; /*!< NAND memory Block address */
}NAND_AddressTypeDef;
@ -106,31 +106,43 @@ typedef struct
*/
typedef struct
{
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
for 8 bits adressing or words for 16 bits addressing */
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
for 8 bits adressing or words for 16 bits addressing */
uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
uint32_t BlockSize; /*!< NAND memory block size number of pages */
uint32_t BlockNbr; /*!< NAND memory number of total blocks */
uint32_t PlaneNbr; /*!< NAND memory number of planes */
uint32_t BlockNbr; /*!< NAND memory number of blocks */
uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */
uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
}NAND_InfoTypeDef;
FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
parameter is mandatory for some NAND parts after the read
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
Example: Toshiba THTH58BYG3S0HBAI6.
This parameter could be ENABLE or DISABLE
Please check the Read Mode sequnece in the NAND device datasheet */
}NAND_DeviceConfigTypeDef;
/**
* @brief NAND handle Structure definition
*/
typedef struct
{
FSMC_NAND_TypeDef *Instance; /*!< Register base address */
FSMC_NAND_TypeDef *Instance; /*!< Register base address */
FSMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
FSMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
HAL_LockTypeDef Lock; /*!< NAND locking object */
HAL_LockTypeDef Lock; /*!< NAND locking object */
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
}NAND_HandleTypeDef;
/**
* @}
@ -164,10 +176,12 @@ typedef struct
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
/**
* @}
@ -178,13 +192,20 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
*/
/* IO operation functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
@ -225,34 +246,34 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
/** @defgroup NAND_Private_Constants NAND Private Constants
* @{
*/
#define NAND_DEVICE1 ((uint32_t)0x70000000U)
#define NAND_DEVICE2 ((uint32_t)0x80000000U)
#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
#define NAND_DEVICE1 0x70000000U
#define NAND_DEVICE2 0x80000000U
#define NAND_WRITE_TIMEOUT 0x01000000U
#define CMD_AREA ((uint32_t)(1U<<16U)) /* A16 = CLE high */
#define ADDR_AREA ((uint32_t)(1U<<17U)) /* A17 = ALE high */
#define NAND_CMD_AREA_A ((uint8_t)0x00U)
#define NAND_CMD_AREA_B ((uint8_t)0x01U)
#define NAND_CMD_AREA_C ((uint8_t)0x50U)
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
#define NAND_CMD_AREA_A ((uint8_t)0x00)
#define NAND_CMD_AREA_B ((uint8_t)0x01)
#define NAND_CMD_AREA_C ((uint8_t)0x50)
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
#define NAND_CMD_WRITE0 ((uint8_t)0x80U)
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
#define NAND_CMD_ERASE0 ((uint8_t)0x60U)
#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)
#define NAND_CMD_READID ((uint8_t)0x90U)
#define NAND_CMD_STATUS ((uint8_t)0x70U)
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
#define NAND_CMD_RESET ((uint8_t)0xFFU)
#define NAND_CMD_WRITE0 ((uint8_t)0x80)
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
#define NAND_CMD_ERASE0 ((uint8_t)0x60)
#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
#define NAND_CMD_READID ((uint8_t)0x90)
#define NAND_CMD_STATUS ((uint8_t)0x70)
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
#define NAND_CMD_RESET ((uint8_t)0xFF)
/* NAND memory status */
#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
#define NAND_BUSY ((uint32_t)0x00000000U)
#define NAND_ERROR ((uint32_t)0x00000001U)
#define NAND_READY ((uint32_t)0x00000040U)
#define NAND_VALID_ADDRESS 0x00000100U
#define NAND_INVALID_ADDRESS 0x00000200U
#define NAND_TIMEOUT_ERROR 0x00000400U
#define NAND_BUSY 0x00000000U
#define NAND_ERROR 0x00000001U
#define NAND_READY 0x00000040U
/**
* @}
*/
@ -269,7 +290,14 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
* @retval NAND Raw address value
*/
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
(((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
(((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
/**
* @brief NAND memory Column address computation.
* @param __HANDLE__: NAND handle.
* @retval NAND Raw address value
*/
#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
/**
* @brief NAND memory address cycling.
@ -281,8 +309,12 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16U) /* 3rd addressing cycle */
#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24U) /* 4th addressing cycle */
/**
* @}
* @brief NAND memory Columns cycling.
* @param __ADDRESS__: NAND memory address.
* @retval NAND Column address cycling value.
*/
#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
/**

57
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_nor.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_nor.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.
@ -55,7 +55,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -103,33 +103,33 @@
*/
/* Constants to define address to set to write a command */
#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555U
#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055U
#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AAU
#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555U
#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555U
#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AAU
#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555U
#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
/* Constants to define data to program a command */
#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0U
#define NOR_CMD_DATA_FIRST (uint16_t)0x00AAU
#define NOR_CMD_DATA_SECOND (uint16_t)0x0055U
#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090U
#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0U
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080U
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AAU
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055U
#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010U
#define NOR_CMD_DATA_CFI (uint16_t)0x0098U
#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
#define NOR_CMD_DATA_SECOND (uint16_t)0x0055
#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
#define NOR_CMD_DATA_CFI (uint16_t)0x0098
#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25U
#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29U
#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30U
#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
/* Mask on NOR STATUS REGISTER */
#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020U
#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040U
#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
/**
* @}
@ -659,7 +659,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
/* Write Buffer Load Command */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uwBufferSize - 1));
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uwBufferSize - 1U));
/* Load Data into NOR Buffer */
while(p_currentaddress <= p_endaddress)
@ -754,7 +754,10 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
{
uint32_t deviceaddress = 0U;
/* Prevent unused argument(s) compilation warning */
UNUSED(Address);
/* Process Locked */
__HAL_LOCK(hnor);

36
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_nor.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_nor.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -224,29 +224,29 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
* @{
*/
/* NOR device IDs addresses */
#define MC_ADDRESS ((uint16_t)0x0000U)
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
#define MC_ADDRESS ((uint16_t)0x0000)
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
/* NOR CFI IDs addresses */
#define CFI1_ADDRESS ((uint16_t)0x61U)
#define CFI2_ADDRESS ((uint16_t)0x62U)
#define CFI3_ADDRESS ((uint16_t)0x63U)
#define CFI4_ADDRESS ((uint16_t)0x64U)
#define CFI1_ADDRESS ((uint16_t)0x61)
#define CFI2_ADDRESS ((uint16_t)0x62)
#define CFI3_ADDRESS ((uint16_t)0x63)
#define CFI4_ADDRESS ((uint16_t)0x64)
/* NOR operation wait timeout */
#define NOR_TMEOUT ((uint16_t)0xFFFFU)
#define NOR_TMEOUT ((uint16_t)0xFFFF)
/* NOR memory data width */
#define NOR_MEMORY_8B ((uint8_t)0x0U)
#define NOR_MEMORY_16B ((uint8_t)0x1U)
#define NOR_MEMORY_8B ((uint8_t)0x00)
#define NOR_MEMORY_16B ((uint8_t)0x01)
/* NOR memory device read/write start address */
#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)
#define NOR_MEMORY_ADRESS1 0x60000000U
#define NOR_MEMORY_ADRESS2 0x64000000U
#define NOR_MEMORY_ADRESS3 0x68000000U
#define NOR_MEMORY_ADRESS4 0x6C000000U
/**
* @}
*/

52
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_pccard.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_pccard.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief PCCARD HAL module driver.
* This file provides a generic firmware to drive PCCARD memories mounted
* as external device.
@ -50,7 +50,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -95,13 +95,13 @@
/** @defgroup PCCARD_Private_Defines PCCARD Private Defines
* @{
*/
#define PCCARD_TIMEOUT_READ_ID (uint32_t)0x0000FFFFU
#define PCCARD_TIMEOUT_READ_WRITE_SECTOR (uint32_t)0x0000FFFFU
#define PCCARD_TIMEOUT_ERASE_SECTOR (uint32_t)0x00000400U
#define PCCARD_TIMEOUT_STATUS (uint32_t)0x01000000U
#define PCCARD_TIMEOUT_READ_ID 0x0000FFFFU
#define PCCARD_TIMEOUT_READ_WRITE_SECTOR 0x0000FFFFU
#define PCCARD_TIMEOUT_ERASE_SECTOR 0x00000400U
#define PCCARD_TIMEOUT_STATUS 0x01000000U
#define PCCARD_STATUS_OK (uint8_t)0x58U
#define PCCARD_STATUS_WRITE_OK (uint8_t)0x50U
#define PCCARD_STATUS_OK (uint8_t)0x58
#define PCCARD_STATUS_WRITE_OK (uint8_t)0x50
/**
* @}
*/
@ -262,7 +262,7 @@ __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
{
uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U;
uint8_t status = 0U;
uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@ -282,7 +282,7 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp
*pStatus = PCCARD_READY;
/* Send the Identify Command */
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = 0xECECU;
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = 0xECEC;
/* Read PCCARD IDs and timeout treatment */
do
@ -327,7 +327,7 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
{
uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
uint8_t status = 0U;
uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@ -345,16 +345,16 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t
*pStatus = PCCARD_READY;
/* Set the parameters to write a sector */
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00U;
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100U ) | ((uint16_t)SectorAddress);
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0U;
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress);
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0;
do
{
/* wait till the Status = 0x80 */
status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}while((status == 0x80U) && timeout);
}while((status == 0x80) && timeout);
if(timeout == 0U)
{
@ -403,7 +403,7 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
{
uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
uint8_t status = 0U;
uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@ -421,9 +421,9 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_
*pStatus = PCCARD_READY;
/* Set the parameters to write a sector */
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00U;
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100U ) | ((uint16_t)SectorAddress);
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0x30A0U;
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress);
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0x30A0;
do
{
@ -476,7 +476,7 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
{
uint32_t timeout = PCCARD_TIMEOUT_ERASE_SECTOR;
uint8_t status = 0U;
uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
@ -494,11 +494,11 @@ HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16
*pStatus = PCCARD_READY;
/* Set the parameters to write a sector */
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_LOW) = 0x00U;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = 0x00U;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_LOW) = 0x00;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = 0x00;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_NUMBER) = SectorAddress;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = 0x01U;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CARD_HEAD) = 0xA0U;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = 0x01;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CARD_HEAD) = 0xA0;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = ATA_ERASE_SECTOR_CMD;
/* wait till the PCCARD is ready */
@ -551,7 +551,7 @@ HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
/* Check the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
*(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION ) = 0x01U;
*(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION ) = 0x01;
/* Check the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_READY;

6
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_pccard.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_pccard.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of PCCARD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

83
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_pcd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_pcd.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -45,7 +45,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -174,12 +174,12 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->IN_ep[i].tx_fifo_num = i;
/* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
hpcd->IN_ep[i].maxpacket = 0U;
hpcd->IN_ep[i].maxpacket = 0U;
hpcd->IN_ep[i].xfer_buff = 0U;
hpcd->IN_ep[i].xfer_len = 0U;
}
for (i = 0U; i < 15U ; i++)
for (i = 0U; i < 15U; i++)
{
hpcd->OUT_ep[i].is_in = 0U;
hpcd->OUT_ep[i].num = i;
@ -315,7 +315,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
uint32_t i = 0U, ep_intr = 0U, epint = 0U, epnum = 0U;
uint32_t fifoemptymsk = 0U, temp = 0U;
USB_OTG_EPTypeDef *ep;
uint32_t hclk = 168000000U;
uint32_t hclk = 120000000U;
/* ensure that we are in device mode */
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
@ -379,7 +379,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
}
epnum++;
ep_intr >>= 1;
ep_intr >>= 1U;
}
}
@ -472,9 +472,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
{
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
USB_FlushTxFifo(hpcd->Instance , 0U );
USB_FlushTxFifo(hpcd->Instance , 0x10U);
for (i = 0U; i < hpcd->Init.dev_endpoints ; i++)
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
{
USBx_INEP(i)->DIEPINT = 0xFFU;
USBx_OUTEP(i)->DOEPINT = 0xFFU;
@ -893,17 +893,17 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
HAL_StatusTypeDef ret = HAL_OK;
USB_OTG_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
if ((ep_addr & 0x80) == 0x80)
{
ep = &hpcd->IN_ep[ep_addr & 0x7FU];
ep = &hpcd->IN_ep[ep_addr & 0x7F];
}
else
{
ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
ep = &hpcd->OUT_ep[ep_addr & 0x7F];
}
ep->num = ep_addr & 0x7FU;
ep->num = ep_addr & 0x7F;
ep->is_in = (0x80U & ep_addr) != 0U;
ep->is_in = (0x80 & ep_addr) != 0;
ep->maxpacket = ep_mps;
ep->type = ep_type;
if (ep->is_in)
@ -934,17 +934,17 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
USB_OTG_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
if ((ep_addr & 0x80) == 0x80)
{
ep = &hpcd->IN_ep[ep_addr & 0x7FU];
ep = &hpcd->IN_ep[ep_addr & 0x7F];
}
else
{
ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
ep = &hpcd->OUT_ep[ep_addr & 0x7F];
}
ep->num = ep_addr & 0x7FU;
ep->num = ep_addr & 0x7F;
ep->is_in = (0x80U & ep_addr) != 0U;
ep->is_in = (0x80 & ep_addr) != 0;
__HAL_LOCK(hpcd);
USB_DeactivateEndpoint(hpcd->Instance , ep);
@ -965,14 +965,14 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
{
USB_OTG_EPTypeDef *ep;
ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
ep = &hpcd->OUT_ep[ep_addr & 0x7F];
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_count = 0U;
ep->is_in = 0U;
ep->num = ep_addr & 0x7FU;
ep->num = ep_addr & 0x7F;
if (hpcd->Init.dma_enable == 1U)
{
@ -980,8 +980,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
}
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
if ((ep_addr & 0x7FU) == 0U )
if ((ep_addr & 0x7F) == 0)
{
USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
}
@ -1002,7 +1001,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
*/
uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
return hpcd->OUT_ep[ep_addr & 0x7FU].xfer_count;
return hpcd->OUT_ep[ep_addr & 0xF].xfer_count;
}
/**
* @brief Send an amount of data.
@ -1016,14 +1015,14 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
{
USB_OTG_EPTypeDef *ep;
ep = &hpcd->IN_ep[ep_addr & 0x7FU];
ep = &hpcd->IN_ep[ep_addr & 0x7F];
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_count = 0U;
ep->is_in = 1U;
ep->num = ep_addr & 0x7FU;
ep->num = ep_addr & 0x7F;
if (hpcd->Init.dma_enable == 1U)
{
@ -1031,8 +1030,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
}
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
if ((ep_addr & 0x7FU) == 0U )
if ((ep_addr & 0x7F) == 0)
{
USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
}
@ -1042,7 +1040,6 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
}
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
return HAL_OK;
}
@ -1056,9 +1053,9 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
USB_OTG_EPTypeDef *ep;
if ((0x80U & ep_addr) == 0x80U)
if ((0x80 & ep_addr) == 0x80)
{
ep = &hpcd->IN_ep[ep_addr & 0x7FU];
ep = &hpcd->IN_ep[ep_addr & 0x7F];
}
else
{
@ -1066,13 +1063,13 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
ep->is_stall = 1U;
ep->num = ep_addr & 0x7FU;
ep->is_in = ((ep_addr & 0x80U) == 0x80U);
ep->num = ep_addr & 0x7F;
ep->is_in = ((ep_addr & 0x80) == 0x80);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
USB_EPSetStall(hpcd->Instance , ep);
if((ep_addr & 0x7FU) == 0U)
if((ep_addr & 0x7F) == 0)
{
USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
}
@ -1091,9 +1088,9 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
USB_OTG_EPTypeDef *ep;
if ((0x80U & ep_addr) == 0x80U)
if ((0x80 & ep_addr) == 0x80)
{
ep = &hpcd->IN_ep[ep_addr & 0x7FU];
ep = &hpcd->IN_ep[ep_addr & 0x7F];
}
else
{
@ -1101,8 +1098,8 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
ep->is_stall = 0U;
ep->num = ep_addr & 0x7FU;
ep->is_in = ((ep_addr & 0x80U) == 0x80U);
ep->num = ep_addr & 0x7F;
ep->is_in = ((ep_addr & 0x80) == 0x80);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
USB_EPClearStall(hpcd->Instance , ep);
@ -1121,9 +1118,9 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
if ((ep_addr & 0x80U) == 0x80U)
if ((ep_addr & 0x80) == 0x80)
{
USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7FU);
USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
}
else
{
@ -1231,9 +1228,9 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
len32b = (len + 3U) / 4U;
while ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
ep->xfer_count < ep->xfer_len &&
ep->xfer_len != 0U)
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b) &&
(ep->xfer_count < ep->xfer_len) &&
(ep->xfer_len != 0U))
{
/* Write the FIFO */
len = ep->xfer_len - ep->xfer_count;

46
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_pcd.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_pcd.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -86,8 +86,8 @@ typedef struct
{
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
PCD_EPTypeDef IN_ep[16U]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[16U]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
PCD_EPLockDef EPLock[15];
__IO PCD_StateTypeDef State; /*!< PCD communication state */
@ -150,7 +150,7 @@ typedef struct
*/
#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
@ -160,19 +160,19 @@ typedef struct
~(USB_OTG_PCGCCTL_STOPCLK)
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10U)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U)
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U)
#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U)
#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU)
#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000U) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000U) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U
#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
#define USB_OTG_HS_WAKEUP_EXTI_LINE 0x00100000U /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
#define USB_OTG_FS_WAKEUP_EXTI_LINE 0x00040000U /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
@ -181,8 +181,8 @@ typedef struct
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
}while(0)
}while(0U)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
@ -190,7 +190,7 @@ typedef struct
EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
}while(0)
}while(0U)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
@ -201,17 +201,17 @@ typedef struct
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
}while(0);
}while(0U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
}while(0)
}while(0U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
}while(0)
}while(0U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
/**

14
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_pcd_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_pcd_ex.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -86,7 +86,7 @@
*/
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
{
uint8_t i = 0U;
uint8_t i = 0;
uint32_t Tx_Offset = 0U;
/* TXn min size = 16 words. (n : Transmit FIFO index)
@ -101,20 +101,20 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin
Tx_Offset = hpcd->Instance->GRXFSIZ;
if(fifo == 0U)
if(fifo == 0)
{
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);
}
else
{
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16U;
for (i = 0U; i < (fifo - 1U); i++)
for (i = 0; i < (fifo - 1); i++)
{
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16U);
}
/* Multiply Tx_Size by 2 to get higher performance */
hpcd->Instance->DIEPTXF[fifo - 1U] = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);
hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);
}
return HAL_OK;

6
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_pcd_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_pcd_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

17
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_pwr.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_pwr.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -63,10 +63,10 @@
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
* @{
*/
#define PVD_MODE_IT ((uint32_t)0x00010000U)
#define PVD_MODE_EVT ((uint32_t)0x00020000U)
#define PVD_RISING_EDGE ((uint32_t)0x00000001U)
#define PVD_FALLING_EDGE ((uint32_t)0x00000002U)
#define PVD_MODE_IT 0x00010000U
#define PVD_MODE_EVT 0x00020000U
#define PVD_RISING_EDGE 0x00000001U
#define PVD_FALLING_EDGE 0x00000002U
/**
* @}
*/
@ -376,6 +376,9 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
*/
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(Regulator);
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));

32
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_pwr.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_pwr.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -84,7 +84,7 @@ typedef struct
/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
* @{
*/
#define PWR_WAKEUP_PIN1 ((uint32_t)0x00000100U)
#define PWR_WAKEUP_PIN1 0x00000100U
/**
* @}
*/
@ -108,13 +108,13 @@ typedef struct
/** @defgroup PWR_PVD_Mode PWR PVD Mode
* @{
*/
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */
#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
@ -123,7 +123,7 @@ typedef struct
/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
* @{
*/
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)
#define PWR_MAINREGULATOR_ON 0x00000000U
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
/**
* @}
@ -132,8 +132,8 @@ typedef struct
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{
*/
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
/**
* @}
*/
@ -141,8 +141,8 @@ typedef struct
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
* @{
*/
#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)
#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
/**
* @}
*/

6
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_pwr_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_pwr_ex.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of PWR extension peripheral:
@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_pwr_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_pwr_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

28
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rcc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_rcc.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@ -48,17 +48,15 @@
after the clock enable bit is set on the hardware register
[..]
Possible Workarounds:
(#) Enable the peripheral clock sometimes before the peripheral read/write
register is required.
(#) For AHB peripheral, insert two dummy read to the peripheral register.
(#) For APB peripheral, insert a dummy read to the peripheral register.
Implemented Workaround:
(+) For AHB & APB peripherals, a dummy read to the peripheral register has been
inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -104,7 +102,7 @@
/** @addtogroup RCC_Private_Constants
* @{
*/
#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */
#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */
/* Private macro -------------------------------------------------------------*/
#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
@ -122,11 +120,9 @@
/** @defgroup RCC_Private_Variables RCC Private Variables
* @{
*/
const uint8_t APBAHBPrescTable[16] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
@ -480,7 +476,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@ -736,7 +732,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
@ -830,7 +826,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
/* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U)));
}
}
@ -957,7 +953,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void)
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
}
/**
@ -969,7 +965,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void)
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
}
/**

188
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rcc.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_rcc.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -80,7 +80,7 @@ typedef struct
This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
}RCC_PLLInitTypeDef;
@ -144,11 +144,11 @@ typedef struct
/** @defgroup RCC_Oscillator_Type Oscillator Type
* @{
*/
#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)
#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)
#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)
#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)
#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)
#define RCC_OSCILLATORTYPE_NONE 0x00000000U
#define RCC_OSCILLATORTYPE_HSE 0x00000001U
#define RCC_OSCILLATORTYPE_HSI 0x00000002U
#define RCC_OSCILLATORTYPE_LSE 0x00000004U
#define RCC_OSCILLATORTYPE_LSI 0x00000008U
/**
* @}
*/
@ -156,9 +156,9 @@ typedef struct
/** @defgroup RCC_HSE_Config HSE Config
* @{
*/
#define RCC_HSE_OFF ((uint8_t)0x00U)
#define RCC_HSE_ON ((uint8_t)0x01U)
#define RCC_HSE_BYPASS ((uint8_t)0x05U)
#define RCC_HSE_OFF ((uint8_t)0x00)
#define RCC_HSE_ON ((uint8_t)0x01)
#define RCC_HSE_BYPASS ((uint8_t)0x05)
/**
* @}
*/
@ -166,9 +166,9 @@ typedef struct
/** @defgroup RCC_LSE_Config LSE Config
* @{
*/
#define RCC_LSE_OFF ((uint8_t)0x00U)
#define RCC_LSE_ON ((uint8_t)0x01U)
#define RCC_LSE_BYPASS ((uint8_t)0x05U)
#define RCC_LSE_OFF ((uint8_t)0x00)
#define RCC_LSE_ON ((uint8_t)0x01)
#define RCC_LSE_BYPASS ((uint8_t)0x05)
/**
* @}
*/
@ -176,10 +176,10 @@ typedef struct
/** @defgroup RCC_HSI_Config HSI Config
* @{
*/
#define RCC_HSI_OFF ((uint8_t)0x00U)
#define RCC_HSI_ON ((uint8_t)0x01U)
#define RCC_HSI_OFF ((uint8_t)0x00)
#define RCC_HSI_ON ((uint8_t)0x01)
#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
/**
* @}
*/
@ -187,8 +187,8 @@ typedef struct
/** @defgroup RCC_LSI_Config LSI Config
* @{
*/
#define RCC_LSI_OFF ((uint8_t)0x00U)
#define RCC_LSI_ON ((uint8_t)0x01U)
#define RCC_LSI_OFF ((uint8_t)0x00)
#define RCC_LSI_ON ((uint8_t)0x01)
/**
* @}
*/
@ -196,9 +196,9 @@ typedef struct
/** @defgroup RCC_PLL_Config PLL Config
* @{
*/
#define RCC_PLL_NONE ((uint8_t)0x00U)
#define RCC_PLL_OFF ((uint8_t)0x01U)
#define RCC_PLL_ON ((uint8_t)0x02U)
#define RCC_PLL_NONE ((uint8_t)0x00)
#define RCC_PLL_OFF ((uint8_t)0x01)
#define RCC_PLL_ON ((uint8_t)0x02)
/**
* @}
*/
@ -206,10 +206,10 @@ typedef struct
/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
* @{
*/
#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U)
#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U)
#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U)
#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U)
#define RCC_PLLP_DIV2 0x00000002U
#define RCC_PLLP_DIV4 0x00000004U
#define RCC_PLLP_DIV6 0x00000006U
#define RCC_PLLP_DIV8 0x00000008U
/**
* @}
*/
@ -226,10 +226,10 @@ typedef struct
/** @defgroup RCC_System_Clock_Type System Clock Type
* @{
*/
#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)
#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)
#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)
#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)
#define RCC_CLOCKTYPE_SYSCLK 0x00000001U
#define RCC_CLOCKTYPE_HCLK 0x00000002U
#define RCC_CLOCKTYPE_PCLK1 0x00000004U
#define RCC_CLOCKTYPE_PCLK2 0x00000008U
/**
* @}
*/
@ -285,38 +285,38 @@ typedef struct
/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
* @{
*/
#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)
#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)
#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)
#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)
#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)
#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)
#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)
#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)
#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)
#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)
#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)
#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)
#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)
#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)
#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)
#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)
#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)
#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)
#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)
#define RCC_RTCCLKSOURCE_LSE 0x00000100U
#define RCC_RTCCLKSOURCE_LSI 0x00000200U
#define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U
#define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U
#define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U
#define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U
#define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U
#define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U
#define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U
#define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U
#define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U
#define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U
#define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U
#define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U
#define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U
#define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U
#define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U
#define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U
#define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U
#define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U
#define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U
#define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U
#define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U
#define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U
#define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U
#define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U
#define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U
#define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U
#define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U
#define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U
#define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U
#define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U
/**
* @}
*/
@ -324,8 +324,8 @@ typedef struct
/** @defgroup RCC_MCO_Index MCO Index
* @{
*/
#define RCC_MCO1 ((uint32_t)0x00000000U)
#define RCC_MCO2 ((uint32_t)0x00000001U)
#define RCC_MCO1 0x00000000U
#define RCC_MCO2 0x00000001U
/**
* @}
*/
@ -333,7 +333,7 @@ typedef struct
/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
* @{
*/
#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)
#define RCC_MCO1SOURCE_HSI 0x00000000U
#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
@ -344,7 +344,7 @@ typedef struct
/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
* @{
*/
#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)
#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
@ -355,7 +355,7 @@ typedef struct
/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
* @{
*/
#define RCC_MCODIV_1 ((uint32_t)0x00000000U)
#define RCC_MCODIV_1 0x00000000U
#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
@ -367,13 +367,13 @@ typedef struct
/** @defgroup RCC_Interrupt Interrupts
* @{
*/
#define RCC_IT_LSIRDY ((uint8_t)0x01U)
#define RCC_IT_LSERDY ((uint8_t)0x02U)
#define RCC_IT_HSIRDY ((uint8_t)0x04U)
#define RCC_IT_HSERDY ((uint8_t)0x08U)
#define RCC_IT_PLLRDY ((uint8_t)0x10U)
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20U)
#define RCC_IT_CSS ((uint8_t)0x80U)
#define RCC_IT_LSIRDY ((uint8_t)0x01)
#define RCC_IT_LSERDY ((uint8_t)0x02)
#define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
#define RCC_IT_CSS ((uint8_t)0x80)
/**
* @}
*/
@ -388,23 +388,23 @@ typedef struct
* @{
*/
/* Flags in the CR register */
#define RCC_FLAG_HSIRDY ((uint8_t)0x21U)
#define RCC_FLAG_HSERDY ((uint8_t)0x31U)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39U)
#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
/* Flags in the BDCR register */
#define RCC_FLAG_LSERDY ((uint8_t)0x41U)
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
/* Flags in the CSR register */
#define RCC_FLAG_LSIRDY ((uint8_t)0x61U)
#define RCC_FLAG_BORRST ((uint8_t)0x79U)
#define RCC_FLAG_PINRST ((uint8_t)0x7AU)
#define RCC_FLAG_PORRST ((uint8_t)0x7BU)
#define RCC_FLAG_SFTRST ((uint8_t)0x7CU)
#define RCC_FLAG_IWDGRST ((uint8_t)0x7DU)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7EU)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7FU)
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define RCC_FLAG_BORRST ((uint8_t)0x79)
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
/**
* @}
*/
@ -1939,7 +1939,7 @@ void HAL_RCC_CSSCallback(void);
#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
/* CR register byte 3 (Bits[23:16]) base address */
#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802U)
#define RCC_CR_BYTE2_ADDRESS 0x40023802U
/* CIR register byte 2 (Bits[15:8]) base address */
#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
@ -1950,14 +1950,14 @@ void HAL_RCC_CSSCallback(void);
/* BDCR register base address */
#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U)
#define RCC_DBP_TIMEOUT_VALUE 2U
#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */
#define LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */
#define HSI_TIMEOUT_VALUE 2U /* 2 ms */
#define LSI_TIMEOUT_VALUE 2U /* 2 ms */
#define PLLI2S_TIMEOUT_VALUE ((uint32_t)2U) /* Timeout value fixed to 100 ms */
#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 100 ms */
/**
* @}
*/
@ -2034,7 +2034,7 @@ void HAL_RCC_CSSCallback(void);
#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
#define IS_RCC_PLLQ_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 15U))
#define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \

6
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rcc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_rcc_ex.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Extension RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rcc_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_rcc_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rng.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_rng.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
@ -29,7 +29,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rng.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_rng.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of RNG HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

91
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rtc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_rtc.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
@ -108,7 +108,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -207,7 +207,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
@ -215,7 +215,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
assert_param (IS_RTC_OUTPUT(hrtc->Init.OutPut));
assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
if(hrtc->State == HAL_RTC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@ -223,10 +223,10 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
/* Initialize RTC MSP */
HAL_RTC_MspInit(hrtc);
}
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
@ -234,36 +234,45 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
if(RTC_EnterInitMode(hrtc) != HAL_OK)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
return HAL_ERROR;
}
}
else
{
{
/* Clear RTC_CR FMT, OSEL and POL Bits */
hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
/* Set RTC_CR register */
hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
/* Configure the RTC PRER */
hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
/* Exit Initialization mode */
hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_ERROR;
return HAL_ERROR;
}
hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_READY;
return HAL_OK;
}
}
@ -299,10 +308,10 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
else
{
/* Reset TR, DR and CR registers */
hrtc->Instance->TR = (uint32_t)0x00000000U;
hrtc->Instance->DR = (uint32_t)0x00002101U;
hrtc->Instance->TR = 0x00000000U;
hrtc->Instance->DR = 0x00002101U;
/* Reset All CR bits except CR[2:0] */
hrtc->Instance->CR &= (uint32_t)0x00000007U;
hrtc->Instance->CR &= 0x00000007U;
/* Get tick */
tickstart = HAL_GetTick();
@ -323,15 +332,15 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
}
/* Reset all RTC CR register bits */
hrtc->Instance->CR &= (uint32_t)0x00000000U;
hrtc->Instance->WUTR = (uint32_t)0x0000FFFFU;
hrtc->Instance->PRER = (uint32_t)0x007F00FFU;
hrtc->Instance->CALIBR = (uint32_t)0x00000000U;
hrtc->Instance->ALRMAR = (uint32_t)0x00000000U;
hrtc->Instance->ALRMBR = (uint32_t)0x00000000U;
hrtc->Instance->CR &= 0x00000000U;
hrtc->Instance->WUTR = 0x0000FFFFU;
hrtc->Instance->PRER = 0x007F00FFU;
hrtc->Instance->CALIBR = 0x00000000U;
hrtc->Instance->ALRMAR = 0x00000000U;
hrtc->Instance->ALRMBR = 0x00000000U;
/* Reset ISR register and exit initialization mode */
hrtc->Instance->ISR = (uint32_t)0x00000000U;
hrtc->Instance->ISR = 0x00000000U;
/* Reset Tamper and alternate functions configuration register */
hrtc->Instance->TAFCR = 0x00000000U;
@ -595,9 +604,9 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
hrtc->State = HAL_RTC_STATE_BUSY;
if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
{
sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~0x10) + (uint8_t)0x0A);
}
assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
@ -771,7 +780,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
}
else
{
sAlarm->AlarmTime.TimeFormat = 0x00U;
sAlarm->AlarmTime.TimeFormat = 0x00;
assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
}
assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
@ -804,7 +813,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
}
else
{
sAlarm->AlarmTime.TimeFormat = 0x00U;
sAlarm->AlarmTime.TimeFormat = 0x00;
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
}
@ -948,7 +957,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
}
else
{
sAlarm->AlarmTime.TimeFormat = 0x00U;
sAlarm->AlarmTime.TimeFormat = 0x00;
assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
}
assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
@ -980,7 +989,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
}
else
{
sAlarm->AlarmTime.TimeFormat = 0x00U;
sAlarm->AlarmTime.TimeFormat = 0x00;
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
}
@ -1464,10 +1473,10 @@ uint8_t RTC_ByteToBcd2(uint8_t Value)
{
uint32_t bcdhigh = 0U;
while(Value >= 10U)
while(Value >= 10)
{
bcdhigh++;
Value -= 10U;
Value -= 10;
}
return ((uint8_t)(bcdhigh << 4U) | Value);
@ -1481,8 +1490,8 @@ uint8_t RTC_ByteToBcd2(uint8_t Value)
uint8_t RTC_Bcd2ToByte(uint8_t Value)
{
uint32_t tmp = 0U;
tmp = ((uint8_t)(Value & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U;
return (tmp + (Value & (uint8_t)0x0FU));
tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
return (tmp + (Value & (uint8_t)0x0F));
}
/**

218
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rtc.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_rtc.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -78,22 +78,22 @@ typedef enum
typedef struct
{
uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
This parameter can be a value of @ref RTC_Hour_Formats */
This parameter can be a value of @ref RTC_Hour_Formats */
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FFF */
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FFF */
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
This parameter can be a value of @ref RTC_Output_selection_Definitions */
This parameter can be a value of @ref RTC_Output_selection_Definitions */
uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
}RTC_InitTypeDef;
/**
@ -107,16 +107,16 @@ typedef struct
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
This parameter can be a value of @ref RTC_AM_PM_Definitions */
uint32_t DayLightSaving; /*!< Specifies DayLight Save Operation.
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
in CR register to store the operation.
This parameter can be a value of @ref RTC_StoreOperation_Definitions */
@ -129,16 +129,16 @@ typedef struct
{
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
This parameter can be a value of @ref RTC_WeekDay_Definitions */
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
This parameter can be a value of @ref RTC_Month_Date_Definitions */
uint8_t Date; /*!< Specifies the RTC Date.
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
uint8_t Year; /*!< Specifies the RTC Date Year.
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
}RTC_DateTypeDef;
/**
@ -147,19 +147,19 @@ typedef struct
typedef struct
{
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
uint32_t Alarm; /*!< Specifies the alarm .
This parameter can be a value of @ref RTC_Alarms_Definitions */
This parameter can be a value of @ref RTC_Alarms_Definitions */
}RTC_AlarmTypeDef;
/**
@ -168,13 +168,13 @@ typedef struct
typedef struct
{
RTC_TypeDef *Instance; /*!< Register base address */
RTC_InitTypeDef Init; /*!< RTC required parameters */
HAL_LockTypeDef Lock; /*!< RTC locking object */
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */
}RTC_HandleTypeDef;
/**
@ -189,8 +189,8 @@ typedef struct
/** @defgroup RTC_Hour_Formats RTC Hour Formats
* @{
*/
#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000U)
#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040U)
#define RTC_HOURFORMAT_24 0x00000000U
#define RTC_HOURFORMAT_12 0x00000040U
/**
* @}
*/
@ -198,10 +198,10 @@ typedef struct
/** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions
* @{
*/
#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000U)
#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000U)
#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000U)
#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000U)
#define RTC_OUTPUT_DISABLE 0x00000000U
#define RTC_OUTPUT_ALARMA 0x00200000U
#define RTC_OUTPUT_ALARMB 0x00400000U
#define RTC_OUTPUT_WAKEUP 0x00600000U
/**
* @}
*/
@ -209,8 +209,8 @@ typedef struct
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
* @{
*/
#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000U)
#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000U)
#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U
#define RTC_OUTPUT_POLARITY_LOW 0x00100000U
/**
* @}
*/
@ -218,8 +218,8 @@ typedef struct
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
* @{
*/
#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U)
#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)0x00040000U)
#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U
#define RTC_OUTPUT_TYPE_PUSHPULL 0x00040000U
/**
* @}
*/
@ -227,8 +227,8 @@ typedef struct
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
* @{
*/
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00U)
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40U)
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
/**
* @}
*/
@ -236,9 +236,9 @@ typedef struct
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
* @{
*/
#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000U)
#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000U)
#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000U)
#define RTC_DAYLIGHTSAVING_SUB1H 0x00020000U
#define RTC_DAYLIGHTSAVING_ADD1H 0x00010000U
#define RTC_DAYLIGHTSAVING_NONE 0x00000000U
/**
* @}
*/
@ -246,8 +246,8 @@ typedef struct
/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
* @{
*/
#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000U)
#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000U)
#define RTC_STOREOPERATION_RESET 0x00000000U
#define RTC_STOREOPERATION_SET 0x00040000U
/**
* @}
*/
@ -255,8 +255,8 @@ typedef struct
/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
* @{
*/
#define RTC_FORMAT_BIN ((uint32_t)0x000000000U)
#define RTC_FORMAT_BCD ((uint32_t)0x000000001U)
#define RTC_FORMAT_BIN 0x00000000U
#define RTC_FORMAT_BCD 0x00000001U
/**
* @}
*/
@ -265,18 +265,18 @@ typedef struct
* @{
*/
/* Coded in BCD format */
#define RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define RTC_MONTH_MARCH ((uint8_t)0x03U)
#define RTC_MONTH_APRIL ((uint8_t)0x04U)
#define RTC_MONTH_MAY ((uint8_t)0x05U)
#define RTC_MONTH_JUNE ((uint8_t)0x06U)
#define RTC_MONTH_JULY ((uint8_t)0x07U)
#define RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define RTC_MONTH_DECEMBER ((uint8_t)0x12U)
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define RTC_MONTH_MARCH ((uint8_t)0x03)
#define RTC_MONTH_APRIL ((uint8_t)0x04)
#define RTC_MONTH_MAY ((uint8_t)0x05)
#define RTC_MONTH_JUNE ((uint8_t)0x06)
#define RTC_MONTH_JULY ((uint8_t)0x07)
#define RTC_MONTH_AUGUST ((uint8_t)0x08)
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
/**
* @}
*/
@ -284,13 +284,13 @@ typedef struct
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
* @{
*/
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
/**
* @}
*/
@ -298,8 +298,8 @@ typedef struct
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
* @{
*/
#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U)
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000U)
#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY 0x40000000U
/**
* @}
*/
@ -307,12 +307,12 @@ typedef struct
/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
* @{
*/
#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000U)
#define RTC_ALARMMASK_NONE 0x00000000U
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080U)
#define RTC_ALARMMASK_ALL 0x80808080U
/**
* @}
*/
@ -329,12 +329,12 @@ typedef struct
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
* @{
*/
#define RTC_IT_TS ((uint32_t)0x00008000U)
#define RTC_IT_WUT ((uint32_t)0x00004000U)
#define RTC_IT_ALRB ((uint32_t)0x00002000U)
#define RTC_IT_ALRA ((uint32_t)0x00001000U)
#define RTC_IT_TAMP ((uint32_t)0x00000004U) /* Used only to Enable the Tamper Interrupt */
#define RTC_IT_TAMP1 ((uint32_t)0x00020000U)
#define RTC_IT_TS 0x00008000U
#define RTC_IT_WUT 0x00004000U
#define RTC_IT_ALRB 0x00002000U
#define RTC_IT_ALRA 0x00001000U
#define RTC_IT_TAMP 0x00000004U /* Used only to Enable the Tamper Interrupt */
#define RTC_IT_TAMP1 0x00020000U
/**
* @}
*/
@ -342,18 +342,18 @@ typedef struct
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
* @{
*/
#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000U)
#define RTC_FLAG_TSOVF ((uint32_t)0x00001000U)
#define RTC_FLAG_TSF ((uint32_t)0x00000800U)
#define RTC_FLAG_WUTF ((uint32_t)0x00000400U)
#define RTC_FLAG_ALRBF ((uint32_t)0x00000200U)
#define RTC_FLAG_ALRAF ((uint32_t)0x00000100U)
#define RTC_FLAG_INITF ((uint32_t)0x00000040U)
#define RTC_FLAG_RSF ((uint32_t)0x00000020U)
#define RTC_FLAG_INITS ((uint32_t)0x00000010U)
#define RTC_FLAG_WUTWF ((uint32_t)0x00000004U)
#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002U)
#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001U)
#define RTC_FLAG_TAMP1F 0x00002000U
#define RTC_FLAG_TSOVF 0x00001000U
#define RTC_FLAG_TSF 0x00000800U
#define RTC_FLAG_WUTF 0x00000400U
#define RTC_FLAG_ALRBF 0x00000200U
#define RTC_FLAG_ALRAF 0x00000100U
#define RTC_FLAG_INITF 0x00000040U
#define RTC_FLAG_RSF 0x00000020U
#define RTC_FLAG_INITS 0x00000010U
#define RTC_FLAG_WUTWF 0x00000004U
#define RTC_FLAG_ALRBWF 0x00000002U
#define RTC_FLAG_ALRAWF 0x00000001U
/**
* @}
*/
@ -382,7 +382,7 @@ typedef struct
do{ \
(__HANDLE__)->Instance->WPR = 0xCAU; \
(__HANDLE__)->Instance->WPR = 0x53U; \
} while(0)
} while(0U)
/**
* @brief Enable the write protection for RTC registers.
@ -392,7 +392,7 @@ typedef struct
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
do{ \
(__HANDLE__)->Instance->WPR = 0xFFU; \
} while(0)
} while(0U)
/**
* @brief Enable the RTC ALARMA peripheral.
@ -545,7 +545,7 @@ typedef struct
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();\
__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();\
}while(0)
}while(0U)
/**
* @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
@ -553,7 +553,7 @@ typedef struct
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();\
__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();\
}while(0)
}while(0U)
/**
* @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
@ -652,16 +652,16 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
* @{
*/
/* Masks Definition */
#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7FU)
#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3FU)
#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)
#define RTC_TR_RESERVED_MASK 0x007F7F7FU
#define RTC_DR_RESERVED_MASK 0x00FFFF3FU
#define RTC_INIT_MASK 0xFFFFFFFFU
#define RTC_RSF_MASK 0xFFFFFF5FU
#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F))
#define RTC_TIMEOUT_VALUE 1000
#define RTC_TIMEOUT_VALUE 1000U
#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
/**
@ -686,12 +686,12 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
((POL) == RTC_OUTPUT_POLARITY_LOW))
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0U) && ((HOUR) <= (uint32_t)12U))
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23U)
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FU)
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x1FFFU)
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59U)
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59U)
#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU)
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x1FFFU)
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
@ -700,9 +700,9 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
((OPERATION) == RTC_STOREOPERATION_SET))
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99U)
#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1U) && ((MONTH) <= (uint32_t)12U))
#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1U) && ((DATE) <= (uint32_t)31U))
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
@ -710,7 +710,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \

8
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rtc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_rtc_ex.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extension peripheral:
@ -66,7 +66,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -328,7 +328,7 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe
sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U);
/* Fill the Date structure fields with the read parameters */
sTimeStampDate->Year = 0U;
sTimeStampDate->Year = 0;
sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U);

86
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rtc_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_rtc_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of RTC HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -84,26 +84,26 @@ typedef struct
/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions
* @{
*/
#define RTC_BKP_DR0 ((uint32_t)0x00000000U)
#define RTC_BKP_DR1 ((uint32_t)0x00000001U)
#define RTC_BKP_DR2 ((uint32_t)0x00000002U)
#define RTC_BKP_DR3 ((uint32_t)0x00000003U)
#define RTC_BKP_DR4 ((uint32_t)0x00000004U)
#define RTC_BKP_DR5 ((uint32_t)0x00000005U)
#define RTC_BKP_DR6 ((uint32_t)0x00000006U)
#define RTC_BKP_DR7 ((uint32_t)0x00000007U)
#define RTC_BKP_DR8 ((uint32_t)0x00000008U)
#define RTC_BKP_DR9 ((uint32_t)0x00000009U)
#define RTC_BKP_DR10 ((uint32_t)0x0000000AU)
#define RTC_BKP_DR11 ((uint32_t)0x0000000BU)
#define RTC_BKP_DR12 ((uint32_t)0x0000000CU)
#define RTC_BKP_DR13 ((uint32_t)0x0000000DU)
#define RTC_BKP_DR14 ((uint32_t)0x0000000EU)
#define RTC_BKP_DR15 ((uint32_t)0x0000000FU)
#define RTC_BKP_DR16 ((uint32_t)0x00000010U)
#define RTC_BKP_DR17 ((uint32_t)0x00000011U)
#define RTC_BKP_DR18 ((uint32_t)0x00000012U)
#define RTC_BKP_DR19 ((uint32_t)0x00000013U)
#define RTC_BKP_DR0 0x00000000U
#define RTC_BKP_DR1 0x00000001U
#define RTC_BKP_DR2 0x00000002U
#define RTC_BKP_DR3 0x00000003U
#define RTC_BKP_DR4 0x00000004U
#define RTC_BKP_DR5 0x00000005U
#define RTC_BKP_DR6 0x00000006U
#define RTC_BKP_DR7 0x00000007U
#define RTC_BKP_DR8 0x00000008U
#define RTC_BKP_DR9 0x00000009U
#define RTC_BKP_DR10 0x0000000AU
#define RTC_BKP_DR11 0x0000000BU
#define RTC_BKP_DR12 0x0000000CU
#define RTC_BKP_DR13 0x0000000DU
#define RTC_BKP_DR14 0x0000000EU
#define RTC_BKP_DR15 0x0000000FU
#define RTC_BKP_DR16 0x00000010U
#define RTC_BKP_DR17 0x00000011U
#define RTC_BKP_DR18 0x00000012U
#define RTC_BKP_DR19 0x00000013U
/**
* @}
*/
@ -111,8 +111,8 @@ typedef struct
/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC TimeStamp Edges Definitions
* @{
*/
#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000U)
#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008U)
#define RTC_TIMESTAMPEDGE_RISING 0x00000000U
#define RTC_TIMESTAMPEDGE_FALLING 0x00000008U
/**
* @}
*/
@ -128,8 +128,8 @@ typedef struct
/** @defgroup RTCEx_Tamper_Pins_Selection RTC tamper Pins Selection
* @{
*/
#define RTC_TAMPERPIN_DEFAULT ((uint32_t)0x00000000U)
#define RTC_TAMPERPIN_POS1 ((uint32_t)0x00010000U)
#define RTC_TAMPERPIN_DEFAULT 0x00000000U
#define RTC_TAMPERPIN_POS1 0x00010000U
/**
* @}
@ -138,8 +138,8 @@ typedef struct
/** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection
* @{
*/
#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000U)
#define RTC_TIMESTAMPPIN_POS1 ((uint32_t)0x00020000U)
#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U
#define RTC_TIMESTAMPPIN_POS1 0x00020000U
/**
* @}
@ -148,8 +148,8 @@ typedef struct
/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions
* @{
*/
#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000U)
#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002U)
#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U
#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x00000002U
/**
* @}
@ -158,12 +158,12 @@ typedef struct
/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wake-up Timer Definitions
* @{
*/
#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000U)
#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001U)
#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002U)
#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003U)
#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004U)
#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006U)
#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U
#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 0x00000001U
#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 0x00000002U
#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 0x00000003U
#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS 0x00000004U
#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS 0x00000006U
/**
* @}
*/
@ -171,8 +171,8 @@ typedef struct
/** @defgroup RTCEx_Digital_Calibration_Definitions RTC Digital Calib Definitions
* @{
*/
#define RTC_CALIBSIGN_POSITIVE ((uint32_t)0x00000000U)
#define RTC_CALIBSIGN_NEGATIVE ((uint32_t)0x00000080U)
#define RTC_CALIBSIGN_POSITIVE 0x00000000U
#define RTC_CALIBSIGN_NEGATIVE 0x00000080U
/**
* @}
*/
@ -320,7 +320,7 @@ typedef struct
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
}while(0)
}while(0U)
/**
* @brief Disable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
@ -329,7 +329,7 @@ typedef struct
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
}while(0)
}while(0U)
/**
* @brief Check whether the RTC Wake-up Timer associated Exti line interrupt flag is set or not.
@ -558,7 +558,7 @@ typedef struct
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();\
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();\
}while(0)
}while(0U)
/**
* @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
@ -567,7 +567,7 @@ typedef struct
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();\
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();\
}while(0)
}while(0U)
/**
* @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.

4834
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_sd.c
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File diff suppressed because it is too large Load Diff

578
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_sd.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_sd.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of SD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -53,55 +53,123 @@
/** @defgroup SD SD
* @brief SD HAL module driver
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SD_Exported_Types SD Exported Types
* @{
*/
/** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition
/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
* @{
*/
typedef enum
{
HAL_SD_STATE_RESET = 0x00000000U, /*!< SD not yet initialized or disabled */
HAL_SD_STATE_READY = 0x00000001U, /*!< SD initialized and ready for use */
HAL_SD_STATE_TIMEOUT = 0x00000002U, /*!< SD Timeout state */
HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */
HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */
HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receinving State */
HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfert State */
HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */
}HAL_SD_StateTypeDef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
* @{
*/
typedef enum
{
HAL_SD_CARD_READY = 0x00000001U, /*!< Card state is ready */
HAL_SD_CARD_IDENTIFICATION = 0x00000002U, /*!< Card is in identification state */
HAL_SD_CARD_STANDBY = 0x00000003U, /*!< Card is in standby state */
HAL_SD_CARD_TRANSFER = 0x00000004U, /*!< Card is in transfer state */
HAL_SD_CARD_SENDING = 0x00000005U, /*!< Card is sending an operation */
HAL_SD_CARD_RECEIVING = 0x00000006U, /*!< Card is receiving operation information */
HAL_SD_CARD_PROGRAMMING = 0x00000007U, /*!< Card is in programming state */
HAL_SD_CARD_DISCONNECTED = 0x00000008U, /*!< Card is disconnected */
HAL_SD_CARD_ERROR = 0x000000FFU /*!< Card response Error */
}HAL_SD_CardStateTypeDef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
* @{
*/
#define SD_InitTypeDef SDIO_InitTypeDef
#define SD_TypeDef SDIO_TypeDef
/**
* @brief SD Card Information Structure definition
*/
typedef struct
{
SD_TypeDef *Instance; /*!< SDIO register base address */
uint32_t CardType; /*!< Specifies the card Type */
SD_InitTypeDef Init; /*!< SD required parameters */
uint32_t CardVersion; /*!< Specifies the card version */
uint32_t Class; /*!< Specifies the class of the card class */
uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
HAL_LockTypeDef Lock; /*!< SD locking object */
uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
uint32_t BlockSize; /*!< Specifies one block size in bytes */
uint32_t CardType; /*!< SD card type */
uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
}HAL_SD_CardInfoTypeDef;
/**
* @brief SD handle Structure definition
*/
typedef struct
{
SD_TypeDef *Instance; /*!< SD registers base address */
uint32_t RCA; /*!< SD relative card address */
SD_InitTypeDef Init; /*!< SD required parameters */
uint32_t CSD[4]; /*!< SD card specific data table */
HAL_LockTypeDef Lock; /*!< SD locking object */
uint32_t CID[4]; /*!< SD card identification number table */
uint32_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
uint32_t TxXferSize; /*!< SD Tx Transfer size */
uint32_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
uint32_t RxXferSize; /*!< SD Rx Transfer size */
__IO uint32_t SdTransferCplt; /*!< SD transfer complete flag in non blocking mode */
__IO uint32_t Context; /*!< SD transfer context */
__IO HAL_SD_StateTypeDef State; /*!< SD card State */
__IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */
__IO uint32_t ErrorCode; /*!< SD Card Error codes */
DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
__IO uint32_t DmaTransferCplt; /*!< SD DMA transfer complete flag */
DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
__IO uint32_t SdOperation; /*!< SD transfer operation (read/write) */
HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */
DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
uint32_t CSD[4]; /*!< SD card specific data table */
DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
uint32_t CID[4]; /*!< SD card identification number table */
}SD_HandleTypeDef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register
/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
* @{
*/
*/
typedef struct
{
__IO uint8_t CSDStruct; /*!< CSD structure */
@ -141,15 +209,15 @@ typedef struct
__IO uint8_t ECC; /*!< ECC code */
__IO uint8_t CSD_CRC; /*!< CSD CRC */
__IO uint8_t Reserved4; /*!< Always 1 */
}HAL_SD_CSDTypedef;
}HAL_SD_CardCSDTypeDef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register
/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
* @{
*/
*/
typedef struct
{
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */
@ -163,304 +231,160 @@ typedef struct
__IO uint8_t CID_CRC; /*!< CID CRC */
__IO uint8_t Reserved2; /*!< Always 1 */
}HAL_SD_CIDTypedef;
}HAL_SD_CardCIDTypeDef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13
/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
* @{
*/
*/
typedef struct
{
__IO uint8_t DAT_BUS_WIDTH; /*!< Shows the currently defined data bus width */
__IO uint8_t SECURED_MODE; /*!< Card is in secured mode of operation */
__IO uint16_t SD_CARD_TYPE; /*!< Carries information about card type */
__IO uint32_t SIZE_OF_PROTECTED_AREA; /*!< Carries information about the capacity of protected area */
__IO uint8_t SPEED_CLASS; /*!< Carries information about the speed class of the card */
__IO uint8_t PERFORMANCE_MOVE; /*!< Carries information about the card's performance move */
__IO uint8_t AU_SIZE; /*!< Carries information about the card's allocation unit size */
__IO uint16_t ERASE_SIZE; /*!< Determines the number of AUs to be erased in one operation */
__IO uint8_t ERASE_TIMEOUT; /*!< Determines the timeout for any number of AU erase */
__IO uint8_t ERASE_OFFSET; /*!< Carries information about the erase offset */
__IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
__IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
__IO uint16_t CardType; /*!< Carries information about card type */
__IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
__IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
__IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
__IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
__IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
__IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
__IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
}HAL_SD_CardStatusTypedef;
}HAL_SD_CardStatusTypeDef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group5 SD Card information structure
* @{
*/
typedef struct
{
HAL_SD_CSDTypedef SD_csd; /*!< SD card specific data register */
HAL_SD_CIDTypedef SD_cid; /*!< SD card identification number register */
uint64_t CardCapacity; /*!< Card capacity */
uint32_t CardBlockSize; /*!< Card block size */
uint16_t RCA; /*!< SD relative card address */
uint8_t CardType; /*!< SD card type */
}HAL_SD_CardInfoTypedef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition
* @{
*/
typedef enum
{
/**
* @brief SD specific error defines
*/
SD_CMD_CRC_FAIL = (1U), /*!< Command response received (but CRC check failed) */
SD_DATA_CRC_FAIL = (2U), /*!< Data block sent/received (CRC check failed) */
SD_CMD_RSP_TIMEOUT = (3U), /*!< Command response timeout */
SD_DATA_TIMEOUT = (4U), /*!< Data timeout */
SD_TX_UNDERRUN = (5U), /*!< Transmit FIFO underrun */
SD_RX_OVERRUN = (6U), /*!< Receive FIFO overrun */
SD_START_BIT_ERR = (7U), /*!< Start bit not detected on all data signals in wide bus mode */
SD_CMD_OUT_OF_RANGE = (8U), /*!< Command's argument was out of range. */
SD_ADDR_MISALIGNED = (9U), /*!< Misaligned address */
SD_BLOCK_LEN_ERR = (10U), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
SD_ERASE_SEQ_ERR = (11U), /*!< An error in the sequence of erase command occurs. */
SD_BAD_ERASE_PARAM = (12U), /*!< An invalid selection for erase groups */
SD_WRITE_PROT_VIOLATION = (13U), /*!< Attempt to program a write protect block */
SD_LOCK_UNLOCK_FAILED = (14U), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
SD_COM_CRC_FAILED = (15U), /*!< CRC check of the previous command failed */
SD_ILLEGAL_CMD = (16U), /*!< Command is not legal for the card state */
SD_CARD_ECC_FAILED = (17U), /*!< Card internal ECC was applied but failed to correct the data */
SD_CC_ERROR = (18U), /*!< Internal card controller error */
SD_GENERAL_UNKNOWN_ERROR = (19U), /*!< General or unknown error */
SD_STREAM_READ_UNDERRUN = (20U), /*!< The card could not sustain data transfer in stream read operation. */
SD_STREAM_WRITE_OVERRUN = (21U), /*!< The card could not sustain data programming in stream mode */
SD_CID_CSD_OVERWRITE = (22U), /*!< CID/CSD overwrite error */
SD_WP_ERASE_SKIP = (23U), /*!< Only partial address space was erased */
SD_CARD_ECC_DISABLED = (24U), /*!< Command has been executed without using internal ECC */
SD_ERASE_RESET = (25U), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
SD_AKE_SEQ_ERROR = (26U), /*!< Error in sequence of authentication. */
SD_INVALID_VOLTRANGE = (27U),
SD_ADDR_OUT_OF_RANGE = (28U),
SD_SWITCH_ERROR = (29U),
SD_SDIO_DISABLED = (30U),
SD_SDIO_FUNCTION_BUSY = (31U),
SD_SDIO_FUNCTION_FAILED = (32U),
SD_SDIO_UNKNOWN_FUNCTION = (33U),
/**
* @brief Standard error defines
*/
SD_INTERNAL_ERROR = (34U),
SD_NOT_CONFIGURED = (35U),
SD_REQUEST_PENDING = (36U),
SD_REQUEST_NOT_APPLICABLE = (37U),
SD_INVALID_PARAMETER = (38U),
SD_UNSUPPORTED_FEATURE = (39U),
SD_UNSUPPORTED_HW = (40U),
SD_ERROR = (41U),
SD_OK = (0U)
}HAL_SD_ErrorTypedef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure
* @{
*/
typedef enum
{
SD_TRANSFER_OK = 0U, /*!< Transfer success */
SD_TRANSFER_BUSY = 1U, /*!< Transfer is occurring */
SD_TRANSFER_ERROR = 2U /*!< Transfer failed */
}HAL_SD_TransferStateTypedef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure
* @{
*/
typedef enum
{
SD_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */
SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */
SD_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */
SD_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */
SD_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */
SD_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */
SD_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */
SD_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */
SD_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card is in error state */
}HAL_SD_CardStateTypedef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure
* @{
*/
typedef enum
{
SD_READ_SINGLE_BLOCK = 0U, /*!< Read single block operation */
SD_READ_MULTIPLE_BLOCK = 1U, /*!< Read multiple blocks operation */
SD_WRITE_SINGLE_BLOCK = 2U, /*!< Write single block operation */
SD_WRITE_MULTIPLE_BLOCK = 3U /*!< Write multiple blocks operation */
}HAL_SD_OperationTypedef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SD_Exported_Constants SD Exported Constants
/** @defgroup SD_Exported_Constants Exported Constants
* @{
*/
/**
* @brief SD Commands Index
*/
#define SD_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */
#define SD_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */
#define SD_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
#define SD_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */
#define SD_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */
#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
operating condition register (OCR) content in the response on the CMD line. */
#define SD_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
and asks the card whether card supports voltage. */
#define SD_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
#define SD_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */
#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */
#define SD_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */
#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14U)
#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */
#define SD_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
for SDHS and SDXC. */
#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
fixed 512 bytes in case of SDHC and SDXC. */
#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
STOP_TRANSMISSION command. */
#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */
#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */
#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
fixed 512 bytes in case of SDHC and SDXC. */
#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
#define SD_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */
#define SD_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */
#define SD_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */
#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */
#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */
#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
#define SD_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
system set by switch function command (CMD6). */
#define SD_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
Reserved for each command system set by switch function command (CMD6). */
#define SD_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */
#define SD_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */
#define SD_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */
#define SD_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
the SET_BLOCK_LEN command. */
#define SD_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
than a standard command. */
#define SD_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
for general purpose/application specific commands. */
#define SD_CMD_NO_CMD ((uint8_t)64U)
#define BLOCKSIZE 512U /*!< Block size is 512 bytes */
/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
* @{
*/
#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
number of transferred bytes does not match the block length */
#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
command or if there was an attempt to access a locked card */
#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
of erase sequence command was received */
#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
/**
* @brief Following commands are SD Card Specific commands.
* SDIO_APP_CMD should be sent before sending these commands.
* @}
*/
#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
widths are given in SCR register. */
#define SD_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */
#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
32bit+CRC data block. */
#define SD_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
send its operating condition register (OCR) content in the response on the CMD line. */
#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */
#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */
#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */
/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
* @{
*/
#define SD_CONTEXT_NONE 0x00000000U /*!< None */
#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
/**
* @brief Following commands are SD Card Specific security commands.
* SD_CMD_APP_CMD should be sent before sending these commands.
/**
* @}
*/
#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43U) /*!< For SD card only */
#define SD_CMD_SD_APP_GET_MID ((uint8_t)44U) /*!< For SD card only */
#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) /*!< For SD card only */
#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) /*!< For SD card only */
#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) /*!< For SD card only */
#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) /*!< For SD card only */
#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) /*!< For SD card only */
#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) /*!< For SD card only */
#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) /*!< For SD card only */
#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) /*!< For SD card only */
#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) /*!< For SD card only */
/**
* @brief Supported SD Memory Cards
/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
* @{
*/
#define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000U)
#define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001U)
#define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002U)
#define MULTIMEDIA_CARD ((uint32_t)0x00000003U)
#define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004U)
#define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005U)
#define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006U)
#define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007U)
#define CARD_SDSC 0x00000000U
#define CARD_SDHC_SDXC 0x00000001U
#define CARD_SECURED 0x00000003U
/**
* @}
*/
/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
* @{
*/
#define CARD_V1_X 0x00000000U
#define CARD_V2_X 0x00000001U
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SD_Exported_macros SD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
/**
* @brief Enable the SD device.
* @retval None
*/
#define __HAL_SD_SDIO_ENABLE() __SDIO_ENABLE()
#define __HAL_SD_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
/**
* @brief Disable the SD device.
* @retval None
*/
#define __HAL_SD_SDIO_DISABLE() __SDIO_DISABLE()
#define __HAL_SD_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
/**
* @brief Enable the SDIO DMA transfer.
* @brief Enable the SDMMC DMA transfer.
* @retval None
*/
#define __HAL_SD_SDIO_DMA_ENABLE() __SDIO_DMA_ENABLE()
#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
/**
* @brief Disable the SDIO DMA transfer.
* @brief Disable the SDMMC DMA transfer.
* @retval None
*/
#define __HAL_SD_SDIO_DMA_DISABLE() __SDIO_DMA_DISABLE()
#define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
/**
* @brief Enable the SD device interrupt.
* @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the SDIO interrupt sources to be enabled.
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@ -471,8 +395,6 @@ typedef enum
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
* bus mode interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@ -486,15 +408,14 @@ typedef enum
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
* @retval None
*/
#define __HAL_SD_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Disable the SD device interrupt.
* @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the SDIO interrupt sources to be disabled.
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@ -505,8 +426,6 @@ typedef enum
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
* bus mode interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@ -519,11 +438,10 @@ typedef enum
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* @retval None
*/
#define __HAL_SD_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Check whether the specified SD flag is set or not.
@ -539,7 +457,6 @@ typedef enum
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
* @arg SDIO_FLAG_TXACT: Data transmit in progress
@ -553,10 +470,9 @@ typedef enum
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
* @retval The new state of SD FLAG (SET or RESET).
*/
#define __HAL_SD_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Clear the SD's pending flags.
@ -572,18 +488,16 @@ typedef enum
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
* @retval None
*/
#define __HAL_SD_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Check whether the specified SD interrupt has occurred or not.
* @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the SDIO interrupt source to check.
* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@ -594,8 +508,6 @@ typedef enum
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
* bus mode interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@ -609,14 +521,13 @@ typedef enum
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
* @retval The new state of SD IT (SET or RESET).
*/
#define __HAL_SD_SDIO_GET_IT (__HANDLE__, __INTERRUPT__) __SDIO_GET_IT ((__HANDLE__)->Instance, __INTERRUPT__)
#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Clear the SD's interrupt pending bits.
* @param __HANDLE__ : SD Handle
* @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
@ -627,14 +538,12 @@ typedef enum
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
* bus mode interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
* @retval None
*/
#define __HAL_SD_SDIO_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @}
*/
@ -643,68 +552,79 @@ typedef enum
/** @defgroup SD_Exported_Functions SD Exported Functions
* @{
*/
/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
/**
* @}
*/
/** @defgroup SD_Exported_Functions_Group2 I/O operation functions
/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* Blocking mode: Polling */
HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr);
HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
/* Non-Blocking mode: IT */
HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
/* Non-Blocking mode: Interrupt */
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
/* Callback in non blocking modes (DMA) */
void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
/* Non-Blocking mode: DMA */
HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
/**
* @}
*/
/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
/**
* @}
*/
/* Peripheral State functions ************************************************/
/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions
/** @defgroup SD_Exported_Functions_Group4 SD card related functions
* @{
*/
HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
HAL_StatusTypeDef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
/**
* @}
*/
/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
* @{
*/
HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
/**
* @}
*/
/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
* @{
*/
HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
/**
* @}
*/
@ -772,6 +692,7 @@ HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
* @}
*/
/**
* @}
*/
@ -779,6 +700,9 @@ HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}

635
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_smartcard.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_smartcard.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief SMARTCARD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:
@ -100,7 +100,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -163,6 +163,10 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
/**
* @}
@ -373,13 +377,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
===============================================================================
##### IO operation functions #####
===============================================================================
This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
[..]
Smartcard is a single wire half duplex communication protocol.
[..] This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
[..]
(#) Smartcard is a single wire half duplex communication protocol.
The Smartcard interface is designed to support asynchronous protocol Smartcards as
defined in the ISO 7816-3 standard. The USART should be configured as:
(+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
(+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
defined in the ISO 7816-3 standard.
(#) The USART should be configured as:
(++) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
(++) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
(#) There are two modes of transfer:
(++) Blocking mode: The communication is performed in polling mode.
@ -432,7 +438,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
if(hsc->gState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -448,7 +454,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
hsc->TxXferSize = Size;
hsc->TxXferCount = Size;
while(hsc->TxXferCount > 0U)
while(hsc->TxXferCount > 0)
{
hsc->TxXferCount--;
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
@ -456,7 +462,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
return HAL_TIMEOUT;
}
tmp = (uint16_t*) pData;
hsc->Instance->DR = (*tmp & (uint16_t)0x01FFU);
hsc->Instance->DR = (*tmp & (uint16_t)0x01FF);
pData +=1U;
}
@ -495,7 +501,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -513,7 +519,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
hsc->RxXferCount = Size;
/* Check the remain data to be received */
while(hsc->RxXferCount > 0U)
while(hsc->RxXferCount > 0)
{
hsc->RxXferCount--;
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
@ -521,7 +527,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
return HAL_TIMEOUT;
}
tmp = (uint16_t*) pData;
*tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFFU);
*tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF);
pData +=1U;
}
@ -552,7 +558,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_
/* Check that a Tx process is not already ongoing */
if(hsc->gState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -600,7 +606,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t
/* Check that a Rx process is not already ongoing */
if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -647,7 +653,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8
/* Check that a Tx process is not already ongoing */
if(hsc->gState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -709,7 +715,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_
/* Check that a Rx process is not already ongoing */
if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -736,6 +742,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t*)tmp, Size);
/* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
__HAL_SMARTCARD_CLEAR_OREFLAG(hsc);
/* Process Unlocked */
__HAL_UNLOCK(hsc);
@ -757,6 +766,407 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_
}
}
/**
* @brief Abort ongoing transfers (blocking mode).
* @param hsc SMARTCARD handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc)
{
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
/* Disable the SMARTCARD DMA Tx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
if(hsc->hdmatx != NULL)
{
/* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hsc->hdmatx->XferAbortCallback = NULL;
HAL_DMA_Abort(hsc->hdmatx);
}
}
/* Disable the SMARTCARD DMA Rx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
if(hsc->hdmarx != NULL)
{
/* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hsc->hdmarx->XferAbortCallback = NULL;
HAL_DMA_Abort(hsc->hdmarx);
}
}
/* Reset Tx and Rx transfer counters */
hsc->TxXferCount = 0x00U;
hsc->RxXferCount = 0x00U;
/* Reset ErrorCode */
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Restore hsc->RxState and hsc->gState to Ready */
hsc->RxState = HAL_SMARTCARD_STATE_READY;
hsc->gState = HAL_SMARTCARD_STATE_READY;
return HAL_OK;
}
/**
* @brief Abort ongoing Transmit transfer (blocking mode).
* @param hsc SMARTCARD handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc)
{
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Disable the SMARTCARD DMA Tx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
if(hsc->hdmatx != NULL)
{
/* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hsc->hdmatx->XferAbortCallback = NULL;
HAL_DMA_Abort(hsc->hdmatx);
}
}
/* Reset Tx transfer counter */
hsc->TxXferCount = 0x00U;
/* Restore hsc->gState to Ready */
hsc->gState = HAL_SMARTCARD_STATE_READY;
return HAL_OK;
}
/**
* @brief Abort ongoing Receive transfer (blocking mode).
* @param hsc SMARTCARD handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
/* Disable the SMARTCARD DMA Rx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
if(hsc->hdmarx != NULL)
{
/* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hsc->hdmarx->XferAbortCallback = NULL;
HAL_DMA_Abort(hsc->hdmarx);
}
}
/* Reset Rx transfer counter */
hsc->RxXferCount = 0x00U;
/* Restore hsc->RxState to Ready */
hsc->RxState = HAL_SMARTCARD_STATE_READY;
return HAL_OK;
}
/**
* @brief Abort ongoing transfers (Interrupt mode).
* @param hsc SMARTCARD handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc)
{
uint32_t AbortCplt = 0x01U;
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
/* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
if(hsc->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
Otherwise, set it to NULL */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
{
hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
}
else
{
hsc->hdmatx->XferAbortCallback = NULL;
}
}
/* DMA Rx Handle is valid */
if(hsc->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
Otherwise, set it to NULL */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
{
hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
}
else
{
hsc->hdmarx->XferAbortCallback = NULL;
}
}
/* Disable the SMARTCARD DMA Tx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at SMARTCARD level */
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
if(hsc->hdmatx != NULL)
{
/* SMARTCARD Tx DMA Abort callback has already been initialised :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA TX */
if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
{
hsc->hdmatx->XferAbortCallback = NULL;
}
else
{
AbortCplt = 0x00U;
}
}
}
/* Disable the SMARTCARD DMA Rx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
if(hsc->hdmarx != NULL)
{
/* SMARTCARD Rx DMA Abort callback has already been initialised :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA RX */
if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
{
hsc->hdmarx->XferAbortCallback = NULL;
AbortCplt = 0x01U;
}
else
{
AbortCplt = 0x00U;
}
}
}
/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
if(AbortCplt == 0x01U)
{
/* Reset Tx and Rx transfer counters */
hsc->TxXferCount = 0x00U;
hsc->RxXferCount = 0x00U;
/* Reset ErrorCode */
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Restore hsc->gState and hsc->RxState to Ready */
hsc->gState = HAL_SMARTCARD_STATE_READY;
hsc->RxState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
HAL_SMARTCARD_AbortCpltCallback(hsc);
}
return HAL_OK;
}
/**
* @brief Abort ongoing Transmit transfer (Interrupt mode).
* @param hsc SMARTCARD handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc)
{
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Disable the SMARTCARD DMA Tx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
if(hsc->hdmatx != NULL)
{
/* Set the SMARTCARD DMA Abort callback :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
/* Abort DMA TX */
if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
{
/* Call Directly hsc->hdmatx->XferAbortCallback function in case of error */
hsc->hdmatx->XferAbortCallback(hsc->hdmatx);
}
}
else
{
/* Reset Tx transfer counter */
hsc->TxXferCount = 0x00U;
/* Restore hsc->gState to Ready */
hsc->gState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
}
}
else
{
/* Reset Tx transfer counter */
hsc->TxXferCount = 0x00U;
/* Restore hsc->gState to Ready */
hsc->gState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
}
return HAL_OK;
}
/**
* @brief Abort ongoing Receive transfer (Interrupt mode).
* @param hsc SMARTCARD handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
/* Disable the SMARTCARD DMA Rx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
if(hsc->hdmarx != NULL)
{
/* Set the SMARTCARD DMA Abort callback :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
/* Abort DMA RX */
if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
{
/* Call Directly hsc->hdmarx->XferAbortCallback function in case of error */
hsc->hdmarx->XferAbortCallback(hsc->hdmarx);
}
}
else
{
/* Reset Rx transfer counter */
hsc->RxXferCount = 0x00U;
/* Restore hsc->RxState to Ready */
hsc->RxState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
}
}
else
{
/* Reset Rx transfer counter */
hsc->RxXferCount = 0x00U;
/* Restore hsc->RxState to Ready */
hsc->RxState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
}
return HAL_OK;
}
/**
* @brief This function handles SMARTCARD interrupt request.
* @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
@ -927,6 +1337,51 @@ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
*/
}
/**
* @brief SMARTCARD Abort Complete callback.
* @param hsc SMARTCARD handle.
* @retval None
*/
__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
*/
}
/**
* @brief SMARTCARD Abort Transmit Complete callback.
* @param hsc SMARTCARD handle.
* @retval None
*/
__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
*/
}
/**
* @brief SMARTCARD Abort ReceiveComplete callback.
* @param hsc SMARTCARD handle.
* @retval None
*/
__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
*/
}
/**
* @}
*/
@ -986,7 +1441,7 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsc->TxXferCount = 0U;
hsc->TxXferCount = 0;
/* Disable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
@ -1006,7 +1461,7 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsc->RxXferCount = 0U;
hsc->RxXferCount = 0;
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
@ -1032,8 +1487,8 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
{
uint32_t dmarequest = 0x00U;
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsc->RxXferCount = 0U;
hsc->TxXferCount = 0U;
hsc->RxXferCount = 0;
hsc->TxXferCount = 0;
hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
/* Stop SMARTCARD DMA Tx request if ongoing */
@ -1133,10 +1588,10 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
if(hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX)
{
tmp = (uint16_t*) hsc->pTxBuffPtr;
hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FFU);
hsc->pTxBuffPtr += 1U;
hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
hsc->pTxBuffPtr += 1;
if(--hsc->TxXferCount == 0U)
if(--hsc->TxXferCount == 0)
{
/* Disable the SMARTCARD Transmit data register empty Interrupt */
CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
@ -1189,10 +1644,10 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
{
tmp = (uint16_t*) hsc->pRxBuffPtr;
*tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FFU);
hsc->pRxBuffPtr += 1U;
*tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
hsc->pRxBuffPtr += 1;
if(--hsc->RxXferCount == 0U)
if(--hsc->RxXferCount == 0)
{
CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
@ -1226,12 +1681,130 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = (SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsc->RxXferCount = 0x00U;
hsc->TxXferCount = 0x00U;
hsc->RxXferCount = 0x00;
hsc->TxXferCount = 0x00;
HAL_SMARTCARD_ErrorCallback(hsc);
}
/**
* @brief DMA SMARTCARD Tx communication abort callback, when initiated by user
* (To be called at end of DMA Tx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Rx DMA Handle.
* @param hdma DMA handle.
* @retval None
*/
static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsc->hdmatx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
if(hsc->hdmarx != NULL)
{
if(hsc->hdmarx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
hsc->TxXferCount = 0x00U;
hsc->RxXferCount = 0x00U;
/* Reset ErrorCode */
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Restore hsc->gState and hsc->RxState to Ready */
hsc->gState = HAL_SMARTCARD_STATE_READY;
hsc->RxState = HAL_SMARTCARD_STATE_READY;
/* Call user Abort complete callback */
HAL_SMARTCARD_AbortCpltCallback(hsc);
}
/**
* @brief DMA SMARTCARD Rx communication abort callback, when initiated by user
* (To be called at end of DMA Rx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Tx DMA Handle.
* @param hdma DMA handle.
* @retval None
*/
static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsc->hdmarx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
if(hsc->hdmatx != NULL)
{
if(hsc->hdmatx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
hsc->TxXferCount = 0x00U;
hsc->RxXferCount = 0x00U;
/* Reset ErrorCode */
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Restore hsc->gState and hsc->RxState to Ready */
hsc->gState = HAL_SMARTCARD_STATE_READY;
hsc->RxState = HAL_SMARTCARD_STATE_READY;
/* Call user Abort complete callback */
HAL_SMARTCARD_AbortCpltCallback(hsc);
}
/**
* @brief DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
* HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
* (This callback is executed at end of DMA Tx Abort procedure following user abort request,
* and leads to user Tx Abort Complete callback execution).
* @param hdma DMA handle.
* @retval None
*/
static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsc->TxXferCount = 0x00U;
/* Restore hsc->gState to Ready */
hsc->gState = HAL_SMARTCARD_STATE_READY;
/* Call user Abort complete callback */
HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
}
/**
* @brief DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
* HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
* (This callback is executed at end of DMA Rx Abort procedure following user abort request,
* and leads to user Rx Abort Complete callback execution).
* @param hdma DMA handle.
* @retval None
*/
static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsc->RxXferCount = 0x00U;
/* Restore hsc->RxState to Ready */
hsc->RxState = HAL_SMARTCARD_STATE_READY;
/* Call user Abort complete callback */
HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
}
/**
* @brief Configure the SMARTCARD peripheral
* @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains

118
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_smartcard.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_smartcard.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -216,12 +216,12 @@ typedef struct
* @brief SMARTCARD Error Code
* @{
*/
#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#define HAL_SMARTCARD_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_SMARTCARD_ERROR_PE 0x00000001U /*!< Parity error */
#define HAL_SMARTCARD_ERROR_NE 0x00000002U /*!< Noise error */
#define HAL_SMARTCARD_ERROR_FE 0x00000004U /*!< Frame error */
#define HAL_SMARTCARD_ERROR_ORE 0x00000008U /*!< Overrun error */
#define HAL_SMARTCARD_ERROR_DMA 0x00000010U /*!< DMA transfer error */
/**
* @}
*/
@ -265,7 +265,7 @@ typedef struct
/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
* @{
*/
#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000U)
#define SMARTCARD_POLARITY_LOW 0x00000000U
#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
/**
* @}
@ -274,7 +274,7 @@ typedef struct
/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
* @{
*/
#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000U)
#define SMARTCARD_PHASE_1EDGE 0x00000000U
#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
/**
* @}
@ -283,7 +283,7 @@ typedef struct
/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
* @{
*/
#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000U)
#define SMARTCARD_LASTBIT_DISABLE 0x00000000U
#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
/**
* @}
@ -293,7 +293,7 @@ typedef struct
* @{
*/
#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000U)
#define SMARTCARD_NACK_DISABLE 0x00000000U
/**
* @}
*/
@ -310,37 +310,37 @@ typedef struct
/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
* @{
*/
#define SMARTCARD_PRESCALER_SYSCLK_DIV2 ((uint32_t)0x00000001U) /*!< SYSCLK divided by 2 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV4 ((uint32_t)0x00000002U) /*!< SYSCLK divided by 4 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV6 ((uint32_t)0x00000003U) /*!< SYSCLK divided by 6 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV8 ((uint32_t)0x00000004U) /*!< SYSCLK divided by 8 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV10 ((uint32_t)0x00000005U) /*!< SYSCLK divided by 10 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV12 ((uint32_t)0x00000006U) /*!< SYSCLK divided by 12 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV14 ((uint32_t)0x00000007U) /*!< SYSCLK divided by 14 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV16 ((uint32_t)0x00000008U) /*!< SYSCLK divided by 16 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV18 ((uint32_t)0x00000009U) /*!< SYSCLK divided by 18 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV20 ((uint32_t)0x0000000AU) /*!< SYSCLK divided by 20 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV22 ((uint32_t)0x0000000BU) /*!< SYSCLK divided by 22 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV24 ((uint32_t)0x0000000CU) /*!< SYSCLK divided by 24 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV26 ((uint32_t)0x0000000DU) /*!< SYSCLK divided by 26 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV28 ((uint32_t)0x0000000EU) /*!< SYSCLK divided by 28 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV30 ((uint32_t)0x0000000FU) /*!< SYSCLK divided by 30 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV32 ((uint32_t)0x00000010U) /*!< SYSCLK divided by 32 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV34 ((uint32_t)0x00000011U) /*!< SYSCLK divided by 34 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV36 ((uint32_t)0x00000012U) /*!< SYSCLK divided by 36 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV38 ((uint32_t)0x00000013U) /*!< SYSCLK divided by 38 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV40 ((uint32_t)0x00000014U) /*!< SYSCLK divided by 40 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV42 ((uint32_t)0x00000015U) /*!< SYSCLK divided by 42 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV44 ((uint32_t)0x00000016U) /*!< SYSCLK divided by 44 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV46 ((uint32_t)0x00000017U) /*!< SYSCLK divided by 46 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV48 ((uint32_t)0x00000018U) /*!< SYSCLK divided by 48 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV50 ((uint32_t)0x00000019U) /*!< SYSCLK divided by 50 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV52 ((uint32_t)0x0000001AU) /*!< SYSCLK divided by 52 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV54 ((uint32_t)0x0000001BU) /*!< SYSCLK divided by 54 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV56 ((uint32_t)0x0000001CU) /*!< SYSCLK divided by 56 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV58 ((uint32_t)0x0000001DU) /*!< SYSCLK divided by 58 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV60 ((uint32_t)0x0000001EU) /*!< SYSCLK divided by 60 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV62 ((uint32_t)0x0000001FU) /*!< SYSCLK divided by 62 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV2 0x00000001U /*!< SYSCLK divided by 2 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV4 0x00000002U /*!< SYSCLK divided by 4 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV6 0x00000003U /*!< SYSCLK divided by 6 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV8 0x00000004U /*!< SYSCLK divided by 8 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV10 0x00000005U /*!< SYSCLK divided by 10 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV12 0x00000006U /*!< SYSCLK divided by 12 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV14 0x00000007U /*!< SYSCLK divided by 14 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV16 0x00000008U /*!< SYSCLK divided by 16 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV18 0x00000009U /*!< SYSCLK divided by 18 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV20 0x0000000AU /*!< SYSCLK divided by 20 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV22 0x0000000BU /*!< SYSCLK divided by 22 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV24 0x0000000CU /*!< SYSCLK divided by 24 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV26 0x0000000DU /*!< SYSCLK divided by 26 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV28 0x0000000EU /*!< SYSCLK divided by 28 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV30 0x0000000FU /*!< SYSCLK divided by 30 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV32 0x00000010U /*!< SYSCLK divided by 32 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV34 0x00000011U /*!< SYSCLK divided by 34 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV36 0x00000012U /*!< SYSCLK divided by 36 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV38 0x00000013U /*!< SYSCLK divided by 38 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV40 0x00000014U /*!< SYSCLK divided by 40 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV42 0x00000015U /*!< SYSCLK divided by 42 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV44 0x00000016U /*!< SYSCLK divided by 44 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV46 0x00000017U /*!< SYSCLK divided by 46 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV48 0x00000018U /*!< SYSCLK divided by 48 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV50 0x00000019U /*!< SYSCLK divided by 50 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV52 0x0000001AU /*!< SYSCLK divided by 52 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV54 0x0000001BU /*!< SYSCLK divided by 54 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV56 0x0000001CU /*!< SYSCLK divided by 56 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV58 0x0000001DU /*!< SYSCLK divided by 58 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV60 0x0000001EU /*!< SYSCLK divided by 60 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV62 0x0000001FU /*!< SYSCLK divided by 62 */
/**
* @}
*/
@ -350,14 +350,14 @@ typedef struct
* - 0xXXXX : Flag mask in the SR register
* @{
*/
#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080U)
#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040U)
#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020U)
#define SMARTCARD_FLAG_IDLE ((uint32_t)0x00000010U)
#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008U)
#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004U)
#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002U)
#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001U)
#define SMARTCARD_FLAG_TXE 0x00000080U
#define SMARTCARD_FLAG_TC 0x00000040U
#define SMARTCARD_FLAG_RXNE 0x00000020U
#define SMARTCARD_FLAG_IDLE 0x00000010U
#define SMARTCARD_FLAG_ORE 0x00000008U
#define SMARTCARD_FLAG_NE 0x00000004U
#define SMARTCARD_FLAG_FE 0x00000002U
#define SMARTCARD_FLAG_PE 0x00000001U
/**
* @}
*/
@ -396,7 +396,7 @@ typedef struct
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
} while(0)
} while(0U)
/** @brief Flushs the Smartcard DR register
* @param __HANDLE__: specifies the SMARTCARD Handle.
@ -580,11 +580,21 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc);
/**
* @}
*/
@ -640,7 +650,7 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
((STOPBITS) == SMARTCARD_STOPBITS_1_5))
#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
((PARITY) == SMARTCARD_PARITY_ODD))
#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3U) == 0x00U) && ((MODE) != (uint32_t)0x000000U))
#define IS_SMARTCARD_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x000000U))
#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \

132
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_spi.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_spi.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief SPI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Peripheral Interface (SPI) peripheral:
@ -124,7 +124,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -461,7 +461,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
goto error;
}
if((pData == NULL ) || (Size == 0U))
if((pData == NULL ) || (Size == 0))
{
errorcode = HAL_ERROR;
goto error;
@ -476,8 +476,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/*Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
hspi->RxXferSize = 0U;
hspi->RxXferCount = 0U;
hspi->RxXferSize = 0;
hspi->RxXferCount = 0;
hspi->TxISR = NULL;
hspi->RxISR = NULL;
@ -512,7 +512,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
hspi->TxXferCount--;
}
/* Transmit data in 16 Bit mode */
while (hspi->TxXferCount > 0U)
while (hspi->TxXferCount > 0)
{
/* Wait until TXE flag is set to send data */
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
@ -541,7 +541,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
pData += sizeof(uint8_t);
hspi->TxXferCount--;
}
while (hspi->TxXferCount > 0U)
while (hspi->TxXferCount > 0)
{
/* Wait until TXE flag is set to send data */
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
@ -614,7 +614,7 @@ error:
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
#if (USE_SPI_CRC != 0U)
__IO uint16_t tmpreg = 0U;
__IO uint16_t tmpreg = 0;
#endif /* USE_SPI_CRC */
uint32_t tickstart = 0U;
HAL_StatusTypeDef errorcode = HAL_OK;
@ -638,7 +638,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
goto error;
}
if((pData == NULL ) || (Size == 0U))
if((pData == NULL ) || (Size == 0))
{
errorcode = HAL_ERROR;
goto error;
@ -653,8 +653,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/*Init field not used in handle to zero */
hspi->pTxBuffPtr = (uint8_t *)NULL;
hspi->TxXferSize = 0U;
hspi->TxXferCount = 0U;
hspi->TxXferSize = 0;
hspi->TxXferCount = 0;
hspi->RxISR = NULL;
hspi->TxISR = NULL;
@ -685,7 +685,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
{
/* Transfer loop */
while(hspi->RxXferCount > 0U)
while(hspi->RxXferCount > 0)
{
/* Check the RXNE flag */
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
@ -709,7 +709,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
else
{
/* Transfer loop */
while(hspi->RxXferCount > 0U)
while(hspi->RxXferCount > 0)
{
/* Check the RXNE flag */
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
@ -811,7 +811,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
uint32_t tmp = 0U, tmp1 = 0U;
#if (USE_SPI_CRC != 0U)
__IO uint16_t tmpreg1 = 0U;
__IO uint16_t tmpreg1 = 0;
#endif /* USE_SPI_CRC */
uint32_t tickstart = 0U;
/* Variable used to alternate Rx and Tx during transfer */
@ -837,7 +837,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
goto error;
}
if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
{
errorcode = HAL_ERROR;
goto error;
@ -886,10 +886,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
pTxData += sizeof(uint16_t);
hspi->TxXferCount--;
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
while ((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
{
/* Check TXE flag */
if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
if(txallowed && (hspi->TxXferCount > 0) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
{
hspi->Instance->DR = *((uint16_t *)pTxData);
pTxData += sizeof(uint16_t);
@ -899,7 +899,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
@ -907,7 +907,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
/* Check RXNE flag */
if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
if((hspi->RxXferCount > 0) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
{
*((uint16_t *)pRxData) = hspi->Instance->DR;
pRxData += sizeof(uint16_t);
@ -931,10 +931,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
pTxData += sizeof(uint8_t);
hspi->TxXferCount--;
}
while((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
{
/* check TXE flag */
if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
if(txallowed && (hspi->TxXferCount > 0) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
{
*(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
hspi->TxXferCount--;
@ -943,7 +943,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
@ -951,7 +951,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
/* Wait until RXNE flag is reset */
if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
if((hspi->RxXferCount > 0) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
{
(*(uint8_t *)pRxData++) = hspi->Instance->DR;
hspi->RxXferCount--;
@ -1040,7 +1040,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Process Locked */
__HAL_LOCK(hspi);
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
errorcode = HAL_ERROR;
goto error;
@ -1061,8 +1061,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
hspi->RxXferSize = 0U;
hspi->RxXferCount = 0U;
hspi->RxXferSize = 0;
hspi->RxXferCount = 0;
hspi->RxISR = NULL;
/* Set the function for IT treatment */
@ -1140,7 +1140,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
goto error;
}
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
errorcode = HAL_ERROR;
goto error;
@ -1155,8 +1155,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
/* Init field not used in handle to zero */
hspi->pTxBuffPtr = (uint8_t *)NULL;
hspi->TxXferSize = 0U;
hspi->TxXferCount = 0U;
hspi->TxXferSize = 0;
hspi->TxXferCount = 0;
hspi->TxISR = NULL;
/* Set the function for IT treatment */
@ -1233,7 +1233,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
goto error;
}
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
{
errorcode = HAL_ERROR;
goto error;
@ -1314,7 +1314,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
goto error;
}
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
errorcode = HAL_ERROR;
goto error;
@ -1331,8 +1331,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
hspi->pRxBuffPtr = (uint8_t *)NULL;
hspi->TxISR = NULL;
hspi->RxISR = NULL;
hspi->RxXferSize = 0U;
hspi->RxXferCount = 0U;
hspi->RxXferSize = 0;
hspi->RxXferCount = 0;
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
@ -1411,7 +1411,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
goto error;
}
if((pData == NULL) || (Size == 0U))
if((pData == NULL) || (Size == 0))
{
errorcode = HAL_ERROR;
goto error;
@ -1427,8 +1427,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/*Init field not used in handle to zero */
hspi->RxISR = NULL;
hspi->TxISR = NULL;
hspi->TxXferSize = 0U;
hspi->TxXferCount = 0U;
hspi->TxXferSize = 0;
hspi->TxXferCount = 0;
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
@ -1508,7 +1508,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
goto error;
}
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
{
errorcode = HAL_ERROR;
goto error;
@ -1918,7 +1918,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
hspi->TxXferCount = 0U;
hspi->TxXferCount = 0;
hspi->State = HAL_SPI_STATE_READY;
if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
@ -1941,7 +1941,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
#if (USE_SPI_CRC != 0U)
uint32_t tickstart = 0U;
__IO uint16_t tmpreg = 0U;
__IO uint16_t tmpreg = 0;
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@ -1975,7 +1975,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
__HAL_SPI_DISABLE(hspi);
}
hspi->RxXferCount = 0U;
hspi->RxXferCount = 0;
hspi->State = HAL_SPI_STATE_READY;
#if (USE_SPI_CRC != 0U)
@ -2007,7 +2007,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
uint32_t tickstart = 0U;
#if (USE_SPI_CRC != 0U)
__IO int16_t tmpreg = 0U;
__IO int16_t tmpreg = 0;
#endif /* USE_SPI_CRC */
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@ -2038,8 +2038,8 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
/* Disable Rx/Tx DMA Request */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
hspi->TxXferCount = 0U;
hspi->RxXferCount = 0U;
hspi->TxXferCount = 0;
hspi->RxXferCount = 0;
hspi->State = HAL_SPI_STATE_READY;
#if (USE_SPI_CRC != 0U)
@ -2145,7 +2145,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
hspi->RxXferCount--;
/* check end of the reception */
if(hspi->RxXferCount == 0U)
if(hspi->RxXferCount == 0)
{
#if (USE_SPI_CRC != 0U)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
@ -2158,7 +2158,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
if(hspi->TxXferCount == 0U)
if(hspi->TxXferCount == 0)
{
SPI_CloseRxTx_ISR(hspi);
}
@ -2186,7 +2186,7 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
if(hspi->TxXferCount == 0U)
if(hspi->TxXferCount == 0)
{
SPI_CloseRxTx_ISR(hspi);
}
@ -2205,7 +2205,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
hspi->TxXferCount--;
/* check the end of the transmission */
if(hspi->TxXferCount == 0U)
if(hspi->TxXferCount == 0)
{
#if (USE_SPI_CRC != 0U)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
@ -2219,7 +2219,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
/* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
if(hspi->RxXferCount == 0U)
if(hspi->RxXferCount == 0)
{
SPI_CloseRxTx_ISR(hspi);
}
@ -2239,7 +2239,7 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
if(hspi->RxXferCount == 0U)
if(hspi->RxXferCount == 0)
{
#if (USE_SPI_CRC != 0U)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
@ -2252,7 +2252,7 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
if(hspi->TxXferCount == 0U)
if(hspi->TxXferCount == 0)
{
SPI_CloseRxTx_ISR(hspi);
}
@ -2269,7 +2269,7 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
/* Receive data in 16 Bit mode */
__IO uint16_t tmpreg = 0U;
__IO uint16_t tmpreg = 0;
/* Read data register to flush CRC */
tmpreg = hspi->Instance->DR;
@ -2298,7 +2298,7 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
hspi->TxXferCount--;
/* Enable CRC Transmission */
if(hspi->TxXferCount == 0U)
if(hspi->TxXferCount == 0)
{
#if (USE_SPI_CRC != 0U)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
@ -2312,7 +2312,7 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
/* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
if(hspi->RxXferCount == 0U)
if(hspi->RxXferCount == 0)
{
SPI_CloseRxTx_ISR(hspi);
}
@ -2328,7 +2328,7 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
__IO uint8_t tmpreg = 0U;
__IO uint8_t tmpreg = 0;
/* Read data register to flush CRC */
tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
@ -2353,13 +2353,13 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
if(hspi->RxXferCount == 0U)
if(hspi->RxXferCount == 0)
{
#if (USE_SPI_CRC != 0U)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
@ -2381,7 +2381,7 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
__IO uint16_t tmpreg = 0U;
__IO uint16_t tmpreg = 0;
/* Read data register to flush CRC */
tmpreg = hspi->Instance->DR;
@ -2410,13 +2410,13 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
if(hspi->RxXferCount == 0U)
if(hspi->RxXferCount == 0)
{
#if (USE_SPI_CRC != 0U)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
@ -2440,7 +2440,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
*(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
hspi->TxXferCount--;
if(hspi->TxXferCount == 0U)
if(hspi->TxXferCount == 0)
{
#if (USE_SPI_CRC != 0U)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
@ -2466,7 +2466,7 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
if(hspi->TxXferCount == 0U)
if(hspi->TxXferCount == 0)
{
#if (USE_SPI_CRC != 0U)
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
@ -2556,7 +2556,7 @@ static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Tim
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
{
uint32_t tickstart = 0U;
__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000);
__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
@ -2566,7 +2566,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
/* Wait until TXE flag is set */
do
{
if(count-- == 0)
if(count-- == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
break;
@ -2679,7 +2679,7 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
{
uint32_t tickstart = 0U;
__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000);
__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@ -2687,7 +2687,7 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
/* Wait until TXE flag is set */
do
{
if(count-- == 0)
if(count-- == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
break;

56
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_spi.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_spi.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -165,13 +165,13 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Error_Code SPI Error Code
* @{
*/
#define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001U) /*!< MODF error */
#define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002U) /*!< CRC error */
#define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004U) /*!< OVR error */
#define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008U) /*!< FRE error */
#define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020U) /*!< Flag: RXNE,TXE, BSY */
#define HAL_SPI_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_SPI_ERROR_MODF 0x00000001U /*!< MODF error */
#define HAL_SPI_ERROR_CRC 0x00000002U /*!< CRC error */
#define HAL_SPI_ERROR_OVR 0x00000004U /*!< OVR error */
#define HAL_SPI_ERROR_FRE 0x00000008U /*!< FRE error */
#define HAL_SPI_ERROR_DMA 0x00000010U /*!< DMA transfer error */
#define HAL_SPI_ERROR_FLAG 0x00000020U /*!< Flag: RXNE,TXE, BSY */
/**
* @}
*/
@ -179,7 +179,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Mode SPI Mode
* @{
*/
#define SPI_MODE_SLAVE ((uint32_t)0x00000000U)
#define SPI_MODE_SLAVE 0x00000000U
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
/**
* @}
@ -188,7 +188,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Direction SPI Direction Mode
* @{
*/
#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000U)
#define SPI_DIRECTION_2LINES 0x00000000U
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
/**
@ -198,7 +198,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Data_Size SPI Data Size
* @{
*/
#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000U)
#define SPI_DATASIZE_8BIT 0x00000000U
#define SPI_DATASIZE_16BIT SPI_CR1_DFF
/**
* @}
@ -207,7 +207,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
* @{
*/
#define SPI_POLARITY_LOW ((uint32_t)0x00000000U)
#define SPI_POLARITY_LOW 0x00000000U
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
/**
* @}
@ -216,7 +216,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Clock_Phase SPI Clock Phase
* @{
*/
#define SPI_PHASE_1EDGE ((uint32_t)0x00000000U)
#define SPI_PHASE_1EDGE 0x00000000U
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
/**
* @}
@ -226,8 +226,8 @@ typedef struct __SPI_HandleTypeDef
* @{
*/
#define SPI_NSS_SOFT SPI_CR1_SSM
#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U)
#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000U)
#define SPI_NSS_HARD_INPUT 0x00000000U
#define SPI_NSS_HARD_OUTPUT 0x00040000U
/**
* @}
*/
@ -235,14 +235,14 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
* @{
*/
#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000U)
#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008U)
#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010U)
#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018U)
#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020U)
#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028U)
#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030U)
#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038U)
#define SPI_BAUDRATEPRESCALER_2 0x00000000U
#define SPI_BAUDRATEPRESCALER_4 0x00000008U
#define SPI_BAUDRATEPRESCALER_8 0x00000010U
#define SPI_BAUDRATEPRESCALER_16 0x00000018U
#define SPI_BAUDRATEPRESCALER_32 0x00000020U
#define SPI_BAUDRATEPRESCALER_64 0x00000028U
#define SPI_BAUDRATEPRESCALER_128 0x00000030U
#define SPI_BAUDRATEPRESCALER_256 0x00000038U
/**
* @}
*/
@ -250,7 +250,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
* @{
*/
#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000U)
#define SPI_FIRSTBIT_MSB 0x00000000U
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
/**
* @}
@ -259,7 +259,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_TI_mode SPI TI Mode
* @{
*/
#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000U)
#define SPI_TIMODE_DISABLE 0x00000000U
#define SPI_TIMODE_ENABLE SPI_CR2_FRF
/**
* @}
@ -268,7 +268,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
* @{
*/
#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U)
#define SPI_CRCCALCULATION_DISABLE 0x00000000U
#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
/**
* @}

6
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_sram.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_sram.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief SRAM HAL module driver.
* This file provides a generic firmware to drive SRAM memories
* mounted as external device.
@ -64,7 +64,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

6
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_sram.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_sram.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of SRAM HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

54
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_tim.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_tim.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
@ -98,7 +98,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -217,6 +217,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if(htim->State == HAL_TIM_STATE_RESET)
{
@ -404,7 +405,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
}
else if((htim->State == HAL_TIM_STATE_READY))
{
if((pData == 0 ) && (Length > 0))
if((pData == 0U ) && (Length > 0))
{
return HAL_ERROR;
}
@ -499,7 +500,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if(htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@ -803,7 +805,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
}
else if((htim->State == HAL_TIM_STATE_READY))
{
if(((uint32_t)pData == 0U ) && (Length > 0U))
if(((uint32_t)pData == 0U ) && (Length > 0))
{
return HAL_ERROR;
}
@ -1011,7 +1013,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if(htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@ -1318,7 +1321,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
}
else if((htim->State == HAL_TIM_STATE_READY))
{
if(((uint32_t)pData == 0U ) && (Length > 0U))
if(((uint32_t)pData == 0U ) && (Length > 0))
{
return HAL_ERROR;
}
@ -1526,7 +1529,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if(htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@ -1806,7 +1810,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
}
else if((htim->State == HAL_TIM_STATE_READY))
{
if((pData == 0U ) && (Length > 0U))
if((pData == 0U ) && (Length > 0))
{
return HAL_ERROR;
}
@ -2008,6 +2012,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
assert_param(IS_TIM_OPM_MODE(OnePulseMode));
if(htim->State == HAL_TIM_STATE_RESET)
@ -2115,6 +2120,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
/* Prevent unused argument(s) compilation warning */
UNUSED(OutputChannel);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
@ -2145,7 +2153,10 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
/* Prevent unused argument(s) compilation warning */
UNUSED(OutputChannel);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
@ -2182,7 +2193,10 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
/* Prevent unused argument(s) compilation warning */
UNUSED(OutputChannel);
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
@ -2214,6 +2228,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(OutputChannel);
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
@ -2286,6 +2303,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
@ -2626,7 +2646,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
}
else if((htim->State == HAL_TIM_STATE_READY))
{
if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0))
{
return HAL_ERROR;
}
@ -3604,7 +3624,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
}
else if((htim->State == HAL_TIM_STATE_READY))
{
if((BurstBuffer == 0 ) && (BurstLength > 0))
if((BurstBuffer == 0U ) && (BurstLength > 0U))
{
return HAL_ERROR;
}
@ -4488,6 +4508,10 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
tmpcr1 |= (uint32_t)Structure->ClockDivision;
}
/* Set the auto-reload preload */
tmpcr1 &= ~TIM_CR1_ARPE;
tmpcr1 |= (uint32_t)Structure->AutoReloadPreload;
TIMx->CR1 = tmpcr1;
/* Set the Auto-reload value */
@ -5024,7 +5048,7 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
/* Write to TIMx CCMR1 and CCER registers */
htim->Instance->CCMR1 = tmpccmr1;

418
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_tim.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_tim.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -85,6 +85,9 @@ typedef struct
- the number of half PWM period in center-aligned mode
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
@note This parameter is valid only for TIM1 and TIM8. */
uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
This parameter can be a value of @ref TIM_AutoReloadPreload */
} TIM_Base_InitTypeDef;
/**
@ -308,7 +311,7 @@ typedef struct
/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
* @{
*/
#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U) /*!< Polarity for TIx source */
#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
/**
@ -319,7 +322,7 @@ typedef struct
* @{
*/
#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000U) /*!< Polarity for ETR source */
#define TIM_ETRPOLARITY_NONINVERTED 0x0000U /*!< Polarity for ETR source */
/**
* @}
*/
@ -327,7 +330,7 @@ typedef struct
/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
* @{
*/
#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000U) /*!< No prescaler is used */
#define TIM_ETRPRESCALER_DIV1 0x0000U /*!< No prescaler is used */
#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
@ -338,7 +341,7 @@ typedef struct
/** @defgroup TIM_Counter_Mode TIM Counter Mode
* @{
*/
#define TIM_COUNTERMODE_UP ((uint32_t)0x0000U)
#define TIM_COUNTERMODE_UP 0x0000U
#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
@ -350,9 +353,19 @@ typedef struct
/** @defgroup TIM_ClockDivision TIM Clock Division
* @{
*/
#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000U)
#define TIM_CLOCKDIVISION_DIV1 0x0000U
#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
/**
* @}
*/
/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
* @{
*/
#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x0000U /*!< TIMx_ARR register is not buffered */
#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */
/**
* @}
*/
@ -360,7 +373,7 @@ typedef struct
/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
* @{
*/
#define TIM_OCMODE_TIMING ((uint32_t)0x0000U)
#define TIM_OCMODE_TIMING 0x0000U
#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
@ -376,7 +389,7 @@ typedef struct
/** @defgroup TIM_Output_Fast_State TIM Output Fast State
* @{
*/
#define TIM_OCFAST_DISABLE ((uint32_t)0x0000U)
#define TIM_OCFAST_DISABLE 0x0000U
#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
/**
* @}
@ -385,7 +398,7 @@ typedef struct
/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
* @{
*/
#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000U)
#define TIM_OCPOLARITY_HIGH 0x0000U
#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
/**
* @}
@ -394,7 +407,7 @@ typedef struct
/** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
* @{
*/
#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000U)
#define TIM_OCNPOLARITY_HIGH 0x0000U
#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
/**
* @}
@ -404,7 +417,7 @@ typedef struct
* @{
*/
#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000U)
#define TIM_OCIDLESTATE_RESET 0x0000U
/**
* @}
*/
@ -413,7 +426,7 @@ typedef struct
* @{
*/
#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000U)
#define TIM_OCNIDLESTATE_RESET 0x0000U
/**
* @}
*/
@ -421,10 +434,10 @@ typedef struct
/** @defgroup TIM_Channel TIM Channel
* @{
*/
#define TIM_CHANNEL_1 ((uint32_t)0x0000U)
#define TIM_CHANNEL_2 ((uint32_t)0x0004U)
#define TIM_CHANNEL_3 ((uint32_t)0x0008U)
#define TIM_CHANNEL_4 ((uint32_t)0x000CU)
#define TIM_CHANNEL_1 0x0000U
#define TIM_CHANNEL_2 0x0004U
#define TIM_CHANNEL_3 0x0008U
#define TIM_CHANNEL_4 0x000CU
#define TIM_CHANNEL_ALL ((uint32_t)0x0018U)
/**
@ -457,7 +470,7 @@ typedef struct
/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
* @{
*/
#define TIM_ICPSC_DIV1 ((uint32_t)0x0000U) /*!< Capture performed each time an edge is detected on the capture input */
#define TIM_ICPSC_DIV1 0x0000U /*!< Capture performed each time an edge is detected on the capture input */
#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
@ -469,7 +482,7 @@ typedef struct
* @{
*/
#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000U)
#define TIM_OPMODE_REPETITIVE 0x0000U
/**
* @}
*/
@ -504,7 +517,7 @@ typedef struct
* @{
*/
#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000U)
#define TIM_COMMUTATION_SOFTWARE 0x0000U
/**
* @}
*/
@ -563,7 +576,7 @@ typedef struct
*/
#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000U)
#define TIM_CLOCKSOURCE_ITR0 0x0000U
#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
@ -601,8 +614,8 @@ typedef struct
/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
* @{
*/
#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U)
#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U)
#define TIM_CLEARINPUTSOURCE_ETR 0x0001U
#define TIM_CLEARINPUTSOURCE_NONE 0x0000U
/**
* @}
*/
@ -630,8 +643,8 @@ typedef struct
/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
* @{
*/
#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
#define TIM_OSSR_DISABLE ((uint32_t)0x0000U)
#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
#define TIM_OSSR_DISABLE 0x0000U
/**
* @}
*/
@ -639,8 +652,8 @@ typedef struct
/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
* @{
*/
#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
#define TIM_OSSI_DISABLE ((uint32_t)0x0000U)
#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
#define TIM_OSSI_DISABLE 0x0000U
/**
* @}
*/
@ -648,7 +661,7 @@ typedef struct
/** @defgroup TIM_Lock_level TIM Lock level
* @{
*/
#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000U)
#define TIM_LOCKLEVEL_OFF 0x0000U
#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
@ -657,9 +670,9 @@ typedef struct
*/
/** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
* @{
*/
*/
#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
#define TIM_BREAK_DISABLE ((uint32_t)0x0000U)
#define TIM_BREAK_DISABLE 0x0000U
/**
* @}
*/
@ -667,7 +680,7 @@ typedef struct
/** @defgroup TIM_Break_Polarity TIM Break Polarity
* @{
*/
#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000U)
#define TIM_BREAKPOLARITY_LOW 0x0000U
#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
/**
* @}
@ -677,7 +690,7 @@ typedef struct
* @{
*/
#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000U)
#define TIM_AUTOMATICOUTPUT_DISABLE 0x0000U
/**
* @}
*/
@ -685,14 +698,14 @@ typedef struct
/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
* @{
*/
#define TIM_TRGO_RESET ((uint32_t)0x0000U)
#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define TIM_TRGO_RESET 0x0000U
#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
/**
* @}
*/
@ -700,11 +713,11 @@ typedef struct
/** @defgroup TIM_Slave_Mode TIM Slave Mode
* @{
*/
#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000U)
#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004U)
#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005U)
#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006U)
#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007U)
#define TIM_SLAVEMODE_DISABLE 0x0000U
#define TIM_SLAVEMODE_RESET 0x0004U
#define TIM_SLAVEMODE_GATED 0x0005U
#define TIM_SLAVEMODE_TRIGGER 0x0006U
#define TIM_SLAVEMODE_EXTERNAL1 0x0007U
/**
* @}
*/
@ -712,8 +725,8 @@ typedef struct
/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
* @{
*/
#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080U)
#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000U)
#define TIM_MASTERSLAVEMODE_ENABLE 0x0080U
#define TIM_MASTERSLAVEMODE_DISABLE 0x0000U
/**
* @}
*/
@ -721,15 +734,15 @@ typedef struct
/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
* @{
*/
#define TIM_TS_ITR0 ((uint32_t)0x0000U)
#define TIM_TS_ITR1 ((uint32_t)0x0010U)
#define TIM_TS_ITR2 ((uint32_t)0x0020U)
#define TIM_TS_ITR3 ((uint32_t)0x0030U)
#define TIM_TS_TI1F_ED ((uint32_t)0x0040U)
#define TIM_TS_TI1FP1 ((uint32_t)0x0050U)
#define TIM_TS_TI2FP2 ((uint32_t)0x0060U)
#define TIM_TS_ETRF ((uint32_t)0x0070U)
#define TIM_TS_NONE ((uint32_t)0xFFFFU)
#define TIM_TS_ITR0 0x0000U
#define TIM_TS_ITR1 0x0010U
#define TIM_TS_ITR2 0x0020U
#define TIM_TS_ITR3 0x0030U
#define TIM_TS_TI1F_ED 0x0040U
#define TIM_TS_TI1FP1 0x0050U
#define TIM_TS_TI2FP2 0x0060U
#define TIM_TS_ETRF 0x0070U
#define TIM_TS_NONE 0xFFFFU
/**
* @}
*/
@ -737,8 +750,8 @@ typedef struct
/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
* @{
*/
#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
@ -761,7 +774,7 @@ typedef struct
/** @defgroup TIM_TI1_Selection TIM TI1 Selection
* @{
*/
#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000U)
#define TIM_TI1SELECTION_CH1 0x0000U
#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
/**
* @}
@ -770,26 +783,26 @@ typedef struct
/** @defgroup TIM_DMA_Base_address TIM DMA Base address
* @{
*/
#define TIM_DMABASE_CR1 (0x00000000U)
#define TIM_DMABASE_CR2 (0x00000001U)
#define TIM_DMABASE_SMCR (0x00000002U)
#define TIM_DMABASE_DIER (0x00000003U)
#define TIM_DMABASE_SR (0x00000004U)
#define TIM_DMABASE_EGR (0x00000005U)
#define TIM_DMABASE_CCMR1 (0x00000006U)
#define TIM_DMABASE_CCMR2 (0x00000007U)
#define TIM_DMABASE_CCER (0x00000008U)
#define TIM_DMABASE_CNT (0x00000009U)
#define TIM_DMABASE_PSC (0x0000000AU)
#define TIM_DMABASE_ARR (0x0000000BU)
#define TIM_DMABASE_RCR (0x0000000CU)
#define TIM_DMABASE_CCR1 (0x0000000DU)
#define TIM_DMABASE_CCR2 (0x0000000EU)
#define TIM_DMABASE_CCR3 (0x0000000FU)
#define TIM_DMABASE_CCR4 (0x00000010U)
#define TIM_DMABASE_BDTR (0x00000011U)
#define TIM_DMABASE_DCR (0x00000012U)
#define TIM_DMABASE_OR (0x00000013U)
#define TIM_DMABASE_CR1 0x00000000U
#define TIM_DMABASE_CR2 0x00000001U
#define TIM_DMABASE_SMCR 0x00000002U
#define TIM_DMABASE_DIER 0x00000003U
#define TIM_DMABASE_SR 0x00000004U
#define TIM_DMABASE_EGR 0x00000005U
#define TIM_DMABASE_CCMR1 0x00000006U
#define TIM_DMABASE_CCMR2 0x00000007U
#define TIM_DMABASE_CCER 0x00000008U
#define TIM_DMABASE_CNT 0x00000009U
#define TIM_DMABASE_PSC 0x0000000AU
#define TIM_DMABASE_ARR 0x0000000BU
#define TIM_DMABASE_RCR 0x0000000CU
#define TIM_DMABASE_CCR1 0x0000000DU
#define TIM_DMABASE_CCR2 0x0000000EU
#define TIM_DMABASE_CCR3 0x0000000FU
#define TIM_DMABASE_CCR4 0x00000010U
#define TIM_DMABASE_BDTR 0x00000011U
#define TIM_DMABASE_DCR 0x00000012U
#define TIM_DMABASE_OR 0x00000013U
/**
* @}
*/
@ -797,24 +810,24 @@ typedef struct
/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{
*/
#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
/**
* @}
*/
@ -822,13 +835,13 @@ typedef struct
/** @defgroup DMA_Handle_index DMA Handle index
* @{
*/
#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */
#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */
#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */
#define TIM_DMA_ID_UPDATE (uint16_t)0x00 /*!< Index of the DMA handle used for Update DMA requests */
#define TIM_DMA_ID_CC1 (uint16_t)0x01 /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
#define TIM_DMA_ID_CC2 (uint16_t)0x02 /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
#define TIM_DMA_ID_CC3 (uint16_t)0x03 /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
#define TIM_DMA_ID_CC4 (uint16_t)0x04 /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
#define TIM_DMA_ID_COMMUTATION (uint16_t)0x05 /*!< Index of the DMA handle used for Commutation DMA requests */
#define TIM_DMA_ID_TRIGGER (uint16_t)0x06 /*!< Index of the DMA handle used for Trigger DMA requests */
/**
* @}
*/
@ -836,10 +849,10 @@ typedef struct
/** @defgroup Channel_CC_State Channel CC State
* @{
*/
#define TIM_CCx_ENABLE ((uint32_t)0x0001U)
#define TIM_CCx_DISABLE ((uint32_t)0x0000U)
#define TIM_CCxN_ENABLE ((uint32_t)0x0004U)
#define TIM_CCxN_DISABLE ((uint32_t)0x0000U)
#define TIM_CCx_ENABLE 0x0001U
#define TIM_CCx_DISABLE 0x0000U
#define TIM_CCxN_ENABLE 0x0004U
#define TIM_CCxN_DISABLE 0x0000U
/**
* @}
*/
@ -907,17 +920,172 @@ typedef struct
} \
} while(0)
/**
* @brief Disable the TIM main Output.
* @param __HANDLE__: TIM handle
* @retval None
* @note The Main Output Enable of a timer instance is disabled unconditionally
*/
#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
/** @brief Enable the specified TIM interrupt.
* @param __HANDLE__: specifies the TIM Handle.
* @param __INTERRUPT__: specifies the TIM interrupt source to enable.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
* @arg TIM_IT_COM: Commutation interrupt
* @arg TIM_IT_TRIGGER: Trigger interrupt
* @arg TIM_IT_BREAK: Break interrupt
* @retval None
*/
#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
/** @brief Disable the specified TIM interrupt.
* @param __HANDLE__: specifies the TIM Handle.
* @param __INTERRUPT__: specifies the TIM interrupt source to disable.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
* @arg TIM_IT_COM: Commutation interrupt
* @arg TIM_IT_TRIGGER: Trigger interrupt
* @arg TIM_IT_BREAK: Break interrupt
* @retval None
*/
#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
/** @brief Enable the specified DMA request.
* @param __HANDLE__: specifies the TIM Handle.
* @param __DMA__: specifies the TIM DMA request to enable.
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: Update DMA request
* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
* @arg TIM_DMA_COM: Commutation DMA request
* @arg TIM_DMA_TRIGGER: Trigger DMA request
* @retval None
*/
#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
/** @brief Disable the specified DMA request.
* @param __HANDLE__: specifies the TIM Handle.
* @param __DMA__: specifies the TIM DMA request to disable.
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: Update DMA request
* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
* @arg TIM_DMA_COM: Commutation DMA request
* @arg TIM_DMA_TRIGGER: Trigger DMA request
* @retval None
*/
#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
/** @brief Check whether the specified TIM interrupt flag is set or not.
* @param __HANDLE__: specifies the TIM Handle.
* @param __FLAG__: specifies the TIM interrupt flag to check.
* This parameter can be one of the following values:
* @arg TIM_FLAG_UPDATE: Update interrupt flag
* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
* @arg TIM_FLAG_CC5: Compare 5 interrupt flag
* @arg TIM_FLAG_CC6: Compare 6 interrupt flag
* @arg TIM_FLAG_COM: Commutation interrupt flag
* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
* @arg TIM_FLAG_BREAK: Break interrupt flag
* @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
* @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
/** @brief Clear the specified TIM interrupt flag.
* @param __HANDLE__: specifies the TIM Handle.
* @param __FLAG__: specifies the TIM interrupt flag to clear.
* This parameter can be one of the following values:
* @arg TIM_FLAG_UPDATE: Update interrupt flag
* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
* @arg TIM_FLAG_CC5: Compare 5 interrupt flag
* @arg TIM_FLAG_CC6: Compare 6 interrupt flag
* @arg TIM_FLAG_COM: Commutation interrupt flag
* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
* @arg TIM_FLAG_BREAK: Break interrupt flag
* @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
* @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/**
* @brief Check whether the specified TIM interrupt source is enabled or not.
* @param __HANDLE__: TIM handle
* @param __INTERRUPT__: specifies the TIM interrupt source to check.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
* @arg TIM_IT_COM: Commutation interrupt
* @arg TIM_IT_TRIGGER: Trigger interrupt
* @arg TIM_IT_BREAK: Break interrupt
* @retval The state of TIM_IT (SET or RESET).
*/
#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Clear the TIM interrupt pending bits.
* @param __HANDLE__: TIM handle
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
* @arg TIM_IT_COM: Commutation interrupt
* @arg TIM_IT_TRIGGER: Trigger interrupt
* @arg TIM_IT_BREAK: Break interrupt
* @retval None
*/
#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
/**
* @brief Indicates whether or not the TIM Counter is used as downcounter.
* @param __HANDLE__: TIM handle.
* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
mode.
*/
#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
/**
* @brief Set the TIM Prescaler on runtime.
* @param __HANDLE__: TIM handle.
* @param __PRESC__: specifies the Prescaler new value.
* @retval None
*/
#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
@ -969,7 +1137,7 @@ typedef struct
* @arg TIM_CHANNEL_2: get capture/compare 2 register value
* @arg TIM_CHANNEL_3: get capture/compare 3 register value
* @arg TIM_CHANNEL_4: get capture/compare 4 register value
* @retval None
* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
*/
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
@ -985,7 +1153,7 @@ typedef struct
/**
* @brief Gets the TIM Counter Register value on runtime.
* @param __HANDLE__: TIM handle.
* @retval None
* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
*/
#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
@ -1004,7 +1172,7 @@ typedef struct
/**
* @brief Gets the TIM Autoreload Register value on runtime
* @param __HANDLE__: TIM handle.
* @retval None
* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
*/
#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
@ -1014,9 +1182,9 @@ typedef struct
* @param __HANDLE__: TIM handle.
* @param __CKD__: specifies the clock division value.
* This parameter can be one of the following value:
* @arg TIM_CLOCKDIVISION_DIV1
* @arg TIM_CLOCKDIVISION_DIV2
* @arg TIM_CLOCKDIVISION_DIV4
* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
* @retval None
*/
#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
@ -1026,9 +1194,12 @@ typedef struct
(__HANDLE__)->Init.ClockDivision = (__CKD__); \
} while(0)
/**
* @brief Gets the TIM Clock Division value on runtime
* @brief Gets the TIM Clock Division value on runtime.
* @param __HANDLE__: TIM handle.
* @retval None
* @retval The clock division can be one of the following values:
* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
*/
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
@ -1057,7 +1228,7 @@ typedef struct
} while(0)
/**
* @brief Gets the TIM Input Capture prescaler on runtime
* @brief Gets the TIM Input Capture prescaler on runtime.
* @param __HANDLE__: TIM handle.
* @param __CHANNEL__ : TIM Channels to be configured.
* This parameter can be one of the following values:
@ -1065,7 +1236,11 @@ typedef struct
* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
* @retval None
* @retval The input capture prescaler can be one of the following values:
* @arg TIM_ICPSC_DIV1: no prescaler
* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
*/
#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
@ -1349,6 +1524,9 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
((DIV) == TIM_CLOCKDIVISION_DIV2) || \
((DIV) == TIM_CLOCKDIVISION_DIV4))
#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
((MODE) == TIM_OCMODE_PWM2))

50
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_tim_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_tim_ex.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer extension peripheral:
@ -69,7 +69,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -169,6 +169,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
@ -394,7 +395,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
}
else if((htim->State == HAL_TIM_STATE_READY))
{
if(((uint32_t)pData == 0U ) && (Length > 0U))
if(((uint32_t)pData == 0U ) && (Length > 0))
{
return HAL_ERROR;
}
@ -701,7 +702,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
}
else if((htim->State == HAL_TIM_STATE_READY))
{
if(((uint32_t)pData == 0U ) && (Length > 0U))
if(((uint32_t)pData == 0U ) && (Length > 0))
{
return HAL_ERROR;
}
@ -1119,7 +1120,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
}
else if((htim->State == HAL_TIM_STATE_READY))
{
if(((uint32_t)pData == 0U ) && (Length > 0U))
if(((uint32_t)pData == 0U ) && (Length > 0))
{
return HAL_ERROR;
}
@ -1655,39 +1656,42 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
* contains the BDTR Register configuration information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
{
uint32_t tmpbdtr = 0;
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
/* Process Locked */
/* Check input state */
__HAL_LOCK(htim);
htim->State = HAL_TIM_STATE_BUSY;
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode |
sBreakDeadTimeConfig->OffStateIDLEMode |
sBreakDeadTimeConfig->LockLevel |
sBreakDeadTimeConfig->DeadTime |
sBreakDeadTimeConfig->BreakState |
sBreakDeadTimeConfig->BreakPolarity |
sBreakDeadTimeConfig->AutomaticOutput;
htim->State = HAL_TIM_STATE_READY;
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
__HAL_UNLOCK(htim);
return HAL_OK;
}

61
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_tim_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_tim_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of TIM HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -120,16 +120,16 @@ typedef struct
/** @defgroup TIMEx_Remap TIM Remap
* @{
*/
#define TIM_TIM2_TIM8_TRGO (0x00000000U)
#define TIM_TIM2_ETH_PTP (0x00000400U)
#define TIM_TIM2_USBFS_SOF (0x00000800U)
#define TIM_TIM2_USBHS_SOF (0x00000C00U)
#define TIM_TIM5_GPIO (0x00000000U)
#define TIM_TIM5_LSI (0x00000040U)
#define TIM_TIM5_LSE (0x00000080U)
#define TIM_TIM5_RTC (0x000000C0U)
#define TIM_TIM11_GPIO (0x00000000U)
#define TIM_TIM11_HSE (0x00000002U)
#define TIM_TIM2_TIM8_TRGO 0x00000000U
#define TIM_TIM2_ETH_PTP 0x00000400U
#define TIM_TIM2_USBFS_SOF 0x00000800U
#define TIM_TIM2_USBHS_SOF 0x00000C00U
#define TIM_TIM5_GPIO 0x00000000U
#define TIM_TIM5_LSI 0x00000040U
#define TIM_TIM5_LSE 0x00000080U
#define TIM_TIM5_RTC 0x000000C0U
#define TIM_TIM11_GPIO 0x00000000U
#define TIM_TIM11_HSE 0x00000002U
/**
* @}
@ -277,6 +277,41 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
((TIM_REMAP) == TIM_TIM11_HSE))
#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU)
/**
* @brief Sets the TIM Output compare preload.
* @param __HANDLE__: TIM handle.
* @param __CHANNEL__: TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval None
*/
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
/**
* @brief Resets the TIM Output compare preload.
* @param __HANDLE__: TIM handle.
* @param __CHANNEL__: TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
/**
* @}
*/

651
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_uart.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_uart.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
@ -126,7 +126,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -188,6 +188,10 @@ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAError(DMA_HandleTypeDef *hdma);
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
@ -507,7 +511,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
HAL_UART_MspDeInit(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->gState = HAL_UART_STATE_RESET;
huart->gState = HAL_UART_STATE_RESET;
huart->RxState = HAL_UART_STATE_RESET;
/* Process Lock */
@ -619,7 +623,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
/* Check that a Tx process is not already ongoing */
if(huart->gState == HAL_UART_STATE_READY)
{
if((pData == NULL ) || (Size == 0U))
if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@ -635,7 +639,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
huart->TxXferSize = Size;
huart->TxXferCount = Size;
while(huart->TxXferCount > 0U)
while(huart->TxXferCount > 0)
{
huart->TxXferCount--;
if(huart->Init.WordLength == UART_WORDLENGTH_9B)
@ -645,7 +649,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
return HAL_TIMEOUT;
}
tmp = (uint16_t*) pData;
huart->Instance->DR = (*tmp & (uint16_t)0x01FFU);
huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
if(huart->Init.Parity == UART_PARITY_NONE)
{
pData +=2;
@ -661,7 +665,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
{
return HAL_TIMEOUT;
}
huart->Instance->DR = (*pData++ & (uint8_t)0xFFU);
huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
}
}
@ -701,7 +705,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
/* Check that a Rx process is not already ongoing */
if(huart->RxState == HAL_UART_STATE_READY)
{
if((pData == NULL ) || (Size == 0U))
if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@ -719,7 +723,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
huart->RxXferCount = Size;
/* Check the remain data to be received */
while(huart->RxXferCount > 0U)
while(huart->RxXferCount > 0)
{
huart->RxXferCount--;
if(huart->Init.WordLength == UART_WORDLENGTH_9B)
@ -731,12 +735,12 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
tmp = (uint16_t*) pData ;
if(huart->Init.Parity == UART_PARITY_NONE)
{
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FFU);
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
pData +=2;
}
else
{
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FFU);
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
pData +=1;
}
@ -749,11 +753,11 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
}
if(huart->Init.Parity == UART_PARITY_NONE)
{
*pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FFU);
*pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
}
else
{
*pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007FU);
*pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
}
}
@ -786,7 +790,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
/* Check that a Tx process is not already ongoing */
if(huart->gState == HAL_UART_STATE_READY)
{
if((pData == NULL ) || (Size == 0U))
if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@ -828,7 +832,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
/* Check that a Rx process is not already ongoing */
if(huart->RxState == HAL_UART_STATE_READY)
{
if((pData == NULL ) || (Size == 0U))
if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@ -875,7 +879,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
/* Check that a Tx process is not already ongoing */
if(huart->gState == HAL_UART_STATE_READY)
{
if((pData == NULL ) || (Size == 0U))
if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@ -940,7 +944,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
/* Check that a Rx process is not already ongoing */
if(huart->RxState == HAL_UART_STATE_READY)
{
if((pData == NULL ) || (Size == 0U))
if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
@ -953,7 +957,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
/* Set the UART DMA transfer complete callback */
huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
@ -970,19 +974,22 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size);
/* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
__HAL_UART_CLEAR_OREFLAG(huart);
/* Process Unlocked */
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error Interrupt */
SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the UART CR3 register */
SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
else
@ -1107,6 +1114,408 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
return HAL_OK;
}
/**
* @brief Abort ongoing transfers (blocking mode).
* @param huart UART handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
{
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Disable the UART DMA Tx request if enabled */
if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel: use blocking DMA Abort API (no callback) */
if(huart->hdmatx != NULL)
{
/* Set the UART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
huart->hdmatx->XferAbortCallback = NULL;
HAL_DMA_Abort(huart->hdmatx);
}
}
/* Disable the UART DMA Rx request if enabled */
if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel: use blocking DMA Abort API (no callback) */
if(huart->hdmarx != NULL)
{
/* Set the UART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = NULL;
HAL_DMA_Abort(huart->hdmarx);
}
}
/* Reset Tx and Rx transfer counters */
huart->TxXferCount = 0x00U;
huart->RxXferCount = 0x00U;
/* Reset ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
/* Restore huart->RxState and huart->gState to Ready */
huart->RxState = HAL_UART_STATE_READY;
huart->gState = HAL_UART_STATE_READY;
return HAL_OK;
}
/**
* @brief Abort ongoing Transmit transfer (blocking mode).
* @param huart UART handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
{
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Disable the UART DMA Tx request if enabled */
if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
if(huart->hdmatx != NULL)
{
/* Set the UART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
huart->hdmatx->XferAbortCallback = NULL;
HAL_DMA_Abort(huart->hdmatx);
}
}
/* Reset Tx transfer counter */
huart->TxXferCount = 0x00U;
/* Restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
return HAL_OK;
}
/**
* @brief Abort ongoing Receive transfer (blocking mode).
* @param huart UART handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Disable the UART DMA Rx request if enabled */
if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
if(huart->hdmarx != NULL)
{
/* Set the UART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = NULL;
HAL_DMA_Abort(huart->hdmarx);
}
}
/* Reset Rx transfer counter */
huart->RxXferCount = 0x00U;
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
return HAL_OK;
}
/**
* @brief Abort ongoing transfers (Interrupt mode).
* @param huart UART handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
{
uint32_t AbortCplt = 0x01U;
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
if(huart->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
Otherwise, set it to NULL */
if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
}
else
{
huart->hdmatx->XferAbortCallback = NULL;
}
}
/* DMA Rx Handle is valid */
if(huart->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
Otherwise, set it to NULL */
if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
}
else
{
huart->hdmarx->XferAbortCallback = NULL;
}
}
/* Disable the UART DMA Tx request if enabled */
if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at UART level */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
if(huart->hdmatx != NULL)
{
/* UART Tx DMA Abort callback has already been initialised :
will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA TX */
if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
{
huart->hdmatx->XferAbortCallback = NULL;
}
else
{
AbortCplt = 0x00U;
}
}
}
/* Disable the UART DMA Rx request if enabled */
if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
if(huart->hdmarx != NULL)
{
/* UART Rx DMA Abort callback has already been initialised :
will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA RX */
if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
{
huart->hdmarx->XferAbortCallback = NULL;
AbortCplt = 0x01U;
}
else
{
AbortCplt = 0x00U;
}
}
}
/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
if(AbortCplt == 0x01U)
{
/* Reset Tx and Rx transfer counters */
huart->TxXferCount = 0x00U;
huart->RxXferCount = 0x00U;
/* Reset ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
/* Restore huart->gState and huart->RxState to Ready */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
HAL_UART_AbortCpltCallback(huart);
}
return HAL_OK;
}
/**
* @brief Abort ongoing Transmit transfer (Interrupt mode).
* @param huart UART handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
{
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Disable the UART DMA Tx request if enabled */
if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
if(huart->hdmatx != NULL)
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
/* Abort DMA TX */
if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
{
/* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
huart->hdmatx->XferAbortCallback(huart->hdmatx);
}
}
else
{
/* Reset Tx transfer counter */
huart->TxXferCount = 0x00U;
/* Restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
HAL_UART_AbortTransmitCpltCallback(huart);
}
}
else
{
/* Reset Tx transfer counter */
huart->TxXferCount = 0x00U;
/* Restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
HAL_UART_AbortTransmitCpltCallback(huart);
}
return HAL_OK;
}
/**
* @brief Abort ongoing Receive transfer (Interrupt mode).
* @param huart UART handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Disable the UART DMA Rx request if enabled */
if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
if(huart->hdmarx != NULL)
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
/* Abort DMA RX */
if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
{
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
}
}
else
{
/* Reset Rx transfer counter */
huart->RxXferCount = 0x00U;
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
HAL_UART_AbortReceiveCpltCallback(huart);
}
}
else
{
/* Reset Rx transfer counter */
huart->RxXferCount = 0x00U;
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
HAL_UART_AbortReceiveCpltCallback(huart);
}
return HAL_OK;
}
/**
* @brief This function handles UART interrupt request.
* @param huart: pointer to a UART_HandleTypeDef structure that contains
@ -1309,6 +1718,50 @@ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
*/
}
/**
* @brief UART Abort Complete callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_AbortCpltCallback can be implemented in the user file.
*/
}
/**
* @brief UART Abort Complete callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
*/
}
/**
* @brief UART Abort Receive Complete callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
*/
}
/**
* @}
*/
@ -1419,7 +1872,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
*/
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
{
uint32_t tmpreg = 0x00;
uint32_t tmpreg = 0x00U;
/* Process Locked */
__HAL_LOCK(huart);
@ -1544,7 +1997,7 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
/* DMA Normal mode*/
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
{
huart->TxXferCount = 0U;
huart->TxXferCount = 0;
/* Disable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
@ -1585,7 +2038,7 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
/* DMA Normal mode*/
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
{
huart->RxXferCount = 0U;
huart->RxXferCount = 0;
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
@ -1628,7 +2081,7 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma)
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
{
huart->TxXferCount = 0U;
huart->TxXferCount = 0;
UART_EndTxTransfer(huart);
}
@ -1636,7 +2089,7 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma)
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
{
huart->RxXferCount = 0U;
huart->RxXferCount = 0;
UART_EndRxTransfer(huart);
}
@ -1650,8 +2103,8 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma)
* the configuration information for the specified UART module.
* @param Flag: specifies the UART flag to check.
* @param Status: The new Flag status (SET or RESET).
* @param Timeout: Timeout duration
* @param Tickstart Tick start value
* @param Timeout: Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
@ -1720,12 +2173,130 @@ static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
huart->RxXferCount = 0U;
huart->TxXferCount = 0U;
huart->RxXferCount = 0;
huart->TxXferCount = 0;
HAL_UART_ErrorCallback(huart);
}
/**
* @brief DMA UART Tx communication abort callback, when initiated by user
* (To be called at end of DMA Tx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Rx DMA Handle.
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
huart->hdmatx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
if(huart->hdmarx != NULL)
{
if(huart->hdmarx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
huart->TxXferCount = 0x00U;
huart->RxXferCount = 0x00U;
/* Reset ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
/* Restore huart->gState and huart->RxState to Ready */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
/* Call user Abort complete callback */
HAL_UART_AbortCpltCallback(huart);
}
/**
* @brief DMA UART Rx communication abort callback, when initiated by user
* (To be called at end of DMA Rx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Tx DMA Handle.
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
huart->hdmarx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
if(huart->hdmatx != NULL)
{
if(huart->hdmatx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
huart->TxXferCount = 0x00U;
huart->RxXferCount = 0x00U;
/* Reset ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
/* Restore huart->gState and huart->RxState to Ready */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
/* Call user Abort complete callback */
HAL_UART_AbortCpltCallback(huart);
}
/**
* @brief DMA UART Tx communication abort callback, when initiated by user by a call to
* HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
* (This callback is executed at end of DMA Tx Abort procedure following user abort request,
* and leads to user Tx Abort Complete callback execution).
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
huart->TxXferCount = 0x00U;
/* Restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
/* Call user Abort complete callback */
HAL_UART_AbortTransmitCpltCallback(huart);
}
/**
* @brief DMA UART Rx communication abort callback, when initiated by user by a call to
* HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
* (This callback is executed at end of DMA Rx Abort procedure following user abort request,
* and leads to user Rx Abort Complete callback execution).
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
huart->RxXferCount = 0x00U;
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
/* Call user Abort complete callback */
HAL_UART_AbortReceiveCpltCallback(huart);
}
/**
* @brief Sends an amount of data in non blocking mode.
* @param huart: Pointer to a UART_HandleTypeDef structure that contains
@ -1742,7 +2313,7 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
if(huart->Init.WordLength == UART_WORDLENGTH_9B)
{
tmp = (uint16_t*) huart->pTxBuffPtr;
huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FFU);
huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
if(huart->Init.Parity == UART_PARITY_NONE)
{
huart->pTxBuffPtr += 2;
@ -1754,7 +2325,7 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
}
else
{
huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FFU);
huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
}
if(--huart->TxXferCount == 0)
@ -1810,24 +2381,24 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
tmp = (uint16_t*) huart->pRxBuffPtr;
if(huart->Init.Parity == UART_PARITY_NONE)
{
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FFU);
huart->pRxBuffPtr += 2U;
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
huart->pRxBuffPtr += 2;
}
else
{
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FFU);
huart->pRxBuffPtr += 1U;
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
huart->pRxBuffPtr += 1;
}
}
else
{
if(huart->Init.Parity == UART_PARITY_NONE)
{
*huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FFU);
*huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
}
else
{
*huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007FU);
*huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
}
}
@ -1865,7 +2436,7 @@ static void UART_SetConfig(UART_HandleTypeDef *huart)
uint32_t tmpreg = 0x00U;
/* Check the parameters */
assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
assert_param(IS_UART_PARITY(huart->Init.Parity));
assert_param(IS_UART_MODE(huart->Init.Mode));

66
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_uart.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_uart.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of UART HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -204,12 +204,12 @@ typedef struct
* @brief UART Error Code
* @{
*/
#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */
#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */
#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */
#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */
#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
/**
* @}
*/
@ -217,7 +217,7 @@ typedef struct
/** @defgroup UART_Word_Length UART Word Length
* @{
*/
#define UART_WORDLENGTH_8B ((uint32_t)0x00000000U)
#define UART_WORDLENGTH_8B 0x00000000U
#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
/**
* @}
@ -226,7 +226,7 @@ typedef struct
/** @defgroup UART_Stop_Bits UART Number of Stop Bits
* @{
*/
#define UART_STOPBITS_1 ((uint32_t)0x00000000U)
#define UART_STOPBITS_1 0x00000000U
#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
/**
* @}
@ -235,7 +235,7 @@ typedef struct
/** @defgroup UART_Parity UART Parity
* @{
*/
#define UART_PARITY_NONE ((uint32_t)0x00000000U)
#define UART_PARITY_NONE 0x00000000U
#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
@ -245,7 +245,7 @@ typedef struct
/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
* @{
*/
#define UART_HWCONTROL_NONE ((uint32_t)0x00000000U)
#define UART_HWCONTROL_NONE 0x00000000U
#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
@ -266,7 +266,7 @@ typedef struct
/** @defgroup UART_State UART State
* @{
*/
#define UART_STATE_DISABLE ((uint32_t)0x00000000U)
#define UART_STATE_DISABLE 0x00000000U
#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
/**
* @}
@ -275,7 +275,7 @@ typedef struct
/** @defgroup UART_Over_Sampling UART Over Sampling
* @{
*/
#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000U)
#define UART_OVERSAMPLING_16 0x00000000U
#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
/**
* @}
@ -284,8 +284,8 @@ typedef struct
/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length
* @{
*/
#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000U)
#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)0x00000020U)
#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U
#define UART_LINBREAKDETECTLENGTH_11B 0x00000020U
/**
* @}
*/
@ -293,8 +293,8 @@ typedef struct
/** @defgroup UART_WakeUp_functions UART Wakeup Functions
* @{
*/
#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000U)
#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)0x00000800U)
#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U
#define UART_WAKEUPMETHOD_ADDRESSMARK 0x00000800U
/**
* @}
*/
@ -361,7 +361,7 @@ typedef struct
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
} while(0)
} while(0U)
/** @brief Flushes the UART DR register
* @param __HANDLE__: specifies the UART Handle.
@ -475,7 +475,7 @@ typedef struct
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define UART_IT_MASK ((uint32_t)0x0000FFFFU)
#define UART_IT_MASK 0x0000FFFFU
#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
(((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
@ -534,7 +534,7 @@ typedef struct
do{ \
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
} while(0)
} while(0U)
/** @brief Disable CTS flow control
* This macro allows to disable CTS hardware flow control for a given UART instance,
@ -553,7 +553,7 @@ typedef struct
do{ \
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
} while(0)
} while(0U)
/** @brief Enable RTS flow control
* This macro allows to enable RTS hardware flow control for a given UART instance,
@ -572,7 +572,7 @@ typedef struct
do{ \
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
} while(0)
} while(0U)
/** @brief Disable RTS flow control
* This macro allows to disable RTS hardware flow control for a given UART instance,
@ -591,7 +591,7 @@ typedef struct
do{ \
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
} while(0)
} while(0U)
/** @brief macros to enables the UART's one bit sample method
* @param __HANDLE__: specifies the UART Handle.
@ -653,12 +653,23 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart);
void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart);
void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart);
/**
* @}
*/
@ -722,7 +733,7 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
((CONTROL) == UART_HWCONTROL_RTS) || \
((CONTROL) == UART_HWCONTROL_CTS) || \
((CONTROL) == UART_HWCONTROL_RTS_CTS))
#define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3U) == 0x00U) && ((MODE) != (uint32_t)0x00U))
#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))
#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
((STATE) == UART_STATE_ENABLE))
#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
@ -772,7 +783,8 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
/**
* @}
*/
*/
#ifdef __cplusplus
}
#endif

416
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_usart.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_usart.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief USART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
@ -105,7 +105,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -174,6 +174,8 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void USART_DMAError(DMA_HandleTypeDef *hdma);
static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
/**
@ -408,7 +410,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
if(husart->State == HAL_USART_STATE_READY)
{
if((pTxData == NULL) || (Size == 0U))
if((pTxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -424,7 +426,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
husart->TxXferSize = Size;
husart->TxXferCount = Size;
while(husart->TxXferCount > 0U)
while(husart->TxXferCount > 0)
{
husart->TxXferCount--;
if(husart->Init.WordLength == USART_WORDLENGTH_9B)
@ -435,7 +437,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
return HAL_TIMEOUT;
}
tmp = (uint16_t*) pTxData;
husart->Instance->DR = (*tmp & (uint16_t)0x01FFU);
husart->Instance->DR = (*tmp & (uint16_t)0x01FF);
if(husart->Init.Parity == USART_PARITY_NONE)
{
pTxData += 2U;
@ -451,7 +453,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
{
return HAL_TIMEOUT;
}
husart->Instance->DR = (*pTxData++ & (uint8_t)0xFFU);
husart->Instance->DR = (*pTxData++ & (uint8_t)0xFF);
}
}
@ -489,7 +491,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
if(husart->State == HAL_USART_STATE_READY)
{
if((pRxData == NULL) || (Size == 0U))
if((pRxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -505,7 +507,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
husart->RxXferSize = Size;
husart->RxXferCount = Size;
/* Check the remain data to be received */
while(husart->RxXferCount > 0U)
while(husart->RxXferCount > 0)
{
husart->RxXferCount--;
if(husart->Init.WordLength == USART_WORDLENGTH_9B)
@ -516,7 +518,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
return HAL_TIMEOUT;
}
/* Send dummy byte in order to generate clock */
husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FFU);
husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
/* Wait for RXNE Flag */
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
@ -526,12 +528,12 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
tmp = (uint16_t*) pRxData ;
if(husart->Init.Parity == USART_PARITY_NONE)
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FFU);
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
pRxData +=2;
}
else
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FFU);
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
pRxData +=1;
}
}
@ -544,7 +546,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
}
/* Send Dummy Byte in order to generate clock */
husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FFU);
husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FF);
/* Wait until RXNE flag is set to receive the byte */
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
@ -554,12 +556,12 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
if(husart->Init.Parity == USART_PARITY_NONE)
{
/* Receive data */
*pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FFU);
*pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
}
else
{
/* Receive data */
*pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007FU);
*pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
}
}
@ -595,7 +597,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
if(husart->State == HAL_USART_STATE_READY)
{
if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -614,7 +616,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
husart->RxXferCount = Size;
/* Check the remain data to be received */
while(husart->TxXferCount > 0U)
while(husart->TxXferCount > 0)
{
husart->TxXferCount--;
husart->RxXferCount--;
@ -626,14 +628,14 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
return HAL_TIMEOUT;
}
tmp = (uint16_t*) pTxData;
husart->Instance->DR = (*tmp & (uint16_t)0x01FFU);
husart->Instance->DR = (*tmp & (uint16_t)0x01FF);
if(husart->Init.Parity == USART_PARITY_NONE)
{
pTxData += 2U;
pTxData += 2;
}
else
{
pTxData += 1U;
pTxData += 1;
}
/* Wait for RXNE Flag */
@ -644,12 +646,12 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
tmp = (uint16_t*) pRxData ;
if(husart->Init.Parity == USART_PARITY_NONE)
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FFU);
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
pRxData += 2U;
}
else
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FFU);
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
pRxData += 1U;
}
}
@ -660,7 +662,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
{
return HAL_TIMEOUT;
}
husart->Instance->DR = (*pTxData++ & (uint8_t)0x00FFU);
husart->Instance->DR = (*pTxData++ & (uint8_t)0x00FF);
/* Wait for RXNE Flag */
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
@ -670,12 +672,12 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
if(husart->Init.Parity == USART_PARITY_NONE)
{
/* Receive data */
*pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FFU);
*pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
}
else
{
/* Receive data */
*pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007FU);
*pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
}
}
}
@ -706,7 +708,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
{
if(husart->State == HAL_USART_STATE_READY)
{
if((pTxData == NULL) || (Size == 0U))
if((pTxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -755,7 +757,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
{
if(husart->State == HAL_USART_STATE_READY)
{
if((pRxData == NULL) || (Size == 0U))
if((pRxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -779,7 +781,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Send dummy byte in order to generate the clock for the slave to send data */
husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FFU);
husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
return HAL_OK;
}
@ -802,7 +804,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
{
if(husart->State == HAL_USART_STATE_READY)
{
if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -856,7 +858,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
if(husart->State == HAL_USART_STATE_READY)
{
if((pTxData == NULL) || (Size == 0U))
if((pTxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -920,7 +922,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
if(husart->State == HAL_USART_STATE_READY)
{
if((pRxData == NULL) || (Size == 0U))
if((pRxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -968,8 +970,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
this mode isn't a simplex receive mode but a full-duplex receive one */
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
/* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer
when using the USART in circular mode */
/* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer */
__HAL_USART_CLEAR_OREFLAG(husart);
/* Process Unlocked */
@ -1013,7 +1014,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
if(husart->State == HAL_USART_STATE_READY)
{
if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@ -1178,6 +1179,192 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
return HAL_OK;
}
/**
* @brief Abort ongoing transfer (blocking mode).
* @param husart USART handle.
* @note This procedure could be used for aborting any ongoing transfer (either Tx or Rx,
* as described by TransferType parameter) started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts (depending of transfer direction)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
{
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Disable the USART DMA Tx request if enabled */
if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
/* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
if(husart->hdmatx != NULL)
{
/* Set the USART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
husart->hdmatx->XferAbortCallback = NULL;
HAL_DMA_Abort(husart->hdmatx);
}
}
/* Disable the USART DMA Rx request if enabled */
if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
if(husart->hdmarx != NULL)
{
/* Set the USART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
husart->hdmarx->XferAbortCallback = NULL;
HAL_DMA_Abort(husart->hdmarx);
}
}
/* Reset Tx and Rx transfer counters */
husart->TxXferCount = 0x00U;
husart->RxXferCount = 0x00U;
/* Restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
/* Reset Handle ErrorCode to No Error */
husart->ErrorCode = HAL_USART_ERROR_NONE;
return HAL_OK;
}
/**
* @brief Abort ongoing transfer (Interrupt mode).
* @param husart USART handle.
* @note This procedure could be used for aborting any ongoing transfer (either Tx or Rx,
* as described by TransferType parameter) started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts (depending of transfer direction)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
{
uint32_t AbortCplt = 0x01U;
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
if(husart->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
Otherwise, set it to NULL */
if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
}
else
{
husart->hdmatx->XferAbortCallback = NULL;
}
}
/* DMA Rx Handle is valid */
if(husart->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
Otherwise, set it to NULL */
if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
}
else
{
husart->hdmarx->XferAbortCallback = NULL;
}
}
/* Disable the USART DMA Tx request if enabled */
if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at USART level */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
/* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
if(husart->hdmatx != NULL)
{
/* USART Tx DMA Abort callback has already been initialised :
will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA TX */
if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
{
husart->hdmatx->XferAbortCallback = NULL;
}
else
{
AbortCplt = 0x00U;
}
}
}
/* Disable the USART DMA Rx request if enabled */
if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
if(husart->hdmarx != NULL)
{
/* USART Rx DMA Abort callback has already been initialised :
will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA RX */
if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
{
husart->hdmarx->XferAbortCallback = NULL;
AbortCplt = 0x01U;
}
else
{
AbortCplt = 0x00U;
}
}
}
/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
if(AbortCplt == 0x01U)
{
/* Reset Tx and Rx transfer counters */
husart->TxXferCount = 0x00U;
husart->RxXferCount = 0x00U;
/* Reset errorCode */
husart->ErrorCode = HAL_USART_ERROR_NONE;
/* Restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
HAL_USART_AbortCpltCallback(husart);
}
return HAL_OK;
}
/**
* @brief This function handles USART interrupt request.
* @param husart: pointer to a USART_HandleTypeDef structure that contains
@ -1412,6 +1599,21 @@ __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
*/
}
/**
* @brief USART Abort Complete callback.
* @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_USART_AbortCpltCallback can be implemented in the user file.
*/
}
/**
* @}
*/
@ -1472,7 +1674,7 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
/* DMA Normal mode */
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
{
husart->TxXferCount = 0U;
husart->TxXferCount = 0;
if(husart->State == HAL_USART_STATE_BUSY_TX)
{
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
@ -1517,7 +1719,7 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
/* DMA Normal mode */
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
{
husart->RxXferCount = 0x00U;
husart->RxXferCount = 0x00;
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
@ -1581,8 +1783,8 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma)
{
uint32_t dmarequest = 0x00U;
USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
husart->RxXferCount = 0x00U;
husart->TxXferCount = 0x00U;
husart->RxXferCount = 0x00;
husart->TxXferCount = 0x00;
/* Stop USART DMA Tx request if ongoing */
dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT);
@ -1686,12 +1888,86 @@ static void USART_EndRxTransfer(USART_HandleTypeDef *husart)
static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
husart->RxXferCount = 0x00U;
husart->TxXferCount = 0x00U;
husart->RxXferCount = 0x00;
husart->TxXferCount = 0x00;
HAL_USART_ErrorCallback(husart);
}
/**
* @brief DMA USART Tx communication abort callback, when initiated by user
* (To be called at end of DMA Tx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Rx DMA Handle.
* @param hdma DMA handle.
* @retval None
*/
static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
husart->hdmatx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
if(husart->hdmarx != NULL)
{
if(husart->hdmarx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
husart->TxXferCount = 0x00U;
husart->RxXferCount = 0x00U;
/* Reset errorCode */
husart->ErrorCode = HAL_USART_ERROR_NONE;
/* Restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
/* Call user Abort complete callback */
HAL_USART_AbortCpltCallback(husart);
}
/**
* @brief DMA USART Rx communication abort callback, when initiated by user
* (To be called at end of DMA Rx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Tx DMA Handle.
* @param hdma DMA handle.
* @retval None
*/
static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
husart->hdmarx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
if(husart->hdmatx != NULL)
{
if(husart->hdmatx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
husart->TxXferCount = 0x00U;
husart->RxXferCount = 0x00U;
/* Reset errorCode */
husart->ErrorCode = HAL_USART_ERROR_NONE;
/* Restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
/* Call user Abort complete callback */
HAL_USART_AbortCpltCallback(husart);
}
/**
* @brief Simplex Send an amount of data in non-blocking mode.
* @param husart: pointer to a USART_HandleTypeDef structure that contains
@ -1708,22 +1984,22 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
if(husart->Init.WordLength == USART_WORDLENGTH_9B)
{
tmp = (uint16_t*) husart->pTxBuffPtr;
husart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FFU);
husart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
if(husart->Init.Parity == USART_PARITY_NONE)
{
husart->pTxBuffPtr += 2U;
husart->pTxBuffPtr += 2;
}
else
{
husart->pTxBuffPtr += 1U;
husart->pTxBuffPtr += 1;
}
}
else
{
husart->Instance->DR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FFU);
husart->Instance->DR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF);
}
if(--husart->TxXferCount == 0U)
if(--husart->TxXferCount == 0)
{
/* Disable the USART Transmit data register empty Interrupt */
CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
@ -1776,39 +2052,39 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
tmp = (uint16_t*) husart->pRxBuffPtr;
if(husart->Init.Parity == USART_PARITY_NONE)
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FFU);
husart->pRxBuffPtr += 2U;
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
husart->pRxBuffPtr += 2;
}
else
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FFU);
husart->pRxBuffPtr += 1U;
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
husart->pRxBuffPtr += 1;
}
if(--husart->RxXferCount != 0x00U)
if(--husart->RxXferCount != 0x00)
{
/* Send dummy byte in order to generate the clock for the slave to send the next data */
husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FFU);
husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
}
}
else
{
if(husart->Init.Parity == USART_PARITY_NONE)
{
*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FFU);
*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
}
else
{
*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007FU);
*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
}
if(--husart->RxXferCount != 0x00U)
if(--husart->RxXferCount != 0x00)
{
/* Send dummy byte in order to generate the clock for the slave to send the next data */
husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FFU);
husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FF);
}
}
if(husart->RxXferCount == 0U)
if(husart->RxXferCount == 0)
{
/* Disable the USART RXNE Interrupt */
CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
@ -1844,38 +2120,38 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
{
if(husart->TxXferCount != 0x00U)
if(husart->TxXferCount != 0x00)
{
if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
{
if(husart->Init.WordLength == USART_WORDLENGTH_9B)
{
tmp = (uint16_t*) husart->pTxBuffPtr;
husart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FFU);
husart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
if(husart->Init.Parity == USART_PARITY_NONE)
{
husart->pTxBuffPtr += 2U;
husart->pTxBuffPtr += 2;
}
else
{
husart->pTxBuffPtr += 1U;
husart->pTxBuffPtr += 1;
}
}
else
{
husart->Instance->DR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FFU);
husart->Instance->DR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF);
}
husart->TxXferCount--;
/* Check the latest data transmitted */
if(husart->TxXferCount == 0U)
if(husart->TxXferCount == 0)
{
CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
}
}
}
if(husart->RxXferCount != 0x00U)
if(husart->RxXferCount != 0x00)
{
if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
{
@ -1884,24 +2160,24 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
tmp = (uint16_t*) husart->pRxBuffPtr;
if(husart->Init.Parity == USART_PARITY_NONE)
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FFU);
husart->pRxBuffPtr += 2U;
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
husart->pRxBuffPtr += 2;
}
else
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FFU);
husart->pRxBuffPtr += 1U;
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
husart->pRxBuffPtr += 1;
}
}
else
{
if(husart->Init.Parity == USART_PARITY_NONE)
{
*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FFU);
*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
}
else
{
*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007FU);
*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
}
}
husart->RxXferCount--;
@ -1909,7 +2185,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
}
/* Check the latest data received */
if(husart->RxXferCount == 0U)
if(husart->RxXferCount == 0)
{
/* Disable the USART RXNE Interrupt */
CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);

56
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_usart.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_usart.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -156,12 +156,12 @@ typedef struct
* @brief USART Error Code
* @{
*/
#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#define HAL_USART_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_USART_ERROR_PE 0x00000001U /*!< Parity error */
#define HAL_USART_ERROR_NE 0x00000002U /*!< Noise error */
#define HAL_USART_ERROR_FE 0x00000004U /*!< Frame error */
#define HAL_USART_ERROR_ORE 0x00000008U /*!< Overrun error */
#define HAL_USART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
/**
* @}
*/
@ -169,7 +169,7 @@ typedef struct
/** @defgroup USART_Word_Length USART Word Length
* @{
*/
#define USART_WORDLENGTH_8B ((uint32_t)0x00000000U)
#define USART_WORDLENGTH_8B 0x00000000U
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
/**
* @}
@ -178,7 +178,7 @@ typedef struct
/** @defgroup USART_Stop_Bits USART Number of Stop Bits
* @{
*/
#define USART_STOPBITS_1 ((uint32_t)0x00000000U)
#define USART_STOPBITS_1 0x00000000U
#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
@ -189,7 +189,7 @@ typedef struct
/** @defgroup USART_Parity USART Parity
* @{
*/
#define USART_PARITY_NONE ((uint32_t)0x00000000U)
#define USART_PARITY_NONE 0x00000000U
#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
@ -209,7 +209,7 @@ typedef struct
/** @defgroup USART_Clock USART Clock
* @{
*/
#define USART_CLOCK_DISABLE ((uint32_t)0x00000000U)
#define USART_CLOCK_DISABLE 0x00000000U
#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
/**
* @}
@ -218,7 +218,7 @@ typedef struct
/** @defgroup USART_Clock_Polarity USART Clock Polarity
* @{
*/
#define USART_POLARITY_LOW ((uint32_t)0x00000000U)
#define USART_POLARITY_LOW 0x00000000U
#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
/**
* @}
@ -227,7 +227,7 @@ typedef struct
/** @defgroup USART_Clock_Phase USART Clock Phase
* @{
*/
#define USART_PHASE_1EDGE ((uint32_t)0x00000000U)
#define USART_PHASE_1EDGE 0x00000000U
#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
/**
* @}
@ -236,7 +236,7 @@ typedef struct
/** @defgroup USART_Last_Bit USART Last Bit
* @{
*/
#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000U)
#define USART_LASTBIT_DISABLE 0x00000000U
#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
/**
* @}
@ -245,8 +245,8 @@ typedef struct
/** @defgroup USART_NACK_State USART NACK State
* @{
*/
#define USART_NACK_DISABLE 0x00000000U
#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define USART_NACK_DISABLE ((uint32_t)0x00000000U)
/**
* @}
*/
@ -256,14 +256,14 @@ typedef struct
* - 0xXXXX : Flag mask in the SR register
* @{
*/
#define USART_FLAG_TXE ((uint32_t)0x00000080U)
#define USART_FLAG_TC ((uint32_t)0x00000040U)
#define USART_FLAG_RXNE ((uint32_t)0x00000020U)
#define USART_FLAG_IDLE ((uint32_t)0x00000010U)
#define USART_FLAG_ORE ((uint32_t)0x00000008U)
#define USART_FLAG_NE ((uint32_t)0x00000004U)
#define USART_FLAG_FE ((uint32_t)0x00000002U)
#define USART_FLAG_PE ((uint32_t)0x00000001U)
#define USART_FLAG_TXE 0x00000080U
#define USART_FLAG_TC 0x00000040U
#define USART_FLAG_RXNE 0x00000020U
#define USART_FLAG_IDLE 0x00000010U
#define USART_FLAG_ORE 0x00000008U
#define USART_FLAG_NE 0x00000004U
#define USART_FLAG_FE 0x00000002U
#define USART_FLAG_PE 0x00000001U
/**
* @}
*/
@ -486,6 +486,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
@ -494,6 +497,7 @@ void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart);
/**
* @}
*/
@ -551,7 +555,7 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
((PARITY) == USART_PARITY_EVEN) || \
((PARITY) == USART_PARITY_ODD))
#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFF3) == 0x00U) && ((MODE) != (uint32_t)0x00U))
#define IS_USART_MODE(MODE) ((((MODE) & 0xFFF3U) == 0x00U) && ((MODE) != 0x00U))
#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 7500001U)
#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))

6
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_wwdg.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f2xx_hal_wwdg.c
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief WWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Window Watchdog (WWDG) peripheral:
@ -90,7 +90,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

10
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_wwdg.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f2xx_hal_wwdg.h
* @author MCD Application Team
* @version V1.1.3
* @date 29-June-2016
* @version V1.2.1
* @date 14-April-2017
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -118,7 +118,7 @@ typedef struct
/** @defgroup WWDG_Prescaler WWDG Prescaler
* @{
*/
#define WWDG_PRESCALER_1 ((uint32_t)0x00000000U) /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */
@ -129,7 +129,7 @@ typedef struct
/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
* @{
*/
#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */
#define WWDG_EWI_DISABLE 0x00000000U /*!< EWI Disable */
#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
/**
* @}

934
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_adc.c Normal file
View File

@ -0,0 +1,934 @@
/**
******************************************************************************
* @file stm32f2xx_ll_adc.c
* @author MCD Application Team
* @version V1.2.1
* @date 14-April-2017
* @brief ADC LL module driver
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f2xx_ll_adc.h"
#include "stm32f2xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F2xx_LL_Driver
* @{
*/
#if defined (ADC1) || defined (ADC2) || defined (ADC3)
/** @addtogroup ADC_LL ADC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup ADC_LL_Private_Macros
* @{
*/
/* Check of parameters for configuration of ADC hierarchical scope: */
/* common to several ADC instances. */
#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \
)
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC instance. */
#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
)
#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
|| ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
)
#define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
|| ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \
)
#define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
|| ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \
)
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC group regular */
#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
)
#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
|| ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
)
#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
|| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
|| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
)
#define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \
( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \
|| ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \
)
#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
)
#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
)
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC group injected */
#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH2) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH3) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
)
#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
|| ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
|| ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
)
#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
|| ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
)
#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
)
#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
|| ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
)
#if defined(ADC_MULTIMODE_SUPPORT)
/* Check of parameters for configuration of ADC hierarchical scope: */
/* multimode. */
#if defined(ADC3)
#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \
)
#else
#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
)
#endif
#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \
)
#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \
)
#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
|| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
|| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
)
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ADC_LL_Exported_Functions
* @{
*/
/** @addtogroup ADC_LL_EF_Init
* @{
*/
/**
* @brief De-initialize registers of all ADC instances belonging to
* the same ADC common instance to their default reset values.
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ADC common registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
{
/* Check the parameters */
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
/* Force reset of ADC clock (core clock) */
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
/* Release reset of ADC clock (core clock) */
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
return SUCCESS;
}
/**
* @brief Initialize some features of ADC common parameters
* (all ADC instances belonging to the same ADC common instance)
* and multimode (for devices with several ADC instances available).
* @note The setting of ADC common parameters is conditioned to
* ADC instances state:
* All ADC instances belonging to the same ADC common instance
* must be disabled.
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ADC common registers are initialized
* - ERROR: ADC common registers are not initialized
*/
ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
#if defined(ADC_MULTIMODE_SUPPORT)
assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
{
assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
}
#endif /* ADC_MULTIMODE_SUPPORT */
/* Note: Hardware constraint (refer to description of functions */
/* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
/* On this STM32 serie, setting of these features is conditioned to */
/* ADC state: */
/* All ADC instances of the ADC common group must be disabled. */
if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
{
/* Configuration of ADC hierarchical scope: */
/* - common to several ADC */
/* (all ADC instances belonging to the same ADC common instance) */
/* - Set ADC clock (conversion clock) */
/* - multimode (if several ADC instances available on the */
/* selected device) */
/* - Set ADC multimode configuration */
/* - Set ADC multimode DMA transfer */
/* - Set ADC multimode: delay between 2 sampling phases */
#if defined(ADC_MULTIMODE_SUPPORT)
if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
{
MODIFY_REG(ADCxy_COMMON->CCR,
ADC_CCR_ADCPRE
| ADC_CCR_MULTI
| ADC_CCR_DMA
| ADC_CCR_DDS
| ADC_CCR_DELAY
,
ADC_CommonInitStruct->CommonClock
| ADC_CommonInitStruct->Multimode
| ADC_CommonInitStruct->MultiDMATransfer
| ADC_CommonInitStruct->MultiTwoSamplingDelay
);
}
else
{
MODIFY_REG(ADCxy_COMMON->CCR,
ADC_CCR_ADCPRE
| ADC_CCR_MULTI
| ADC_CCR_DMA
| ADC_CCR_DDS
| ADC_CCR_DELAY
,
ADC_CommonInitStruct->CommonClock
| LL_ADC_MULTI_INDEPENDENT
);
}
#else
LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
#endif
}
else
{
/* Initialization error: One or several ADC instances belonging to */
/* the same ADC common instance are not disabled. */
status = ERROR;
}
return status;
}
/**
* @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
* @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
{
/* Set ADC_CommonInitStruct fields to default values */
/* Set fields of ADC common */
/* (all ADC instances belonging to the same ADC common instance) */
ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
#if defined(ADC_MULTIMODE_SUPPORT)
/* Set fields of ADC multimode */
ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES;
#endif /* ADC_MULTIMODE_SUPPORT */
}
/**
* @brief De-initialize registers of the selected ADC instance
* to their default reset values.
* @note To reset all ADC instances quickly (perform a hard reset),
* use function @ref LL_ADC_CommonDeInit().
* @param ADCx ADC instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ADC registers are de-initialized
* - ERROR: ADC registers are not de-initialized
*/
ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
/* Disable ADC instance if not already disabled. */
if(LL_ADC_IsEnabled(ADCx) == 1U)
{
/* Set ADC group regular trigger source to SW start to ensure to not */
/* have an external trigger event occurring during the conversion stop */
/* ADC disable process. */
LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
/* Set ADC group injected trigger source to SW start to ensure to not */
/* have an external trigger event occurring during the conversion stop */
/* ADC disable process. */
LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
/* Disable the ADC instance */
LL_ADC_Disable(ADCx);
}
/* Check whether ADC state is compliant with expected state */
/* (hardware requirements of bits state to reset registers below) */
if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
{
/* ========== Reset ADC registers ========== */
/* Reset register SR */
CLEAR_BIT(ADCx->SR,
( LL_ADC_FLAG_STRT
| LL_ADC_FLAG_JSTRT
| LL_ADC_FLAG_EOCS
| LL_ADC_FLAG_OVR
| LL_ADC_FLAG_JEOS
| LL_ADC_FLAG_AWD1 )
);
/* Reset register CR1 */
CLEAR_BIT(ADCx->CR1,
( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN
| ADC_CR1_JAWDEN
| ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
| ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
| ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
| ADC_CR1_AWDCH )
);
/* Reset register CR2 */
CLEAR_BIT(ADCx->CR2,
( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL
| ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL
| ADC_CR2_ALIGN | ADC_CR2_EOCS
| ADC_CR2_DDS | ADC_CR2_DMA
| ADC_CR2_CONT | ADC_CR2_ADON )
);
/* Reset register SMPR1 */
CLEAR_BIT(ADCx->SMPR1,
( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
| ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
| ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
);
/* Reset register SMPR2 */
CLEAR_BIT(ADCx->SMPR2,
( ADC_SMPR2_SMP9
| ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
| ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
| ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
);
/* Reset register JOFR1 */
CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
/* Reset register JOFR2 */
CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
/* Reset register JOFR3 */
CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
/* Reset register JOFR4 */
CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
/* Reset register HTR */
SET_BIT(ADCx->HTR, ADC_HTR_HT);
/* Reset register LTR */
CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
/* Reset register SQR1 */
CLEAR_BIT(ADCx->SQR1,
( ADC_SQR1_L
| ADC_SQR1_SQ16
| ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
);
/* Reset register SQR2 */
CLEAR_BIT(ADCx->SQR2,
( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
| ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
);
/* Reset register JSQR */
CLEAR_BIT(ADCx->JSQR,
( ADC_JSQR_JL
| ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
| ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
);
/* Reset register DR */
/* bits in access mode read only, no direct reset applicable */
/* Reset registers JDR1, JDR2, JDR3, JDR4 */
/* bits in access mode read only, no direct reset applicable */
/* Reset register CCR */
CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE);
}
return status;
}
/**
* @brief Initialize some features of ADC instance.
* @note These parameters have an impact on ADC scope: ADC instance.
* Affects both group regular and group injected (availability
* of ADC group injected depends on STM32 families).
* Refer to corresponding unitary functions into
* @ref ADC_LL_EF_Configuration_ADC_Instance .
* @note The setting of these parameters by function @ref LL_ADC_Init()
* is conditioned to ADC state:
* ADC instance must be disabled.
* This condition is applied to all ADC features, for efficiency
* and compatibility over all STM32 families. However, the different
* features can be set under different ADC state conditions
* (setting possible with ADC enabled without conversion on going,
* ADC enabled with conversion on going, ...)
* Each feature can be updated afterwards with a unitary function
* and potentially with ADC in a different state than disabled,
* refer to description of each function for setting
* conditioned to ADC state.
* @note After using this function, some other features must be configured
* using LL unitary functions.
* The minimum configuration remaining to be done is:
* - Set ADC group regular or group injected sequencer:
* map channel on the selected sequencer rank.
* Refer to function @ref LL_ADC_REG_SetSequencerRanks().
* - Set ADC channel sampling time
* Refer to function LL_ADC_SetChannelSamplingTime();
* @param ADCx ADC instance
* @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ADC registers are initialized
* - ERROR: ADC registers are not initialized
*/
ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
/* Note: Hardware constraint (refer to description of this function): */
/* ADC instance must be disabled. */
if(LL_ADC_IsEnabled(ADCx) == 0U)
{
/* Configuration of ADC hierarchical scope: */
/* - ADC instance */
/* - Set ADC data resolution */
/* - Set ADC conversion data alignment */
MODIFY_REG(ADCx->CR1,
ADC_CR1_RES
| ADC_CR1_SCAN
,
ADC_InitStruct->Resolution
| ADC_InitStruct->SequencersScanMode
);
MODIFY_REG(ADCx->CR2,
ADC_CR2_ALIGN
,
ADC_InitStruct->DataAlignment
);
}
else
{
/* Initialization error: ADC instance is not disabled. */
status = ERROR;
}
return status;
}
/**
* @brief Set each @ref LL_ADC_InitTypeDef field to default value.
* @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
{
/* Set ADC_InitStruct fields to default values */
/* Set fields of ADC instance */
ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
/* Enable scan mode to have a generic behavior with ADC of other */
/* STM32 families, without this setting available: */
/* ADC group regular sequencer and ADC group injected sequencer depend */
/* only of their own configuration. */
ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
}
/**
* @brief Initialize some features of ADC group regular.
* @note These parameters have an impact on ADC scope: ADC group regular.
* Refer to corresponding unitary functions into
* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
* (functions with prefix "REG").
* @note The setting of these parameters by function @ref LL_ADC_Init()
* is conditioned to ADC state:
* ADC instance must be disabled.
* This condition is applied to all ADC features, for efficiency
* and compatibility over all STM32 families. However, the different
* features can be set under different ADC state conditions
* (setting possible with ADC enabled without conversion on going,
* ADC enabled with conversion on going, ...)
* Each feature can be updated afterwards with a unitary function
* and potentially with ADC in a different state than disabled,
* refer to description of each function for setting
* conditioned to ADC state.
* @note After using this function, other features must be configured
* using LL unitary functions.
* The minimum configuration remaining to be done is:
* - Set ADC group regular or group injected sequencer:
* map channel on the selected sequencer rank.
* Refer to function @ref LL_ADC_REG_SetSequencerRanks().
* - Set ADC channel sampling time
* Refer to function LL_ADC_SetChannelSamplingTime();
* @param ADCx ADC instance
* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ADC registers are initialized
* - ERROR: ADC registers are not initialized
*/
ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
}
assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
/* Note: Hardware constraint (refer to description of this function): */
/* ADC instance must be disabled. */
if(LL_ADC_IsEnabled(ADCx) == 0U)
{
/* Configuration of ADC hierarchical scope: */
/* - ADC group regular */
/* - Set ADC group regular trigger source */
/* - Set ADC group regular sequencer length */
/* - Set ADC group regular sequencer discontinuous mode */
/* - Set ADC group regular continuous mode */
/* - Set ADC group regular conversion data transfer: no transfer or */
/* transfer by DMA, and DMA requests mode */
/* Note: On this STM32 serie, ADC trigger edge is set when starting */
/* ADC conversion. */
/* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
MODIFY_REG(ADCx->CR1,
ADC_CR1_DISCEN
| ADC_CR1_DISCNUM
,
ADC_REG_InitStruct->SequencerLength
| ADC_REG_InitStruct->SequencerDiscont
);
}
else
{
MODIFY_REG(ADCx->CR1,
ADC_CR1_DISCEN
| ADC_CR1_DISCNUM
,
ADC_REG_InitStruct->SequencerLength
| LL_ADC_REG_SEQ_DISCONT_DISABLE
);
}
MODIFY_REG(ADCx->CR2,
ADC_CR2_EXTSEL
| ADC_CR2_EXTEN
| ADC_CR2_CONT
| ADC_CR2_DMA
| ADC_CR2_DDS
,
(ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL)
| ADC_REG_InitStruct->ContinuousMode
| ADC_REG_InitStruct->DMATransfer
);
/* Set ADC group regular sequencer length and scan direction */
/* Note: Hardware constraint (refer to description of this function): */
/* Note: If ADC instance feature scan mode is disabled */
/* (refer to ADC instance initialization structure */
/* parameter @ref SequencersScanMode */
/* or function @ref LL_ADC_SetSequencersScanMode() ), */
/* this parameter is discarded. */
LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
}
else
{
/* Initialization error: ADC instance is not disabled. */
status = ERROR;
}
return status;
}
/**
* @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
{
/* Set ADC_REG_InitStruct fields to default values */
/* Set fields of ADC group regular */
/* Note: On this STM32 serie, ADC trigger edge is set when starting */
/* ADC conversion. */
/* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
}
/**
* @brief Initialize some features of ADC group injected.
* @note These parameters have an impact on ADC scope: ADC group injected.
* Refer to corresponding unitary functions into
* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
* (functions with prefix "INJ").
* @note The setting of these parameters by function @ref LL_ADC_Init()
* is conditioned to ADC state:
* ADC instance must be disabled.
* This condition is applied to all ADC features, for efficiency
* and compatibility over all STM32 families. However, the different
* features can be set under different ADC state conditions
* (setting possible with ADC enabled without conversion on going,
* ADC enabled with conversion on going, ...)
* Each feature can be updated afterwards with a unitary function
* and potentially with ADC in a different state than disabled,
* refer to description of each function for setting
* conditioned to ADC state.
* @note After using this function, other features must be configured
* using LL unitary functions.
* The minimum configuration remaining to be done is:
* - Set ADC group injected sequencer:
* map channel on the selected sequencer rank.
* Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
* - Set ADC channel sampling time
* Refer to function LL_ADC_SetChannelSamplingTime();
* @param ADCx ADC instance
* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ADC registers are initialized
* - ERROR: ADC registers are not initialized
*/
ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
{
assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
}
assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
/* Note: Hardware constraint (refer to description of this function): */
/* ADC instance must be disabled. */
if(LL_ADC_IsEnabled(ADCx) == 0U)
{
/* Configuration of ADC hierarchical scope: */
/* - ADC group injected */
/* - Set ADC group injected trigger source */
/* - Set ADC group injected sequencer length */
/* - Set ADC group injected sequencer discontinuous mode */
/* - Set ADC group injected conversion trigger: independent or */
/* from ADC group regular */
/* Note: On this STM32 serie, ADC trigger edge is set when starting */
/* ADC conversion. */
/* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
MODIFY_REG(ADCx->CR1,
ADC_CR1_JDISCEN
| ADC_CR1_JAUTO
,
ADC_INJ_InitStruct->SequencerDiscont
| ADC_INJ_InitStruct->TrigAuto
);
}
else
{
MODIFY_REG(ADCx->CR1,
ADC_CR1_JDISCEN
| ADC_CR1_JAUTO
,
LL_ADC_REG_SEQ_DISCONT_DISABLE
| ADC_INJ_InitStruct->TrigAuto
);
}
MODIFY_REG(ADCx->CR2,
ADC_CR2_JEXTSEL
| ADC_CR2_JEXTEN
,
(ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL)
);
/* Note: Hardware constraint (refer to description of this function): */
/* Note: If ADC instance feature scan mode is disabled */
/* (refer to ADC instance initialization structure */
/* parameter @ref SequencersScanMode */
/* or function @ref LL_ADC_SetSequencersScanMode() ), */
/* this parameter is discarded. */
LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
}
else
{
/* Initialization error: ADC instance is not disabled. */
status = ERROR;
}
return status;
}
/**
* @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
{
/* Set ADC_INJ_InitStruct fields to default values */
/* Set fields of ADC group injected */
ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* ADC1 || ADC2 || ADC3 */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_bus.h Normal file
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