mirror of https://github.com/ARMmbed/mbed-os.git
Remove uARM dependencies for EFM32FF targets
Harrison Mutai
parent
c5bfa7e471
commit
5b1c704622
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@ -1,54 +0,0 @@
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#! armcc -E
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; *************************************************************
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; *** Scatter-Loading Description File generated by uVision ***
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; *************************************************************
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#if !defined(MBED_APP_START)
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#define MBED_APP_START 0x00000000
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#endif
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#if !defined(MBED_APP_SIZE)
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#define MBED_APP_SIZE 0x00100000
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#endif
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#if !defined(MBED_RAM_START)
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#define MBED_RAM_START 0x20000000
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#endif
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#if !defined(MBED_RAM_SIZE)
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#define MBED_RAM_SIZE 0x00020000
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#endif
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#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
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# if defined(MBED_BOOT_STACK_SIZE)
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# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
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# else
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# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
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# endif
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#endif
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#define VECTOR_SIZE 0xE0
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#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE+VECTOR_SIZE)
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#define MBED_RAM1_START (MBED_RAM_START+VECTOR_SIZE)
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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RW_IRAM1 MBED_RAM1_START (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
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.ANY (+RW +ZI)
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}
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ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM1_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
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}
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ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; stack
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}
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}
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@ -1,245 +0,0 @@
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;/**************************************************************************//**
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; * @file startup_efm32gg.s
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; * @brief CMSIS Core Device Startup File for
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; * Silicon Labs EFM32GG Device Series
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; * @version 4.2.1
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; * @date 03. February 2012
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; *
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; * @note
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; * Copyright (C) 2012 ARM Limited. All rights reserved.
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; *
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; * @par
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; * ARM Limited (ARM) is supplying this software for use with Cortex-M
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
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; *
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; * @par
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; ******************************************************************************/
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY, ALIGN=8
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EXPORT __Vectors
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EXPORT __Vectors_End
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IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
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__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD DMA_IRQHandler ; 0: DMA Interrupt
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DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt
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DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt
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DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt
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DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt
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DCD USB_IRQHandler ; 5: USB Interrupt
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DCD ACMP0_IRQHandler ; 6: ACMP0 Interrupt
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DCD ADC0_IRQHandler ; 7: ADC0 Interrupt
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DCD DAC0_IRQHandler ; 8: DAC0 Interrupt
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DCD I2C0_IRQHandler ; 9: I2C0 Interrupt
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DCD I2C1_IRQHandler ; 10: I2C1 Interrupt
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DCD GPIO_ODD_IRQHandler ; 11: GPIO_ODD Interrupt
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DCD TIMER1_IRQHandler ; 12: TIMER1 Interrupt
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DCD TIMER2_IRQHandler ; 13: TIMER2 Interrupt
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DCD TIMER3_IRQHandler ; 14: TIMER3 Interrupt
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DCD USART1_RX_IRQHandler ; 15: USART1_RX Interrupt
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DCD USART1_TX_IRQHandler ; 16: USART1_TX Interrupt
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DCD LESENSE_IRQHandler ; 17: LESENSE Interrupt
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DCD USART2_RX_IRQHandler ; 18: USART2_RX Interrupt
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DCD USART2_TX_IRQHandler ; 19: USART2_TX Interrupt
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DCD UART0_RX_IRQHandler ; 20: UART0_RX Interrupt
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DCD UART0_TX_IRQHandler ; 21: UART0_TX Interrupt
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DCD UART1_RX_IRQHandler ; 22: UART1_RX Interrupt
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DCD UART1_TX_IRQHandler ; 23: UART1_TX Interrupt
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DCD LEUART0_IRQHandler ; 24: LEUART0 Interrupt
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DCD LEUART1_IRQHandler ; 25: LEUART1 Interrupt
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DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt
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DCD PCNT0_IRQHandler ; 27: PCNT0 Interrupt
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DCD PCNT1_IRQHandler ; 28: PCNT1 Interrupt
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DCD PCNT2_IRQHandler ; 29: PCNT2 Interrupt
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DCD RTC_IRQHandler ; 30: RTC Interrupt
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DCD BURTC_IRQHandler ; 31: BURTC Interrupt
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DCD CMU_IRQHandler ; 32: CMU Interrupt
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DCD VCMP_IRQHandler ; 33: VCMP Interrupt
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DCD LCD_IRQHandler ; 34: LCD Interrupt
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DCD MSC_IRQHandler ; 35: MSC Interrupt
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DCD AES_IRQHandler ; 36: AES Interrupt
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DCD EBI_IRQHandler ; 37: EBI Interrupt
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DCD EMU_IRQHandler ; 38: EMU Interrupt
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT DMA_IRQHandler [WEAK]
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EXPORT GPIO_EVEN_IRQHandler [WEAK]
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EXPORT TIMER0_IRQHandler [WEAK]
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EXPORT USART0_RX_IRQHandler [WEAK]
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EXPORT USART0_TX_IRQHandler [WEAK]
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EXPORT USB_IRQHandler [WEAK]
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EXPORT ACMP0_IRQHandler [WEAK]
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EXPORT ADC0_IRQHandler [WEAK]
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EXPORT DAC0_IRQHandler [WEAK]
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EXPORT I2C0_IRQHandler [WEAK]
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EXPORT I2C1_IRQHandler [WEAK]
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EXPORT GPIO_ODD_IRQHandler [WEAK]
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EXPORT TIMER1_IRQHandler [WEAK]
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EXPORT TIMER2_IRQHandler [WEAK]
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EXPORT TIMER3_IRQHandler [WEAK]
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EXPORT USART1_RX_IRQHandler [WEAK]
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EXPORT USART1_TX_IRQHandler [WEAK]
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EXPORT LESENSE_IRQHandler [WEAK]
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EXPORT USART2_RX_IRQHandler [WEAK]
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EXPORT USART2_TX_IRQHandler [WEAK]
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EXPORT UART0_RX_IRQHandler [WEAK]
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EXPORT UART0_TX_IRQHandler [WEAK]
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EXPORT UART1_RX_IRQHandler [WEAK]
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EXPORT UART1_TX_IRQHandler [WEAK]
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EXPORT LEUART0_IRQHandler [WEAK]
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EXPORT LEUART1_IRQHandler [WEAK]
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EXPORT LETIMER0_IRQHandler [WEAK]
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EXPORT PCNT0_IRQHandler [WEAK]
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EXPORT PCNT1_IRQHandler [WEAK]
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EXPORT PCNT2_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT BURTC_IRQHandler [WEAK]
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EXPORT CMU_IRQHandler [WEAK]
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EXPORT VCMP_IRQHandler [WEAK]
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EXPORT LCD_IRQHandler [WEAK]
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EXPORT MSC_IRQHandler [WEAK]
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EXPORT AES_IRQHandler [WEAK]
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EXPORT EBI_IRQHandler [WEAK]
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EXPORT EMU_IRQHandler [WEAK]
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DMA_IRQHandler
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GPIO_EVEN_IRQHandler
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TIMER0_IRQHandler
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USART0_RX_IRQHandler
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USART0_TX_IRQHandler
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USB_IRQHandler
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ACMP0_IRQHandler
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ADC0_IRQHandler
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DAC0_IRQHandler
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I2C0_IRQHandler
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I2C1_IRQHandler
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GPIO_ODD_IRQHandler
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TIMER1_IRQHandler
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TIMER2_IRQHandler
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TIMER3_IRQHandler
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USART1_RX_IRQHandler
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USART1_TX_IRQHandler
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LESENSE_IRQHandler
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USART2_RX_IRQHandler
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USART2_TX_IRQHandler
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UART0_RX_IRQHandler
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UART0_TX_IRQHandler
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UART1_RX_IRQHandler
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UART1_TX_IRQHandler
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LEUART0_IRQHandler
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LEUART1_IRQHandler
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LETIMER0_IRQHandler
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PCNT0_IRQHandler
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PCNT1_IRQHandler
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PCNT2_IRQHandler
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RTC_IRQHandler
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BURTC_IRQHandler
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CMU_IRQHandler
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VCMP_IRQHandler
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LCD_IRQHandler
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MSC_IRQHandler
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AES_IRQHandler
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EBI_IRQHandler
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EMU_IRQHandler
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B .
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ENDP
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ALIGN
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END
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