mirror of https://github.com/ARMmbed/mbed-os.git
[NUCLEO_F401RE] Update STM32CubeF4 driver V1.0.0 (part 3/4)
bcostm
parent
3a37a058c5
commit
5a4e51ad4e
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f4xx_hal_nand.c
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* @author MCD Application Team
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* @version V1.0.0RC2
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* @date 04-February-2014
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* @version V1.0.0
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* @date 18-February-2014
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* @brief NAND HAL module driver.
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* This file provides a generic firmware to drive NAND memories mounted
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* as external device.
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@ -154,13 +154,12 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT
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FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
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/* Enable the NAND device */
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__FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
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__FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
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/* Update the NAND controller state */
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hnand->State = HAL_NAND_STATE_READY;
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return HAL_OK;
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hnand->State = HAL_NAND_STATE_READY;
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return HAL_OK;
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}
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/**
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@ -172,12 +171,17 @@ HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
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{
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/* Initialize the low level hardware (MSP) */
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HAL_NAND_MspDeInit(hnand);
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/* Configure the NAND registers with their reset values */
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FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
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return HAL_OK;
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/* Reset the NAND controller state */
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hnand->State = HAL_NAND_STATE_RESET;
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/* Release Lock */
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__HAL_UNLOCK(hnand);
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return HAL_OK;
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}
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/**
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f4xx_hal_nand.h
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* @author MCD Application Team
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* @version V1.0.0RC2
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* @date 04-February-2014
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* @version V1.0.0
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* @date 18-February-2014
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* @brief Header file of NAND HAL module.
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******************************************************************************
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* @attention
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@ -193,10 +193,10 @@ typedef struct
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/* Initialization/de-initialization functions **********************************/
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HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
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HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
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__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
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__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
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void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
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void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
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void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
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__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
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void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
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/* IO operation functions *****************************************************/
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HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f4xx_hal_nor.c
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* @author MCD Application Team
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* @version V1.0.0RC2
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* @date 04-February-2014
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* @version V1.0.0
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* @date 18-February-2014
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* @brief NOR HAL module driver.
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* This file provides a generic firmware to drive NOR memories mounted
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* as external device.
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@ -94,12 +94,11 @@
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* @{
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*/
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#ifdef HAL_NOR_MODULE_ENABLED
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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@ -144,7 +143,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
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{
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/* Initialize the low level hardware (MSP) */
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HAL_NOR_MspInit(hnor);
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}
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}
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/* Initialize NOR control Interface */
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FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
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@ -154,15 +153,14 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
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/* Initialize NOR extended mode timing Interface */
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FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
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/* Enable the NORSRAM device */
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__FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
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/* Check the NOR controller state */
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hnor->State = HAL_NOR_STATE_READY;
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return HAL_OK;
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}
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/**
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@ -172,9 +170,6 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
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*/
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HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
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{
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/* Update the NOR controller state */
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hnor->State = HAL_NOR_STATE_BUSY;
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/* De-Initialize the low level hardware (MSP) */
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HAL_NOR_MspDeInit(hnor);
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@ -182,8 +177,11 @@ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
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FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
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/* Update the NOR controller state */
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hnor->State = HAL_NOR_STATE_READY;
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hnor->State = HAL_NOR_STATE_RESET;
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/* Release Lock */
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__HAL_UNLOCK(hnor);
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return HAL_OK;
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}
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@ -309,7 +307,6 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
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return HAL_OK;
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}
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/**
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* @brief Read data from NOR memory
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* @param hnor: pointer to NOR handle
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@ -348,7 +345,6 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
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return HAL_OK;
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}
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/**
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* @brief Program data to NOR memory
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* @param hnor: pointer to NOR handle
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@ -387,7 +383,6 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
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return HAL_OK;
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}
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/**
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* @brief Reads a block of data from the FMC NOR memory.
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* @param hnor: pointer to NOR handle
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@ -433,7 +428,6 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
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return HAL_OK;
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}
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/**
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* @brief Writes a half-word buffer to the FMC NOR memory. This function
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* must be used only with S29GL128P NOR memory.
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@ -536,7 +530,6 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
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}
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/**
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* @brief Erase the entire NOR chip.
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* @param hnor: pointer to NOR handle
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@ -574,7 +567,6 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
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return HAL_OK;
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}
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/**
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* @brief Read NOR flash CFI IDs
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* @param hnor: pointer to NOR handle
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@ -613,7 +605,6 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
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return HAL_OK;
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}
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/**
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* @}
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*/
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@ -624,7 +615,7 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
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@verbatim
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==============================================================================
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##### NOR Control functions #####
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==============================================================================
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==============================================================================
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[..]
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This subsection provides a set of functions allowing to control dynamically
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the NOR interface.
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f4xx_hal_nor.h
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* @author MCD Application Team
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* @version V1.0.0RC2
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* @date 04-February-2014
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* @version V1.0.0
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* @date 18-February-2014
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* @brief Header file of NOR HAL module.
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******************************************************************************
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* @attention
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@ -190,16 +190,16 @@ typedef struct
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* @param __DATA__: Data to write
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* @retval None
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*/
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#define __NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint32_t *)(__ADDRESS__) = (__DATA__))
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#define __NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
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/* Exported functions --------------------------------------------------------*/
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/* Initialization/de-initialization functions **********************************/
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HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
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HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
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__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
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__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
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__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
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void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
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void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
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void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
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/* I/O operation functions *****************************************************/
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HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f4xx_hal_pccard.c
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* @author MCD Application Team
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* @version V1.0.0RC2
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* @date 04-February-2014
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* @version V1.0.0
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* @date 18-February-2014
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* @brief PCCARD HAL module driver.
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* This file provides a generic firmware to drive PCCARD memories mounted
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* as external device.
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@ -86,12 +86,11 @@
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* @{
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*/
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#ifdef HAL_PCCARD_MODULE_ENABLED
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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@ -169,18 +168,18 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_Ti
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*/
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HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
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{
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/* Update the PCCARD controller state */
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hpccard->State = HAL_PCCARD_STATE_BUSY;
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/* De-Initialize the low level hardware (MSP) */
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HAL_PCCARD_MspDeInit(hpccard);
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HAL_PCCARD_MspDeInit(hpccard);
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/* Configure the PCCARD registers with their reset values */
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FMC_PCCARD_DeInit(hpccard->Instance);
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/* Update the PCCARD controller state */
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hpccard->State = HAL_PCCARD_STATE_RESET;
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/* Release Lock */
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__HAL_UNLOCK(hpccard);
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return HAL_OK;
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}
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f4xx_hal_pccard.h
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* @author MCD Application Team
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* @version V1.0.0RC2
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* @date 04-February-2014
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* @version V1.0.0
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* @date 18-February-2014
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* @brief Header file of PCCARD HAL module.
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******************************************************************************
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* @attention
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@ -143,8 +143,8 @@ typedef struct
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/* Initialization/de-initialization functions **********************************/
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HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
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HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
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__weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
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__weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
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void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
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void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
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/* IO operation functions *****************************************************/
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HAL_StatusTypeDef HAL_CF_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
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@ -153,7 +153,7 @@ HAL_StatusTypeDef HAL_CF_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *p
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HAL_StatusTypeDef HAL_CF_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
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HAL_StatusTypeDef HAL_CF_Reset(PCCARD_HandleTypeDef *hpccard);
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void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
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__weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
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void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
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/* PCCARD State functions *******************************************************/
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HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f4xx_hal_pcd.c
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* @author MCD Application Team
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* @version V1.0.0RC2
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* @date 04-February-2014
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* @version V1.0.0
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* @date 18-February-2014
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* @brief PCD HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of the USB Peripheral Controller:
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@ -177,11 +177,9 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
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/* Init Device */
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USB_DevInit(hpcd->Instance, hpcd->Init);
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/* Enable the Interrupts */
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__HAL_PCD_ENABLE(hpcd);
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hpcd->State= PCD_READY;
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USB_DevDisconnect (hpcd->Instance);
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return HAL_OK;
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}
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@ -200,6 +198,9 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
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hpcd->State = PCD_BUSY;
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/* Stop Device */
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HAL_PCD_Stop(hpcd);
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/* DeInit the low level hardware */
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HAL_PCD_MspDeInit(hpcd);
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@ -413,8 +414,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
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}
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if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
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{
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fifoemptymsk = 0x1 << epnum;
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USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
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PCD_WriteEmptyTxFifo(hpcd , epnum);
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}
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}
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@ -423,33 +422,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
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}
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}
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/* Handle Suspend Interrupt */
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if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
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{
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HAL_PCD_SuspendCallback(hpcd);
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if( (hpcd->Init.low_power_enable) && \
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( (USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS))
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{
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/* un-gate USB Core clock */
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USBx_PCGCCTL |= (USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
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/* Request to enter Sleep mode after exit from current ISR */
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SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk);
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}
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__HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
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}
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/* Handle Resume Interrupt */
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if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
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{
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if( hpcd->Init.low_power_enable)
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{
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/* un-gate USB Core clock */
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USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
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}
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{
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/* Clear the Remote Wake-up Signaling */
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USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
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@ -457,6 +432,20 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
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__HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
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}
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/* Handle Suspend Interrupt */
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if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
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{
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|
||||
if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
|
||||
{
|
||||
|
||||
HAL_PCD_SuspendCallback(hpcd);
|
||||
}
|
||||
__HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Handle Reset Interrupt */
|
||||
if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
|
||||
|
|
@ -488,8 +477,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|||
|
||||
/* setup EP0 to receive SETUP packets */
|
||||
USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
|
||||
|
||||
HAL_PCD_ResetCallback(hpcd);
|
||||
|
||||
__HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
|
||||
}
|
||||
|
|
@ -512,6 +499,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|||
hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ;
|
||||
hpcd->Instance->GUSBCFG |= (USB_OTG_GUSBCFG_TRDT_0 | USB_OTG_GUSBCFG_TRDT_2);
|
||||
}
|
||||
|
||||
HAL_PCD_ResetCallback(hpcd);
|
||||
|
||||
__HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
|
||||
}
|
||||
|
||||
|
|
@ -641,6 +631,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|||
*/
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Suspend event callbacks
|
||||
* @param hpcd: PCD handle
|
||||
|
|
@ -1054,17 +1045,27 @@ HAL_StatusTypeDef HAL_PCD_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint1
|
|||
|
||||
Tx_Offset = hpcd->Instance->GRXFSIZ;
|
||||
|
||||
for (i = 0; i < fifo; i++)
|
||||
if(fifo == 0)
|
||||
{
|
||||
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
|
||||
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset;
|
||||
}
|
||||
else
|
||||
{
|
||||
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
|
||||
for (i = 0; i < (fifo - 1); i++)
|
||||
{
|
||||
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
|
||||
}
|
||||
|
||||
/* Multiply Tx_Size by 2 to get higher performance */
|
||||
hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset;
|
||||
|
||||
}
|
||||
|
||||
/* Multiply Tx_Size by 2 to get higher performance */
|
||||
hpcd->Instance->DIEPTXF[fifo] = (size << 16) | Tx_Offset;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Update FIFO configuration
|
||||
* @param hpcd: PCD handle
|
||||
|
|
@ -1078,6 +1079,37 @@ HAL_StatusTypeDef HAL_PCD_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
|
|||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief HAL_PCD_ActiveRemoteWakeup : active remote wakeup signalling
|
||||
* @param hpcd: PCD handle
|
||||
* @retval status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
||||
|
||||
if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
|
||||
{
|
||||
/* active Remote wakeup signaling */
|
||||
USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
|
||||
}
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief HAL_PCD_DeActiveRemoteWakeup : de-active remote wakeup signalling
|
||||
* @param hpcd: PCD handle
|
||||
* @retval status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
||||
|
||||
/* active Remote wakeup signaling */
|
||||
USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
|
||||
return HAL_OK;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1120,9 +1152,10 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
|
|||
{
|
||||
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
||||
USB_OTG_EPTypeDef *ep;
|
||||
uint32_t len = 0;
|
||||
int32_t len = 0;
|
||||
uint32_t len32b;
|
||||
|
||||
uint32_t fifoemptymsk = 0;
|
||||
|
||||
ep = &hpcd->IN_ep[epnum];
|
||||
len = ep->xfer_len - ep->xfer_count;
|
||||
|
||||
|
|
@ -1131,6 +1164,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
|
|||
len = ep->maxpacket;
|
||||
}
|
||||
|
||||
|
||||
len32b = (len + 3) / 4;
|
||||
|
||||
while ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
|
||||
|
|
@ -1152,6 +1186,13 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
|
|||
ep->xfer_count += len;
|
||||
}
|
||||
|
||||
if(len <= 0)
|
||||
{
|
||||
fifoemptymsk = 0x1 << epnum;
|
||||
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
|
||||
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_pcd.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief Header file of PCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -98,8 +98,7 @@ typedef struct
|
|||
*/
|
||||
#define PCD_SPEED_HIGH 0
|
||||
#define PCD_SPEED_HIGH_IN_FULL 1
|
||||
#define PCD_SPEED_LOW 2
|
||||
#define PCD_SPEED_FULL 3
|
||||
#define PCD_SPEED_FULL 2
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -142,7 +141,68 @@ typedef struct
|
|||
|
||||
#define __HAL_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#define __HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) |= (__INTERRUPT__))
|
||||
#define __HAL_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
|
||||
#define __HAL_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
|
||||
|
||||
|
||||
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
|
||||
~(USB_OTG_PCGCCTL_STOPCLK)
|
||||
|
||||
|
||||
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
|
||||
|
||||
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
|
||||
|
||||
#define USB_FS_EXTI_TRIGGER_RISING_EDGE ((uint32_t)0x08)
|
||||
#define USB_FS_EXTI_TRIGGER_FALLING_EDGE ((uint32_t)0x0C)
|
||||
#define USB_FS_EXTI_TRIGGER_BOTH_EDGE ((uint32_t)0x10)
|
||||
|
||||
#define USB_HS_EXTI_TRIGGER_RISING_EDGE ((uint32_t)0x08)
|
||||
#define USB_HS_EXTI_TRIGGER_FALLING_EDGE ((uint32_t)0x0C)
|
||||
#define USB_HS_EXTI_TRIGGER_BOTH_EDGE ((uint32_t)0x10)
|
||||
|
||||
|
||||
#define USB_HS_EXTI_LINE_WAKEUP ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
|
||||
#define USB_FS_EXTI_LINE_WAKEUP ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
|
||||
|
||||
|
||||
|
||||
#define __HAL_USB_HS_EXTI_ENABLE_IT() EXTI->IMR |= (USB_HS_EXTI_LINE_WAKEUP)
|
||||
#define __HAL_USB_HS_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_HS_EXTI_LINE_WAKEUP)
|
||||
#define __HAL_USB_HS_EXTI_GET_FLAG() EXTI->PR & (USB_HS_EXTI_LINE_WAKEUP)
|
||||
#define __HAL_USB_HS_EXTI_CLEAR_FLAG() EXTI->PR = (USB_HS_EXTI_LINE_WAKEUP)
|
||||
|
||||
#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER() EXTI->FTSR &= ~(USB_HS_EXTI_LINE_WAKEUP);\
|
||||
EXTI->RTSR |= USB_HS_EXTI_LINE_WAKEUP
|
||||
|
||||
|
||||
#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (USB_HS_EXTI_LINE_WAKEUP);\
|
||||
EXTI->RTSR &= ~(USB_HS_EXTI_LINE_WAKEUP)
|
||||
|
||||
|
||||
#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(USB_HS_EXTI_LINE_WAKEUP);\
|
||||
EXTI->FTSR &= ~(USB_HS_EXTI_LINE_WAKEUP;)\
|
||||
EXTI->RTSR |= USB_HS_EXTI_LINE_WAKEUP;\
|
||||
EXTI->FTSR |= USB_HS_EXTI_LINE_WAKEUP
|
||||
|
||||
|
||||
#define __HAL_USB_FS_EXTI_ENABLE_IT() EXTI->IMR |= USB_FS_EXTI_LINE_WAKEUP
|
||||
#define __HAL_USB_FS_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_FS_EXTI_LINE_WAKEUP)
|
||||
#define __HAL_USB_FS_EXTI_GET_FLAG() EXTI->PR & (USB_FS_EXTI_LINE_WAKEUP)
|
||||
#define __HAL_USB_FS_EXTI_CLEAR_FLAG() EXTI->PR = USB_FS_EXTI_LINE_WAKEUP
|
||||
|
||||
#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER() EXTI->FTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\
|
||||
EXTI->RTSR |= USB_FS_EXTI_LINE_WAKEUP
|
||||
|
||||
|
||||
#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (USB_FS_EXTI_LINE_WAKEUP);\
|
||||
EXTI->RTSR &= ~(USB_FS_EXTI_LINE_WAKEUP)
|
||||
|
||||
|
||||
#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\
|
||||
EXTI->FTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\
|
||||
EXTI->RTSR |= USB_FS_EXTI_LINE_WAKEUP;\
|
||||
EXTI->FTSR |= USB_FS_EXTI_LINE_WAKEUP
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -161,17 +221,19 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
|
|||
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
|
||||
__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
|
||||
__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
|
||||
__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
|
||||
__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
|
||||
|
|
@ -187,7 +249,8 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
|||
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
|
||||
HAL_StatusTypeDef HAL_PCD_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
/* Peripheral State functions **************************************************/
|
||||
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief PWR HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief Header file of PWR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -312,7 +312,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
|
|||
void HAL_PWR_EnterSTANDBYMode(void);
|
||||
|
||||
void HAL_PWR_PVD_IRQHandler(void);
|
||||
__weak void HAL_PWR_PVDCallback(void);
|
||||
void HAL_PWR_PVDCallback(void);
|
||||
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_pwr_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief Extended PWR HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of PWR extension peripheral:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_pwr_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief Header file of PWR HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_rcc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief RCC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Reset and Clock Control (RCC) peripheral:
|
||||
|
|
@ -85,7 +85,6 @@
|
|||
#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
|
||||
#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
|
||||
#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
|
||||
#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
|
||||
#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
|
||||
#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
|
||||
|
||||
|
|
@ -476,15 +475,23 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|||
/* Check the parameters */
|
||||
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
||||
|
||||
/* Check the LSE State before enabling the access to the Bachup domain */
|
||||
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
|
||||
/* Enable Power Clock*/
|
||||
__PWR_CLK_ENABLE();
|
||||
|
||||
/* Enable write access to Backup domain */
|
||||
PWR->CR |= PWR_CR_DBP;
|
||||
|
||||
/* Wait for Backup domain Write protection disable */
|
||||
timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE;
|
||||
|
||||
while((PWR->CR & PWR_CR_DBP) == RESET)
|
||||
{
|
||||
/* Enable Power Controller clock */
|
||||
__PWR_CLK_ENABLE();
|
||||
|
||||
/* Enable write access to Backup domain */
|
||||
PWR->CR |= PWR_CR_DBP;
|
||||
if(HAL_GetTick() >= timeout)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
|
||||
__HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_rcc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief Header file of RCC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -186,8 +186,11 @@ typedef struct
|
|||
#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
|
||||
|
||||
/* BDCR register base address */
|
||||
#define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
|
||||
#define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
|
||||
|
||||
|
||||
#define DBP_TIMEOUT_VALUE ((uint32_t)100)
|
||||
#define LSE_TIMEOUT_VALUE ((uint32_t)5000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -195,6 +198,7 @@ typedef struct
|
|||
/** @defgroup RCC_Oscillator_Type
|
||||
* @{
|
||||
*/
|
||||
#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
|
||||
#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
|
||||
#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
|
||||
#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
|
||||
|
|
@ -934,8 +938,8 @@ typedef struct
|
|||
* RTC clock source).
|
||||
*/
|
||||
#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
|
||||
MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : 0
|
||||
|
||||
MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
|
||||
|
||||
#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
|
||||
RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
|
||||
} while (0)
|
||||
|
|
@ -1100,7 +1104,7 @@ typedef struct
|
|||
/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
|
||||
* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
|
||||
*/
|
||||
#define __HAL_RCC_CLEAR_FLAG() (RCC->CSR |= RCC_CSR_RMVF)
|
||||
#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
|
||||
|
||||
/** @brief Check RCC flag is set or not.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
|
|
@ -1154,7 +1158,7 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t
|
|||
void HAL_RCC_NMI_IRQHandler(void);
|
||||
|
||||
/* User Callbacks in non blocking mode (IT mode) */
|
||||
__weak void HAL_RCC_CCSCallback(void);
|
||||
void HAL_RCC_CCSCallback(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_rcc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief Extension RCC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities RCC extension peripheral:
|
||||
|
|
@ -76,16 +76,28 @@
|
|||
[..]
|
||||
This subsection provides a set of functions allowing to control the RCC Clocks
|
||||
frequencies.
|
||||
[..]
|
||||
(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
|
||||
select the RTC clock source; in this case the Backup domain will be reset in
|
||||
order to modify the RTC Clock source, as consequence RTC registers (including
|
||||
the backup registers) and RCC_BDCR register are set to their reset values.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
||||
/**
|
||||
* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
|
||||
* RCC_PeriphCLKInitTypeDef.
|
||||
* @brief Initializes the RCC extended peripherals clocks according to the specified
|
||||
* parameters in the RCC_PeriphCLKInitTypeDef.
|
||||
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
|
||||
* contains the configuration information for the Extended Peripherals clocks(I2S, SAI, LTDC RTC and TIM clocks).
|
||||
* contains the configuration information for the Extended Peripherals
|
||||
* clocks(I2S, SAI, LTDC RTC and TIM).
|
||||
*
|
||||
* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
|
||||
* the RTC clock source; in this case the Backup domain will be reset in
|
||||
* order to modify the RTC Clock source, as consequence RTC registers (including
|
||||
* the backup registers) and RCC_BDCR register are set to their reset values.
|
||||
*
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
||||
|
|
@ -246,7 +258,51 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
|
|||
/*---------------------------- RTC configuration -------------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
||||
{
|
||||
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
||||
/* Enable Power Clock*/
|
||||
__PWR_CLK_ENABLE();
|
||||
|
||||
/* Enable write access to Backup domain */
|
||||
PWR->CR |= PWR_CR_DBP;
|
||||
|
||||
/* Wait for Backup domain Write protection disable */
|
||||
timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE;
|
||||
|
||||
while((PWR->CR & PWR_CR_DBP) == RESET)
|
||||
{
|
||||
if(HAL_GetTick() >= timeout)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Reset the Backup domain only if the RTC Clock source selction is modified */
|
||||
if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
|
||||
{
|
||||
/* Store the content of BDCR register before the reset of Backup Domain */
|
||||
tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
||||
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
||||
__HAL_RCC_BACKUPRESET_FORCE();
|
||||
__HAL_RCC_BACKUPRESET_RELEASE();
|
||||
/* Restore the Content of BDCR register */
|
||||
RCC->BDCR = tmpreg;
|
||||
}
|
||||
|
||||
/* If LSE is selected as RTC clock source, wait for LSE reactivation */
|
||||
if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
|
||||
{
|
||||
/* Get timeout */
|
||||
timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE;
|
||||
|
||||
/* Wait till LSE is ready */
|
||||
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
||||
{
|
||||
if(HAL_GetTick() >= timeout)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
||||
}
|
||||
|
||||
/*---------------------------- TIM configuration -------------------------------*/
|
||||
|
|
@ -304,11 +360,17 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|||
* RCC_PeriphCLKInitTypeDef.
|
||||
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
|
||||
* contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
|
||||
*
|
||||
* @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
|
||||
* the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
|
||||
* domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
|
||||
*
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
||||
{
|
||||
uint32_t timeout = 0;
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
||||
|
|
@ -356,7 +418,51 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
|
|||
/*---------------------------- RTC configuration -------------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
||||
{
|
||||
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
||||
/* Enable Power Clock*/
|
||||
__PWR_CLK_ENABLE();
|
||||
|
||||
/* Enable write access to Backup domain */
|
||||
PWR->CR |= PWR_CR_DBP;
|
||||
|
||||
/* Wait for Backup domain Write protection disable */
|
||||
timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE;
|
||||
|
||||
while((PWR->CR & PWR_CR_DBP) == RESET)
|
||||
{
|
||||
if(HAL_GetTick() >= timeout)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Reset the Backup domain only if the RTC Clock source selction is modified */
|
||||
if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
|
||||
{
|
||||
/* Store the content of BDCR register before the reset of Backup Domain */
|
||||
tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
||||
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
||||
__HAL_RCC_BACKUPRESET_FORCE();
|
||||
__HAL_RCC_BACKUPRESET_RELEASE();
|
||||
/* Restore the Content of BDCR register */
|
||||
RCC->BDCR = tmpreg;
|
||||
}
|
||||
|
||||
/* If LSE is selected as RTC clock source, wait for LSE reactivation */
|
||||
if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
|
||||
{
|
||||
/* Get timeout */
|
||||
timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE;
|
||||
|
||||
/* Wait till LSE is ready */
|
||||
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
||||
{
|
||||
if(HAL_GetTick() >= timeout)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_rcc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief Header file of RCC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -154,7 +154,7 @@ typedef struct
|
|||
RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
|
||||
This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
|
||||
|
||||
uint8_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
|
||||
uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
|
||||
This parameter can be a value of @ref RCC_RTC_Clock_Source */
|
||||
|
||||
}RCC_PeriphCLKInitTypeDef;
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_rng.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief RNG HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Random Number Generator (RNG) peripheral:
|
||||
|
|
@ -118,9 +118,6 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
|
|||
/* Init the low level hardware */
|
||||
HAL_RNG_MspInit(hrng);
|
||||
}
|
||||
|
||||
/* Change RNG peripheral state */
|
||||
hrng->State = HAL_RNG_STATE_BUSY;
|
||||
|
||||
/* Enable the RNG Peripheral */
|
||||
__HAL_RNG_ENABLE(hrng);
|
||||
|
|
@ -132,7 +129,6 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
|
|||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the RNG peripheral.
|
||||
* @param hrng: RNG handle
|
||||
|
|
@ -160,10 +156,13 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
|
|||
/* DeInit the low level hardware */
|
||||
HAL_RNG_MspDeInit(hrng);
|
||||
|
||||
/* Update the RNG state */
|
||||
/* Update the RNG state */
|
||||
hrng->State = HAL_RNG_STATE_RESET;
|
||||
|
||||
/* Return the function status */
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hrng);
|
||||
|
||||
/* Return the function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_rng.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief Header file of RNG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -182,15 +182,15 @@ typedef struct
|
|||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
|
||||
HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
|
||||
__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
|
||||
__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);
|
||||
uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
|
||||
__weak void HAL_RNG_ReadyCallback(RNG_HandleTypeDef* hrng);
|
||||
__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_ReadyCallback(RNG_HandleTypeDef* hrng);
|
||||
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
|
||||
|
||||
/* Peripheral State functions **************************************************/
|
||||
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_rtc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief RTC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Real Time Clock (RTC) peripheral:
|
||||
|
|
@ -151,18 +151,6 @@
|
|||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Masks Definition */
|
||||
#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
|
||||
#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
|
||||
#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
|
||||
#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
|
||||
#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
|
||||
RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
|
||||
RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
|
||||
RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
|
||||
RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
|
||||
|
||||
#define RTC_TIMEOUT_VALUE 1000
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
|
@ -334,7 +322,7 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
|
|||
hrtc->Instance->WUTR = (uint32_t)0x0000FFFF;
|
||||
hrtc->Instance->PRER = (uint32_t)0x007F00FF;
|
||||
hrtc->Instance->CALIBR = (uint32_t)0x00000000;
|
||||
hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
|
||||
hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
|
||||
hrtc->Instance->ALRMBR = (uint32_t)0x00000000;
|
||||
hrtc->Instance->SHIFTR = (uint32_t)0x00000000;
|
||||
hrtc->Instance->CALR = (uint32_t)0x00000000;
|
||||
|
|
@ -363,13 +351,16 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
|
|||
}
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* De-Initialize RTC MSP */
|
||||
HAL_RTC_MspDeInit(hrtc);
|
||||
|
||||
hrtc->State = HAL_RTC_STATE_RESET;
|
||||
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hrtc);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
|
@ -1030,7 +1021,10 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
|
|||
{
|
||||
/* Disable the Alarm A interrupt */
|
||||
__HAL_RTC_ALARMA_DISABLE(hrtc);
|
||||
|
||||
|
||||
/* Clear flag alarm A */
|
||||
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
|
||||
|
||||
timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
|
||||
/* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
|
||||
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
|
||||
|
|
@ -1061,7 +1055,10 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
|
|||
{
|
||||
/* Disable the Alarm B interrupt */
|
||||
__HAL_RTC_ALARMB_DISABLE(hrtc);
|
||||
|
||||
|
||||
/* Clear flag alarm B */
|
||||
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
|
||||
|
||||
timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
|
||||
/* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
|
||||
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief Header file of RTC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -694,8 +694,8 @@ typedef struct
|
|||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
|
||||
__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
|
||||
__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
|
||||
|
||||
/* RTC Time and Date functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||
|
|
@ -710,7 +710,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
|
|||
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
|
||||
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_rtc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief RTC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Real Time Clock (RTC) Extension peripheral:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_rtc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief Header file of RTC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -638,9 +638,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
|
|||
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
|
||||
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||
|
||||
__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
|
|
@ -651,7 +651,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
|
|||
uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
|
||||
uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||
__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
|
||||
/* Extension Control functions ************************************************/
|
||||
|
|
@ -670,7 +670,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
|
|||
HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
|
||||
|
||||
/* Extension RTC features functions *******************************************/
|
||||
__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_sai.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief SAI HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Serial Audio Interface (SAI) peripheral:
|
||||
|
|
@ -440,14 +440,14 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
|
|||
/*Set MCKDIV value in CR1 register*/
|
||||
hsai->Instance->CR1 |= (tmpclock << 20);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/* Initialise the error code */
|
||||
hsai->ErrorCode = HAL_SAI_ERROR_NONE;
|
||||
|
||||
|
||||
/* Initialize the SAI state */
|
||||
hsai->State= HAL_SAI_STATE_READY;
|
||||
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
|
@ -463,9 +463,9 @@ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
|
|||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
|
||||
hsai->State = HAL_SAI_STATE_BUSY;
|
||||
|
||||
|
||||
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
|
||||
HAL_SAI_MspDeInit(hsai);
|
||||
|
||||
|
|
@ -474,7 +474,10 @@ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
|
|||
|
||||
/* Initialize the SAI state */
|
||||
hsai->State = HAL_SAI_STATE_RESET;
|
||||
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hsai);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
|
@ -910,10 +913,17 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
|
|||
/* Disable the SAI DMA request */
|
||||
hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
|
||||
|
||||
/* Disable the SAI DMA Stream */
|
||||
__HAL_DMA_DISABLE(hsai->hdmatx);
|
||||
__HAL_DMA_DISABLE(hsai->hdmarx);
|
||||
|
||||
/* Abort the SAI DMA Tx Stream */
|
||||
if(hsai->hdmatx != NULL)
|
||||
{
|
||||
HAL_DMA_Abort(hsai->hdmatx);
|
||||
}
|
||||
/* Abort the SAI DMA Rx Stream */
|
||||
if(hsai->hdmarx != NULL)
|
||||
{
|
||||
HAL_DMA_Abort(hsai->hdmarx);
|
||||
}
|
||||
|
||||
/* Disable SAI peripheral */
|
||||
__HAL_SAI_DISABLE(hsai);
|
||||
|
||||
|
|
@ -1219,19 +1229,37 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
|
|||
*/
|
||||
static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
uint32_t timeout = 0x00;
|
||||
|
||||
SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
|
||||
hsai->TxXferCount = 0;
|
||||
hsai->RxXferCount = 0;
|
||||
|
||||
/* Disable SAI Tx DMA Request */
|
||||
hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
|
||||
|
||||
/* Flush Fifo*/
|
||||
hsai->Instance->CR2 |= SAI_xCR2_FFLUSH;
|
||||
|
||||
hsai->State= HAL_SAI_STATE_READY;
|
||||
|
||||
|
||||
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
|
||||
{
|
||||
hsai->TxXferCount = 0;
|
||||
hsai->RxXferCount = 0;
|
||||
|
||||
/* Disable SAI Tx DMA Request */
|
||||
hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
|
||||
|
||||
/* Set timeout: 10 is the max delay to send the remaining data in the SAI FIFO */
|
||||
timeout = HAL_GetTick() + 10;
|
||||
|
||||
/* Wait until FIFO is empty */
|
||||
while(__HAL_SAI_GET_FLAG(hsai, SAI_xSR_FLVL) != RESET)
|
||||
{
|
||||
/* Check for the Timeout */
|
||||
if(HAL_GetTick() >= timeout)
|
||||
{
|
||||
/* Update error code */
|
||||
hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
|
||||
|
||||
/* Change the SAI state */
|
||||
HAL_SAI_ErrorCallback(hsai);
|
||||
}
|
||||
}
|
||||
|
||||
hsai->State= HAL_SAI_STATE_READY;
|
||||
}
|
||||
HAL_SAI_TxCpltCallback(hsai);
|
||||
}
|
||||
|
||||
|
|
@ -1255,12 +1283,14 @@ static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
|
|||
static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
|
||||
/* Disable Rx DMA Request */
|
||||
hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
|
||||
hsai->RxXferCount = 0;
|
||||
|
||||
hsai->State = HAL_SAI_STATE_READY;
|
||||
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
|
||||
{
|
||||
/* Disable Rx DMA Request */
|
||||
hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
|
||||
hsai->RxXferCount = 0;
|
||||
|
||||
hsai->State = HAL_SAI_STATE_READY;
|
||||
}
|
||||
HAL_SAI_RxCpltCallback(hsai);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_sai.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief Header file of SAI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -735,11 +735,11 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
|
|||
|
||||
/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
|
||||
__weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
__weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
__weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
__weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
__weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
|
||||
|
||||
/* Peripheral State functions **************************************************/
|
||||
HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_sd.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief SD card HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Secure Digital (SD) peripheral:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_sd.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief Header file of SD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -610,8 +610,8 @@ typedef enum
|
|||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
|
||||
HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
|
||||
__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
|
||||
__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
|
||||
|
||||
/* I/O operation functions *****************************************************/
|
||||
/* Blocking mode: Polling */
|
||||
|
|
@ -623,12 +623,12 @@ HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint
|
|||
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
|
||||
|
||||
/* Callback in non blocking modes (DMA) */
|
||||
__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
|
||||
__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
|
||||
__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
|
||||
__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
|
||||
__weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
|
||||
__weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_sdram.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief SDRAM HAL module driver.
|
||||
* This file provides a generic firmware to drive SDRAM memories mounted
|
||||
* as external device.
|
||||
|
|
@ -102,7 +102,6 @@
|
|||
* @{
|
||||
*/
|
||||
#ifdef HAL_SDRAM_MODULE_ENABLED
|
||||
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
|
|
@ -176,10 +175,16 @@ HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
|
|||
{
|
||||
/* Initialize the low level hardware (MSP) */
|
||||
HAL_SDRAM_MspDeInit(hsdram);
|
||||
|
||||
|
||||
/* Configure the SDRAM registers with their reset values */
|
||||
FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
|
||||
|
||||
|
||||
/* Reset the SDRAM controller state */
|
||||
hsdram->State = HAL_SDRAM_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hsdram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
|
@ -309,11 +314,11 @@ HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddr
|
|||
{
|
||||
*pDstBuffer = *(__IO uint8_t *)pSdramAddress;
|
||||
pDstBuffer++;
|
||||
pSdramAddress++;
|
||||
pSdramAddress++;
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hsdram);
|
||||
__HAL_UNLOCK(hsdram);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
|
@ -352,7 +357,7 @@ HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd
|
|||
{
|
||||
*(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
|
||||
pSrcBuffer++;
|
||||
pSdramAddress++;
|
||||
pSdramAddress++;
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_sdram.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief Header file of SDRAM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -96,13 +96,13 @@ typedef struct
|
|||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
|
||||
HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
|
||||
__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
|
||||
__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
|
||||
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
|
||||
void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
|
||||
|
||||
void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
|
||||
__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
|
||||
__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
|
||||
__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
|
||||
void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/* I/O operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_smartcard.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief SMARTCARD HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the SMARTCARD peripheral:
|
||||
|
|
@ -64,7 +64,7 @@
|
|||
add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
|
||||
(+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT()
|
||||
(+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
|
||||
add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
|
||||
add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
|
||||
(+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
|
||||
add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
|
||||
|
||||
|
|
@ -76,7 +76,7 @@
|
|||
add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
|
||||
(+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
|
||||
(+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
|
||||
add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
|
||||
add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
|
||||
(+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
|
||||
add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
|
||||
|
||||
|
|
@ -140,6 +140,7 @@
|
|||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define SMARTCARD_TIMEOUT_VALUE 22000
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
|
@ -291,7 +292,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
|
||||
{
|
||||
/* Check the SMARTCARD handle allocation */
|
||||
/* Check the SMARTCARD handle allocation */
|
||||
if(hsc == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
|
|
@ -308,6 +309,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
|
|||
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
|
||||
hsc->State = HAL_SMARTCARD_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hsc);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
|
@ -899,7 +903,7 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc)
|
|||
* @param hdma : DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
|
||||
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||
|
||||
|
|
@ -908,10 +912,20 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
|
|||
/* Disable the DMA transfer for transmit request by setting the DMAT bit
|
||||
in the USART CR3 register */
|
||||
hsc->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
|
||||
|
||||
hsc->State= HAL_SMARTCARD_STATE_READY;
|
||||
|
||||
HAL_SMARTCARD_TxCpltCallback(hsc);
|
||||
|
||||
/* Wait for SMARTCARD TC Flag */
|
||||
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, SMARTCARD_TIMEOUT_VALUE) != HAL_OK)
|
||||
{
|
||||
/* Timeout Occured */
|
||||
hsc->State = HAL_SMARTCARD_STATE_TIMEOUT;
|
||||
HAL_SMARTCARD_ErrorCallback(hsc);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No Timeout */
|
||||
hsc->State= HAL_SMARTCARD_STATE_READY;
|
||||
HAL_SMARTCARD_TxCpltCallback(hsc);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_smartcard.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0RC2
|
||||
* @date 04-February-2014
|
||||
* @version V1.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief Header file of SMARTCARD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -410,8 +410,8 @@ typedef struct
|
|||
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
|
||||
__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
|
||||
__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
|
||||
/* IO operation functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
|
|
@ -420,9 +420,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t
|
|||
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
|
||||
void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
|
||||
__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||
__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||
__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||
void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||
|
||||
/* Peripheral State functions **************************************************/
|
||||
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
|
||||
|
|
|
|||
Loading…
Reference in New Issue