STM32WL : ADDING STM32 SUPPORT

Add code concerning all STM32 platforms
pull/14207/head
reme 2021-01-26 10:50:31 +01:00
parent e6565a4486
commit 5a2835c18c
17 changed files with 74 additions and 60 deletions

View File

@ -15,6 +15,7 @@ add_subdirectory(TARGET_STM32L1 EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32L4 EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32L4 EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32L5 EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32L5 EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32WB EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32WB EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32WL EXCLUDE_FROM_ALL)
add_library(STM INTERFACE) add_library(STM INTERFACE)

View File

@ -92,14 +92,14 @@ static void _can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_FDCAN; RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
RCC_PeriphClkInit.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL; // 10 MHz (RCC_OscInitStruct.PLL.PLLQ = 80) RCC_PeriphClkInit.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL; // 10 MHz (RCC_OscInitStruct.PLL.PLLQ = 80)
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
error("HAL_RCCEx_PeriphCLKConfig error\n"); error("HAL_RCCEx_PeriphCLKConfig error\n");
} }
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
// Configure CAN pins // Configure CAN pins
@ -247,13 +247,13 @@ void can_irq_free(can_t *obj)
void can_free(can_t *obj) void can_free(can_t *obj)
{ {
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
__HAL_RCC_FDCAN_FORCE_RESET(); __HAL_RCC_FDCAN_FORCE_RESET();
__HAL_RCC_FDCAN_RELEASE_RESET(); __HAL_RCC_FDCAN_RELEASE_RESET();
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
__HAL_RCC_FDCAN_CLK_DISABLE(); __HAL_RCC_FDCAN_CLK_DISABLE();
@ -772,7 +772,7 @@ void can_irq_free(can_t *obj)
void can_free(can_t *obj) void can_free(can_t *obj)
{ {
CANName can = (CANName) obj->CanHandle.Instance; CANName can = (CANName) obj->CanHandle.Instance;
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
@ -796,7 +796,7 @@ void can_free(can_t *obj)
__HAL_RCC_CAN3_CLK_DISABLE(); __HAL_RCC_CAN3_CLK_DISABLE();
} }
#endif #endif
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
} }

View File

@ -170,7 +170,7 @@ void gpio_mode(gpio_t *obj, PinMode mode)
inline void gpio_dir(gpio_t *obj, PinDirection direction) inline void gpio_dir(gpio_t *obj, PinDirection direction)
{ {
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
@ -181,7 +181,7 @@ inline void gpio_dir(gpio_t *obj, PinDirection direction)
LL_GPIO_SetPinMode(obj->gpio, obj->ll_pin, LL_GPIO_MODE_OUTPUT); LL_GPIO_SetPinMode(obj->gpio, obj->ll_pin, LL_GPIO_MODE_OUTPUT);
} }
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
} }

View File

@ -149,7 +149,7 @@ static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line)
#else /* TARGET_STM32L5 */ #else /* TARGET_STM32L5 */
// Clear interrupt flag // Clear interrupt flag
#if defined(DUAL_CORE) && defined(CORE_CM4) #if defined(DUAL_CORE) && defined(CORE_CM4) && defined(TARGET_STM32H7)
if (__HAL_GPIO_EXTID2_GET_FLAG(pin) != RESET) { if (__HAL_GPIO_EXTID2_GET_FLAG(pin) != RESET) {
__HAL_GPIO_EXTID2_CLEAR_FLAG(pin); __HAL_GPIO_EXTID2_CLEAR_FLAG(pin);
#else #else
@ -323,7 +323,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
core_util_critical_section_enter(); core_util_critical_section_enter();
/* Enable SYSCFG Clock */ /* Enable SYSCFG Clock */
#if !defined(TARGET_STM32WB) #if (!defined(TARGET_STM32WB) && !defined(TARGET_STM32WL))
__HAL_RCC_SYSCFG_CLK_ENABLE(); __HAL_RCC_SYSCFG_CLK_ENABLE();
#endif #endif
@ -503,7 +503,7 @@ void gpio_irq_enable(gpio_irq_t *obj)
SYSCFG->EXTICR[pin_index >> 2] = temp; SYSCFG->EXTICR[pin_index >> 2] = temp;
#endif #endif
#if defined(DUAL_CORE) && defined(CORE_CM4) #if defined(DUAL_CORE) && defined(CORE_CM4) && defined(TARGET_STM32H7)
LL_C2_EXTI_EnableIT_0_31(1 << pin_index); LL_C2_EXTI_EnableIT_0_31(1 << pin_index);
#else #else
LL_EXTI_EnableIT_0_31(1 << pin_index); LL_EXTI_EnableIT_0_31(1 << pin_index);
@ -532,7 +532,7 @@ void gpio_irq_disable(gpio_irq_t *obj)
LL_EXTI_DisableRisingTrig_0_31(1 << pin_index); LL_EXTI_DisableRisingTrig_0_31(1 << pin_index);
LL_EXTI_DisableFallingTrig_0_31(1 << pin_index); LL_EXTI_DisableFallingTrig_0_31(1 << pin_index);
#if defined(DUAL_CORE) && defined(CORE_CM4) #if defined(DUAL_CORE) && defined(CORE_CM4) && defined(TARGET_STM32H7)
LL_C2_EXTI_DisableIT_0_31(1 << pin_index); LL_C2_EXTI_DisableIT_0_31(1 << pin_index);
#else #else
LL_EXTI_DisableIT_0_31(1 << pin_index); LL_EXTI_DisableIT_0_31(1 << pin_index);

View File

@ -57,7 +57,7 @@ typedef struct {
static inline void gpio_write(gpio_t *obj, int value) static inline void gpio_write(gpio_t *obj, int value)
{ {
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
@ -72,7 +72,7 @@ static inline void gpio_write(gpio_t *obj, int value)
#endif #endif
} }
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
} }

View File

@ -214,7 +214,7 @@ void i2c_hw_reset(i2c_t *obj)
// wait before reset // wait before reset
timeout = BYTE_TIMEOUT; timeout = BYTE_TIMEOUT;
while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0)); while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
@ -248,7 +248,7 @@ void i2c_hw_reset(i2c_t *obj)
__HAL_RCC_FMPI2C1_RELEASE_RESET(); __HAL_RCC_FMPI2C1_RELEASE_RESET();
} }
#endif #endif
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
} }
@ -497,7 +497,7 @@ void i2c_frequency(i2c_t *obj, int hz)
#endif //I2C_IP_VERSION_V2 #endif //I2C_IP_VERSION_V2
/*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/ /*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
@ -521,7 +521,7 @@ void i2c_frequency(i2c_t *obj, int hz)
__HAL_RCC_I2C4_CONFIG(I2CAPI_I2C4_CLKSRC); __HAL_RCC_I2C4_CONFIG(I2CAPI_I2C4_CLKSRC);
} }
#endif #endif
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */

View File

@ -55,7 +55,7 @@
#define LP_TIMER_SAFE_GUARD 5 #define LP_TIMER_SAFE_GUARD 5
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
#if defined(CORE_CM7) #if defined(CORE_CM7)
#define LPTIM_MST_BASE LPTIM4_BASE #define LPTIM_MST_BASE LPTIM4_BASE
#define LPTIM_MST ((LPTIM_TypeDef *)LPTIM_MST_BASE) #define LPTIM_MST ((LPTIM_TypeDef *)LPTIM_MST_BASE)
@ -212,7 +212,7 @@ void lp_ticker_init(void)
#endif /* TARGET_STM32L0 */ #endif /* TARGET_STM32L0 */
#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
@ -229,7 +229,7 @@ void lp_ticker_init(void)
LPTIM_MST_RCC(); LPTIM_MST_RCC();
LPTIM_MST_RESET_ON(); LPTIM_MST_RESET_ON();
LPTIM_MST_RESET_OFF(); LPTIM_MST_RESET_OFF();
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
/* Configure EXTI wakeup and configure autonomous mode */ /* Configure EXTI wakeup and configure autonomous mode */
LPTIM_MST_RCC_CLKAM(); LPTIM_MST_RCC_CLKAM();
LPTIM_MST_EXTI_LPTIM_WAKEUP_CONFIG(); LPTIM_MST_EXTI_LPTIM_WAKEUP_CONFIG();
@ -283,6 +283,11 @@ void lp_ticker_init(void)
NVIC_SetVector(LPTIM_MST_IRQ, (uint32_t)LPTIM_IRQHandler); NVIC_SetVector(LPTIM_MST_IRQ, (uint32_t)LPTIM_IRQHandler);
#if (LPTIM_MST_BASE == LPTIM1_BASE)
#if defined (__HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT)
__HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT();
#endif
#endif
#if defined (__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT) #if defined (__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT)
/* EXTI lines are not configured by default */ /* EXTI lines are not configured by default */
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();

View File

@ -179,7 +179,7 @@ void mbed_sdk_init()
} }
#endif /* __ICACHE_PRESENT */ #endif /* __ICACHE_PRESENT */
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
/* HW semaphore Clock enable*/ /* HW semaphore Clock enable*/
__HAL_RCC_HSEM_CLK_ENABLE(); __HAL_RCC_HSEM_CLK_ENABLE();

View File

@ -82,7 +82,7 @@ void pin_function(PinName pin, int data)
#if defined (TARGET_STM32F1) #if defined (TARGET_STM32F1)
if (mode == STM_PIN_OUTPUT) { if (mode == STM_PIN_OUTPUT) {
#endif #endif
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
@ -99,7 +99,7 @@ void pin_function(PinName pin, int data)
LL_GPIO_SetPinSpeed(gpio, ll_pin, speed); LL_GPIO_SetPinSpeed(gpio, ll_pin, speed);
break; break;
} }
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
#if defined (TARGET_STM32F1) #if defined (TARGET_STM32F1)
@ -126,7 +126,7 @@ void pin_function(PinName pin, int data)
break; break;
} }
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
@ -155,7 +155,7 @@ void pin_function(PinName pin, int data)
stm_pin_DisconnectDebug(pin); stm_pin_DisconnectDebug(pin);
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
} }
@ -174,7 +174,7 @@ void pin_mode(PinName pin, PinMode mode)
// Enable GPIO clock // Enable GPIO clock
GPIO_TypeDef *gpio = Set_GPIO_Clock(port_index); GPIO_TypeDef *gpio = Set_GPIO_Clock(port_index);
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
@ -197,7 +197,7 @@ void pin_mode(PinName pin, PinMode mode)
stm_pin_PullConfig(gpio, ll_pin, GPIO_NOPULL); stm_pin_PullConfig(gpio, ll_pin, GPIO_NOPULL);
} }
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
} }

View File

@ -540,13 +540,13 @@ static qspi_status_t _qspi_init_direct(qspi_t *obj, const qspi_pinmap_t *pinmap,
__HAL_RCC_QSPI_CLK_ENABLE(); __HAL_RCC_QSPI_CLK_ENABLE();
// Reset QSPI // Reset QSPI
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
__HAL_RCC_QSPI_FORCE_RESET(); __HAL_RCC_QSPI_FORCE_RESET();
__HAL_RCC_QSPI_RELEASE_RESET(); __HAL_RCC_QSPI_RELEASE_RESET();
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
@ -675,13 +675,13 @@ qspi_status_t qspi_free(qspi_t *obj)
} }
// Reset QSPI // Reset QSPI
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
__HAL_RCC_QSPI_FORCE_RESET(); __HAL_RCC_QSPI_FORCE_RESET();
__HAL_RCC_QSPI_RELEASE_RESET(); __HAL_RCC_QSPI_RELEASE_RESET();
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */

View File

@ -58,7 +58,7 @@ void rtc_init(void)
__HAL_RCC_PWR_CLK_ENABLE(); __HAL_RCC_PWR_CLK_ENABLE();
HAL_PWR_EnableBkUpAccess(); HAL_PWR_EnableBkUpAccess();
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
@ -102,7 +102,7 @@ void rtc_init(void)
error("PeriphClkInitStruct RTC failed with LSI\n"); error("PeriphClkInitStruct RTC failed with LSI\n");
} }
#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */

View File

@ -223,7 +223,7 @@ void serial_free(serial_t *obj)
struct serial_s *obj_s = SERIAL_S(obj); struct serial_s *obj_s = SERIAL_S(obj);
// Reset UART and disable clock // Reset UART and disable clock
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
@ -346,7 +346,7 @@ void serial_free(serial_t *obj)
__HAL_RCC_LPUART1_CLK_DISABLE(); __HAL_RCC_LPUART1_CLK_DISABLE();
} }
#endif #endif
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
@ -386,24 +386,24 @@ void serial_baud(serial_t *obj, int baudrate)
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF;
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
HAL_RCC_OscConfig(&RCC_OscInitStruct); HAL_RCC_OscConfig(&RCC_OscInitStruct);
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
} }
// Keep it to verify if HAL_RCC_OscConfig didn't exit with a timeout // Keep it to verify if HAL_RCC_OscConfig didn't exit with a timeout
if (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY)) { if (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY)) {
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE; PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
if (init_uart(obj) == HAL_OK) { if (init_uart(obj) == HAL_OK) {
@ -427,24 +427,24 @@ void serial_baud(serial_t *obj, int baudrate)
RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
HAL_RCC_OscConfig(&RCC_OscInitStruct); HAL_RCC_OscConfig(&RCC_OscInitStruct);
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
} }
// Keep it to verify if HAL_RCC_OscConfig didn't exit with a timeout // Keep it to verify if HAL_RCC_OscConfig didn't exit with a timeout
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY)) { if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY)) {
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
if (init_uart(obj) == HAL_OK) { if (init_uart(obj) == HAL_OK) {
@ -454,12 +454,12 @@ void serial_baud(serial_t *obj, int baudrate)
#endif #endif
// Last chance using SYSCLK // Last chance using SYSCLK
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_SYSCLK; PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_SYSCLK;
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
} }

View File

@ -181,7 +181,8 @@ __WEAK void hal_deepsleep(void)
save_timer_ctx(); save_timer_ctx();
// Request to enter STOP mode with regulator in low power mode // Request to enter STOP mode with regulator in low power mode
#ifdef PWR_CR1_LPMS_STOP2 /* STM32L4 */ //PWR_CR1_LPMS_STOP2 -> STM32L4 ; PWR_LOWPOWERMODE_STOP2 -> STM32WL
#if defined (PWR_CR1_LPMS_STOP2) || defined(PWR_LOWPOWERMODE_STOP2)
int pwrClockEnabled = __HAL_RCC_PWR_IS_CLK_ENABLED(); int pwrClockEnabled = __HAL_RCC_PWR_IS_CLK_ENABLED();
int lowPowerModeEnabled = PWR->CR1 & PWR_CR1_LPR; int lowPowerModeEnabled = PWR->CR1 & PWR_CR1_LPR;
@ -204,7 +205,7 @@ __WEAK void hal_deepsleep(void)
if (!pwrClockEnabled) { if (!pwrClockEnabled) {
__HAL_RCC_PWR_CLK_DISABLE(); __HAL_RCC_PWR_CLK_DISABLE();
} }
#elif defined(DUAL_CORE) #elif defined(DUAL_CORE) && (TARGET_STM32H7)
int lowPowerModeEnabled = LL_PWR_GetRegulModeDS(); int lowPowerModeEnabled = LL_PWR_GetRegulModeDS();
#if defined(CORE_CM7) #if defined(CORE_CM7)
@ -232,7 +233,7 @@ __WEAK void hal_deepsleep(void)
mbed_sdk_inited = 0; mbed_sdk_inited = 0;
/* After wake-up from STOP reconfigure the PLL */ /* After wake-up from STOP reconfigure the PLL */
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
/* CFG_HW_STOP_MODE_SEMID is used to protect read access to STOP flag, and this avoid both core to configure clocks if both exit from stop at the same time */ /* CFG_HW_STOP_MODE_SEMID is used to protect read access to STOP flag, and this avoid both core to configure clocks if both exit from stop at the same time */
while (LL_HSEM_1StepLock(HSEM, CFG_HW_STOP_MODE_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_STOP_MODE_SEMID)) {
} }

View File

@ -320,7 +320,7 @@ void spi_free(spi_t *obj)
__HAL_SPI_DISABLE(handle); __HAL_SPI_DISABLE(handle);
HAL_SPI_DeInit(handle); HAL_SPI_DeInit(handle);
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
@ -371,7 +371,7 @@ void spi_free(spi_t *obj)
__HAL_RCC_SPI6_CLK_DISABLE(); __HAL_RCC_SPI6_CLK_DISABLE();
} }
#endif #endif
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
// Configure GPIOs // Configure GPIOs

View File

@ -37,7 +37,7 @@ void trng_init(trng_t *obj)
{ {
uint32_t dummy; uint32_t dummy;
#if defined(RCC_PERIPHCLK_RNG) /* STM32L4 / STM32H7 / STM32WB / STM32G4 */ #if defined(RCC_PERIPHCLK_RNG) /* STM32L4 */ /* STM32H7 */ /* STM32WB */ /* STM32G4 */ /* STM32WL */
#if defined(TARGET_STM32WB) #if defined(TARGET_STM32WB)
/* No need to configure RngClockSelection as already done in SetSysClock */ /* No need to configure RngClockSelection as already done in SetSysClock */
@ -48,17 +48,24 @@ void trng_init(trng_t *obj)
/*Select PLLQ output as RNG clock source */ /*Select PLLQ output as RNG clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG; PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG;
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLL; PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLL;
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
error("RNG clock configuration error\n"); error("RNG clock configuration error\n");
} }
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
#elif defined(TARGET_STM32WL)
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
/*Select PLLQ output as RNG clock source*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG;
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_MSI;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
error("RNG clock configuration error\n");
}
#elif defined(TARGET_STM32L4) #elif defined(TARGET_STM32L4)
/* RNG and USB clocks have the same source, so the common source selection could be already done by USB */ /* RNG and USB clocks have the same source, so the common source selection could be already done by USB */
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;

View File

@ -73,13 +73,13 @@ void init_16bit_timer(void)
TIM_MST_RCC; TIM_MST_RCC;
// Reset timer // Reset timer
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
TIM_MST_RESET_ON; TIM_MST_RESET_ON;
TIM_MST_RESET_OFF; TIM_MST_RESET_OFF;
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
@ -162,13 +162,13 @@ void init_32bit_timer(void)
TIM_MST_RCC; TIM_MST_RCC;
// Reset timer // Reset timer
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
} }
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
TIM_MST_RESET_ON; TIM_MST_RESET_ON;
TIM_MST_RESET_OFF; TIM_MST_RESET_OFF;
#if defined(DUAL_CORE) #if defined(DUAL_CORE) && (TARGET_STM32H7)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */

View File

@ -137,7 +137,7 @@ watchdog_features_t hal_watchdog_get_platform_features(void)
features.clock_max_frequency = 47000; features.clock_max_frequency = 47000;
#elif defined(STM32F0) || defined(STM32F3) #elif defined(STM32F0) || defined(STM32F3)
features.clock_max_frequency = 50000; features.clock_max_frequency = 50000;
#elif defined(STM32H7) || defined(STM32L4) || defined(STM32WB) #elif defined(STM32H7) || defined(STM32L4) || defined(STM32WB) || defined(STM32WL)
features.clock_max_frequency = 33600; features.clock_max_frequency = 33600;
#elif defined(STM32G0) || defined(STM32L5) || defined(STM32G4) #elif defined(STM32G0) || defined(STM32L5) || defined(STM32G4)
features.clock_max_frequency = 34000; features.clock_max_frequency = 34000;