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Merge pull request #11014 from SiliconLabs/fix/fpga_tests/adc_methodology 

Increase ADC tolerance to 5% in FPGA-based tests
pull/11062/head
Seppo Takalo 2019-07-17 14:29:37 +03:00 committed by GitHub
parent 0a4e5146b0 f6a70b2028
commit 59b9f1da17
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1 changed files with 2 additions and 2 deletions
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TESTS/mbed_hal_fpga_ci_test_shield/analogin/main.cpp
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@ -36,8 +36,8 @@ using namespace utest::v1;
#define analogin_debug_printf(...)
#define DELTA_FLOAT 0.03f // 3%
#define DELTA_U16 1965 // 3%
#define DELTA_FLOAT 0.05f // 5%
#define DELTA_U16 3277 // 5%
const PinList *form_factor = pinmap_ff_default_pins();
const PinList *restricted = pinmap_restricted_pins();