From c8ef00561255c533317556ec63159170bc473225 Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Thu, 14 May 2015 16:46:10 +0900 Subject: [PATCH 01/26] add WIZNET TARGET --- .../TOOLCHAIN_ARM_MICRO/W7500.sct | 15 + .../TOOLCHAIN_ARM_MICRO/startup_W7500x.s | 213 +++ .../TOOLCHAIN_ARM_MICRO/sys.cpp | 31 + .../TOOLCHAIN_GCC_ARM/W7500.ld | 152 +++ .../TOOLCHAIN_GCC_ARM/startup_W7500.s | 259 ++++ .../TARGET_WIZwiki_W7500/W7500x.h | 1148 +++++++++++++++++ .../TARGET_WIZwiki_W7500/cmsis.h | 38 + .../TARGET_WIZwiki_W7500/cmsis_nvic.c | 47 + .../TARGET_WIZwiki_W7500/cmsis_nvic.h | 51 + .../TARGET_WIZwiki_W7500/system_W7500x.c | 104 ++ .../TARGET_WIZwiki_W7500/system_W7500x.h | 84 ++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_adc.c | 54 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_adc.h | 59 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_conf.h | 15 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_crg.c | 276 ++++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_crg.h | 145 +++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_exti.c | 157 +++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_exti.h | 86 ++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.c | 288 +++++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.h | 134 ++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.c | 563 ++++++++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.h | 231 ++++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.c | 905 +++++++++++++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.h | 289 +++++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_uart.c | 370 ++++++ .../TARGET_WIZNET/TARGET_W7500x/W7500x_uart.h | 289 +++++ .../TARGET_W7500x/PeripheralPins.h | 26 + .../TARGET_WIZwiki_W7500/PeripheralNames.h | 77 ++ .../TARGET_WIZwiki_W7500/PeripheralPins.c | 106 ++ .../TARGET_WIZwiki_W7500/PinNames.h | 197 +++ .../TARGET_WIZwiki_W7500/PortNames.h | 48 + .../TARGET_WIZwiki_W7500/device.h | 74 ++ .../TARGET_WIZwiki_W7500/objects.h | 98 ++ .../TARGET_W7500x/analogin_api.c | 102 ++ .../TARGET_W7500x/analogout_api.c | 64 + .../TARGET_WIZNET/TARGET_W7500x/gpio_api.c | 62 + .../TARGET_W7500x/gpio_irq_api.c | 148 +++ .../TARGET_WIZNET/TARGET_W7500x/gpio_object.h | 86 ++ .../hal/TARGET_WIZNET/TARGET_W7500x/i2c_api.c | 316 +++++ .../TARGET_W7500x/mbed_overrides.c | 24 + .../hal/TARGET_WIZNET/TARGET_W7500x/pinmap.c | 139 ++ .../TARGET_WIZNET/TARGET_W7500x/port_api.c | 96 ++ .../TARGET_WIZNET/TARGET_W7500x/pwmout_api.c | 0 .../hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c | 0 .../TARGET_WIZNET/TARGET_W7500x/serial_api.c | 280 ++++ .../hal/TARGET_WIZNET/TARGET_W7500x/sleep.c | 43 + .../hal/TARGET_WIZNET/TARGET_W7500x/spi_api.c | 187 +++ .../TARGET_WIZNET/TARGET_W7500x/us_ticker.c | 121 ++ 48 files changed, 8297 insertions(+) create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/W7500.sct create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/W7500.ld create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/startup_W7500.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/W7500x.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_conf.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_exti.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_exti.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.h create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PinNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PortNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/objects.h create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogout_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_object.h create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/i2c_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/mbed_overrides.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pinmap.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/port_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/sleep.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/spi_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/W7500.sct b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/W7500.sct new file mode 100644 index 0000000000..f9ead04667 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/W7500.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00020000 { ; load region size_region + ER_IROM1 0x00000000 0x00020000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00004000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s new file mode 100644 index 0000000000..1cbb5d3f56 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s @@ -0,0 +1,213 @@ +;/**************************************************************************//** +; * @file startup_CMSDK_CM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File for +; * Device CMSDK_CM0 +; * @version V3.01 +; * @date 06. March 2012 +; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER + +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000100 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + DCD SSP0_Handler ; 16+ 0: SSP 0 Handler + DCD SSP1_Handler ; 16+ 1: SSP 1 Handler + DCD UART0_Handler ; 16+ 2: UART 0 Handler + DCD UART1_Handler ; 16+ 3: UART 1 Handler + DCD UART2_Handler ; 16+ 4: UART 2 Handler + DCD I2C0_Handler ; 16+ 5: I2C 0 Handler + DCD I2C1_Handler ; 16+ 6: I2C 1 Handler + DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler + DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler + DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler + DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler + DCD DMA_Handler ; 16+11: DMA Combined Handler + DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler + DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler + DCD PWM0_Handler ; 16+14: PWM0 Handler + DCD PWM1_Handler ; 16+15: PWM1 Handler + DCD PWM2_Handler ; 16+16: PWM2 Handler + DCD PWM3_Handler ; 16+17: PWM3 Handler + DCD PWM4_Handler ; 16+18: PWM4 Handler + DCD PWM5_Handler ; 16+19: PWM5 Handler + DCD PWM6_Handler ; 16+20: PWM6 Handler + DCD PWM7_Handler ; 16+21: PWM7 Handler + DCD RTC_Handler ; 16+22: RTC Handler + DCD ADC_Handler ; 16+23: ADC Handler + DCD WZTOE_Handler ; 16+24: WZTOE_Handler + DCD EXTI_Handler ; 16+25: EXTI_Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Default_Handler PROC + EXPORT SSP0_Handler [WEAK] + EXPORT SSP1_Handler [WEAK] + EXPORT UART0_Handler [WEAK] + EXPORT UART1_Handler [WEAK] + EXPORT UART2_Handler [WEAK] + EXPORT I2C0_Handler [WEAK] + EXPORT I2C1_Handler [WEAK] + EXPORT PORT0_Handler [WEAK] + EXPORT PORT1_Handler [WEAK] + EXPORT PORT2_Handler [WEAK] + EXPORT PORT3_Handler [WEAK] + EXPORT DMA_Handler [WEAK] + EXPORT DUALTIMER0_Handler [WEAK] + EXPORT DUALTIMER1_Handler [WEAK] + EXPORT PWM0_Handler [WEAK] + EXPORT PWM1_Handler [WEAK] + EXPORT PWM2_Handler [WEAK] + EXPORT PWM3_Handler [WEAK] + EXPORT PWM4_Handler [WEAK] + EXPORT PWM5_Handler [WEAK] + EXPORT PWM6_Handler [WEAK] + EXPORT PWM7_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT WZTOE_Handler [WEAK] + EXPORT EXTI_Handler [WEAK] +SSP0_Handler +SSP1_Handler +UART0_Handler +UART1_Handler +UART2_Handler +I2C0_Handler +I2C1_Handler +PORT0_Handler +PORT1_Handler +PORT2_Handler +PORT3_Handler +DMA_Handler +DUALTIMER0_Handler +DUALTIMER1_Handler +PWM0_Handler +PWM1_Handler +PWM2_Handler +PWM3_Handler +PWM4_Handler +PWM5_Handler +PWM6_Handler +PWM7_Handler +RTC_Handler +ADC_Handler +WZTOE_Handler +EXTI_Handler + B . + ENDP + + + ALIGN + + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/sys.cpp new file mode 100644 index 0000000000..2f1024ace8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/sys.cpp @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library - stackheap + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/W7500.ld b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/W7500.ld new file mode 100644 index 0000000000..0d53146fc5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/W7500.ld @@ -0,0 +1,152 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 /* 16K */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/startup_W7500.s b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/startup_W7500.s new file mode 100644 index 0000000000..2808b2ad57 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/startup_W7500.s @@ -0,0 +1,259 @@ +/* File: startup_W7500.s + * Purpose: startup file for Cortex-M0 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.4 + * Date: 20 Dezember 2012 + * + */ +/* Copyright (c) 2011 - 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x200 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + +/* Vector Table */ + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long SSP0_Handler /* 16+ 0: SSP 0 Handler */ + .long SSP1_Handler /* 16+ 1: SSP 1 Handler */ + .long UART0_Handler /* 16+ 2: UART 0 Handler */ + .long UART1_Handler /* 16+ 3: UART 1 Handler */ + .long UART2_Handler /* 16+ 4: UART 2 Handler */ + .long I2C0_Handler /* 16+ 5: I2C 0 Handler */ + .long I2C1_Handler /* 16+ 6: I2C 1 Handler */ + .long PORT0_Handler /* 16+ 7: GPIO Port 0 Combined Handler */ + .long PORT1_Handler /* 16+ 8: GPIO Port 1 Combined Handler */ + .long PORT2_Handler /* 16+ 9: GPIO Port 2 Combined Handler */ + .long PORT3_Handler /* 16+10: GPIO Port 3 Combined Handler */ + .long DMA_Handler /* 16+11: DMA Combined Handler */ + .long DUALTIMER0_Handler /* 16+12: Dual timer 0 handler */ + .long DUALTIMER1_Handler /* 16+ 13: Dual timer 1 Handler */ + .long PWM0_Handler /* 16+ 14: PWM0 Handler */ + .long PWM1_Handler /* 16+ 15: PWM1 Handler */ + .long PWM2_Handler /* 16+ 16: PWM2 Handler */ + .long PWM3_Handler /* 16+ 17: PWM3 Handler */ + .long PWM4_Handler /* 16+ 18: PWM4 Handler */ + .long PWM5_Handler /* 16+ 19: PWM5 Handler */ + .long PWM6_Handler /* 16+ 20: PWM6 Handler */ + .long PWM7_Handler /* 16+ 21: PWM7 Handler */ + .long RTC_Handler /* 16+ 22: RTC Handler */ + .long ADC_Handler /* 16+ 23: ADC Handler */ + .long WZTOE_Handler /* 16+ 24: WZTOE Handler */ + .long EXTI_Handler /* 16+ 25: EXTI Handler */ + + .size __isr_vector, . - __isr_vector +/* Reset Handler */ + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + subs r2, r1 + ble .LC3 + + movs r0, 0 +.LC2: + str r0, [r1, r2] + subs r2, 4 + bge .LC2 +.LC3: +#endif /* __STARTUP_CLEAR_BSS */ + + /*bl _start*/ + bl main + + .pool + .size Reset_Handler, . - Reset_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + +/* System Exception Handlers */ + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + +/* IRQ Handlers */ + + def_default_handler SSP0_Handler + def_default_handler SSP1_Handler + def_default_handler UART0_Handler + def_default_handler UART1_Handler + def_default_handler UART2_Handler + def_default_handler I2C0_Handler + def_default_handler I2C1_Handler + def_default_handler PORT0_Handler + def_default_handler PORT1_Handler + def_default_handler PORT2_Handler + def_default_handler PORT3_Handler + + def_default_handler DMA_Handler + def_default_handler DUALTIMER0_Handler + def_default_handler DUALTIMER1_Handler + def_default_handler PWM0_Handler + def_default_handler PWM1_Handler + def_default_handler PWM2_Handler + def_default_handler PWM3_Handler + def_default_handler PWM4_Handler + def_default_handler PWM5_Handler + def_default_handler PWM6_Handler + def_default_handler PWM7_Handler + def_default_handler RTC_Handler + def_default_handler ADC_Handler + def_default_handler WZTOE_Handler + def_default_handler EXTI_Handler + + /* + def_default_handler Default_Handler + .weak DEF_IRQHandler + .set DEF_IRQHandler, Default_Handler + */ + + .end + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/W7500x.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/W7500x.h new file mode 100644 index 0000000000..ff519c60ce --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/W7500x.h @@ -0,0 +1,1148 @@ +/**************************************************************************//** + * @file W7500x.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for + * Device W7500x + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2010-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef W7500x_H +#define W7500x_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup W7500x_Definitions W7500x Definitions + This file defines all structures and symbols for W7500x: + - registers and bitfields + - peripheral base address + - peripheral ID + - Peripheral definitions + @{ +*/ + + +/******************************************************************************/ +/* Processor and Core Peripherals */ +/******************************************************************************/ +/** @addtogroup W7500x_CMSIS Device CMSIS Definitions + Configuration of the Cortex-M0 Processor and Core Peripherals + @{ +*/ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers **************************************************/ + +/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ +/****** W7500x Specific Interrupt Numbers *********************************************************/ + SSP0_IRQn = 0, /*!< SSP 0 Interrupt */ + SSP1_IRQn = 1, /*!< SSP 1 Interrupt */ + UART0_IRQn = 2, /*!< UART 0 Interrupt */ + UART1_IRQn = 3, /*!< UART 1 Interrupt */ + UART2_IRQn = 4, /*!< UART 2 Interrupt */ + I2C0_IRQn = 5, /*!< I2C 0 Interrupt */ + I2C1_IRQn = 6, /*!< I2C 1 Interrupt */ + PORT0_IRQn = 7, /*!< Port 1 combined Interrupt */ + PORT1_IRQn = 8, /*!< Port 2 combined Interrupt */ + PORT2_IRQn = 9, /*!< Port 2 combined Interrupt */ + PORT3_IRQn = 10, /*!< Port 2 combined Interrupt */ + DMA_IRQn = 11, /*!< DMA combined Interrupt */ + DUALTIMER0_IRQn = 12, /*!< Dual Timer 0 Interrupt */ + DUALTIMER1_IRQn = 13, /*!< Dual Timer 1 Interrupt */ + PWM0_IRQn = 14, /*!< PWM 0 Interrupt */ + PWM1_IRQn = 15, /*!< PWM 1 Interrupt */ + PWM2_IRQn = 16, /*!< PWM 2 Interrupt */ + PWM3_IRQn = 17, /*!< PWM 3 Interrupt */ + PWM4_IRQn = 18, /*!< PWM 4 Interrupt */ + PWM5_IRQn = 19, /*!< PWM 5 Interrupt */ + PWM6_IRQn = 20, /*!< PWM 6 Interrupt */ + PWM7_IRQn = 21, /*!< PWM 7 Interrupt */ + RTC_IRQn = 22, /*!< RTC Interrupt */ + ADC_IRQn = 23, /*!< ADC Interrupt */ + WZTOE_IRQn = 24, /*!< WZTOE Interrupt */ + EXTI_IRQn = 25 /*!< EXTI Interrupt */ +} IRQn_Type; + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M0 Processor and Core Peripherals */ +#define __CM0_REV 0x0000 /*!< Core Revision r0p0 */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ + +/*@}*/ /* end of group W7500x_CMSIS */ + + +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#include "system_W7500x.h" /* W7500x System include file */ + + +/** @addtogroup Exported_types + * @{ + */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + + + + + +/** + * @} + */ + + + + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Clock Reset Generator + */ +typedef struct +{ + __IO uint32_t OSC_PDR; /*!< Oscillator power down register, Address offset : 0x00 */ + uint32_t RESERVED0[3]; + __IO uint32_t PLL_PDR; /*!< PLL power down register, Address offset : 0x10 */ + __IO uint32_t PLL_FCR; /*!< PLL frequency calculating register, Address offset : 0x14 */ + __IO uint32_t PLL_OER; /*!< PLL output enable register, Address offset : 0x18 */ + __IO uint32_t PLL_BPR; /*!< PLL bypass register, Address offset : 0x1c */ + __IO uint32_t PLL_IFSR; /*!< PLL input frequency select register, Address offset : 0x20 */ + uint32_t RESERVED1[3]; + __IO uint32_t FCLK_SSR; /*!< FCLK source select register, Address offset : 0x30 */ + __IO uint32_t FCLK_PVSR; /*!< FCLK prescale value select register, Address offset : 0x34 */ + uint32_t RESERVED2[2]; + __IO uint32_t SSPCLK_SSR; /*!< SSPCLK source select register, Address offset : 0x40 */ + __IO uint32_t SSPCLK_PVSR; /*!< SSPCLK prescale value select register, Address offset : 0x44 */ + uint32_t RESERVED3[6]; + __IO uint32_t ADCCLK_SSR; /*!< ADCCLK source select register, Address offset : 0x60 */ + __IO uint32_t ADCCLK_PVSR; /*!< ADCCLK prescale value select register, Address offset : 0x64 */ + uint32_t RESERVED4[2]; + __IO uint32_t TIMER0CLK_SSR; /*!< TIMER0CLK source select register, Address offset : 0x70 */ + __IO uint32_t TIMER0CLK_PVSR; /*!< TIMER0CLK prescale value select register, Address offset : 0x74 */ + uint32_t RESERVED5[2]; + __IO uint32_t TIMER1CLK_SSR; /*!< TIMER1CLK source select register, Address offset : 0x80 */ + __IO uint32_t TIMER1CLK_PVSR; /*!< TIMER1CLK prescale value select register, Address offset : 0x84 */ + uint32_t RESERVED6[10]; + __IO uint32_t PWM0CLK_SSR; /*!< PWM0CLK source select register, Address offset : 0xb0 */ + __IO uint32_t PWM0CLK_PVSR; /*!< PWM0CLK prescale value select register, Address offset : 0xb4 */ + uint32_t RESERVED7[2]; + __IO uint32_t PWM1CLK_SSR; /*!< PWM1CLK source select register, Address offset : 0xc0 */ + __IO uint32_t PWM1CLK_PVSR; /*!< PWM1CLK prescale value select register, Address offset : 0xc4 */ + uint32_t RESERVED8[2]; + __IO uint32_t PWM2CLK_SSR; /*!< PWM2CLK source select register, Address offset : 0xd0 */ + __IO uint32_t PWM2CLK_PVSR; /*!< PWM2CLK prescale value select register, Address offset : 0xd4 */ + uint32_t RESERVED9[2]; + __IO uint32_t PWM3CLK_SSR; /*!< PWM3CLK source select register, Address offset : 0xe0 */ + __IO uint32_t PWM3CLK_PVSR; /*!< PWM3CLK prescale value select register, Address offset : 0xe4 */ + uint32_t RESERVED10[2]; + __IO uint32_t PWM4CLK_SSR; /*!< PWM4CLK source select register, Address offset : 0xf0 */ + __IO uint32_t PWM4CLK_PVSR; /*!< PWM4CLK prescale value select register, Address offset : 0xf4 */ + uint32_t RESERVED11[2]; + __IO uint32_t PWM5CLK_SSR; /*!< PWM5CLK source select register, Address offset : 0x100 */ + __IO uint32_t PWM5LK_PVSR; /*!< PWM5CLK prescale value select register, Address offset : 0x104 */ + uint32_t RESERVED12[2]; + __IO uint32_t PWM6CLK_SSR; /*!< PWM6CLK source select register, Address offset : 0x110 */ + __IO uint32_t PWM6CLK_PVSR; /*!< PWM6CLK prescale value select register, Address offset : 0x114 */ + uint32_t RESERVED13[2]; + __IO uint32_t PWM7CLK_SSR; /*!< PWM7CLK source select register, Address offset : 0x120 */ + __IO uint32_t PWM7CLK_PVSR; /*!< PWM7CLK prescale value select register, Address offset : 0x124 */ + uint32_t RESERVED14[2]; + __IO uint32_t RTC_HS_SSR; /*!< RTC High Speed source select register, Address offset : 0x130 */ + __IO uint32_t RTC_HS_PVSR; /*!< RTC High Speed prescale value select register, Address offset : 0x134 */ + uint32_t RESERVED15; + __IO uint32_t RTC_SSR; /*!< RTC source select register, Address offset : 0x13c */ + + __IO uint32_t WDOGCLK_HS_SSR; /*!< WDOGCLK High Speed source select register, Address offset : 0x140 */ + __IO uint32_t WDOGCLK_HS_PVSR; /*!< WDOGCLK High Speed prescale value select register, Address offset : 0x144 */ + uint32_t RESERVED16; + __IO uint32_t WDOGCLK_SSR; /*!< WDOGCLK source select register, Address offset : 0x14c */ + + __IO uint32_t UARTCLK_SSR; /*!< UARTCLK source select register, Address offset : 0x150 */ + __IO uint32_t UARTCLK_PVSR; /*!< UARTCLK prescale value select register, Address offset : 0x154 */ + uint32_t RESERVED17[2]; + __IO uint32_t MIICLK_ECR; /*!< MII clock enable control register, Address offset : 0x160 */ + uint32_t RESERVED18[3]; + __IO uint32_t MONCLK_SSR; /*!< Monitoring clock source select I found Treasure was IoT Base Station in March.register, Address offset : 0x170 */ +}CRG_TypeDef; + + +/** + * @brief UART + */ +typedef struct +{ + __IO uint32_t DR; /*!< Data, Address offset : 0x00 */ + union { + __I uint32_t RSR; /*!< Receive Status, Address offset : 0x04 */ + __O uint32_t ECR; /*!< Error Clear, Address offset : 0x04 */ + } STATUS; + uint32_t RESERVED0[4]; + __IO uint32_t FR; /*!< Flags, Address offset : 0x18 */ + uint32_t RESERVED1; + __IO uint32_t ILPR; /*!< IrDA Low-power Counter, Address offset : 0x20 */ + __IO uint32_t IBRD; /*!< Integer Baud Rate, Address offset : 0x24 */ + __IO uint32_t FBRD; /*!< Fractional Baud Rate, Address offset : 0x28 */ + __IO uint32_t LCR_H; /*!< Line Control, Address offset : 0x2C */ + __IO uint32_t CR; /*!< Control, Address offset : 0x30 */ + __IO uint32_t IFLS; /*!< Interrupt FIFO Level Select, Address offset : 0x34 */ + __IO uint32_t IMSC; /*!< Interrupt Mask Set / Clear, Address offset : 0x38 */ + __IO uint32_t RIS; /*!< Raw Interrupt Status , Address offset : 0x3C */ + __IO uint32_t MIS; /*!< Masked Interrupt Status , Address offset : 0x40 */ + __O uint32_t ICR; /*!< Interrupt Clear, Address offset : 0x44 */ + __IO uint32_t DMACR; /*!< DMA Control, Address offset : 0x48 */ +} UART_TypeDef; + + +/** + * @brief Simple UART + */ +typedef struct +{ + __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */ + __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */ + __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */ + union { + __I uint32_t STATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */ + __O uint32_t CLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */ + }INT; + __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */ + +} S_UART_TypeDef; + +/** + * @brief Analog Digital Converter + */ + +typedef struct +{ + __IO uint32_t ADC_CTR; /* ADC control register, Address offset : 0x000 */ + __IO uint32_t ADC_CHSEL; /* ADC channel select register, Address offset : 0x004 */ + __IO uint32_t ADC_START; /* ADC start register, Address offset : 0x008 */ + __I uint32_t ADC_DATA; /* ADC conversion data register, Address offset : 0x00c */ + __IO uint32_t ADC_INT; /* ADC interrupt register, Address offset : 0x010 */ + uint32_t RESERVED0[2]; + __IO uint32_t ADC_INTCLR; /* ADC interrupt clear register, Address offset : 0x01c */ +}ADC_TypeDef; + +/** + * @brief dualtimer + */ +typedef struct +{ + __IO uint32_t TimerLoad; // Timer Load + __I uint32_t TimerValue; // Timer Counter Current Value + __IO uint32_t TimerControl; // Timer Control + // TimerEn: Timer Enable + // TimerMode: Timer Mode + // <0=> Freerunning-mode + // <1=> Periodic mode + // IntEnable: Interrupt Enable + // TimerPre: Timer Prescale + // <0=> / 1 + // <1=> / 16 + // <2=> / 256 + // <3=> Undefined! + // TimerSize: Timer Size + // <0=> 16-bit counter + // <1=> 32-bit counter + // OneShot: One-shoot mode + // <0=> Wrapping mode + // <1=> One-shot mode + // + __O uint32_t TimerIntClr; // Timer Interrupt Clear + __I uint32_t TimerRIS; // Timer Raw Interrupt Status + __I uint32_t TimerMIS; // Timer Masked Interrupt Status + __IO uint32_t TimerBGLoad; // Background Load Register +} DUALTIMER_TypeDef; + +/** + * @brief GPIO + */ +typedef struct +{ + __IO uint32_t DATA; /* DATA Register (R/W), offset : 0x000 */ + __IO uint32_t DATAOUT; /* Data Output Latch Register (R/W), offset : 0x004 */ + uint32_t RESERVED0[2]; + __IO uint32_t OUTENSET; /* Output Enable Set Register (R/W) offset : 0x010 */ + __IO uint32_t OUTENCLR; /* Output Enable Clear Register (R/W) offset : 0x014 */ + __IO uint32_t RESERVED1; /* Alternate Function Set Register (R/W) offset : 0x018 */ + __IO uint32_t RESERVED2; /* Alternate Function Clear Register (R/W) offset : 0x01C */ + __IO uint32_t INTENSET; /* Interrupt Enable Set Register (R/W) offset : 0x020 */ + __IO uint32_t INTENCLR; /* Interrupt Enable Clear Register (R/W) offset : 0x024 */ + __IO uint32_t INTTYPESET; /* Interrupt Type Set Register (R/W) offset : 0x028 */ + __IO uint32_t INTTYPECLR; /* Interrupt Type Clear Register (R/W) offset : 0x02C */ + __IO uint32_t INTPOLSET; /* Interrupt Polarity Set Register (R/W) offset : 0x030 */ + __IO uint32_t INTPOLCLR; /* Interrupt Polarity Clear Register (R/W) offset : 0x034 */ + union { + __I uint32_t INTSTATUS; /* Interrupt Status Register (R/ ) offset : 0x038 */ + __O uint32_t INTCLEAR; /* Interrupt Clear Register ( /W) offset : 0x038 */ + }Interrupt; + uint32_t RESERVED3[241]; + __IO uint32_t LB_MASKED[256]; /* Lower byte Masked Access Register (R/W) offset : 0x400 - 0x7FC */ + __IO uint32_t UB_MASKED[256]; /* Upper byte Masked Access Register (R/W) offset : 0x800 - 0xBFC */ +} GPIO_TypeDef; + +typedef struct +{ + __IO uint32_t Port[16]; /* Port_00, offset : 0x00 */ + /* Port_01, offset : 0x04 */ + /* Port_02, offset : 0x08 */ + /* Port_03, offset : 0x0C */ + /* Port_04, offset : 0x10 */ + /* Port_05, offset : 0x14 */ + /* Port_06, offset : 0x18 */ + /* Port_07, offset : 0x1C */ + /* Port_08, offset : 0x20 */ + /* Port_09, offset : 0x24 */ + /* Port_10, offset : 0x28 */ + /* Port_11, offset : 0x2C */ + /* Port_12, offset : 0x30 */ + /* Port_13, offset : 0x34 */ + /* Port_14, offset : 0x38 */ + /* Port_15, offset : 0x3C */ +} P_Port_Def; + +typedef struct +{ + __IO uint32_t Port[5]; /* Port_00, offset : 0x00 */ + /* Port_01, offset : 0x04 */ + /* Port_02, offset : 0x08 */ + /* Port_03, offset : 0x0C */ + /* Port_04, offset : 0x10 */ +} P_Port_D_Def; + +/** + * @brief I2C Register structure definition + */ +typedef struct +{ + __IO uint32_t PRER; //0x00 + __IO uint32_t CTR; //0x04 + __IO uint32_t CMDR; //0x08 + __I uint32_t SR; //0x0C + __IO uint32_t TSR; //0x10 + __IO uint32_t SADDR; //0x14 + __IO uint32_t TXR; //0x18 + __I uint32_t RXR; //0x1C + __I uint32_t ISR; //0x20 + __IO uint32_t ISCR; //0x24 + __IO uint32_t ISMR; //0x28 +}I2C_TypeDef; + +/** + * @brief PWM Register structure definition + */ +typedef struct +{ + __IO uint32_t IER; //Interrupt enable register + // <7> IE7 : Channel 7 interrupt enable + // <6> IE6 : Channel 6 interrupt enable + // <5> IE5 : Channel 5 interrupt enable + // <4> IE4 : Channel 4 interrupt enable + // <3> IE3 : Channel 3 interrupt enable + // <2> IE2 : Channel 2 interrupt enable + // <1> IE1 : Channel 1 interrupt enable + // <0> IE0 : Channel 0 interrupt enable + + __IO uint32_t SSR; //Start Stop register + // <7> SS7 : Channel 7 TC start or stop + // <6> SS6 : Channel 6 TC start or stop + // <5> SS5 : Channel 5 TC start or stop + // <4> SS4 : Channel 4 TC start or stop + // <3> SS3 : Channel 3 TC start or stop + // <2> SS2 : Channel 2 TC start or stop + // <1> SS1 : Channel 1 TC start or stop + // <0> SS0 : Channel 0 TC start or stop + + __IO uint32_t PSR; //Pause register + // <7> PS7 : Channel 7 TC pasue + // <6> PS6 : Channel 6 TC pasue + // <5> PS5 : Channel 5 TC pasue + // <4> PS4 : Channel 4 TC pasue + // <3> PS3 : Channel 3 TC pasue + // <2> PS2 : Channel 2 TC pasue + // <1> PS1 : Channel 1 TC pasue + // <0> PS0 : Channel 0 TC pasue +} PWM_TypeDef; + +typedef struct +{ + __I uint32_t IR; //Interrupt register + // <2> CI : Capture interrupt + // <1> OI : Overflow interrupt + // <0> MI : Match interrupt + + __IO uint32_t IER; //Interrupt enable register + // <2> CIE : Capture interrupt enable + // <1> OIE : Overflow interrupt enable + // <0> MIE : Match interrupt enable + + __O uint32_t ICR; //Interrupt clear register + // <2> CIC : Capture interrupt clear + // <1> OIC : Overflow interrupt clear + // <0> MIC : Match interrupt clear + + __I uint32_t TCR; //Timer/Counter register + // <0..31> TCR : Timer/Counter register + + __I uint32_t PCR; //Prescale counter register + // <0..5> PCR : Prescale Counter register + + __IO uint32_t PR; //Prescale register + // <0..5> PR : prescale register + + __IO uint32_t MR; //Match register + // <0..31> MR : Match register + + __IO uint32_t LR; //Limit register + // <0..31> LR : Limit register + __IO uint32_t UDMR; //Up-Down mode register + // <0> UDM : Up-down mode + + __IO uint32_t TCMR; //Timer/Counter mode register + // <0> TCM : Timer/Counter mode + + __IO uint32_t PEEER; //PWM output enable and external input enable register + // <0..1> PEEE : PWM output enable and external input enable + + __IO uint32_t CMR; //Capture mode register + // <0> CM : Capture mode + + __IO uint32_t CR; //Capture register + // <0..31> CR : Capture register + + __IO uint32_t PDMR; //Periodic mode register + // <0> PDM : Periodic mode + + __IO uint32_t DZER; //Dead-zone enable register + // <0> DZE : Dead-zone enable + + __IO uint32_t DZCR; //Dead-zone counter register + // <0..9> DZC : Dead-zone counter +} PWM_CHn_TypeDef; + +typedef struct +{ + __IO uint32_t PWM_CHn_PR; //Prescale register + // <0..5> PR : prescale register + __IO uint32_t PWM_CHn_MR; //Match register + // <0..31> MR : Match register + __IO uint32_t PWM_CHn_LR; //Limit register + // <0..31> LR : Limit register + __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register + // <0> UDM : Up-down mode + __IO uint32_t PWM_CHn_PDMR; //Periodic mode register + // <0> PDM : Periodic mode +}PWM_TimerModeInitTypeDef; + +typedef struct +{ + __IO uint32_t PWM_CHn_PR; //Prescale register + // <0..5> PR : prescale register + __IO uint32_t PWM_CHn_MR; //Match register + // <0..31> MR : Match register + __IO uint32_t PWM_CHn_LR; //Limit register + // <0..31> LR : Limit register + __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register + // <0> UDM : Up-down mode + __IO uint32_t PWM_CHn_PDMR; //Periodic mode register + // <0> PDM : Peiodic mode + __IO uint32_t PWM_CHn_CMR; //Capture mode register + // <0> CM : Capture mode +}PWM_CaptureModeInitTypeDef; + +typedef struct +{ + __IO uint32_t PWM_CHn_MR; + __IO uint32_t PWM_CHn_LR; + __IO uint32_t PWM_CHn_UDMR; + __IO uint32_t PWM_CHn_PDMR; + __IO uint32_t PWM_CHn_TCMR; +}PWM_CounterModeInitTypeDef; + + +/** + * @brief Random Number generator + */ +typedef struct +{ + __IO uint32_t RNG_RUN; /* RNG run register, Address offset : 0x000 */ + __IO uint32_t RNG_SEED; /* RNG seed value register, Address offset : 0x004 */ + __IO uint32_t RNG_CLKSEL; /* RNG Clock source select register, Address offset : 0x008 */ + __IO uint32_t RNG_MODE; /* RNG MODE select register, Address offset : 0x00c */ + __I uint32_t RNG_RN; /* RNG random number value register, Address offset : 0x010 */ + __IO uint32_t RNG_POLY; /* RNG polynomial register, Address offset : 0x014 */ +}RNG_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR0; + __IO uint32_t CR1; + __IO uint32_t DR; + __IO uint32_t SR; + __IO uint32_t CPSR; + __IO uint32_t IMSC; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t ICR; + __IO uint32_t DMACR; +} SSP_TypeDef; + +typedef struct +{ + __IO uint32_t WatchdogLoad; // Watchdog Load Register + __I uint32_t WatchdogValue; // Watchdog Value Register + __IO uint32_t WatchdogControl; // Watchdog Control Register + // RESEN: Reset enable + // INTEN: Interrupt enable + // + __O uint32_t WatchdogIntClr; // Watchdog Clear Interrupt Register + __I uint32_t WatchdogRIS; // Watchdog Raw Interrupt Status Register + __I uint32_t WatchdogMIS; // Watchdog Interrupt Status Register + uint32_t RESERVED[762]; + __IO uint32_t WatchdogLock; // Watchdog Lock Register +}WATCHDOG_TypeDef; + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +/* Peripheral and SRAM base address */ +#define W7500x_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */ +#define W7500x_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */ +#define W7500x_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */ + +#define W7500x_RAM_BASE (0x20000000UL) +#define W7500x_APB1_BASE (0x40000000UL) +#define W7500x_APB2_BASE (0x41000000UL) +#define W7500x_AHB_BASE (0x42000000UL) + +#define W7500x_UART0_BASE (W7500x_APB1_BASE + 0x0000C000UL) +#define W7500x_UART1_BASE (W7500x_APB1_BASE + 0x0000D000UL) +#define W7500x_UART2_BASE (W7500x_APB1_BASE + 0x00006000UL) + +#define W7500x_CRG_BASE (W7500x_APB2_BASE + 0x00001000UL) +#define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL) + +#define W7500x_INFO_BGT (0x0003FDB8) +#define W7500x_INFO_OSC (0x0003FDBC) + +#define W7500x_TRIM_BGT (0x41001210) +#define W7500x_TRIM_OSC (0x41001004) + +#define W7500x_DUALTIMER0_BASE (W7500x_APB1_BASE + 0x00001000ul) +#define W7500x_DUALTIMER1_BASE (W7500x_APB1_BASE + 0x00002000ul) + +#define EXTI_Px_BASE (W7500x_APB2_BASE + 0x00002200UL) + +#define GPIOA_BASE (W7500x_AHB_BASE + 0x00000000UL) // W7500x_AHB_BASE : 0x42000000UL +#define GPIOB_BASE (W7500x_AHB_BASE + 0x01000000UL) +#define GPIOC_BASE (W7500x_AHB_BASE + 0x02000000UL) +#define GPIOD_BASE (W7500x_AHB_BASE + 0x03000000UL) + +#define P_AFSR_BASE (W7500x_APB2_BASE + 0x00002000UL) + +#define P_PCR_BASE (W7500x_APB2_BASE + 0x00003000UL) + +#define I2C0_BASE (W7500x_APB1_BASE + 0x8000) +#define I2C1_BASE (W7500x_APB1_BASE + 0x9000) + +#define W7500x_PWM_BASE (W7500x_APB1_BASE + 0x00005000UL) + +#define W7500x_RNG_BASE (W7500x_APB1_BASE + 0x00007000UL) + +#define SSP0_BASE (0x4000A000) +#define SSP1_BASE (0x4000B000) + +#define W7500x_WATCHDOG_BASE (W7500x_APB1_BASE + 0x0000UL) + +/** + * @} + */ + + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define CRG ((CRG_TypeDef *) W7500x_CRG_BASE) + +#define UART0 ((UART_TypeDef *) W7500x_UART0_BASE) +#define UART1 ((UART_TypeDef *) W7500x_UART1_BASE) +#define UART2 ((S_UART_TypeDef *) W7500x_UART2_BASE) + +#define ADC ((ADC_TypeDef *) W7500x_ADC_BASE) + +#define DUALTIMER0_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE) ) +#define DUALTIMER0_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE + 0x20ul)) +#define DUALTIMER1_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE) ) +#define DUALTIMER1_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE + 0x20ul)) + +#define EXTI_PA ((P_Port_Def *) (EXTI_Px_BASE + 0x00000000UL)) /* PA_XX External interrupt Enable Register */ +#define EXTI_PB ((P_Port_Def *) (EXTI_Px_BASE + 0x00000040UL)) /* PB_XX External interrupt Enable Register */ +#define EXTI_PC ((P_Port_Def *) (EXTI_Px_BASE + 0x00000080UL)) /* PC_XX External interrupt Enable Register */ +#define EXTI_PD ((P_Port_D_Def *) (EXTI_Px_BASE + 0x000000C0UL)) /* PD_XX External interrupt Enable Register */ + +#define GPIOA ((GPIO_TypeDef *) (GPIOA_BASE) ) +#define GPIOB ((GPIO_TypeDef *) (GPIOB_BASE) ) +#define GPIOC ((GPIO_TypeDef *) (GPIOC_BASE) ) +#define GPIOD ((GPIO_TypeDef *) (GPIOD_BASE) ) + +#define PA_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000000UL)) /* PA_XX Pad Alternate Function Select Register */ +#define PB_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000040UL)) /* PB_XX Pad Alternate Function Select Register */ +#define PC_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000080UL)) /* PC_XX Pad Alternate Function Select Register */ +#define PD_AFSR ((P_Port_D_Def *) (P_AFSR_BASE + 0x000000C0UL)) /* PD_XX Pad Alternate Function Select Register */ + +#define PA_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000000UL)) /* PA_XX Pad Control Register */ +#define PB_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000040UL)) /* PB_XX Pad Control Register */ +#define PC_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000080UL)) /* PC_XX Pad Control Register */ +#define PD_PCR ((P_Port_D_Def *) (P_PCR_BASE + 0x000000C0UL)) /* PD_XX Pad Control Register */ + +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) + + +#define TIMCLKEN0_0 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0x80ul) +#define TIMCLKEN0_1 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0xA0ul) +#define TIMCLKEN1_0 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0x80ul) +#define TIMCLKEN1_1 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0xA0ul) + +#define PWM ((PWM_TypeDef *) (W7500x_PWM_BASE + 0x800UL )) +#define PWM_CH0 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE)) +#define PWM_CH1 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x100UL)) +#define PWM_CH2 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x200UL)) +#define PWM_CH3 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x300UL)) +#define PWM_CH4 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x400UL)) +#define PWM_CH5 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x500UL)) +#define PWM_CH6 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x600UL)) +#define PWM_CH7 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x700UL)) + +#define RNG ((RNG_TypeDef *) W7500x_RNG_BASE) + +#define SSP0 ((SSP_TypeDef*) (SSP0_BASE)) +#define SSP1 ((SSP_TypeDef*) (SSP1_BASE)) + +#define WATCHDOG ((WATCHDOG_TypeDef *) W7500x_WATCHDOG_BASE) + +/** + * @} + */ + + + +/******************************************************************************/ +/* */ +/* Clock Reset Generator */ +/* */ +/******************************************************************************/ +/**************** Bit definition for CRG_OSC_PDR **************************/ +#define CRG_OSC_PDR_NRMLOP (0x0ul) // Normal Operation +#define CRG_OSC_PDR_PD (0x1ul) // Power Down +/**************** Bit definition for CRG_PLL_PDR **************************/ +#define CRG_PLL_PDR_PD (0x0ul) // Power Down +#define CRG_PLL_PDR_NRMLOP (0x1ul) // Normal Operation +/**************** Bit definition for CRG_PLL_FCR **************************/ +//ToDo +/**************** Bit definition for CRG_PLL_OER **************************/ +#define CRG_PLL_OER_DIS (0x0ul) // Clock out is disable +#define CRG_PLL_OER_EN (0x1ul) // Clock out is enable +/**************** Bit definition for CRG_PLL_BPR **************************/ +#define CRG_PLL_BPR_DIS (0x0ul) // Bypass disable. Normal operation +#define CRG_PLL_BPR_EN (0x1ul) // Bypass enable. Clock will be set to external clock +/**************** Bit definition for CRG_PLL_IFSR **************************/ +#define CRG_PLL_IFSR_RCLK (0x0ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_PLL_IFSR_OCLK (0x1ul) // External oscillator clock (OCLK, 8MHz ~ 24MHz) +/**************** Bit definition for CRG_FCLK_SSR **************************/ +#define CRG_FCLK_SSR_MCLK (0x01ul) // 00,01 Output clock of PLL(MCLK) +#define CRG_FCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_FCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) +/**************** Bit definition for CRG_FCLK_PVSR **************************/ +#define CRG_FCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass) +#define CRG_FCLK_PVSR_DIV2 (0x01ul) // 1/2 +#define CRG_FCLK_PVSR_DIV4 (0x02ul) // 1/4 +#define CRG_FCLK_PVSR_DIV8 (0x03ul) // 1/8 +/**************** Bit definition for CRG_SSPCLK_SSR **************************/ +#define CRG_SSPCLK_SSR_DIS (0x00ul) // Disable clock +#define CRG_SSPCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK) +#define CRG_SSPCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_SSPCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) +/**************** Bit definition for CRG_SSPCLK_PVSR **************************/ +#define CRG_SSPCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass) +#define CRG_SSPCLK_PVSR_DIV2 (0x01ul) // 1/2 +#define CRG_SSPCLK_PVSR_DIV4 (0x02ul) // 1/4 +#define CRG_SSPCLK_PVSR_DIV8 (0x03ul) // 1/8 +/**************** Bit definition for CRG_ADCCLK_SSR **************************/ +#define CRG_ADCCLK_SSR_DIS (0x00ul) // Disable clock +#define CRG_ADCCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK) +#define CRG_ADCCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_ADCCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) +/**************** Bit definition for CRG_ADCCLK_PVSR **************************/ +#define CRG_ADCCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass) +#define CRG_ADCCLK_PVSR_DIV2 (0x01ul) // 1/2 +#define CRG_ADCCLK_PVSR_DIV4 (0x02ul) // 1/4 +#define CRG_ADCCLK_PVSR_DIV8 (0x03ul) // 1/8 +/**************** Bit definition for CRG_TIMER0/1CLK_SSR **************************/ +#define CRG_TIMERCLK_SSR_DIS (0x00ul) // Disable clock +#define CRG_TIMERCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK) +#define CRG_TIMERCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_TIMERCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) +/**************** Bit definition for CRG_TIMER0/1CLK_PVSR **************************/ +#define CRG_TIMERCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass) +#define CRG_TIMERCLK_PVSR_DIV2 (0x01ul) // 1/2 +#define CRG_TIMERCLK_PVSR_DIV4 (0x02ul) // 1/4 +#define CRG_TIMERCLK_PVSR_DIV8 (0x03ul) // 1/8 +#define CRG_TIMERCLK_PVSR_DIV16 (0x04ul) // 1/16 +#define CRG_TIMERCLK_PVSR_DIV32 (0x05ul) // 1/32 +#define CRG_TIMERCLK_PVSR_DIV64 (0x06ul) // 1/64 +#define CRG_TIMERCLK_PVSR_DIV128 (0x07ul) // 1/128 +/**************** Bit definition for CRG_PWMnCLK_SSR **************************/ +#define CRG_PWMCLK_SSR_DIS (0x00ul) // Disable clock +#define CRG_PWMCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK) +#define CRG_PWMCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_PWMCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) +/**************** Bit definition for CRG_PWMnCLK_PVSR **************************/ +#define CRG_PWMCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass) +#define CRG_PWMCLK_PVSR_DIV2 (0x01ul) // 1/2 +#define CRG_PWMCLK_PVSR_DIV4 (0x02ul) // 1/4 +#define CRG_PWMCLK_PVSR_DIV8 (0x03ul) // 1/8 +#define CRG_PWMCLK_PVSR_DIV16 (0x04ul) // 1/16 +#define CRG_PWMCLK_PVSR_DIV32 (0x05ul) // 1/32 +#define CRG_PWMCLK_PVSR_DIV64 (0x06ul) // 1/64 +#define CRG_PWMCLK_PVSR_DIV128 (0x07ul) // 1/128 +/**************** Bit definition for CRG_RTC_HS_SSR **************************/ +#define CRG_RTC_HS_SSR_DIS (0x00ul) // Disable clock +#define CRG_RTC_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK) +#define CRG_RTC_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_RTC_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) +/**************** Bit definition for CRG_RTC_HS_PVSR **************************/ +#define CRG_RTC_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass) +#define CRG_RTC_HS_PVSR_DIV2 (0x01ul) // 1/2 +#define CRG_RTC_HS_PVSR_DIV4 (0x02ul) // 1/4 +#define CRG_RTC_HS_PVSR_DIV8 (0x03ul) // 1/8 +#define CRG_RTC_HS_PVSR_DIV16 (0x04ul) // 1/16 +#define CRG_RTC_HS_PVSR_DIV32 (0x05ul) // 1/32 +#define CRG_RTC_HS_PVSR_DIV64 (0x06ul) // 1/64 +#define CRG_RTC_HS_PVSR_DIV128 (0x07ul) // 1/128 +/**************** Bit definition for CRG_RTC_SSR **************************/ +#define CRG_RTC_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock) +#define CRG_RTC_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock) +/**************** Bit definition for CRG_WDOGCLK_HS_SSR **************************/ +#define CRG_WDOGCLK_HS_SSR_DIS (0x00ul) // Disable clock +#define CRG_WDOGCLK_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK) +#define CRG_WDOGCLK_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_WDOGCLK_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) +/**************** Bit definition for CRG_WDOGCLK_HS_PVSR **************************/ +#define CRG_WDOGCLK_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass) +#define CRG_WDOGCLK_HS_PVSR_DIV2 (0x01ul) // 1/2 +#define CRG_WDOGCLK_HS_PVSR_DIV4 (0x02ul) // 1/4 +#define CRG_WDOGCLK_HS_PVSR_DIV8 (0x03ul) // 1/8 +#define CRG_WDOGCLK_HS_PVSR_DIV16 (0x04ul) // 1/16 +#define CRG_WDOGCLK_HS_PVSR_DIV32 (0x05ul) // 1/32 +#define CRG_WDOGCLK_HS_PVSR_DIV64 (0x06ul) // 1/64 +#define CRG_WDOGCLK_HS_PVSR_DIV128 (0x07ul) // 1/128 +/**************** Bit definition for CRG_WDOGCLK_SSR **************************/ +#define CRG_WDOGCLK_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock) +#define CRG_WDOGCLK_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock) +/**************** Bit definition for CRG_UARTCLK_SSR **************************/ +#define CRG_UARTCLK_SSR_DIS (0x00ul) // Disable clock +#define CRG_UARTCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK) +#define CRG_UARTCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_UARTCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) +/**************** Bit definition for CRG_UARTCLK_PVSR **************************/ +#define CRG_UARTCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass) +#define CRG_UARTCLK_PVSR_DIV2 (0x01ul) // 1/2 +#define CRG_UARTCLK_PVSR_DIV4 (0x02ul) // 1/4 +#define CRG_UARTCLK_PVSR_DIV8 (0x03ul) // 1/8 +/**************** Bit definition for CRG_MIICLK_ECR **************************/ +#define CRG_MIICLK_ECR_EN_RXCLK (0x01ul << 0) // Enable MII_RCK and MII_RCK_N +#define CRG_MIICLK_ECR_EN_TXCLK (0x01ul << 1) // Enable MII_TCK and MII_TCK_N +/**************** Bit definition for CRG_MONCLK_SSR **************************/ +#define CRG_MONCLK_SSR_MCLK (0x00ul) // PLL output clock (MCLK) +#define CRG_MONCLK_SSR_FCLK (0x01ul) // FCLK +#define CRG_MONCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK) +#define CRG_MONCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz) +#define CRG_MONCLK_SSR_ADCCLK (0x04ul) // ADCCLK +#define CRG_MONCLK_SSR_SSPCLK (0x05ul) // SSPCLK +#define CRG_MONCLK_SSR_TIMCLK0 (0x06ul) // TIMCLK0 +#define CRG_MONCLK_SSR_TIMCLK1 (0x07ul) // TIMCLK1 +#define CRG_MONCLK_SSR_PWMCLK0 (0x08ul) // PWMCLK0 +#define CRG_MONCLK_SSR_PWMCLK1 (0x09ul) // PWMCLK1 +#define CRG_MONCLK_SSR_PWMCLK2 (0x0Aul) // PWMCLK2 +#define CRG_MONCLK_SSR_PWMCLK3 (0x0Bul) // PWMCLK3 +#define CRG_MONCLK_SSR_PWMCLK4 (0x0Cul) // PWMCLK4 +#define CRG_MONCLK_SSR_PWMCLK5 (0x0Dul) // PWMCLK5 +#define CRG_MONCLK_SSR_PWMCLK6 (0x0Eul) // PWMCLK6 +#define CRG_MONCLK_SSR_PWMCLK7 (0x0Ful) // PWMCLK7 +#define CRG_MONCLK_SSR_UARTCLK (0x10ul) // UARTCLK +#define CRG_MONCLK_SSR_MII_RXCLK (0x11ul) // MII_RXCLK +#define CRG_MONCLK_SSR_MII_TXCLK (0x12ul) // MII_TXCLK +#define CRG_MONCLK_SSR_RTCCLK (0x13ul) // RTCCLK + +/******************************************************************************/ +/* */ +/* UART */ +/* */ +/******************************************************************************/ +/****************** Bit definition for UART Data(UARTDR) register *************************/ +#define UART_DR_OE (0x01ul << 11) // Overrun Error +#define UART_DR_BE (0x01ul << 10) // Break Error +#define UART_DR_PE (0x01ul << 9) // Parity Error +#define UART_DR_FE (0x01ul << 8) // Framing Error +//#define UART_DR_DR // ToDo +/***************** Bit definition for UART Receive Status(UARTRSR) register ***************/ +#define UARTR_SR_OE (0x01ul << 3) // Overrun Error +#define UARTR_SR_BE (0x01ul << 2) // Break Error +#define UARTR_SR_PE (0x01ul << 1) // Parity Error +#define UARTR_SR_FE (0x01ul << 0) // Framing Error +/***************** Bit definition for UART Error Clear(UARTECR) register ******************/ +#define UARTE_CR_OE (0x01ul << 3) // Overrun Error +#define UARTE_CR_BE (0x01ul << 2) // Break Error +#define UARTE_CR_PE (0x01ul << 1) // Parity Error +#define UARTE_CR_FE (0x01ul << 0) // Framing Error +/****************** Bit definition for UART Flags(UARTFR) register ************************/ +#define UART_FR_RI (0x01ul << 8) // Ring indicator +#define UART_FR_TXFE (0x01ul << 7) // Transmit FIFO empty +#define UART_FR_RXFF (0x01ul << 6) // Receive FIFO full +#define UART_FR_TXFF (0x01ul << 5) // Transmit FIFO full +#define UART_FR_RXFE (0x01ul << 4) // Receive FIFO empty +#define UART_FR_BUSY (0x01ul << 3) // UART busy +#define UART_FR_DCD (0x01ul << 2) // Data carrier detect +#define UART_FR_DSR (0x01ul << 1) // Data set ready +#define UART_FR_CTS (0x01ul << 0) // Clear to send +/********** Bit definition for UART Low-power Counter(UARTILPR) register *******************/ +#define UARTILPR_COUNTER (0xFFul << 0) // 8-bit low-power divisor value (0..255) +/********************* Bit definition for Line Control(UARTLCR_H) register *****************/ +#define UART_LCR_H_SPS (0x1ul << 7) // Stick parity select +#define UART_LCR_H_WLEN(n) ((n & 0x3ul) << 5) // Word length ( 0=5bits, 1=6bits, 2=7bits, 3=8bits ) +#define UART_LCR_H_FEN (0x1ul << 4) // Enable FIFOs +#define UART_LCR_H_STP2 (0x1ul << 3) // Two stop bits select +#define UART_LCR_H_EPS (0x1ul << 2) // Even parity select +#define UART_LCR_H_PEN (0x1ul << 1) // Parity enable +#define UART_LCR_H_BRK (0x1ul << 0) // Send break +/********************* Bit definition for Contro(UARTCR) register *************************/ +#define UART_CR_CTSEn (0x1ul << 15) // CTS hardware flow control enable +#define UART_CR_RTSEn (0x1ul << 14) // RTS hardware flow control enable +#define UART_CR_Out2 (0x1ul << 13) // Complement of Out2 modem status output +#define UART_CR_Out1 (0x1ul << 12) // Complement of Out1 modem status output +#define UART_CR_RTS (0x1ul << 11) // Request to send +#define UART_CR_DTR (0x1ul << 10) // Data transmit ready +#define UART_CR_RXE (0x1ul << 9) // Receive enable +#define UART_CR_TXE (0x1ul << 8) // Transmit enable +#define UART_CR_LBE (0x1ul << 7) // Loop-back enable +#define UART_CR_SIRLP (0x1ul << 2) // IrDA SIR low power mode +#define UART_CR_SIREN (0x1ul << 1) // SIR enable +#define UART_CR_UARTEN (0x1ul << 0) // UART enable +/******* Bit definition for Interrupt FIFO Level Select(UARTIFLS) register *****************/ +#define UART_IFLS_RXIFLSEL(n) ((n & 0x7ul) << 3) // Receive interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full) +#define UART_IFLS_TXIFLSEL(n) ((n & 0x7ul) << 0) // Transmit interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full) +/******* Bit definition for Interrupt Mask Set/Clear(UARTIMSC) register ********************/ +#define UART_IMSC_OEIM (0x1ul << 10) // Overrun error interrupt mask +#define UART_IMSC_BEIM (0x1ul << 9) // Break error interrupt mask +#define UART_IMSC_PEIM (0x1ul << 8) // Parity error interrupt mask +#define UART_IMSC_FEIM (0x1ul << 7) // Framing error interrupt mask +#define UART_IMSC_RTIM (0x1ul << 6) // Receive interrupt mask +#define UART_IMSC_TXIM (0x1ul << 5) // Transmit interrupt mask +#define UART_IMSC_RXIM (0x1ul << 4) // Receive interrupt mask +#define UART_IMSC_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt mask +#define UART_IMSC_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt mask +#define UART_IMSC_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt mask +#define UART_IMSC_RIMIM (0x1ul << 0) // nUARTRI modem interrupt mask +/*************** Bit definition for Raw Interrupt Status(UARTRIS) register *****************/ +#define UART_RIS_OEIM (0x1ul << 10) // Overrun error interrupt status +#define UART_RIS_BEIM (0x1ul << 9) // Break error interrupt status +#define UART_RIS_PEIM (0x1ul << 8) // Parity error interrupt status +#define UART_RIS_FEIM (0x1ul << 7) // Framing error interrupt status +#define UART_RIS_RTIM (0x1ul << 6) // Receive interrupt status +#define UART_RIS_TXIM (0x1ul << 5) // Transmit interrupt status +#define UART_RIS_RXIM (0x1ul << 4) // Receive interrupt status +#define UART_RIS_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt status +#define UART_RIS_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt status +#define UART_RIS_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt status +#define UART_RIS_RIMIM (0x1ul << 0) // nUARTRI modem interrupt status +/************** Bit definition for Masked Interrupt Status(UARTMIS) register ****************/ +#define UART_MIS_OEIM (0x1ul << 10) // Overrun error masked interrupt status +#define UART_MIS_BEIM (0x1ul << 9) // Break error masked interrupt status +#define UART_MIS_PEIM (0x1ul << 8) // Parity error masked interrupt status +#define UART_MIS_FEIM (0x1ul << 7) // Framing error masked interrupt status +#define UART_MIS_RTIM (0x1ul << 6) // Receive masked interrupt status +#define UART_MIS_TXIM (0x1ul << 5) // Transmit masked interrupt status +#define UART_MIS_RXIM (0x1ul << 4) // Receive masked interrupt status +#define UART_MIS_DSRMIM (0x1ul << 3) // nUARTDSR modem masked interrupt status +#define UART_MIS_DCDMIM (0x1ul << 2) // nUARTDCD modem masked interrupt status +#define UART_MIS_CTSMIM (0x1ul << 1) // nUARTCTS modem masked interrupt status +#define UART_MIS_RIMIM (0x1ul << 0) // nUARTRI modem masked interrupt status +/*************** Bit definition for Interrupt Clear(UARTICR) register ************************/ +#define UART_ICR_OEIM (0x1ul << 10) // Overrun error interrupt clear +#define UART_ICR_BEIM (0x1ul << 9) // Break error interrupt clear +#define UART_ICR_PEIM (0x1ul << 8) // Parity error interrupt clear +#define UART_ICR_FEIM (0x1ul << 7) // Framing error interrupt clear +#define UART_ICR_RTIM (0x1ul << 6) // Receive interrupt clear +#define UART_ICR_TXIM (0x1ul << 5) // Transmit interrupt clear +#define UART_ICR_RXIM (0x1ul << 4) // Receive interrupt clear +#define UART_ICR_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt clear +#define UART_ICR_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt clear +#define UART_ICR_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt clear +#define UART_ICR_RIMIM (0x1ul << 0) // nUARTRI modem interrupt clear +/***************** Bit definition for DMA Control(UARTDMACR) register ************************/ +#define UART_DMACR_DMAONERR (0x1ul << 2) // DMA on error +#define UART_DMACR_TXDMAE (0x1ul << 1) // Transmit DMA enable +#define UART_DMACR_RXDMAE (0x1ul << 0) // Receive DMA enable + +/******************************************************************************/ +/* */ +/* Simple UART */ +/* */ +/******************************************************************************/ +/***************** Bit definition for S_UART Data () register ************************/ +#define S_UART_DATA (0xFFul << 0) +/***************** Bit definition for S_UART State() register ************************/ +#define S_UART_STATE_TX_BUF_OVERRUN (0x01ul << 2) // TX buffer overrun, wirte 1 to clear. +#define S_UART_STATE_RX_BUF_FULL (0x01ul << 1) // RX buffer full, read only. +#define S_UART_STATE_TX_BUF_FULL (0x01ul << 0) // TX buffer full, read only. +/***************** Bit definition for S_UART Control() register ************************/ +#define S_UART_CTRL_HIGH_SPEED_TEST (0x01ul << 6) // High-speed test mode for TX only. +#define S_UART_CTRL_RX_OVERRUN_EN (0x01ul << 5) // RX overrun interrupt enable. +#define S_UART_CTRL_TX_OVERRUN_EN (0x01ul << 4) // TX overrun interrupt enable. +#define S_UART_CTRL_RX_INT_EN (0x01ul << 3) // RX interrupt enable. +#define S_UART_CTRL_TX_INT_EN (0x01ul << 2) // TX interrupt enable. +#define S_UART_CTRL_RX_EN (0x01ul << 1) // RX enable. +#define S_UART_CTRL_TX_EN (0x01ul << 0) // TX enable. +/***************** Bit definition for S_UART Interrupt() register ************************/ +#define S_UART_INT_RX_OVERRUN (0x01ul << 3) // RX overrun interrupt. Wirte 1 to clear +#define S_UART_INT_TX_OVERRUN (0x01ul << 2) // TX overrun interrupt. Write 1 to clear +#define S_UART_INT_RX (0x01ul << 1) // RX interrupt. Write 1 to clear +#define S_UART_INT_TX (0x01ul << 0) // TX interrupt. Write 1 to clear + +/******************************************************************************/ +/* */ +/* Analog Digital Register */ +/* */ +/******************************************************************************/ + +/*********************** Bit definition for ADC_CTR ***********************/ +//#define ADC_CTR_SAMSEL_ABNORMAL (0x0ul) // Abnormal Operation +//#define ADC_CTR_SAMSEL_NORMAL (0x1ul) // Normal Operation +#define ADC_CTR_PWD_NRMOP (0x1ul) // Active Operation +#define ADC_CTR_PWD_PD (0x3ul) // Power down +/*********************** Bit definition for ADC_CHSEL ***********************/ +#define ADC_CHSEL_CH0 (0x0ul) // Channel 0 +#define ADC_CHSEL_CH1 (0x1ul) // Channel 1 +#define ADC_CHSEL_CH2 (0x2ul) // Channel 2 +#define ADC_CHSEL_CH3 (0x3ul) // Channel 3 +#define ADC_CHSEL_CH4 (0x4ul) // Channel 4 +#define ADC_CHSEL_CH5 (0x5ul) // Channel 5 +#define ADC_CHSEL_CH6 (0x6ul) // Channel 6 +#define ADC_CHSEL_CH7 (0x7ul) // Channel 7 +#define ADC_CHSEL_CH15 (0xful) // LDO output(1.5V) +/*********************** Bit definition for ADC_START ***********************/ +#define ADC_START_START (0x1ul) // ADC conversion start +/*********************** Bit definition for ADC_DATA ***********************/ +//ToDo (Readonly) + +/*********************** Bit definition for ADC_INT ***********************/ +#define ADC_INT_MASK_DIS (0x0ul << 1) // Interrupt disable +#define ADC_INT_MASK_ENA (0x1ul << 1) // Interrupt enable +//ToDo (Readonly) + +/*********************** Bit definition for ADC_INTCLR ***********************/ +#define ADC_INTCLEAR (0x1ul) // ADC Interrupt clear + +#define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL) +#define ADC ((ADC_TypeDef *) W7500x_ADC_BASE) + +/******************************************************************************/ +/* */ +/* Dual Timer */ +/* */ +/******************************************************************************/ + +/*********************** Bit definition for dualtimer ***********************/ +#define DUALTIMER_TimerControl_TimerDIsable (0x0ul << 7) +#define DUALTIMER_TimerControl_TimerEnable (0x1ul << 7) +#define DUALTIMER_TimerControl_FreeRunning (0x0ul << 6) +#define DUALTIMER_TimerControl_Periodic (0x1ul << 6) +#define DUALTIMER_TimerControl_IntDisable (0x0ul << 5) +#define DUALTIMER_TimerControl_IntEnable (0x1ul << 5) +#define DUALTIMER_TimerControl_Pre_1 (0x0ul << 2) +#define DUALTIMER_TimerControl_Pre_16 (0x1ul << 2) +#define DUALTIMER_TimerControl_Pre_256 (0x2ul << 2) +#define DUALTIMER_TimerControl_Size_16 (0x0ul << 1) +#define DUALTIMER_TimerControl_Size_32 (0x1ul << 1) +#define DUALTIMER_TimerControl_Wrapping (0x0ul << 0) +#define DUALTIMER_TimerControl_OneShot (0x1ul << 0) + +/******************************************************************************/ +/* */ +/* External Interrupt */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for Px_IER **************************/ +#define EXTI_Px_INTPOR_RISING_EDGE (0x00ul << 0) +#define EXTI_Px_INTPOR_FALLING_EDGE (0x01ul << 0) +#define EXTI_Px_INTEN_DISABLE (0x00ul << 1) +#define EXTI_Px_INTEN_ENABLE (0x01ul << 1) + +/******************************************************************************/ +/* */ +/* GPIO */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for Px_AFSR **************************/ +#define Px_AFSR_AF0 (0x00ul) +#define Px_AFSR_AF1 (0x01ul) +#define Px_AFSR_AF2 (0x02ul) +#define Px_AFSR_AF3 (0x03ul) +/**************** Bit definition for Px_PCR **************************/ +#define Px_PCR_PUPD_DOWN (0x01ul << 0) // Pull Down +#define Px_PCR_PUPD_UP (0x01ul << 1) // Pull Up +#define Px_PCR_DS_HIGH (0x01ul << 2) // High Driving +#define Px_PCR_OD (0x01ul << 3) // Open Drain +#define Px_PCR_IE (0x01ul << 5) // Input Buffer Enable +#define Px_PCR_CS_SUMMIT (0x01ul << 6) // Use Summit Trigger Input Buffer + +/******************************************************************************/ +/* */ +/* I2C */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for I2C_CTR **************************/ +#define I2C_CTR_COREEN (0x01ul << 7 ) // 0x80 +#define I2C_CTR_INTEREN (0x01ul << 6 ) // 0x40 +#define I2C_CTR_MODE (0x01ul << 5 ) // 0x20 +#define I2C_CTR_ADDR10 (0x01ul << 4 ) // 0x10 +#define I2C_CTR_CTRRWN (0x01ul << 3 ) // 0x08 +#define I2C_CTR_CTEN (0x01ul << 2 ) // 0x04 + +/**************** Bit definition for I2C_CMDR **************************/ +#define I2C_CMDR_STA (0x01ul << 7 ) // 0x80 +#define I2C_CMDR_STO (0x01ul << 6 ) // 0x40 +#define I2C_CMDR_ACK (0x01ul << 5 ) // 0x20 +#define I2C_CMDR_RESTA (0x01ul << 4 ) // 0x10 + +/**************** Bit definition for I2C_ISCR **************************/ +#define I2C_ISCR_RST (0x01ul << 1) // 0x01 + +/**************** Bit definition for I2C_SR **************************/ +#define I2C_SR_TX (0x01ul << 9 ) // 0x200 +#define I2C_SR_RX (0x01ul << 8 ) // 0x100 +#define I2C_SR_ACKT (0x01ul << 7 ) // 0x080 +#define I2C_SR_BT (0x01ul << 6 ) // 0x040 +#define I2C_SR_SA (0x01ul << 5 ) // 0x020 +#define I2C_SR_SB (0x01ul << 4 ) // 0x010 +#define I2C_SR_AL (0x01ul << 3 ) // 0x008 +#define I2C_SR_TO (0x01ul << 2 ) // 0x004 +#define I2C_SR_SRW (0x01ul << 1 ) // 0x002 +#define I2C_SR_ACKR (0x01ul << 0 ) // 0x001 + +/**************** Bit definition for I2C_ISR **************************/ +#define I2C_ISR_STAE (0x01ul << 4 ) // 0x010 +#define I2C_ISR_STOE (0x01ul << 3 ) // 0x008 +#define I2C_ISR_TOE (0x01ul << 2 ) // 0x004 +#define I2C_ISR_ACK_RXE (0x01ul << 1 ) // 0x002 +#define I2C_ISR_ACK_TXE (0x01ul << 0 ) // 0x001 + +/**************** Bit definition for I2C_ISMR **************************/ +#define I2C_ISR_STAEM (0x01ul << 4 ) // 0x010 +#define I2C_ISR_STOEM (0x01ul << 3 ) // 0x008 +#define I2C_ISR_TOEM (0x01ul << 2 ) // 0x004 +#define I2C_ISR_ACK_RXEM (0x01ul << 1 ) // 0x002 +#define I2C_ISR_ACK_TXEM (0x01ul << 0 ) // 0x001 + +/******************************************************************************/ +/* */ +/* PWM */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Random number generator Register */ +/* */ +/******************************************************************************/ + +/*********************** Bit definition for RNG_RUN ***********************/ +#define RNG_RUN_STOP (0x0ul) // STOP RNG shift register +#define RNG_RUN_RUN (0x1ul) // RUN RNG shift register +/*********************** Bit definition for RNG_SEED ***********************/ +//ToDo + +/*********************** Bit definition for RNG_CLKSEL ***********************/ +#define RNG_CLKSEL_RNGCLK (0x0ul) // RNGCLK is source clock for rng shift register +#define RNG_CLKSEL_APBCLK (0x1ul) // APBCLK is source clock for rng shift register +/*********************** Bit definition for RNG_ENABLE ***********************/ +#define RNG_MANUAL_DISABLE (0x0ul) // RNG disble +#define RNG_MANUAL_ENABLE (0x1ul) // RNG enable +/*********************** Bit definition for RNG_RN ***********************/ +//ToDo + +/*********************** Bit definition for RNG_POLY ***********************/ +//ToDo + + + +#if !defined (USE_HAL_DRIVER) +#define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + + + +#if defined (USE_HAL_DRIVER) + #include "W7500x_conf.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* W7500x_H */ + + + +/************************ (C) COPYRIGHT Wiznet *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis.h new file mode 100644 index 0000000000..59a30a998a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "W7500x.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.c new file mode 100644 index 0000000000..71da98cf15 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.c @@ -0,0 +1,47 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash + + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS; + + vectors[IRQn + 16] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + // Return the vector + return vectors[IRQn + 16]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.h new file mode 100644 index 0000000000..3d1e0ed80f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.h @@ -0,0 +1,51 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS 41 +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.c b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.c new file mode 100644 index 0000000000..46193b12b0 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.c @@ -0,0 +1,104 @@ +/**************************************************************************//** + * @file system_CMSDK_CM0.c + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for + * Device CMSDK + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2010-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#include "system_W7500x.h" + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ +//#define SYSCLK_EXTERN_OSC + + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemFrequency = 0; /*!< System Clock Frequency (Core Clock) */ +uint32_t SystemCoreClock = 0; /*!< Processor Clock Frequency */ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + uint8_t M,N,OD; + +#ifdef SYSCLK_EXTERN_OSC + CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK; +#else + CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK; +#endif + OD = (1 << (CRG->PLL_FCR & 0x01)) * (1 << ((CRG->PLL_FCR & 0x02) >> 1)); + N = (CRG->PLL_FCR >> 8 ) & 0x3F; + M = (CRG->PLL_FCR >> 16) & 0x3F; + +#ifdef SYSCLK_EXTERN_OSC + SystemCoreClock = EXTERN_XTAL * M / N * 1 / OD; +#else + SystemCoreClock = INTERN_XTAL * M / N * 1 / OD; +#endif +} + +uint32_t GetSystemClock() +{ + return SystemCoreClock; +} + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + uint8_t M,N,OD; + + (*((volatile uint32_t *)(W7500x_TRIM_BGT))) = (*((volatile uint32_t *)(W7500x_INFO_BGT))); + (*((volatile uint32_t *)(W7500x_TRIM_OSC))) = (*((volatile uint32_t *)(W7500x_INFO_OSC))); + + + // Set PLL input frequency +#ifdef SYSCLK_EXTERN_OSC + CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK; +#else + CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK; +#endif + OD = (1 << (CRG->PLL_FCR & 0x01)) * (1 << ((CRG->PLL_FCR & 0x02) >> 1)); + N = (CRG->PLL_FCR >> 8 ) & 0x3F; + M = (CRG->PLL_FCR >> 16) & 0x3F; + +#ifdef SYSCLK_EXTERN_OSC + SystemCoreClock = EXTERN_XTAL * M / N * 1 / OD; +#else + SystemCoreClock = INTERN_XTAL * M / N * 1 / OD; +#endif +} diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.h new file mode 100644 index 0000000000..74af23d9d8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.h @@ -0,0 +1,84 @@ +/**************************************************************************//** + * @file system_W7500x.h + * @brief CMSIS Cortex-M# Device Peripheral Access Layer Header File for + * Device W7500x + * @version V3.10 + * @date 23. November 2012 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef SYSTEM_W7500x_H /* ToDo: replace '' with your device name */ +#define SYSTEM_W7500x_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "W7500x.h" + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t GetSystemClock(void); /*!< Get System Clock Frequency */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define EXTERN_XTAL (8000000UL) /* External Oscillator Frequency */ +#define INTERN_XTAL (8000000UL) /* Internal Oscillator Frequency */ + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_W7500x_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.c b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.c new file mode 100644 index 0000000000..cd473752b5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.c @@ -0,0 +1,54 @@ +#include "W7500x.h" + +void ADC_PowerDownEnable (FunctionalState NewState) +{ + if (NewState != DISABLE) ADC->ADC_CTR = ADC_CTR_PWD_PD; + else ADC->ADC_CTR = ADC_CTR_PWD_NRMOP; +} + +void ADC_ChannelSelect (ADC_CH num) +{ + assert_param(IS_ADC_CH_NUM(num)); + ADC->ADC_CHSEL = num; +} + +void ADC_Start (void) +{ + ADC->ADC_START = ADC_START_START; +} + +uint16_t ADC_ReadData (void) +{ + return ((uint16_t)ADC->ADC_DATA); +} + +void ADC_InterruptMask (FunctionalState NewState) +{ + if (NewState != DISABLE) ADC->ADC_INT = ADC_INT_MASK_ENA; + else ADC->ADC_INT = ADC_INT_MASK_DIS; +} + +uint8_t ADC_IsInterrupt (void) +{ + return (((uint8_t)ADC->ADC_INT && 0x01ul)); +} + +void ADC_InterruptClear (void) +{ + ADC->ADC_INT = ADC_INTCLEAR; +} + +void ADC_Init (void) +{ + // ADC_CLK on + ADC_PowerDownEnable(DISABLE); + //ADC_ChannelSelect(num); +} + +void ADC_DeInit (void) +{ + // ADC_CLK off + ADC_PowerDownEnable(ENABLE); + ADC_InterruptMask(DISABLE); +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.h new file mode 100644 index 0000000000..7985370e33 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.h @@ -0,0 +1,59 @@ +/** + ****************************************************************************** + * @file + * @author + * @version + * @date + * @brief This file contains all the functions prototypes for the ADC + * firmware library. + ****************************************************************************** + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __W7500X_ADC_H +#define __W7500X_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "W7500x.h" + +typedef enum { ADC_CH0 = 0, + ADC_CH1 = 1, + ADC_CH2 = 2, + ADC_CH3 = 3, + ADC_CH4 = 4, + ADC_CH5 = 5, + ADC_CH6 = 6, + ADC_CH7 = 7, + ADC_CH15 = 15} ADC_CH; + +#define IS_ADC_CH_NUM(NUM) (((NUM) == ADC_CH0) || \ + ((NUM) == ADC_CH1) || \ + ((NUM) == ADC_CH2) || \ + ((NUM) == ADC_CH3) || \ + ((NUM) == ADC_CH4) || \ + ((NUM) == ADC_CH5) || \ + ((NUM) == ADC_CH6) || \ + ((NUM) == ADC_CH7) || \ + ((NUM) == ADC_CH15)) + +void ADC_Init(void); +void ADC_DeInit(void); +void ADC_PowerDownEnable (FunctionalState NewState); +void ADC_ChannelSelect (ADC_CH num); +void ADC_Start (void); +uint16_t ADC_ReadData (void); +void ADC_InterruptMask (FunctionalState NewState); +uint8_t ADC_IsInterrupt (void); +void ADC_InterruptClear (void); + +#ifdef __cplusplus + } +#endif + +#endif //__W7500X_ADC_H diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_conf.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_conf.h new file mode 100644 index 0000000000..cbc6929c1a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_conf.h @@ -0,0 +1,15 @@ +#include "W7500x_gpio.h" +#include "W7500x_exti.h" +#include "W7500x_pwm.h" +#include "W7500x_uart.h" +#include "W7500x_i2c.h" +#include "W7500x_adc.h" +#include "system_W7500x.h" + + +#ifdef USE_FULL_ASSERT + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__,__LINE__)) +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.c b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.c new file mode 100644 index 0000000000..f533e1d2ba --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.c @@ -0,0 +1,276 @@ +#include "W7500x_crg.h" + +void CRG_DeInit(void) +{ +//To Do +} + +void CRG_OSC_PowerDownEnable(FunctionalState NewState) +{ + if(NewState != DISABLE) CRG->OSC_PDR = CRG_OSC_PDR_PD; + else CRG->OSC_PDR = CRG_OSC_PDR_NRMLOP; +} + +void CRG_PLL_PowerDownEnable(FunctionalState NewState) +{ + if(NewState != DISABLE) CRG->PLL_PDR = CRG_PLL_PDR_PD; + else CRG->PLL_PDR = CRG_PLL_PDR_NRMLOP; +} + +void CRG_PLL_OutputEnable(FunctionalState NewState) +{ + if(NewState != DISABLE) CRG->PLL_OER = CRG_PLL_OER_EN; + else CRG->PLL_OER = CRG_PLL_OER_DIS; +} + +void CRG_PLL_BypassEnable(FunctionalState NewState) +{ + if(NewState != DISABLE) CRG->PLL_BPR = CRG_PLL_BPR_EN; + else CRG->PLL_BPR = CRG_PLL_BPR_DIS; +} + +void CRG_PLL_InputFrequencySelect(CRG_CLK_SOURCE src) +{ + assert_param(IS_CRG_PLL_SRC(src)); + + if( src == CRG_RCLK ) CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK; + else CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK; +} + +void CRG_FCLK_SourceSelect(CRG_CLK_SOURCE src) +{ + assert_param(IS_CRG_FCLK_SRC(src)); + + if ( src == CRG_RCLK ) CRG->FCLK_SSR = CRG_FCLK_SSR_RCLK; + else if ( src == CRG_OCLK ) CRG->FCLK_SSR = CRG_FCLK_SSR_OCLK; + else CRG->FCLK_SSR = CRG_FCLK_SSR_MCLK; +} + +void CRG_FCLK_SetPrescale(CRG_PREDIV prediv) +{ + assert_param(IS_CRG_FCLK_PREDIV(prediv)); + + if ( prediv == CRG_PREDIV1 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV1; + else if ( prediv == CRG_PREDIV2 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV2; + else if ( prediv == CRG_PREDIV4 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV4; + else CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV8; +} + +void CRG_SSPCLK_SourceSelect(CRG_CLK_SOURCE src) +{ + assert_param(IS_CRG_SSPCLK_SRC(src)); + + if ( src == CRG_CLK_DIS ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_DIS; + else if ( src == CRG_MCLK ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK; + else if ( src == CRG_RCLK ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_RCLK; + else CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_OCLK; +} + +void CRG_SSPCLK_SetPrescale(CRG_PREDIV prediv) +{ + assert_param(IS_CRG_SSPCLK_PREDIV(prediv)); + + if ( prediv == CRG_PREDIV1 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1; + else if ( prediv == CRG_PREDIV2 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV2; + else if ( prediv == CRG_PREDIV4 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV4; + else CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV8; +} + +void CRG_ADCCLK_SourceSelect(CRG_CLK_SOURCE src) +{ + assert_param(IS_CRG_ADCCLK_SRC(src)); + + if ( src == CRG_CLK_DIS ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_DIS; + else if ( src == CRG_MCLK ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_MCLK; + else if ( src == CRG_RCLK ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_RCLK; + else CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_OCLK; +} + +void CRG_ADCCLK_SetPrescale(CRG_PREDIV prediv) +{ + assert_param(IS_CRG_ADCCLK_PREDIV(prediv)); + + if ( prediv == CRG_PREDIV1 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV1; + else if ( prediv == CRG_PREDIV2 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV2; + else if ( prediv == CRG_PREDIV4 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV4; + else CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV8; +} + +void CRG_TIMERCLK_SourceSelect(CRG_TIMER num, CRG_CLK_SOURCE src) +{ + assert_param(IS_CRG_TIMERCLK_NUM(num)); + assert_param(IS_CRG_TIMERCLK_SRC(src)); + + if ( src == CRG_CLK_DIS ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_DIS); + else if ( src == CRG_MCLK ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_MCLK); + else if ( src == CRG_RCLK ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_RCLK); + else CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_OCLK); +} + +void CRG_TIMERCLK_SetPrescale(CRG_TIMER num, CRG_PREDIV prediv) +{ + assert_param(IS_CRG_TIMERCLK_NUM(num)); + assert_param(IS_CRG_TIMERCLK_PREDIV(prediv)); + + if ( prediv == CRG_PREDIV1 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV1); + else if ( prediv == CRG_PREDIV2 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV2); + else if ( prediv == CRG_PREDIV4 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV4); + else if ( prediv == CRG_PREDIV8 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV8); + else if ( prediv == CRG_PREDIV16 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV16); + else if ( prediv == CRG_PREDIV32 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV32); + else if ( prediv == CRG_PREDIV64 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV64); + else CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV128); +} + +void CRG_PWMCLK_SourceSelect(CRG_PWM num, CRG_CLK_SOURCE src) +{ + assert_param(IS_CRG_PWMCLK_NUM(num)); + assert_param(IS_CRG_PWMCLK_SRC(src)); + + if ( src == CRG_CLK_DIS ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_DIS); + else if ( src == CRG_MCLK ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_MCLK); + else if ( src == CRG_RCLK ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_RCLK); + else CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_OCLK); +} + +void CRG_PWMCLK_SetPrescale(CRG_PWM num, CRG_PREDIV prediv) +{ + assert_param(IS_CRG_PWMCLK_NUM(num)); + assert_param(IS_CRG_PWMCLK_PREDIV(prediv)); + + if ( prediv == CRG_PREDIV1 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV1); + else if ( prediv == CRG_PREDIV2 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV2); + else if ( prediv == CRG_PREDIV4 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV4); + else if ( prediv == CRG_PREDIV8 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV8); + else if ( prediv == CRG_PREDIV16 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV16); + else if ( prediv == CRG_PREDIV32 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV32); + else if ( prediv == CRG_PREDIV64 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV64); + else CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV128); +} + +void CRG_RTC_HS_SourceSelect(CRG_CLK_SOURCE src) +{ + assert_param(IS_CRG_RTC_HS_SRC(src)); + + if ( src == CRG_CLK_DIS ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_DIS; + else if ( src == CRG_MCLK ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_MCLK; + else if ( src == CRG_RCLK ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_RCLK; + else CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_OCLK; + + if ( src != CRG_CLK_DIS ) CRG_RTC_SourceSelect(CRG_CLK_HIGH); +} + +void CRG_RTC_HS_SetPrescale(CRG_PREDIV prediv) +{ + assert_param(IS_CRG_RTC_HS_PREDIV(prediv)); + + if ( prediv == CRG_PREDIV1 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV1; + else if ( prediv == CRG_PREDIV2 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV2; + else if ( prediv == CRG_PREDIV4 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV4; + else if ( prediv == CRG_PREDIV8 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV8; + else if ( prediv == CRG_PREDIV16 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV16; + else if ( prediv == CRG_PREDIV32 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV32; + else if ( prediv == CRG_PREDIV64 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV64; + else CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV128; +} + +void CRG_RTC_SourceSelect(CRG_CLK_LOW_SOURCE src) +{ + assert_param(IS_CRG_RTC_LOW_SRC(src)); + + if (src == CRG_CLK_LOW) + { + CRG_RTC_HS_SourceSelect(CRG_CLK_DIS); + CRG->RTC_SSR = CRG_RTC_SSR_LW; + } + else + { + CRG->RTC_SSR = CRG_RTC_SSR_HS; + } +} + +void CRG_WDOGCLK_HS_SourceSelect(CRG_CLK_SOURCE src) +{ + assert_param(IS_CRG_WDOGCLK_HS_SRC(src)); + + if ( src == CRG_CLK_DIS ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_DIS; + else if ( src == CRG_MCLK ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_MCLK; + else if ( src == CRG_RCLK ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_RCLK; + else CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_OCLK; + + if ( src != CRG_CLK_DIS ) CRG_WDOGCLK_SourceSelect(CRG_CLK_HIGH); +} + +void CRG_WDOGCLK_HS_SetPrescale(CRG_PREDIV prediv) +{ + assert_param(IS_CRG_WDOGCLK_HS_PREDIV(prediv)); + + if ( prediv == CRG_PREDIV1 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV1; + else if ( prediv == CRG_PREDIV2 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV2; + else if ( prediv == CRG_PREDIV4 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV4; + else if ( prediv == CRG_PREDIV8 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV8; + else if ( prediv == CRG_PREDIV16 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV16; + else if ( prediv == CRG_PREDIV32 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV32; + else if ( prediv == CRG_PREDIV64 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV64; + else CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV128; +} + +void CRG_WDOGCLK_SourceSelect(CRG_CLK_LOW_SOURCE src) +{ + assert_param(IS_CRG_WDOGCLK_LOW_SRC(src)); + + if (src == CRG_CLK_LOW) + { + CRG_WDOGCLK_HS_SourceSelect(CRG_CLK_DIS); + CRG->WDOGCLK_SSR = CRG_WDOGCLK_SSR_LW; + } + else + { + CRG->WDOGCLK_SSR = CRG_WDOGCLK_SSR_HS; + } +} + +void CRG_UARTCLK_SourceSelect(CRG_CLK_SOURCE src) +{ + assert_param(IS_CRG_UARTCLK_SRC(src)); + + if ( src == CRG_CLK_DIS ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_DIS; + else if ( src == CRG_MCLK ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_MCLK; + else if ( src == CRG_RCLK ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_RCLK; + else CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_OCLK; +} + +void CRG_UARTCLK_SetPrescale(CRG_PREDIV prediv) +{ + assert_param(IS_CRG_UARTCLK_PREDIV(prediv)); + + if ( prediv == CRG_PREDIV1 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV1; + else if ( prediv == CRG_PREDIV2 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV2; + else if ( prediv == CRG_PREDIV4 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV4; + else CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV8; +} + +void CRG_MII_Enable(FunctionalState rx_clk, FunctionalState tx_clk) +{ + assert_param(IS_FUNCTIONAL_STATE(rx_clk)); + assert_param(IS_FUNCTIONAL_STATE(tx_clk)); + + if ( rx_clk != DISABLE ) CRG->MIICLK_ECR |= CRG_MIICLK_ECR_EN_RXCLK; + else CRG->MIICLK_ECR &= ~(CRG_MIICLK_ECR_EN_RXCLK); + + if ( tx_clk != DISABLE ) CRG->MIICLK_ECR |= CRG_MIICLK_ECR_EN_TXCLK; + else CRG->MIICLK_ECR &= ~(CRG_MIICLK_ECR_EN_TXCLK); +} + +void CRG_SetMonitoringClock(uint32_t value) +{ + assert_param(IS_CRG_MONCLK_SSR(value)); + + CRG->MONCLK_SSR = value; +} + +uint32_t CRG_GetMonitoringClock(void) +{ + return (uint8_t)CRG->MONCLK_SSR; +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.h new file mode 100644 index 0000000000..28a60d1e45 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.h @@ -0,0 +1,145 @@ +/** + ****************************************************************************** + * @file + * @author + * @version + * @date + * @brief This file contains all the functions prototypes for the Clock Reset Generator + * firmware library. + ****************************************************************************** + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __W7500X_CRG_H +#define __W7500X_CRG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "W7500x.h" + +// It will be in W7500x_crg.h +typedef enum { CRG_CLK_DIS = 0, CRG_MCLK, CRG_RCLK, CRG_OCLK } CRG_CLK_SOURCE; +typedef enum { CRG_CLK_HIGH = 0, CRG_CLK_LOW } CRG_CLK_LOW_SOURCE; +typedef enum { CRG_PREDIV1 = 0, CRG_PREDIV2, CRG_PREDIV4, CRG_PREDIV8, CRG_PREDIV16, \ + CRG_PREDIV32, CRG_PREDIV64, CRG_PREDIV128 } CRG_PREDIV; +typedef enum { CRG_TIMER0 = 0, CRG_TIMER1 } CRG_TIMER; +typedef enum { CRG_PWM0 = 0, CRG_PWM1, CRG_PWM2, CRG_PWM3, CRG_PWM4, CRG_PWM5, CRG_PWM6, CRG_PWM7 } CRG_PWM; + + + +#define IS_CRG_PLL_SRC(SRC) (((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK)) +#define IS_CRG_FCLK_SRC(SRC) (((SRC) == CRG_MCLK) || ((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK)) + +#define CRG_CLK_SRC_DEFAULT(SRC) (((SRC) == CRG_CLK_DIS) || ((SRC) == CRG_MCLK) || \ + ((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK)) +#define CRG_CLK_SRC_LOW(SRC) (((SRC) == CRG_CLK_HIGH) || ((SRC) == CRG_CLK_LOW)) + +#define CRG_CLK_PREDIV_DEFAULT(DIV) (((DIV) == CRG_PREDIV1) || ((DIV) == CRG_PREDIV2) || \ + ((DIV) == CRG_PREDIV4) || ((DIV) == CRG_PREDIV8)) +#define CRG_CLK_PREDIV_ADVANCE(DIV) (((DIV) == CRG_PREDIV1) || ((DIV) == CRG_PREDIV2) || \ + ((DIV) == CRG_PREDIV4) || ((DIV) == CRG_PREDIV8) || \ + ((DIV) == CRG_PREDIV16) || ((DIV) == CRG_PREDIV32) || \ + ((DIV) == CRG_PREDIV64) || ((DIV) == CRG_PREDIV128)) + + +#define IS_CRG_FCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV) + +#define IS_CRG_SSPCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) +#define IS_CRG_SSPCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV) + +#define IS_CRG_ADCCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV) +#define IS_CRG_ADCCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) + + + + + +#define IS_CRG_TIMERCLK_NUM(NUM) (((NUM) == CRG_TIMER0) || ((NUM) == CRG_TIMER1)) +#define IS_CRG_TIMERCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) +#define IS_CRG_TIMERCLK_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV) + +#define CRG_SET_TIMERCLK_SSR(NUM,VALUE) \ + (*((volatile uint32_t *)(CRG->TIMER0CLK_SSR) + (0x10ul * NUM)) = VALUE) +#define CRG_SET_TIMERCLK_PREDIV(NUM,VALUE) \ + (*((volatile uint32_t *)(CRG->TIMER0CLK_PVSR) + (0x10ul * NUM)) = VALUE) +//#define CRG_SET_TIMERCLK_SSR(num,value) CRG->TIMER##num##CLK_SSR = value +//#define CRG_SET_TIMERCLK_PREDIV(num,value) CRG->TIMER##num##CLK_PVSR = value + + +#define IS_CRG_PWMCLK_NUM(NUM) (((NUM) == CRG_PWM0) || ((NUM) == CRG_PWM1) || \ + ((NUM) == CRG_PWM2) || ((NUM) == CRG_PWM3) || \ + ((NUM) == CRG_PWM4) || ((NUM) == CRG_PWM5) || \ + ((NUM) == CRG_PWM6) || ((NUM) == CRG_PWM7) ) +#define IS_CRG_PWMCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) +#define IS_CRG_PWMCLK_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV) + +#define CRG_SET_PWMCLK_SSR(NUM,VALUE) \ + (*((volatile uint32_t *)(CRG->PWM0CLK_SSR) + (0x10ul * NUM)) = VALUE) +#define CRG_SET_PWMCLK_PREDIV(NUM,VALUE) \ + (*((volatile uint32_t *)(CRG->PWM0CLK_PVSR) + (0x10ul * NUM)) = VALUE) +//#define CRG_SET_PWMCLK_SSR(num,value) CRG->PWM##num##CLK_SSR = value +//#define CRG_SET_PWMCLK_PREDIV(num,value) CRG->PWM##num##CLK_PVSR = value + +#define IS_CRG_RTC_HS_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) +#define IS_CRG_RTC_HS_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV) +#define IS_CRG_RTC_LOW_SRC(SRC) CRG_CLK_SRC_LOW(SRC) + +#define IS_CRG_WDOGCLK_HS_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) +#define IS_CRG_WDOGCLK_HS_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV) +#define IS_CRG_WDOGCLK_LOW_SRC(SRC) CRG_CLK_SRC_LOW(SRC) + +#define IS_CRG_UARTCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC) +#define IS_CRG_UARTCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV) + +#define IS_CRG_MONCLK_SSR(value) (((value) >= 0x00ul) || ((value) <= 0x13ul)) + +void CRG_DeInit(void); +void CRG_OSC_PowerDownEnable (FunctionalState NewState); +void CRG_PLL_PowerDownEnable (FunctionalState NewState); +void CRG_PLL_OutputEnable (FunctionalState NewState); +void CRG_PLL_BypassEnable (FunctionalState NewState); +void CRG_PLL_InputFrequencySelect (CRG_CLK_SOURCE src); + +void CRG_FCLK_SourceSelect (CRG_CLK_SOURCE src); +void CRG_FCLK_SetPrescale (CRG_PREDIV prediv); + +void CRG_SSPCLK_SourceSelect (CRG_CLK_SOURCE src); +void CRG_SSPCLK_SetPrescale (CRG_PREDIV prediv); + +void CRG_ADCCLK_SourceSelect (CRG_CLK_SOURCE src); +void CRG_ADCCLK_SetPrescale (CRG_PREDIV prediv); + +void CRG_TIMERCLK_SourceSelect (CRG_TIMER num, CRG_CLK_SOURCE src); +void CRG_TIMERCLK_SetPrescale (CRG_TIMER num, CRG_PREDIV prediv); + +void CRG_PWMCLK_SourceSelect (CRG_PWM num, CRG_CLK_SOURCE src); +void CRG_PWMCLK_SetPrescale (CRG_PWM num, CRG_PREDIV prediv); + +void CRG_RTC_HS_SourceSelect (CRG_CLK_SOURCE src); +void CRG_RTC_HS_SetPrescale (CRG_PREDIV prediv); +void CRG_RTC_SourceSelect (CRG_CLK_LOW_SOURCE src); + +void CRG_WDOGCLK_HS_SourceSelect (CRG_CLK_SOURCE src); +void CRG_WDOGCLK_HS_SetPrescale (CRG_PREDIV prediv); +void CRG_WDOGCLK_SourceSelect (CRG_CLK_LOW_SOURCE src); + +void CRG_UARTCLK_SourceSelect (CRG_CLK_SOURCE src); +void CRG_UARTCLK_SetPrescale (CRG_PREDIV prediv); + +void CRG_MII_Enable (FunctionalState rx_clk, FunctionalState tx_clk); + +void CRG_SetMonitoringClock (uint32_t value); +uint32_t CRG_GetMonitoringClock (void); + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_exti.c b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_exti.c new file mode 100644 index 0000000000..ab6b1e4948 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_exti.c @@ -0,0 +1,157 @@ +#include "W7500x.h" + + + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset values. + * @param None + * @retval None + */ +void EXTI_DeInit(void) +{ + uint32_t i, loop =16; + for(i=0; iPort[i] = 0x00; + EXTI_PB->Port[i] = 0x00; + EXTI_PC->Port[i] = 0x00; + } + for(i=0; i<5; i++) + { + EXTI_PD->Port[i] = 0x00; + } +} + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * that contains the configuration information for the EXTI peripheral. + * @retval None + */ +void EXTI_Init(PAD_Type Px, EXTI_InitTypeDef* EXTI_InitStruct) +{ + uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16; + P_Port_Def *px_exti; + + assert_param(IS_PAD_TYPE(Px)); + + if (Px == PAD_PA) px_exti = EXTI_PA; + else if (Px == PAD_PB) px_exti = EXTI_PB; + else if (Px == PAD_PC) px_exti = EXTI_PC; + else + { + px_exti = (P_Port_Def*)EXTI_PD; + loop = 5; + } + + for(pinpos = 0x00; pinpos < loop; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + + currentpin = (EXTI_InitStruct->EXTI_Line) & pos; + if(currentpin == pos) + { + px_exti->Port[pinpos] |= EXTI_Px_INTEN_ENABLE; + + if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising) + px_exti->Port[pinpos] |= EXTI_Px_INTPOR_RISING_EDGE; + else + px_exti->Port[pinpos] |= EXTI_Px_INTPOR_FALLING_EDGE; + } + } + +} + +void EXTI_Polarity_Set(PAD_Type Px, uint16_t GPIO_Pin, uint16_t Polarity ) +{ + uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16; + P_Port_Def *px_exti; + + assert_param(IS_PAD_TYPE(Px)); + + if (Px == PAD_PA) px_exti = EXTI_PA; + else if (Px == PAD_PB) px_exti = EXTI_PB; + else if (Px == PAD_PC) px_exti = EXTI_PC; + else + { + px_exti = (P_Port_Def*)EXTI_PD; + loop = 5; + } + + for(pinpos = 0x00; pinpos < loop; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + + currentpin = GPIO_Pin & pos; + if(currentpin == pos) + { + if(Polarity == EXTI_Trigger_Rising) + px_exti->Port[pinpos] |= EXTI_Px_INTPOR_RISING_EDGE; + else + px_exti->Port[pinpos] |= EXTI_Px_INTPOR_FALLING_EDGE; + } + } + +} + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = 0xFF; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; +} + +uint16_t EXTI_Px_GetEXTEN(PAD_Type Px) +{ + uint32_t i, loop = 16; + uint16_t ret=0; + P_Port_Def *px_exti; + + assert_param(IS_PAD_TYPE(Px)); + + if (Px == PAD_PA) px_exti = EXTI_PA; + else if (Px == PAD_PB) px_exti = EXTI_PB; + else if (Px == PAD_PC) px_exti = EXTI_PC; + else + { + px_exti = (P_Port_Def*)EXTI_PD; + loop = 5; + } + + for(i = 0x00; i < loop; i++) + { + ret |= (((px_exti->Port[i]&0x2)>>1)<Port[i]&0x1)<DATA = 0x0000; + GPIOx->DATAOUT = 0x0000; + //GPIOx->OUTENSET = 0x0000; + GPIOx->OUTENCLR = 0xFFFF; + //GPIOx->INTENSET = 0x0000; + GPIOx->INTENCLR = 0xFFFF; + //GPIOx->INTTYPESET = 0x0000; + GPIOx->INTTYPECLR = 0xFFFF; + //GPIOx->INTPOLSET = 0x0000; + GPIOx->INTPOLCLR = 0xFFFF; + + + /* DeInit GPIOx + * Pad Control Register + * Pad Extern interrupt Enable Register + * Pad Alternate Function Select Register + */ + if (GPIOx == GPIOA) + { + px_pcr = PA_PCR; + px_afsr = PA_AFSR; + } + else if (GPIOx == GPIOB) + { + px_pcr = PB_PCR; + px_afsr = PB_AFSR; + } + else if (GPIOx == GPIOC) + { + px_pcr = PC_PCR; + px_afsr = PC_AFSR; + } + else // if (GPIOx == GPIOD) + { + px_pcr = (P_Port_Def*)PD_PCR; + px_afsr = (P_Port_Def*)PD_AFSR; + loop = 5; + } + + for(i=0; iPort[i] = 0x60; + px_afsr->Port[i] = PAD_AF0; + + } +} + +void HAL_GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16; + P_Port_Def *px_pcr; + + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); +// assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); + + if (GPIOx == GPIOA) px_pcr = PA_PCR; + else if (GPIOx == GPIOB) px_pcr = PB_PCR; + else if (GPIOx == GPIOC) px_pcr = PC_PCR; + else + { + px_pcr = (P_Port_Def*)PD_PCR; + loop = 5; + } + + for(pinpos = 0x00; pinpos < loop; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if(currentpin == pos) + { + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) + { + GPIOx->OUTENSET |= pos; + } + else // GPIO_Mode_In + { + GPIOx->OUTENCLR = pos; + } + + // Configure pull-up pull-down bits + if(GPIO_InitStruct->GPIO_Pad & Px_PCR_PUPD_UP) + { + px_pcr->Port[pinpos] &= ~(Px_PCR_PUPD_UP | Px_PCR_PUPD_DOWN); + px_pcr->Port[pinpos] |= Px_PCR_PUPD_UP; + } + else + { + px_pcr->Port[pinpos] &= ~(Px_PCR_PUPD_UP | Px_PCR_PUPD_DOWN); + px_pcr->Port[pinpos] |= Px_PCR_PUPD_DOWN; + } + + // Configure Driving stregnth selections bit + if(GPIO_InitStruct->GPIO_Pad & Px_PCR_DS_HIGH) + { + px_pcr->Port[pinpos] |= Px_PCR_DS_HIGH; + } + else + { + px_pcr->Port[pinpos] &= ~(Px_PCR_DS_HIGH); + } + + // Configure Open Drain selections bit + if(GPIO_InitStruct->GPIO_Pad & Px_PCR_OD) + { + px_pcr->Port[pinpos] |= Px_PCR_OD; + } + else + { + px_pcr->Port[pinpos] &= ~(Px_PCR_OD); + } + + // Configure Input buffer enable selection bit + if(GPIO_InitStruct->GPIO_Pad & Px_PCR_IE) + { + px_pcr->Port[pinpos] |= Px_PCR_IE; + } + else + { + px_pcr->Port[pinpos] &= ~(Px_PCR_IE); + } + + // Configure input type (CMOS input or Summit trigger input) select bit + if(GPIO_InitStruct->GPIO_Pad & Px_PCR_CS_SUMMIT) + { + px_pcr->Port[pinpos] |= Px_PCR_CS_SUMMIT; + } + else + { + px_pcr->Port[pinpos] &= ~(Px_PCR_CS_SUMMIT); + } + } + } +} + +void HAL_GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStruct->GPIO_Pad = (GPIOPad_TypeDef)(GPIO_PuPd_UP); +} + + +uint8_t HAL_GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if((GPIOx->DATA & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +uint8_t HAL_GPIO_ReadInputData(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + return ((uint16_t)GPIOx->DATA); +} + +uint8_t HAL_GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + + + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if((GPIOx->DATAOUT & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} +uint16_t HAL_GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALLPERIPH(GPIOx)); + return ((uint16_t)GPIOx->DATAOUT); +} + +void HAL_GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + (GPIOx->LB_MASKED[(uint8_t)(GPIO_Pin)]) = GPIO_Pin; + (GPIOx->UB_MASKED[(uint8_t)((GPIO_Pin)>>8)]) = GPIO_Pin; +} + +void HAL_GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + (GPIOx->LB_MASKED[(uint8_t)(GPIO_Pin)]) = ~(GPIO_Pin); + (GPIOx->UB_MASKED[(uint8_t)(GPIO_Pin>>8)]) = ~(GPIO_Pin); +} + +void HAL_GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + (GPIOx->LB_MASKED[(uint8_t)(GPIO_Pin)]) = BitVal; + (GPIOx->UB_MASKED[(uint8_t)((GPIO_Pin)>>8)]) = BitVal; +} + +void HAL_GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->DATAOUT = PortVal; +} + +void HAL_PAD_AFConfig(PAD_Type Px, uint16_t GPIO_Pin, PAD_AF_TypeDef P_AF) +{ + int i; + uint16_t idx =0x1; + assert_param(IS_PAD_Type(Px)); + + for(i=0;i<16;i++) + { + if(GPIO_Pin & (idx<Port[i] &= ~(0x03ul); + PA_AFSR->Port[i] |= P_AF; + } + else if(Px == PAD_PB) + { + assert_param(IS_PB_NUM(i)); + PB_AFSR->Port[i] &= ~(0x03ul); + PB_AFSR->Port[i] |= P_AF; + } + else if(Px == PAD_PC) + { + assert_param(IS_PC_NUM(i)); + PC_AFSR->Port[i] &= ~(0x03ul); + PC_AFSR->Port[i] |= P_AF; + } + else + { + assert_param(IS_PD_NUM(i)); + PD_AFSR->Port[i] &= ~(0x03ul); + PD_AFSR->Port[i] |= P_AF; + } + } + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.h new file mode 100644 index 0000000000..31586c4a72 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.h @@ -0,0 +1,134 @@ +/** + ****************************************************************************** + * @file + * @author + * @version + * @date + * @brief This file contains all the functions prototypes for the GPIO + * firmware library. + ****************************************************************************** + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __W7500X_HAL_GPIO_H +#define __W7500X_HAL_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "W7500x.h" + +#define GPIO_Pin_0 (uint16_t)(0x01 << 0) // Pin 0 Selected +#define GPIO_Pin_1 (uint16_t)(0x01 << 1) // Pin 1 Selected +#define GPIO_Pin_2 (uint16_t)(0x01 << 2) // Pin 2 Selected +#define GPIO_Pin_3 (uint16_t)(0x01 << 3) // Pin 3 Selected +#define GPIO_Pin_4 (uint16_t)(0x01 << 4) // Pin 4 Selected +#define GPIO_Pin_5 (uint16_t)(0x01 << 5) // Pin 5 Selected +#define GPIO_Pin_6 (uint16_t)(0x01 << 6) // Pin 6 Selected +#define GPIO_Pin_7 (uint16_t)(0x01 << 7) // Pin 7 Selected +#define GPIO_Pin_8 (uint16_t)(0x01 << 8) // Pin 8 Selected +#define GPIO_Pin_9 (uint16_t)(0x01 << 9) // Pin 9 Selected +#define GPIO_Pin_10 (uint16_t)(0x01 << 10) // Pin 10 Selected +#define GPIO_Pin_11 (uint16_t)(0x01 << 11) // Pin 11 Selected +#define GPIO_Pin_12 (uint16_t)(0x01 << 12) // Pin 12 Selected +#define GPIO_Pin_13 (uint16_t)(0x01 << 13) // Pin 13 Selected +#define GPIO_Pin_14 (uint16_t)(0x01 << 14) // Pin 14 Selected +#define GPIO_Pin_15 (uint16_t)(0x01 << 15) // Pin 15 Selected +#define GPIO_Pin_All (uint16_t)(0xFFFF) // All pins Selected + + +#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00) +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || ((PIN) == GPIO_Pin_1) || \ + (((PIN) == GPIO_Pin_2) || ((PIN) == GPIO_Pin_3) || \ + (((PIN) == GPIO_Pin_4) || ((PIN) == GPIO_Pin_5) || \ + (((PIN) == GPIO_Pin_6) || ((PIN) == GPIO_Pin_7) || \ + (((PIN) == GPIO_Pin_8) || ((PIN) == GPIO_Pin_9) || \ + (((PIN) == GPIO_Pin_10) || ((PIN) == GPIO_Pin_11) || \ + (((PIN) == GPIO_Pin_12) || ((PIN) == GPIO_Pin_13) || \ + (((PIN) == GPIO_Pin_14) || ((PIN) == GPIO_Pin_15) ) + + +#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || \ + ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD) ) + +typedef enum +{ + GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ + GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ + GPIO_Mode_AF = 0x02 /*!< GPIO Alternate function Mode */ +}GPIOMode_TypeDef; + +typedef enum +{ + GPIO_NO_PUPD = 0x0ul, + GPIO_PuPd_UP = Px_PCR_PUPD_UP, + GPIO_PuPd_DOWN = Px_PCR_PUPD_DOWN, + GPIO_OD = Px_PCR_OD, +}GPIOPad_TypeDef; + +typedef struct +{ + uint32_t GPIO_Pin; + GPIOMode_TypeDef GPIO_Mode; + GPIOPad_TypeDef GPIO_Pad; +}GPIO_InitTypeDef; + +typedef enum +{ + Bit_RESET = 0, + Bit_SET +}BitAction; + +typedef enum +{ + PAD_PA = 0, + PAD_PB, + PAD_PC, + PAD_PD +}PAD_Type; + +typedef enum +{ + PAD_AF0 = Px_AFSR_AF0, + PAD_AF1 = Px_AFSR_AF1, + PAD_AF2 = Px_AFSR_AF2, + PAD_AF3 = Px_AFSR_AF3 +}PAD_AF_TypeDef; + +#define IS_PAD_TYPE(Px) (((Px) == PAD_PA) || ((Px) == PAD_PB) \ + ((Px) == PAD_PC) || ((Px) == PAD_PD)) + +#define IS_PA_NUM(NUM) (((NUM)>=0) && ((NUM)<16)) +#define IS_PB_NUM(NUM) (((NUM)>=0) && ((NUM)<16)) +#define IS_PC_NUM(NUM) (((NUM)>=0) && ((NUM)<16)) +#define IS_PD_NUM(NUM) (((NUM)>=0) && ((NUM)< 5)) + +#define IS_PAD_AF(AF) (((AF) == PAD_AF0) || ((AF) == PAD_AF1) || \ + ((AF) == PAD_AF2) || ((AF) == PAD_AF3)) + + +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION_ == Bit_RESET) || (ACTION) ==Bit_SET)) + +void HAL_GPIO_DeInit(GPIO_TypeDef* GPIOx); +void HAL_GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void HAL_GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +uint8_t HAL_GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint8_t HAL_GPIO_ReadInputData(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint8_t HAL_GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t HAL_GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void HAL_GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void HAL_GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void HAL_PAD_AFConfig(PAD_Type Px, uint16_t Pnum, PAD_AF_TypeDef P_AF); + + +#ifdef __cplusplus +} +#endif + +#endif // __W7500X_HAL_GPIO_H diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.c b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.c new file mode 100644 index 0000000000..0d23d46774 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.c @@ -0,0 +1,563 @@ +#include "W7500x.h" + +/** @defgroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * @retval None + */ +void I2C_Delay(uint32_t nCount) +{ + for(; nCount != 0; nCount--); +} + +uint32_t I2C_Init(I2C_TypeDef* I2Cx, I2C_ConfigStruct conf) +{ + uint32_t mode; + uint8_t prescale; + uint16_t timeout; + uint16_t slave_address; + + + mode = conf.mode; + slave_address = conf.slave_address; + if(mode == I2C_Master) + { + prescale = conf.master.prescale; + timeout = conf.master.timeout; + + I2C_CoreEn(I2Cx,ENABLE); + I2C_MasterSlave(I2Cx,ENABLE); + + I2C_Prescale(I2Cx,prescale); // 0x61 //When PLL clk is 20MHz and Prescale value set 0x61, SCL is 100KHz + I2C_TimeoutSet(I2Cx,timeout); // 0xFFFF + + I2C_CoreEn(I2Cx,DISABLE); + } + else if(conf.mode == I2C_Slave) + { + I2C_AcknowledgeConfig(I2Cx,ENABLE); + I2C_SetSlavAddress(I2Cx,slave_address); + } + else + return ERROR; + + + I2C_AcknowledgeConfig(I2Cx,ENABLE); + + return SUCCESS; +} + + +void I2C_DeInit(I2C_TypeDef* I2Cx) +{ + I2C_InterRst(I2Cx,ENABLE); + I2C_CoreEn(I2Cx, ENABLE); + I2C_InterRst(I2Cx,DISABLE); + I2C_CoreEn(I2Cx, DISABLE); +} + + +ErrorStatus I2C_Start(I2C_TypeDef* I2Cx, uint16_t slave_address, I2C_CTR ctr) +{ + ErrorStatus ret; + + I2C_GenerateSTART(I2Cx,ENABLE); + I2C_SendSlaveAddress(I2Cx,slave_address,(I2C_CTR)ctr); + I2C_GenerateSTART(I2Cx,DISABLE); + + ret=I2C_CheckEvent(I2Cx,I2C_ACKR); + + return ret; +} + +void I2C_Stop(I2C_TypeDef* I2Cx) +{ + I2C_GenerateSTOP(I2Cx,ENABLE); + I2C_GenerateSTOP(I2Cx,DISABLE); +} + +void I2C_Reset(I2C_TypeDef* I2Cx) +{ + I2C_CoreEn(I2Cx,ENABLE); + // Maybe, it needs a little delay + I2C_CoreEn(I2Cx,DISABLE); +} + +void I2C_SendData(I2C_TypeDef* I2Cx,uint16_t Data) +{ + I2Cx -> TXR = (uint16_t)Data; +} + +int8_t I2C_SendDataAck(I2C_TypeDef* I2Cx,uint16_t Data) +{ + I2Cx -> TXR = (uint16_t)Data; + if(I2C_CheckEvent(I2Cx,I2C_ACKR) == ERROR) + { + return ERROR; + } + return SUCCESS; +} + +int I2C_ReceiveData(I2C_TypeDef* I2Cx, int last) +{ + if( I2C_CheckEvent(I2Cx,I2C_ACKT) == ERROR ) + return -1; + + if(last) + { + I2C_AcknowledgeConfig(I2Cx,DISABLE); + if( I2C_CheckEvent(I2Cx,I2C_ACKT) == ERROR ) + return -1; + + I2C_Stop(I2Cx); + } + + + return (uint8_t)I2Cx -> RXR; +} + + +int I2C_Burst_Read(I2C_TypeDef* I2Cx, uint16_t address, uint8_t *data, int length, int stop) +{ + int recv_cnt; + + if( I2C_Start(I2Cx,address,I2C_READ_SA7) == ERROR){ + return -1; + } + + for(recv_cnt=0;recv_cntCMDR = I2C_CMDR_STA; + else I2Cx->CMDR = I2C_CMDR_STA; + } +/** + * @brief Generates I2Cx communication STOP condition. + * @param I2Cx: where x can be 0 or 1 to select the I2C peripheral. + * @param NewState: NewState of the I2C STOP condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) I2Cx->CMDR = I2C_CMDR_STO; + else I2Cx->CMDR = I2C_CMDR_STO; +} + +/** + * @brief Enables or disables the specified I2C acknowledge feature. + * @param I2Cx: where x can be 0 or 1 to select the I2C peripheral. + * @param NewState: NewState of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) I2Cx -> CMDR = I2C_CMDR_ACK; + else I2Cx -> CMDR = I2C_CMDR_ACK; +} + +/** + * @brief Generates I2Cx communication REGenerateSTART condition + * @param I2Cx: where x can be 0 or 1 to select the I2C peripheral. + * @param NewState: NewState of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_RESTART(I2C_TypeDef * I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) I2Cx->CMDR = I2C_CMDR_RESTA; + else I2Cx->CMDR = I2C_CMDR_RESTA; +} + +/** + * @brief Enable or disable the specified I2C Core_en feature + * @param I2Cx: where x can be 0 or 1 to select the I2C peripheral. + * @param NewState: NewState of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_CoreEn(I2C_TypeDef* I2Cx,FunctionalState NewState) +{ + /*Control*/ + if(NewState != DISABLE) I2Cx -> CTR = I2C_CTR_COREEN; + else I2Cx -> CTR = I2C_CTR_COREEN; +} + + +void I2C_InterEn(I2C_TypeDef* I2Cx,FunctionalState NewState) +{ + /*Control Interrupt Enable*/ + if(NewState != DISABLE) I2Cx -> CTR = I2C_CTR_INTEREN; + else I2Cx -> CTR = I2C_CTR_INTEREN; +} + + +void I2C_MasterSlave(I2C_TypeDef* I2Cx,FunctionalState NewState) +{ + /*Control MasterSlave select*/ + if(NewState == ENABLE) + { + if( (I2Cx->CTR & I2C_CTR_MODE) != I2C_CTR_MODE ) + { + I2Cx->CTR = I2C_CTR_MODE; + } + } + else // DISABLE + { + if( (I2Cx->CTR & I2C_CTR_MODE) == I2C_CTR_MODE ) + { + I2Cx->CTR = I2C_CTR_MODE; + } + } +} + + +void I2C_ControlRW(I2C_TypeDef* I2Cx,FunctionalState NewState) +{ + /*Control Read(receive)*/ + if(NewState == ENABLE) + { + if( (I2Cx->CTR & I2C_CTR_CTRRWN) != I2C_CTR_CTRRWN ) + { + I2Cx->CTR = I2C_CTR_CTRRWN; + } + } + else // DISABLE + { + if( (I2Cx->CTR & I2C_CTR_CTRRWN) == I2C_CTR_CTRRWN ) + { + I2Cx->CTR = I2C_CTR_CTRRWN; + } + } +} + + +void I2C_ControlEn(I2C_TypeDef* I2Cx,FunctionalState NewState) +{ + /*Control*/ + if(NewState == ENABLE) + { + if( (I2Cx->CTR & I2C_CTR_CTEN) != I2C_CTR_CTEN ) + { + I2Cx->CTR = I2C_CTR_CTEN; + } + } + else // DISABLE + { + if( (I2Cx->CTR & I2C_CTR_CTEN) == I2C_CTR_CTEN ) + { + I2Cx->CTR = I2C_CTR_CTEN; + } + } +} + + +void I2C_InterRst(I2C_TypeDef* I2Cx,FunctionalState NewState) +{ + /*Control*/ + if(NewState == ENABLE) + { + if( (I2Cx->ISCR & I2C_ISCR_RST) != I2C_ISCR_RST ) + { + I2Cx->ISCR = I2C_ISCR_RST; + } + } + else // DISABLE + { + if( (I2Cx->ISCR & I2C_ISCR_RST) == I2C_ISCR_RST ) + { + I2Cx->ISCR = I2C_ISCR_RST; + } + } +} + +void I2C_Prescale(I2C_TypeDef* I2Cx,uint16_t Data) +{ + I2Cx -> PRER = (uint16_t)Data; +} + +void I2C_TimeoutSet(I2C_TypeDef* I2Cx,uint16_t Data) +{ + I2Cx -> TSR = (uint16_t)Data; +} +void I2C_SetSlavAddress(I2C_TypeDef* I2Cx,uint16_t Data) +{ + I2Cx -> SADDR = (uint16_t)Data; +} + + +uint8_t I2C_StatusRead(I2C_TypeDef* I2Cx) +{ + return (uint8_t)I2Cx -> SR; +} + + +ErrorStatus WaitEvent(I2C_TypeDef* I2Cx, uint32_t flag, FlagStatus status) +{ + int Timeout=0,loopcnt=0; + + Timeout = I2Cx->TSR; + if(status == SET) + { + for(loopcnt=Timeout; loopcnt>0; loopcnt--) + { + if( ((I2Cx->SR) & flag) == flag ) + return SUCCESS; + } + } + else + { + for(loopcnt=Timeout; loopcnt>0; loopcnt--) + { + if( ((I2Cx->SR) & flag) != flag ) + return SUCCESS; + } + } + + + return ERROR; +} + + +/** + * @brief Checks whether the specified I2C flag is set or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_EVENT: specifies the event to be checked. + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx,I2C_SR sr) +{ + switch(sr) + { + case(I2C_ACKR): + if( WaitEvent(I2Cx, I2C_SR_ACKR, SET) == ERROR) return ERROR; + if( WaitEvent(I2Cx, I2C_SR_ACKR, RESET) == ERROR) return ERROR; + break; + + case(I2C_ACKT ): + if( WaitEvent(I2Cx, I2C_SR_ACKT, SET) == ERROR) return ERROR; + if( WaitEvent(I2Cx, I2C_SR_ACKT, RESET) == ERROR) return ERROR; + break; + + case(I2C_OACKR): + if( WaitEvent(I2Cx, I2C_SR_ACKR, SET) == ERROR) return ERROR; + break; + + case(I2C_SACKR ): + if( WaitEvent(I2Cx, I2C_SR_ACKR, RESET) == ERROR) return ERROR; + break; + + case(I2C_BT ): + if( WaitEvent(I2Cx, I2C_SR_BT, RESET) == ERROR) return ERROR; + break; + + default: + return ERROR; + } + + return SUCCESS; +} + + +/* +void I2C_MasterInit(I2C_TypeDef * I2Cx,uint8_t Prescale,uint16_t Timeout,I2C_CTR Ctr) +{ + switch(Ctr) + { + case(I2C_WRITE_SA7): //000 + case(I2C_READ_SA7): //001 + I2C_CoreEn(I2Cx,ENABLE); + break; + + case(I2C_WRITE_SA10): //010 + case(I2C_READ_SA10): //011 + I2C_CoreEn(I2Cx,ENABLE); + I2C_SlaveAddressLength(I2Cx,ENABLE); + break; + + case(I2C_CTRWRITE_SA7): //100 + I2C_CoreEn(I2Cx,ENABLE); + I2C_ControlEn(I2Cx,ENABLE); + break; + + case(I2C_CTRREAD_SA7): //101 + I2C_CoreEn(I2Cx,ENABLE); + I2C_ControlRW(I2Cx,ENABLE); + I2C_ControlEn(I2Cx,ENABLE); + break; + + case(I2C_CTRWRITE_SA10): //110 + I2C_CoreEn(I2Cx,ENABLE); + I2C_ControlRW(I2Cx,DISABLE); + I2C_ControlEn(I2Cx,ENABLE); + I2C_SlaveAddressLength(I2Cx,ENABLE); + break; + case(I2C_CTRREAD_SA10): //111 + I2C_CoreEn(I2Cx,ENABLE); + I2C_ControlRW(I2Cx,ENABLE); + I2C_ControlEn(I2Cx,ENABLE); + I2C_SlaveAddressLength(I2Cx,ENABLE); + break; + + default: + return; + + } + + I2C_MasterSlave(I2Cx,ENABLE); + I2C_MasterSlave(I2Cx,DISABLE); + I2C_MasterSlave(I2Cx,ENABLE); + + I2C_Prescale(I2Cx,Prescale); // 0x61 //When PLL clk is 20MHz and Prescale value set 0x61, SCL is 100KHz + I2C_TimeoutSet(I2Cx,Timeout); // 0xFFFF + +#if defined(I2C_INT) + I2C_CoreEn(I2Cx,DISABLE); + I2C_InterEn(I2Cx,ENABLE); +#else + I2C_CoreEn(I2Cx,DISABLE); + +#endif + +} + +void I2C_SlaveInit(I2C_TypeDef * I2Cx, FunctionalState NewState,uint16_t data) +{ + if(NewState != DISABLE) + { + I2C_SlaveAddressLength(I2Cx,ENABLE); + } + else + I2C_AcknowledgeConfig(I2Cx,ENABLE); + + I2C_SetSlavAddress(I2Cx,data); +} +*/ + +void I2C_SendSlaveAddress(I2C_TypeDef* I2Cx, uint8_t SlaveAddress,I2C_CTR Ctr) +{ + switch(Ctr) + { + case(I2C_READ_SA7): + I2C_SendData(I2Cx,SlaveAddress|I2C_READ); + break; + + + case(I2C_WRITE_SA7): + I2C_SendData(I2Cx,SlaveAddress|I2C_WRITE); + break; + +// case(I2C_READ_SA10): +// I2C_SendData(I2Cx,SlaveAddress|I2C_READ); +// break; +// +// case(I2C_WRITE_SA10): +// I2C_SendData(I2Cx,SlaveAddress|I2C_WRITE); +// break; + + case(I2C_CTRWRITE_SA7): + case(I2C_CTRREAD_SA7): +// case(I2C_CTRWRITE_SA10): +// case(I2C_CTRREAD_SA10): + I2C_SendData(I2Cx,SlaveAddress); + break; + + default: + return; + + } +} + + int8_t I2C_Restart_Structure(I2C_TypeDef * I2Cx,uint32_t SlaveAddress,I2C_CTR Ctr) +{ + + I2C_RESTART(I2Cx,ENABLE); + I2C_SendSlaveAddress(I2Cx,SlaveAddress,Ctr); + if((I2C_CheckEvent(I2Cx,I2C_OACKR)) == ERROR ) + { + return 0; + } + I2C_RESTART(I2Cx,DISABLE); + if((I2C_CheckEvent(I2Cx,I2C_SACKR)) == ERROR) + { + return 0; + } + return 1; +} + +/** + * @brief Reads the specified I2C register and returns its value. + * @param I2C_Register: specifies the register to read. + * This parameter can be one of the following values: + * @arg I2C_Register_CR1: CR1 register. + * @arg I2C_Register_CR2: CR2 register. + * @arg I2C_Register_OAR1: OAR1 register. + * @arg I2C_Register_OAR2: OAR2 register. + * @arg I2C_Register_DR: DR register. + * @arg I2C_Register_SR1: SR1 register. + * @arg I2C_Register_SR2: SR2 register. + * @arg I2C_Register_CCR: CCR register. + * @arg I2C_Register_TRISE: TRISE register. + * @retval The value of the read register. + */ +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + + tmp = (uint32_t) I2Cx; + tmp += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint16_t *) tmp); +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.h new file mode 100644 index 0000000000..683dee9296 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.h @@ -0,0 +1,231 @@ +#include "W7500x.h" + +/** +* @defgroup I2C_Public_Types I2X Public Types +*/ +typedef enum +{ + I2C_WRITE_SA7=0, + I2C_READ_SA7, + //I2C_WRITE_SA10, + //I2C_READ_SA10, + I2C_CTRWRITE_SA7, + I2C_CTRREAD_SA7, + //I2C_CTRWRITE_SA10, + //I2C_CTRREAD_SA10, +} I2C_CTR; + +typedef enum +{ + I2C_ACKR=0, + I2C_ACKT, + I2C_OACKR, + I2C_SACKR, + I2C_BT, +} I2C_SR; + + +typedef enum +{ + INT_ACKR=-1, + INT_ACKT=-2, + INT_NACKR=-3, + INT_NACKT=-4, + INT_BT=-5, +} I2C_ERROR; + + +/** +*@ +*/ +/** @defgroup I2C_registers + * @{ + */ + +#define I2C_Register_PRER ((uint8_t)0x00) +#define I2C_Register_CTR ((uint8_t)0x04) +#define I2C_Register_CMDR ((uint8_t)0x08) +#define I2C_Register_SR ((uint8_t)0x0C) +#define I2C_Register_TSR ((uint8_t)0x10) +#define I2C_Register_SADDR ((uint8_t)0x14) +#define I2C_Register_TXR ((uint8_t)0x18) +#define I2C_Register_RXR ((uint8_t)0x1C) +#define I2C_Register_ISR ((uint8_t)0x20) +#define I2C_Register_ISCR ((uint8_t)0x24) +#define I2C_Register_ISMR ((uint8_t)0x28) +#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_PRER) || \ + ((REGISTER) == I2C_Register_CTR) || \ + ((REGISTER) == I2C_Register_CMDR) || \ + ((REGISTER) == I2C_Register_SR) || \ + ((REGISTER) == I2C_Register_TSR) || \ + ((REGISTER) == I2C_Register_SADDR) || \ + ((REGISTER) == I2C_Register_TXR) || \ + ((REGISTER) == I2C_Register_RXR) || \ + ((REGISTER) == I2C_Register_ISR)|| \ + ((REGISTER) == I2C_Register_ISCR)| \ + ((REGISTER) == I2C_Register_ISMR)) +/** + * @} + */ +/** @addtogroup Peripheral_registers_structures + * @{ + */ + + + + + + +/** + * @} + */ + +/** + * @brief I2C Interrput Status Register Mask flags + */ +//------------------------------------------------ +// I2C_ISMR_BIT +//------------------------------------------------ + +/** + * @} + */ + +/** @defgroup I2C_Private_Defines + * @{ + */ +/* I2C COREEN mask */ +#define I2C_CTR_COREEN_DIS ((uint16_t)0xFF7F) + +/* I2C INTEREN mask */ +#define I2C_CTR_INTEREN_DIS ((uint16_t)0xFFBF) + +/* I2C MODE(M/SN) mask */ +#define I2C_CTR_MODE_SLAVE ((uint16_t)0xFFDF) + +/* I2C ADDR10(10/7N) mask */ +#define I2C_CTR_ADDR10_7BIT ((uint16_t)0xFFEF) + +/* I2C CTRRWN(R/WN) mask */ +#define I2C_CTR_CTRRWN_DIS ((uint16_t)0xFFF7) + +/* I2C CTREN mask */ +#define I2C_CTR_CTEN_DIS ((uint16_t)0xFFFB) + + +/* I2C START mask */ +#define I2C_CMDR_START_DIS ((uint16_t)0xFF7F) + +/* I2C STOP mask */ +#define I2C_CMDR_STOP_DIS ((uint16_t)0xFFBF) + +/* I2C ACK mask */ +#define I2C_CMDR_ACK_NAK ((uint16_t)0xFFDF) + +/* I2C RESTART mask */ +#define I2C_CMDR_RESTA_DIS ((uint16_t)0xFFEF) + +/* I2C INTERRUPT RESET mask */ +#define I2C_ISCR_RST_DIS ((uint16_t)0xFFFE) +/** + * @} + */ + + + +#define I2C_WRITE 0 +#define I2C_READ 1 +#define I2C_RWSEL(NewState) (((NewState) == I2C_WRITE)|| \ + ((NewState) == I2C_READ)) + + +#define I2C_Ack_Enable (0x01ul << 5) +#define I2C_Ack_Disable (0x00ul << 5) +#define IS_I2C_ACK_NewState(NewState) (((NewState) == I2C_Ack_Enable) || \ + ((NewState) == I2C_Ack_Disable)) + +#define I2C_MASTER_MODE (0x01ul << 5 ) // 0x20 +#define I2C_SLAVE_MODE (0x00ul << 5 ) // 0x20 +#define IS_I2C_MODE(MODE) ((MODE) == I2C_MASTER_MODE)|| \ + (MODE) == I2C_SLAVE_MODE)) + +#define I2C_CTR_MODE (0x01ul << 5 ) // 0x20 + +#define SLAVE_ADDR10 0x208 + + +typedef enum + { + I2C_Master = I2C_MASTER_MODE, + I2C_Slave = I2C_SLAVE_MODE + }I2C_MODE; + + +typedef struct +{ + uint8_t prescale; + uint16_t timeout; + I2C_CTR control; +}I2C_MasterConfStruct; + + +typedef struct +{ + uint32_t mode; + uint16_t slave_address; // only on slave mode + I2C_MasterConfStruct master; +}I2C_ConfigStruct; + + +/** @defgroup I2C_Exported_Functions + * @{ + */ + +uint32_t I2C_Init (I2C_TypeDef* I2Cx, I2C_ConfigStruct conf); +void setFrequency (I2C_TypeDef* I2Cx, uint8_t prescale); +void I2C_DeInit (I2C_TypeDef* I2Cx); + +ErrorStatus I2C_Start (I2C_TypeDef* I2Cx, uint16_t slave_address, I2C_CTR ctr); +void I2C_Stop (I2C_TypeDef* I2Cx); +void I2C_Reset (I2C_TypeDef* I2Cx); + +void I2C_SendData (I2C_TypeDef* I2Cx,uint16_t Data); +int8_t I2C_SendDataAck (I2C_TypeDef* I2Cx,uint16_t Data); +int I2C_ReceiveData (I2C_TypeDef* I2Cx, int last); + +int I2C_Burst_Read (I2C_TypeDef* I2Cx, uint16_t address, uint8_t *data, int length, int stop); +int I2C_Burst_Write (I2C_TypeDef* I2Cx, uint16_t address, uint8_t *data, int length, int stop); + +void I2C_Delay (uint32_t nCount); + +void I2C_GenerateSTART (I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP (I2C_TypeDef* I2Cx, FunctionalState NewState); + +void I2C_AcknowledgeConfig (I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_RESTART (I2C_TypeDef * I2Cx, FunctionalState NewState); + +void I2C_CoreEn (I2C_TypeDef* I2Cx,FunctionalState NewState); +void I2C_InterEn (I2C_TypeDef* I2Cx,FunctionalState NewState); +void I2C_MasterSlave(I2C_TypeDef* I2Cx,FunctionalState NewState); +void I2C_ControlRW (I2C_TypeDef* I2Cx,FunctionalState NewState); +void I2C_ControlEn (I2C_TypeDef* I2Cx,FunctionalState NewState); + +void I2C_InterRst (I2C_TypeDef* I2Cx,FunctionalState NewState); +void I2C_Prescale (I2C_TypeDef* I2Cx,uint16_t Data); +void I2C_TimeoutSet (I2C_TypeDef* I2Cx,uint16_t Data); +void I2C_SetSlavAddress (I2C_TypeDef* I2Cx,uint16_t Data); +uint8_t I2C_StatusRead (I2C_TypeDef* I2Cx); + +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx,I2C_SR sr); + +void I2C_MasterInit (I2C_TypeDef * I2Cx,uint8_t Prescale,uint16_t Timeout,I2C_CTR Ctr); +void I2C_SlaveInit (I2C_TypeDef * I2Cx,FunctionalState NewState, uint16_t data); +void I2C_SendSlaveAddress (I2C_TypeDef* I2Cx, uint8_t SlaveAddress,I2C_CTR Ctr); + +int8_t I2C_Restart_Structure(I2C_TypeDef * I2Cx,uint32_t SlaveAddress,I2C_CTR Ctr); +uint16_t I2C_ReadRegister (I2C_TypeDef* I2Cx, uint8_t I2C_Register); + +/** + * @} + */ + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.c b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.c new file mode 100644 index 0000000000..d364279a3a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.c @@ -0,0 +1,905 @@ +/** + ****************************************************************************** + * @file + * @author + * @version + * @date + * @brief This file contains all the functions prototypes for the UART + * firmware library. + ****************************************************************************** + * + ****************************************************************************** + */ + +/* Includes -------------------------------------------*/ +#include "W7500x.h" + +void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn) +{ + if( PWM_CHn == PWM_CH0 ) + { + PWM->IER &= PWM_IER_IE0_Disable; ///< Interrupt enable register + PWM->SSR &= PWM_SSR_SS0_Stop; ///< Start Stop register + PWM->PSR &= PWM_PSR_PS0_Restart; ///< Pause register + PWM_CH0->IER = 0; ///< Interrupt enable register + PWM_CH0->ICR = PWM_CHn_ICR_MatchInterruptClear | + PWM_CHn_ICR_OverflowInterruptClear | + PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register + PWM_CH0->PR = 0; ///< Prescale register + PWM_CH0->MR = 0; ///< Match register + PWM_CH0->LR = 0xFFFFFFFF; ///< Limit register + PWM_CH0->UDMR = 0; ///< Up Dowm mode register + PWM_CH0->TCMR = 0; ///< Timer Counter mode register + PWM_CH0->PEEER = 0; ///< PWM output Enable and External input Enable register + PWM_CH0->CMR = 0; ///< Capture mode register + PWM_CH0->PDMR = 0; ///< Periodic Mode register + PWM_CH0->DZER = 0; ///< Dead Zone Enable register + PWM_CH0->DZCR = 0; ///< Dead Zone Counter register + } + else if( PWM_CHn == PWM_CH1 ) + { + PWM->IER &= PWM_IER_IE1_Disable; ///< Reset Interrupt enable register + PWM->SSR &= PWM_SSR_SS1_Stop; ///< Reset Start Stop register + PWM->PSR &= PWM_PSR_PS1_Restart; ///< Reset Pause register + PWM_CH1->IER = 0; ///< Interrupt enable register + PWM_CH1->ICR = PWM_CHn_ICR_MatchInterruptClear | + PWM_CHn_ICR_OverflowInterruptClear | + PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register + PWM_CH1->PR = 0; ///< Prescale register + PWM_CH1->MR = 0; ///< Match register + PWM_CH1->LR = 0xFFFFFFFF; ///< Limit register + PWM_CH1->UDMR = 0; ///< Up Dowm mode register + PWM_CH1->TCMR = 0; ///< Timer Counter mode register + PWM_CH1->PEEER = 0; ///< PWM output Enable and External input Enable register + PWM_CH1->CMR = 0; ///< Capture mode register + PWM_CH1->PDMR = 0; ///< Periodic Mode register + PWM_CH1->DZER = 0; ///< Dead Zone Enable register + PWM_CH1->DZCR = 0; ///< Dead Zone Counter register + } + else if( PWM_CHn == PWM_CH2) + { + PWM->IER &= PWM_IER_IE2_Disable; ///< Interrupt enable register + PWM->SSR &= PWM_SSR_SS2_Stop; ///< Start Stop register + PWM->PSR &= PWM_PSR_PS2_Restart; ///< Pause register + PWM_CH2->IER = 0; ///< Interrupt enable register + PWM_CH2->ICR = PWM_CHn_ICR_MatchInterruptClear | + PWM_CHn_ICR_OverflowInterruptClear | + PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register + PWM_CH2->PR = 0; ///< Prescale register + PWM_CH2->MR = 0; ///< Match register + PWM_CH2->LR = 0xFFFFFFFF; ///< Limit register + PWM_CH2->UDMR = 0; ///< Up Dowm mode register + PWM_CH2->TCMR = 0; ///< Timer Counter mode register + PWM_CH2->PEEER = 0; ///< PWM output Enable and External input Enable register + PWM_CH2->CMR = 0; ///< Capture mode register + PWM_CH2->PDMR = 0; ///< Periodic Mode register + PWM_CH2->DZER = 0; ///< Dead Zone Enable register + PWM_CH2->DZCR = 0; ///< Dead Zone Counter register + } + else if( PWM_CHn == PWM_CH3 ) + { + PWM->IER &= PWM_IER_IE3_Disable; ///< Interrupt enable register + PWM->SSR &= PWM_SSR_SS3_Stop; ///< Start Stop register + PWM->PSR &= PWM_PSR_PS3_Restart; ///< Pause register + PWM_CH3->IER = 0; ///< Interrupt enable register + PWM_CH3->ICR = PWM_CHn_ICR_MatchInterruptClear | + PWM_CHn_ICR_OverflowInterruptClear | + PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register + PWM_CH3->MR = 0; ///< Match register + PWM_CH3->LR = 0xFFFFFFFF; ///< Limit register + PWM_CH3->UDMR = 0; ///< Up Dowm mode register + PWM_CH3->TCMR = 0; ///< Timer Counter mode register + PWM_CH3->PEEER = 0; ///< PWM output Enable and External input Enable register + PWM_CH3->CMR = 0; ///< Capture mode register + PWM_CH3->PDMR = 0; ///< Periodic Mode register + PWM_CH3->DZER = 0; ///< Dead Zone Enable register + PWM_CH3->DZCR = 0; ///< Dead Zone Counter register + } + else if( PWM_CHn == PWM_CH4 ) + { + PWM->SSR &= PWM_IER_IE4_Disable; ///< Start Stop register + PWM->PSR &= PWM_SSR_SS4_Stop; ///< Pause register + PWM->IER &= PWM_PSR_PS4_Restart; ///< Interrupt enable register + PWM_CH4->IER = 0; ///< Interrupt enable register + PWM_CH4->ICR = PWM_CHn_ICR_MatchInterruptClear | + PWM_CHn_ICR_OverflowInterruptClear | + PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register + PWM_CH4->PR = 0; ///< Prescale register + PWM_CH4->MR = 0; ///< Match register + PWM_CH4->LR = 0xFFFF; ///< Limit register + PWM_CH4->UDMR = 0; ///< Up Dowm mode register + PWM_CH4->TCMR = 0; ///< Timer Counter mode register + PWM_CH4->PEEER = 0; ///< PWM output Enable and External input Enable register + PWM_CH4->CMR = 0; ///< Capture mode register + PWM_CH4->PDMR = 0; ///< Periodic Mode register + PWM_CH4->DZER = 0; ///< Dead Zone Enable register + PWM_CH4->DZCR = 0; ///< Dead Zone Counter register + } + else if( PWM_CHn == PWM_CH5 ) + { + PWM->SSR &= PWM_IER_IE5_Disable; ///< Start Stop register + PWM->PSR &= PWM_SSR_SS5_Stop; ///< Pause register + PWM->IER &= PWM_PSR_PS5_Restart; ///< Interrupt enable register + PWM_CH5->IER = 0; ///< Interrupt enable register + PWM_CH5->ICR = PWM_CHn_ICR_MatchInterruptClear | + PWM_CHn_ICR_OverflowInterruptClear | + PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register + PWM_CH5->PR = 0; ///< Prescale register + PWM_CH5->MR = 0; ///< Match register + PWM_CH5->LR = 0xFFFFFFFF; ///< Limit register + PWM_CH5->UDMR = 0; ///< Up Dowm mode register + PWM_CH5->TCMR = 0; ///< Timer Counter mode register + PWM_CH5->PEEER = 0; ///< PWM output Enable and External input Enable register + PWM_CH5->CMR = 0; ///< Capture mode register + PWM_CH5->PDMR = 0; ///< Periodic Mode register + PWM_CH5->DZER = 0; ///< Dead Zone Enable register + PWM_CH5->DZCR = 0; ///< Dead Zone Counter register + } + else if( PWM_CHn == PWM_CH6 ) + { + PWM->SSR &= PWM_IER_IE6_Disable; ///< Start Stop register + PWM->PSR &= PWM_SSR_SS6_Stop; ///< Pause register + PWM->IER &= PWM_PSR_PS6_Restart; ///< Interrupt enable register + PWM_CH6->IER = 0; ///< Interrupt enable register + PWM_CH6->ICR = PWM_CHn_ICR_MatchInterruptClear | + PWM_CHn_ICR_OverflowInterruptClear | + PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register + PWM_CH6->PR = 0; ///< Prescale register + PWM_CH6->MR = 0; ///< Match register + PWM_CH6->LR = 0xFFFFFFFF; ///< Limit register + PWM_CH6->UDMR = 0; ///< Up Dowm mode register + PWM_CH6->TCMR = 0; ///< Timer Counter mode register + PWM_CH6->PEEER = 0; ///< PWM output Enable and External input Enable register + PWM_CH6->CMR = 0; ///< Capture mode register + PWM_CH6->PDMR = 0; ///< Periodic Mode register + PWM_CH6->DZER = 0; ///< Dead Zone Enable register + PWM_CH6->DZCR = 0; ///< Dead Zone Counter register + } + else if( PWM_CHn == PWM_CH7 ) + { + PWM->SSR &= PWM_IER_IE7_Disable; ///< Start Stop register + PWM->PSR &= PWM_SSR_SS7_Stop; ///< Pause register + PWM->IER &= PWM_PSR_PS7_Restart; ///< Interrupt enable register + PWM_CH7->IER = 0; ///< Interrupt enable register + PWM_CH7->ICR = PWM_CHn_ICR_MatchInterruptClear | + PWM_CHn_ICR_OverflowInterruptClear | + PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register + PWM_CH7->PR = 0; ///< Prescale register + PWM_CH7->MR = 0; ///< Match register + PWM_CH7->LR = 0xFFFFFFFF; ///< Limit register + PWM_CH7->UDMR = 0; ///< Up Dowm mode register + PWM_CH7->TCMR = 0; ///< Timer Counter mode register + PWM_CH7->PEEER = 0; ///< PWM output Enable and External input Enable register + PWM_CH7->CMR = 0; ///< Capture mode register + PWM_CH7->PDMR = 0; ///< Periodic Mode register + PWM_CH7->DZER = 0; ///< Dead Zone Enable register + PWM_CH7->DZCR = 0; ///< Dead Zone Counter register + } +} + + +void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct) //complet +{ + /* Stop PWM_CHn */ + PWM_CHn_Stop(PWM_CHn); + /* Select Timer/Counter mode as Timer mode */ + PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode; + /* Set Prescale register value */ + PWM_CHn->PR = PWM_TimerModeInitStruct->PWM_CHn_PR; + /* Set Match register value */ + PWM_CHn->MR = PWM_TimerModeInitStruct->PWM_CHn_MR; + /* Set Limit register value */ + PWM_CHn->LR = PWM_TimerModeInitStruct->PWM_CHn_LR; + /* Select Up-down mode */ + PWM_CHn->UDMR = PWM_TimerModeInitStruct->PWM_CHn_UDMR; + /* Select Periodic mode */ + PWM_CHn->PDMR = PWM_TimerModeInitStruct->PWM_CHn_PDMR; +} + +void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_PR_FILTER(PWM_CaptureModeInitStruct->PWM_CHn_PR)); + assert_param(IS_PWM_MR_FILTER(PWM_CHn, PWM_CaptureModeInitStruct->PWM_CHn_MR)); + assert_param(IS_PWM_LR_FILTER(PWM_CHn, PWM_CaptureModeInitStruct->PWM_CHn_LR)); + assert_param(IS_PWM_CHn_UDMR(PWM_CaptureModeInitStruct->PWM_CHn_UDMR)); + assert_param(IS_PWM_CHn_PDMR(PWM_CaptureModeInitStruct->PWM_CHn_PDMR)); + assert_param(IS_PWM_CHn_CMR(PWM_CaptureModeInitStruct->PWM_CHn_CMR)); + + /* Stop PWM_CHn */ + PWM_CHn_Stop(PWM_CHn); + /* Select Timer/Counter mode as Timer mode */ + PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode; + /* Set Prescale register value */ + PWM_CHn->PR = PWM_CaptureModeInitStruct->PWM_CHn_PR; + /* Set Match register value */ + PWM_CHn->MR = PWM_CaptureModeInitStruct->PWM_CHn_MR; + /* Set Limit register value */ + PWM_CHn->LR = PWM_CaptureModeInitStruct->PWM_CHn_LR; + /* Select Up-down mode */ + PWM_CHn->UDMR = PWM_CaptureModeInitStruct->PWM_CHn_UDMR; + /* Select Periodic mode */ + PWM_CHn->PDMR = PWM_CaptureModeInitStruct->PWM_CHn_PDMR; + /* Select Capture mode */ + PWM_CHn->CMR = PWM_CaptureModeInitStruct->PWM_CHn_CMR; + /* External input enable */ + PWM_CHn->PEEER = PWM_CHn_PEEER_ExtEnable; +} + +void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + /* Stop PWM_CHn */ + PWM_CHn_Stop(PWM_CHn); + /* Select Timer/Counter mode as Timer mode */ + PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode; + /* Set Match register value */ + PWM_CHn->MR = PWM_CounterModeInitStruct->PWM_CHn_MR; + /* Set Limit register value */ + PWM_CHn->LR = PWM_CounterModeInitStruct->PWM_CHn_LR; + /* Select Up-down mode */ + PWM_CHn->UDMR = PWM_CounterModeInitStruct->PWM_CHn_UDMR; + /* Select Periodic mode */ + PWM_CHn->PDMR = PWM_CounterModeInitStruct->PWM_CHn_PDMR; + /* Select Counter mode */ + PWM_CHn->TCMR = PWM_CounterModeInitStruct->PWM_CHn_TCMR; + /* Enable external input */ + PWM_CHn->PEEER = PWM_CHn_PEEER_ExtEnable; +} + +void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_PR_FILTER(PWM_DeadzoneModeInitStruct->PWM_CHn_PR)); + assert_param(IS_PWM_MR_FILTER(PWM_CHn, PWM_DeadzoneModeInitStruct->PWM_CHn_MR)); + assert_param(IS_PWM_LR_FILTER(PWM_CHn, PWM_DeadzoneModeInitStruct->PWM_CHn_LR)); + assert_param(IS_PWM_CHn_UDMR(PWM_DeadzoneModeInitStruct->PWM_CHn_UDMR)); + assert_param(IS_PWM_CHn_PDMR(PWM_DeadzoneModeInitStruct->PWM_CHn_PDMR)); + assert_param(IS_PWM_Deadznoe(PWM_CHn)); + + /* Stop PWM_CHn */ + PWM_CHn_Stop(PWM_CHn); + /* Select Timer/Counter mode as Timer mode */ + PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode; + /* Set Prescale register value */ + PWM_CHn->PR = PWM_DeadzoneModeInitStruct->PWM_CHn_PR; + /* Set Match register value */ + PWM_CHn->MR = PWM_DeadzoneModeInitStruct->PWM_CHn_MR; + /* Set Limit register value */ + PWM_CHn->LR = PWM_DeadzoneModeInitStruct->PWM_CHn_LR; + /* Select Up-down mode */ + PWM_CHn->UDMR = PWM_DeadzoneModeInitStruct->PWM_CHn_UDMR; + /* Select Periodic mode */ + PWM_CHn->PDMR = PWM_DeadzoneModeInitStruct->PWM_CHn_PDMR; + /* Enable Dead Zone generation */ + PWM_CHn->DZER = PWM_CHn_DZER_Enable; + /* Set Dead Zone Counter */ + PWM_CHn->DZCR = PWM_DeadzoneModeInitStruct->PWM_CHn_DZCR; +} + +void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable ) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_Output(outputEnDisable)); + if( PWM_CHn->DZER ) + assert_param(IS_PWM_Deadznoe(PWM_CHn)); + + /* Stop PWM_CHn */ + PWM_CHn_Stop(PWM_CHn); + /*Config PWM output and External input */ + PWM_CHn->PEEER = outputEnDisable; +} + +void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn) +{ + PWM_CtrlPWMOutput(PWM_CHn, PWM_CHn_PEEER_PWMEnable); +} + +void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn) +{ + PWM_CtrlPWMOutput(PWM_CHn, PWM_CHn_PEEER_Disable); +} + +void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + /* Stop PWM_CHn */ + PWM_CHn_Stop(PWM_CHn); + + if(state == ENABLE) + { + if(PWM_CHn == PWM_CH0) { + PWM->IER |= PWM_IER_IE0_Enable; + } + else if(PWM_CHn == PWM_CH1) { + PWM->IER |= PWM_IER_IE1_Enable; + } + else if(PWM_CHn == PWM_CH2) { + PWM->IER |= PWM_IER_IE2_Enable; + } + else if(PWM_CHn == PWM_CH3) { + PWM->IER |= PWM_IER_IE3_Enable; + } + else if(PWM_CHn == PWM_CH4) { + PWM->IER |= PWM_IER_IE4_Enable; + } + else if(PWM_CHn == PWM_CH5) { + PWM->IER |= PWM_IER_IE5_Enable; + } + else if(PWM_CHn == PWM_CH6) { + PWM->IER |= PWM_IER_IE6_Enable; + } + else if(PWM_CHn == PWM_CH7) { + PWM->IER |= PWM_IER_IE7_Enable; + } + } + else + { + if(PWM_CHn == PWM_CH0) { + PWM->IER &= PWM_IER_IE0_Disable; + } + else if(PWM_CHn == PWM_CH1) { + PWM->IER &= PWM_IER_IE1_Disable; + } + else if(PWM_CHn == PWM_CH2) { + PWM->IER &= PWM_IER_IE2_Disable; + } + else if(PWM_CHn == PWM_CH3) { + PWM->IER &= PWM_IER_IE3_Disable; + } + else if(PWM_CHn == PWM_CH4) { + PWM->IER &= PWM_IER_IE4_Disable; + } + else if(PWM_CHn == PWM_CH5) { + PWM->IER &= PWM_IER_IE5_Disable; + } + else if(PWM_CHn == PWM_CH6) { + PWM->IER &= PWM_IER_IE6_Disable; + } + else if(PWM_CHn == PWM_CH7) { + PWM->IER &= PWM_IER_IE7_Disable; + } + } +} + +FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn) +{ + FlagStatus ret_val = RESET; + + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + if(PWM_CHn == PWM_CH0) { + ret_val = (FlagStatus)((PWM->IER & 0x01) >> 0); + } + else if(PWM_CHn == PWM_CH1) { + ret_val = (FlagStatus)((PWM->IER & 0x02) >> 1); + } + else if(PWM_CHn == PWM_CH2) { + ret_val = (FlagStatus)((PWM->IER & 0x04) >> 2); + } + else if(PWM_CHn == PWM_CH3) { + ret_val = (FlagStatus)((PWM->IER & 0x08) >> 3); + } + else if(PWM_CHn == PWM_CH4) { + ret_val = (FlagStatus)((PWM->IER & 0x10) >> 4); + } + else if(PWM_CHn == PWM_CH5) { + ret_val = (FlagStatus)((PWM->IER & 0x20) >> 5); + } + else if(PWM_CHn == PWM_CH6) { + ret_val = (FlagStatus)((PWM->IER & 0x40) >> 6); + } + else if(PWM_CHn == PWM_CH7) { + ret_val = (FlagStatus)((PWM->IER & 0x80) >> 7); + } + + return ret_val; +} + +void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + + assert_param(IS_PWM_CHn_IER(PWM_CHn_IER)); + + /* Stop PWM_CHn */ + PWM_CHn_Stop(PWM_CHn); + + if(state == ENABLE) + PWM_CHn->IER |= PWM_CHn_IER; + else + PWM_CHn->IER &= ~PWM_CHn_IER; +} + +uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->IER; +} + +uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->IR; +} + +void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR) +{ + /* Check the parameters */ + + PWM_CHn->ICR = PWM_CHn_ICR; +} + +void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + /* Set Start Stop register */ + if(PWM_CHn == PWM_CH0) { + PWM->SSR |= PWM_SSR_SS0_Start; + } + else if(PWM_CHn == PWM_CH1) { + PWM->SSR |= PWM_SSR_SS1_Start; + } + else if(PWM_CHn == PWM_CH2) { + PWM->SSR |= PWM_SSR_SS2_Start; + } + else if(PWM_CHn == PWM_CH3) { + PWM->SSR |= PWM_SSR_SS3_Start; + } + else if(PWM_CHn == PWM_CH4) { + PWM->SSR |= PWM_SSR_SS4_Start; + } + else if(PWM_CHn == PWM_CH5) { + PWM->SSR |= PWM_SSR_SS5_Start; + } + else if(PWM_CHn == PWM_CH6) { + PWM->SSR |= PWM_SSR_SS6_Start; + } + else if(PWM_CHn == PWM_CH7) { + PWM->SSR |= PWM_SSR_SS7_Start; + } +} + +void PWM_Multi_Start(uint32_t ssr_bit_flag) //complete +{ + /* Set Start Stop register */ + PWM->SSR |= ssr_bit_flag; +} + +void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Reset Start Stop register */ + if(PWM_CHn == PWM_CH0) { + PWM->SSR &= PWM_SSR_SS0_Stop; + } + else if(PWM_CHn == PWM_CH1) { + PWM->SSR &= PWM_SSR_SS1_Stop; + } + else if(PWM_CHn == PWM_CH2) { + PWM->SSR &= PWM_SSR_SS2_Stop; + } + else if(PWM_CHn == PWM_CH3) { + PWM->SSR &= PWM_SSR_SS3_Stop; + } + else if(PWM_CHn == PWM_CH4) { + PWM->SSR &= PWM_SSR_SS4_Stop; + } + else if(PWM_CHn == PWM_CH5) { + PWM->SSR &= PWM_SSR_SS5_Stop; + } + else if(PWM_CHn == PWM_CH6) { + PWM->SSR &= PWM_SSR_SS6_Stop; + } + else if(PWM_CHn == PWM_CH7) { + PWM->SSR &= PWM_SSR_SS7_Stop; + } +} + +void PWM_Multi_Stop(uint32_t ssr_bit_flag) //complete +{ + /* Reset Start Stop register */ + PWM->SSR &= ~ssr_bit_flag; +} + +void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn) +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + /* Set Pause register */ + if(PWM_CHn == PWM_CH0) { + PWM->PSR |= PWM_PSR_PS0_Pause; + } + else if(PWM_CHn == PWM_CH1) { + PWM->PSR |= PWM_PSR_PS1_Pause; + } + else if(PWM_CHn == PWM_CH2) { + PWM->PSR |= PWM_PSR_PS2_Pause; + } + else if(PWM_CHn == PWM_CH3) { + PWM->PSR |= PWM_PSR_PS3_Pause; + } + else if(PWM_CHn == PWM_CH4) { + PWM->PSR |= PWM_PSR_PS4_Pause; + } + else if(PWM_CHn == PWM_CH5) { + PWM->PSR |= PWM_PSR_PS5_Pause; + } + else if(PWM_CHn == PWM_CH6) { + PWM->PSR |= PWM_PSR_PS6_Pause; + } + else if(PWM_CHn == PWM_CH7) { + PWM->PSR |= PWM_PSR_PS7_Pause; + } +} + +void PWM_Multi_Pause(uint32_t psr_bit_flag) +{ + PWM->PSR |= psr_bit_flag; +} + +void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn) +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + /* Reset Pause register */ + if(PWM_CHn == PWM_CH0) { + PWM->PSR &= PWM_PSR_PS0_Restart; + } + else if(PWM_CHn == PWM_CH1) { + PWM->PSR &= PWM_PSR_PS1_Restart; + } + else if(PWM_CHn == PWM_CH2) { + PWM->PSR &= PWM_PSR_PS2_Restart; + } + else if(PWM_CHn == PWM_CH3) { + PWM->PSR &= PWM_PSR_PS3_Restart; + } + else if(PWM_CHn == PWM_CH4) { + PWM->PSR &= PWM_PSR_PS4_Restart; + } + else if(PWM_CHn == PWM_CH5) { + PWM->PSR &= PWM_PSR_PS5_Restart; + } + else if(PWM_CHn == PWM_CH6) { + PWM->PSR &= PWM_PSR_PS6_Restart; + } + else if(PWM_CHn == PWM_CH7) { + PWM->PSR &= PWM_PSR_PS7_Restart; + } +} + +void PWM_Multi_Restart(uint32_t psr_bit_flag) +{ + PWM->PSR &= ~psr_bit_flag; +} + + +uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->TCR; +} + +uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->PCR; +} + +uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->PR; +} + +void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_PR_FILTER(PR)); + + PWM_CHn->PR = PR; +} + +uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->MR; +} + +void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + PWM_CHn->MR = MR; +} + +uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->LR; +} + +void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + PWM_CHn->LR = LR; +} + +uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->UDMR; +} + +void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_CHn_UDMR(UDMR)); + + PWM_CHn->UDMR = UDMR; +} + +uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->TCMR; +} + +void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_CHn_TCMR(TCMR)); + + PWM_CHn->TCMR = TCMR; +} + +uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->PEEER; +} + +void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_CHn_PEEER(PEEER)); + + PWM_CHn->PEEER = PEEER; +} + +uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->CMR; +} + +void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_CHn_CMR(CMR)); + + PWM_CHn->CMR = CMR; +} + +uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn) +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->CR; +} + +uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->PDMR; +} + +void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_CHn_PDMR(PDMR)); + + PWM_CHn->PDMR = PDMR; +} + +uint32_t PWM_CHn_GetDZER(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->DZER; +} + +void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_CHn_DZER(DZER)); + + PWM_CHn->DZER = DZER; +} + +uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + + return PWM_CHn->DZCR; +} + +void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR) //complete +{ + /* Check the parameters */ + assert_param(IS_PWM_ALL_CH(PWM_CHn)); + assert_param(IS_PWM_CHn_DZCR_FILTER(DZCR)); + + PWM_CHn->DZCR = DZCR; +} + +void PWM_CH0_ClearMatchInt(void) +{ + PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_MatchInterruptClear); +} + +void PWM_CH0_ClearOverflowInt(void) +{ + PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_OverflowInterruptClear); +} + +void PWM_CH0_ClearCaptureInt(void) +{ + PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_CaptureInterruptClear); +} + +void PWM_CH1_ClearMatchInt(void) +{ + PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_MatchInterruptClear); +} + +void PWM_CH1_ClearOverflowInt(void) +{ + PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_OverflowInterruptClear); +} + +void PWM_CH1_ClearCaptureInt(void) +{ + PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_CaptureInterruptClear); +} + +void PWM_CH2_ClearMatchInt(void) +{ + PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_MatchInterruptClear); +} + +void PWM_CH2_ClearOverflowInt(void) +{ + PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_OverflowInterruptClear); +} + +void PWM_CH2_ClearCaptureInt(void) +{ + PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_CaptureInterruptClear); +} + +void PWM_CH3_ClearMatchInt(void) +{ + PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_MatchInterruptClear); +} + +void PWM_CH3_ClearOverflowInt(void) +{ + PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_OverflowInterruptClear); +} + +void PWM_CH3_ClearCaptureInt(void) +{ + PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_CaptureInterruptClear); +} + +void PWM_CH4_ClearMatchInt(void) +{ + PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_MatchInterruptClear); +} + +void PWM_CH4_ClearOverflowInt(void) +{ + PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_OverflowInterruptClear); +} + +void PWM_CH4_ClearCaptureInt(void) +{ + PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_CaptureInterruptClear); +} + +void PWM_CH5_ClearMatchInt(void) +{ + PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_MatchInterruptClear); +} + +void PWM_CH5_ClearOverflowInt(void) +{ + PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_OverflowInterruptClear); +} + +void PWM_CH5_ClearCaptureInt(void) +{ + PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_CaptureInterruptClear); +} + +void PWM_CH6_ClearMatchInt(void) +{ + PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_MatchInterruptClear); +} + +void PWM_CH6_ClearOverflowInt(void) +{ + PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_OverflowInterruptClear); +} + +void PWM_CH6_ClearCaptureInt(void) +{ + PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_CaptureInterruptClear); +} + +void PWM_CH7_ClearMatchInt(void) +{ + PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_MatchInterruptClear); +} + +void PWM_CH7_ClearOverflowInt(void) +{ + PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_OverflowInterruptClear); +} + +void PWM_CH7_ClearCaptureInt(void) +{ + PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_CaptureInterruptClear); +} diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.h new file mode 100644 index 0000000000..d3d44c376c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.h @@ -0,0 +1,289 @@ +/** + ****************************************************************************** + * @file + * @author + * @version + * @date + * @brief This file contains all the functions prototypes for the UART + * firmware library. + ****************************************************************************** + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __W7500X_PWM_H +#define __W7500X_PWM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "W7500x.h" + +/**********************************************************************************************/ +/**********************************************************************************************/ +// This structure and define must be in W7500x.h +/**********************************************************************************************/ +/**********************************************************************************************/ + +typedef struct +{ + uint32_t PWM_CHn_PEEER; +}PWM_CtrlPWMOutputTypeDef; + +typedef struct +{ + uint32_t PWM_CHn_PR; + uint32_t PWM_CHn_MR; + uint32_t PWM_CHn_LR; + uint32_t PWM_CHn_UDMR; + uint32_t PWM_CHn_PDMR; + uint32_t PWM_CHn_DZCR; +}PWM_DeadzoneModeInitTypDef; + +#define IS_PWM_ALL_CH(CHn) ((CHn == PWM_CH0) || \ + (CHn == PWM_CH1) || \ + (CHn == PWM_CH2) || \ + (CHn == PWM_CH3) || \ + (CHn == PWM_CH4) || \ + (CHn == PWM_CH5) || \ + (CHn == PWM_CH6) || \ + (CHn == PWM_CH7)) + +#define PWM_IER_IE0_Enable (0x1ul << 0) +#define PWM_IER_IE1_Enable (0x1ul << 1) +#define PWM_IER_IE2_Enable (0x1ul << 2) +#define PWM_IER_IE3_Enable (0x1ul << 3) +#define PWM_IER_IE4_Enable (0x1ul << 4) +#define PWM_IER_IE5_Enable (0x1ul << 5) +#define PWM_IER_IE6_Enable (0x1ul << 6) +#define PWM_IER_IE7_Enable (0x1ul << 7) + +#define PWM_IER_IE0_Disable ~PWM_IER_IE0_Enable +#define PWM_IER_IE1_Disable ~PWM_IER_IE1_Enable +#define PWM_IER_IE2_Disable ~PWM_IER_IE2_Enable +#define PWM_IER_IE3_Disable ~PWM_IER_IE3_Enable +#define PWM_IER_IE4_Disable ~PWM_IER_IE4_Enable +#define PWM_IER_IE5_Disable ~PWM_IER_IE5_Enable +#define PWM_IER_IE6_Disable ~PWM_IER_IE6_Enable +#define PWM_IER_IE7_Disable ~PWM_IER_IE7_Enable + +#define PWM_SSR_SS0_Start (0x1ul << 0) +#define PWM_SSR_SS1_Start (0x1ul << 1) +#define PWM_SSR_SS2_Start (0x1ul << 2) +#define PWM_SSR_SS3_Start (0x1ul << 3) +#define PWM_SSR_SS4_Start (0x1ul << 4) +#define PWM_SSR_SS5_Start (0x1ul << 5) +#define PWM_SSR_SS6_Start (0x1ul << 6) +#define PWM_SSR_SS7_Start (0x1ul << 7) + +#define PWM_SSR_SS0_Stop ~PWM_SSR_SS0_Start +#define PWM_SSR_SS1_Stop ~PWM_SSR_SS1_Start +#define PWM_SSR_SS2_Stop ~PWM_SSR_SS2_Start +#define PWM_SSR_SS3_Stop ~PWM_SSR_SS3_Start +#define PWM_SSR_SS4_Stop ~PWM_SSR_SS4_Start +#define PWM_SSR_SS5_Stop ~PWM_SSR_SS5_Start +#define PWM_SSR_SS6_Stop ~PWM_SSR_SS6_Start +#define PWM_SSR_SS7_Stop ~PWM_SSR_SS7_Start + +#define IS_SSR_BIT_FLAG(FLAG) (FLAG <= 0xFF) + +#define PWM_PSR_PS0_Pause (0x1ul << 0) +#define PWM_PSR_PS1_Pause (0x1ul << 1) +#define PWM_PSR_PS2_Pause (0x1ul << 2) +#define PWM_PSR_PS3_Pause (0x1ul << 3) +#define PWM_PSR_PS4_Pause (0x1ul << 4) +#define PWM_PSR_PS5_Pause (0x1ul << 5) +#define PWM_PSR_PS6_Pause (0x1ul << 6) +#define PWM_PSR_PS7_Pause (0x1ul << 7) + +#define PWM_PSR_PS0_Restart ~PWM_PSR_PS0_Pause +#define PWM_PSR_PS1_Restart ~PWM_PSR_PS1_Pause +#define PWM_PSR_PS2_Restart ~PWM_PSR_PS2_Pause +#define PWM_PSR_PS3_Restart ~PWM_PSR_PS3_Pause +#define PWM_PSR_PS4_Restart ~PWM_PSR_PS4_Pause +#define PWM_PSR_PS5_Restart ~PWM_PSR_PS5_Pause +#define PWM_PSR_PS6_Restart ~PWM_PSR_PS6_Pause +#define PWM_PSR_PS7_Restart ~PWM_PSR_PS7_Pause + +#define IS_PWM_PSR_BIT_FLAG(FLAG) (FLAG <= 0xFF) + +#define PWM_CHn_IER_MIE (0x1ul << 0) ///< Match Interrupt Enable +#define PWM_CHn_IER_OIE (0x1ul << 1) ///< Overflow Interrupt Enable +#define PWM_CHn_IER_CIE (0x1ul << 2) ///< Capture Interrupt Enable +#define IS_PWM_CHn_IER(FLAG) (FLAG <= 0x7) + +#define PWM_CHn_IER_MI_Msk (0x1ul << 0) ///< Match Interrupt Enable Mask +#define PWM_CHn_IER_OI_Msk (0x1ul << 1) ///< Overflow Interrupt Enable Mask +#define PWM_CHn_IER_CI_Msk (0x1ul << 2) ///< Capture Interrupt Enable Mask + +#define PWM_CHn_ICR_MatchInterruptClear (0x1ul << 0) +#define PWM_CHn_ICR_OverflowInterruptClear (0x1ul << 1) +#define PWM_CHn_ICR_CaptureInterruptClear (0x1ul << 2) +#define IS_PWM_CHn_IntClearFlag(FLAG) FLAG <= 0x7 + +/* +#define IS_PWM_STOP(CHn) (((CHn == PWM_CH0) && (PWM->SSR & PWM_SSR_SS0)) || \ + ((CHn == PWM_CH1) && (PWM->SSR & PWM_SSR_SS1)) || \ + ((CHn == PWM_CH2) && (PWM->SSR & PWM_SSR_SS2)) || \ + ((CHn == PWM_CH3) && (PWM->SSR & PWM_SSR_SS3)) || \ + ((CHn == PWM_CH4) && (PWM->SSR & PWM_SSR_SS4)) || \ + ((CHn == PWM_CH5) && (PWM->SSR & PWM_SSR_SS5)) || \ + ((CHn == PWM_CH6) && (PWM->SSR & PWM_SSR_SS6)) || \ + ((CHn == PWM_CH7) && (PWM->SSR & PWM_SSR_SS7))) +*/ + + +#define IS_PWM_PR_FILTER(MAXVAL) (MAXVAL <= 0x1F) + + +#define PWM_CHn_UDMR_UpCount (0x0ul) +#define PWM_CHn_UDMR_DownCount (0x1ul) +#define IS_PWM_CHn_UDMR(MODE) ((MODE == PWM_CHn_UDMR_UpCount) || \ + (MODE == PWM_CHn_UDMR_DownCount)) + +#define PWM_CHn_TCMR_TimerMode (0x0ul) +#define PWM_CHn_TCMR_RisingCounterMode (0x1ul) +#define PWM_CHn_TCMR_FallingCounterMode (0x2ul) +#define PWM_CHn_TCMR_BothCounterMode (0x3ul) +#define IS_PWM_CHn_TCMR(MODE) ((MODE == PWM_CHn_TCMR_RisingCounterMode) || \ + (MODE == PWM_CHn_TCMR_FallingCounterMode) || \ + (MODE == PWM_CHn_TCMR_BothCounterMode)) + +#define PWM_CHn_PEEER_Disable (0x0ul) +#define PWM_CHn_PEEER_ExtEnable (0x1ul) +#define PWM_CHn_PEEER_PWMEnable (0x2ul) +#define IS_PWM_CHn_PEEER(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \ + (ENABLE == PWM_CHn_PEEER_ExtEnable) || \ + (ENABLE == PWM_CHn_PEEER_PWMEnable)) + +#define IS_PWM_Output(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \ + (ENABLE == PWM_CHn_PEEER_PWMEnable)) + +#define PWM_CHn_CMR_RisingEdge 0x0ul +#define PWM_CHn_CMR_FallingEdge 0x1ul +#define IS_PWM_CHn_CMR(MODE) ((MODE == PWM_CHn_CMR_RisingEdge) || \ + (MODE == PWM_CHn_CMR_FallingEdge)) + +#define PWM_CHn_PDMR_Oneshot (0x0ul) +#define PWM_CHn_PDMR_Periodic (0x1ul) +#define IS_PWM_CHn_PDMR(MODE) ((MODE == PWM_CHn_PDMR_Periodic) || \ + (MODE == PWM_CHn_PDMR_Oneshot)) + +#define PWM_CHn_DZER_Enable (0x1ul) +#define PWM_CHn_DZER_Disable (0x0ul) +#define PWM_CHn_DZER(ENABLE) ((ENABLE == PWM_CHn_DZER_Enable) || \ + (ENABLE == PWM_CHn_DZER_Disable)) + +#define IS_PWM_Deadznoe(CHn) (((CHn == PWM_CH0) && (PWM_CH1->DZER == PWM_CHn_DZER_Disable)) || \ + ((CHn == PWM_CH1) && (PWM_CH0->DZER == PWM_CHn_DZER_Disable)) || \ + ((CHn == PWM_CH2) && (PWM_CH3->DZER == PWM_CHn_DZER_Disable)) || \ + ((CHn == PWM_CH3) && (PWM_CH2->DZER == PWM_CHn_DZER_Disable)) || \ + ((CHn == PWM_CH4) && (PWM_CH5->DZER == PWM_CHn_DZER_Disable)) || \ + ((CHn == PWM_CH5) && (PWM_CH4->DZER == PWM_CHn_DZER_Disable)) || \ + ((CHn == PWM_CH6) && (PWM_CH7->DZER == PWM_CHn_DZER_Disable)) || \ + ((CHn == PWM_CH7) && (PWM_CH6->DZER == PWM_CHn_DZER_Disable))) + +#define IS_PWM_CHn_DZCR_FILTER(MAXVAL) (MAXVAL <= 0x3FF) + + + + + + +void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn); +void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct); +void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct); +void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct); +void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct); +void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable ); +void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn) ; +void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn) ; +void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state); +FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state); +void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn); +void PWM_Multi_Start(uint32_t ssr_bit_flag); +void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn); +void PWM_Multi_Stop(uint32_t ssr_bit_flag); +void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn); +void PWM_Multi_Pause(uint32_t psr_bit_flag); +void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn); +void PWM_Multi_Restart(uint32_t psr_bit_flag); +uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn); +uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR); +uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn); +uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn); +uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR); +uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR); +uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR); +uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR); +uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR); +uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER); +uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR); +uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn); +uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR); +void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER); +uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn); +void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR); +void PWM_CH0_ClearMatchInt(void); +void PWM_CH0_ClearOverflowInt(void); +void PWM_CH0_ClearCaptureInt(void); +void PWM_CH1_ClearMatchInt(void); +void PWM_CH1_ClearOverflowInt(void); +void PWM_CH1_ClearCaptureInt(void); +void PWM_CH2_ClearMatchInt(void); +void PWM_CH2_ClearOverflowInt(void); +void PWM_CH2_ClearCaptureInt(void); +void PWM_CH3_ClearMatchInt(void); +void PWM_CH3_ClearOverflowInt(void); +void PWM_CH3_ClearCaptureInt(void); +void PWM_CH4_ClearMatchInt(void); +void PWM_CH4_ClearOverflowInt(void); +void PWM_CH4_ClearCaptureInt(void); +void PWM_CH5_ClearMatchInt(void); +void PWM_CH5_ClearOverflowInt(void); +void PWM_CH5_ClearCaptureInt(void); +void PWM_CH6_ClearMatchInt(void); +void PWM_CH6_ClearOverflowInt(void); +void PWM_CH6_ClearCaptureInt(void); +void PWM_CH7_ClearMatchInt(void); +void PWM_CH7_ClearOverflowInt(void); +void PWM_CH7_ClearCaptureInt(void); + + +void PWM0_Handler(void); +void PWM1_Handler(void); +void PWM2_Handler(void); +void PWM3_Handler(void); +void PWM4_Handler(void); +void PWM5_Handler(void); +void PWM6_Handler(void); +void PWM7_Handler(void); + + + + +//Temporary macro======= +#define PWM_CH(N) ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + (N * 0x100UL))) +//====================== + + +#ifdef __cplusplus +} +#endif + + +#endif //__W7500X_PWM_H + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.c b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.c new file mode 100644 index 0000000000..67eba2e88d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.c @@ -0,0 +1,370 @@ +/** + ****************************************************************************** + * @file W7500x_uart.c + * @author + * @version + * @date + * @brief + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "W7500x.h" + +void UART_StructInit(UART_InitTypeDef* UART_InitStruct) +{ + /* UART_InitStruct members default value */ + UART_InitStruct->UART_BaudRate = 115200; + UART_InitStruct->UART_WordLength = UART_WordLength_8b ; + UART_InitStruct->UART_StopBits = UART_StopBits_1; + UART_InitStruct->UART_Parity = UART_Parity_No ; + UART_InitStruct->UART_Mode = UART_Mode_Rx | UART_Mode_Tx; + UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None ; +} + +void UART_DeInit(UART_TypeDef *UARTx) +{ + +} + +uint32_t UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct) +{ + float baud_divisor; + uint32_t tmpreg=0x00, uartclock=0x00; + uint32_t integer_baud = 0x00, fractional_baud = 0x00; + + assert_param(IS_UART_01_PERIPH(UARTx)); + assert_param(IS_UART_WORD_LENGTH(UART_InitStruct->UART_WordLength)); + assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity)); + assert_param(IS_UART_STOPBITS(UART_InitStruct->UART_StopBits)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(UART_InitStruct->UART_HardwareFlowControl)); + assert_param(IS_UART_MODE(UART_InitStruct->UART_Mode)); + + + UARTx->CR &= ~(UART_CR_UARTEN); + + // Set baudrate + CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_RCLK; // Set UART Clock using internal Oscilator ( 8MHz ) + uartclock = (8000000UL) / (1 << CRG->UARTCLK_PVSR); + + baud_divisor = ((float)uartclock / (16 * UART_InitStruct->UART_BaudRate)); + integer_baud = (uint32_t)baud_divisor; + fractional_baud = (uint32_t)((baud_divisor - integer_baud) * 64 + 0.5); + + UARTx->IBRD = integer_baud; + UARTx->FBRD = fractional_baud; + + + tmpreg = UARTx->LCR_H; + tmpreg &= ~(0x00EE); + tmpreg |= (UART_InitStruct->UART_WordLength | UART_InitStruct->UART_StopBits | UART_InitStruct->UART_Parity); + UARTx->LCR_H |= tmpreg; + + tmpreg = UARTx->CR; + tmpreg &= ~(UART_CR_CTSEn | UART_CR_RTSEn | UART_CR_RXE | UART_CR_TXE | UART_CR_UARTEN); + tmpreg |= (UART_InitStruct->UART_Mode | UART_InitStruct->UART_HardwareFlowControl); + UARTx->CR |= tmpreg; + + UARTx->CR |= UART_CR_UARTEN; + + return 0; +} + + +void UART_SendData(UART_TypeDef* UARTx, uint16_t Data) +{ + assert_param(IS_UART_01_PERIPH(UARTx)); + + UARTx->DR = Data; +} + + +uint16_t UART_ReceiveData(UART_TypeDef* UARTx) +{ + assert_param(IS_UART_01_PERIPH(UARTx)); + + return (uint16_t)(UARTx->DR); +} + + +void UART_SendBreak(UART_TypeDef* UARTx) +{ + assert_param(IS_UART_01_PERIPH(UARTx)); + + UARTx->LCR_H |= UART_LCR_H_BRK; +} + + +FlagStatus UART_GetRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS) +{ + FlagStatus bitstatus = RESET; + + assert_param(IS_UART_01_PERIPH(UARTx)); + assert_param(IS_UART_RECV_STATUS(UART_RECV_STATUS)); + + if( (UARTx->STATUS.RSR & UART_RECV_STATUS) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + +void UART_ClearRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS) +{ + assert_param(IS_UART_01_PERIPH(UARTx)); + assert_param(IS_UART_RECV_STATUS(UART_RECV_STATUS)); + + UARTx->STATUS.ECR = (uint16_t)UART_RECV_STATUS; +} + + +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG) +{ + FlagStatus bitstatus = RESET; + + assert_param(IS_UART_01_PERIPH(UARTx)); + assert_param(IS_UART_FLAG(UART_FLAG)); + + if ((UARTx->FR & UART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; + +} + +/* +void UART_ClearFlag(UART_TypeDef* UARTx, uint16_t UART_FLAG) +{ + +} +*/ + +void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState) +{ + assert_param(IS_UART_01_PERIPH(UARTx)); + assert_param(IS_UART_IT_FLAG(UART_IT)); + + if ( NewState != DISABLE ) + { + UARTx->IMSC |= UART_IT; + } + else + { + UARTx->ICR |= UART_IT; + } +} + + +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT) +{ + ITStatus bitstatus = RESET; + + assert_param(IS_UART_01_PERIPH(UARTx)); + assert_param(IS_UART_IT_FLAG(UART_IT)); + + if ((UARTx->MIS & UART_IT) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT) +{ + assert_param(IS_UART_01_PERIPH(UARTx)); + assert_param(IS_UART_IT_FLAG(UART_IT)); + + UARTx->ICR |= UART_IT; +} + + +void S_UART_DeInit() +{ + +} + +uint32_t S_UART_Init(uint32_t baud) +{ + uint32_t tmpreg=0x00; + uint32_t uartclock = 0x00, integer_baud = 0x00; + + assert_param(IS_UART_MODE(S_UART_InitStruct->UART_Mode)); + + if(CRG->FCLK_SSR == CRG_FCLK_SSR_RCLK) + { + uartclock = INTERN_XTAL; + } + else if(CRG->FCLK_SSR == CRG_FCLK_SSR_OCLK) + { + uartclock = EXTERN_XTAL; + } + else + { + uartclock = GetSystemClock(); + } + + integer_baud = (uint32_t)(uartclock / baud); + UART2->BAUDDIV = integer_baud; + + tmpreg = UART2->CTRL; + tmpreg &= ~(S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN); + tmpreg |= (S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN); + UART2->CTRL = tmpreg; + + return 0; +} + +void S_UART_SendData(uint16_t Data) +{ + while(UART2->STATE & S_UART_STATE_TX_BUF_FULL); + UART2->DATA = Data; +} + +uint16_t S_UART_ReceiveData() +{ + return (uint16_t)(UART2->DATA); +} + + +FlagStatus S_UART_GetFlagStatus(uint16_t S_UART_FLAG) +{ + FlagStatus bitstatus = RESET; + + assert_param(IS_S_UART_FLAG(S_UART_FLAG)); + + if ((UART2->STATE & S_UART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + +void S_UART_ITConfig(uint16_t S_UART_IT, FunctionalState NewState) +{ + assert_param(IS_S_UART_IT_FLAG(S_UART_IT)); + + if ( NewState != DISABLE ) + { + UART2->CTRL |= S_UART_IT; + } + else + { + UART2->CTRL &= ~(S_UART_IT); + } +} + +ITStatus S_UART_GetITStatus(uint16_t S_UART_IT) +{ + ITStatus bitstatus = RESET; + + assert_param(IS_S_UART_IT_FLAG(S_UART_IT)); + + if ((UART2->INT.STATUS & (S_UART_IT >> 2)) != (uint16_t) RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +void S_UART_ClearITPendingBit(uint16_t S_UART_IT) +{ + assert_param(IS_S_UART_IT_FLAG(S_UART_IT)); + + UART2->INT.CLEAR |= (S_UART_IT >> 2); +} + + +/**************************************************/ +// It will be moved to application board's driver */ +/**************************************************/ +uint8_t UartPutc(UART_TypeDef* UARTx, uint8_t ch) +{ + UART_SendData(UARTx,ch); + + while(UARTx->FR & UART_FR_BUSY); + + return (ch); +} + +void UartPuts(UART_TypeDef* UARTx, uint8_t *str) +{ + uint8_t ch; + + do{ + ch = *str; + if(ch != (uint8_t)0x0) + { + UartPutc(UARTx, ch); + } + *str++; + }while(ch != 0); +} + +uint8_t UartGetc(UART_TypeDef* UARTx) +{ + while(UARTx->FR & UART_FR_RXFE); + + return (UARTx->DR & 0xFF); +} + + +uint8_t S_UartPutc(uint8_t ch) +{ + S_UART_SendData(ch); + + return (ch); +} + +void S_UartPuts(uint8_t *str) +{ + uint8_t ch; + + do{ + ch = *str; + if(ch != (uint8_t)0x0) + { + S_UART_SendData(ch); + } + *str++; + }while(ch != 0); +} + +uint8_t S_UartGetc() +{ + while( (UART2->STATE & S_UART_STATE_RX_BUF_FULL) == 0 ); + return (uint8_t)S_UART_ReceiveData(); +} + + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.h b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.h new file mode 100644 index 0000000000..791978b237 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.h @@ -0,0 +1,289 @@ +/** + ****************************************************************************** + * @file + * @author + * @version + * @date + * @brief This file contains all the functions prototypes for the UART + * firmware library. + ****************************************************************************** + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __W7500X_UART_H +#define __W7500X_UART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "W7500x.h" + + +/** + * @brief UART Init Structure definition + */ + +typedef struct +{ + uint32_t UART_BaudRate; + uint16_t UART_WordLength; + uint16_t UART_StopBits; + uint16_t UART_Parity; + uint16_t UART_Mode; + uint16_t UART_HardwareFlowControl; +} UART_InitTypeDef; + +/** + * @} + */ + + +/** @defgroup UART_Exported_Constants + * @{ + */ + +#define IS_UART_01_PERIPH(PERIPH) (((PERIPH) == UART0) || ((PERIPH) == UART1)) +#define IS_UART_2_PERIPH(PERIPH) ((PERIPH) == UART2) + +/** + * @} + */ + + + +/** @addtogroup UART_Word_Length + * @{ + */ + +#define UART_WordLength_8b ((uint16_t)UART_LCR_H_WLEN(3)) +#define UART_WordLength_7b ((uint16_t)UART_LCR_H_WLEN(2)) +#define UART_WordLength_6b ((uint16_t)UART_LCR_H_WLEN(1)) +#define UART_WordLength_5b ((uint16_t)UART_LCR_H_WLEN(0)) +#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WordLength_8b) || \ + ((LENGTH) == UART_WordLength_7b) || \ + ((LENGTH) == UART_WordLength_6b) || \ + ((LENGTH) == UART_WordLength_5b) ) +/** + * @} + */ + + +/** @addtogroup UART_Parity + * @{ + */ + +#define UART_Parity_No ((uint16_t)0x0000) +#define UART_Parity_Even ((uint16_t)(UART_LCR_H_PEN | UART_LCR_H_EPS)) +#define UART_Parity_Odd ((uint16_t)(UART_LCR_H_PEN)) +#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_No) || \ + ((PARITY) == UART_Parity_Even) || \ + ((PARITY) == UART_Parity_Odd)) + +/** + * @} + */ + + +/** @addtogroup UART_Stop_Bits + * @{ + */ + +#define UART_StopBits_1 ((uint16_t)0x0000) +#define UART_StopBits_2 ((uint16_t)(UART_LCR_H_STP2)) +#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_StopBits_1) || \ + ((STOPBITS) == UART_StopBits_2)) +/** + * @} + */ + + +/** @addtogroup UART_Mode + * @{ + */ + +#define UART_Mode_Rx ((uint16_t)(UART_CR_RXE)) +#define UART_Mode_Tx ((uint16_t)(UART_CR_TXE)) +#define IS_UART_MODE(MODE) (((MODE) == UART_Mode_Rx) || \ + ((MODE) == UART_Mode_Tx)) + +/** + * @} + */ + + +/** @addtogroup UART_Hardware_Flow_Control + * @{ + */ + +#define UART_HardwareFlowControl_None ((uint16_t)0x0000) +#define UART_HardwareFlowControl_RTS ((uint16_t)UART_CR_RTSEn) +#define UART_HardwareFlowControl_CTS ((uint16_t)UART_CR_CTSEn) +#define UART_HardwareFlowControl_RTS_CTS ((uint16_t)(UART_CR_RTSEn | UART_CR_CTSEn)) +#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL) \ + (((CONTROL) == UART_HardwareFlowControl_None) || \ + ((CONTROL) == UART_HardwareFlowControl_RTS) || \ + ((CONTROL) == UART_HardwareFlowControl_CTS) || \ + ((CONTROL) == UART_HardwareFlowControl_RTS_CTS)) +/** + * @} + */ + + +/** @addtogroup UART_Receive Status + * @{ + */ + +#define UART_RECV_STATUS_OE ((uint16_t)0x01UL << 3) /*!< Overrun error */ +#define UART_RECV_STATUS_BE ((uint16_t)0x01UL << 2) /*!< Break error */ +#define UART_RECV_STATUS_PE ((uint16_t)0x01UL << 1) /*!< Parity error */ +#define UART_RECV_STATUS_FE ((uint16_t)0x01UL << 0) /*!< Framing error */ +#define IS_UART_RECV_STATUS(FLAG) (((FLAG) == UART_RECV_STATUS_OE) || ((FLAG) == UART_RECV_STATUS_BE) || \ + ((FLAG) == UART_RECV_STATUS_PE) || ((FLAG) == UART_RECV_STATUS_FE)) +/** + * @} + */ + + + +/** @addtogroup UART_Flags + * @{ + */ + +#define UART_FLAG_RI ((uint16_t)0x01UL << 8) /*!< Ring indicator */ +#define UART_FLAG_TXFE ((uint16_t)0x01UL << 7) /*!< Transmit FIFO empty */ +#define UART_FLAG_RXFF ((uint16_t)0x01UL << 6) /*!< Receive FIFO full */ +#define UART_FLAG_TXFF ((uint16_t)0x01UL << 5) /*!< Transmit FIFO full */ +#define UART_FLAG_RXFE ((uint16_t)0x01UL << 4) /*!< Receive FIFO empty */ +#define UART_FLAG_BUSY ((uint16_t)0x01UL << 3) /*!< UART busy */ +#define UART_FLAG_DCD ((uint16_t)0x01UL << 2) /*!< Data carrier detect */ +#define UART_FLAG_DSR ((uint16_t)0x01UL << 1) /*!< Data set ready */ +#define UART_FLAG_CTS ((uint16_t)0x01UL << 0) /*!< Clear to send */ +#define IS_UART_FLAG(FLAG) (((FLAG) == UART_FLAG_RI) || ((FLAG) == UART_FLAG_TXFE) || \ + ((FLAG) == UART_FLAG_RXFF) || ((FLAG) == UART_FLAG_TXFF) || \ + ((FLAG) == UART_FLAG_RXFE) || ((FLAG) == UART_FLAG_BUSY) || \ + ((FLAG) == UART_FLAG_DCD) || ((FLAG) == UART_FLAG_DSR) || \ + ((FLAG) == UART_FLAG_CTS)) + +/** + * @} + */ + + +/** @addtogroup UART_IT_Flags + * @{ + */ + +#define UART_IT_FLAG_OEI ((uint16_t)0x01UL << 10) /*!< Overrun error interrupt */ +#define UART_IT_FLAG_BEI ((uint16_t)0x01UL << 9) /*!< Break error interrupt */ +#define UART_IT_FLAG_PEI ((uint16_t)0x01UL << 8) /*!< Parity error interrupt */ +#define UART_IT_FLAG_FEI ((uint16_t)0x01UL << 7) /*!< Framing error interrupt */ +#define UART_IT_FLAG_RTI ((uint16_t)0x01UL << 6) /*!< Receive timeout interrupt */ +#define UART_IT_FLAG_TXI ((uint16_t)0x01UL << 5) /*!< Transmit interrupt */ +#define UART_IT_FLAG_RXI ((uint16_t)0x01UL << 4) /*!< Receive interrupt */ +#define UART_IT_FLAG_DSRMI ((uint16_t)0x01UL << 3) /*!< UARTDSR modem interrupt */ +#define UART_IT_FLAG_DCDMI ((uint16_t)0x01UL << 2) /*!< UARTDCD modem interrupt */ +#define UART_IT_FLAG_CTSMI ((uint16_t)0x01UL << 1) /*!< UARTCTS modem interrupt */ +#define UART_IT_FLAG_RIMI ((uint16_t)0x01UL << 0) /*!< UARTRI modem interrupt */ +#define IS_UART_IT_FLAG(FLAG) (((FLAG) == UART_IT_FLAG_OEI) || ((FLAG) == UART_IT_FLAG_BEI) || \ + ((FLAG) == UART_IT_FLAG_PEI) || ((FLAG) == UART_IT_FLAG_FEI) || \ + ((FLAG) == UART_IT_FLAG_RTI) || ((FLAG) == UART_IT_FLAG_TXI) || \ + ((FLAG) == UART_IT_FLAG_RXI) || ((FLAG) == UART_IT_FLAG_DSRMI) || \ + ((FLAG) == UART_IT_FLAG_DCDMI)|| ((FLAG) == UART_IT_FLAG_CTSMI) || \ + ((FLAG) == UART_IT_FLAG_RIMI)) +/** + * @} + */ +/** @addtogroup UART_FIFO_Level Select + * @{ + */ + +#define UART_IFLS_RXIFLSEL7_8 ((uint16_t)(UART_IFLS_RXIFLSEL(4))) +#define UART_IFLS_RXIFLSEL3_4 ((uint16_t)(UART_IFLS_RXIFLSEL(3))) +#define UART_IFLS_RXIFLSEL1_2 ((uint16_t)(UART_IFLS_RXIFLSEL(2))) +#define UART_IFLS_RXIFLSEL1_4 ((uint16_t)(UART_IFLS_RXIFLSEL(1))) +#define UART_IFLS_RXIFLSEL1_8 ((uint16_t)(UART_IFLS_RXIFLSEL(0))) +#define UART_IFLS_TXIFLSEL7_8 ((uint16_t)(UART_IFLS_TXIFLSEL(4))) +#define UART_IFLS_TXIFLSEL3_4 ((uint16_t)(UART_IFLS_TXIFLSEL(3))) +#define UART_IFLS_TXIFLSEL1_2 ((uint16_t)(UART_IFLS_TXIFLSEL(2))) +#define UART_IFLS_TXIFLSEL1_4 ((uint16_t)(UART_IFLS_TXIFLSEL(1))) +#define UART_IFLS_TXIFLSEL1_8 ((uint16_t)(UART_IFLS_TXIFLSEL(0))) + +#define IS_UART_FIFO_Level(FLAG) (((FLAG) == UART_IFLS_RXIFLSEL7_8) || ((FLAG) == UART_IFLS_RXIFLSEL3_4)|| \ + ((FLAG) == UART_IFLS_RXIFLSEL1_2)|| ((FLAG) == UART_IFLS_RXIFLSEL1_4)|| ((FLAG) == UART_IFLS_RXIFLSEL1_8)||\ + ((FLAG) == UART_IFLS_TXIFLSEL7_8)|| ((FLAG) == UART_IFLS_TXIFLSEL3_4)|| \ + ((FLAG) == UART_IFLS_TXIFLSEL1_2)|| ((FLAG) == UART_IFLS_TXIFLSEL1_4)||((FLAG) == UART_IFLS_TXIFLSEL1_8)) + +/** + * @} + */ + +/** @addtogroup S_UART_Flags + * @{ + */ +#define S_UART_FLAG_RXO ((uint16_t)0x01UL << 3) /*!< RX buffer Overrun */ +#define S_UART_FLAG_TXO ((uint16_t)0x01UL << 2) /*!< TX buffer Overrun */ +#define S_UART_FLAG_RXF ((uint16_t)0x01UL << 1) /*!< RX buffer Full */ +#define S_UART_FLAG_TXF ((uint16_t)0x01UL << 0) /*!< TX buffer Full */ +#define IS_S_UART_FLAG(FLAG) (((FLAG) == S_UART_FLAG_RXO) || ((FLAG) == S_UART_FLAG_TXO) || \ + ((FLAG) == S_UART_FLAG_RXF) || ((FLAG) == S_UART_FLAG_TXF)) +/** + * @} + */ + + +/** @addtogroup S_UART_IT_Flags + * @{ + */ + +#define S_UART_IT_FLAG_RXOI ((uint16_t)0x01UL << 5) /*!< RX overrun interrupt */ +#define S_UART_IT_FLAG_TXOI ((uint16_t)0x01UL << 4) /*!< TX overrun interrupt */ +#define S_UART_IT_FLAG_RXI ((uint16_t)0x01UL << 3) /*!< RX interrupt */ +#define S_UART_IT_FLAG_TXI ((uint16_t)0x01UL << 2) /*!< TX interrupt */ +#define IS_S_UART_IT_FLAG(FLAG) (((FLAG) == S_UART_IT_FLAG_RXOI) || ((FLAG) == S_UART_IT_FLAG_TXOI) || \ + ((FLAG) == S_UART_IT_FLAG_RXI) || ((FLAG) == S_UART_IT_FLAG_TXI)) + +/** + * @} + */ + + +void UART_StructInit (UART_InitTypeDef* UART_InitStruct); + +uint32_t UART_Init (UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct); +void UART_SendData (UART_TypeDef* UARTx, uint16_t Data); +uint16_t UART_ReceiveData (UART_TypeDef* UARTx); +void UART_SendBreak (UART_TypeDef* UARTx); +void UART_ClearRecvStatus (UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS); +FlagStatus UART_GetFlagStatus (UART_TypeDef* UARTx, uint16_t UART_FLAG); +void UART_ITConfig (UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState); +ITStatus UART_GetITStatus (UART_TypeDef* UARTx, uint16_t UART_IT); +void UART_ClearITPendingBit (UART_TypeDef* UARTx, uint16_t UART_IT); + + +void S_UART_DeInit(void); +uint32_t S_UART_Init(uint32_t baud); +void S_UART_SendData(uint16_t Data); +uint16_t S_UART_ReceiveData(void); + + + +uint8_t UartPutc (UART_TypeDef* UARTx, uint8_t ch); +void UartPuts (UART_TypeDef* UARTx, uint8_t *str); +uint8_t UartGetc (UART_TypeDef* UARTx); + +uint8_t S_UartPutc(uint8_t ch); +void S_UartPuts(uint8_t *str); +uint8_t S_UartGetc(void); + + +#ifdef __cplusplus +} +#endif + + +#endif // __W7500X_UART_H + diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h new file mode 100644 index 0000000000..9a5d507fa7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h @@ -0,0 +1,26 @@ +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + + +//*** ADC *** +extern const PinMap PinMap_ADC[]; + +//*** SERIAL *** +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +//*** I2C *** +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + + +//*** SPI *** + +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralNames.h new file mode 100644 index 0000000000..e0bacfc987 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralNames.h @@ -0,0 +1,77 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PinNames.h" +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_0 = (int)W7500x_ADC_BASE +} ADCName; + +typedef enum { + UART_0 = (int)W7500x_UART0_BASE, + UART_1 = (int)W7500x_UART1_BASE +} UARTName; + +#define STDIO_UART_TX PC_2 +#define STDIO_UART_RX PC_3 +#define STDIO_UART UART_1 + +typedef enum { + SPI_0 = (int)SSP0_BASE, + SPI_1 = (int)SSP1_BASE +} SPIName; + +typedef enum { + I2C_0 = (int)I2C0_BASE, + I2C_1 = (int)I2C1_BASE +} I2CName; + +typedef enum { + PWM_1 = 0 +// PWM_1 = (int)TIM1_BASE, +// PWM_3 = (int)TIM3_BASE, +// PWM_14 = (int)TIM14_BASE, +// PWM_15 = (int)TIM15_BASE, +// PWM_16 = (int)TIM16_BASE, +// PWM_17 = (int)TIM17_BASE +} PWMName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c new file mode 100644 index 0000000000..136a93f8cb --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c @@ -0,0 +1,106 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" +#include "PeripheralNames.h" +#include "pinmap.h" + + +//*** ADC *** +const PinMap PinMap_ADC[] = { + {PC_15, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN0 + {PC_14, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN1 + {PC_13, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN2 + {PC_12, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN3 + {PC_11, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN4 + {PC_10, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN5 + {NC, NC, 0} +}; + + +//*** SERIAL *** +const PinMap PinMap_UART_TX[] = { + {PA_14, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {PC_2, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_13, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {PC_3, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {NC, NC, 0} +}; + +//*** I2C *** +const PinMap PinMap_I2C_SDA[] = { + {PA_10, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_SCLK[] = { + {PA_6 , SPI_0, 0}, + {PB_1 , SPI_1, 0}, + {PC_12, SPI_0, 3}, + {PA_12, SPI_1, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {PA_8 , SPI_0, 0}, + {PB_3 , SPI_1, 0}, + {PC_10, SPI_0, 3}, + {PA_14, SPI_1, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_7 , SPI_0, 0}, + {PB_2 , SPI_1, 0}, + {PC_11, SPI_0, 3}, + {PA_13, SPI_1, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_5 , SPI_0, 0}, + {PB_0 , SPI_1, 0}, + {PC_13, SPI_0, 3}, + {PA_11, SPI_1, 3}, + {NC , NC , 0} +}; + diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PinNames.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PinNames.h new file mode 100644 index 0000000000..5233ccec2d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PinNames.h @@ -0,0 +1,197 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +// See W7500x_hal_gpio.h for values of MODE, PUPD and AFNUM +#define WIZ_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 8) | ((PUPD) << 4) | ((MODE) << 0))) +#define WIZ_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define WIZ_PIN_PUPD(X) (((X) >> 4) & 0x0F) +#define WIZ_PIN_AFNUM(X) (((X) >> 8) & 0x0F) +#define WIZ_MODE_INPUT (0) +#define WIZ_MODE_OUTPUT (1) +#define WIZ_MODE_AF (2) + +#define WIZ_GPIO_NOPULL (0) /*!< No Pull-up or Pull-down activation */ +#define WIZ_GPIO_PULLDOWN (1) /*!< Pull-down activation */ +#define WIZ_GPIO_PULLUP (2) /*!< Pull-up activation */ +#define WIZ_GPIO_OPEN_DRAIN (3) /*!< Open Drain activation */ + + +#define WIZ_AFNUM(X)(((uint32_t)(X) >> 8) & 0xF) // AF number (0=AF0, 1=AF1, 2=AF2, 3=AF3) +#define WIZ_PORT(X) (((uint32_t)(X) >> 4) & 0xF) // port number (0=A, 1=B, 2=C, 3=D) +#define WIZ_PIN(X) ((uint32_t)(X) & 0xF) // pin number + + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + + +typedef enum { + // W7500x Pin Names (AF[9:8] + PORT[5:4] + PIN[3:0]) + + PA_0 = 0x000, + PA_1 = 0x001, + PA_2 = 0x002, + PA_3 = 0x003, + PA_4 = 0x004, + PA_5 = 0x005, + PA_6 = 0x006, + PA_7 = 0x007, + PA_8 = 0x008, + PA_9 = 0x009, + PA_10 = 0x00A, + PA_11 = 0x00B, + PA_12 = 0x00C, + PA_13 = 0x00D, + PA_14 = 0x00E, + PA_15 = 0x00F, + + PB_0 = 0x010, //SSEL1/SD_SEL + PB_1 = 0x011, //SCLK1/SD_CLK + PB_2 = 0x012, //MISO1/SD_MISO + PB_3 = 0x013, //MOSI1/SD_MOSI + PB_4 = 0x014, + PB_5 = 0x015, + PB_6 = 0x016, + PB_7 = 0x017, + PB_8 = 0x018, + PB_9 = 0x019, + PB_10 = 0x01A, + PB_11 = 0x01B, + PB_12 = 0x01C, + PB_13 = 0x01D, + PB_14 = 0x01E, + PB_15 = 0x01F, + + PC_0 = 0x120, // 0xx:U_CTS1, 1xx:GPIOC_0, 2xx:PWM0 + PC_1 = 0x121, // 0xx:U_RTS1, 1xx:GPIOC_1, 2xx:PWM1 + PC_2 = 0x022, + PC_3 = 0x023, + PC_4 = 0x124, // 0xx:SDA1, 1xx:GPIOC_4, 2xx:PWM4 + PC_5 = 0x025, + PC_6 = 0x026, + PC_7 = 0x027, + PC_8 = 0x128, // 0xx:PWM0, 1xx:GPIOC_8, 2xx:SCL0, 3xx:AIN7 + PC_9 = 0x129, // 0xx:PWM1, 1xx:GPIOC_9, 2xx:SDA0, 3xx:AIN6 + + PC_10 = 0x32A, // 0xx:U_TXD2, 1xx:GPIOC_10, 2xx:PWM2, 3xx:AIN5 + PC_11 = 0x32B, // 0xx:U_RXD2, 1xx:GPIOC_11, 2xx:PWM3, 3xx:AIN4 + PC_12 = 0x32C, // 0xx:AIN3, 1xx:GPIOC_12, 2xx:SSEL0, 3xx:AIN3 + PC_13 = 0x32D, // 0xx:AIN2, 1xx:GPIOC_13, 2xx:SCLK0, 3xx:AIN2 + PC_14 = 0x32E, // 0xx:AIN1, 1xx:GPIOC_14, 2xx:MISO0, 3xx:AIN1 + PC_15 = 0x32F, // 0xx:AIN0, 1xx:GPIOC_15, 2xx:MOSI0, 3xx:AIN0 + + PD_0 = 0x030, + PD_1 = 0x031, + PD_2 = 0x032, + PD_3 = 0x033, + PD_4 = 0x034, + + + // Arduino connector namings + A0 = PC_15, // AIN0 + A1 = PC_14, // AIN1 + A2 = PC_13, // AIN2 + A3 = PC_12, // AIN3 + A4 = PC_11, // AIN4 + A5 = PC_10, // AIN5 + D0 = PA_14, // U_TXD0 + D1 = PA_13, // U_RXD0 + D2 = PC_1, // GPIOC_1, EXTI + D3 = PC_0, // GPIOC_0, EXTI + D4 = PA_2, // GPIOA_2, + D5 = PA_1, // GPIOA_1, + D6 = PA_0, // GPIOA_0, + D7 = PC_6, // GPIOC_6, EXTI + D8 = PC_7, // GPIOC_7, EXTI + D9 = PC_4, // GPIOC_4, EXTI + D10 = PA_5, // SSEL0 + D11 = PA_8, // MOSI0 + D12 = PA_7, // MISO0 + D13 = PA_6, // SCLK0 + D14 = PA_10, // SDA0 + D15 = PA_9, // SCL0 + + // Generic signals namings + LED_RED = PC_8, + LED_GREEN = PC_9, + LED_BLUE = PC_5, + + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + LED4 = LED_BLUE, + +// USER_BUTTON = PC_13, + SERIAL_TX = PC_2, // U_TXD1 + SERIAL_RX = PC_3, // U_RXD1 + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + I2C_SCL = PA_9, // SCL0 + I2C_SDA = PA_10, // SDA0 + SPI_MOSI = PA_8, // MISO0 + SPI_MISO = PA_7, // MOSI0 + SPI_SCK = PA_9, // SCL0 + SPI_CS = PA_5, // SSEL0 + SD_SEL = PB_0, // SSEL1 + SD_CLK = PB_1, // SCL1 + SD_MISO = PB_2, // MOSI1 + SD_MOSI = PB_3, // MISO1 +// PWM_OUT = PC_7, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + OpenDrain = 3, + PullDefault = PullNone +} PinMode; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PortNames.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PortNames.h new file mode 100644 index 0000000000..0eb8287078 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PortNames.h @@ -0,0 +1,48 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h new file mode 100644 index 0000000000..9973c40578 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h @@ -0,0 +1,74 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 // Not present on this device + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +#define DEVICE_ETHERNET 0 + + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/objects.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/objects.h new file mode 100644 index 0000000000..7a3b8967ba --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/objects.h @@ -0,0 +1,98 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "PortNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct analogin_s { + ADCName adc; + PinName pin; +}; + +struct serial_s { + UARTName uart; + int index; // Used by irq + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + PinName pin_tx; + PinName pin_rx; +}; + +struct spi_s { + SSP_TypeDef *spi; +}; + +struct i2c_s { + I2CName i2c; + uint16_t ADDRESS; + uint16_t is_setAddress; +}; + +struct pwmout_s { + PWMName pwm; + PinName pin; + uint32_t period; + uint32_t pulse; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c new file mode 100644 index 0000000000..af28f7924e --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c @@ -0,0 +1,102 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed_assert.h" +#include "analogin_api.h" + +#if DEVICE_ANALOGIN + +#include "wait_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" + + +ADC_TypeDef * AdcHandle; + +int adc_inited = 0; + +void analogin_init(analogin_t *obj, PinName pin) +{ + // Get the peripheral name from the pin and assign it to the object + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + + MBED_ASSERT(obj->adc != (ADCName)NC); + + // Configure GPIO + pinmap_pinout(pin, PinMap_ADC); + + // Save pin number for the read function + obj->pin = pin; + + // The ADC initialization is done once + if (adc_inited == 0) { + adc_inited = 1; + + ADC_Init(); + } +} + +static inline uint16_t adc_read(analogin_t *obj) +{ + ADC_CH adc_ch; + + switch (obj->pin) { + case PC_15: + adc_ch = ADC_CH0; + break; + case PC_14: + adc_ch = ADC_CH1; + break; + case PC_13: + adc_ch = ADC_CH2; + break; + case PC_12: + adc_ch = ADC_CH3; + break; + case PC_11: + adc_ch = ADC_CH4; + break; + case PC_10: + adc_ch = ADC_CH5; + break; + default: + return 0; + } + + ADC_ChannelSelect(adc_ch); + ADC_Start(); + + // Wait end of conversion and get value + while(ADC_IsInterrupt()); + return ADC_ReadData(); +} + +uint16_t analogin_read_u16(analogin_t *obj) +{ + uint16_t value = adc_read(obj); + // 12-bit to 16-bit conversion + return value; +} + +float analogin_read(analogin_t *obj) +{ + uint16_t value = adc_read(obj); + + return (float)value * (1.0f / (float)0xFFF); // 12 bits range +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogout_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogout_api.c new file mode 100644 index 0000000000..5b77b3febe --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogout_api.c @@ -0,0 +1,64 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed_assert.h" +#include "analogout_api.h" + +#if DEVICE_ANALOGOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "PeripheralPins.h" + +#define DAC_RANGE (0xFFF) // 12 bits + +static DAC_HandleTypeDef DacHandle; + +void analogout_init(dac_t *obj, PinName pin) +{ + +} + +void analogout_free(dac_t *obj) +{ +} + +static inline void dac_write(dac_t *obj, uint16_t value) +{ +} + +static inline int dac_read(dac_t *obj) +{ +} + +void analogout_write(dac_t *obj, float value) +{ +} + +void analogout_write_u16(dac_t *obj, uint16_t value) +{ +} + +float analogout_read(dac_t *obj) +{ +} + +uint16_t analogout_read_u16(dac_t *obj) +{ +} + +#endif // DEVICE_ANALOGOUT diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_api.c new file mode 100644 index 0000000000..635a73c176 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_api.c @@ -0,0 +1,62 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "gpio_api.h" +#include "pinmap.h" + +extern uint32_t Get_GPIO_BaseAddress(uint32_t port_idx); + +uint32_t gpio_set(PinName pin) +{ + MBED_ASSERT(pin != (PinName)NC); + + pin_function(pin, WIZ_PIN_DATA(WIZ_MODE_INPUT, WIZ_GPIO_NOPULL, 0)); + + return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask +} + +void gpio_init(gpio_t *obj, PinName pin) +{ + obj->pin = pin; + if (pin == (PinName)NC) { + return; + } + + uint32_t port_index = WIZ_PORT(pin); + + GPIO_TypeDef *gpio = (GPIO_TypeDef *)Get_GPIO_BaseAddress(port_index); + + // Fill GPIO object structure for future use + obj->mask = gpio_set(pin); + obj->reg_data_in = &gpio->DATA; +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + pin_mode(obj->pin, mode); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + MBED_ASSERT(obj->pin != (PinName)NC); + obj->direction = direction; + + if (direction == PIN_OUTPUT) { + pin_function(obj->pin, WIZ_PIN_DATA(WIZ_MODE_OUTPUT, WIZ_GPIO_NOPULL, 0)); + } else { // PIN_INPUT + pin_function(obj->pin, WIZ_PIN_DATA(WIZ_MODE_INPUT, WIZ_GPIO_NOPULL, 0)); + } +} diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c new file mode 100644 index 0000000000..57a8e004f9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c @@ -0,0 +1,148 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "cmsis.h" +#include "gpio_irq_api.h" +#include "pinmap.h" +#include "mbed_error.h" + +#define EDGE_NONE (0) +#define EDGE_RISE (1) +#define EDGE_FALL (2) +#define EDGE_BOTH (3) + +static gpio_irq_handler irq_handler; + + +typedef struct gpio_channel { + uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts + uint32_t channel_ids; // mbed "gpio_irq_t gpio_irq" field of instance + uint32_t channel_pin; // pin number in port group + gpio_irq_t * obj; +} gpio_channel_t; + +static gpio_channel_t channel; + +#ifdef __cplusplus +extern "C"{ +#endif +void EXTI_Handler() +{ + // To Do + //irq_handler(channel.channel_ids); +} +#ifdef __cplusplus +} +#endif + + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + IRQn_Type irq_n = (IRQn_Type)0; + uint32_t gpio_pin; + + if (pin == NC) return -1; + + uint32_t port_index = WIZ_PORT(pin); + uint32_t pin_index = WIZ_PIN(pin); + + // If port_index is not GPIOC, return -1 + if (port_index != 2 ) { + error("InterruptIn error: pin not supported.\n"); + return -1; + } + + // Select irq number and interrupt routine + if ((pin_index == 0) || (pin_index == 1) || (pin_index == 4) || (pin_index == 6) || (pin_index == 7)) { + irq_n = EXTI_IRQn; + gpio_pin = 1 << pin_index; + } else { + error("InterruptIn error: pin not supported.\n"); + return -1; + } + + // Enable GPIO clock + uint32_t gpio_add = Get_GPIO_BaseAddress(port_index); + + // Configure GPIO + EXTI_InitTypeDef EXTI_InitDef; + EXTI_InitDef.EXTI_Line = gpio_pin; + EXTI_InitDef.EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_Init(gpio_add, &EXTI_InitDef); + + // Enable EXTI interrupt + NVIC_ClearPendingIRQ(irq_n); // Pending bit Clear + NVIC_EnableIRQ(irq_n); + + obj->irq_n = irq_n; +// obj->irq_index = irq_index; + obj->event = EDGE_FALL; + obj->pin = pin; + + channel.channel_pin = pin_index; + channel.pin_mask = gpio_pin; + channel.channel_ids = id; + channel.obj = obj; + + irq_handler = handler; + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + // Disable EXTI line + NVIC_ClearPendingIRQ(obj->irq_n); + EXTI_DeInit(); + pin_function(obj->pin, WIZ_PIN_DATA(WIZ_MODE_INPUT, WIZ_GPIO_NOPULL, 0)); + obj->event = EDGE_NONE; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + uint16_t porarity; + + if (enable) { + if (event == IRQ_RISE) { + porarity = EXTI_Trigger_Rising; + obj->event = EDGE_RISE; + } + if (event == IRQ_FALL) { + porarity = EXTI_Trigger_Falling; + obj->event = EDGE_FALL; + } + + uint32_t port_index = WIZ_PORT(obj->pin); + uint32_t pin_index = WIZ_PIN(obj->pin); + + // Enable GPIO clock + uint32_t gpio_add = Get_GPIO_BaseAddress(port_index); + EXTI_Polarity_Set(port_index,(1<irq_n); +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ + NVIC_DisableIRQ(obj->irq_n); + obj->event = EDGE_NONE; +} diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_object.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_object.h new file mode 100644 index 0000000000..42472bead6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_object.h @@ -0,0 +1,86 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; + uint32_t mask; + uint32_t direction; + __IO uint32_t *reg_data_in; +} gpio_t; + + +extern uint32_t Get_GPIO_BaseAddress(uint32_t port_idx); + + +static inline void gpio_write(gpio_t *obj, int value) { + MBED_ASSERT(obj->pin != (PinName)NC); + + uint32_t port_index = WIZ_PORT(obj->pin); + uint32_t pin_index = WIZ_PIN(obj->pin); + + uint32_t gpio_add = Get_GPIO_BaseAddress(port_index); + GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; + + + if (value) + { + HAL_GPIO_SetBits(gpio,(0x01 << pin_index)); + } + else + { + HAL_GPIO_ResetBits(gpio,(0x01 << pin_index)); + } +} + +static inline int gpio_read(gpio_t *obj) { + int ret; + + MBED_ASSERT(obj->pin != (PinName)NC); + + uint32_t port_index = WIZ_PORT(obj->pin); + + uint32_t gpio_add = Get_GPIO_BaseAddress(port_index); + GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; + + if(obj->direction == PIN_OUTPUT) + { + ret = ( HAL_GPIO_ReadOutputData(gpio) & obj->mask ) ? 1 : 0; + } + else + { + ret = ((*obj->reg_data_in & obj->mask) ? 1 : 0); + } + + return ret; +} + +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/i2c_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/i2c_api.c new file mode 100644 index 0000000000..0e6bb4f04b --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/i2c_api.c @@ -0,0 +1,316 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "mbed_assert.h" +#include "i2c_api.h" + +#if DEVICE_I2C + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" + +/* Timeout values for flags and events waiting loops. These timeouts are + not based on accurate values, they just guarantee that the application will + not remain stuck if the I2C communication is corrupted. */ +#define FLAG_TIMEOUT ((int)0x1000) +#define LONG_TIMEOUT ((int)0xFFFF) + +I2C_TypeDef * I2cHandle; + +int i2c0_inited = 0; +int i2c1_inited = 0; + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + // Determine the I2C to use + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + + obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT(obj->i2c != (I2CName)NC); + + // Enable I2C1 clock and pinout if not done + if ((obj->i2c == I2C_0) && !i2c0_inited) { + i2c0_inited = 1; + // Configure I2C pins + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + pin_mode(sda, OpenDrain); + pin_mode(scl, OpenDrain); + } + + // Enable I2C2 clock and pinout if not done + if ((obj->i2c == I2C_1) && !i2c1_inited) { + i2c1_inited = 1; + // Configure I2C pins + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + pin_mode(sda, OpenDrain); + pin_mode(scl, OpenDrain); + } + + // Reset to clear pending flags if any + i2c_reset(obj); + + // I2C configuration + i2c_frequency(obj, 100000); // 100 kHz per default + obj->is_setAddress = 0; +} + +void i2c_frequency(i2c_t *obj, int hz) +{ + MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); + I2cHandle = (I2C_TypeDef *)(obj->i2c); + + // wait before init + I2C_ConfigStruct conf; + + conf.mode = I2C_Master; + conf.master.timeout = LONG_TIMEOUT; + + // Common settings: I2C clock = 48 MHz, Analog filter = ON, Digital filter coefficient = 0 + switch (hz) { + case 100000: + conf.master.prescale = 0x61; // Standard mode with Rise Time = 400ns and Fall Time = 100ns + break; + case 400000: + break; + case 1000000: + break; + default: + break; + } + + // I2C configuration + I2C_Init(I2cHandle, conf); +} + +inline int i2c_start(i2c_t *obj) +{ + obj->is_setAddress = 0; + + return 0; +} + +inline int i2c_stop(i2c_t *obj) +{ + I2cHandle = (I2C_TypeDef *)(obj->i2c); + + // Generate the STOP condition + I2C_Stop(I2cHandle); + I2C_Reset(I2cHandle); + obj->is_setAddress = 0; + + return 0; +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + I2cHandle = (I2C_TypeDef *)(obj->i2c); + int count; + int value; + + if(!obj->is_setAddress) + { + if( I2C_Start(I2cHandle, address, I2C_READ_SA7) == ERROR ) + { + return -1; + } + obj->is_setAddress = 1; + obj->ADDRESS = address; + } + else + { + I2C_Restart_Structure(I2cHandle, address, I2C_READ_SA7); + obj->ADDRESS = address; + } + + // Read all bytes + for (count = 0; count < (length-1); count++) { + if( (value = i2c_byte_read(obj, 0)) == -1) return value; + data[count] = (char)value; + } + + if(stop){ + if( (value = i2c_byte_read(obj, 1)) == -1) return value; + data[count] = (char)value; + } + else{ + if( (value = i2c_byte_read(obj, 0)) == -1) return value; + data[count] = (char)value; + } + + return count; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + I2cHandle = (I2C_TypeDef *)(obj->i2c); + int count; + + if(!obj->is_setAddress) + { + if( I2C_Start(I2cHandle, address, I2C_WRITE_SA7) == ERROR ) + { + return -1; + } + obj->is_setAddress = 1; + obj->ADDRESS = address; + } + else + { + I2C_Restart_Structure(I2cHandle, address, I2C_WRITE_SA7); + obj->ADDRESS = address; + } + + for (count = 0; count < length; count++) { + i2c_byte_write(obj, data[count]); + } + + // If not repeated start, send stop + if (stop) { + i2c_stop(obj); + } + + return count; +} + +int i2c_byte_read(i2c_t *obj, int last) +{ + I2cHandle = (I2C_TypeDef *)(obj->i2c); + + return I2C_ReceiveData(I2cHandle, last); +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + I2cHandle = (I2C_TypeDef *)(obj->i2c); + return I2C_SendDataAck(I2cHandle,(uint8_t)data); +} + +void i2c_reset(i2c_t *obj) +{ + I2cHandle = (I2C_TypeDef *)(obj->i2c); + + I2C_Reset(I2cHandle); +} + +//#if DEVICE_I2CSLAVE +// +//void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +//{ +// I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); +// uint16_t tmpreg = 0; +// +// // disable +// i2c->OAR1 &= (uint32_t)(~I2C_OAR1_OA1EN); +// // Get the old register value +// tmpreg = i2c->OAR1; +// // Reset address bits +// tmpreg &= 0xFC00; +// // Set new address +// tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits +// // Store the new register value +// i2c->OAR1 = tmpreg; +// // enable +// i2c->OAR1 |= I2C_OAR1_OA1EN; +//} +// +//void i2c_slave_mode(i2c_t *obj, int enable_slave) +//{ +// I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); +// uint16_t tmpreg; +// +// // Get the old register value +// tmpreg = i2c->OAR1; +// +// // Enable / disable slave +// if (enable_slave == 1) { +// tmpreg |= I2C_OAR1_OA1EN; +// } else { +// tmpreg &= (uint32_t)(~I2C_OAR1_OA1EN); +// } +// +// // Set new mode +// i2c->OAR1 = tmpreg; +//} +// +//// See I2CSlave.h +//#define NoData 0 // the slave has not been addressed +//#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) +//#define WriteGeneral 2 // the master is writing to all slave +//#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) +// +//int i2c_slave_receive(i2c_t *obj) +//{ +// I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); +// int retValue = NoData; +// +// if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) { +// if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) { +// if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_DIR) == 1) +// retValue = ReadAddressed; +// else +// retValue = WriteAddressed; +// +// __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR); +// } +// } +// +// return (retValue); +//} +// +//int i2c_slave_read(i2c_t *obj, char *data, int length) +//{ +// char size = 0; +// +// while (size < length) data[size++] = (char)i2c_byte_read(obj, 0); +// +// return size; +//} +// +//int i2c_slave_write(i2c_t *obj, const char *data, int length) +//{ +// char size = 0; +// I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); +// +// do { +// i2c_byte_write(obj, data[size]); +// size++; +// } while (size < length); +// +// return size; +//} +// +// +//#endif // DEVICE_I2CSLAVE + +#endif // DEVICE_I2C diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/mbed_overrides.c new file mode 100644 index 0000000000..3e7b4fb61a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/mbed_overrides.c @@ -0,0 +1,24 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "cmsis.h" + +// This function is called after RAM initialization and before main. +void mbed_sdk_init() +{ + // Update the SystemCoreClock variable. + SystemInit(); +} diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pinmap.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pinmap.c new file mode 100644 index 0000000000..dd37dec726 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pinmap.c @@ -0,0 +1,139 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pinmap.h" +#include "PortNames.h" + + +// GPIO mode look-up table +// It have to same with PinMode index in "PinNames.h" +static const uint32_t gpio_pupd[4] = { + GPIO_NO_PUPD, // PullNone + GPIO_PuPd_DOWN, // PullDown + GPIO_PuPd_UP, // PullUp + GPIO_OD // OpenDrain +}; + +uint32_t Get_GPIO_BaseAddress(uint32_t port_idx) +{ + uint32_t gpio_add = 0; + switch(port_idx) { + case PortA: + gpio_add = GPIOA_BASE; + break; + case PortB: + gpio_add = GPIOB_BASE; + break; + case PortC: + gpio_add = GPIOC_BASE; + break; + case PortD: + gpio_add = GPIOD_BASE; + break; + default: + error("Pinmap error: wrong port number."); + break; + } + return gpio_add; +} + + +/** + * Configure pin (input, output, alternate function or analog) + output speed + AF + */ + +void pin_function(PinName pin, int data) { + MBED_ASSERT(pin != (PinName)NC); + // Get the pin informations + uint32_t mode = WIZ_PIN_MODE(data); + uint32_t pupd = WIZ_PIN_PUPD(data); + uint32_t afnum; + + if( mode == WIZ_MODE_AF ) + afnum = WIZ_PIN_AFNUM(data); + else + afnum = WIZ_AFNUM(pin); + + uint32_t port_index = WIZ_PORT(pin); + uint32_t pin_index = WIZ_PIN(pin); + + + uint32_t gpio_add = Get_GPIO_BaseAddress(port_index); + GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; + + // Configure Alternate Function + // Warning: Must be done before the GPIO is initialized + switch (afnum) { + case 0: + HAL_PAD_AFConfig(port_index,(uint32_t)(1 << pin_index),Px_AFSR_AF0); + break; + case 1: + HAL_PAD_AFConfig(port_index,(uint32_t)(1 << pin_index),Px_AFSR_AF1); + break; + case 2: + HAL_PAD_AFConfig(port_index,(uint32_t)(1 << pin_index),Px_AFSR_AF2); + break; + case 3: + HAL_PAD_AFConfig(port_index,(uint32_t)(1 << pin_index),Px_AFSR_AF3); + break; + default: + break; + } + + if(mode == WIZ_MODE_AF) + return; + + // Configure GPIO + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = (uint32_t)(1 << pin_index); + GPIO_InitStructure.GPIO_Mode = mode; + GPIO_InitStructure.GPIO_Pad = gpio_pupd[pupd]; + HAL_GPIO_Init(gpio, &GPIO_InitStructure); +} + +/** + * Configure pin pull-up/pull-down + */ +void pin_mode(PinName pin, PinMode pupd) +{ + MBED_ASSERT(pin != (PinName)NC); + + P_Port_Def *px_pcr; + + uint32_t port_index = WIZ_PORT(pin); + + switch(port_index) { + case PortA: + px_pcr = PA_PCR; + break; + case PortB: + px_pcr = PB_PCR; + break; + case PortC: + px_pcr = PC_PCR; + break; + case PortD: + px_pcr = (P_Port_Def*)PD_PCR; + break; + default: + error("Pinmap error: wrong port number."); + return; + } + + px_pcr->Port[port_index] &= ~(Px_PCR_PUPD_DOWN|Px_PCR_PUPD_UP|Px_PCR_DS_HIGH| \ + Px_PCR_OD | Px_PCR_IE | Px_PCR_CS_SUMMIT); + px_pcr->Port[port_index] |= gpio_pupd[pupd]; +} diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/port_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/port_api.c new file mode 100644 index 0000000000..3680a48b2d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/port_api.c @@ -0,0 +1,96 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" +#include "pinmap.h" +#include "gpio_api.h" +#include "mbed_error.h" + +#if DEVICE_PORTIN || DEVICE_PORTOUT + +extern uint32_t Get_GPIO_BaseAddress(uint32_t port_idx); + +//port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...) +PinName port_pin(PortName port, int pin_n) +{ + int af_num = 0; + + if( (port == 2) && ((pin_n == 0) || (pin_n == 1) || (pin_n == 4) || (pin_n == 8) || (pin_n == 9)) ) + { + af_num = 1; + } + + + return (PinName)(pin_n + (port << 4) + (af_num << 8)); +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ + uint32_t port_index = (uint32_t)port; + + // Enable GPIO clock + uint32_t gpio_add = Get_GPIO_BaseAddress(port_index); + GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; + + // Fill PORT object structure for future use + obj->port = port; + obj->mask = mask; + obj->direction = dir; + obj->reg_in = &gpio->DATA; + obj->reg_out = &gpio->DATAOUT; + + port_dir(obj, dir); +} + +void port_dir(port_t *obj, PinDirection dir) +{ + uint32_t i; + obj->direction = dir; + for (i = 0; i < 16; i++) { // Process all pins + if (obj->mask & (1 << i)) { // If the pin is used + if (dir == PIN_OUTPUT) { + pin_function(port_pin(obj->port, i), WIZ_PIN_DATA(WIZ_MODE_OUTPUT, WIZ_GPIO_NOPULL, 0)); + } else { // PIN_INPUT + pin_function(port_pin(obj->port, i), WIZ_PIN_DATA(WIZ_MODE_INPUT, WIZ_GPIO_NOPULL, 0)); + } + } + } +} + +void port_mode(port_t *obj, PinMode mode) +{ + uint32_t i; + for (i = 0; i < 16; i++) { // Process all pins + if (obj->mask & (1 << i)) { // If the pin is used + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_write(port_t *obj, int value) +{ + *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); +} + +int port_read(port_t *obj) +{ + if (obj->direction == PIN_OUTPUT) { + return (*obj->reg_out & obj->mask); + } else { // PIN_INPUT + return (*obj->reg_in & obj->mask); + } +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c new file mode 100644 index 0000000000..110b46a20e --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c @@ -0,0 +1,280 @@ +#include "mbed_assert.h" +#include "serial_api.h" + +#if DEVICE_SERIAL + +#include "cmsis.h" +#include "pinmap.h" +#include +#include "PeripheralPins.h" + +#define UART_NUM (2) + +static uint32_t serial_irq_ids[UART_NUM] = {0, 0}; + + +static uart_irq_handler irq_handler; +static UART_TypeDef *UART; + + +UART_InitTypeDef UART_InitStructure; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +static void init_uart(serial_t *obj) +{ + UART = (UART_TypeDef *)(obj->uart); + UART_InitStructure.UART_BaudRate = obj->baudrate; + UART_InitStructure.UART_WordLength = obj->databits; + UART_InitStructure.UART_StopBits = obj->stopbits; + UART_InitStructure.UART_Parity = obj->parity; + UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; + + + if (obj->pin_rx == NC) { + UART_InitStructure.UART_Mode = UART_Mode_Tx; + } else if (obj->pin_tx == NC) { + UART_InitStructure.UART_Mode = UART_Mode_Rx; + } else { + UART_InitStructure.UART_Mode = (UART_Mode_Rx | UART_Mode_Tx); + } + + UART_Init(UART,&UART_InitStructure); +} + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + // Determine the UART to use (UART_1, UART_2, ...) + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + + // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object + obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + + MBED_ASSERT(obj->uart != (UARTName)NC); + + // Enable USART clock + if (obj->uart == UART_0) { + obj->index = 0; + } + + if (obj->uart == UART_1) { + obj->index = 1; + } + + // Configure the UART pins + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + if (tx != NC) { + pin_mode(tx, PullUp); + } + if (rx != NC) { + pin_mode(rx, PullUp); + } + + // Configure UART + obj->baudrate = 9600; + obj->databits = UART_WordLength_8b; + obj->stopbits = UART_StopBits_1; + obj->parity = UART_Parity_No; + + obj->pin_tx = tx; + obj->pin_rx = rx; + + + init_uart(obj); + + // For stdio management + if (obj->uart == STDIO_UART) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) +{ + // Reset UART and disable clock + if (obj->uart == UART_0) { + } + + if (obj->uart == UART_1) { + } + + + // Configure GPIOs +// pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); +// pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + + serial_irq_ids[obj->index] = 0; +} + +void serial_baud(serial_t *obj, int baudrate) +{ + obj->baudrate = baudrate; + init_uart(obj); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + if (data_bits == 7) { + obj->databits = UART_WordLength_7b; + } else { + obj->databits = UART_WordLength_8b; + } + + switch (parity) { + case ParityOdd: + case ParityForced0: + obj->parity = UART_Parity_Odd; + break; + case ParityEven: + case ParityForced1: + obj->parity = UART_Parity_Even; + break; + default: // ParityNone + obj->parity = UART_Parity_No; + break; + } + + if (stop_bits == 2) { + obj->stopbits = UART_StopBits_2; + } else { + obj->stopbits = UART_StopBits_1; + } + + init_uart(obj); +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ + +static void uart_irq(UARTName name, int id) +{ + UART = (UART_TypeDef *)name; + if (serial_irq_ids[id] != 0) { + if( UART_GetITStatus(UART,UART_IT_FLAG_TXI) != RESET ){ + irq_handler(serial_irq_ids[id], TxIrq); + UART_ClearITPendingBit(UART,UART_IT_FLAG_TXI); + } + if( UART_GetITStatus(UART,UART_IT_FLAG_RXI) != RESET ){ + irq_handler(serial_irq_ids[id], RxIrq); + } + } +} + +#ifdef __cplusplus +extern "C"{ +#endif +void UART0_Handler() +{ + uart_irq(UART_0, 0); +} + +void UART1_Handler() +{ + uart_irq(UART_1, 1); +} +#ifdef __cplusplus +} +#endif + + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + IRQn_Type irq_n = (IRQn_Type)0; + + UART = (UART_TypeDef *)(obj->uart); + + if (obj->uart == UART_0) { + irq_n = UART0_IRQn; + } + + if (obj->uart == UART_1) { + irq_n = UART1_IRQn; + } + + if (enable) { + if (irq == RxIrq) { + UART_ITConfig(UART,UART_IT_FLAG_RXI,ENABLE); + } else { // TxIrq + UART_ITConfig(UART,UART_IT_FLAG_TXI,ENABLE); + } + + NVIC_ClearPendingIRQ(irq_n); + NVIC_EnableIRQ(irq_n); + } else { // disable + UART_ITConfig(UART,(UART_IT_FLAG_RXI|UART_IT_FLAG_TXI),DISABLE); + NVIC_DisableIRQ(irq_n); + } +} + +/****************************************************************************** + * READ/WRITE + ******************************************************************************/ + +int serial_getc(serial_t *obj) +{ + UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); +// while(!serial_readable(obj)); + while(uart->FR & UART_FR_RXFE); + + return (uart->DR & 0xFF); +} + +void serial_putc(serial_t *obj, int c) +{ + UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); + + uart->DR = (uint32_t)(c & (uint16_t)0xFF); + while(uart->FR & UART_FR_BUSY); +} + +int serial_readable(serial_t *obj) +{ + int status; + UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); + // Check if data is received + status = ((uart->FR & UART_FR_RXFE) ? 0: 1); + return status; +} + +int serial_writable(serial_t *obj) +{ + int status; + UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); + // Check if data is transmitted + status = ((uart->FR & UART_FR_BUSY) ? 0: 1); + return status; +} + +void serial_clear(serial_t *obj) +{ +// UartHandle.Instance = (USART_TypeDef *)(obj->uart); +// __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); +// __HAL_UART_SEND_REQ(&UartHandle, UART_RXDATA_FLUSH_REQUEST); +} + +void serial_pinout_tx(PinName tx) +{ + //pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) +{ + // [TODO] +} + +void serial_break_clear(serial_t *obj) +{ + // [TODO] +} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/sleep.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/sleep.c new file mode 100644 index 0000000000..81ed6b36d6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/sleep.c @@ -0,0 +1,43 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "sleep_api.h" +#include "cmsis.h" +#include "mbed_interface.h" + +void sleep(void) +{ + // To Do +} + +void deepsleep(void) +{ + // To Do +} diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/spi_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/spi_api.c new file mode 100644 index 0000000000..c37942b73e --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/spi_api.c @@ -0,0 +1,187 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include + +#include "spi_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "PeripheralPins.h" + +static inline int ssp_disable(spi_t *obj); +static inline int ssp_enable(spi_t *obj); + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { + // determine the SPI to use + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + obj->spi = (SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj->spi != NC); + + // enable power and clocking + switch ((int)obj->spi) { + case SPI_0: CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK; break; //PLL output clock + case SPI_1: CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK; break; + } + + // set default format and frequency + if (ssel == NC) { + spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master + } else { + spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave + } + spi_frequency(obj, 1000000); + + // enable the ssp channel + ssp_enable(obj); + + // pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } +} + +void spi_free(spi_t *obj) {} + +void spi_format(spi_t *obj, int bits, int mode, int slave) { + ssp_disable(obj); + MBED_ASSERT(((bits >= 4) && (bits <= 16)) && (mode >= 0 && mode <= 3)); + + int polarity = (mode & 0x2) ? 1 : 0; + int phase = (mode & 0x1) ? 1 : 0; + + // set it up + int DSS = bits - 1; // DSS (data select size) + int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity + int SPH = (phase) ? 1 : 0; // SPH - clock out phase + + int FRF = 0; // FRF (frame format) = SPI + uint32_t tmp = obj->spi->CR0; + tmp &= ~(0xFFFF); + tmp |= DSS << 0 + | FRF << 4 + | SPO << 6 + | SPH << 7; + obj->spi->CR0 = tmp; + + tmp = obj->spi->CR1; + tmp &= ~(0xD); + tmp |= 0 << 0 // LBM - loop back mode - off + | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave + | 0 << 3; // SOD - slave output disable - na + obj->spi->CR1 = tmp; + + ssp_enable(obj); +} + +void spi_frequency(spi_t *obj, int hz) { + ssp_disable(obj); + + // setup the spi clock diveder to /1 + switch ((int)obj->spi) { + case SPI_0: + CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1; //1/1 (bypass) + break; + case SPI_1: + CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1; //1/1 (bypass) + break; + } + + uint32_t HCLK = SystemCoreClock; + + int prescaler; + + for (prescaler = 2; prescaler <= 254; prescaler += 2) { + int prescale_hz = HCLK / prescaler; + + // calculate the divider + int divider = floor(((float)prescale_hz / (float)hz) + 0.5f); + + // check we can support the divider + if (divider < 256) { + // prescaler + obj->spi->CPSR = prescaler; + + // divider + obj->spi->CR0 &= ~(0xFFFF << 8); + obj->spi->CR0 |= (divider - 1) << 8; + ssp_enable(obj); + return; + } + } + error("Couldn't setup requested SPI frequency"); +} + +static inline int ssp_disable(spi_t *obj) { + return obj->spi->CR1 &= ~(1 << 1); +} + +static inline int ssp_enable(spi_t *obj) { + return obj->spi->CR1 |= (1 << 1); +} + +static inline int ssp_readable(spi_t *obj) { + return obj->spi->SR & (1 << 2); +} + +static inline int ssp_writeable(spi_t *obj) { + return obj->spi->SR & (1 << 1); +} + +static inline void ssp_write(spi_t *obj, int value) { + while (!ssp_writeable(obj)); + obj->spi->DR = value; +} + +static inline int ssp_read(spi_t *obj) { + while (!ssp_readable(obj)); + return obj->spi->DR; +} + +static inline int ssp_busy(spi_t *obj) { + return (obj->spi->SR & (1 << 4)) ? (1) : (0); +} + +int spi_master_write(spi_t *obj, int value) { + ssp_write(obj, value); + return ssp_read(obj); +} + +int spi_slave_receive(spi_t *obj) { + return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); +} + +int spi_slave_read(spi_t *obj) { + return obj->spi->DR; +} + +void spi_slave_write(spi_t *obj, int value) { + while (ssp_writeable(obj) == 0) ; + obj->spi->DR = value; +} + +int spi_busy(spi_t *obj) { + return ssp_busy(obj); +} + diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c new file mode 100644 index 0000000000..5320ed3da9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c @@ -0,0 +1,121 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "us_ticker_api.h" +#include "PeripheralNames.h" +#include "system_W7500x.h" + +// 32-bit timer selection +#define TIM_MST7 PWM_CH7 +#define TIM_MST6 PWM_CH6 +#define IRQn_PWM6 PWM6_IRQn + +static PWM_TimerModeInitTypeDef TimMasterHandle_CH7; +static PWM_TimerModeInitTypeDef TimMasterHandle_CH6; + +static int us_ticker_inited = 0; + + +#ifdef __cplusplus +extern "C"{ +#endif +void PWM6_Handler(void) +{ + uint32_t IntFlag = 0; + + IntFlag = PWM_CHn_GetIntFlagStatus(TIM_MST6); + + /* If overflow interrupt is occurred */ + if( (IntFlag & PWM_CHn_IER_OI_Msk) != 0 ) + { + /* Clear overflow interrupt */ + PWM_CH6_ClearOverflowInt(); + us_ticker_irq_handler(); + } +} + +#ifdef __cplusplus +} +#endif + +void us_ticker_init(void) +{ + if (us_ticker_inited) return; + us_ticker_inited = 1; + + SystemCoreClockUpdate(); + TimMasterHandle_CH7.PWM_CHn_PR = (GetSystemClock() / 1000000) -1; + TimMasterHandle_CH7.PWM_CHn_LR = 0xFFFFFFFF; + TimMasterHandle_CH7.PWM_CHn_PDMR = 1; + + PWM_TimerModeInit(TIM_MST7, &TimMasterHandle_CH7); + PWM_CHn_Start(TIM_MST7); +} + + +uint32_t us_ticker_read() +{ + if (!us_ticker_inited) us_ticker_init(); + + return (TIM_MST7->TCR); +} + + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + int32_t dev = 0; + if (!us_ticker_inited) + { + us_ticker_init(); + } + + dev = (timestamp - us_ticker_read() + 0x5153); + if(dev <= 0) + { + us_ticker_irq_handler(); + return; + } + + PWM_CHn_Stop(TIM_MST6); + + TimMasterHandle_CH6.PWM_CHn_PR = (GetSystemClock() / 1000000) -1; + TimMasterHandle_CH6.PWM_CHn_LR = dev; + + TimMasterHandle_CH6.PWM_CHn_UDMR = 0; + TimMasterHandle_CH6.PWM_CHn_PDMR = 0; + + NVIC_EnableIRQ(IRQn_PWM6); + + PWM_CHn_IntConfig(TIM_MST6, PWM_CHn_IER_OIE, ENABLE); + PWM_IntConfig(TIM_MST6, ENABLE); + PWM_TimerModeInit(TIM_MST6, &TimMasterHandle_CH6); + + PWM_CHn_Start(TIM_MST6); +} + +void us_ticker_disable_interrupt(void) +{ + NVIC_DisableIRQ(IRQn_PWM6); + + PWM_CHn_IntConfig(TIM_MST6, PWM_CHn_IER_OIE, DISABLE); + PWM_IntConfig(TIM_MST6, DISABLE); +} + +void us_ticker_clear_interrupt(void) +{ + PWM_CHn_ClearInt(TIM_MST6, PWM_CHn_IER_OIE); +} From 2f751039fc06f77134b4ad38763468a25c498a4a Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Fri, 15 May 2015 11:28:46 +0900 Subject: [PATCH 02/26] add some files --- workspace_tools/muts_all.json | 7 +++++++ workspace_tools/targets.py | 16 +++++++++++++++- workspace_tools/test_spec.json | 5 +++++ 3 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 workspace_tools/muts_all.json create mode 100644 workspace_tools/test_spec.json diff --git a/workspace_tools/muts_all.json b/workspace_tools/muts_all.json new file mode 100644 index 0000000000..ea7cb6e0e0 --- /dev/null +++ b/workspace_tools/muts_all.json @@ -0,0 +1,7 @@ +{ + "1" : {"mcu": "WIZwiki_W7500", + "port":"COM29", + "disk":"E:\\", + "peripherals": [] + } +} diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 4de30c80a9..93c8b630ec 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -69,8 +69,19 @@ class Target: def init_hooks(self, hook, toolchain_name): pass +##WIZnet - +class WIZwiki_W7500(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['WIZNET', 'W7500x', 'WIZwiki_W7500'] + self.supported_toolchains = ["ARM", "uARM",] + self.default_toolchain = "ARM" + self.supported_form_factors = ["ARDUINO"] + + + ### NXP ### # This class implements the post-link patching step needed by LPC targets @@ -1201,6 +1212,9 @@ class EFM32HG_STK3400(Target): # Get a single instance for each target TARGETS = [ + ### WIZnet ### + WIZwiki_W7500(), + ### NXP ### LPC11C24(), LPC11U24(), diff --git a/workspace_tools/test_spec.json b/workspace_tools/test_spec.json new file mode 100644 index 0000000000..a4818818ae --- /dev/null +++ b/workspace_tools/test_spec.json @@ -0,0 +1,5 @@ +{ + "targets": { + "WIZwiki_W7500" : ["ARM", "uARM"] + } +} From c452befc0aded41bcbad41c4297f276e1c752ae7 Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Mon, 18 May 2015 09:32:49 +0900 Subject: [PATCH 03/26] Delete json files --- workspace_tools/muts_all.json | 7 ------- workspace_tools/test_spec.json | 5 ----- 2 files changed, 12 deletions(-) delete mode 100644 workspace_tools/muts_all.json delete mode 100644 workspace_tools/test_spec.json diff --git a/workspace_tools/muts_all.json b/workspace_tools/muts_all.json deleted file mode 100644 index ea7cb6e0e0..0000000000 --- a/workspace_tools/muts_all.json +++ /dev/null @@ -1,7 +0,0 @@ -{ - "1" : {"mcu": "WIZwiki_W7500", - "port":"COM29", - "disk":"E:\\", - "peripherals": [] - } -} diff --git a/workspace_tools/test_spec.json b/workspace_tools/test_spec.json deleted file mode 100644 index a4818818ae..0000000000 --- a/workspace_tools/test_spec.json +++ /dev/null @@ -1,5 +0,0 @@ -{ - "targets": { - "WIZwiki_W7500" : ["ARM", "uARM"] - } -} From 7d82bcacaa3e2480f6a728f147a57cc19a8eb0ff Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Mon, 18 May 2015 14:31:19 +0900 Subject: [PATCH 04/26] Remove rtc_api.c and pwmout_api.c And change define in device.h about RTC and pwmout. --- .../TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h | 4 ++-- .../mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c | 0 .../mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c | 0 3 files changed, 2 insertions(+), 2 deletions(-) delete mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h index 9973c40578..f94476da70 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h @@ -48,9 +48,9 @@ #define DEVICE_SPI 1 #define DEVICE_SPISLAVE 1 -#define DEVICE_RTC 1 +#define DEVICE_RTC 0 -#define DEVICE_PWMOUT 1 +#define DEVICE_PWMOUT 0 #define DEVICE_SLEEP 1 diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c deleted file mode 100644 index e69de29bb2..0000000000 From 9c329b93573127e6bc28d0de3510ab0e87953edb Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Wed, 20 May 2015 10:50:45 +0900 Subject: [PATCH 05/26] Remove analogout_api.c Remove toolchain ARM at targets.py --- .../TARGET_W7500x/analogout_api.c | 64 ------------------- workspace_tools/targets.py | 4 +- 2 files changed, 2 insertions(+), 66 deletions(-) delete mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogout_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogout_api.c deleted file mode 100644 index 5b77b3febe..0000000000 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogout_api.c +++ /dev/null @@ -1,64 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "mbed_assert.h" -#include "analogout_api.h" - -#if DEVICE_ANALOGOUT - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" - -#define DAC_RANGE (0xFFF) // 12 bits - -static DAC_HandleTypeDef DacHandle; - -void analogout_init(dac_t *obj, PinName pin) -{ - -} - -void analogout_free(dac_t *obj) -{ -} - -static inline void dac_write(dac_t *obj, uint16_t value) -{ -} - -static inline int dac_read(dac_t *obj) -{ -} - -void analogout_write(dac_t *obj, float value) -{ -} - -void analogout_write_u16(dac_t *obj, uint16_t value) -{ -} - -float analogout_read(dac_t *obj) -{ -} - -uint16_t analogout_read_u16(dac_t *obj) -{ -} - -#endif // DEVICE_ANALOGOUT diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 93c8b630ec..0b148f35c2 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -76,8 +76,8 @@ class WIZwiki_W7500(Target): Target.__init__(self) self.core = "Cortex-M0" self.extra_labels = ['WIZNET', 'W7500x', 'WIZwiki_W7500'] - self.supported_toolchains = ["ARM", "uARM",] - self.default_toolchain = "ARM" + self.supported_toolchains = ["uARM",] + self.default_toolchain = "uARM" self.supported_form_factors = ["ARDUINO"] From 0551f6e8b955bd081d69afd121ef2e84f17a0189 Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Thu, 21 May 2015 15:17:17 -0500 Subject: [PATCH 06/26] Added tests for the WFI instruction --- libraries/tests/mbed/wfi/main.cpp | 18 +++++++++++++ workspace_tools/host_tests/__init__.py | 2 ++ workspace_tools/host_tests/wfi_auto.py | 37 ++++++++++++++++++++++++++ workspace_tools/tests.py | 9 +++++-- 4 files changed, 64 insertions(+), 2 deletions(-) create mode 100644 libraries/tests/mbed/wfi/main.cpp create mode 100644 workspace_tools/host_tests/wfi_auto.py diff --git a/libraries/tests/mbed/wfi/main.cpp b/libraries/tests/mbed/wfi/main.cpp new file mode 100644 index 0000000000..775872c650 --- /dev/null +++ b/libraries/tests/mbed/wfi/main.cpp @@ -0,0 +1,18 @@ +#include "mbed.h" +#include "test_env.h" + +int main(void) +{ + MBED_HOSTTEST_TIMEOUT(15); + MBED_HOSTTEST_SELECT(wfi_auto); + MBED_HOSTTEST_DESCRIPTION(WFI correct behavior); + MBED_HOSTTEST_START("MBED_36"); + + + int count = 0; + + while(1) { + printf("%d\r\n", count++); + __WFI(); + } +} diff --git a/workspace_tools/host_tests/__init__.py b/workspace_tools/host_tests/__init__.py index cae0e20908..3e3f10f55c 100644 --- a/workspace_tools/host_tests/__init__.py +++ b/workspace_tools/host_tests/__init__.py @@ -30,6 +30,7 @@ from tcpecho_server_auto import TCPEchoServerTest from udpecho_server_auto import UDPEchoServerTest from tcpecho_client_auto import TCPEchoClientTest from udpecho_client_auto import UDPEchoClientTest +from wfi_auto import WFITest # Populate registry with supervising objects HOSTREGISTRY = HostRegistry() @@ -46,6 +47,7 @@ HOSTREGISTRY.register_host_test("tcpecho_server_auto", TCPEchoServerTest()) HOSTREGISTRY.register_host_test("udpecho_server_auto", UDPEchoServerTest()) HOSTREGISTRY.register_host_test("tcpecho_client_auto", TCPEchoClientTest()) HOSTREGISTRY.register_host_test("udpecho_client_auto", UDPEchoClientTest()) +HOSTREGISTRY.register_host_test("wfi_auto", WFITest()) ############################################################################### # Functional interface for test supervisor registry diff --git a/workspace_tools/host_tests/wfi_auto.py b/workspace_tools/host_tests/wfi_auto.py new file mode 100644 index 0000000000..b51beca13f --- /dev/null +++ b/workspace_tools/host_tests/wfi_auto.py @@ -0,0 +1,37 @@ +""" +mbed SDK +Copyright (c) 2011-2013 ARM Limited + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" + +import sys +import uuid +import time +from sys import stdout + +class WFITest(): + + def test(self, selftest): + result = True + c = selftest.mbed.serial_readline() + if c is None or c.strip() != "0": + return selftest.RESULT_IO_SERIAL + + # Wait 10 seconds to allow serial prints (indicating failure) + selftest.mbed.set_serial_timeout(10) + + # If no characters received, pass the test + result = not selftest.mbed.serial_readline() + + return selftest.RESULT_SUCCESS if result else selftest.RESULT_FAILURE diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py index 815c292035..1f8060f4d3 100644 --- a/workspace_tools/tests.py +++ b/workspace_tools/tests.py @@ -66,7 +66,7 @@ Wiring: * analog_pot (AnalogIn): * Arduino headers: (A0, A1) - + * SD (SPI): * LPC1*: (mosi=p11 , miso=p12 , sclk=p13 , cs=p14 ) * KL25Z: (mosi=PTD2, miso=PTD3, sclk=PTD1, cs=PTD0) @@ -579,7 +579,12 @@ TESTS = [ "automated": True, "duration": 10, }, - + { + "id": "MBED_36", "description": "WFI correct behavior", + "source_dir": join(TEST_DIR, "mbed", "wfi"), + "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB], + "automated": True + }, # CMSIS RTOS tests { From 5fb844ce8701e585254cec2d7ae19965d5fb03b7 Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Fri, 22 May 2015 08:04:37 +0900 Subject: [PATCH 07/26] Change startup code for toolchain ARM Add possible toolchain ARM at targets.py --- .../TOOLCHAIN_ARM_MICRO/startup_W7500x.s | 6 +++--- workspace_tools/targets.py | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s index 1cbb5d3f56..410655e1f7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s @@ -31,18 +31,18 @@ ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Stack_Size EQU 0x00000200 +Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size -__initial_sp +__initial_sp EQU 0x20004000 ; Top of RAM (8 KB for STM32F030R8) ; Heap Configuration ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Heap_Size EQU 0x00000100 +Heap_Size EQU 0x00000400 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 0b148f35c2..47e38db303 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -76,8 +76,8 @@ class WIZwiki_W7500(Target): Target.__init__(self) self.core = "Cortex-M0" self.extra_labels = ['WIZNET', 'W7500x', 'WIZwiki_W7500'] - self.supported_toolchains = ["uARM",] - self.default_toolchain = "uARM" + self.supported_toolchains = ["uARM", "ARM"] + self.default_toolchain = "ARM" self.supported_form_factors = ["ARDUINO"] From feb9f51e2c6e572ca8adf57ed3ba18548b1e0444 Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Fri, 22 May 2015 09:34:46 +0900 Subject: [PATCH 08/26] Now, we support toolchain ARM. So Add the files. --- .../TOOLCHAIN_ARM_STD/W7500.sct | 15 ++ .../TOOLCHAIN_ARM_STD/startup_W7500x.s | 186 ++++++++++++++++++ .../TOOLCHAIN_ARM_STD/sys.cpp | 31 +++ .../TARGET_WIZwiki_W7500/device.h | 2 +- 4 files changed, 233 insertions(+), 1 deletion(-) create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/W7500.sct create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/startup_W7500x.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/sys.cpp diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/W7500.sct b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/W7500.sct new file mode 100644 index 0000000000..f9ead04667 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/W7500.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00020000 { ; load region size_region + ER_IROM1 0x00000000 0x00020000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00004000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/startup_W7500x.s b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/startup_W7500x.s new file mode 100644 index 0000000000..5b161ed02e --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/startup_W7500x.s @@ -0,0 +1,186 @@ +;/**************************************************************************//** +; * @file startup_CMSDK_CM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File for +; * Device CMSDK_CM0 +; * @version V3.01 +; * @date 06. March 2012 +; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER + +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +__initial_sp EQU 0x20004000 ; Top of RAM (16 KB for WIZwiki_W7500) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + DCD SSP0_Handler ; 16+ 0: SSP 0 Handler + DCD SSP1_Handler ; 16+ 1: SSP 1 Handler + DCD UART0_Handler ; 16+ 2: UART 0 Handler + DCD UART1_Handler ; 16+ 3: UART 1 Handler + DCD UART2_Handler ; 16+ 4: UART 2 Handler + DCD I2C0_Handler ; 16+ 5: I2C 0 Handler + DCD I2C1_Handler ; 16+ 6: I2C 1 Handler + DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler + DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler + DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler + DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler + DCD DMA_Handler ; 16+11: DMA Combined Handler + DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler + DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler + DCD PWM0_Handler ; 16+14: PWM0 Handler + DCD PWM1_Handler ; 16+15: PWM1 Handler + DCD PWM2_Handler ; 16+16: PWM2 Handler + DCD PWM3_Handler ; 16+17: PWM3 Handler + DCD PWM4_Handler ; 16+18: PWM4 Handler + DCD PWM5_Handler ; 16+19: PWM5 Handler + DCD PWM6_Handler ; 16+20: PWM6 Handler + DCD PWM7_Handler ; 16+21: PWM7 Handler + DCD RTC_Handler ; 16+22: RTC Handler + DCD ADC_Handler ; 16+23: ADC Handler + DCD WZTOE_Handler ; 16+24: WZTOE_Handler + DCD EXTI_Handler ; 16+25: EXTI_Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Default_Handler PROC + EXPORT SSP0_Handler [WEAK] + EXPORT SSP1_Handler [WEAK] + EXPORT UART0_Handler [WEAK] + EXPORT UART1_Handler [WEAK] + EXPORT UART2_Handler [WEAK] + EXPORT I2C0_Handler [WEAK] + EXPORT I2C1_Handler [WEAK] + EXPORT PORT0_Handler [WEAK] + EXPORT PORT1_Handler [WEAK] + EXPORT PORT2_Handler [WEAK] + EXPORT PORT3_Handler [WEAK] + EXPORT DMA_Handler [WEAK] + EXPORT DUALTIMER0_Handler [WEAK] + EXPORT DUALTIMER1_Handler [WEAK] + EXPORT PWM0_Handler [WEAK] + EXPORT PWM1_Handler [WEAK] + EXPORT PWM2_Handler [WEAK] + EXPORT PWM3_Handler [WEAK] + EXPORT PWM4_Handler [WEAK] + EXPORT PWM5_Handler [WEAK] + EXPORT PWM6_Handler [WEAK] + EXPORT PWM7_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT WZTOE_Handler [WEAK] + EXPORT EXTI_Handler [WEAK] +SSP0_Handler +SSP1_Handler +UART0_Handler +UART1_Handler +UART2_Handler +I2C0_Handler +I2C1_Handler +PORT0_Handler +PORT1_Handler +PORT2_Handler +PORT3_Handler +DMA_Handler +DUALTIMER0_Handler +DUALTIMER1_Handler +PWM0_Handler +PWM1_Handler +PWM2_Handler +PWM3_Handler +PWM4_Handler +PWM5_Handler +PWM6_Handler +PWM7_Handler +RTC_Handler +ADC_Handler +WZTOE_Handler +EXTI_Handler + B . + ENDP + + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..2f1024ace8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library - stackheap + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h index f94476da70..aae25ad347 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h @@ -52,7 +52,7 @@ #define DEVICE_PWMOUT 0 -#define DEVICE_SLEEP 1 +#define DEVICE_SLEEP 0 #define DEVICE_ETHERNET 0 From 82dd920c7e12db5fb2e9372fa100bb75173aacfd Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Fri, 22 May 2015 09:44:03 +0900 Subject: [PATCH 09/26] Change Stack size and heap size to 0x400 --- .../TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s index 410655e1f7..124a5e65c8 100644 --- a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s @@ -35,7 +35,7 @@ Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20004000 ; Top of RAM (8 KB for STM32F030R8) +__initial_sp EQU 0x20004000 ; Top of RAM (16 KB for WIZwiki_W7500) ; Heap Configuration From 446bcdd7dfc185cc4ec1677d19bfce97a3d255aa Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Fri, 22 May 2015 10:05:40 +0900 Subject: [PATCH 10/26] Change header scripts about PeripheralPins.c and PeripheralPins.h --- .../TARGET_W7500x/PeripheralPins.h | 30 ++++++++++++++++ .../TARGET_WIZwiki_W7500/PeripheralPins.c | 36 ++++++------------- 2 files changed, 40 insertions(+), 26 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h index 9a5d507fa7..2a42b0b568 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h @@ -1,3 +1,33 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ #ifndef MBED_PERIPHERALPINS_H #define MBED_PERIPHERALPINS_H diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c index 136a93f8cb..85d7195dea 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c @@ -1,34 +1,18 @@ /* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. + * Copyright (c) 2006-2013 ARM Limited * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * http://www.apache.org/licenses/LICENSE-2.0 * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ - #include "PeripheralPins.h" #include "PeripheralNames.h" #include "pinmap.h" From 8fae6b7a85f39a28f9fc75ee862fbce1a06d35d3 Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Fri, 22 May 2015 10:42:56 +0900 Subject: [PATCH 11/26] Change to static. --- .../mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c index af28f7924e..1a2c52af9f 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c @@ -27,7 +27,7 @@ ADC_TypeDef * AdcHandle; -int adc_inited = 0; +static int adc_inited = 0; void analogin_init(analogin_t *obj, PinName pin) { From fef219f493d2f4957ff86c2c501b38714cfc1ace Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Fri, 22 May 2015 14:08:01 +0900 Subject: [PATCH 12/26] Disable I2C slave --- .../TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h index aae25ad347..8299147f84 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h @@ -43,7 +43,7 @@ #define DEVICE_SERIAL 1 #define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 +#define DEVICE_I2CSLAVE 0 #define DEVICE_SPI 1 #define DEVICE_SPISLAVE 1 From 1cb4afc60b8e4260e20617b35d5811e934117bb5 Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Fri, 22 May 2015 10:16:05 -0500 Subject: [PATCH 13/26] Returns IO_FAIL when inital output is incorrect instead of IO_SERIAL --- workspace_tools/host_tests/wfi_auto.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/workspace_tools/host_tests/wfi_auto.py b/workspace_tools/host_tests/wfi_auto.py index b51beca13f..5f9e211548 100644 --- a/workspace_tools/host_tests/wfi_auto.py +++ b/workspace_tools/host_tests/wfi_auto.py @@ -25,9 +25,13 @@ class WFITest(): def test(self, selftest): result = True c = selftest.mbed.serial_readline() - if c is None or c.strip() != "0": + + if c is None return selftest.RESULT_IO_SERIAL + if c.strip() != "0": + return selftest.RESULT_IO_FAIL + # Wait 10 seconds to allow serial prints (indicating failure) selftest.mbed.set_serial_timeout(10) From 39c887c769f3e4a4ed0e13ad7cc1452a3171437f Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Tue, 26 May 2015 08:55:30 +0900 Subject: [PATCH 14/26] Bug fixed for test MBED_24(Timeout) --- .../mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c index 5320ed3da9..29735e4307 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c @@ -82,8 +82,9 @@ void us_ticker_set_interrupt(timestamp_t timestamp) { us_ticker_init(); } + + dev = (int32_t)(timestamp - (us_ticker_read() + 150)); - dev = (timestamp - us_ticker_read() + 0x5153); if(dev <= 0) { us_ticker_irq_handler(); @@ -92,6 +93,7 @@ void us_ticker_set_interrupt(timestamp_t timestamp) PWM_CHn_Stop(TIM_MST6); + SystemCoreClockUpdate(); TimMasterHandle_CH6.PWM_CHn_PR = (GetSystemClock() / 1000000) -1; TimMasterHandle_CH6.PWM_CHn_LR = dev; From 12a708f8b5f09943219fad44d408a2297dd7fcda Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Tue, 26 May 2015 10:24:44 -0500 Subject: [PATCH 15/26] Fixed return status of test --- workspace_tools/host_tests/wfi_auto.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/workspace_tools/host_tests/wfi_auto.py b/workspace_tools/host_tests/wfi_auto.py index 5f9e211548..3c5d10c716 100644 --- a/workspace_tools/host_tests/wfi_auto.py +++ b/workspace_tools/host_tests/wfi_auto.py @@ -30,7 +30,7 @@ class WFITest(): return selftest.RESULT_IO_SERIAL if c.strip() != "0": - return selftest.RESULT_IO_FAIL + return selftest.RESULT_FAILURE # Wait 10 seconds to allow serial prints (indicating failure) selftest.mbed.set_serial_timeout(10) From f0f89fc9a4674b8b127d9fd6e0436e516938bd26 Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Wed, 27 May 2015 10:52:34 +0900 Subject: [PATCH 16/26] remove gpio_irq_api.c because not complete --- .../TARGET_W7500x/gpio_irq_api.c | 148 ------------------ 1 file changed, 148 deletions(-) delete mode 100644 libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c deleted file mode 100644 index 57a8e004f9..0000000000 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c +++ /dev/null @@ -1,148 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "cmsis.h" -#include "gpio_irq_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -#define EDGE_NONE (0) -#define EDGE_RISE (1) -#define EDGE_FALL (2) -#define EDGE_BOTH (3) - -static gpio_irq_handler irq_handler; - - -typedef struct gpio_channel { - uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts - uint32_t channel_ids; // mbed "gpio_irq_t gpio_irq" field of instance - uint32_t channel_pin; // pin number in port group - gpio_irq_t * obj; -} gpio_channel_t; - -static gpio_channel_t channel; - -#ifdef __cplusplus -extern "C"{ -#endif -void EXTI_Handler() -{ - // To Do - //irq_handler(channel.channel_ids); -} -#ifdef __cplusplus -} -#endif - - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t gpio_pin; - - if (pin == NC) return -1; - - uint32_t port_index = WIZ_PORT(pin); - uint32_t pin_index = WIZ_PIN(pin); - - // If port_index is not GPIOC, return -1 - if (port_index != 2 ) { - error("InterruptIn error: pin not supported.\n"); - return -1; - } - - // Select irq number and interrupt routine - if ((pin_index == 0) || (pin_index == 1) || (pin_index == 4) || (pin_index == 6) || (pin_index == 7)) { - irq_n = EXTI_IRQn; - gpio_pin = 1 << pin_index; - } else { - error("InterruptIn error: pin not supported.\n"); - return -1; - } - - // Enable GPIO clock - uint32_t gpio_add = Get_GPIO_BaseAddress(port_index); - - // Configure GPIO - EXTI_InitTypeDef EXTI_InitDef; - EXTI_InitDef.EXTI_Line = gpio_pin; - EXTI_InitDef.EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_Init(gpio_add, &EXTI_InitDef); - - // Enable EXTI interrupt - NVIC_ClearPendingIRQ(irq_n); // Pending bit Clear - NVIC_EnableIRQ(irq_n); - - obj->irq_n = irq_n; -// obj->irq_index = irq_index; - obj->event = EDGE_FALL; - obj->pin = pin; - - channel.channel_pin = pin_index; - channel.pin_mask = gpio_pin; - channel.channel_ids = id; - channel.obj = obj; - - irq_handler = handler; - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - // Disable EXTI line - NVIC_ClearPendingIRQ(obj->irq_n); - EXTI_DeInit(); - pin_function(obj->pin, WIZ_PIN_DATA(WIZ_MODE_INPUT, WIZ_GPIO_NOPULL, 0)); - obj->event = EDGE_NONE; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - uint16_t porarity; - - if (enable) { - if (event == IRQ_RISE) { - porarity = EXTI_Trigger_Rising; - obj->event = EDGE_RISE; - } - if (event == IRQ_FALL) { - porarity = EXTI_Trigger_Falling; - obj->event = EDGE_FALL; - } - - uint32_t port_index = WIZ_PORT(obj->pin); - uint32_t pin_index = WIZ_PIN(obj->pin); - - // Enable GPIO clock - uint32_t gpio_add = Get_GPIO_BaseAddress(port_index); - EXTI_Polarity_Set(port_index,(1<irq_n); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - NVIC_DisableIRQ(obj->irq_n); - obj->event = EDGE_NONE; -} From ccd7e79d8ce72683211d17aa46e58bfa2413bf42 Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Wed, 27 May 2015 17:38:27 +0900 Subject: [PATCH 17/26] Add WIZwiki_W7500 in build_release.py --- workspace_tools/build_release.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 5d1dc812a0..b3312a3655 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -98,6 +98,8 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('EFM32WG_STK3800', ('ARM', 'GCC_ARM', 'uARM')), ('MAXWSNENV', ('ARM', 'GCC_ARM', 'IAR')), + + ('WIZwiki_W7500', ('ARM', 'uARM')), ) From f1040bdd04241610f649d444d9634745b04e0815 Mon Sep 17 00:00:00 2001 From: bcostm Date: Mon, 1 Jun 2015 12:18:02 +0200 Subject: [PATCH 18/26] [DISCO_F334C8] Add uVision and IAR exporters --- .../export/iar_disco_f334c8.ewd.tmpl | 2733 +++++++++++++++++ .../export/iar_disco_f334c8.ewp.tmpl | 1899 ++++++++++++ .../export/uvision4_disco_f334c8.uvopt.tmpl | 208 ++ .../export/uvision4_disco_f334c8.uvproj.tmpl | 438 +++ 4 files changed, 5278 insertions(+) create mode 100644 workspace_tools/export/iar_disco_f334c8.ewd.tmpl create mode 100644 workspace_tools/export/iar_disco_f334c8.ewp.tmpl create mode 100644 workspace_tools/export/uvision4_disco_f334c8.uvopt.tmpl create mode 100644 workspace_tools/export/uvision4_disco_f334c8.uvproj.tmpl diff --git a/workspace_tools/export/iar_disco_f334c8.ewd.tmpl b/workspace_tools/export/iar_disco_f334c8.ewd.tmpl new file mode 100644 index 0000000000..1b9216e2ee --- /dev/null +++ b/workspace_tools/export/iar_disco_f334c8.ewd.tmpl @@ -0,0 +1,2733 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + IJET_ID + 2 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 5 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 15 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/workspace_tools/export/iar_disco_f334c8.ewp.tmpl b/workspace_tools/export/iar_disco_f334c8.ewp.tmpl new file mode 100644 index 0000000000..7f267e6463 --- /dev/null +++ b/workspace_tools/export/iar_disco_f334c8.ewp.tmpl @@ -0,0 +1,1899 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + {{source_files}} + + + diff --git a/workspace_tools/export/uvision4_disco_f334c8.uvopt.tmpl b/workspace_tools/export/uvision4_disco_f334c8.uvopt.tmpl new file mode 100644 index 0000000000..9f37a88940 --- /dev/null +++ b/workspace_tools/export/uvision4_disco_f334c8.uvopt.tmpl @@ -0,0 +1,208 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + mbed DISCO_F334C8 + 0x4 + ARM-ADS + + 72000000 + + 1 + 1 + 0 + 1 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 11 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U -O206 -S3 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F3xx_256.FLM -FS08000000 -FL040000 -FP0($$Device:STM32F302RC$Flash\STM32F3xx_256.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F3xx_256 -FL040000 -FS08000000 -FP0($$Device:STM32F302RC$Flash\STM32F3xx_256.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + src + 1 + 0 + 0 + 0 + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + main.cpp + main.cpp + 0 + 0 + + + + diff --git a/workspace_tools/export/uvision4_disco_f334c8.uvproj.tmpl b/workspace_tools/export/uvision4_disco_f334c8.uvproj.tmpl new file mode 100644 index 0000000000..5651bac46c --- /dev/null +++ b/workspace_tools/export/uvision4_disco_f334c8.uvproj.tmpl @@ -0,0 +1,438 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + mbed DISCO_F334C8 + 0x4 + ARM-ADS + + + STM32F334C8 + STMicroelectronics + IROM(0x08000000,0x40000) IRAM(0x20000000,0x8000) CPUTYPE("Cortex-M4") FPU2 CLOCK(72000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F3xx_256 -FS08000000 -FL040000 -FP0($$Device:STM32F302RC$Flash\STM32F3xx_256.FLM)) + 6576 + $$Device:STM32F302RC$Device\Include\STM32F30x.h + + + + + + + + + + $$Device:STM32F302RC$SVD\STM32F30x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + fromelf --bin -o build\{{name}}_DISCO_F334C8.bin build\{{name}}.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + + 0 + 11 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x8000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + + + {% endfor %} + + + {% endfor %} + + + + + From 17335f493569458f1447ec01ffd7242debed1a7f Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Mon, 1 Jun 2015 12:09:35 -0500 Subject: [PATCH 19/26] Fixed syntax error --- workspace_tools/host_tests/wfi_auto.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/workspace_tools/host_tests/wfi_auto.py b/workspace_tools/host_tests/wfi_auto.py index 3c5d10c716..63b3b3c760 100644 --- a/workspace_tools/host_tests/wfi_auto.py +++ b/workspace_tools/host_tests/wfi_auto.py @@ -26,7 +26,7 @@ class WFITest(): result = True c = selftest.mbed.serial_readline() - if c is None + if c == None: return selftest.RESULT_IO_SERIAL if c.strip() != "0": From a417bc4114f202b35fb9fbda654882397138b03c Mon Sep 17 00:00:00 2001 From: Brian Daniels Date: Mon, 1 Jun 2015 12:16:37 -0500 Subject: [PATCH 20/26] Added host test info --- workspace_tools/host_tests/wfi_auto.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/workspace_tools/host_tests/wfi_auto.py b/workspace_tools/host_tests/wfi_auto.py index 63b3b3c760..a62c432068 100644 --- a/workspace_tools/host_tests/wfi_auto.py +++ b/workspace_tools/host_tests/wfi_auto.py @@ -23,19 +23,23 @@ from sys import stdout class WFITest(): def test(self, selftest): - result = True c = selftest.mbed.serial_readline() if c == None: + selftest.notify("HOST: No output detected") return selftest.RESULT_IO_SERIAL if c.strip() != "0": + selftest.notify("HOST: Unexpected output. Expected '0' but received '%s'" % c.strip()) return selftest.RESULT_FAILURE # Wait 10 seconds to allow serial prints (indicating failure) selftest.mbed.set_serial_timeout(10) # If no characters received, pass the test - result = not selftest.mbed.serial_readline() - - return selftest.RESULT_SUCCESS if result else selftest.RESULT_FAILURE + if not selftest.mbed.serial_readline(): + selftest.notify("HOST: No further output detected") + return selftest.RESULT_SUCCESS + else: + selftest.notify("HOST: Extra output detected") + return selftest.RESULT_FAILURE From 86a6703ef54d682bb856ef5ee5cd8d429654ea3e Mon Sep 17 00:00:00 2001 From: hjjeon0608 Date: Tue, 2 Jun 2015 11:01:27 +0900 Subject: [PATCH 21/26] Change header about license. --- .../TARGET_W7500x/PeripheralPins.h | 6 +-- .../TARGET_WIZwiki_W7500/PeripheralNames.h | 6 +-- .../TARGET_WIZwiki_W7500/PeripheralPins.c | 37 ++++++++++++------ .../TARGET_WIZwiki_W7500/PinNames.h | 6 +-- .../TARGET_WIZwiki_W7500/PortNames.h | 6 +-- .../TARGET_WIZwiki_W7500/device.h | 6 +-- .../TARGET_WIZwiki_W7500/objects.h | 6 +-- .../TARGET_W7500x/analogin_api.c | 36 ++++++++++++------ .../TARGET_WIZNET/TARGET_W7500x/gpio_api.c | 37 ++++++++++++------ .../TARGET_WIZNET/TARGET_W7500x/gpio_object.h | 37 ++++++++++++------ .../hal/TARGET_WIZNET/TARGET_W7500x/i2c_api.c | 6 +-- .../TARGET_W7500x/mbed_overrides.c | 38 +++++++++++++------ .../hal/TARGET_WIZNET/TARGET_W7500x/pinmap.c | 37 ++++++++++++------ .../TARGET_WIZNET/TARGET_W7500x/port_api.c | 37 ++++++++++++------ .../TARGET_WIZNET/TARGET_W7500x/serial_api.c | 30 +++++++++++++++ .../hal/TARGET_WIZNET/TARGET_W7500x/sleep.c | 5 +-- .../hal/TARGET_WIZNET/TARGET_W7500x/spi_api.c | 37 ++++++++++++------ .../TARGET_WIZNET/TARGET_W7500x/us_ticker.c | 36 ++++++++++++------ 18 files changed, 285 insertions(+), 124 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h index 2a42b0b568..3b116bec23 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h @@ -1,7 +1,6 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors +/* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,6 +27,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ + #ifndef MBED_PERIPHERALPINS_H #define MBED_PERIPHERALPINS_H diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralNames.h index e0bacfc987..0104e82a3c 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralNames.h @@ -1,7 +1,6 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors +/* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,6 +27,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ + #ifndef MBED_PERIPHERALNAMES_H #define MBED_PERIPHERALNAMES_H diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c index 85d7195dea..f97f158ef9 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c @@ -1,18 +1,33 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. + * All rights reserved. * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* */ + #include "PeripheralPins.h" #include "PeripheralNames.h" #include "pinmap.h" diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PinNames.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PinNames.h index 5233ccec2d..18ceb4e4c1 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PinNames.h @@ -1,7 +1,6 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors +/* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,6 +27,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ + #ifndef MBED_PINNAMES_H #define MBED_PINNAMES_H diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PortNames.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PortNames.h index 0eb8287078..6a8638752e 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PortNames.h +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PortNames.h @@ -1,7 +1,6 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors +/* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,6 +27,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ + #ifndef MBED_PORTNAMES_H #define MBED_PORTNAMES_H diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h index 8299147f84..e7d0398b33 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h @@ -1,7 +1,6 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors +/* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,6 +27,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ + #ifndef MBED_DEVICE_H #define MBED_DEVICE_H diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/objects.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/objects.h index 7a3b8967ba..7d7244288e 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/objects.h +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/objects.h @@ -1,7 +1,6 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors +/* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,6 +27,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ + #ifndef MBED_OBJECTS_H #define MBED_OBJECTS_H diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c index 1a2c52af9f..0725ce673a 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c @@ -1,17 +1,31 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. + * All rights reserved. * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* */ #include "mbed_assert.h" diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_api.c index 635a73c176..73145f149c 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_api.c +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_api.c @@ -1,18 +1,33 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. + * All rights reserved. * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* */ + #include "mbed_assert.h" #include "gpio_api.h" #include "pinmap.h" diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_object.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_object.h index 42472bead6..d84d665663 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_object.h @@ -1,18 +1,33 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. + * All rights reserved. * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* */ + #ifndef MBED_GPIO_OBJECT_H #define MBED_GPIO_OBJECT_H diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/i2c_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/i2c_api.c index 0e6bb4f04b..8a6f22a442 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/i2c_api.c @@ -1,7 +1,6 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors +/* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,6 +27,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ + #include "mbed_assert.h" #include "i2c_api.h" diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/mbed_overrides.c index 3e7b4fb61a..93d9c582c1 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/mbed_overrides.c +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/mbed_overrides.c @@ -1,19 +1,33 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. + * All rights reserved. * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* */ - + #include "cmsis.h" // This function is called after RAM initialization and before main. diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pinmap.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pinmap.c index dd37dec726..0584cf14a0 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pinmap.c +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/pinmap.c @@ -1,18 +1,33 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. + * All rights reserved. * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* */ + #include "mbed_assert.h" #include "pinmap.h" #include "PortNames.h" diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/port_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/port_api.c index 3680a48b2d..51cec9c93d 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/port_api.c +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/port_api.c @@ -1,18 +1,33 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. + * All rights reserved. * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* */ + #include "port_api.h" #include "pinmap.h" #include "gpio_api.h" diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c index 110b46a20e..8867d39f80 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c @@ -1,3 +1,33 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + #include "mbed_assert.h" #include "serial_api.h" diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/sleep.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/sleep.c index 81ed6b36d6..30a8716736 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/sleep.c +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/sleep.c @@ -1,7 +1,6 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors +/* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/spi_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/spi_api.c index c37942b73e..f5566e02da 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/spi_api.c @@ -1,18 +1,33 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. + * All rights reserved. * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* */ + #include "mbed_assert.h" #include diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c index 29735e4307..f427274c12 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c @@ -1,17 +1,31 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. + * All rights reserved. * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* */ #include From 204e71641702774e19f6f13675ec076c7d6ba430 Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Tue, 2 Jun 2015 10:11:44 +0200 Subject: [PATCH 22/26] * [PwmOut] Fixed same bug as pulsewidth_us in period_us * [PwmOut] Get rid of superfluous static uint32_t, save 4 bytes of RAM in static allocation. * [PwmOut] Use 16-bit values for saving the top and CC register of the timer to RAM. Saves 4 bytes of RAM per PWM channel. --- .../TARGET_Silicon_Labs/TARGET_EFM32/objects.h | 4 ++-- .../TARGET_EFM32/pwmout_api.c | 18 ++++++++---------- 2 files changed, 10 insertions(+), 12 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/objects.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/objects.h index d3c8b9ea4f..986bc761e2 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/objects.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/objects.h @@ -68,9 +68,9 @@ struct port_s { #if DEVICE_PWMOUT struct pwmout_s { //The period of the pulse in clock cycles - uint32_t period_cycles; + uint16_t period_cycles; //The width of the pulse in clock cycles - uint32_t width_cycles; + uint16_t width_cycles; //Channel on TIMER uint32_t channel; PinName pin; diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c index f956f57533..cd8f45f17b 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c @@ -30,7 +30,6 @@ #include "em_gpio.h" #include "em_timer.h" -static int pwm_clockfreq; static int pwm_prescaler_div; uint32_t pwmout_get_channel_route(pwmout_t *obj) @@ -109,9 +108,6 @@ void pwmout_init(pwmout_t *obj, PinName pin) PWM_TIMER->ROUTE &= ~_TIMER_ROUTE_LOCATION_MASK; PWM_TIMER->ROUTE |= PWM_ROUTE; - /*HFPER is the default clock we will use. It has a frequency of 14MHz*/ - pwm_clockfreq = REFERENCE_FREQUENCY; - /* Set default 20ms frequency and 0ms pulse width */ pwmout_period(obj, 0.02); } @@ -139,7 +135,7 @@ void pwmout_write(pwmout_t *obj, float value) value = 1; } - float pulse_period_in_s = obj->period_cycles / ((float) (pwm_clockfreq >> pwm_prescaler_div)); + float pulse_period_in_s = obj->period_cycles / ((float) (REFERENCE_FREQUENCY >> pwm_prescaler_div)); pwmout_pulsewidth(obj, value * pulse_period_in_s); } @@ -155,7 +151,7 @@ void pwmout_period(pwmout_t *obj, float seconds) // This gives us max resolution for a given period //The value of the top register if prescaler is set to 0 - int cycles = pwm_clockfreq * seconds; + int cycles = REFERENCE_FREQUENCY * seconds; pwm_prescaler_div = 0; //The top register is only 16 bits, so we keep dividing till we are below 0xFFFF @@ -187,23 +183,25 @@ void pwmout_period_ms(pwmout_t *obj, int ms) void pwmout_period_us(pwmout_t *obj, int us) { - pwmout_period_ms(obj, us / 1000.0f); + pwmout_period(obj, us / 1000000.0f); } void pwmout_pulsewidth(pwmout_t *obj, float seconds) { - obj->width_cycles = (uint32_t) (((float) (pwm_clockfreq >> pwm_prescaler_div)) * seconds); + obj->width_cycles = (uint32_t) (((float) (REFERENCE_FREQUENCY >> pwm_prescaler_div)) * seconds); TIMER_CompareBufSet(PWM_TIMER, obj->channel, obj->width_cycles); } void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) { - pwmout_pulsewidth(obj, ms / 1000.0f); + obj->width_cycles = (uint32_t) ((REFERENCE_FREQUENCY >> pwm_prescaler_div) * ms) / 1000; + TIMER_CompareBufSet(PWM_TIMER, obj->channel, obj->width_cycles); } void pwmout_pulsewidth_us(pwmout_t *obj, int us) { - pwmout_pulsewidth_ms(obj, us / 1000.0f); + obj->width_cycles = (uint32_t) ((REFERENCE_FREQUENCY >> pwm_prescaler_div) * us) / 1000000; + TIMER_CompareBufSet(PWM_TIMER, obj->channel, obj->width_cycles); } #endif From 4b020f80e7b6a77def898b8ab31c3277bc5966f9 Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Tue, 2 Jun 2015 10:16:52 +0200 Subject: [PATCH 23/26] [GPIO] optimize memory usage: get rid of 8 bytes of RAM allocation per GPIO object. --- .../hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_api.c | 4 +--- .../TARGET_Silicon_Labs/TARGET_EFM32/gpio_object.h | 12 +++++------- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_api.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_api.c index cce9443ef1..f1c0566094 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_api.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_api.c @@ -42,8 +42,6 @@ void gpio_init(gpio_t *obj, PinName pin) CMU_ClockEnable(cmuClock_HFPER, true); CMU_ClockEnable(cmuClock_GPIO, true); obj->pin = pin; - obj->mask = gpio_set(pin); - obj->port = pin >> 4; } void gpio_pin_enable(gpio_t *obj, uint8_t enable) @@ -63,7 +61,7 @@ void gpio_mode(gpio_t *obj, PinMode mode) //Handle pullup for input if(mode == InputPullUp) { //Set DOUT - GPIO->P[obj->port & 0xF].DOUTSET = 1 << (obj->pin & 0xF); + GPIO->P[(obj->pin >> 4) & 0xF].DOUTSET = 1 << (obj->pin & 0xF); } } diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_object.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_object.h index ba23f311b4..9e2569728c 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_object.h @@ -25,27 +25,25 @@ extern "C" { typedef struct { PinName pin; - uint32_t mask; - GPIO_Port_TypeDef port; PinMode mode; - uint32_t dir; + PinDirection dir; } gpio_t; static inline void gpio_write(gpio_t *obj, int value) { if (value) { - GPIO_PinOutSet(obj->port, obj->pin & 0xF); // Pin number encoded in first four bits of obj->pin + GPIO_PinOutSet((GPIO_Port_TypeDef)((obj->pin >> 4) & 0xF), obj->pin & 0xF); // Pin number encoded in first four bits of obj->pin } else { - GPIO_PinOutClear(obj->port, obj->pin & 0xF); + GPIO_PinOutClear((GPIO_Port_TypeDef)((obj->pin >> 4) & 0xF), obj->pin & 0xF); } } static inline int gpio_read(gpio_t *obj) { if (obj->dir == PIN_INPUT) { - return GPIO_PinInGet(obj->port, obj->pin & 0xF); // Pin number encoded in first four bits of obj->pin + return GPIO_PinInGet((GPIO_Port_TypeDef)((obj->pin >> 4) & 0xF), obj->pin & 0xF); // Pin number encoded in first four bits of obj->pin } else { - return GPIO_PinOutGet(obj->port, obj->pin & 0xF); + return GPIO_PinOutGet((GPIO_Port_TypeDef)((obj->pin >> 4) & 0xF), obj->pin & 0xF); } } From 0abf0f3e410a7d53b9c9092c48a7d27f5c420667 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Wed, 3 Jun 2015 01:02:38 +0200 Subject: [PATCH 24/26] [STM32F4xx] PWM frequency calculation correction All STM32F4xx mcu with a clock frequency larger than 100MHz (F405, F407, F429, F446), have two different maximal timer frequencies: SYSCLK and SYSCLK/2. The pwm frequency calculation was based only on SYSCLK. For Nucleo target this was OK but for some Discovery and some other targets the pwm frequency was partly wrong, depending on the used timer. This PR reads out the specific timer frequency and calculates the correct pwm frequency. --- .../TARGET_STM/TARGET_STM32F4/pwmout_api.c | 73 ++++++++++++++++++- 1 file changed, 71 insertions(+), 2 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/pwmout_api.c index 767ec1297c..3820e46f1f 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/pwmout_api.c @@ -165,7 +165,9 @@ void pwmout_period_ms(pwmout_t* obj, int ms) void pwmout_period_us(pwmout_t* obj, int us) { TimHandle.Instance = (TIM_TypeDef *)(obj->pwm); - + RCC_ClkInitTypeDef RCC_ClkInitStruct; + uint32_t PclkFreq; + uint32_t APBxCLKDivider; float dc = pwmout_read(obj); __HAL_TIM_DISABLE(&TimHandle); @@ -173,8 +175,75 @@ void pwmout_period_us(pwmout_t* obj, int us) // Update the SystemCoreClock variable SystemCoreClockUpdate(); + HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &PclkFreq); + + switch (obj->pwm) { + + case PWM_1: + PclkFreq = HAL_RCC_GetPCLK2Freq(); + APBxCLKDivider = RCC_ClkInitStruct.APB2CLKDivider; + break; + + case PWM_2: + PclkFreq = HAL_RCC_GetPCLK1Freq(); + APBxCLKDivider = RCC_ClkInitStruct.APB1CLKDivider; + break; + + case PWM_3: + PclkFreq = HAL_RCC_GetPCLK1Freq(); + APBxCLKDivider = RCC_ClkInitStruct.APB1CLKDivider; + break; + + case PWM_4: + PclkFreq = HAL_RCC_GetPCLK1Freq(); + APBxCLKDivider = RCC_ClkInitStruct.APB1CLKDivider; + break; + +#if defined(TIM8_BASE) + case PWM_8: + PclkFreq = HAL_RCC_GetPCLK2Freq(); + APBxCLKDivider = RCC_ClkInitStruct.APB2CLKDivider; + break; +#endif + + case PWM_9: + PclkFreq = HAL_RCC_GetPCLK2Freq(); + APBxCLKDivider = RCC_ClkInitStruct.APB2CLKDivider; + break; + + case PWM_10: + PclkFreq = HAL_RCC_GetPCLK2Freq(); + APBxCLKDivider = RCC_ClkInitStruct.APB2CLKDivider; + break; + + case PWM_11: + PclkFreq = HAL_RCC_GetPCLK2Freq(); + APBxCLKDivider = RCC_ClkInitStruct.APB2CLKDivider; + break; + +#if defined(TIM13_BASE) + case PWM_13: + PclkFreq = HAL_RCC_GetPCLK1Freq(); + APBxCLKDivider = RCC_ClkInitStruct.APB1CLKDivider; + break; +#endif + +#if defined(TIM14_BASE) + case PWM_14: + PclkFreq = HAL_RCC_GetPCLK1Freq(); + APBxCLKDivider = RCC_ClkInitStruct.APB1CLKDivider; + break; +#endif + + default: + return; + } + TimHandle.Init.Period = us - 1; - TimHandle.Init.Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick + if (APBxCLKDivider == RCC_HCLK_DIV1) + TimHandle.Init.Prescaler = (uint16_t)((PclkFreq*2) / 1000000) - 1; // 1 µs tick + else + TimHandle.Init.Prescaler = (uint16_t)((PclkFreq) / 1000000) - 1; // 1 µs tick TimHandle.Init.ClockDivision = 0; TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; HAL_TIM_PWM_Init(&TimHandle); From 4b93618af68071c92bbdc1e239d9735b0c9aeb8a Mon Sep 17 00:00:00 2001 From: 0xc0170 Date: Wed, 3 Jun 2015 08:07:07 +0100 Subject: [PATCH 25/26] Squashed commit of the following (#1149 PR on github): commit 4810979575d8feccff1d6dc75ab24e3753c4e0f0 Merge: 83c82b0 0e23067 Author: 0xc0170 Date: Wed Jun 3 08:06:14 2015 +0100 Merge branch 'master' of https://github.com/screamerbg/mbed into screamerbg-master commit 0e23067718c61808401311bb594ed25fb4ed62c6 Author: Mihail Stoyanov Date: Tue Jun 2 16:08:08 2015 +0300 Add the Delta NNN40 platform to releases commit 62a585dcda553b6e3b5c84e90a55b465f0894863 Merge: e1cd545 7a1d25e Author: Mihail Stoyanov Date: Tue Jun 2 16:06:44 2015 +0300 Merge branch 'master' of https://github.com/mbedmicro/mbed Conflicts: workspace_tools/tests.py commit e1cd545a9c92c4177f72da964d50d163dae5990f Merge: 5c5e61f ffd5586 Author: Mihail Stoyanov Date: Thu May 7 13:07:48 2015 +0300 Merge branch 'master' of https://github.com/mbedmicro/mbed commit 5c5e61f0ac38d91ad04738fd33af36f91452d984 Author: Mihail Stoyanov Date: Thu May 7 13:07:35 2015 +0300 Remove the Disco L053 from RTOS tests as it's not ready yet commit e75efe346742fa22e124861fddf1b51c291f4219 Author: Mihail Stoyanov Date: Wed May 6 13:49:05 2015 +0300 Tidy up targets.py --- workspace_tools/build_release.py | 1 + workspace_tools/targets.py | 53 +++++++++++++++++++++----------- 2 files changed, 36 insertions(+), 18 deletions(-) diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 73ee358007..822f97eada 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -87,6 +87,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('RBLAB_NRF51822', ('ARM', 'GCC_ARM')), ('RBLAB_BLENANO', ('ARM', 'GCC_ARM')), ('WALLBOT_BLE', ('ARM', 'GCC_ARM')), + ('DELTA_DFCM_NNN40', ('ARM', 'GCC_ARM')), ('LPC11U68', ('ARM', 'uARM','GCC_ARM','GCC_CR', 'IAR')), ('OC_MBUINO', ('ARM', 'uARM', 'GCC_ARM', 'IAR')), diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 849ed9eb89..c39aec5784 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -844,7 +844,6 @@ class NZ32ST1L(Target): self.default_toolchain = "uARM" - ### Nordic ### class NRF51822(Target): @@ -1078,58 +1077,74 @@ class DELTA_DFCM_NNN40_OTA(NRF51822): self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'DELTA_DFCM_NNN40'] self.MERGE_SOFT_DEVICE = False self.macros += self.common_macros + + ### ARM ### -class ARM_MPS2_M0(Target): +class ARM_MPS2_Target(Target): def __init__(self): Target.__init__(self) + self.OUTPUT_EXT = 'axf' + + def init_hooks(self, hook, toolchain_name): + hook.hook_add_binary("replace", self.output_axf) + + @staticmethod + def output_axf(t_self, resources, elf, bin): + shutil.copy(elf, bin) + t_self.debug("Passing ELF file %s" % bin) + + +class ARM_MPS2_M0(ARM_MPS2_Target): + def __init__(self): + ARM_MPS2_Target.__init__(self) self.core = "Cortex-M0" - self.extra_labels = ['ARM_SSG', 'MPS2_M0'] + self.extra_labels = ['ARM_SSG', 'MPS2', 'MPS2_M0'] self.macros = ['CMSDK_CM0'] self.supported_toolchains = ["ARM", "GCC_ARM"] self.default_toolchain = "ARM" -class ARM_MPS2_M0P(Target): +class ARM_MPS2_M0P(ARM_MPS2_Target): def __init__(self): - Target.__init__(self) + ARM_MPS2_Target.__init__(self) self.core = "Cortex-M0+" - self.extra_labels = ['ARM_SSG', 'MPS2_M0P'] + self.extra_labels = ['ARM_SSG', 'MPS2', 'MPS2_M0P'] self.macros = ['CMSDK_CM0plus'] self.supported_toolchains = ["ARM", "GCC_ARM"] self.default_toolchain = "ARM" -class ARM_MPS2_M1(Target): +class ARM_MPS2_M1(ARM_MPS2_Target): def __init__(self): - Target.__init__(self) + ARM_MPS2_Target.__init__(self) self.core = "Cortex-M1" - self.extra_labels = ['ARM_SSG', 'MPS2_M1'] + self.extra_labels = ['ARM_SSG', 'MPS2', 'MPS2_M1'] self.macros = ['CMSDK_CM1'] self.supported_toolchains = ["ARM", "GCC_ARM"] self.default_toolchain = "ARM" -class ARM_MPS2_M3(Target): +class ARM_MPS2_M3(ARM_MPS2_Target): def __init__(self): - Target.__init__(self) + ARM_MPS2_Target.__init__(self) self.core = "Cortex-M3" - self.extra_labels = ['ARM_SSG', 'MPS2_M3'] + self.extra_labels = ['ARM_SSG', 'MPS2', 'MPS2_M3'] self.macros = ['CMSDK_CM3'] self.supported_toolchains = ["ARM", "GCC_ARM"] self.default_toolchain = "ARM" -class ARM_MPS2_M4(Target): +class ARM_MPS2_M4(ARM_MPS2_Target): def __init__(self): - Target.__init__(self) + ARM_MPS2_Target.__init__(self) self.core = "Cortex-M4F" - self.extra_labels = ['ARM_SSG', 'MPS2_M4'] + self.extra_labels = ['ARM_SSG', 'MPS2', 'MPS2_M4'] self.macros = ['CMSDK_CM4'] self.supported_toolchains = ["ARM", "GCC_ARM"] self.default_toolchain = "ARM" -class ARM_MPS2_M7(Target): +class ARM_MPS2_M7(ARM_MPS2_Target): def __init__(self): - Target.__init__(self) + ARM_MPS2_Target.__init__(self) self.core = "Cortex-M7F" - self.extra_labels = ['ARM_SSG', 'MPS2_M7'] + self.extra_labels = ['ARM_SSG', 'MPS2', 'MPS2_M7'] self.macros = ['CMSDK_CM7'] self.supported_toolchains = ["ARM", "GCC_ARM"] self.default_toolchain = "ARM" @@ -1173,7 +1188,9 @@ class MAX32600MBED(Target): self.supported_toolchains = ["GCC_ARM", "IAR", "ARM"] self.default_toolchain = "ARM" + ### Silicon Labs ### + class EFM32GG_STK3700(Target): def __init__(self): Target.__init__(self) From 56e43df1c7e87296c22fc4b4c68222b7ccc3df50 Mon Sep 17 00:00:00 2001 From: Toyomasa Watarai Date: Wed, 3 Jun 2015 16:13:06 +0900 Subject: [PATCH 26/26] [SSCI824] Add rtos - Add rtos TARGET_SSCI824 (same as LPC824) and test - Fixed warning of pwmout_api.c by GCC_ARM --- .../hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c | 2 +- libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h | 2 +- libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c | 8 +++++--- workspace_tools/tests.py | 16 ++++++++-------- 4 files changed, 15 insertions(+), 13 deletions(-) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c index 05c5113e46..38ef6b9f8f 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c @@ -36,7 +36,7 @@ static int get_available_sct() void pwmout_init(pwmout_t* obj, PinName pin) { - MBED_ASSERT(pin != (uint32_t)NC); + MBED_ASSERT(pin != (PinName)NC); int sct_n = get_available_sct(); if (sct_n == -1) { diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h index a6fee43e52..c0931f414a 100755 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h @@ -214,7 +214,7 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL} #elif defined(TARGET_LPC812) #define INITIAL_SP (0x10001000UL) -#elif defined(TARGET_LPC824) +#elif defined(TARGET_LPC824) || defined(TARGET_SSCI824) #define INITIAL_SP (0x10002000UL) #elif defined(TARGET_KL25Z) diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c index 1ca6c13995..b247dd88dc 100755 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c @@ -57,7 +57,8 @@ # elif defined(TARGET_LPC11U24) || defined(TARGET_STM32F303RE) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) \ - || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) || defined(TARGET_NZ32ST1L) + || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) || defined(TARGET_NZ32ST1L) \ + || defined(TARGET_SSCI824) # define OS_TASKCNT 6 # else # error "no target defined" @@ -73,7 +74,8 @@ # define OS_SCHEDULERSTKSIZE 256 # elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ - || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) || defined(TARGET_NZ32ST1L) + || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) || defined(TARGET_NZ32ST1L) \ + || defined(TARGET_SSCI824) # define OS_SCHEDULERSTKSIZE 128 # elif defined(TARGET_STM32F334R8) || defined(TARGET_STM32F303RE) || defined(TARGET_STM32F334C8) || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) # define OS_SCHEDULERSTKSIZE 112 @@ -131,7 +133,7 @@ # elif defined(TARGET_LPC812) # define OS_CLOCK 36000000 -# elif defined(TARGET_LPC824) +# elif defined(TARGET_LPC824) || defined(TARGET_SSCI824) # define OS_CLOCK 30000000 # elif defined(TARGET_STM32F100RB) diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py index 4c6e252bdc..d03fd71ea6 100644 --- a/workspace_tools/tests.py +++ b/workspace_tools/tests.py @@ -635,7 +635,7 @@ TESTS = [ "duration": 15, "automated": True, #"host_test": "wait_us_auto", - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", @@ -648,7 +648,7 @@ TESTS = [ "dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB], "duration": 20, "automated": True, - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", @@ -661,7 +661,7 @@ TESTS = [ "dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB], "duration": 20, "automated": True, - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", @@ -673,7 +673,7 @@ TESTS = [ "source_dir": join(TEST_DIR, "rtos", "mbed", "signals"), "dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB], "automated": True, - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", @@ -685,7 +685,7 @@ TESTS = [ "source_dir": join(TEST_DIR, "rtos", "mbed", "queue"), "dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB], "automated": True, - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", @@ -697,7 +697,7 @@ TESTS = [ "source_dir": join(TEST_DIR, "rtos", "mbed", "mail"), "dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB], "automated": True, - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", @@ -711,7 +711,7 @@ TESTS = [ "duration": 15, "automated": True, #"host_test": "wait_us_auto", - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", @@ -723,7 +723,7 @@ TESTS = [ "source_dir": join(TEST_DIR, "rtos", "mbed", "isr"), "dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB], "automated": True, - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8",