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Refine coding style

pull/4974/head
ccli8 2017-07-05 17:40:55 +08:00 committed by adbridge
parent abd8dee9e5
commit 592f46b382
18 changed files with 1037 additions and 1073 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

68
targets/TARGET_NUVOTON/TARGET_M480/can_api.c
View File

@ -14,26 +14,26 @@
* limitations under the License.
*/
#include "can_api.h"
#include "m480_gpio.h"
#include "m480_can.h"
#include "can_api.h"
#include "m480_gpio.h"
#include "m480_can.h"
#if DEVICE_CAN
#include <string.h>
#include "cmsis.h"
#include "pinmap.h"
#include "PeripheralPins.h"
#include "nu_modutil.h"
#include "nu_miscutil.h"
#include "nu_bitutil.h"
#include "mbed_critical.h"
#if DEVICE_CAN
#include <string.h>
#include "cmsis.h"
#include "pinmap.h"
#include "PeripheralPins.h"
#include "nu_modutil.h"
#include "nu_miscutil.h"
#include "nu_bitutil.h"
#include "mbed_critical.h"
#define NU_CAN_DEBUG 0
#define CAN_NUM 2
#define NU_CAN_DEBUG 0
#define CAN_NUM 2
static uint32_t can_irq_ids[CAN_NUM] = {0};
static can_irq_handler can0_irq_handler;
static can_irq_handler can1_irq_handler;
static uint32_t can_irq_ids[CAN_NUM] = {0};
static can_irq_handler can0_irq_handler;
static can_irq_handler can1_irq_handler;
extern uint32_t CAN_GetCANBitRate(CAN_T *tCAN);
extern void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask);
@ -41,7 +41,7 @@ extern void CAN_LeaveInitMode(CAN_T *tCAN);
extern void CAN_LeaveTestMode(CAN_T *tCAN);
extern void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask);
static const struct nu_modinit_s can_modinit_tab[] = {
static const struct nu_modinit_s can_modinit_tab[] = {
{CAN_0, CAN0_MODULE, 0, 0, CAN0_RST, CAN0_IRQn, NULL},
{CAN_1, CAN1_MODULE, 0, 0, CAN1_RST, CAN1_IRQn, NULL},
@ -70,8 +70,7 @@ void can_init_freq(can_t *obj, PinName rd, PinName td, int hz)
if(obj->can == CAN_1) {
obj->index = 1;
}
else
} else
obj->index = 0;
pinmap_pinout(td, PinMap_CAN_TD);
@ -85,7 +84,7 @@ void can_init_freq(can_t *obj, PinName rd, PinName td, int hz)
CAN_Open((CAN_T *)NU_MODBASE(obj->can), hz, CAN_NORMAL_MODE);
can_filter(obj, 0, 0, CANStandard, 0);
}
}
void can_init(can_t *obj, PinName rd, PinName td)
{
@ -128,7 +127,7 @@ static void can_irq(CANName name, int id)
if(can->STATUS & CAN_STATUS_RXOK_Msk) {
can->STATUS &= ~CAN_STATUS_RXOK_Msk; /* Clear Rx Ok status*/
if(id)
can1_irq_handler(can_irq_ids[id] , IRQ_RX);
can1_irq_handler(can_irq_ids[id], IRQ_RX);
else
can0_irq_handler(can_irq_ids[id], IRQ_RX);
}
@ -136,7 +135,7 @@ static void can_irq(CANName name, int id)
if(can->STATUS & CAN_STATUS_TXOK_Msk) {
can->STATUS &= ~CAN_STATUS_TXOK_Msk; /* Clear Tx Ok status*/
if(id)
can1_irq_handler(can_irq_ids[id] , IRQ_TX);
can1_irq_handler(can_irq_ids[id], IRQ_TX);
else
can0_irq_handler(can_irq_ids[id], IRQ_TX);
@ -147,21 +146,21 @@ static void can_irq(CANName name, int id)
/**************************/
if(can->STATUS & CAN_STATUS_EWARN_Msk) {
if(id)
can1_irq_handler(can_irq_ids[id] , IRQ_ERROR);
can1_irq_handler(can_irq_ids[id], IRQ_ERROR);
else
can0_irq_handler(can_irq_ids[id], IRQ_ERROR);
}
if(can->STATUS & CAN_STATUS_BOFF_Msk) {
if(id)
can1_irq_handler(can_irq_ids[id] , IRQ_BUS);
can1_irq_handler(can_irq_ids[id], IRQ_BUS);
else
can0_irq_handler(can_irq_ids[id], IRQ_BUS);
}
} else if (u8IIDRstatus!=0) {
if(id)
can1_irq_handler(can_irq_ids[id] , IRQ_OVERRUN);
can1_irq_handler(can_irq_ids[id], IRQ_OVERRUN);
else
can0_irq_handler(can_irq_ids[id], IRQ_OVERRUN);
@ -171,7 +170,7 @@ static void can_irq(CANName name, int id)
can->WU_STATUS = 0; /* Write '0' to clear */
if(id)
can1_irq_handler(can_irq_ids[id] , IRQ_WAKEUP);
can1_irq_handler(can_irq_ids[id], IRQ_WAKEUP);
else
can0_irq_handler(can_irq_ids[id], IRQ_WAKEUP);
}
@ -217,8 +216,7 @@ void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable)
u8Mask = ((enable != 0 )? CAN_CON_IE_Msk :0);
switch (irq)
{
switch (irq) {
case IRQ_ERROR:
case IRQ_BUS:
case IRQ_PASSIVE:
@ -240,13 +238,10 @@ void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable)
CAN_LeaveInitMode((CAN_T*)NU_MODBASE(obj->can));
if(!obj->index)
{
if(!obj->index) {
NVIC_SetVector(CAN0_IRQn, (uint32_t)&CAN0_IRQHandler);
NVIC_EnableIRQ(CAN0_IRQn);
}
else
{
} else {
NVIC_SetVector(CAN1_IRQn, (uint32_t)&CAN1_IRQHandler);
NVIC_EnableIRQ(CAN1_IRQn);
}
@ -285,8 +280,7 @@ int can_read(can_t *obj, CAN_Message *msg, int handle)
int can_mode(can_t *obj, CanMode mode)
{
int success = 0;
switch (mode)
{
switch (mode) {
case MODE_RESET:
CAN_LeaveTestMode((CAN_T*)NU_MODBASE(obj->can));
success = 1;
@ -325,7 +319,7 @@ int can_mode(can_t *obj, CanMode mode)
int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle)
{
return CAN_SetRxMsg((CAN_T *)NU_MODBASE(obj->can), handle , (uint32_t)format, id);
return CAN_SetRxMsg((CAN_T *)NU_MODBASE(obj->can), handle, (uint32_t)format, id);
}

62
targets/TARGET_NUVOTON/TARGET_M480/flash_api.c
View File

@ -22,37 +22,37 @@
// NOTE: On ARMv7-M/ARMv8-M, instruction fetches are always little-endian.
static uint32_t FLASH_ALGO[] = {
0x4603b530, 0x2164460c, 0x4df72059, 0x20166028, 0xf8c5070d, 0x20880100, 0x0100f8c5, 0xf8d006c0,
0xf0000100, 0xb9080001, 0xbd302001, 0x680048ef, 0x0004f040, 0x4580f04f, 0x0200f8c5, 0xf8d04628,
0xf0400204, 0xf8c50004, 0xbf000204, 0xf1a11e08, 0xd1fb0101, 0x680048e6, 0x0029f040, 0x60284de4,
0x68004628, 0x0001f000, 0x2001b908, 0x48e0e7dd, 0xf0406800, 0x4dde0040, 0x20006028, 0x4601e7d5,
0x48dbbf00, 0xf0006900, 0x28000001, 0x48d8d1f9, 0xf0206800, 0x4ad60029, 0x20006010, 0x60104ad2,
0x46014770, 0x48d2bf00, 0xf0006900, 0x28000001, 0x48cfd1f9, 0xf0406800, 0x4acd0040, 0x20226010,
0xf02160d0, 0x60500003, 0x1f00f5b1, 0x48c9d101, 0x20016090, 0x61104ac6, 0x8f60f3bf, 0x48c4bf00,
0xf0006900, 0x28000001, 0x48c1d1f9, 0xf0006800, 0xb1380040, 0x680048be, 0x0040f040, 0x60104abc,
0x47702001, 0xe7fc2000, 0x4603b570, 0x2500460c, 0x4629e009, 0xf8531c6d, 0xf7ff0021, 0x1e06ffc2,
0x4630d001, 0x42a5bd70, 0x2000d3f3, 0xb570e7fa, 0x460b4604, 0x22004615, 0xf1034629, 0xf020000f,
0xbf00030f, 0x690048aa, 0x0001f000, 0xd1f92800, 0x680048a7, 0x0040f040, 0x60304ea5, 0x000ff024,
0x20276070, 0x461060f0, 0xf8511c52, 0x4ea00020, 0x60303680, 0x1c524610, 0x0020f851, 0xf8c64e9c,
0x46100084, 0xf8511c52, 0x4e990020, 0x60303688, 0x1c524610, 0x0020f851, 0x60301d36, 0x4e942001,
0x3b106130, 0xbf00e02c, 0x30c04891, 0xf0006800, 0x28000030, 0x4610d1f8, 0xf8511c52, 0x4e8c0020,
0x60303680, 0x1c524610, 0x0020f851, 0xf8c64e88, 0xbf000084, 0x30c04886, 0xf0006800, 0x280000c0,
0x4610d1f8, 0xf8511c52, 0x4e810020, 0x60303688, 0x1c524610, 0x0020f851, 0xf8c64e7d, 0x3b10008c,
0xd1d02b00, 0x487abf00, 0xf0006900, 0x28000001, 0xbd70d1f9, 0x4603b510, 0xf0201cc8, 0xbf000103,
0x69004873, 0x0001f000, 0xd1f92800, 0x68004870, 0x0040f040, 0x60204c6e, 0x60e02021, 0xf023e020,
0x4c6b0003, 0x68106060, 0x200160a0, 0xf3bf6120, 0xbf008f60, 0x69004866, 0x0001f000, 0xd1f92800,
0x68004863, 0x0040f000, 0x4861b138, 0xf0406800, 0x4c5f0040, 0x20016020, 0x1d1bbd10, 0x1f091d12,
0xd1dc2900, 0xe7f72000, 0x47f0e92d, 0x460c4605, 0xf04f4616, 0x46c20800, 0x4855bf00, 0xf0006900,
0x28000001, 0x4852d1f9, 0xf0406800, 0x49500040, 0x1ce06008, 0x0403f020, 0xf3c5e02f, 0xb9600008,
0x7f00f5b4, 0xf44fd309, 0xeb067700, 0x46390208, 0xf7ff4628, 0x4682ff2c, 0xf3c5e016, 0xb9580008,
0xd3092c10, 0x070ff024, 0x0208eb06, 0x46284639, 0xff1df7ff, 0xe0074682, 0xeb064627, 0x46390208,
0xf7ff4628, 0x4682ff87, 0x44b8443d, 0xf1ba1be4, 0xd0020f00, 0xe8bd2001, 0x2c0087f0, 0x2000d1cd,
0xb510e7f9, 0xf0231ccb, 0xbf000103, 0x691b4b30, 0x0301f003, 0xd1f92b00, 0x681b4b2d, 0x0340f043,
0x60234c2b, 0x60e32300, 0xf020e025, 0x4c280303, 0x23006063, 0x230160a3, 0xf3bf6123, 0xbf008f60,
0x691b4b23, 0x0301f003, 0xd1f92b00, 0x681b4b20, 0x0340f003, 0x4b1eb133, 0xf043681b, 0x4c1c0340,
0xbd106023, 0x689b4b1a, 0x42a36814, 0xe7f8d000, 0x1d121d00, 0x29001f09, 0xbf00d1d7, 0xb510e7f1,
0x48134603, 0xf0006e00, 0xb1680002, 0x65034810, 0x65826541, 0x4c0e2001, 0xbf0065e0, 0x6e00480c,
0x0001f000, 0xd1f92800, 0x6e004809, 0x0004f000, 0x2002b908, 0x4806bd10, 0xf0006e00, 0xb1080002,
0xe7f72001, 0xe7f52000, 0x40000100, 0x40000200, 0x4000c000, 0x0055aa03, 0x00000000,
0xf0000100, 0xb9080001, 0xbd302001, 0x680048ef, 0x0004f040, 0x4580f04f, 0x0200f8c5, 0xf8d04628,
0xf0400204, 0xf8c50004, 0xbf000204, 0xf1a11e08, 0xd1fb0101, 0x680048e6, 0x0029f040, 0x60284de4,
0x68004628, 0x0001f000, 0x2001b908, 0x48e0e7dd, 0xf0406800, 0x4dde0040, 0x20006028, 0x4601e7d5,
0x48dbbf00, 0xf0006900, 0x28000001, 0x48d8d1f9, 0xf0206800, 0x4ad60029, 0x20006010, 0x60104ad2,
0x46014770, 0x48d2bf00, 0xf0006900, 0x28000001, 0x48cfd1f9, 0xf0406800, 0x4acd0040, 0x20226010,
0xf02160d0, 0x60500003, 0x1f00f5b1, 0x48c9d101, 0x20016090, 0x61104ac6, 0x8f60f3bf, 0x48c4bf00,
0xf0006900, 0x28000001, 0x48c1d1f9, 0xf0006800, 0xb1380040, 0x680048be, 0x0040f040, 0x60104abc,
0x47702001, 0xe7fc2000, 0x4603b570, 0x2500460c, 0x4629e009, 0xf8531c6d, 0xf7ff0021, 0x1e06ffc2,
0x4630d001, 0x42a5bd70, 0x2000d3f3, 0xb570e7fa, 0x460b4604, 0x22004615, 0xf1034629, 0xf020000f,
0xbf00030f, 0x690048aa, 0x0001f000, 0xd1f92800, 0x680048a7, 0x0040f040, 0x60304ea5, 0x000ff024,
0x20276070, 0x461060f0, 0xf8511c52, 0x4ea00020, 0x60303680, 0x1c524610, 0x0020f851, 0xf8c64e9c,
0x46100084, 0xf8511c52, 0x4e990020, 0x60303688, 0x1c524610, 0x0020f851, 0x60301d36, 0x4e942001,
0x3b106130, 0xbf00e02c, 0x30c04891, 0xf0006800, 0x28000030, 0x4610d1f8, 0xf8511c52, 0x4e8c0020,
0x60303680, 0x1c524610, 0x0020f851, 0xf8c64e88, 0xbf000084, 0x30c04886, 0xf0006800, 0x280000c0,
0x4610d1f8, 0xf8511c52, 0x4e810020, 0x60303688, 0x1c524610, 0x0020f851, 0xf8c64e7d, 0x3b10008c,
0xd1d02b00, 0x487abf00, 0xf0006900, 0x28000001, 0xbd70d1f9, 0x4603b510, 0xf0201cc8, 0xbf000103,
0x69004873, 0x0001f000, 0xd1f92800, 0x68004870, 0x0040f040, 0x60204c6e, 0x60e02021, 0xf023e020,
0x4c6b0003, 0x68106060, 0x200160a0, 0xf3bf6120, 0xbf008f60, 0x69004866, 0x0001f000, 0xd1f92800,
0x68004863, 0x0040f000, 0x4861b138, 0xf0406800, 0x4c5f0040, 0x20016020, 0x1d1bbd10, 0x1f091d12,
0xd1dc2900, 0xe7f72000, 0x47f0e92d, 0x460c4605, 0xf04f4616, 0x46c20800, 0x4855bf00, 0xf0006900,
0x28000001, 0x4852d1f9, 0xf0406800, 0x49500040, 0x1ce06008, 0x0403f020, 0xf3c5e02f, 0xb9600008,
0x7f00f5b4, 0xf44fd309, 0xeb067700, 0x46390208, 0xf7ff4628, 0x4682ff2c, 0xf3c5e016, 0xb9580008,
0xd3092c10, 0x070ff024, 0x0208eb06, 0x46284639, 0xff1df7ff, 0xe0074682, 0xeb064627, 0x46390208,
0xf7ff4628, 0x4682ff87, 0x44b8443d, 0xf1ba1be4, 0xd0020f00, 0xe8bd2001, 0x2c0087f0, 0x2000d1cd,
0xb510e7f9, 0xf0231ccb, 0xbf000103, 0x691b4b30, 0x0301f003, 0xd1f92b00, 0x681b4b2d, 0x0340f043,
0x60234c2b, 0x60e32300, 0xf020e025, 0x4c280303, 0x23006063, 0x230160a3, 0xf3bf6123, 0xbf008f60,
0x691b4b23, 0x0301f003, 0xd1f92b00, 0x681b4b20, 0x0340f003, 0x4b1eb133, 0xf043681b, 0x4c1c0340,
0xbd106023, 0x689b4b1a, 0x42a36814, 0xe7f8d000, 0x1d121d00, 0x29001f09, 0xbf00d1d7, 0xb510e7f1,
0x48134603, 0xf0006e00, 0xb1680002, 0x65034810, 0x65826541, 0x4c0e2001, 0xbf0065e0, 0x6e00480c,
0x0001f000, 0xd1f92800, 0x6e004809, 0x0004f000, 0x2002b908, 0x4806bd10, 0xf0006e00, 0xb1080002,
0xe7f72001, 0xe7f52000, 0x40000100, 0x40000200, 0x4000c000, 0x0055aa03, 0x00000000,
};
static const flash_algo_t flash_algo_config = {

6
targets/TARGET_NUVOTON/TARGET_M480/gpio_irq_api.c
View File

@ -160,8 +160,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
case IRQ_RISE:
if (enable) {
GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING);
}
else {
} else {
gpio_base->INTEN &= ~(GPIO_INT_RISING << pin_index);
}
break;
@ -169,8 +168,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
case IRQ_FALL:
if (enable) {
GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING);
}
else {
} else {
gpio_base->INTEN &= ~(GPIO_INT_FALLING << pin_index);
}
break;

81
targets/TARGET_NUVOTON/TARGET_M480/i2c_api.c
View File

@ -230,8 +230,7 @@ int i2c_byte_write(i2c_t *obj, int data)
if (i2c_do_tran(obj, data_, 1, 0, 0) == 1 &&
! (obj->i2c.tran_ctrl & TRANCTRL_LASTDATANAKED)) {
return 1;
}
else {
} else {
return 0;
}
}
@ -337,8 +336,7 @@ static int i2c_set_int(i2c_t *obj, int inten)
if (inten) {
i2c_enable_int(obj);
}
else {
} else {
i2c_disable_int(obj);
}
@ -384,8 +382,7 @@ static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastd
MY_I2C_2 = obj->i2c;
while (1);
#endif
}
else {
} else {
i2c_disable_int(obj);
tran_len = obj->i2c.tran_pos - obj->i2c.tran_beg;
obj->i2c.tran_beg = NULL;
@ -410,8 +407,7 @@ static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync)
MY_I2C_2 = obj->i2c;
while (1);
#endif
}
else {
} else {
#if 1
// NOTE: Avoid duplicate Start/Stop. Otherwise, we may meet strange error.
uint32_t status = I2C_GET_STATUS(i2c_base);
@ -421,15 +417,13 @@ static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync)
case 0x10: // Master Repeat Start
if (i2c_ctl & I2C_CTL0_STA_Msk) {
return 0;
}
else {
} else {
break;
}
case 0xF8: // Bus Released
if ((i2c_ctl & (I2C_CTL0_STA_Msk | I2C_CTL0_STO_Msk)) == I2C_CTL0_STO_Msk) {
return 0;
}
else {
} else {
break;
}
}
@ -601,8 +595,7 @@ static void i2c_irq(i2c_t *obj)
#if NU_I2C_DEBUG
if (MY_I2C_STATUS_POS < (sizeof (MY_I2C_STATUS) / sizeof (MY_I2C_STATUS[0]))) {
MY_I2C_STATUS[MY_I2C_STATUS_POS ++] = status;
}
else {
} else {
memset(MY_I2C_STATUS, 0x00, sizeof (MY_I2C_STATUS));
MY_I2C_STATUS_POS = 0;
}
@ -618,12 +611,10 @@ static void i2c_irq(i2c_t *obj)
if (obj->i2c.tran_pos < obj->i2c.tran_end) {
I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
}
else {
} else {
i2c_fsm_tranfini(obj, 0);
}
}
else {
} else {
i2c_disable_int(obj);
}
break;
@ -661,8 +652,7 @@ static void i2c_irq(i2c_t *obj)
}
#endif
i2c_fsm_tranfini(obj, 1);
}
else {
} else {
uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk;
if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
@ -671,14 +661,12 @@ static void i2c_irq(i2c_t *obj)
}
I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
}
}
else {
} else {
obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
i2c_disable_int(obj);
break;
}
}
else {
} else {
i2c_disable_int(obj);
}
break;
@ -700,14 +688,12 @@ static void i2c_irq(i2c_t *obj)
i2c_ctl &= ~I2C_CTL0_AA_Msk;
}
I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
}
else {
} else {
obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
i2c_disable_int(obj);
break;
}
}
else {
} else {
i2c_disable_int(obj);
}
obj->i2c.slaveaddr_state = ReadAddressed;
@ -740,8 +726,7 @@ static void i2c_irq(i2c_t *obj)
#endif
obj->i2c.slaveaddr_state = NoData;
i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
}
else {
} else {
uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk;
if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
@ -750,14 +735,12 @@ static void i2c_irq(i2c_t *obj)
}
I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
}
}
else {
} else {
obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
i2c_disable_int(obj);
break;
}
}
else {
} else {
i2c_disable_int(obj);
}
break;
@ -785,8 +768,7 @@ static void i2c_irq(i2c_t *obj)
#endif
obj->i2c.slaveaddr_state = NoData;
i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
}
else {
} else {
uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk;
if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
@ -795,14 +777,12 @@ static void i2c_irq(i2c_t *obj)
}
I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
}
}
else {
} else {
obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
i2c_disable_int(obj);
break;
}
}
else {
} else {
i2c_disable_int(obj);
}
break;
@ -869,12 +849,10 @@ uint32_t i2c_irq_handler_asynch(i2c_t *obj)
if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 0)));
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
}
else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
} else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 1)));
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
}
else {
} else {
event = I2C_EVENT_TRANSFER_COMPLETE;
if (obj->i2c.stop) {
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
@ -889,11 +867,9 @@ uint32_t i2c_irq_handler_asynch(i2c_t *obj)
uint8_t *tx = (uint8_t *)obj->tx_buff.buffer;
I2C_SET_DATA(i2c_base, tx[obj->tx_buff.pos ++]);
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
}
else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
} else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk);
}
else {
} else {
event = I2C_EVENT_TRANSFER_COMPLETE;
if (obj->i2c.stop) {
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
@ -912,11 +888,9 @@ uint32_t i2c_irq_handler_asynch(i2c_t *obj)
if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
event = I2C_EVENT_TRANSFER_EARLY_NACK;
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
}
else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
} else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk);
}
else {
} else {
event = I2C_EVENT_TRANSFER_COMPLETE;
if (obj->i2c.stop) {
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
@ -1009,8 +983,7 @@ static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable
if (enable) {
NVIC_SetVector(modinit->irq_n, handler);
i2c_enable_int(obj);
}
else {
} else {
i2c_disable_int(obj);
}

15
targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c
View File

@ -130,19 +130,16 @@ timestamp_t lp_ticker_read()
// When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Handle carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
}
else {
} else {
major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
}
core_util_critical_section_exit();
}
while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
} while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
// Add power-down compensation
return ((uint64_t) major_minor_clks * US_PER_SEC / TMR2_CLK_PER_SEC / US_PER_TICK);
}
while (0);
} while (0);
}
void lp_ticker_set_interrupt(timestamp_t timestamp)
@ -163,8 +160,7 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
if (delta > 0) {
cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
lp_ticker_arm_cd();
}
else {
} else {
cd_major_minor_clks = cd_minor_clks = 0;
/**
* This event was in the past. Set the interrupt as pending, but don't process it here.
@ -199,8 +195,7 @@ static void tmr3_vec(void)
if (cd_major_minor_clks == 0) {
// NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
lp_ticker_irq_handler();
}
else {
} else {
lp_ticker_arm_cd();
}
}

12
targets/TARGET_NUVOTON/TARGET_M480/serial_api.c
View File

@ -291,7 +291,8 @@ void serial_free(serial_t *obj)
}
}
void serial_baud(serial_t *obj, int baudrate) {
void serial_baud(serial_t *obj, int baudrate)
{
// Flush Tx FIFO. Otherwise, output data may get lost on this change.
while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart)));
@ -299,7 +300,8 @@ void serial_baud(serial_t *obj, int baudrate) {
UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
// Flush Tx FIFO. Otherwise, output data may get lost on this change.
while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart)));
@ -1104,8 +1106,7 @@ static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enabl
UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
break;
}
}
else { // disable
} else { // disable
switch (irq) {
case RxIrq:
UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
@ -1140,8 +1141,7 @@ static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch)
if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
*dma_usage = DMA_USAGE_NEVER;
}
}
else {
} else {
dma_channel_free(*dma_ch);
*dma_ch = DMA_ERROR_OUT_OF_CHANNELS;
}

3
targets/TARGET_NUVOTON/TARGET_M480/sleep.c
View File

@ -79,8 +79,7 @@ static void mbed_enter_sleep(struct sleep_s *obj)
SYS_UnlockReg();
CLK_PowerDown();
SYS_LockReg();
}
else { // CPU halt mode (HIRC/HXT enabled, LIRC/LXT enabled)
} else { // CPU halt mode (HIRC/HXT enabled, LIRC/LXT enabled)
SYS_UnlockReg();
CLK_Idle();
SYS_LockReg();

36
targets/TARGET_NUVOTON/TARGET_M480/spi_api.c
View File

@ -102,7 +102,8 @@ static const struct nu_modinit_s spi_modinit_tab[] = {
{NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
};
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
// Determine which SPI_x the pins are used for
uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
@ -201,12 +202,10 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
if (obj->spi.pin_ssel != NC) {
// Configure SS as low active.
SPI_EnableAutoSS(spi_base, SPI_SS, SPI_SS_ACTIVE_LOW);
}
else {
} else {
SPI_DisableAutoSS(spi_base);
}
}
else {
} else {
// Slave
// Configure SS as low active.
spi_base->SSCTL &= ~SPI_SSCTL_SSACTPOL_Msk;
@ -247,6 +246,21 @@ int spi_master_write(spi_t *obj, int value)
return value2;
}
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length)
{
int total = (tx_length > rx_length) ? tx_length : rx_length;
for (int i = 0; i < total; i++) {
char out = (i < tx_length) ? tx_buffer[i] : 0xff;
char in = spi_master_write(obj, out);
if (i < rx_length) {
rx_buffer[i] = in;
}
}
return total;
}
#if DEVICE_SPISLAVE
int spi_slave_receive(spi_t *obj)
{
@ -495,8 +509,7 @@ static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t en
if (enable) {
NVIC_SetVector(modinit->irq_n, handler);
NVIC_EnableIRQ(modinit->irq_n);
}
else {
} else {
NVIC_DisableIRQ(modinit->irq_n);
}
}
@ -510,8 +523,7 @@ static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable)
SPI_SetFIFO(spi_base, fifo_depth / 2, fifo_depth / 2);
// Enable tx/rx FIFO threshold interrupt
SPI_EnableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK);
}
else {
} else {
SPI_DisableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK);
}
}
@ -576,8 +588,7 @@ static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit)
if (spi_is_tx_complete(obj)) {
// Transmit dummy as transmit buffer is empty
SPI_WRITE_TX(spi_base, 0);
}
else {
} else {
switch (bytes_per_word) {
case 4:
SPI_WRITE_TX(spi_base, nu_get32_le(tx));
@ -628,8 +639,7 @@ static uint32_t spi_master_read_asynch(spi_t *obj)
if (spi_is_rx_complete(obj)) {
// Disregard as receive buffer is full
SPI_READ_RX(spi_base);
}
else {
} else {
switch (bytes_per_word) {
case 4: {
uint32_t val = SPI_READ_RX(spi_base);

15
targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c
View File

@ -122,18 +122,15 @@ uint32_t us_ticker_read()
// When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
if (carry && minor_us > (US_PER_TMR0HIRES_INT / 2)) {
major_minor_us = (counter_major + 1) * US_PER_TMR0HIRES_INT;
}
else {
} else {
major_minor_us = (counter_major + carry) * US_PER_TMR0HIRES_INT + minor_us;
}
core_util_critical_section_exit();
}
while (minor_us == 0 || minor_us == US_PER_TMR0HIRES_INT);
} while (minor_us == 0 || minor_us == US_PER_TMR0HIRES_INT);
return (major_minor_us / US_PER_TICK);
}
while (0);
} while (0);
}
void us_ticker_disable_interrupt(void)
@ -154,8 +151,7 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
if (delta > 0) {
cd_major_minor_us = delta * US_PER_TICK;
us_ticker_arm_cd();
}
else {
} else {
cd_major_minor_us = cd_minor_us = 0;
/**
* This event was in the past. Set the interrupt as pending, but don't process it here.
@ -178,8 +174,7 @@ static void tmr1_vec(void)
if (cd_major_minor_us == 0) {
// NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
us_ticker_irq_handler();
}
else {
} else {
us_ticker_arm_cd();
}
}