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Refine coding style

pull/4974/head
ccli8 2017-07-05 17:40:55 +08:00 committed by adbridge
parent abd8dee9e5
commit 592f46b382
18 changed files with 1037 additions and 1073 deletions
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16
targets/TARGET_NUVOTON/TARGET_M480/can_api.c
View File

@ -70,8 +70,7 @@ void can_init_freq(can_t *obj, PinName rd, PinName td, int hz)
if(obj->can == CAN_1) {
obj->index = 1;
}
else
} else
obj->index = 0;
pinmap_pinout(td, PinMap_CAN_TD);
@ -217,8 +216,7 @@ void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable)
u8Mask = ((enable != 0 )? CAN_CON_IE_Msk :0);
switch (irq)
{
switch (irq) {
case IRQ_ERROR:
case IRQ_BUS:
case IRQ_PASSIVE:
@ -240,13 +238,10 @@ void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable)
CAN_LeaveInitMode((CAN_T*)NU_MODBASE(obj->can));
if(!obj->index)
{
if(!obj->index) {
NVIC_SetVector(CAN0_IRQn, (uint32_t)&CAN0_IRQHandler);
NVIC_EnableIRQ(CAN0_IRQn);
}
else
{
} else {
NVIC_SetVector(CAN1_IRQn, (uint32_t)&CAN1_IRQHandler);
NVIC_EnableIRQ(CAN1_IRQn);
}
@ -285,8 +280,7 @@ int can_read(can_t *obj, CAN_Message *msg, int handle)
int can_mode(can_t *obj, CanMode mode)
{
int success = 0;
switch (mode)
{
switch (mode) {
case MODE_RESET:
CAN_LeaveTestMode((CAN_T*)NU_MODBASE(obj->can));
success = 1;

6
targets/TARGET_NUVOTON/TARGET_M480/gpio_irq_api.c
View File

@ -160,8 +160,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
case IRQ_RISE:
if (enable) {
GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING);
}
else {
} else {
gpio_base->INTEN &= ~(GPIO_INT_RISING << pin_index);
}
break;
@ -169,8 +168,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
case IRQ_FALL:
if (enable) {
GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING);
}
else {
} else {
gpio_base->INTEN &= ~(GPIO_INT_FALLING << pin_index);
}
break;

81
targets/TARGET_NUVOTON/TARGET_M480/i2c_api.c
View File

@ -230,8 +230,7 @@ int i2c_byte_write(i2c_t *obj, int data)
if (i2c_do_tran(obj, data_, 1, 0, 0) == 1 &&
! (obj->i2c.tran_ctrl & TRANCTRL_LASTDATANAKED)) {
return 1;
}
else {
} else {
return 0;
}
}
@ -337,8 +336,7 @@ static int i2c_set_int(i2c_t *obj, int inten)
if (inten) {
i2c_enable_int(obj);
}
else {
} else {
i2c_disable_int(obj);
}
@ -384,8 +382,7 @@ static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastd
MY_I2C_2 = obj->i2c;
while (1);
#endif
}
else {
} else {
i2c_disable_int(obj);
tran_len = obj->i2c.tran_pos - obj->i2c.tran_beg;
obj->i2c.tran_beg = NULL;
@ -410,8 +407,7 @@ static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync)
MY_I2C_2 = obj->i2c;
while (1);
#endif
}
else {
} else {
#if 1
// NOTE: Avoid duplicate Start/Stop. Otherwise, we may meet strange error.
uint32_t status = I2C_GET_STATUS(i2c_base);
@ -421,15 +417,13 @@ static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync)
case 0x10: // Master Repeat Start
if (i2c_ctl & I2C_CTL0_STA_Msk) {
return 0;
}
else {
} else {
break;
}
case 0xF8: // Bus Released
if ((i2c_ctl & (I2C_CTL0_STA_Msk | I2C_CTL0_STO_Msk)) == I2C_CTL0_STO_Msk) {
return 0;
}
else {
} else {
break;
}
}
@ -601,8 +595,7 @@ static void i2c_irq(i2c_t *obj)
#if NU_I2C_DEBUG
if (MY_I2C_STATUS_POS < (sizeof (MY_I2C_STATUS) / sizeof (MY_I2C_STATUS[0]))) {
MY_I2C_STATUS[MY_I2C_STATUS_POS ++] = status;
}
else {
} else {
memset(MY_I2C_STATUS, 0x00, sizeof (MY_I2C_STATUS));
MY_I2C_STATUS_POS = 0;
}
@ -618,12 +611,10 @@ static void i2c_irq(i2c_t *obj)
if (obj->i2c.tran_pos < obj->i2c.tran_end) {
I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
}
else {
} else {
i2c_fsm_tranfini(obj, 0);
}
}
else {
} else {
i2c_disable_int(obj);
}
break;
@ -661,8 +652,7 @@ static void i2c_irq(i2c_t *obj)
}
#endif
i2c_fsm_tranfini(obj, 1);
}
else {
} else {
uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk;
if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
@ -671,14 +661,12 @@ static void i2c_irq(i2c_t *obj)
}
I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
}
}
else {
} else {
obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
i2c_disable_int(obj);
break;
}
}
else {
} else {
i2c_disable_int(obj);
}
break;
@ -700,14 +688,12 @@ static void i2c_irq(i2c_t *obj)
i2c_ctl &= ~I2C_CTL0_AA_Msk;
}
I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
}
else {
} else {
obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
i2c_disable_int(obj);
break;
}
}
else {
} else {
i2c_disable_int(obj);
}
obj->i2c.slaveaddr_state = ReadAddressed;
@ -740,8 +726,7 @@ static void i2c_irq(i2c_t *obj)
#endif
obj->i2c.slaveaddr_state = NoData;
i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
}
else {
} else {
uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk;
if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
@ -750,14 +735,12 @@ static void i2c_irq(i2c_t *obj)
}
I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
}
}
else {
} else {
obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
i2c_disable_int(obj);
break;
}
}
else {
} else {
i2c_disable_int(obj);
}
break;
@ -785,8 +768,7 @@ static void i2c_irq(i2c_t *obj)
#endif
obj->i2c.slaveaddr_state = NoData;
i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
}
else {
} else {
uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk;
if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
@ -795,14 +777,12 @@ static void i2c_irq(i2c_t *obj)
}
I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
}
}
else {
} else {
obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
i2c_disable_int(obj);
break;
}
}
else {
} else {
i2c_disable_int(obj);
}
break;
@ -869,12 +849,10 @@ uint32_t i2c_irq_handler_asynch(i2c_t *obj)
if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 0)));
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
}
else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
} else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 1)));
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
}
else {
} else {
event = I2C_EVENT_TRANSFER_COMPLETE;
if (obj->i2c.stop) {
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
@ -889,11 +867,9 @@ uint32_t i2c_irq_handler_asynch(i2c_t *obj)
uint8_t *tx = (uint8_t *)obj->tx_buff.buffer;
I2C_SET_DATA(i2c_base, tx[obj->tx_buff.pos ++]);
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
}
else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
} else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk);
}
else {
} else {
event = I2C_EVENT_TRANSFER_COMPLETE;
if (obj->i2c.stop) {
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
@ -912,11 +888,9 @@ uint32_t i2c_irq_handler_asynch(i2c_t *obj)
if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
event = I2C_EVENT_TRANSFER_EARLY_NACK;
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
}
else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
} else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk);
}
else {
} else {
event = I2C_EVENT_TRANSFER_COMPLETE;
if (obj->i2c.stop) {
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
@ -1009,8 +983,7 @@ static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable
if (enable) {
NVIC_SetVector(modinit->irq_n, handler);
i2c_enable_int(obj);
}
else {
} else {
i2c_disable_int(obj);
}

15
targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c
View File

@ -130,19 +130,16 @@ timestamp_t lp_ticker_read()
// When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Handle carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
}
else {
} else {
major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
}
core_util_critical_section_exit();
}
while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
} while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
// Add power-down compensation
return ((uint64_t) major_minor_clks * US_PER_SEC / TMR2_CLK_PER_SEC / US_PER_TICK);
}
while (0);
} while (0);
}
void lp_ticker_set_interrupt(timestamp_t timestamp)
@ -163,8 +160,7 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
if (delta > 0) {
cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
lp_ticker_arm_cd();
}
else {
} else {
cd_major_minor_clks = cd_minor_clks = 0;
/**
* This event was in the past. Set the interrupt as pending, but don't process it here.
@ -199,8 +195,7 @@ static void tmr3_vec(void)
if (cd_major_minor_clks == 0) {
// NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
lp_ticker_irq_handler();
}
else {
} else {
lp_ticker_arm_cd();
}
}

12
targets/TARGET_NUVOTON/TARGET_M480/serial_api.c
View File

@ -291,7 +291,8 @@ void serial_free(serial_t *obj)
}
}
void serial_baud(serial_t *obj, int baudrate) {
void serial_baud(serial_t *obj, int baudrate)
{
// Flush Tx FIFO. Otherwise, output data may get lost on this change.
while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart)));
@ -299,7 +300,8 @@ void serial_baud(serial_t *obj, int baudrate) {
UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
// Flush Tx FIFO. Otherwise, output data may get lost on this change.
while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart)));
@ -1104,8 +1106,7 @@ static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enabl
UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
break;
}
}
else { // disable
} else { // disable
switch (irq) {
case RxIrq:
UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
@ -1140,8 +1141,7 @@ static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch)
if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
*dma_usage = DMA_USAGE_NEVER;
}
}
else {
} else {
dma_channel_free(*dma_ch);
*dma_ch = DMA_ERROR_OUT_OF_CHANNELS;
}

3
targets/TARGET_NUVOTON/TARGET_M480/sleep.c
View File

@ -79,8 +79,7 @@ static void mbed_enter_sleep(struct sleep_s *obj)
SYS_UnlockReg();
CLK_PowerDown();
SYS_LockReg();
}
else { // CPU halt mode (HIRC/HXT enabled, LIRC/LXT enabled)
} else { // CPU halt mode (HIRC/HXT enabled, LIRC/LXT enabled)
SYS_UnlockReg();
CLK_Idle();
SYS_LockReg();

36
targets/TARGET_NUVOTON/TARGET_M480/spi_api.c
View File

@ -102,7 +102,8 @@ static const struct nu_modinit_s spi_modinit_tab[] = {
{NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
};
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
// Determine which SPI_x the pins are used for
uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
@ -201,12 +202,10 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
if (obj->spi.pin_ssel != NC) {
// Configure SS as low active.
SPI_EnableAutoSS(spi_base, SPI_SS, SPI_SS_ACTIVE_LOW);
}
else {
} else {
SPI_DisableAutoSS(spi_base);
}
}
else {
} else {
// Slave
// Configure SS as low active.
spi_base->SSCTL &= ~SPI_SSCTL_SSACTPOL_Msk;
@ -247,6 +246,21 @@ int spi_master_write(spi_t *obj, int value)
return value2;
}
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length)
{
int total = (tx_length > rx_length) ? tx_length : rx_length;
for (int i = 0; i < total; i++) {
char out = (i < tx_length) ? tx_buffer[i] : 0xff;
char in = spi_master_write(obj, out);
if (i < rx_length) {
rx_buffer[i] = in;
}
}
return total;
}
#if DEVICE_SPISLAVE
int spi_slave_receive(spi_t *obj)
{
@ -495,8 +509,7 @@ static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t en
if (enable) {
NVIC_SetVector(modinit->irq_n, handler);
NVIC_EnableIRQ(modinit->irq_n);
}
else {
} else {
NVIC_DisableIRQ(modinit->irq_n);
}
}
@ -510,8 +523,7 @@ static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable)
SPI_SetFIFO(spi_base, fifo_depth / 2, fifo_depth / 2);
// Enable tx/rx FIFO threshold interrupt
SPI_EnableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK);
}
else {
} else {
SPI_DisableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK);
}
}
@ -576,8 +588,7 @@ static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit)
if (spi_is_tx_complete(obj)) {
// Transmit dummy as transmit buffer is empty
SPI_WRITE_TX(spi_base, 0);
}
else {
} else {
switch (bytes_per_word) {
case 4:
SPI_WRITE_TX(spi_base, nu_get32_le(tx));
@ -628,8 +639,7 @@ static uint32_t spi_master_read_asynch(spi_t *obj)
if (spi_is_rx_complete(obj)) {
// Disregard as receive buffer is full
SPI_READ_RX(spi_base);
}
else {
} else {
switch (bytes_per_word) {
case 4: {
uint32_t val = SPI_READ_RX(spi_base);

15
targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c
View File

@ -122,18 +122,15 @@ uint32_t us_ticker_read()
// When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
if (carry && minor_us > (US_PER_TMR0HIRES_INT / 2)) {
major_minor_us = (counter_major + 1) * US_PER_TMR0HIRES_INT;
}
else {
} else {
major_minor_us = (counter_major + carry) * US_PER_TMR0HIRES_INT + minor_us;
}
core_util_critical_section_exit();
}
while (minor_us == 0 || minor_us == US_PER_TMR0HIRES_INT);
} while (minor_us == 0 || minor_us == US_PER_TMR0HIRES_INT);
return (major_minor_us / US_PER_TICK);
}
while (0);
} while (0);
}
void us_ticker_disable_interrupt(void)
@ -154,8 +151,7 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
if (delta > 0) {
cd_major_minor_us = delta * US_PER_TICK;
us_ticker_arm_cd();
}
else {
} else {
cd_major_minor_us = cd_minor_us = 0;
/**
* This event was in the past. Set the interrupt as pending, but don't process it here.
@ -178,8 +174,7 @@ static void tmr1_vec(void)
if (cd_major_minor_us == 0) {
// NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
us_ticker_irq_handler();
}
else {
} else {
us_ticker_arm_cd();
}
}