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Merge pull request #2220 from svastm/update_cube_l1 

[STM32L1XX] Update STM32CUBE_L1 to v1.6
pull/2401/head
Martin Kojtal 2016-08-12 09:50:25 +02:00 committed by GitHub
parent d49a4e6da9 95c17a4ff4
commit 58d9926c0c
155 changed files with 64877 additions and 13933 deletions
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20
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/Release_Notes_stm32l1xx_hal.html
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hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/startup_stm32l152xc.S
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@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l152xc.s
;* Author : MCD Application Team
;* Version : V2.1.3
;* Date : 04-March-2016
;* Version : V2.2.0
;* Date : 01-July-2016
;* Description : STM32L152XC Devices vector for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/startup_stm32l152xc.S
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@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l152xc.s
;* Author : MCD Application Team
;* Version : V2.1.3
;* Date : 04-March-2016
;* Version : V2.2.0
;* Date : 01-July-2016
;* Description : STM32L152XC Devices vector for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/startup_stm32l152xc.S
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@ -2,8 +2,8 @@
******************************************************************************
* @file startup_stm32l152xc.s
* @author MCD Application Team
* @version V2.1.3
* @date 04-March-2016
* @version V2.2.0
* @date 01-July-2016
* @brief STM32L152XC Devices vector table for
* Atollic toolchain.
* This module performs:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_IAR/startup_stm32l152xc.S
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@ -1,8 +1,8 @@
;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l152xc.s
;* Author : MCD Application Team
;* Version : V2.1.3
;* Date : 04-March-2016
;* Version : V2.2.0
;* Date : 01-July-2016
;* Description : STM32L152XC Devices vector for EWARM toolchain.
;* This module performs:
;* - Set the initial SP

9682
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l152xc.h
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10
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l1xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx.h
* @author MCD Application Team
* @version V2.1.3
* @date 04-March-2016
* @version V2.2.0
* @date 01-July-2016
* @brief CMSIS STM32L1xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -118,11 +118,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.1.3
* @brief CMSIS Device version number
*/
#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\

10
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l1xx_hal_conf.h
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@ -1,9 +1,9 @@
/**
******************************************************************************
* @file stm32l1xx_hal_conf_template.h
* @file stm32l1xx_hal_conf.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32l1xx_hal_conf.h.
@ -274,11 +274,11 @@
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32l1xx.c
* @author MCD Application Team
* @version V2.1.3
* @date 04-March-2016
* @version V2.2.0
* @date 01-July-2016
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32l1xx.h
* @author MCD Application Team
* @version V2.1.3
* @date 04-March-2016
* @version V2.2.0
* @date 01-July-2016
* @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/startup_stm32l152xe.S
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@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l152xe.s
;* Author : MCD Application Team
;* Version : V2.1.3
;* Date : 04-March-2016
;* Version : V2.2.0
;* Date : 01-July-2016
;* Description : STM32L152XE Devices vector for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/startup_stm32l152xe.S
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@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l152xe.s
;* Author : MCD Application Team
;* Version : V2.1.3
;* Date : 04-March-2016
;* Version : V2.2.0
;* Date : 01-July-2016
;* Description : STM32L152XE Devices vector for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_GCC_ARM/startup_stm32l152xe.S
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@ -2,8 +2,8 @@
******************************************************************************
* @file startup_stm32l152xe.s
* @author MCD Application Team
* @version V2.1.3
* @date 04-March-2016
* @version V2.2.0
* @date 01-July-2016
* @brief STM32L152XE Devices vector table for
* Atollic toolchain.
* This module performs:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_IAR/startup_stm32l152xe.S
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@ -1,8 +1,8 @@
;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l152xe.s
;* Author : MCD Application Team
;* Version : V2.1.3
;* Date : 04-March-2016
;* Version : V2.2.0
;* Date : 01-July-2016
;* Description : STM32L152XE Devices vector for EWARM toolchain.
;* This module performs:
;* - Set the initial SP

10120
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/stm32l152xe.h
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11
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/stm32l1xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx.h
* @author MCD Application Team
* @version V2.1.3
* @date 04-March-2016
* @version V2.2.0
* @date 01-July-2016
* @brief CMSIS STM32L1xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -95,6 +95,7 @@
/* #define STM32L152xC */ /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */
/* #define STM32L152xCA */ /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */
/* #define STM32L152xD */ /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */
/* #define STM32L152xDX */ /*!< STM32L152VD-X Devices */
#define STM32L152xE /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */
/* #define STM32L162xC */ /*!< STM32L162RC and STM32L162VC */
/* #define STM32L162xCA */ /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */
@ -117,11 +118,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.1.3
* @brief CMSIS Device version number
*/
#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\

8
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/stm32l1xx_hal_conf.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_conf.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32l1xx_hal_conf.h.
@ -274,11 +274,11 @@
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32l1xx.c
* @author MCD Application Team
* @version V2.1.3
* @date 04-March-2016
* @version V2.2.0
* @date 01-July-2016
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32l1xx.h
* @author MCD Application Team
* @version V2.1.3
* @date 04-March-2016
* @version V2.2.0
* @date 01-July-2016
* @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S
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@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l151xc.s
;* Author : MCD Application Team
;* Version : V2.1.3
;* Date : 04-March-2016
;* Version : V2.2.0
;* Date : 01-July-2016
;* Description : STM32L151XC Devices vector for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S
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@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l151xc.s
;* Author : MCD Application Team
;* Version : V2.1.3
;* Date : 04-March-2016
;* Version : V2.2.0
;* Date : 01-July-2016
;* Description : STM32L151XC Devices vector for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S
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@ -2,8 +2,8 @@
******************************************************************************
* @file startup_stm32l151xc.s
* @author MCD Application Team
* @version V2.1.3
* @date 04-March-2016
* @version V2.2.0
* @date 01-July-2016
* @brief STM32L151XC Devices vector table for
* Atollic toolchain.
* This module performs:

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hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/stm32l151xc.h
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10
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/stm32l1xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx.h
* @author MCD Application Team
* @version V2.1.3
* @date 04-March-2016
* @version V2.2.0
* @date 01-July-2016
* @brief CMSIS STM32L1xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -130,11 +130,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.1.3
* @brief CMSIS Device version number
*/
#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\

8
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/stm32l1xx_hal_conf.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_conf.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32l1xx_hal_conf.h.
@ -274,11 +274,11 @@
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/system_stm32l1xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32l1xx.c
* @author MCD Application Team
* @version V2.1.3
* @date 04-March-2016
* @version V2.2.0
* @date 01-July-2016
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/system_stm32l1xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32l1xx.h
* @author MCD Application Team
* @version V2.1.3
* @date 04-March-2016
* @version V2.2.0
* @date 01-July-2016
* @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.
******************************************************************************
* @attention

160
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32_hal_legacy.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
@ -129,7 +129,6 @@
/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
* @{
*/
#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
@ -144,6 +143,73 @@
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
#endif /* STM32F373xC || STM32F378xx */
#if defined(STM32L0) || defined(STM32L4)
#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
#if defined(STM32L0)
/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
/* to the second dedicated IO (only for COMP2). */
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
#else
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
#endif
#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
#if defined(COMP_CSR_LOCK)
#define COMP_FLAG_LOCK COMP_CSR_LOCK
#elif defined(COMP_CSR_COMP1LOCK)
#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
#elif defined(COMP_CSR_COMPxLOCK)
#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
#endif
#if defined(STM32L4)
#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
#endif
#if defined(STM32L0)
#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
#else
#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
#endif
#endif
/**
* @}
*/
@ -384,6 +450,7 @@
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
/**
* @}
*/
@ -424,7 +491,7 @@
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1)
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
@ -875,9 +942,12 @@
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
#endif
#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
@ -897,9 +967,41 @@
#define DCMI_IT_OVF DCMI_IT_OVR
#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
/**
* @}
*/
#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
* @{
*/
#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
#define CM_RGB888 DMA2D_INPUT_RGB888
#define CM_RGB565 DMA2D_INPUT_RGB565
#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
#define CM_L8 DMA2D_INPUT_L8
#define CM_AL44 DMA2D_INPUT_AL44
#define CM_AL88 DMA2D_INPUT_AL88
#define CM_L4 DMA2D_INPUT_L4
#define CM_A8 DMA2D_INPUT_A8
#define CM_A4 DMA2D_INPUT_A4
/**
* @}
*/
#endif /* STM32L4xx || STM32F7*/
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{
@ -957,7 +1059,10 @@
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
#else
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
/**
@ -1461,10 +1566,28 @@
#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
#if defined(STM32L0) || defined(STM32L4)
/* Note: On these STM32 families, the only argument of this macro */
/* is COMP_FLAG_LOCK. */
/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
/* argument. */
#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
#endif
/**
* @}
*/
#if defined(STM32L0) || defined(STM32L4)
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
/**
* @}
*/
#endif
/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
* @{
*/
@ -2508,7 +2631,7 @@
#endif
#if defined(STM32F7)
#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48
#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
#endif
@ -2625,6 +2748,31 @@
#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
#define DfsdmClockSelection Dfsdm1ClockSelection
#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
/**
* @}
*/
@ -2913,6 +3061,8 @@
#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
/**
* @}
*/

12
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@ -72,11 +72,11 @@
*/
/**
* @brief STM32L1xx HAL Driver version number V1.1.3
* @brief STM32L1xx HAL Driver version number
*/
#define __STM32L1xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L1xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32L1xx_HAL_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32L1xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32L1xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L1xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L1xx_HAL_VERSION ((__STM32L1xx_HAL_VERSION_MAIN << 24)\
|(__STM32L1xx_HAL_VERSION_SUB1 << 16)\
@ -96,7 +96,7 @@
* @{
*/
static __IO uint32_t uwTick;
__IO uint32_t uwTick;
/**
* @}

42
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
@ -69,7 +69,7 @@
* @{
*/
#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000)
#define SYSCFG_BOOT_MAINFLASH (0x00000000U)
#define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0)
#if defined(FSMC_R_BASE)
#define SYSCFG_BOOT_FSMC ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1)
@ -105,7 +105,7 @@
* @{
*/
#define TIM_SELECT_NONE ((uint32_t)0x00000000) /*!< None selected */
#define TIM_SELECT_NONE (0x00000000U) /*!< None selected */
#define TIM_SELECT_TIM2 ((uint32_t)RI_ICR_TIM_0) /*!< Timer 2 selected */
#define TIM_SELECT_TIM3 ((uint32_t)RI_ICR_TIM_1) /*!< Timer 3 selected */
#define TIM_SELECT_TIM4 ((uint32_t)RI_ICR_TIM) /*!< Timer 4 selected */
@ -123,22 +123,22 @@
* @{
*/
/* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */
#define RI_INPUTCAPTUREROUTING_0 ((uint32_t)0x00000000) /* PA0 PA1 PA2 PA3 */
#define RI_INPUTCAPTUREROUTING_1 ((uint32_t)0x00000001) /* PA4 PA5 PA6 PA7 */
#define RI_INPUTCAPTUREROUTING_2 ((uint32_t)0x00000002) /* PA8 PA9 PA10 PA11 */
#define RI_INPUTCAPTUREROUTING_3 ((uint32_t)0x00000003) /* PA12 PA13 PA14 PA15 */
#define RI_INPUTCAPTUREROUTING_4 ((uint32_t)0x00000004) /* PC0 PC1 PC2 PC3 */
#define RI_INPUTCAPTUREROUTING_5 ((uint32_t)0x00000005) /* PC4 PC5 PC6 PC7 */
#define RI_INPUTCAPTUREROUTING_6 ((uint32_t)0x00000006) /* PC8 PC9 PC10 PC11 */
#define RI_INPUTCAPTUREROUTING_7 ((uint32_t)0x00000007) /* PC12 PC13 PC14 PC15 */
#define RI_INPUTCAPTUREROUTING_8 ((uint32_t)0x00000008) /* PD0 PD1 PD2 PD3 */
#define RI_INPUTCAPTUREROUTING_9 ((uint32_t)0x00000009) /* PD4 PD5 PD6 PD7 */
#define RI_INPUTCAPTUREROUTING_10 ((uint32_t)0x0000000A) /* PD8 PD9 PD10 PD11 */
#define RI_INPUTCAPTUREROUTING_11 ((uint32_t)0x0000000B) /* PD12 PD13 PD14 PD15 */
#define RI_INPUTCAPTUREROUTING_12 ((uint32_t)0x0000000C) /* PE0 PE1 PE2 PE3 */
#define RI_INPUTCAPTUREROUTING_13 ((uint32_t)0x0000000D) /* PE4 PE5 PE6 PE7 */
#define RI_INPUTCAPTUREROUTING_14 ((uint32_t)0x0000000E) /* PE8 PE9 PE10 PE11 */
#define RI_INPUTCAPTUREROUTING_15 ((uint32_t)0x0000000F) /* PE12 PE13 PE14 PE15 */
#define RI_INPUTCAPTUREROUTING_0 (0x00000000U) /* PA0 PA1 PA2 PA3 */
#define RI_INPUTCAPTUREROUTING_1 (0x00000001U) /* PA4 PA5 PA6 PA7 */
#define RI_INPUTCAPTUREROUTING_2 (0x00000002U) /* PA8 PA9 PA10 PA11 */
#define RI_INPUTCAPTUREROUTING_3 (0x00000003U) /* PA12 PA13 PA14 PA15 */
#define RI_INPUTCAPTUREROUTING_4 (0x00000004U) /* PC0 PC1 PC2 PC3 */
#define RI_INPUTCAPTUREROUTING_5 (0x00000005U) /* PC4 PC5 PC6 PC7 */
#define RI_INPUTCAPTUREROUTING_6 (0x00000006U) /* PC8 PC9 PC10 PC11 */
#define RI_INPUTCAPTUREROUTING_7 (0x00000007U) /* PC12 PC13 PC14 PC15 */
#define RI_INPUTCAPTUREROUTING_8 (0x00000008U) /* PD0 PD1 PD2 PD3 */
#define RI_INPUTCAPTUREROUTING_9 (0x00000009U) /* PD4 PD5 PD6 PD7 */
#define RI_INPUTCAPTUREROUTING_10 (0x0000000AU) /* PD8 PD9 PD10 PD11 */
#define RI_INPUTCAPTUREROUTING_11 (0x0000000BU) /* PD12 PD13 PD14 PD15 */
#define RI_INPUTCAPTUREROUTING_12 (0x0000000CU) /* PE0 PE1 PE2 PE3 */
#define RI_INPUTCAPTUREROUTING_13 (0x0000000DU) /* PE4 PE5 PE6 PE7 */
#define RI_INPUTCAPTUREROUTING_14 (0x0000000EU) /* PE8 PE9 PE10 PE11 */
#define RI_INPUTCAPTUREROUTING_15 (0x0000000FU) /* PE12 PE13 PE14 PE15 */
#define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \
((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \
@ -164,7 +164,7 @@
/** @defgroup RI_IOSwitch IO Switch
* @{
*/
#define RI_ASCR1_REGISTER ((uint32_t)0x80000000)
#define RI_ASCR1_REGISTER (0x80000000U)
/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */
#define RI_IOSWITCH_CH0 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0)
#define RI_IOSWITCH_CH1 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1)

18
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_adc.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
@ -859,7 +859,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
/* Enable conversion of regular group. */
/* If software start has been selected, conversion starts immediately. */
@ -1145,7 +1145,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
/* Enable end of conversion interrupt for regular group */
__HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
@ -1280,7 +1280,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
/* Enable ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
@ -1588,7 +1588,13 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
/**
* @brief ADC error callback in non blocking mode
* (ADC conversion with interruption or transfer by DMA)
* (ADC conversion with interruption or transfer by DMA)
* @note In case of error due to overrun when using ADC with DMA transfer
* (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
* - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
* - If needed, restart a new ADC conversion using function
* "HAL_ADC_Start_DMA()"
* (this function is also clearing overrun flag)
* @param hadc: ADC handle
* @retval None
*/

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_adc.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file containing functions prototypes of ADC HAL library.
******************************************************************************
* @attention

6
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_adc_ex.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
@ -637,7 +637,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
}
if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)
if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
{
assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
}

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_adc_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of ADC HAL Extension module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_comp.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief COMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the COMP peripheral:

24
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_comp.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of COMP HAL module.
******************************************************************************
* @attention
@ -133,7 +133,7 @@ typedef struct
/** @defgroup COMP_Output COMP Output
* @{
*/
#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x00000000) /*!< COMP2 output connected to TIM2 Input Capture 4 */
#define COMP_OUTPUT_TIM2IC4 (0x00000000U) /*!< COMP2 output connected to TIM2 Input Capture 4 */
#define COMP_OUTPUT_TIM2OCREFCLR ( COMP_CSR_OUTSEL_0) /*!< COMP2 output connected to TIM2 OCREF Clear */
#define COMP_OUTPUT_TIM3IC4 ( COMP_CSR_OUTSEL_1 ) /*!< COMP2 output connected to TIM3 Input Capture 4 */
#define COMP_OUTPUT_TIM3OCREFCLR ( COMP_CSR_OUTSEL_1 | COMP_CSR_OUTSEL_0) /*!< COMP2 output connected to TIM3 OCREF Clear */
@ -182,7 +182,7 @@ typedef struct
*/
/* Please refer to the electrical characteristics in the device datasheet for
the power consumption values */
#define COMP_MODE_LOWSPEED ((uint32_t)0x00000000) /*!< Low Speed */
#define COMP_MODE_LOWSPEED (0x00000000U) /*!< Low Speed */
#define COMP_MODE_HIGHSPEED COMP_CSR_SPEED /*!< High Speed */
#define IS_COMP_MODE(SPEED) (((SPEED) == COMP_MODE_LOWSPEED) || \
@ -194,7 +194,7 @@ typedef struct
/** @defgroup COMP_WindowMode COMP WindowMode
* @{
*/
#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disabled: COMP1 non-inverting input is independant */
#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled: COMP1 non-inverting input is independant */
#define COMP_WINDOWMODE_ENABLE COMP_CSR_WNDWE /*!< Window mode enabled: COMP1 non-inverting input is no more accessible, even from ADC channel VCOMP) (connected to COMP2 non-inverting input) */
#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \
@ -208,11 +208,11 @@ typedef struct
*/
/* Comparator output is low when the non-inverting input is at a lower */
/* voltage than the inverting input. */
#define COMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000)
#define COMP_OUTPUTLEVEL_LOW (0x00000000U)
/* Comparator output is high when the non-inverting input is at a higher */
/* voltage than the inverting input. */
#define COMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001)
#define COMP_OUTPUTLEVEL_HIGH (0x00000001U)
/**
* @}
*/
@ -220,10 +220,10 @@ typedef struct
/** @defgroup COMP_TriggerMode COMP TriggerMode
* @{
*/
#define COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000) /*!< No External Interrupt trigger detection */
#define COMP_TRIGGERMODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */
#define COMP_TRIGGERMODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */
#define COMP_TRIGGERMODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define COMP_TRIGGERMODE_NONE (0x00000000U) /*!< No External Interrupt trigger detection */
#define COMP_TRIGGERMODE_IT_RISING (0x00000001U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define COMP_TRIGGERMODE_IT_FALLING (0x00000002U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define COMP_TRIGGERMODE_IT_RISING_FALLING (0x00000003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define IS_COMP_TRIGGERMODE(MODE) (((MODE) == COMP_TRIGGERMODE_NONE) || \
((MODE) == COMP_TRIGGERMODE_IT_RISING) || \
@ -246,7 +246,7 @@ typedef struct
/** @defgroup COMP_NonInvertingInputPull COMP NonInvertingInputPull
* @{
*/
#define COMP_NONINVERTINGINPUT_NOPULL ((uint32_t)0x00000000) /*!< No internal pull-up or pull-down resistor connected to comparator non inverting input */
#define COMP_NONINVERTINGINPUT_NOPULL (0x00000000U) /*!< No internal pull-up or pull-down resistor connected to comparator non inverting input */
#define COMP_NONINVERTINGINPUT_10KPU COMP_CSR_10KPU /*!< Internal 10kOhm pull-up resistor connected to comparator non inverting input */
#define COMP_NONINVERTINGINPUT_10KPD COMP_CSR_10KPD /*!< Internal 10kOhm pull-down resistor connected to comparator non inverting input */
#define COMP_NONINVERTINGINPUT_400KPU COMP_CSR_400KPU /*!< Internal 400kOhm pull-up resistor connected to comparator non inverting input */

10
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_comp_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of COMP HAL Extension module.
******************************************************************************
* @attention
@ -71,7 +71,7 @@
#define COMP_NONINVERTINGINPUT_PB7 RI_IOSWITCH_GR6_4 /*!< I/O pin PB7 connection to COMP2 non-inverting input */
/* Non-inverting inputs specific to COMP1 */
#define COMP_NONINVERTINGINPUT_NONE ((uint32_t)0x00000000) /*!< In case of window mode: No I/O pin connection to COMP1 non-inverting input. Instead, connection to COMP2 non-inverting input. */
#define COMP_NONINVERTINGINPUT_NONE (0x00000000U) /*!< In case of window mode: No I/O pin connection to COMP1 non-inverting input. Instead, connection to COMP2 non-inverting input. */
#define COMP_NONINVERTINGINPUT_PA0 RI_IOSWITCH_CH0 /*!< I/O pin PA0 connection to COMP1 non-inverting input */
#define COMP_NONINVERTINGINPUT_PA1 RI_IOSWITCH_CH1 /*!< I/O pin PA1 connection to COMP1 non-inverting input */
#define COMP_NONINVERTINGINPUT_PA2 RI_IOSWITCH_CH2 /*!< I/O pin PA2 connection to COMP1 non-inverting input */
@ -117,7 +117,7 @@
#define COMP_NONINVERTINGINPUT_PB7 RI_IOSWITCH_GR6_4 /*!< I/O pin PB7 connection to COMP2 non-inverting input */
/* Non-inverting inputs specific to COMP1 */
#define COMP_NONINVERTINGINPUT_NONE ((uint32_t)0x00000000) /*!< In case of window mode: No I/O pin connection to COMP1 non-inverting input. Instead, connection to COMP2 non-inverting input. */
#define COMP_NONINVERTINGINPUT_NONE (0x00000000U) /*!< In case of window mode: No I/O pin connection to COMP1 non-inverting input. Instead, connection to COMP2 non-inverting input. */
#define COMP_NONINVERTINGINPUT_PA0 RI_IOSWITCH_CH0 /*!< I/O pin PA0 connection to COMP1 non-inverting input */
#define COMP_NONINVERTINGINPUT_PA1 RI_IOSWITCH_CH1 /*!< I/O pin PA1 connection to COMP1 non-inverting input */
#define COMP_NONINVERTINGINPUT_PA2 RI_IOSWITCH_CH2 /*!< I/O pin PA2 connection to COMP1 non-inverting input */
@ -153,7 +153,7 @@
#define COMP_NONINVERTINGINPUT_PB5 RI_IOSWITCH_GR6_2 /*!< I/O pin PB5 connection to COMP2 non-inverting input */
/* Non-inverting inputs specific to COMP1 */
#define COMP_NONINVERTINGINPUT_NONE ((uint32_t)0x00000000) /*!< In case of window mode: No I/O pin connection to COMP1 non-inverting input. Instead, connection to COMP2 non-inverting input. */
#define COMP_NONINVERTINGINPUT_NONE (0x00000000U) /*!< In case of window mode: No I/O pin connection to COMP1 non-inverting input. Instead, connection to COMP2 non-inverting input. */
#define COMP_NONINVERTINGINPUT_PA0 RI_IOSWITCH_CH0 /*!< I/O pin PA0 connection to COMP1 non-inverting input */
#define COMP_NONINVERTINGINPUT_PA1 RI_IOSWITCH_CH1 /*!< I/O pin PA1 connection to COMP1 non-inverting input */
#define COMP_NONINVERTINGINPUT_PA2 RI_IOSWITCH_CH2 /*!< I/O pin PA2 connection to COMP1 non-inverting input */

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cortex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_cortex.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief CORTEX HAL module driver.
*
* This file provides firmware functions to manage the following

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cortex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_cortex.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention

7
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_crc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_crc.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@ -158,6 +158,9 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Reset IDR register content */
CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ;
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_crc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_crc.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_cryp.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief CRYP HAL module driver.
*
* This file provides firmware functions to manage the following

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_cryp.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_cryp_ex.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief CRYPEx HAL module driver.
*
* This file provides firmware functions to manage the following

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_cryp_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of CRYPEx HAL module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_dac.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_dac.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_dac_ex.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DAC extension peripheral:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_dac_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention

66
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_def.h
View File

@ -2,10 +2,10 @@
******************************************************************************
* @file stm32l1xx_hal_def.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
* @version V1.2.0
* @date 01-July-2016
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
@ -51,10 +51,10 @@
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL Status structures definition
*/
typedef enum
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00,
HAL_ERROR = 0x01,
@ -62,18 +62,18 @@ typedef enum
HAL_TIMEOUT = 0x03
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
/**
* @brief HAL Lock structures definition
*/
typedef enum
typedef enum
{
HAL_UNLOCKED = 0x00,
HAL_LOCKED = 0x01
HAL_LOCKED = 0x01
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/
#define HAL_MAX_DELAY 0xFFFFFFFF
#define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
@ -88,11 +88,11 @@ typedef enum
/** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function
* Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
@ -139,62 +139,62 @@ typedef enum
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4)
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/**
/**
* @brief __RAM_FUNC definition
*/
*/
#if defined ( __CC_ARM )
/* ARM Compiler
------------
RAM functions are defined using the toolchain options.
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog.
dialog.
*/
#define __RAM_FUNC HAL_StatusTypeDef
#define __RAM_FUNC HAL_StatusTypeDef
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc".
RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
#elif defined ( __GNUC__ )
/* GNU Compiler
------------
RAM functions are defined using a specific toolchain attribute
RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
*/
#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))
#endif
/**
/**
* @brief __NOINLINE definition
*/
*/
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
/* ARM & GNUCompiler
----------------
/* ARM & GNUCompiler
----------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
#define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ )
/* ICCARM Compiler

532
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma.c
View File

@ -2,10 +2,9 @@
******************************************************************************
* @file stm32l1xx_hal_dma.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
* functionalities of the Direct Memory Access (DMA) peripheral:
* + Initialization and de-initialization functions
@ -18,12 +17,12 @@
[..]
(#) Enable and configure the peripheral to be connected to the DMA Channel
(except for internal SRAM / FLASH memories: no initialization is
necessary) please refer to Reference manual for connection between peripherals
necessary). Please refer to the Reference manual for connection between peripherals
and DMA requests.
(#) For a given Channel, program the required configuration through the following parameters:
Transfer Direction, Source and Destination data formats,
Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
Channel request, Transfer Direction, Source and Destination data formats,
Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
using HAL_DMA_Init() function.
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
@ -48,10 +47,10 @@
(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
Source address and destination address and the Length of data to be transferred.
In this case the DMA interrupt is configured
(+) Use HAL_DMAy_Channelx_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
(+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
add his own function by customization of function pointer XferCpltCallback and
XferErrorCallback (i.e a member of DMA handle structure).
XferErrorCallback (i.e. a member of DMA handle structure).
*** DMA HAL driver macros list ***
=============================================
@ -116,14 +115,6 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup DMA_Private_Constants DMA Private Constants
* @{
*/
#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@ -131,6 +122,7 @@
* @{
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
/**
* @}
*/
@ -161,8 +153,8 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
*/
/**
* @brief Initializes the DMA according to the specified
* parameters in the DMA_InitTypeDef and create the associated handle.
* @brief Initialize the DMA according to the specified
* parameters in the DMA_InitTypeDef and initialize the associated handle.
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
@ -187,11 +179,26 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
assert_param(IS_DMA_MODE(hdma->Init.Mode));
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
if(hdma->State == HAL_DMA_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hdma->Lock = HAL_UNLOCKED;
#if defined (DMA2)
/* calculation of the channel index */
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
{
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
hdma->DmaBaseAddress = DMA1;
}
else
{
/* DMA2 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
hdma->DmaBaseAddress = DMA2;
}
#else
/* calculation of the channel index */
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
hdma->DmaBaseAddress = DMA1;
#endif
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
@ -213,17 +220,26 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
/* Write to DMA Channel CR register */
hdma->Instance->CCR = tmp;
/* Clean callbacks */
hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL;
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Initialize the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
/* Allocate lock resource and initialize it */
hdma->Lock = HAL_UNLOCKED;
return HAL_OK;
}
/**
* @brief DeInitializes the DMA peripheral
* @brief DeInitialize the DMA peripheral.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
@ -231,41 +247,54 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
{
/* Check the DMA handle allocation */
if(hdma == NULL)
if (NULL == hdma )
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
/* Check the DMA peripheral state */
if(hdma->State == HAL_DMA_STATE_BUSY)
{
return HAL_ERROR;
}
/* Disable the selected DMA Channelx */
__HAL_DMA_DISABLE(hdma);
#if defined (DMA2)
/* calculation of the channel index */
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
{
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
hdma->DmaBaseAddress = DMA1;
}
else
{
/* DMA2 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
hdma->DmaBaseAddress = DMA2;
}
#else
/* calculation of the channel index */
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
hdma->DmaBaseAddress = DMA1;
#endif
/* Reset DMA Channel control register */
hdma->Instance->CCR = 0;
/* Reset DMA Channel Number of Data to Transfer register */
hdma->Instance->CNDTR = 0;
/* Reset DMA Channel peripheral address register */
hdma->Instance->CPAR = 0;
/* Reset DMA Channel memory address register */
hdma->Instance->CMAR = 0;
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
/* Initialize the error code */
hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Initialize the DMA state */
@ -282,7 +311,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
*/
/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
* @brief I/O operation functions
* @brief Input and Output operation functions
*
@verbatim
===============================================================================
@ -301,7 +330,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
*/
/**
* @brief Starts the DMA Transfer.
* @brief Start the DMA Transfer.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @param SrcAddress: The source memory Buffer address
@ -311,25 +340,36 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
*/
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
/* Configure the source, destination address and the data length */
/* Configure the source, destination address and the data length & clear flags*/
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
return HAL_OK;
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hdma);
status = HAL_BUSY;
}
return status;
}
/**
@ -343,83 +383,121 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
/* Configure the source, destination address and the data length */
/* Configure the source, destination address and the data length & clear flags*/
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the transfer complete interrupt */
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
/* Enable the Half transfer complete interrupt */
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
/* Enable the transfer Error interrupt */
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
if(NULL != hdma->XferHalfCpltCallback )
{
/* Enable the Half transfer complete interrupt as well */
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
}
else
{
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
}
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_OK;
/* Remain BUSY */
status = HAL_BUSY;
}
return status;
}
/**
* @brief Aborts the DMA Transfer.
* @brief Abort the DMA Transfer.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
*
* @note After disabling a DMA Channel, a check for wait until the DMA Channel is
* effectively disabled is added. If a Channel is disabled
* while a data transfer is ongoing, the current data will be transferred
* and the Channel will be effectively disabled only after the transfer of
* this single data is finished.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
uint32_t tickstart = 0x00;
HAL_StatusTypeDef status = HAL_OK;
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
/* Get tick */
tickstart = HAL_GetTick();
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
/* Check if the DMA Channel is effectively disabled */
while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
{
/* Update error code */
SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_TIMEOUT;
}
}
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_OK;
return status;
}
/**
* @brief Aborts the DMA Transfer in Interrupt mode.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
HAL_StatusTypeDef status = HAL_OK;
if(HAL_DMA_STATE_BUSY != hdma->State)
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
status = HAL_ERROR;
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Call User Abort callback */
if(hdma->XferAbortCallback != NULL)
{
hdma->XferAbortCallback(hdma);
}
}
return status;
}
/**
@ -433,35 +511,52 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
{
uint32_t temp;
uint32_t tickstart = 0x00;
uint32_t tickstart = 0;
if(HAL_DMA_STATE_BUSY != hdma->State)
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
/* Polling mode not supported in circular mode */
if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
{
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
return HAL_ERROR;
}
/* Get the level transfer complete flag */
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
{
/* Transfer Complete flag */
temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
}
else
{
/* Half Transfer Complete flag */
temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
temp = DMA_FLAG_HT1 << hdma->ChannelIndex;
}
/* Get tick */
tickstart = HAL_GetTick();
while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
while(RESET == (hdma->DmaBaseAddress->ISR & temp))
{
if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
if((RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex))))
{
/* Clear the transfer error flags */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
/* Update error code */
SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
hdma->ErrorCode = HAL_DMA_ERROR_TE;
/* Change the DMA state */
hdma->State= HAL_DMA_STATE_ERROR;
hdma->State= HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
@ -474,37 +569,32 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Update error code */
SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_TIMEOUT;
hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_TIMEOUT;
return HAL_ERROR;
}
}
}
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
{
/* Clear the transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << hdma->ChannelIndex);
/* The selected Channelx EN bit is cleared (DMA is disabled and
all transfers are complete) */
hdma->State = HAL_DMA_STATE_READY;
}
else
{
/* Clear the half transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
/* The selected Channelx EN bit is cleared (DMA is disabled and
all transfers of half buffer are complete) */
hdma->State = HAL_DMA_STATE_READY_HALF;
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << hdma->ChannelIndex);
}
/* Process unlocked */
@ -514,45 +604,18 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
}
/**
* @brief Handles DMA interrupt request.
* @brief Handle DMA interrupt request.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval None
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
/* Transfer Error Interrupt management ***************************************/
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
{
/* Disable the transfer error interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
uint32_t source_it = hdma->Instance->CCR;
/* Clear the transfer error flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
/* Update error code */
SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
if (hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
}
}
}
/* Half Transfer Complete Interrupt management ******************************/
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
@ -561,10 +624,10 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
}
/* Clear the half transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << hdma->ChannelIndex);
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_READY_HALF;
/* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */
if(hdma->XferHalfCpltCallback != NULL)
{
@ -572,23 +635,45 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
hdma->XferHalfCpltCallback(hdma);
}
}
}
/* Transfer Complete Interrupt management ***********************************/
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
{
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
{
/* Disable the transfer complete interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
}
/* Clear the transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
/* Disable TE & TC */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
}
/* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << hdma->ChannelIndex);
/* Process Unlocked */
__HAL_UNLOCK(hdma);
if(hdma->XferCpltCallback != NULL)
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);
}
}
/* Transfer Error Interrupt management **************************************/
else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
{
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Disable ALL DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
/* Update error code */
SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE);
hdma->ErrorCode = HAL_DMA_ERROR_TE;
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
@ -596,25 +681,138 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Process Unlocked */
__HAL_UNLOCK(hdma);
if(hdma->XferCpltCallback != NULL)
if (hdma->XferErrorCallback != NULL)
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
}
}
return;
}
/**
* @brief Register callbacks
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param CallbackID: User Callback identifer
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @param pCallback: pointer to private callbacsk function which has pointer to
* a DMA_HandleTypeDef structure as parameter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
switch (CallbackID)
{
case HAL_DMA_XFER_CPLT_CB_ID:
hdma->XferCpltCallback = pCallback;
break;
case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma->XferHalfCpltCallback = pCallback;
break;
case HAL_DMA_XFER_ERROR_CB_ID:
hdma->XferErrorCallback = pCallback;
break;
case HAL_DMA_XFER_ABORT_CB_ID:
hdma->XferAbortCallback = pCallback;
break;
default:
status = HAL_ERROR;
break;
}
}
else
{
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdma);
return status;
}
/**
* @brief UnRegister callbacks
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param CallbackID: User Callback identifer
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
switch (CallbackID)
{
case HAL_DMA_XFER_CPLT_CB_ID:
hdma->XferCpltCallback = NULL;
break;
case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma->XferHalfCpltCallback = NULL;
break;
case HAL_DMA_XFER_ERROR_CB_ID:
hdma->XferErrorCallback = NULL;
break;
case HAL_DMA_XFER_ABORT_CB_ID:
hdma->XferAbortCallback = NULL;
break;
case HAL_DMA_XFER_ALL_CB_ID:
hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL;
break;
default:
status = HAL_ERROR;
break;
}
}
else
{
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdma);
return status;
}
/**
* @}
*/
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral State and Errors functions
*
@verbatim
===============================================================================
##### State and Errors functions #####
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection provides functions allowing to
@ -626,18 +824,19 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
*/
/**
* @brief Returns the DMA state.
* @brief Return the DMA hande state.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL state
*/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
{
/* Return DMA handle state */
return hdma->State;
}
/**
* @brief Return the DMA error code
* @brief Return the DMA error code.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval DMA Error Code
@ -655,7 +854,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
* @}
*/
/** @addtogroup DMA_Private_Functions DMA Private Functions
/** @addtogroup DMA_Private_Functions
* @{
*/
@ -670,6 +869,9 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;
@ -693,6 +895,10 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
}
}
/**
* @}
*/
/**
* @}
*/

339
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_dma.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
@ -91,26 +91,14 @@ typedef struct
} DMA_InitTypeDef;
/**
* @brief DMA Configuration enumeration values definition
*/
typedef enum
{
DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
} DMA_ControlTypeDef;
/**
* @brief HAL DMA State structures definition
*/
typedef enum
{
HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
}HAL_DMA_StateTypeDef;
/**
@ -119,9 +107,23 @@ typedef enum
typedef enum
{
HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */
}HAL_DMA_LevelCompleteTypeDef;
/**
* @brief HAL DMA Callback ID structure definition
*/
typedef enum
{
HAL_DMA_XFER_CPLT_CB_ID = 0x00, /*!< Full transfer */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01, /*!< Half transfer */
HAL_DMA_XFER_ERROR_CB_ID = 0x02, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x03, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */
}HAL_DMA_CallbackIDTypeDef;
/**
* @brief DMA handle Structure definition
*/
@ -133,7 +135,7 @@ typedef struct __DMA_HandleTypeDef
HAL_LockTypeDef Lock; /*!< DMA locking object */
HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
void *Parent; /*!< Parent object state */
@ -143,7 +145,14 @@ typedef struct __DMA_HandleTypeDef
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
uint32_t ChannelIndex; /*!< DMA Channel Index */
} DMA_HandleTypeDef;
/**
* @}
@ -158,9 +167,26 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_Error_Code DMA Error Code
* @{
*/
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00) /*!< No error */
#define HAL_DMA_ERROR_TE ((uint32_t)0x01) /*!< Transfer error */
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x20) /*!< Timeout error */
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoing transfer */
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100) /*!< Not supported mode */
/**
* @}
*/
/** @defgroup DMA_request DMA request
* @{
*/
#define DMA_REQUEST_0 ((uint32_t)0x00000000)
#define DMA_REQUEST_1 ((uint32_t)0x00000001)
#define DMA_REQUEST_2 ((uint32_t)0x00000002)
#define DMA_REQUEST_3 ((uint32_t)0x00000003)
#define DMA_REQUEST_4 ((uint32_t)0x00000004)
#define DMA_REQUEST_5 ((uint32_t)0x00000005)
#define DMA_REQUEST_6 ((uint32_t)0x00000006)
#define DMA_REQUEST_7 ((uint32_t)0x00000007)
/**
* @}
@ -285,14 +311,13 @@ typedef struct __DMA_HandleTypeDef
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup DMA_Exported_Macros DMA Exported Macros
* @{
*/
/** @brief Reset DMA handle state
* @param __HANDLE__: DMA handle.
* @param __HANDLE__: DMA handle
* @retval None
*/
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
@ -300,22 +325,220 @@ typedef struct __DMA_HandleTypeDef
/**
* @brief Enable the specified DMA Channel.
* @param __HANDLE__: DMA handle
* @retval None.
* @retval None
*/
#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
/**
* @brief Disable the specified DMA Channel.
* @param __HANDLE__: DMA handle
* @retval None.
* @retval None
*/
#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
/* Interrupt & Flag management */
#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
/**
* @brief Enables the specified DMA Channel interrupts.
* @brief Return the current DMA Channel transfer complete flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
DMA_FLAG_TC7)
/**
* @brief Return the current DMA Channel half transfer complete flag.
* @param __HANDLE__: DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
DMA_FLAG_HT7)
/**
* @brief Return the current DMA Channel transfer error flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
DMA_FLAG_TE7)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
DMA_ISR_GIF7)
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle
* @param __FLAG__: Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* @arg DMA_FLAG_GLx: Global interrupt flag
* Where x can be from 1 to 7 to select the DMA Channel x flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
(DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
/**
* @brief Clear the DMA Channel pending flags.
* @param __HANDLE__: DMA handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* @arg DMA_FLAG_GLx: Global interrupt flag
* Where x can be from 1 to 7 to select the DMA Channel x flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
#else
/**
* @brief Return the current DMA Channel transfer complete flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
DMA_FLAG_TC7)
/**
* @brief Return the current DMA Channel half transfer complete flag.
* @param __HANDLE__: DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
DMA_FLAG_HT7)
/**
* @brief Return the current DMA Channel transfer error flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
DMA_FLAG_TE7)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
DMA_ISR_GIF7)
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle
* @param __FLAG__: Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* @arg DMA_FLAG_GLx: Global interrupt flag
* Where x can be from 1 to 7 to select the DMA Channel x flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
/**
* @brief Clear the DMA Channel pending flags.
* @param __HANDLE__: DMA handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* @arg DMA_FLAG_GLx: Global interrupt flag
* Where x can be from 1 to 7 to select the DMA Channel x flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
/**
* @brief Enable the specified DMA Channel interrupts.
* @param __HANDLE__: DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
@ -324,10 +547,10 @@ typedef struct __DMA_HandleTypeDef
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
/**
* @brief Disables the specified DMA Channel interrupts.
* @brief Disable the specified DMA Channel interrupts.
* @param __HANDLE__: DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
@ -336,10 +559,10 @@ typedef struct __DMA_HandleTypeDef
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
* @brief Check whether the specified DMA Channel interrupt is enabled or not.
* @param __HANDLE__: DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
@ -348,21 +571,26 @@ typedef struct __DMA_HandleTypeDef
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval The state of DMA_IT (SET or RESET).
*/
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
/**
* @brief Return the number of remaining data units in the current DMA Channel transfer.
* @param __HANDLE__: DMA handle
* @retval The number of remaining data units in the current DMA Channel transfer.
*/
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
/**
* @}
*/
/* Include DMA HAL Extension module */
#include "stm32l1xx_hal_dma_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA_Exported_Functions DMA Exported Functions
/** @addtogroup DMA_Exported_Functions
* @{
*/
/** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
/** @addtogroup DMA_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
@ -372,20 +600,24 @@ HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
* @}
*/
/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
/** @addtogroup DMA_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
/**
* @}
*/
/** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
/** @addtogroup DMA_Exported_Functions_Group3
* @{
*/
/* Peripheral State and Error functions ***************************************/
@ -399,33 +631,31 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
* @}
*/
/* Private Constants -------------------------------------------------------------*/
/** @defgroup DMA_Private_Constants DMA Private Constants
* @brief DMA private defines and constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMA_Private_Macros DMA Private Macros
* @brief DMA private macros
* @{
*/
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
((STATE) == DMA_PINC_DISABLE))
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
((STATE) == DMA_MINC_DISABLE))
#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
((REQUEST) == DMA_REQUEST_1) || \
((REQUEST) == DMA_REQUEST_2) || \
((REQUEST) == DMA_REQUEST_3) || \
((REQUEST) == DMA_REQUEST_4) || \
((REQUEST) == DMA_REQUEST_5) || \
((REQUEST) == DMA_REQUEST_6) || \
((REQUEST) == DMA_REQUEST_7))
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
((SIZE) == DMA_PDATAALIGN_WORD))
@ -447,13 +677,6 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DMA_Private_Functions DMA Private Functions
* @brief DMA private functions
* @{
*/
/**
* @}
*/
/**
* @}

244
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma_ex.h
View File

@ -1,244 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_dma_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_HAL_DMA_EX_H
#define __STM32L1xx_HAL_DMA_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal_def.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @defgroup DMAEx DMAEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
* @{
*/
/* Interrupt & Flag management */
#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
/**
* @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
DMA_FLAG_TC5)
/**
* @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__: DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
DMA_FLAG_HT5)
/**
* @brief Returns the current DMA Channel transfer error flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
DMA_FLAG_TE5)
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle
* @param __FLAG__: Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 or 1_5 to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
(DMA1->ISR & (__FLAG__)))
/**
* @brief Clears the DMA Channel pending flags.
* @param __HANDLE__: DMA handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 or 1_5 to select the DMA Channel flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
(DMA1->IFCR = (__FLAG__)))
#else
/**
* @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
DMA_FLAG_TC7)
/**
* @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__: DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
DMA_FLAG_HT7)
/**
* @brief Returns the current DMA Channel transfer error flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
DMA_FLAG_TE7)
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle
* @param __FLAG__: Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
/**
* @brief Clears the DMA Channel pending flags.
* @param __HANDLE__: DMA handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 to select the DMA Channel flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32L1xx_HAL_DMA_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

107
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_flash.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@ -52,8 +52,7 @@
FastProgramWord, Program Byte, Program Half-Word,
Program Word and Program Double-Word (should be executed
from internal SRAM).
(#) FLASH Option Bytes Programming functions: this group includes all needed
functions to manage the Option Bytes:
(++) Lock and Unlock the Option Bytes
@ -87,7 +86,7 @@
(+) Set/Get the latency
(+) Enable/Disable the prefetch buffer
(+) Enable/Disable the 64 bit Read Access.
(+) Enable/Disable the 64 bit Read Access.
(+) Enable/Disable the Flash power-down
(+) Enable/Disable the FLASH interrupts
(+) Monitor the FLASH flags status
@ -215,6 +214,7 @@ FLASH_ProcessTypeDef pFlash;
* @{
*/
static void FLASH_SetErrorCode(void);
extern void FLASH_PageErase(uint32_t PageAddress);
/**
* @}
*/
@ -246,7 +246,7 @@ static void FLASH_SetErrorCode(void);
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
{
HAL_StatusTypeDef status = HAL_ERROR;
@ -258,7 +258,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
@ -269,7 +269,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
*(__IO uint32_t *)Address = Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
}
/* Process Unlocked */
@ -288,7 +288,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
{
HAL_StatusTypeDef status = HAL_OK;
@ -309,7 +309,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
{
/*Program word (32-bit) at a specified address.*/
/* Program word (32-bit) at a specified address. */
*(__IO uint32_t *)Address = Data;
}
return status;
@ -324,35 +324,35 @@ void HAL_FLASH_IRQHandler(void)
uint32_t addresstmp = 0;
/* Check FLASH operation error flags */
if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) ||
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) ||
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) ||
if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) ||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) ||
#if defined(FLASH_SR_RDERR)
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) ||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) ||
#endif /* FLASH_SR_RDERR */
#if defined(FLASH_SR_OPTVERRUSR)
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) ||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) ||
#endif /* FLASH_SR_OPTVERRUSR */
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) )
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) )
{
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
{
/*return the faulty sector*/
/* Return the faulty sector */
addresstmp = pFlash.Page;
pFlash.Page = 0xFFFFFFFF;
pFlash.Page = 0xFFFFFFFFU;
}
else
{
/*return the faulty address*/
/* Return the faulty address */
addresstmp = pFlash.Address;
}
/*Save the Error code*/
/* Save the Error code */
FLASH_SetErrorCode();
/* FLASH error interrupt user callback */
HAL_FLASH_OperationErrorCallback(addresstmp);
/* Stop the procedure ongoing*/
/* Stop the procedure ongoing */
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
@ -370,11 +370,11 @@ void HAL_FLASH_IRQHandler(void)
/* Nb of pages to erased can be decreased */
pFlash.NbPagesToErase--;
/* Check if there are still pages to erase*/
/* Check if there are still pages to erase */
if(pFlash.NbPagesToErase != 0)
{
addresstmp = pFlash.Page;
/*Indicate user which sector has been erased*/
/*Indicate user which sector has been erased */
HAL_FLASH_EndOfOperationCallback(addresstmp);
/*Increment sector number*/
@ -388,9 +388,9 @@ void HAL_FLASH_IRQHandler(void)
}
else
{
/*No more pages to Erase, user callback can be called.*/
/*Reset Sector and stop Erase pages procedure*/
pFlash.Page = addresstmp = 0xFFFFFFFF;
/* No more pages to Erase, user callback can be called. */
/* Reset Sector and stop Erase pages procedure */
pFlash.Page = addresstmp = 0xFFFFFFFFU;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(addresstmp);
@ -401,12 +401,12 @@ void HAL_FLASH_IRQHandler(void)
/* If the program operation is completed, disable the PROG Bit */
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
/*Program ended. Return the selected address*/
/* Program ended. Return the selected address */
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
/* Reset Address and stop Program procedure*/
pFlash.Address = 0xFFFFFFFF;
/* Reset Address and stop Program procedure */
pFlash.Address = 0xFFFFFFFFU;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
}
@ -426,7 +426,6 @@ void HAL_FLASH_IRQHandler(void)
}
}
/**
* @brief FLASH end of operation interrupt callback
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
@ -517,11 +516,9 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void)
/* Set the PRGLOCK Bit to lock the FLASH Registers access */
SET_BIT(FLASH->PECR, FLASH_PECR_PRGLOCK);
return HAL_OK;
}
/**
* @brief Unlock the FLASH Option Control Registers access.
* @retval HAL Status
@ -565,7 +562,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
/**
* @brief Launch the option byte loading.
* @note This function will reset automatically the MCU.
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
{
@ -573,22 +570,22 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
SET_BIT(FLASH->PECR, FLASH_PECR_OBL_LAUNCH);
/* Wait for last operation to be completed */
return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE));
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
* @brief Peripheral errors functions
*
@verbatim
===============================================================================
##### Peripheral State functions #####
##### Peripheral Errors functions #####
===============================================================================
[..]
This subsection permit to get in run-time the status of the FLASH peripheral.
This subsection permit to get in run-time errors of the FLASH peripheral.
@endverbatim
* @{
@ -596,13 +593,14 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
/**
* @brief Get the specific FLASH error flag.
* @retval FLASH_ErrorCode: The returned value can be:
* @retval FLASH_ErrorCode The returned value can be:
* @ref FLASH_Error_Codes
*/
uint32_t HAL_FLASH_GetError(void)
{
{
return pFlash.ErrorCode;
}
}
/**
* @}
*/
@ -615,11 +613,10 @@ uint32_t HAL_FLASH_GetError(void)
* @{
*/
/**
* @brief Wait for a FLASH operation to complete.
* @param Timeout: maximum flash operation timeout
* @retval HAL_StatusTypeDef HAL Status
* @param Timeout maximum flash operation timeout
* @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
@ -662,7 +659,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
return HAL_ERROR;
}
/* If there is no error flag set */
/* There is no error flag set */
return HAL_OK;
}
@ -672,40 +669,42 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
* @retval None
*/
static void FLASH_SetErrorCode(void)
{
{
uint32_t flags = 0;
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
flags |= FLASH_FLAG_WRPERR;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
flags |= FLASH_FLAG_PGAERR;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
flags |= FLASH_FLAG_OPTVERR;
}
#if defined(FLASH_SR_RDERR)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR);
flags |= FLASH_FLAG_RDERR;
}
#endif /* FLASH_SR_RDERR */
#if defined(FLASH_SR_OPTVERRUSR)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTVUSR;
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERRUSR);
flags |= FLASH_FLAG_OPTVERRUSR;
}
#endif /* FLASH_SR_OPTVERRUSR */
/* Clear FLASH error pending bits */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR);
__HAL_FLASH_CLEAR_FLAG(flags);
}
/**
* @}

113
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_flash.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of Flash HAL module.
******************************************************************************
* @attention
@ -57,7 +57,7 @@
/** @addtogroup FLASH_Private_Constants
* @{
*/
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U) /* 50 s */
/**
* @}
*/
@ -80,7 +80,6 @@
* @{
*/
/**
* @brief FLASH Procedure structure definition
*/
@ -123,24 +122,25 @@ typedef struct
* @{
*/
#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00) /*!< No error */
#define HAL_FLASH_ERROR_PGA ((uint32_t)0x01) /*!< Programming alignment error */
#define HAL_FLASH_ERROR_WRP ((uint32_t)0x02) /*!< Write protection error */
#define HAL_FLASH_ERROR_OPTV ((uint32_t)0x04) /*!< Option validity error */
#define HAL_FLASH_ERROR_SIZE ((uint32_t)0x08) /*!< */
#define HAL_FLASH_ERROR_OPTVUSR ((uint32_t)0x10) /*!< Option UserValidity Error. */
#define HAL_FLASH_ERROR_RD ((uint32_t)0x20) /*!< Read protected error */
#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x40) /*!< Not used */
#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
#define HAL_FLASH_ERROR_PGA 0x01U /*!< Programming alignment error */
#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */
#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */
#define HAL_FLASH_ERROR_SIZE 0x08U /*!< */
#define HAL_FLASH_ERROR_RD 0x10U /*!< Read protected error */
#define HAL_FLASH_ERROR_OPTVUSR 0x20U /*!< Option UserValidity Error. */
#define HAL_FLASH_ERROR_OPERATION 0x40U /*!< Not used */
/**
* @}
*/
/** @defgroup FLASH_Page_Size FLASH Page Size
/** @defgroup FLASH_Page_Size FLASH size information
* @{
*/
#define FLASH_PAGE_SIZE ((uint32_t)256)
#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASHSIZE_BASE) * 1024U)
#define FLASH_PAGE_SIZE ((uint32_t)256U) /*!< FLASH Page Size in bytes */
/**
* @}
@ -149,7 +149,7 @@ typedef struct
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02) /*!<Program a word (32-bit) at a specified address.*/
#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!<Program a word (32-bit) at a specified address.*/
/**
* @}
@ -158,7 +158,7 @@ typedef struct
/** @defgroup FLASH_Latency FLASH Latency
* @{
*/
#define FLASH_LATENCY_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_0 ((uint32_t)0x00000000U) /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */
/**
@ -187,6 +187,14 @@ typedef struct
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */
/* Cat2 & Cat3*/
#if defined(FLASH_SR_RDERR)
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< Read protected error flag */
#endif /* FLASH_SR_RDERR */
/* Cat3, Cat4 & Cat5*/
#if defined(FLASH_SR_OPTVERRUSR)
#define FLASH_FLAG_OPTVERRUSR FLASH_SR_OPTVERRUSR /*!< FLASH Option User Validity error flag */
#endif /* FLASH_SR_OPTVERRUSR */
/**
* @}
@ -196,21 +204,21 @@ typedef struct
* @{
*/
#define FLASH_PDKEY1 ((uint32_t)0x04152637) /*!< Flash power down key1 */
#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1
#define FLASH_PDKEY1 ((uint32_t)0x04152637U) /*!< Flash power down key1 */
#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1
to unlock the RUN_PD bit in FLASH_ACR */
#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEF) /*!< Flash program erase key1 */
#define FLASH_PEKEY2 ((uint32_t)0x02030405) /*!< Flash program erase key: used with FLASH_PEKEY2
#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEFU) /*!< Flash program erase key1 */
#define FLASH_PEKEY2 ((uint32_t)0x02030405U) /*!< Flash program erase key: used with FLASH_PEKEY2
to unlock the write access to the FLASH_PECR register and
data EEPROM */
#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF) /*!< Flash program memory key1 */
#define FLASH_PRGKEY2 ((uint32_t)0x13141516) /*!< Flash program memory key2: used with FLASH_PRGKEY2
#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBFU) /*!< Flash program memory key1 */
#define FLASH_PRGKEY2 ((uint32_t)0x13141516U) /*!< Flash program memory key2: used with FLASH_PRGKEY2
to unlock the program memory */
#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8) /*!< Flash option key1 */
#define FLASH_OPTKEY2 ((uint32_t)0x24252627) /*!< Flash option key2: used with FLASH_OPTKEY1 to
#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8U) /*!< Flash option key1 */
#define FLASH_OPTKEY2 ((uint32_t)0x24252627U) /*!< Flash option key2: used with FLASH_OPTKEY1 to
unlock the write access to the option byte block */
/**
* @}
@ -263,8 +271,30 @@ typedef struct
* @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag
* @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag
* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error error flag
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option UserValidity (available only Cat.3, Cat.4 and Cat.5 devices)
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) (available only Cat.2 and Cat.3 devices)
@if STM32L100xB
@elif STM32L100xBA
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
@elif STM32L151xB
@elif STM32L151xBA
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
@elif STM32L152xB
@elif STM32L152xBA
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
@elif STM32L100xC
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@elif STM32L151xC
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@elif STM32L152xC
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@elif STM32L162xC
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@else
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@endif
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
* @retval The new state of __FLAG__ (SET or RESET).
*/
@ -280,8 +310,30 @@ typedef struct
* @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag
* @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag
* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error error flag
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option UserValidity (available only Cat.3, Cat.4 and Cat.5 devices)
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) (available only Cat.2 and Cat.3 devices)
@if STM32L100xB
@elif STM32L100xBA
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
@elif STM32L151xB
@elif STM32L151xBA
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
@elif STM32L152xB
@elif STM32L152xBA
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
@elif STM32L100xC
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@elif STM32L151xC
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@elif STM32L152xC
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@elif STM32L162xC
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@else
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@endif
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
* @retval none
*/
@ -308,8 +360,8 @@ typedef struct
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
/* FLASH IRQ handler function */
void HAL_FLASH_IRQHandler(void);
@ -353,7 +405,6 @@ uint32_t HAL_FLASH_GetError(void);
/** @addtogroup FLASH_Private_Functions
* @{
*/
void FLASH_PageErase(uint32_t PageAddress);
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/**

255
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_flash_ex.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Extended FLASH HAL module driver.
*
* This file provides firmware functions to manage the following
@ -116,6 +116,7 @@ extern FLASH_ProcessTypeDef pFlash;
/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
* @{
*/
void FLASH_PageErase(uint32_t PageAddress);
static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, FunctionalState NewState);
static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalState NewState);
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
@ -133,22 +134,18 @@ static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState
|| defined(STM32L152xDX) || defined(STM32L162xDX)
static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState);
#endif /* STM32L151xE || STM32L152xE || STM32L151xDX || ... */
#if defined(FLASH_OBR_SPRMOD)
static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit, FunctionalState NewState);
#endif /* FLASH_OBR_SPRMOD */
#if defined(FLASH_OBR_nRST_BFB2)
static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT);
#endif /* FLASH_OBR_nRST_BFB2 */
static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP);
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR);
static uint8_t FLASH_OB_GetRDP(void);
static uint8_t FLASH_OB_GetUser(void);
static uint8_t FLASH_OB_GetBOR(void);
#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
|| defined(STM32L162xC)
static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit, FunctionalState NewState);
#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
|| defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
|| defined(STM32L162xE)
static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT);
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint8_t Data);
static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);
static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint32_t Data);
@ -214,12 +211,12 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
__HAL_LOCK(&pFlash);
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if (status == HAL_OK)
{
/*Initialization of PageError variable*/
*PageError = 0xFFFFFFFF;
*PageError = 0xFFFFFFFFU;
/* Check the parameters */
assert_param(IS_NBPAGES(pEraseInit->NbPages));
@ -265,7 +262,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
FLASH_PageErase(address);
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* If the erase operation is completed, disable the ERASE Bit */
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
@ -273,7 +270,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
if (status != HAL_OK)
{
/* In case of error, stop erase procedure and return the faulty address */
/* In case of error, stop erase procedure and return the faulty address */
*PageError = address;
break;
}
@ -292,6 +289,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
* must be called before.
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation)
* End of erase is done when @ref HAL_FLASH_EndOfOperationCallback is called with parameter
* 0xFFFFFFFF
* @note For STM32L151xDX/STM32L152xDX/STM32L162xDX, as memory is not continuous between
* 2 banks, user should perform pages erase by bank only.
* @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
@ -479,7 +478,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
__HAL_UNLOCK(&pFlash);
return status;
}
}
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
@ -535,13 +534,9 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
/*Get BOR Level*/
pOBInit->BORLevel = FLASH_OB_GetBOR();
}
#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
|| defined(STM32L162xC) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) \
|| defined(STM32L152xDX) || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) \
|| defined(STM32L152xE) || defined(STM32L162xE)
#if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2)
/**
* @brief Program option bytes
@ -558,11 +553,9 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO
/* Check the parameters */
assert_param(IS_OBEX(pAdvOBInit->OptionType));
#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
|| defined(STM32L162xC)
#if defined(FLASH_OBR_SPRMOD)
/* Cat2 & Cat3 devices only */
/*Program PCROP option byte*/
/* Program PCROP option byte*/
if ((pAdvOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP)
{
/* Check the parameters */
@ -578,7 +571,7 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO
}
else
{
/*Disable of Write protection on the selected Sector*/
/* Disable of Write protection on the selected Sector*/
status = FLASH_OB_PCROPConfig(pAdvOBInit, DISABLE);
if (status != HAL_OK)
{
@ -587,26 +580,23 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO
}
}
#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
#endif /* FLASH_OBR_SPRMOD */
#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
|| defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
|| defined(STM32L162xE)
#if defined(FLASH_OBR_nRST_BFB2)
/* Cat4 & Cat5 devices only */
/*Program BOOT config option byte*/
/* Program BOOT config option byte */
if ((pAdvOBInit->OptionType & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG)
{
status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig);
}
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
#endif /* FLASH_OBR_nRST_BFB2 */
return status;
}
/**
* @brief Get the OBEX byte configuration
* @brief Get the OBEX byte configuration
* @note This function can be used only for Cat2 & Cat3 devices for PCROP and Cat4 & Cat5 for BFB2.
* @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that
* contains the configuration information for the programming.
@ -615,10 +605,11 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO
*/
void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
{
#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
|| defined(STM32L162xC)
pAdvOBInit->OptionType = 0;
#if defined(FLASH_OBR_SPRMOD)
pAdvOBInit->OptionType = OPTIONBYTE_PCROP;
pAdvOBInit->OptionType |= OPTIONBYTE_PCROP;
/*Get PCROP state */
pAdvOBInit->PCROPState = (FLASH->OBR & FLASH_OBR_SPRMOD) >> POSITION_VAL(FLASH_OBR_SPRMOD);
@ -626,31 +617,27 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
/*Get PCROP protected sector from 0 to 31 */
pAdvOBInit->PCROPSector0To31 = FLASH->WRPR1;
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)
/*Get PCROP protected sector from 32 to 63 */
pAdvOBInit->PCROPSector32To63 = FLASH->WRPR2;
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
#endif /* FLASH_OBR_SPRMOD */
#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
|| defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
|| defined(STM32L162xE)
#if defined(FLASH_OBR_nRST_BFB2)
pAdvOBInit->OptionType = OPTIONBYTE_BOOTCONFIG;
pAdvOBInit->OptionType |= OPTIONBYTE_BOOTCONFIG;
/*Get Boot config OB*/
pAdvOBInit->BootConfig = (FLASH->OBR & 0x80000000) >> 24;
/* Get Boot config OB */
pAdvOBInit->BootConfig = (FLASH->OBR & FLASH_OBR_nRST_BFB2) >> 16;
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
#endif /* FLASH_OBR_nRST_BFB2 */
}
#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */
#endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */
#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
|| defined(STM32L162xC)
#if defined(FLASH_OBR_SPRMOD)
/**
* @brief Select the Protection Mode (SPRMOD).
@ -686,11 +673,11 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
/* program PCRop */
OB->RDP = tmp2;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
}
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* Return the Read protection operation Status */
return status;
}
@ -729,16 +716,16 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
/* program PCRop */
OB->RDP = tmp2;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
}
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* Return the Read protection operation Status */
return status;
}
#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
#endif /* FLASH_OBR_SPRMOD */
/**
* @}
@ -800,9 +787,9 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void)
* @param Address specifies the address to be erased.
* @param TypeErase Indicate the way to erase at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @note To correctly run this function, the DATA_EEPROM_Unlock() function
* @note To correctly run this function, the @ref HAL_FLASHEx_DATAEEPROM_Unlock() function
* must be called before.
* Call the DATA_EEPROM_Lock() to the data EEPROM access
* Call the @ref HAL_FLASHEx_DATAEEPROM_Lock() to the data EEPROM access
* and Flash program erase control register access(recommended to protect
* the DATA_EEPROM against possible unwanted operation).
* @retval HAL_StatusTypeDef HAL Status
@ -816,7 +803,7 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Addr
assert_param(IS_FLASH_DATA_ADDRESS(Address));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
@ -840,6 +827,8 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Addr
/* Write 00h to valid address in the data memory */
*(__IO uint8_t *) Address = (uint8_t)0x00;
}
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
}
/* Return the erase status */
@ -848,12 +837,12 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Addr
/**
* @brief Program word at a specified address
* @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function
* @note To correctly run this function, the @ref HAL_FLASHEx_DATAEEPROM_Unlock() function
* must be called before.
* Call the HAL_FLASHEx_DATAEEPROM_Unlock() to he data EEPROM access
* Call the @ref HAL_FLASHEx_DATAEEPROM_Unlock() to he data EEPROM access
* and Flash program erase control register access(recommended to protect
* the DATA_EEPROM against possible unwanted operation).
* @note The function HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram() can be called before
* @note The function @ref HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram() can be called before
* this function to configure the Fixed Time Programming.
* @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASHEx_Type_Program_Data
@ -874,7 +863,7 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_
assert_param(IS_TYPEPROGRAMDATA(TypeProgram));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
@ -889,31 +878,31 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_
if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTHALFWORD)
{
/*Program word (16-bit) at a specified address.*/
/* Program halfword (16-bit) at a specified address.*/
status = FLASH_DATAEEPROM_FastProgramHalfWord(Address, (uint16_t) Data);
}
if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTWORD)
{
/*Program word (32-bit) at a specified address.*/
/* Program word (32-bit) at a specified address.*/
status = FLASH_DATAEEPROM_FastProgramWord(Address, (uint32_t) Data);
}
if(TypeProgram == FLASH_TYPEPROGRAMDATA_WORD)
{
/*Program word (32-bit) at a specified address.*/
/* Program word (32-bit) at a specified address.*/
status = FLASH_DATAEEPROM_ProgramWord(Address, (uint32_t) Data);
}
if(TypeProgram == FLASH_TYPEPROGRAMDATA_HALFWORD)
{
/*Program word (16-bit) at a specified address.*/
/* Program halfword (16-bit) at a specified address.*/
status = FLASH_DATAEEPROM_ProgramHalfWord(Address, (uint16_t) Data);
}
if(TypeProgram == FLASH_TYPEPROGRAMDATA_BYTE)
{
/*Program word (8-bit) at a specified address.*/
/* Program byte (8-bit) at a specified address.*/
status = FLASH_DATAEEPROM_ProgramByte(Address, (uint8_t) Data);
}
}
@ -961,7 +950,7 @@ void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void)
*/
/**
* @brief Enables or disables the read out protection.
* @note To correctly run this function, the HAL_FLASH_OB_Unlock() function
* @note To correctly run this function, the @ref HAL_FLASH_OB_Unlock() function
* must be called before.
* @param OB_RDP specifies the read protection level.
* This parameter can be:
@ -976,16 +965,17 @@ void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void)
static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmp1 = 0, tmp2 = 0, sprmod = 0;
uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
/* Check the parameters */
assert_param(IS_OB_RDP(OB_RDP));
tmp1 = (uint32_t)(OB->RDP & FLASH_OBR_RDPRT);
/* According to errata sheet, DocID022054 Rev 5, par2.1.5
Before setting Level0 in the RDP register, check that the current level is not equal to Level0.
If the current level is not equal to Level0, Level0 can be activated.
If the current level is Level0 then the RDP register must not be written again with Level0. */
tmp1 = (uint32_t)(OB->RDP & 0x000000FF);
if ((tmp1 == OB_RDP_LEVEL_0) && (OB_RDP == OB_RDP_LEVEL_0))
{
@ -994,30 +984,33 @@ static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP)
}
else
{
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
#if defined(FLASH_OBR_SPRMOD)
/* Mask SPRMOD bit */
sprmod = (uint32_t)(OB->RDP & 0x00000100);
tmp3 = (uint32_t)(OB->RDP & FLASH_OBR_SPRMOD);
#endif
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* calculate the option byte to write */
tmp1 = (~((uint32_t)(OB_RDP | sprmod)));
tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)(OB_RDP | sprmod)));
if(status == HAL_OK)
{
/* program read protection level */
OB->RDP = tmp2;
}
tmp1 = (~((uint32_t)(OB_RDP | tmp3)));
tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)(OB_RDP | tmp3)));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* program read protection level */
OB->RDP = tmp2;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
}
}
/* Return the Read protection operation Status */
return status;
return status;
}
/**
@ -1042,8 +1035,8 @@ static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR)
assert_param(IS_OB_BOR_LEVEL(OB_BOR));
/* Get the User Option byte register */
tmp1 = (FLASH->OBR & (FLASH_OBR_USER)) >> 16;
tmp1 = OB->USER & ((~FLASH_OBR_BOR_LEV) >> 16);
/* Calculate the option byte to write - [0xFF | nUSER | 0x00 | USER]*/
tmp = (uint32_t)~((OB_BOR | tmp1)) << 16;
tmp |= (OB_BOR | tmp1);
@ -1057,13 +1050,13 @@ static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR)
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Write the BOR Option Byte */
OB->USER = tmp;
OB->USER = tmp;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
}
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* Return the Option Byte program Status */
/* Return the Option Byte BOR programmation Status */
return status;
}
@ -1074,12 +1067,12 @@ static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR)
static uint8_t FLASH_OB_GetUser(void)
{
/* Return the User Option Byte */
return (uint8_t)((FLASH->OBR & FLASH_OBR_USER) >> POSITION_VAL(FLASH_OBR_USER));
return (uint8_t)((FLASH->OBR & FLASH_OBR_USER) >> 16);
}
/**
* @brief Checks whether the FLASH Read out Protection Status is set or not.
* @retval FLASH ReadOut Protection Status:
* @brief Returns the FLASH Read Protection level.
* @retval FLASH RDP level
* This parameter can be one of the following values:
* @arg @ref OB_RDP_LEVEL_0 No protection
* @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
@ -1092,12 +1085,12 @@ static uint8_t FLASH_OB_GetRDP(void)
/**
* @brief Returns the FLASH BOR level.
* @retval The FLASH User Option Bytes.
* @retval The BOR level Option Bytes.
*/
static uint8_t FLASH_OB_GetBOR(void)
{
/* Return the BOR level */
return (uint8_t)((FLASH->OBR & (uint32_t)FLASH_OBR_BOR_LEV) >> POSITION_VAL(FLASH_OBR_BOR_LEV));
return (uint8_t)((FLASH->OBR & (uint32_t)FLASH_OBR_BOR_LEV) >> 16);
}
/**
@ -1245,6 +1238,10 @@ static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalStat
uint32_t tmp1 = 0, tmp2 = 0;
/* Check the parameters */
assert_param(IS_OB_WRP(WRP1OrPCROP1));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
wrp01data = (uint16_t)(((WRP1OrPCROP1 & WRP_MASK_LOW) | OB->WRP01));
@ -1287,6 +1284,10 @@ static void FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalStat
uint32_t tmp1 = 0, tmp2 = 0;
/* Check the parameters */
assert_param(IS_OB_WRP(WRP2OrPCROP2));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
wrp45data = (uint16_t)(((WRP2OrPCROP2 & WRP_MASK_LOW) | OB->WRP45));
@ -1329,6 +1330,10 @@ static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState)
uint32_t tmp1 = 0, tmp2 = 0;
/* Check the parameters */
assert_param(IS_OB_WRP(WRP3));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
wrp89data = (uint16_t)(((WRP3 & WRP_MASK_LOW) | OB->WRP89));
@ -1370,6 +1375,10 @@ static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState)
uint32_t tmp1 = 0, tmp2 = 0;
/* Check the parameters */
assert_param(IS_OB_WRP(WRP4));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
wrp1213data = (uint16_t)(((WRP4 & WRP_MASK_LOW) | OB->WRP1213));
@ -1421,8 +1430,8 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, u
assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
/* Get the User Option byte register */
tmp1 = (FLASH->OBR & FLASH_OBR_BOR_LEV) >> 16;
tmp1 = OB->USER & ((~FLASH_OBR_USER) >> 16);
/* Calculate the user option byte to write */
tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << 16);
tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1);
@ -1436,19 +1445,17 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, u
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Write the User Option Byte */
OB->USER = tmp;
}
/* Wait for last operation to be completed */
OB->USER = tmp;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
}
/* Return the Option Byte program Status */
return status;
}
#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
|| defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
|| defined(STM32L162xE)
#if defined(FLASH_OBR_nRST_BFB2)
/**
* @brief Configures to boot from Bank1 or Bank2.
* @param OB_BOOT select the FLASH Bank to boot from.
@ -1474,32 +1481,32 @@ static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT)
assert_param(IS_OB_BOOT_BANK(OB_BOOT));
/* Get the User Option byte register and BOR Level*/
tmp1 = (FLASH->OBR & (FLASH_OBR_nRST_STDBY | FLASH_OBR_nRST_STOP | FLASH_OBR_IWDG_SW | FLASH_OBR_BOR_LEV)) >> 16;
tmp1 = OB->USER & ((~FLASH_OBR_nRST_BFB2) >> 16);
/* Calculate the option byte to write */
tmp = (uint32_t)~(OB_BOOT | tmp1) << 16;
tmp |= (OB_BOOT | tmp1);
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Write the BOOT Option Byte */
OB->USER = tmp;
OB->USER = tmp;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
}
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* Return the Option Byte program Status */
return status;
}
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
#endif /* FLASH_OBR_nRST_BFB2 */
/*
==============================================================================
@ -1830,7 +1837,7 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t
* @brief Erases a specified page in program memory.
* @param PageAddress The page address in program memory to be erased.
* @note A Page is erased in the Program memory only if the address to load
* is the start address of a page (multiple of 256 bytes).
* is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes).
* @retval None
*/
void FLASH_PageErase(uint32_t PageAddress)

366
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_flash.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of Flash HAL module.
******************************************************************************
* @attention
@ -54,7 +54,7 @@
* @{
*/
/** @addtogroup FLASHEx_Private_Defines
/** @addtogroup FLASHEx_Private_Constants
* @{
*/
#if defined(FLASH_SR_RDERR) && defined(FLASH_SR_OPTVERRUSR)
@ -107,15 +107,8 @@
#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */
/** @defgroup FLASHEx_Option_Bytes_Write_Mask FLASHEx Option Bytes Write Mask
* @{
*/
#define WRP_MASK_LOW ((uint32_t)0x0000FFFF)
#define WRP_MASK_HIGH ((uint32_t)0xFFFF0000)
/**
* @}
*/
#define WRP_MASK_LOW ((uint32_t)0x0000FFFFU)
#define WRP_MASK_HIGH ((uint32_t)0xFFFF0000U)
/**
* @}
@ -132,6 +125,8 @@
#define IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || \
((__VALUE__) == OB_WRPSTATE_ENABLE))
#define IS_OB_WRP(__PAGE__) (((__PAGE__) != 0x0000000U))
#define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\
((__LEVEL__) == OB_RDP_LEVEL_1) ||\
((__LEVEL__) == OB_RDP_LEVEL_2))
@ -149,33 +144,38 @@
#define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST))
#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
|| defined(STM32L162xC)
#if defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2)
#define IS_OBEX(__VALUE__) (((__VALUE__) == OPTIONBYTE_PCROP) || ((__VALUE__) == OPTIONBYTE_BOOTCONFIG))
#elif defined(FLASH_OBR_SPRMOD) && !defined(FLASH_OBR_nRST_BFB2)
#define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_PCROP)
#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
|| defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
|| defined(STM32L162xE)
#elif !defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2)
#define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_BOOTCONFIG)
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
#endif /* FLASH_OBR_SPRMOD && FLASH_OBR_nRST_BFB2 */
#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
|| defined(STM32L162xC)
#if defined(FLASH_OBR_SPRMOD)
#define IS_PCROPSTATE(__VALUE__) (((__VALUE__) == OB_PCROP_STATE_DISABLE) || \
((__VALUE__) == OB_PCROP_STATE_ENABLE))
#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
#define IS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000U))
#endif /* FLASH_OBR_SPRMOD */
#if defined(FLASH_OBR_nRST_BFB2)
#define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1))
#endif /* FLASH_OBR_nRST_BFB2 */
#define IS_TYPEERASEDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEERASEDATA_BYTE) || \
((__VALUE__) == FLASH_TYPEERASEDATA_HALFWORD) || \
((__VALUE__) == FLASH_TYPEERASEDATA_WORD))
#define IS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \
((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \
((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD) || \
@ -183,7 +183,6 @@
((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTHALFWORD) || \
((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTWORD))
/** @defgroup FLASHEx_Address FLASHEx Address
* @{
*/
@ -205,15 +204,8 @@
#endif /* STM32L100xB || STM32L151xB || STM32L152xB || (...) || STM32L151xCA || STM32L152xCA || STM32L162xCA */
#define IS_NBPAGES(_PAGES_) (((_PAGES_) >= 1) && ((_PAGES_) <= FLASH_NBPAGES_MAX))
#define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1) && ((__PAGES__) <= FLASH_NBPAGES_MAX))
#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
|| defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
|| defined(STM32L162xE)
#define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1))
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
/**
* @}
*/
@ -223,7 +215,7 @@
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Types Exported Types
/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
* @{
*/
@ -279,7 +271,7 @@ typedef struct
This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4 */
#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */
uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.
This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
uint8_t BORLevel; /*!< BORLevel: Set the BOR Level.
@ -290,6 +282,7 @@ typedef struct
@ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/
} FLASH_OBProgramInitTypeDef;
#if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2)
/**
* @brief FLASH Advanced Option Bytes Program structure definition
*/
@ -298,8 +291,7 @@ typedef struct
uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension .
This parameter can be a value of @ref FLASHEx_OptionAdv_Type */
#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
|| defined(STM32L162xC)
#if defined(FLASH_OBR_SPRMOD)
uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation.
This parameter can be a value of @ref FLASHEx_PCROP_State */
@ -310,31 +302,30 @@ typedef struct
uint32_t PCROPSector32To63; /*!< PCROPSector32To63: specifies the sector(s) set for PCROP
This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */
#endif /* STM32L151xC || STM32L152xC || STM32L162xC */
#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
#endif /* FLASH_OBR_SPRMOD */
#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \
|| defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \
|| defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
#if defined(FLASH_OBR_nRST_BFB2)
uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config
This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || (...) || STM32L151xE || STM32L152xE || STM32L162xE*/
#endif /* FLASH_OBR_nRST_BFB2*/
} FLASH_AdvOBProgramInitTypeDef;
/**
* @}
*/
#endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Constants Exported Constants
/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
* @{
*/
/** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase
* @{
*/
#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Page erase only*/
#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00U) /*!<Page erase only*/
/**
* @}
@ -343,10 +334,10 @@ typedef struct
/** @defgroup FLASHEx_Option_Type FLASHEx Option Type
* @{
*/
#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!<WRP option byte configuration*/
#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!<RDP option byte configuration*/
#define OPTIONBYTE_USER ((uint32_t)0x04) /*!<USER option byte configuration*/
#define OPTIONBYTE_BOR ((uint32_t)0x08) /*!<BOR option byte configuration*/
#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!<WRP option byte configuration*/
#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!<RDP option byte configuration*/
#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!<USER option byte configuration*/
#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!<BOR option byte configuration*/
/**
* @}
@ -355,8 +346,8 @@ typedef struct
/** @defgroup FLASHEx_WRP_State FLASHEx WRP State
* @{
*/
#define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!<Disable the write protection of the desired bank 1 sectors*/
#define OB_WRPSTATE_ENABLE ((uint32_t)0x01) /*!<Enable the write protection of the desired bank 1 sectors*/
#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!<Disable the write protection of the desired sectors*/
#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!<Enable the write protection of the desired sectors*/
/**
* @}
@ -398,7 +389,7 @@ typedef struct
#define OB_WRP1_PAGES448TO463 ((uint32_t)0x10000000) /* Write protection of Sector28 */
#define OB_WRP1_PAGES464TO479 ((uint32_t)0x20000000) /* Write protection of Sector29 */
#define OB_WRP1_PAGES480TO495 ((uint32_t)0x40000000) /* Write protection of Sector30 */
#define OB_WRP1_PAGES496TO511 ((uint32_t)0x80000000) /* Write protection of Sector31 */
#define OB_WRP1_PAGES496TO511 ((uint32_t)0x80000000U) /* Write protection of Sector31 */
#define OB_WRP1_ALLPAGES ((uint32_t)FLASH_WRPR1_WRP) /*!< Write protection of all Sectors */
@ -453,7 +444,7 @@ typedef struct
#define OB_WRP2_PAGES960TO975 ((uint32_t)0x10000000) /* Write protection of Sector60 */
#define OB_WRP2_PAGES976TO991 ((uint32_t)0x20000000) /* Write protection of Sector61 */
#define OB_WRP2_PAGES992TO1007 ((uint32_t)0x40000000) /* Write protection of Sector62 */
#define OB_WRP2_PAGES1008TO1023 ((uint32_t)0x80000000) /* Write protection of Sector63 */
#define OB_WRP2_PAGES1008TO1023 ((uint32_t)0x80000000U) /* Write protection of Sector63 */
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
@ -505,7 +496,7 @@ typedef struct
#define OB_WRP3_PAGES1472TO1487 ((uint32_t)0x10000000) /* Write protection of Sector92 */
#define OB_WRP3_PAGES1488TO1503 ((uint32_t)0x20000000) /* Write protection of Sector93 */
#define OB_WRP3_PAGES1504TO1519 ((uint32_t)0x40000000) /* Write protection of Sector94 */
#define OB_WRP3_PAGES1520TO1535 ((uint32_t)0x80000000) /* Write protection of Sector95 */
#define OB_WRP3_PAGES1520TO1535 ((uint32_t)0x80000000U) /* Write protection of Sector95 */
#define OB_WRP3_ALLPAGES ((uint32_t)FLASH_WRPR3_WRP) /*!< Write protection of all Sectors */
@ -557,7 +548,7 @@ typedef struct
#define OB_WRP4_PAGES1984TO1999 ((uint32_t)0x10000000) /* Write protection of Sector124*/
#define OB_WRP4_PAGES2000TO2015 ((uint32_t)0x20000000) /* Write protection of Sector125*/
#define OB_WRP4_PAGES2016TO2031 ((uint32_t)0x40000000) /* Write protection of Sector126*/
#define OB_WRP4_PAGES2032TO2047 ((uint32_t)0x80000000) /* Write protection of Sector127*/
#define OB_WRP4_PAGES2032TO2047 ((uint32_t)0x80000000U) /* Write protection of Sector127*/
#endif /* STM32L151xE || STM32L152xE || STM32L162xE */
@ -572,10 +563,10 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection
* @{
*/
#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
#define OB_RDP_LEVEL_1 ((uint8_t)0xBB)
#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /* Warning: When enabling read protection level 2
it's no more possible to go back to level 1 or 0 */
#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
#define OB_RDP_LEVEL_1 ((uint8_t)0xBBU)
#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /* Warning: When enabling read protection level 2
it is no more possible to go back to level 1 or 0 */
/**
* @}
@ -585,13 +576,13 @@ typedef struct
* @{
*/
#define OB_BOR_OFF ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD
#define OB_BOR_OFF ((uint8_t)0x00U) /*!< BOR is disabled at power down, the reset is asserted when the VDD
power supply reaches the PDR(Power Down Reset) threshold (1.5V) */
#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */
#define OB_BOR_LEVEL2 ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */
#define OB_BOR_LEVEL3 ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */
#define OB_BOR_LEVEL4 ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */
#define OB_BOR_LEVEL5 ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */
#define OB_BOR_LEVEL1 ((uint8_t)0x08U) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */
#define OB_BOR_LEVEL2 ((uint8_t)0x09U) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */
#define OB_BOR_LEVEL3 ((uint8_t)0x0AU) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */
#define OB_BOR_LEVEL4 ((uint8_t)0x0BU) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */
#define OB_BOR_LEVEL5 ((uint8_t)0x0CU) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */
/**
* @}
@ -601,8 +592,8 @@ typedef struct
* @{
*/
#define OB_IWDG_SW ((uint8_t)0x10) /*!< Software WDG selected */
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */
#define OB_IWDG_SW ((uint8_t)0x10U) /*!< Software WDG selected */
#define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware WDG selected */
/**
* @}
@ -612,8 +603,8 @@ typedef struct
* @{
*/
#define OB_STOP_NORST ((uint8_t)0x20) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
#define OB_STOP_NORST ((uint8_t)0x20U) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
/**
* @}
*/
@ -622,52 +613,48 @@ typedef struct
* @{
*/
#define OB_STDBY_NORST ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
#define OB_STDBY_NORST ((uint8_t)0x40U) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
/**
* @}
*/
#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
|| defined(STM32L162xC)
#if defined(FLASH_OBR_SPRMOD)
/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
* @{
*/
#define OPTIONBYTE_PCROP ((uint32_t)0x01) /*!<PCROP option byte configuration*/
#define OPTIONBYTE_PCROP ((uint32_t)0x01U) /*!<PCROP option byte configuration*/
/**
* @}
*/
#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
#endif /* FLASH_OBR_SPRMOD */
#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
|| defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
|| defined(STM32L162xE)
#if defined(FLASH_OBR_nRST_BFB2)
/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
* @{
*/
#define OPTIONBYTE_BOOTCONFIG ((uint32_t)0x02) /*!<BOOTConfig option byte configuration*/
#define OPTIONBYTE_BOOTCONFIG ((uint32_t)0x02U) /*!<BOOTConfig option byte configuration*/
/**
* @}
*/
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
#endif /* FLASH_OBR_nRST_BFB2 */
#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
|| defined(STM32L162xC)
#if defined(FLASH_OBR_SPRMOD)
/** @defgroup FLASHEx_PCROP_State FLASHEx PCROP State
* @{
*/
#define OB_PCROP_STATE_DISABLE ((uint32_t)0x00) /*!<Disable PCROP for selected sectors */
#define OB_PCROP_STATE_ENABLE ((uint32_t)0x01) /*!<Enable PCROP for selected sectors */
#define OB_PCROP_STATE_DISABLE ((uint32_t)0x00U) /*!<Disable PCROP for selected sectors */
#define OB_PCROP_STATE_ENABLE ((uint32_t)0x01U) /*!<Enable PCROP for selected sectors */
/**
* @}
@ -676,57 +663,59 @@ typedef struct
/** @defgroup FLASHEx_Selection_Protection_Mode FLASHEx Selection Protection Mode
* @{
*/
#define OB_PCROP_DESELECTED ((uint16_t)0x0000) /*!< Disabled PCROP, nWPRi bits used for Write Protection on sector i */
#define OB_PCROP_DESELECTED ((uint16_t)0x0000U) /*!< Disabled PCROP, nWPRi bits used for Write Protection on sector i */
#define OB_PCROP_SELECTED ((uint16_t)FLASH_OBR_SPRMOD) /*!< Enable PCROP, nWPRi bits used for PCRoP Protection on sector i */
/**
* @}
*/
#endif /* FLASH_OBR_SPRMOD */
#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
|| defined(STM32L162xC)
/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 FLASHEx Option Bytes PC ReadWrite Protection 1
* @{
*/
/* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */
#define OB_PCROP1_PAGES0TO15 ((uint32_t)0x00000001) /* PC Read/Write protection of Sector0 */
#define OB_PCROP1_PAGES16TO31 ((uint32_t)0x00000002) /* PC Read/Write protection of Sector1 */
#define OB_PCROP1_PAGES32TO47 ((uint32_t)0x00000004) /* PC Read/Write protection of Sector2 */
#define OB_PCROP1_PAGES48TO63 ((uint32_t)0x00000008) /* PC Read/Write protection of Sector3 */
#define OB_PCROP1_PAGES64TO79 ((uint32_t)0x00000010) /* PC Read/Write protection of Sector4 */
#define OB_PCROP1_PAGES80TO95 ((uint32_t)0x00000020) /* PC Read/Write protection of Sector5 */
#define OB_PCROP1_PAGES96TO111 ((uint32_t)0x00000040) /* PC Read/Write protection of Sector6 */
#define OB_PCROP1_PAGES112TO127 ((uint32_t)0x00000080) /* PC Read/Write protection of Sector7 */
#define OB_PCROP1_PAGES128TO143 ((uint32_t)0x00000100) /* PC Read/Write protection of Sector8 */
#define OB_PCROP1_PAGES144TO159 ((uint32_t)0x00000200) /* PC Read/Write protection of Sector9 */
#define OB_PCROP1_PAGES160TO175 ((uint32_t)0x00000400) /* PC Read/Write protection of Sector10 */
#define OB_PCROP1_PAGES176TO191 ((uint32_t)0x00000800) /* PC Read/Write protection of Sector11 */
#define OB_PCROP1_PAGES192TO207 ((uint32_t)0x00001000) /* PC Read/Write protection of Sector12 */
#define OB_PCROP1_PAGES208TO223 ((uint32_t)0x00002000) /* PC Read/Write protection of Sector13 */
#define OB_PCROP1_PAGES224TO239 ((uint32_t)0x00004000) /* PC Read/Write protection of Sector14 */
#define OB_PCROP1_PAGES240TO255 ((uint32_t)0x00008000) /* PC Read/Write protection of Sector15 */
#define OB_PCROP1_PAGES256TO271 ((uint32_t)0x00010000) /* PC Read/Write protection of Sector16 */
#define OB_PCROP1_PAGES272TO287 ((uint32_t)0x00020000) /* PC Read/Write protection of Sector17 */
#define OB_PCROP1_PAGES288TO303 ((uint32_t)0x00040000) /* PC Read/Write protection of Sector18 */
#define OB_PCROP1_PAGES304TO319 ((uint32_t)0x00080000) /* PC Read/Write protection of Sector19 */
#define OB_PCROP1_PAGES320TO335 ((uint32_t)0x00100000) /* PC Read/Write protection of Sector20 */
#define OB_PCROP1_PAGES336TO351 ((uint32_t)0x00200000) /* PC Read/Write protection of Sector21 */
#define OB_PCROP1_PAGES352TO367 ((uint32_t)0x00400000) /* PC Read/Write protection of Sector22 */
#define OB_PCROP1_PAGES368TO383 ((uint32_t)0x00800000) /* PC Read/Write protection of Sector23 */
#define OB_PCROP1_PAGES384TO399 ((uint32_t)0x01000000) /* PC Read/Write protection of Sector24 */
#define OB_PCROP1_PAGES400TO415 ((uint32_t)0x02000000) /* PC Read/Write protection of Sector25 */
#define OB_PCROP1_PAGES416TO431 ((uint32_t)0x04000000) /* PC Read/Write protection of Sector26 */
#define OB_PCROP1_PAGES432TO447 ((uint32_t)0x08000000) /* PC Read/Write protection of Sector27 */
#define OB_PCROP1_PAGES448TO463 ((uint32_t)0x10000000) /* PC Read/Write protection of Sector28 */
#define OB_PCROP1_PAGES464TO479 ((uint32_t)0x20000000) /* PC Read/Write protection of Sector29 */
#define OB_PCROP1_PAGES480TO495 ((uint32_t)0x40000000) /* PC Read/Write protection of Sector30 */
#define OB_PCROP1_PAGES496TO511 ((uint32_t)0x80000000) /* PC Read/Write protection of Sector31 */
#define OB_PCROP1_PAGES0TO15 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector0 */
#define OB_PCROP1_PAGES16TO31 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector1 */
#define OB_PCROP1_PAGES32TO47 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector2 */
#define OB_PCROP1_PAGES48TO63 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector3 */
#define OB_PCROP1_PAGES64TO79 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector4 */
#define OB_PCROP1_PAGES80TO95 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector5 */
#define OB_PCROP1_PAGES96TO111 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector6 */
#define OB_PCROP1_PAGES112TO127 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector7 */
#define OB_PCROP1_PAGES128TO143 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector8 */
#define OB_PCROP1_PAGES144TO159 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector9 */
#define OB_PCROP1_PAGES160TO175 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector10 */
#define OB_PCROP1_PAGES176TO191 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector11 */
#define OB_PCROP1_PAGES192TO207 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector12 */
#define OB_PCROP1_PAGES208TO223 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector13 */
#define OB_PCROP1_PAGES224TO239 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector14 */
#define OB_PCROP1_PAGES240TO255 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector15 */
#define OB_PCROP1_PAGES256TO271 ((uint32_t)0x00010000U) /* PC Read/Write protection of Sector16 */
#define OB_PCROP1_PAGES272TO287 ((uint32_t)0x00020000U) /* PC Read/Write protection of Sector17 */
#define OB_PCROP1_PAGES288TO303 ((uint32_t)0x00040000U) /* PC Read/Write protection of Sector18 */
#define OB_PCROP1_PAGES304TO319 ((uint32_t)0x00080000U) /* PC Read/Write protection of Sector19 */
#define OB_PCROP1_PAGES320TO335 ((uint32_t)0x00100000U) /* PC Read/Write protection of Sector20 */
#define OB_PCROP1_PAGES336TO351 ((uint32_t)0x00200000U) /* PC Read/Write protection of Sector21 */
#define OB_PCROP1_PAGES352TO367 ((uint32_t)0x00400000U) /* PC Read/Write protection of Sector22 */
#define OB_PCROP1_PAGES368TO383 ((uint32_t)0x00800000U) /* PC Read/Write protection of Sector23 */
#define OB_PCROP1_PAGES384TO399 ((uint32_t)0x01000000U) /* PC Read/Write protection of Sector24 */
#define OB_PCROP1_PAGES400TO415 ((uint32_t)0x02000000U) /* PC Read/Write protection of Sector25 */
#define OB_PCROP1_PAGES416TO431 ((uint32_t)0x04000000U) /* PC Read/Write protection of Sector26 */
#define OB_PCROP1_PAGES432TO447 ((uint32_t)0x08000000U) /* PC Read/Write protection of Sector27 */
#define OB_PCROP1_PAGES448TO463 ((uint32_t)0x10000000U) /* PC Read/Write protection of Sector28 */
#define OB_PCROP1_PAGES464TO479 ((uint32_t)0x20000000U) /* PC Read/Write protection of Sector29 */
#define OB_PCROP1_PAGES480TO495 ((uint32_t)0x40000000U) /* PC Read/Write protection of Sector30 */
#define OB_PCROP1_PAGES496TO511 ((uint32_t)0x80000000U) /* PC Read/Write protection of Sector31 */
#define OB_PCROP1_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< PC Read/Write protection of all Sectors */
#define OB_PCROP1_ALLPAGES ((uint32_t)0xFFFFFFFFU) /*!< PC Read/Write protection of all Sectors */
/**
* @}
*/
#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)
@ -736,53 +725,52 @@ typedef struct
*/
/* Pages for Cat3, Cat4 & Cat5 devices*/
#define OB_PCROP2_PAGES512TO527 ((uint32_t)0x00000001) /* PC Read/Write protection of Sector32 */
#define OB_PCROP2_PAGES528TO543 ((uint32_t)0x00000002) /* PC Read/Write protection of Sector33 */
#define OB_PCROP2_PAGES544TO559 ((uint32_t)0x00000004) /* PC Read/Write protection of Sector34 */
#define OB_PCROP2_PAGES560TO575 ((uint32_t)0x00000008) /* PC Read/Write protection of Sector35 */
#define OB_PCROP2_PAGES576TO591 ((uint32_t)0x00000010) /* PC Read/Write protection of Sector36 */
#define OB_PCROP2_PAGES592TO607 ((uint32_t)0x00000020) /* PC Read/Write protection of Sector37 */
#define OB_PCROP2_PAGES608TO623 ((uint32_t)0x00000040) /* PC Read/Write protection of Sector38 */
#define OB_PCROP2_PAGES624TO639 ((uint32_t)0x00000080) /* PC Read/Write protection of Sector39 */
#define OB_PCROP2_PAGES640TO655 ((uint32_t)0x00000100) /* PC Read/Write protection of Sector40 */
#define OB_PCROP2_PAGES656TO671 ((uint32_t)0x00000200) /* PC Read/Write protection of Sector41 */
#define OB_PCROP2_PAGES672TO687 ((uint32_t)0x00000400) /* PC Read/Write protection of Sector42 */
#define OB_PCROP2_PAGES688TO703 ((uint32_t)0x00000800) /* PC Read/Write protection of Sector43 */
#define OB_PCROP2_PAGES704TO719 ((uint32_t)0x00001000) /* PC Read/Write protection of Sector44 */
#define OB_PCROP2_PAGES720TO735 ((uint32_t)0x00002000) /* PC Read/Write protection of Sector45 */
#define OB_PCROP2_PAGES736TO751 ((uint32_t)0x00004000) /* PC Read/Write protection of Sector46 */
#define OB_PCROP2_PAGES752TO767 ((uint32_t)0x00008000) /* PC Read/Write protection of Sector47 */
#define OB_PCROP2_PAGES768TO783 ((uint32_t)0x00010000) /* PC Read/Write protection of Sector48 */
#define OB_PCROP2_PAGES784TO799 ((uint32_t)0x00020000) /* PC Read/Write protection of Sector49 */
#define OB_PCROP2_PAGES800TO815 ((uint32_t)0x00040000) /* PC Read/Write protection of Sector50 */
#define OB_PCROP2_PAGES816TO831 ((uint32_t)0x00080000) /* PC Read/Write protection of Sector51 */
#define OB_PCROP2_PAGES832TO847 ((uint32_t)0x00100000) /* PC Read/Write protection of Sector52 */
#define OB_PCROP2_PAGES848TO863 ((uint32_t)0x00200000) /* PC Read/Write protection of Sector53 */
#define OB_PCROP2_PAGES864TO879 ((uint32_t)0x00400000) /* PC Read/Write protection of Sector54 */
#define OB_PCROP2_PAGES880TO895 ((uint32_t)0x00800000) /* PC Read/Write protection of Sector55 */
#define OB_PCROP2_PAGES896TO911 ((uint32_t)0x01000000) /* PC Read/Write protection of Sector56 */
#define OB_PCROP2_PAGES912TO927 ((uint32_t)0x02000000) /* PC Read/Write protection of Sector57 */
#define OB_PCROP2_PAGES928TO943 ((uint32_t)0x04000000) /* PC Read/Write protection of Sector58 */
#define OB_PCROP2_PAGES944TO959 ((uint32_t)0x08000000) /* PC Read/Write protection of Sector59 */
#define OB_PCROP2_PAGES960TO975 ((uint32_t)0x10000000) /* PC Read/Write protection of Sector60 */
#define OB_PCROP2_PAGES976TO991 ((uint32_t)0x20000000) /* PC Read/Write protection of Sector61 */
#define OB_PCROP2_PAGES992TO1007 ((uint32_t)0x40000000) /* PC Read/Write protection of Sector62 */
#define OB_PCROP2_PAGES1008TO1023 ((uint32_t)0x80000000) /* PC Read/Write protection of Sector63 */
#define OB_PCROP2_PAGES512TO527 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector32 */
#define OB_PCROP2_PAGES528TO543 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector33 */
#define OB_PCROP2_PAGES544TO559 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector34 */
#define OB_PCROP2_PAGES560TO575 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector35 */
#define OB_PCROP2_PAGES576TO591 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector36 */
#define OB_PCROP2_PAGES592TO607 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector37 */
#define OB_PCROP2_PAGES608TO623 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector38 */
#define OB_PCROP2_PAGES624TO639 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector39 */
#define OB_PCROP2_PAGES640TO655 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector40 */
#define OB_PCROP2_PAGES656TO671 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector41 */
#define OB_PCROP2_PAGES672TO687 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector42 */
#define OB_PCROP2_PAGES688TO703 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector43 */
#define OB_PCROP2_PAGES704TO719 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector44 */
#define OB_PCROP2_PAGES720TO735 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector45 */
#define OB_PCROP2_PAGES736TO751 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector46 */
#define OB_PCROP2_PAGES752TO767 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector47 */
#define OB_PCROP2_PAGES768TO783 ((uint32_t)0x00010000U) /* PC Read/Write protection of Sector48 */
#define OB_PCROP2_PAGES784TO799 ((uint32_t)0x00020000U) /* PC Read/Write protection of Sector49 */
#define OB_PCROP2_PAGES800TO815 ((uint32_t)0x00040000U) /* PC Read/Write protection of Sector50 */
#define OB_PCROP2_PAGES816TO831 ((uint32_t)0x00080000U) /* PC Read/Write protection of Sector51 */
#define OB_PCROP2_PAGES832TO847 ((uint32_t)0x00100000U) /* PC Read/Write protection of Sector52 */
#define OB_PCROP2_PAGES848TO863 ((uint32_t)0x00200000U) /* PC Read/Write protection of Sector53 */
#define OB_PCROP2_PAGES864TO879 ((uint32_t)0x00400000U) /* PC Read/Write protection of Sector54 */
#define OB_PCROP2_PAGES880TO895 ((uint32_t)0x00800000U) /* PC Read/Write protection of Sector55 */
#define OB_PCROP2_PAGES896TO911 ((uint32_t)0x01000000U) /* PC Read/Write protection of Sector56 */
#define OB_PCROP2_PAGES912TO927 ((uint32_t)0x02000000U) /* PC Read/Write protection of Sector57 */
#define OB_PCROP2_PAGES928TO943 ((uint32_t)0x04000000U) /* PC Read/Write protection of Sector58 */
#define OB_PCROP2_PAGES944TO959 ((uint32_t)0x08000000U) /* PC Read/Write protection of Sector59 */
#define OB_PCROP2_PAGES960TO975 ((uint32_t)0x10000000U) /* PC Read/Write protection of Sector60 */
#define OB_PCROP2_PAGES976TO991 ((uint32_t)0x20000000U) /* PC Read/Write protection of Sector61 */
#define OB_PCROP2_PAGES992TO1007 ((uint32_t)0x40000000U) /* PC Read/Write protection of Sector62 */
#define OB_PCROP2_PAGES1008TO1023 ((uint32_t)0x80000000U) /* PC Read/Write protection of Sector63 */
#define OB_PCROP2_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< PC Read/Write protection of all Sectors */
#define OB_PCROP2_ALLPAGES ((uint32_t)0xFFFFFFFFU) /*!< PC Read/Write protection of all Sectors */
/**
* @}
*/
#endif /* STM32L151xC || STM32L152xC || STM32L162xC */
/** @defgroup FLASHEx_Type_Erase_Data FLASHEx Type Erase Data
* @{
*/
#define FLASH_TYPEERASEDATA_BYTE ((uint32_t)0x00) /*!<Erase byte (8-bit) at a specified address.*/
#define FLASH_TYPEERASEDATA_HALFWORD ((uint32_t)0x01) /*!<Erase a half-word (16-bit) at a specified address.*/
#define FLASH_TYPEERASEDATA_WORD ((uint32_t)0x02) /*!<Erase a word (32-bit) at a specified address.*/
#define FLASH_TYPEERASEDATA_BYTE ((uint32_t)0x00U) /*!<Erase byte (8-bit) at a specified address.*/
#define FLASH_TYPEERASEDATA_HALFWORD ((uint32_t)0x01U) /*!<Erase a half-word (16-bit) at a specified address.*/
#define FLASH_TYPEERASEDATA_WORD ((uint32_t)0x02U) /*!<Erase a word (32-bit) at a specified address.*/
/**
* @}
@ -791,48 +779,24 @@ typedef struct
/** @defgroup FLASHEx_Type_Program_Data FLASHEx Type Program Data
* @{
*/
#define FLASH_TYPEPROGRAMDATA_BYTE ((uint32_t)0x00) /*!<Program byte (8-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_HALFWORD ((uint32_t)0x01) /*!<Program a half-word (16-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_WORD ((uint32_t)0x02) /*!<Program a word (32-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_FASTBYTE ((uint32_t)0x04) /*!<Fast Program byte (8-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_FASTHALFWORD ((uint32_t)0x08) /*!<Fast Program a half-word (16-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_FASTWORD ((uint32_t)0x10) /*!<Fast Program a word (32-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_BYTE ((uint32_t)0x00U) /*!<Program byte (8-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_HALFWORD ((uint32_t)0x01U) /*!<Program a half-word (16-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_WORD ((uint32_t)0x02U) /*!<Program a word (32-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_FASTBYTE ((uint32_t)0x04U) /*!<Fast Program byte (8-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_FASTHALFWORD ((uint32_t)0x08U) /*!<Fast Program a half-word (16-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_FASTWORD ((uint32_t)0x10U) /*!<Fast Program a word (32-bit) at a specified address.*/
/**
* @}
*/
/** @defgroup FLASHEx_Flags FLASHEx Flags
* @{
*/
/* Cat2 & Cat3*/
#if defined(FLASH_SR_RDERR)
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< Read protected error flag */
#endif /* FLASH_SR_RDERR */
/* Cat3, Cat4 & Cat5*/
#if defined(FLASH_SR_OPTVERRUSR)
#define FLASH_FLAG_OPTVERRUSR FLASH_SR_OPTVERRUSR /*!< FLASH Option User Validity error flag */
#endif /* FLASH_SR_OPTVERRUSR */
/**
* @}
*/
#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
|| defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
|| defined(STM32L162xE)
#if defined(FLASH_OBR_nRST_BFB2)
/** @defgroup FLASHEx_Option_Bytes_BOOT FLASHEx Option Bytes BOOT
* @{
*/
#define OB_BOOT_BANK2 ((uint8_t)0x00) /*!< At startup, if boot pins are set in boot from user Flash position
#define OB_BOOT_BANK2 ((uint8_t)0x00U) /*!< At startup, if boot pins are set in boot from user Flash position
and this parameter is selected the device will boot from Bank 2
or Bank 1, depending on the activation of the bank */
#define OB_BOOT_BANK1 ((uint8_t)(FLASH_OBR_nRST_BFB2 >> 16)) /*!< At startup, if boot pins are set in boot from user Flash position
@ -841,7 +805,7 @@ typedef struct
/**
* @}
*/
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
#endif /* FLASH_OBR_nRST_BFB2 */
/**
* @}
@ -849,7 +813,7 @@ typedef struct
/* Exported macro ------------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Macros Exported Macros
/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
* @{
*/
@ -875,7 +839,7 @@ typedef struct
*/
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
/**
/**
* @brief Enable the FLASH 64-bit access.
* @note Read access 64 bit is used.
* @note This bit cannot be written at the same time as the LATENCY and
@ -893,7 +857,7 @@ typedef struct
*/
#define __HAL_FLASH_ACC64_DISABLE() (CLEAR_BIT((FLASH->ACR), FLASH_ACR_ACC64))
/**
/**
* @brief Enable the FLASH prefetch buffer.
* @retval none
*/
@ -920,16 +884,20 @@ typedef struct
#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
/**
* @brief Macro to enable or disable the Flash Run power down mode.
* @brief Enable the Flash Run power down mode.
* @note Writing this bit to 0 this bit, automatically the keys are
* loss and a new unlock sequence is necessary to re-write it to 1.
*/
#define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \
FLASH->PDKEYR = FLASH_PDKEY2; \
SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
} while (0)
/**
* @brief Disable the Flash Run power down mode.
* @note Writing this bit to 0 this bit, automatically the keys are
* loss and a new unlock sequence is necessary to re-write it to 1.
*/
#define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \
FLASH->PDKEYR = FLASH_PDKEY2; \
CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
@ -963,23 +931,19 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
|| defined(STM32L162xC) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) \
|| defined(STM32L152xDX) || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) \
|| defined(STM32L152xE) || defined(STM32L162xE)
#if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2)
HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */
#endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */
#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
|| defined(STM32L162xC)
#if defined(FLASH_OBR_SPRMOD)
HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
#endif /* FLASH_OBR_SPRMOD */
/**
* @}

349
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ramfunc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_flash_ramfunc.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief FLASH RAMFUNC driver.
* This file provides a Flash firmware functions which should be
* executed from internal SRAM
@ -68,6 +68,21 @@
#ifdef HAL_FLASH_MODULE_ENABLED
/** @addtogroup FLASH
* @{
*/
/** @addtogroup FLASH_Private_Variables
* @{
*/
extern FLASH_ProcessTypeDef pFlash;
/**
* @}
*/
/**
* @}
*/
/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
* @brief FLASH functions executed from RAM
* @{
@ -79,11 +94,12 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup FLASH_RAMFUNC_Private_Functions Private Functions
/** @defgroup FLASH_RAMFUNC_Private_Functions FLASH RAM Private Functions
* @{
*/
static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout);
static __RAM_FUNC FLASHRAM_SetErrorCode(void);
/**
* @}
@ -91,7 +107,7 @@ static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout);
/* Private functions ---------------------------------------------------------*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions Exported Functions
/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAM Exported Functions
*
@verbatim
===============================================================================
@ -112,21 +128,20 @@ static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout);
/**
* @brief Enable the power down mode during RUN mode.
* @note This function can be used only when the user code is running from Internal SRAM.
* @retval None
* @retval HAL status
*/
__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void)
{
/* Enable the Power Down in Run mode*/
__HAL_FLASH_POWER_DOWN_ENABLE();
return HAL_OK;
}
/**
* @brief Disable the power down mode during RUN mode.
* @note This function can be used only when the user code is running from Internal SRAM.
* @retval None
* @retval HAL status
*/
__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)
{
@ -149,11 +164,11 @@ __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)
#if defined(FLASH_PECR_PARALLBANK)
/**
* @brief Erases a specified 2 page in program memory in parallel.
* @brief Erases a specified 2 pages in program memory in parallel.
* @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices.
* To correctly run this function, the HAL_FLASH_Unlock() function
* To correctly run this function, the @ref HAL_FLASH_Unlock() function
* must be called before.
* Call the HAL_FLASH_Lock() to disable the flash memory access
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation).
* @param Page_Address1: The page address in program memory to be erased in
* the first Bank (BANK1). This parameter should be between FLASH_BASE
@ -162,9 +177,8 @@ __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)
* the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE
* and FLASH_BANK2_END.
* @note A Page is erased in the Program memory only if the address to load
* is the start address of a page (multiple of 256 bytes).
* @retval HAL Status: The returned value can be:
* HAL_ERROR, HAL_OK or HAL_TIMEOUT.
* is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes).
* @retval HAL status
*/
__RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)
{
@ -175,16 +189,10 @@ __RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_A
if(status == HAL_OK)
{
/* If the previous operation is completed, proceed to erase the page */
/* Set the PARALLBANK bit */
FLASH->PECR |= FLASH_PECR_PARALLBANK;
/* Set the ERASE bit */
FLASH->PECR |= FLASH_PECR_ERASE;
/* Set PROG bit */
FLASH->PECR |= FLASH_PECR_PROG;
/* Proceed to erase the page */
SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);
SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
/* Write 00000000h to the first word of the first program page to erase */
*(__IO uint32_t *)Page_Address1 = 0x00000000;
@ -195,16 +203,16 @@ __RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_A
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */
FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);
FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
}
/* Return the Erase Status */
return status;
}
/**
* @brief Programs 2 half page in program memory in parallel.
* @brief Program 2 half pages in program memory in parallel (half page size is 32 Words).
* @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices.
* @param Address1: specifies the first address to be written in the first bank
* (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE).
@ -214,9 +222,9 @@ __RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_A
* (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE).
* @param pBuffer2: pointer to the buffer containing the data to be written
* to the second half page in the second bank.
* @note To correctly run this function, the HAL_FLASH_Unlock() function
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
* must be called before.
* Call the HAL_FLASH_Lock() to disable the flash memory access
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation).
* @note Half page write is possible only from SRAM.
* @note If there are more than 32 words to write, after 32 words another
@ -231,59 +239,66 @@ __RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_A
* complete write operation is aborted. Software should then reset the
* FPRG and PROG/DATA bits and restart the write operation from the
* beginning.
* @retval HAL Status: The returned value can be:
* HAL_ERROR, HAL_OK or HAL_TIMEOUT.
* @retval HAL status
*/
__RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)
{
uint32_t count = 0;
HAL_StatusTypeDef status = HAL_OK;
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
This bit prevents the interruption of multicycle instructions and therefore
will increase the interrupt latency. of Cortex-M3. */
SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* If the previous operation is completed, proceed to program the new
half page */
FLASH->PECR |= FLASH_PECR_PARALLBANK;
FLASH->PECR |= FLASH_PECR_FPRG;
FLASH->PECR |= FLASH_PECR_PROG;
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Write the first half page directly with 32 different words */
while(count < 32)
{
*(__IO uint32_t*) ((uint32_t)(Address1 + (4 * count))) = *(pBuffer1++);
count ++;
}
count = 0;
/* Proceed to program the new half page */
SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
/* Write the second half page directly with 32 different words */
while(count < 32)
{
*(__IO uint32_t*) ((uint32_t)(Address2 + (4 * count))) = *(pBuffer2++);
count ++;
}
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
}
if(status == HAL_OK)
{
/* Disable all IRQs */
__disable_irq();
/* Write the first half page directly with 32 different words */
while(count < 32)
{
*(__IO uint32_t*) ((uint32_t)(Address1 + (4 * count))) = *pBuffer1;
pBuffer1++;
count ++;
}
/* Write the second half page directly with 32 different words */
count = 0;
while(count < 32)
{
*(__IO uint32_t*) ((uint32_t)(Address2 + (4 * count))) = *pBuffer2;
pBuffer2++;
count ++;
}
/* Enable IRQs */
__enable_irq();
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
}
/* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */
FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
}
SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
CLEAR_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
/* Return the Write Status */
return status;
@ -291,13 +306,13 @@ __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuf
#endif /* FLASH_PECR_PARALLBANK */
/**
* @brief Programs a half page in program memory.
* @brief Program a half page in program memory.
* @param Address: specifies the address to be written.
* @param pBuffer: pointer to the buffer containing the data to be written to
* the half page.
* @note To correctly run this function, the HAL_FLASH_Unlock() function
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
* must be called before.
* Call the HAL_FLASH_Lock() to disable the flash memory access
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation)
* @note Half page write is possible only from SRAM.
* @note If there are more than 32 words to write, after 32 words another
@ -312,45 +327,50 @@ __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuf
* complete write operation is aborted. Software should then reset the
* FPRG and PROG/DATA bits and restart the write operation from the
* beginning.
* @retval HAL Status: The returned value can be:
* HAL_ERROR, HAL_OK or HAL_TIMEOUT.
* @retval HAL status
*/
__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer)
{
uint32_t count = 0;
HAL_StatusTypeDef status = HAL_OK;
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
This bit prevents the interruption of multicycle instructions and therefore
will increase the interrupt latency. of Cortex-M3. */
SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* if the previous operation is completed, proceed to program the new
half page */
FLASH->PECR |= FLASH_PECR_FPRG;
FLASH->PECR |= FLASH_PECR_PROG;
/* Proceed to program the new half page */
SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
/* Disable all IRQs */
__disable_irq();
/* Write one half page directly with 32 different words */
while(count < 32)
{
*(__IO uint32_t*) ((uint32_t)(Address + (4 * count))) = *(pBuffer++);
*(__IO uint32_t*) ((uint32_t)(Address + (4 * count))) = *pBuffer;
pBuffer++;
count ++;
}
/* Enable IRQs */
__enable_irq();
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* if the write operation is completed, disable the PROG and FPRG bits */
FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
/* If the write operation is completed, disable the PROG and FPRG bits */
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
}
SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
CLEAR_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
/* Return the Write Status */
return status;
@ -360,7 +380,63 @@ __RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer)
* @}
*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group3 DATA EEPROM functions
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group3 Peripheral errors functions
* @brief Peripheral errors functions
*
@verbatim
===============================================================================
##### Peripheral errors functions #####
===============================================================================
[..]
This subsection permit to get in run-time errors of the FLASH peripheral.
@endverbatim
* @{
*/
/**
* @brief Get the specific FLASH errors flag.
* @param Error pointer is the error value. It can be a mixed of:
@if STM32L100xB
@elif STM32L100xBA
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
@elif STM32L151xB
@elif STM32L151xBA
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
@elif STM32L152xB
@elif STM32L152xBA
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
@elif STM32L100xC
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
* @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
@elif STM32L151xC
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
* @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
@elif STM32L152xC
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
* @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
@elif STM32L162xC
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
* @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
@else
* @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
@endif
* @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming Alignment error flag
* @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protected error flag
* @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option valid error flag
* @retval HAL Status
*/
__RAM_FUNC HAL_FLASHEx_GetError(uint32_t * Error)
{
*Error = pFlash.ErrorCode;
return HAL_OK;
}
/**
* @}
*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group4 DATA EEPROM functions
*
* @{
*/
@ -379,8 +455,7 @@ __RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer)
* @note During the Data memory double word erase, all read operations are
* forbidden (this includes DMA read operations and debugger read
* operations such as breakpoints, periodic updates, etc.).
* @retval HAL Status: The returned value can be:
* HAL_ERROR, HAL_OK or HAL_TIMEOUT.
* @retval HAL status
*/
__RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address)
@ -390,7 +465,7 @@ __RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address)
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
This bit prevents the interruption of multicycle instructions and therefore
will increase the interrupt latency. of Cortex-M3. */
SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
@ -399,10 +474,10 @@ __RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address)
{
/* If the previous operation is completed, proceed to erase the next double word */
/* Set the ERASE bit */
FLASH->PECR |= FLASH_PECR_ERASE;
SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);
/* Set DATA bit */
FLASH->PECR |= FLASH_PECR_DATA;
SET_BIT(FLASH->PECR, FLASH_PECR_DATA);
/* Write 00000000h to the 2 words to erase */
*(__IO uint32_t *)Address = 0x00000000;
@ -413,11 +488,11 @@ __RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address)
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* If the erase operation is completed, disable the ERASE and DATA bits */
FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);
FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA);
}
SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
CLEAR_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
/* Return the erase status */
return status;
@ -439,8 +514,7 @@ __RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address)
* @note During the Data memory double word write, all read operations are
* forbidden (this includes DMA read operations and debugger read
* operations such as breakpoints, periodic updates, etc.).
* @retval HAL Status: The returned value can be:
* HAL_ERROR, HAL_OK or HAL_TIMEOUT.
* @retval HAL status
*/
__RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data)
{
@ -449,7 +523,7 @@ __RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t D
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
This bit prevents the interruption of multicycle instructions and therefore
will increase the interrupt latency. of Cortex-M3. */
SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
@ -457,8 +531,8 @@ __RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t D
if(status == HAL_OK)
{
/* If the previous operation is completed, proceed to program the new data*/
FLASH->PECR |= FLASH_PECR_FPRG;
FLASH->PECR |= FLASH_PECR_DATA;
SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
SET_BIT(FLASH->PECR, FLASH_PECR_DATA);
/* Write the 2 words */
*(__IO uint32_t *)Address = (uint32_t) Data;
@ -469,11 +543,11 @@ __RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t D
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* If the write operation is completed, disable the FPRG and DATA bits */
FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA);
}
SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
CLEAR_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
/* Return the Write Status */
return status;
@ -491,12 +565,57 @@ __RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t D
* @{
*/
/**
* @brief Set the specific FLASH error flag.
* @retval HAL Status
*/
static __RAM_FUNC FLASHRAM_SetErrorCode(void)
{
uint32_t flags = 0;
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
flags |= FLASH_FLAG_WRPERR;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
flags |= FLASH_FLAG_PGAERR;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
flags |= FLASH_FLAG_OPTVERR;
}
#if defined(FLASH_SR_RDERR)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
flags |= FLASH_FLAG_RDERR;
}
#endif /* FLASH_SR_RDERR */
#if defined(FLASH_SR_OPTVERRUSR)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTVUSR;
flags |= FLASH_FLAG_OPTVERRUSR;
}
#endif /* FLASH_SR_OPTVERRUSR */
/* Clear FLASH error pending bits */
__HAL_FLASH_CLEAR_FLAG(flags);
return HAL_OK;
}
/**
* @brief Wait for a FLASH operation to complete.
* @param Timeout: maximum flash operationtimeout
* @retval HAL status
*/
static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout)
static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout)
{
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
@ -512,32 +631,32 @@ static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout)
return HAL_TIMEOUT;
}
/* Check FLASH End of Operation flag */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
}
/* Check FLASH End of Operation flag */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
}
if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) ||
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) ||
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) ||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
#if defined(FLASH_SR_RDERR)
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) ||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) ||
#endif /* FLASH_SR_RDERR */
#if defined(FLASH_SR_OPTVERRUSR)
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) ||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) ||
#endif /* FLASH_SR_OPTVERRUSR */
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) )
{
return HAL_ERROR;
}
/* If there is an error flag set */
return HAL_OK;
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
{
/*Save the error code*/
FLASHRAM_SetErrorCode();
return HAL_ERROR;
}
/* There is no error flag set */
return HAL_OK;
}
/**
* @}
*/

12
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ramfunc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_flash_ramfunc.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention
@ -100,6 +100,14 @@ __RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer);
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group3
* @{
*/
__RAM_FUNC HAL_FLASHEx_GetError(uint32_t *Error);
/**
* @}
*/
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group4
* @{
*/
__RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address);
__RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data);

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_gpio.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:

7
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_gpio.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
@ -201,7 +201,8 @@ typedef enum
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK) != (uint32_t)0x00)
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\
(((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00))
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
((PULL) == GPIO_PULLDOWN))

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_gpio_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention

3363
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2c.c
View File

File diff suppressed because it is too large Load Diff

261
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2c.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_i2c.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
@ -97,17 +97,46 @@ typedef struct
/** @defgroup HAL_state_structure_definition HAL state structure definition
* @brief HAL State structure definition
* @note HAL I2C State value coding follow below described bitmap :
* b7-b6 Error information
* 00 : No Error
* 01 : Abort (Abort user request on going)
* 10 : Timeout
* 11 : Error
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)
* b4 (not used)
* x : Should be set to 0
* b3
* 0 : Ready or Busy (No Listen mode ongoing)
* 1 : Listen (IP in Address Listen Mode)
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (IP busy with some configuration or internal operations)
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* @{
*/
typedef enum
{
HAL_I2C_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
HAL_I2C_STATE_READY = 0x20, /*!< Peripheral Initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x24, /*!< An internal process is ongoing */
HAL_I2C_STATE_BUSY_TX = 0x21, /*!< Data Transmission process is ongoing */
HAL_I2C_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
HAL_I2C_STATE_TIMEOUT = 0xA0, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0 /*!< Error */
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
process is ongoing */
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
}HAL_I2C_StateTypeDef;
@ -117,14 +146,28 @@ typedef enum
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
* @brief HAL Mode structure definition
* @note HAL I2C Mode value coding follow below described bitmap :
* b7 (not used)
* x : Should be set to 0
* b6
* 0 : None
* 1 : Memory (HAL I2C communication is in Memory Mode)
* b5
* 0 : None
* 1 : Slave (HAL I2C communication is in Slave Mode)
* b4
* 0 : None
* 1 : Master (HAL I2C communication is in Master Mode)
* b3-b2-b1-b0 (not used)
* xxxx : Should be set to 0000
* @{
*/
typedef enum
{
HAL_I2C_MODE_NONE = 0x00, /*!< No I2C communication on going */
HAL_I2C_MODE_MASTER = 0x10, /*!< I2C communication is in Master Mode */
HAL_I2C_MODE_SLAVE = 0x20, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40 /*!< I2C communication is in Memory Mode */
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
}HAL_I2C_ModeTypeDef;
@ -136,13 +179,13 @@ typedef enum
* @brief I2C Error Code definition
* @{
*/
#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */
#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */
#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004) /*!< AF error */
#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */
#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001U) /*!< BERR error */
#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002U) /*!< ARLO error */
#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004U) /*!< AF error */
#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008U) /*!< OVR error */
#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout Error */
/**
* @}
*/
@ -153,29 +196,43 @@ typedef enum
*/
typedef struct
{
I2C_TypeDef *Instance; /*!< I2C registers base address */
I2C_TypeDef *Instance; /*!< I2C registers base address */
I2C_InitTypeDef Init; /*!< I2C communication parameters */
I2C_InitTypeDef Init; /*!< I2C communication parameters */
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
uint16_t XferSize; /*!< I2C transfer size */
uint16_t XferSize; /*!< I2C transfer size */
__IO uint16_t XferCount; /*!< I2C transfer counter */
__IO uint16_t XferCount; /*!< I2C transfer counter */
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
__IO uint32_t XferOptions; /*!< I2C transfer options */
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
__IO uint32_t PreviousState; /*!< I2C communication Previous state and mode
context for internal usage */
HAL_LockTypeDef Lock; /*!< I2C locking object */
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t Devaddress; /*!< I2C Target device address */
__IO uint32_t Memaddress; /*!< I2C Target memory address */
__IO uint32_t MemaddSize; /*!< I2C Target memory address size */
__IO uint32_t EventCount; /*!< I2C Event counter */
}I2C_HandleTypeDef;
/**
* @}
*/
@ -188,12 +245,20 @@ typedef struct
* @{
*/
/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
* @{
*/
#define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000U)
#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
/**
* @}
*/
/** @defgroup I2C_addressing_mode I2C addressing mode
* @{
*/
#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000)
#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000))
#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000U)
#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000U))
/**
* @}
*/
@ -201,9 +266,8 @@ typedef struct
/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
* @{
*/
#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U)
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
/**
* @}
*/
@ -211,8 +275,8 @@ typedef struct
/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
* @{
*/
#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000)
#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U)
#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
/**
* @}
*/
@ -220,8 +284,8 @@ typedef struct
/** @defgroup I2C_nostretch_mode I2C nostretch mode
* @{
*/
#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U)
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
@ -229,18 +293,28 @@ typedef struct
/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
* @{
*/
#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010)
#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U)
#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010U)
/**
* @}
*/
/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
/** @defgroup I2C_XferDirection_definition I2C XferDirection definition Master Point of View
* @{
*/
#define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000)
#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
#define I2C_DIRECTION_RECEIVE ((uint32_t)0x00000000U)
#define I2C_DIRECTION_TRANSMIT ((uint32_t)0x00000001U)
/**
* @}
*/
/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
* @{
*/
#define I2C_FIRST_FRAME ((uint32_t)0x00000001U)
#define I2C_NEXT_FRAME ((uint32_t)0x00000002U)
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)0x00000004U)
#define I2C_LAST_FRAME ((uint32_t)0x00000008U)
/**
* @}
*/
@ -261,26 +335,22 @@ typedef struct
/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
#define I2C_FLAG_OVR ((uint32_t)(1 << 16 | I2C_SR1_OVR))
#define I2C_FLAG_AF ((uint32_t)(1 << 16 | I2C_SR1_AF))
#define I2C_FLAG_ARLO ((uint32_t)(1 << 16 | I2C_SR1_ARLO))
#define I2C_FLAG_BERR ((uint32_t)(1 << 16 | I2C_SR1_BERR))
#define I2C_FLAG_TXE ((uint32_t)(1 << 16 | I2C_SR1_TXE))
#define I2C_FLAG_RXNE ((uint32_t)(1 << 16 | I2C_SR1_RXNE))
#define I2C_FLAG_STOPF ((uint32_t)(1 << 16 | I2C_SR1_STOPF))
#define I2C_FLAG_ADD10 ((uint32_t)(1 << 16 | I2C_SR1_ADD10))
#define I2C_FLAG_BTF ((uint32_t)(1 << 16 | I2C_SR1_BTF))
#define I2C_FLAG_ADDR ((uint32_t)(1 << 16 | I2C_SR1_ADDR))
#define I2C_FLAG_SB ((uint32_t)(1 << 16 | I2C_SR1_SB))
#define I2C_FLAG_DUALF ((uint32_t)(2 << 16 | I2C_SR2_DUALF))
#define I2C_FLAG_GENCALL ((uint32_t)(2 << 16 | I2C_SR2_GENCALL))
#define I2C_FLAG_TRA ((uint32_t)(2 << 16 | I2C_SR2_TRA))
#define I2C_FLAG_BUSY ((uint32_t)(2 << 16 | I2C_SR2_BUSY))
#define I2C_FLAG_MSL ((uint32_t)(2 << 16 | I2C_SR2_MSL))
#define I2C_FLAG_MASK ((uint32_t)0x0000FFFF)
#define I2C_FLAG_OVR ((uint32_t)(1U << 16U | I2C_SR1_OVR))
#define I2C_FLAG_AF ((uint32_t)(1U << 16U | I2C_SR1_AF))
#define I2C_FLAG_ARLO ((uint32_t)(1U << 16U | I2C_SR1_ARLO))
#define I2C_FLAG_BERR ((uint32_t)(1U << 16U | I2C_SR1_BERR))
#define I2C_FLAG_TXE ((uint32_t)(1U << 16U | I2C_SR1_TXE))
#define I2C_FLAG_RXNE ((uint32_t)(1U << 16U | I2C_SR1_RXNE))
#define I2C_FLAG_STOPF ((uint32_t)(1U << 16U | I2C_SR1_STOPF))
#define I2C_FLAG_ADD10 ((uint32_t)(1U << 16U | I2C_SR1_ADD10))
#define I2C_FLAG_BTF ((uint32_t)(1U << 16U | I2C_SR1_BTF))
#define I2C_FLAG_ADDR ((uint32_t)(1U << 16U | I2C_SR1_ADDR))
#define I2C_FLAG_SB ((uint32_t)(1U << 16U | I2C_SR1_SB))
#define I2C_FLAG_DUALF ((uint32_t)(2U << 16U | I2C_SR2_DUALF))
#define I2C_FLAG_GENCALL ((uint32_t)(2U << 16U | I2C_SR2_GENCALL))
#define I2C_FLAG_TRA ((uint32_t)(2U << 16U | I2C_SR2_TRA))
#define I2C_FLAG_BUSY ((uint32_t)(2U << 16U | I2C_SR2_BUSY))
#define I2C_FLAG_MSL ((uint32_t)(2U << 16U | I2C_SR2_MSL))
/**
* @}
*/
@ -309,8 +379,8 @@ typedef struct
* @arg I2C_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))
/** @brief Disable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__: specifies the interrupt source to disable.
@ -357,8 +427,8 @@ typedef struct
* @arg I2C_FLAG_MSL: Master/Slave flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16)) == 0x01)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?(((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET): \
(((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET))
/** @brief Clear the I2C pending flags which are cleared by writing 0 in a specific bit.
* @param __HANDLE__ specifies the I2C Handle.
@ -374,12 +444,11 @@ typedef struct
/** @brief Clears the I2C ADDR pending flag.
* @param __HANDLE__: specifies the I2C Handle.
* This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
* @retval None
*/
#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg; \
__IO uint32_t tmpreg = 0x00U; \
tmpreg = (__HANDLE__)->Instance->SR1; \
tmpreg = (__HANDLE__)->Instance->SR2; \
UNUSED(tmpreg); \
@ -387,12 +456,11 @@ typedef struct
/** @brief Clears the I2C STOPF pending flag.
* @param __HANDLE__: specifies the I2C Handle.
* This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
* @retval None
*/
#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg; \
__IO uint32_t tmpreg = 0x00U; \
tmpreg = (__HANDLE__)->Instance->SR1; \
SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE); \
UNUSED(tmpreg); \
@ -455,6 +523,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
@ -476,10 +552,12 @@ void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
@ -503,7 +581,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{
*/
#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU)
/**
* @}
*/
@ -522,8 +600,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
((CYCLE) == I2C_DUTYCYCLE_16_9))
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0)
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (0xFFFFFF01U)) == 0U)
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (0xFFFFFC00U)) == 0U)
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
((CALL) == I2C_GENERALCALL_ENABLE))
@ -533,27 +611,32 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000))
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U))
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_FREQ_RANGE(__PCLK__) ((__PCLK__)/1000000)
#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1))
#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1)))
#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9))
#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \
#define I2C_FREQ_RANGE(__PCLK__) ((__PCLK__)/1000000U)
#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))
#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0xF0U))))
#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0xF1U))))
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME))
/**
* @}
*/

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2s.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_i2s.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2s.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_i2s.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_irda.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_irda.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA SIR ENDEC block (IrDA):

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_irda.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_irda.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief This file contains all the functions prototypes for the IRDA
* firmware library.
******************************************************************************

306
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_iwdg.c
View File

@ -2,38 +2,43 @@
******************************************************************************
* @file stm32l1xx_hal_iwdg.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief IWDG HAL module driver.
*
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
* + Initialization and de-initialization functions
* + Initialization and Start functions
* + IO operation functions
* + Peripheral State functions
*
@verbatim
*
@verbatim
==============================================================================
##### IWDG Generic features #####
==============================================================================
[..]
[..]
(+) The IWDG can be started by either software or hardware (configurable
through option byte).
through option byte).
(+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and
thus stays active even if the main clock fails.
Once the IWDG is started, the LSI is forced ON and cannot be disabled
(LSI cannot be disabled too), and the counter starts counting down from
the reset value of 0xFFF. When it reaches the end of count value (0x000)
a system reset is generated.
(+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
if the main clock fails.
(+) The IWDG counter should be refreshed at regular intervals, otherwise the
watchdog generates an MCU reset when the counter reaches 0.
(+) Once the IWDG is started, the LSI is forced ON and both can not be
disabled. The counter starts counting down from the reset value (0xFFF).
When it reaches the end of count value (0x000) a reset signal is
generated (IWDG reset).
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
the IWDG_RLR value is reloaded in the counter and the watchdog reset is
prevented.
(+) The IWDG is implemented in the VDD voltage domain that is still functional
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
reset occurs.
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
reset occurs.
(+) Debug mode : When the microcontroller enters debug mode (core halted),
the IWDG counter either continues to work normally or stops, depending
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
(+) Min-max timeout value @37KHz (LSI): ~108us / ~28.3s
The IWDG timeout may vary due to LSI frequency dispersion. STM32L1xx
@ -44,31 +49,28 @@
##### How to use this driver #####
==============================================================================
[..]
(+) Use IWDG using HAL_IWDG_Init() function to :
(++) Enable write access to IWDG_PR, IWDG_RLR.
(++) Configure the IWDG prescaler, counter reload value.
This reload value will be loaded in the IWDG counter each time the counter
is reloaded, then the IWDG will start counting down from this value.
(+) Use IWDG using HAL_IWDG_Start() function to :
(++) Reload IWDG counter with value defined in the IWDG_RLR register.
(++) Start the IWDG, when the IWDG is used in software mode (no need
to enable the LSI, it will be enabled by hardware).
(+) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_IWDG_Refresh() function.
[..]
(#) Use IWDG using HAL_IWDG_Init() function to :
(++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
clock is forced ON and IWDG counter starts downcounting.
(++) Enable write access to configuration register: IWDG_PR, IWDG_RLR.
(++) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
(++) wait for status flags to be reset"
(#) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_IWDG_Refresh() function.
*** IWDG HAL driver macros list ***
====================================
[..]
Below the list of most used macros in IWDG HAL driver.
Below the list of most used macros in IWDG HAL driver:
(+) __HAL_IWDG_START: Enable the IWDG peripheral
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register
(+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
(+) IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers
(+) IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
the reload register
@endverbatim
******************************************************************************
* @attention
@ -98,7 +100,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal.h"
@ -107,21 +109,21 @@
* @{
*/
/** @defgroup IWDG IWDG
#ifdef HAL_IWDG_MODULE_ENABLED
/** @addtogroup IWDG
* @brief IWDG HAL module driver.
* @{
*/
#ifdef HAL_IWDG_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
higher prescaler (256), and according to HSI variation, we need to wait at
least 6 cycles so 48 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 48u
/**
* @}
*/
@ -131,36 +133,39 @@
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
/** @addtogroup IWDG_Exported_Functions
* @{
*/
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
/** @addtogroup IWDG_Exported_Functions_Group1
* @brief Initialization and Start functions.
*
@verbatim
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
##### Initialization and Start functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the IWDG according to the specified parameters
in the IWDG_InitTypeDef and create the associated handle
(+) Initialize the IWDG MSP
(+) DeInitialize IWDG MSP
[..] This section provides functions allowing to:
(+) Initialize the IWDG according to the specified parameters in the
IWDG_InitTypeDef of associated handle.
(+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
is reloaded in order to exit function with correct time base.
@endverbatim
* @{
*/
/**
* @brief Initializes the IWDG according to the specified
* parameters in the IWDG_InitTypeDef and creates the associated handle.
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
* @brief Initialize the IWDG according to the specified parameters in the
* IWDG_InitTypeDef and start watchdog. Before exiting function,
* watchdog is refreshed in order to have correct time base.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
{
uint32_t tickstart;
/* Check the IWDG handle allocation */
if(hiwdg == NULL)
{
@ -171,181 +176,72 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
/* Check pending flag, if previous update not done, return error */
if((__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET)
&&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET))
{
return HAL_ERROR;
}
if(hiwdg->State == HAL_IWDG_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hiwdg->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_IWDG_MspInit(hiwdg);
}
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_BUSY;
/* Enable write access to IWDG_PR and IWDG_RLR registers */
/* Enable IWDG. LSI is turned on automaticaly */
__HAL_IWDG_START(hiwdg);
/* Enable write access to IWDG_PR, IWDG_RLR registers by writing
0x5555 in KR */
IWDG_ENABLE_WRITE_ACCESS(hiwdg);
/* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler);
MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload);
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_READY;
/* Write to IWDG registers the Prescaler & Reload values to work with */
hiwdg->Instance->PR = hiwdg->Init.Prescaler;
hiwdg->Instance->RLR = hiwdg->Init.Reload;
/* Check pending flag, if previous update not done, return timeout */
tickstart = HAL_GetTick();
/* Wait for register to be updated */
while(hiwdg->Instance->SR != RESET)
{
if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
{
return HAL_TIMEOUT;
}
}
/* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the IWDG MSP.
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval None
*/
__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hiwdg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IWDG_MspInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
/** @addtogroup IWDG_Exported_Functions_Group2
* @brief IO operation functions
*
@verbatim
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Start the IWDG.
===============================================================================
[..] This section provides functions allowing to:
(+) Refresh the IWDG.
@endverbatim
* @{
*/
/**
* @brief Starts the IWDG.
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
{
/* Process locked */
__HAL_LOCK(hiwdg);
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_BUSY;
/* Start the IWDG peripheral */
__HAL_IWDG_START(hiwdg);
/* Reload IWDG counter with value defined in the RLR register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hiwdg);
/* Return function status */
return HAL_OK;
}
/**
* @brief Refreshes the IWDG.
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
* @brief Refresh the IWDG.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
{
uint32_t tickstart = 0;
/* Process Locked */
__HAL_LOCK(hiwdg);
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_BUSY;
tickstart = HAL_GetTick();
/* Wait until RVU flag is RESET */
while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
{
if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
{
/* Set IWDG state */
hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
/* Process unlocked */
__HAL_UNLOCK(hiwdg);
return HAL_TIMEOUT;
}
}
/* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hiwdg);
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
* @{
*/
/**
* @brief Returns the IWDG state.
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL state
*/
HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
{
return hiwdg->State;
}
/**
* @}
*/

174
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_iwdg.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_iwdg.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_HAL_IWDG_H
@ -50,9 +50,9 @@
* @{
*/
/** @addtogroup IWDG
/** @defgroup IWDG IWDG
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup IWDG_Exported_Types IWDG Exported Types
@ -60,44 +60,27 @@
*/
/**
* @brief IWDG HAL State Structure definition
*/
typedef enum
{
HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */
HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */
HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */
HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */
}HAL_IWDG_StateTypeDef;
/**
* @brief IWDG Init structure definition
*/
* @brief IWDG Init structure definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
This parameter can be a value of @ref IWDG_Prescaler */
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
}IWDG_InitTypeDef;
/**
* @brief IWDG Handle Structure definition
*/
*/
typedef struct
{
IWDG_TypeDef *Instance; /*!< Register base address */
IWDG_TypeDef *Instance; /*!< Register base address */
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
HAL_LockTypeDef Lock; /*!< IWDG Locking object */
__IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
}IWDG_HandleTypeDef;
/**
@ -111,17 +94,17 @@ typedef struct
/** @defgroup IWDG_Prescaler IWDG Prescaler
* @{
*/
#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */
#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */
#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */
#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */
#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */
#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */
*/
#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
/**
* @}
*/
*/
/**
* @}
@ -132,139 +115,107 @@ typedef struct
* @{
*/
/** @brief Reset IWDG handle state
* @param __HANDLE__: IWDG handle.
* @retval None
*/
#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
/**
* @brief Enables the IWDG peripheral.
* @param __HANDLE__: IWDG handle
* @brief Enable the IWDG peripheral.
* @param __HANDLE__ IWDG handle
* @retval None
*/
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
/**
* @brief Reloads IWDG counter with value defined in the reload register
* (write access to IWDG_PR and IWDG_RLR registers disabled).
* @param __HANDLE__: IWDG handle
* @brief Reload IWDG counter with value defined in the reload register
* (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
* @param __HANDLE__ IWDG handle
* @retval None
*/
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
/**
* @brief Gets the selected IWDG's flag status.
* @param __HANDLE__: IWDG handle
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
* @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/**
* @}
*/
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup IWDG_Exported_Functions
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
* @{
*/
/** @addtogroup IWDG_Exported_Functions_Group1
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
/* Initialization/Start functions ********************************************/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
/** @addtogroup IWDG_Exported_Functions_Group2
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
* @{
*/
/* I/O operation functions ****************************************************/
HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
/** @addtogroup IWDG_Exported_Functions_Group3
* @{
*/
/* Peripheral State functions ************************************************/
HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
/**
* @}
*/
*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup IWDG_Private_Defines
/** @defgroup IWDG_Private_Constants IWDG Private Constants
* @{
*/
/**
* @brief IWDG Key Register BitMask
*/
#define IWDG_KEY_RELOAD ((uint32_t)0x0000AAAA) /*!< IWDG Reload Counter Enable */
#define IWDG_KEY_ENABLE ((uint32_t)0x0000CCCC) /*!< IWDG Peripheral Enable */
#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x00005555) /*!< IWDG KR Write Access Enable */
#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x00000000) /*!< IWDG KR Write Access Disable */
/**
* @brief IWDG Flag definition
*/
#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update flag */
#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update flag */
#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Macro IWDG Private Macros
/** @defgroup IWDG_Private_Macros IWDG Private Macros
* @{
*/
/**
* @brief Enables write access to IWDG_PR and IWDG_RLR registers.
* @param __HANDLE__: IWDG handle
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
* @param __HANDLE__ IWDG handle
* @retval None
*/
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
/**
* @brief Disables write access to IWDG_PR and IWDG_RLR registers.
* @param __HANDLE__: IWDG handle
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
* @param __HANDLE__ IWDG handle
* @retval None
*/
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
/**
* @brief Check IWDG prescaler value.
* @param __PRESCALER__: IWDG prescaler value
* @param __PRESCALER__ IWDG prescaler value
* @retval None
*/
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
((__PRESCALER__) == IWDG_PRESCALER_8) || \
((__PRESCALER__) == IWDG_PRESCALER_16) || \
((__PRESCALER__) == IWDG_PRESCALER_32) || \
((__PRESCALER__) == IWDG_PRESCALER_64) || \
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
((__PRESCALER__) == IWDG_PRESCALER_256))
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
((__PRESCALER__) == IWDG_PRESCALER_8) || \
((__PRESCALER__) == IWDG_PRESCALER_16) || \
((__PRESCALER__) == IWDG_PRESCALER_32) || \
((__PRESCALER__) == IWDG_PRESCALER_64) || \
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
((__PRESCALER__) == IWDG_PRESCALER_256))
/**
* @brief Check IWDG reload value.
* @param __RELOAD__: IWDG reload value
* @param __RELOAD__ IWDG reload value
* @retval None
*/
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
/**
* @}
@ -272,12 +223,13 @@ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
*/
/**
* @}
*/
*/
#ifdef __cplusplus
}
#endif

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_lcd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_lcd.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief LCD Controller HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the LCD Controller (LCD) peripheral:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_lcd.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_lcd.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of LCD Controller HAL module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_nor.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_nor.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_nor.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_nor.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_opamp.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief OPAMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc)

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_opamp.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of OPAMP HAL module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_opamp_ex.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Extended OPAMP HAL module driver.
*
* This file provides firmware functions to manage the following

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_opamp_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of OPAMP HAL Extension module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_pcd.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_pcd.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention

6
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_pcd_ex.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Extended PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -128,7 +128,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
ep->doublebuffer = 1;
/*Configure the PMA*/
ep->pmaaddr0 = pmaadress & 0xFFFF;
ep->pmaaddr1 = (pmaadress & 0xFFFF0000) >> 16;
ep->pmaaddr1 = (pmaadress & 0xFFFF0000U) >> 16;
}
return HAL_OK;

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_pcd_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_pwr.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief PWR HAL module driver.
*
* This file provides firmware functions to manage the following

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_pwr.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention

7
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_pwr_ex.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@ -151,11 +151,12 @@ void HAL_PWREx_EnableLowPowerRunMode(void)
* @brief Exits the Low Power Run mode.
* @retval None
*/
void HAL_PWREx_DisableLowPowerRunMode(void)
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
{
/* Exits the Low Power Run mode */
*(__IO uint32_t *) CR_LPRUN_BB = (uint32_t)DISABLE;
*(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)DISABLE;
return HAL_OK;
}
/**

6
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_pwr_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
@ -108,7 +108,7 @@ void HAL_PWREx_DisableFastWakeUp(void);
void HAL_PWREx_EnableUltraLowPower(void);
void HAL_PWREx_DisableUltraLowPower(void);
void HAL_PWREx_EnableLowPowerRunMode(void);
void HAL_PWREx_DisableLowPowerRunMode(void);
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
/**
* @}

152
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_rcc.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@ -76,8 +76,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal.h"
@ -97,6 +97,15 @@
/** @defgroup RCC_Private_Constants RCC Private Constants
* @{
*/
/* Bits position in in the CFGR register */
#define RCC_CFGR_PLLMUL_BITNUMBER POSITION_VAL(RCC_CFGR_PLLMUL)
#define RCC_CFGR_PLLDIV_BITNUMBER POSITION_VAL(RCC_CFGR_PLLDIV)
#define RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE)
#define RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1)
#define RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2)
/* Bits position in in the ICSCR register */
#define RCC_ICSCR_MSIRANGE_BITNUMBER POSITION_VAL(RCC_ICSCR_MSIRANGE)
#define RCC_ICSCR_MSITRIM_BITNUMBER POSITION_VAL(RCC_ICSCR_MSITRIM)
/**
* @}
*/
@ -117,8 +126,7 @@
/** @defgroup RCC_Private_Variables RCC Private Variables
* @{
*/
const uint8_t aPLLDivisionFactorTable[4] = {1, 2, 3, 4};
const uint8_t aPLLMULFactorTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
extern const uint8_t PLLMulTable[]; /* Defined in CMSIS (system_stm32l0xx.c)*/
/**
* @}
*/
@ -127,7 +135,7 @@ const uint8_t aPLLMULFactorTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
/** @defgroup RCC_Private_Functions RCC Private Functions
* @{
*/
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange);
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange);
/**
* @}
*/
@ -189,13 +197,14 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange);
-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
(+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
divided by 2 to 16. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
divided by 2 to 16. You have to use @ref __HAL_RCC_RTC_CONFIG() and @ref __HAL_RCC_RTC_ENABLE()
macros to configure this clock.
(+@) LCD: LCD clock can be derived either from the LSI, LSE or HSE clock
divided by 2 to 16. You have to use __HAL_RCC_LCD_CONFIG()
divided by 2 to 16. You have to use @ref __HAL_RCC_LCD_CONFIG()
macros to configure this clock.
(+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
(+@) USB OTG FS: USB OTG FS require a frequency equal to 48 MHz
to work correctly. This clock is derived of the main PLL through PLL Multiplier.
(+@) IWDG clock which is always the LSI clock.
(#) The maximum frequency of the SYSCLK and HCLK is 32 MHz, PCLK2 32 MHz
@ -244,9 +253,9 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange);
* - AHB, APB1 and APB2 prescaler set to 1.
* - CSS and MCO1 OFF
* - All interrupts disabled
* @note This function doesn't modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
* @note This function does not modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
* @retval None
*/
void HAL_RCC_DeInit(void)
@ -259,12 +268,11 @@ void HAL_RCC_DeInit(void)
/* Reset HSION, HSEON, CSSON, HSEBYP & PLLON bits */
CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON | RCC_CR_HSEBYP);
/* Reset CFGR register */
CLEAR_REG(RCC->CFGR);
/* Set MSIClockRange & MSITRIM[4:0] bits to the reset value */
MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSIRANGE | RCC_ICSCR_MSITRIM), (((uint32_t)0 << POSITION_VAL(RCC_ICSCR_MSITRIM)) | RCC_ICSCR_MSIRANGE_5));
MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSIRANGE | RCC_ICSCR_MSITRIM), (((uint32_t)0 << RCC_ICSCR_MSITRIM_BITNUMBER) | RCC_ICSCR_MSIRANGE_5));
/* Set HSITRIM bits to the reset value */
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_ICSCR_HSITRIM)));
@ -292,18 +300,18 @@ void HAL_RCC_DeInit(void)
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(RCC_OscInitStruct != NULL);
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
@ -418,11 +426,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/*----------------------------- MSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
{
/* Check the parameters */
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* When the MSI is used as system clock it will not be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) )
{
@ -430,10 +433,13 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
return HAL_ERROR;
}
/* Otherwise, just the calibration and MSI range change are allowed */
/* Otherwise, just the calibration and MSI range change are allowed */
else
{
/* Check MSICalibrationValue and MSIClockRange input parameters */
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
@ -465,12 +471,19 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = (32768U * (1U << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_BITNUMBER) + 1U)))
>> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_BITNUMBER)];
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
}
}
else
{
/* Check MSI State */
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
/* Check the MSI State */
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
{
@ -488,7 +501,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
return HAL_TIMEOUT;
}
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
/* Check MSICalibrationValue and MSIClockRange input parameters */
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
@ -558,26 +575,36 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
{
FlagStatus pwrclkchanged = RESET;
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
while((PWR->CR & PWR_CR_DBP) == RESET)
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
__HAL_RCC_PWR_CLK_ENABLE();
pwrclkchanged = SET;
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
/* Check the LSE State */
@ -609,6 +636,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
{
__HAL_RCC_PWR_CLK_DISABLE();
}
}
/*-------------------------------- PLL Configuration -----------------------*/
@ -715,7 +748,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(RCC_ClkInitStruct != NULL);
@ -848,7 +881,6 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
{
@ -864,7 +896,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
@ -876,8 +908,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
* @}
*/
/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
* @brief RCC clocks control functions
/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
* @brief RCC clocks control functions
*
@verbatim
===============================================================================
@ -896,7 +928,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
* @note MCO pin should be configured in alternate function mode.
* @param RCC_MCOx specifies the output direction for the clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_MCO Clock source to output on MCO1 pin(PA8).
* @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
* @param RCC_MCOSource specifies the clock source to output.
* This parameter can be one of the following values:
* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
@ -925,15 +957,16 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
assert_param(IS_RCC_MCODIV(RCC_MCODiv));
assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
/* MCO Clock Enable */
MCO1_CLK_ENABLE();
/* Configure the MCO1 pin in alternate function mode */
gpio.Pin = MCO1_PIN;
gpio.Mode = GPIO_MODE_AF_PP;
gpio.Speed = GPIO_SPEED_FREQ_HIGH;
gpio.Pull = GPIO_NOPULL;
gpio.Pin = MCO1_PIN;
gpio.Alternate = GPIO_AF0_MCO;
/* MCO1 Clock Enable */
MCO1_CLK_ENABLE();
HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
/* Configure the MCO clock source */
@ -1015,8 +1048,8 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllm = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)];
plld = aPLLDivisionFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> POSITION_VAL(RCC_CFGR_PLLDIV)];
pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_BITNUMBER) + 1;
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
{
/* HSE used as PLL clock source */
@ -1033,7 +1066,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
default: /* MSI used as system clock */
{
msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> POSITION_VAL(RCC_ICSCR_MSIRANGE);
msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_BITNUMBER;
sysclockfreq = (32768 * (1 << (msiclkrange + 1)));
break;
}
@ -1064,7 +1097,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void)
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]);
}
/**
@ -1076,7 +1109,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void)
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]);
}
/**
@ -1132,7 +1165,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->MSIState = RCC_MSI_OFF;
}
RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSITRIM) >> POSITION_VAL(RCC_ICSCR_MSITRIM));
RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_BITNUMBER);
RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSIRANGE));
/* Get the LSE configuration -----------------------------------------------*/
@ -1159,6 +1192,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
}
/* Get the PLL configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
{
@ -1250,10 +1284,10 @@ __weak void HAL_RCC_CSSCallback(void)
/**
* @brief Update number of Flash wait states in line with MSI range and current
voltage range
* @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6
* @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6
* @retval HAL status
*/
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange)
{
uint32_t vos = 0;
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
@ -1273,7 +1307,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
}
/* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */
if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (msirange == RCC_MSIRANGE_6))
if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6))
{
latency = FLASH_LATENCY_1; /* 1WS */
}

96
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_rcc.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
@ -63,16 +63,15 @@
*/
/* Disable Backup domain write protection state change timeout */
#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
/* LSE state change timeout */
#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define MSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
/**
* @}
*/
@ -265,7 +264,7 @@ typedef struct
This parameter must be a value of @ref RCC_PLL_Division_Factor*/
} RCC_PLLInitTypeDef;
/**
/**
* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
*/
typedef struct
@ -275,16 +274,16 @@ typedef struct
uint32_t HSEState; /*!< The new state of the HSE.
This parameter can be a value of @ref RCC_HSE_Config */
uint32_t LSEState; /*!< The new state of the LSE.
This parameter can be a value of @ref RCC_LSE_Config */
uint32_t HSIState; /*!< The new state of the HSI.
This parameter can be a value of @ref RCC_HSI_Config */
uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
uint32_t LSIState; /*!< The new state of the LSI.
This parameter can be a value of @ref RCC_LSI_Config */
@ -293,7 +292,7 @@ typedef struct
uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint32_t MSIClockRange; /*!< The MSI frequency range.
This parameter can be a value of @ref RCC_MSI_Clock_Range */
@ -301,23 +300,23 @@ typedef struct
} RCC_OscInitTypeDef;
/**
/**
* @brief RCC System, AHB and APB busses clock configuration structure definition
*/
typedef struct
{
uint32_t ClockType; /*!< The clock to be configured.
This parameter can be a value of @ref RCC_System_Clock_Type */
uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
This parameter can be a value of @ref RCC_System_Clock_Source */
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of @ref RCC_AHB_Clock_Source */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
} RCC_ClkInitTypeDef;
@ -379,8 +378,8 @@ typedef struct
/** @defgroup RCC_HSI_Config HSI Config
* @{
*/
#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */
#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */
#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
@ -392,13 +391,13 @@ typedef struct
* @{
*/
#define RCC_MSIRANGE_0 ((uint32_t)RCC_ICSCR_MSIRANGE_0) /*!< MSI = 65.536 KHz */
#define RCC_MSIRANGE_1 ((uint32_t)RCC_ICSCR_MSIRANGE_1) /*!< MSI = 131.072 KHz */
#define RCC_MSIRANGE_2 ((uint32_t)RCC_ICSCR_MSIRANGE_2) /*!< MSI = 262.144 KHz */
#define RCC_MSIRANGE_3 ((uint32_t)RCC_ICSCR_MSIRANGE_3) /*!< MSI = 524.288 KHz */
#define RCC_MSIRANGE_4 ((uint32_t)RCC_ICSCR_MSIRANGE_4) /*!< MSI = 1.048 MHz */
#define RCC_MSIRANGE_5 ((uint32_t)RCC_ICSCR_MSIRANGE_5) /*!< MSI = 2.097 MHz */
#define RCC_MSIRANGE_6 ((uint32_t)RCC_ICSCR_MSIRANGE_6) /*!< MSI = 4.194 MHz */
#define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */
#define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */
#define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */
#define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */
#define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */
#define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */
#define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */
/**
* @}
@ -420,7 +419,7 @@ typedef struct
#define RCC_MSI_OFF ((uint32_t)0x00000000)
#define RCC_MSI_ON ((uint32_t)0x00000001)
#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0x00) /* Default MSI calibration trimming value */
#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0x00000000U) /* Default MSI calibration trimming value */
/**
* @}
@ -585,14 +584,14 @@ typedef struct
/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
* @{
*/
#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
#define RCC_MCO1SOURCE_MSI ((uint32_t)RCC_CFGR_MCO_MSI)
#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
#define RCC_MCO1SOURCE_LSE ((uint32_t)RCC_CFGR_MCO_LSE)
#define RCC_MCO1SOURCE_LSI ((uint32_t)RCC_CFGR_MCO_LSI)
#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLL)
#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI
#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL
/**
* @}
@ -629,7 +628,6 @@ typedef struct
/* Flags in the CSR register */
#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */
#define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSECSSD))) /*!< CSS on LSE failure Detection */
#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | RCC_RMVF_BIT_NUMBER)) /*!< Remove reset flag */
#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */
#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */
@ -949,7 +947,7 @@ typedef struct
#define __HAL_RCC_FLITF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FLITFRST))
#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST))
#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
@ -985,7 +983,7 @@ typedef struct
#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
#define __HAL_RCC_COMP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_COMPRST))
#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
@ -1019,7 +1017,7 @@ typedef struct
#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
@ -1393,7 +1391,7 @@ typedef struct
* PLL as system clock. In this case, you have to select another source
* of the system clock then change the HSE state (ex. disable it).
* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
* @note This function reset the CSSON bit, so if the Clock security system(CSS)
* @note This function reset the CSSON bit, so if the clock security system(CSS)
* was previously enabled you have to enable it again after calling this
* function.
* @param __STATE__ specifies the new state of the HSE.
@ -1585,12 +1583,12 @@ typedef struct
* @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
* Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
* in Range 3.
*
*
* @param __PLLDIV__ specifies the division factor for PLL VCO input clock
* This parameter can be one of the following values:
* @arg @ref RCC_PLL_DIV2 PLL clock output = PLLVCO /2
* @arg @ref RCC_PLL_DIV3 PLL clock output = PLLVCO /3
* @arg @ref RCC_PLL_DIV4 PLL clock output = PLLVCO /4
* @arg @ref RCC_PLL_DIV2 PLL clock output = PLLVCO / 2
* @arg @ref RCC_PLL_DIV3 PLL clock output = PLLVCO / 3
* @arg @ref RCC_PLL_DIV4 PLL clock output = PLLVCO / 4
*
*/
#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\
@ -1614,15 +1612,15 @@ typedef struct
/**
* @brief Macro to configure the system clock source.
* @param __RCC_SYSCLKSOURCE__ specifies the system clock source.
* @param __SYSCLKSOURCE__ specifies the system clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source.
* @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
* @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
* @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
*/
#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) \
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
/** @brief Macro to get the clock source used as system clock.
* @retval The clock source used as system clock. The returned value can be one
@ -1677,7 +1675,7 @@ typedef struct
* access is denied to this domain after reset, you have to enable write
* access using the Power Backup Access macro before to configure
* the RTC clock source (to be done once after reset).
* @note Once the RTC clock is configured it can't be changed unless the
* @note Once the RTC clock is configured it cannot be changed unless the
* Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
* a Power On Reset (POR).
* @note RTC prescaler cannot be modified if HSE is enabled (HSEON = 1).

93
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc_ex.c
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l1xx_hal_rcc_ex.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Extended RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
* + Extended Peripheral Control functions
*
*
******************************************************************************
* @attention
*
@ -48,7 +48,6 @@
#ifdef HAL_RCC_MODULE_ENABLED
/** @defgroup RCCEx RCCEx
* @brief RCC Extension HAL module driver
* @{
@ -110,8 +109,8 @@
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t tickstart = 0;
uint32_t temp_reg = 0;
uint32_t tickstart = 0U;
uint32_t temp_reg = 0U;
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
@ -136,25 +135,34 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
#endif /* LCD */
FlagStatus pwrclkchanged = RESET;
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
while((PWR->CR & PWR_CR_DBP) == RESET)
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
__HAL_RCC_PWR_CLK_ENABLE();
pwrclkchanged = SET;
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
/* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */
temp_reg = (RCC->CR & RCC_CR_RTCPRE);
if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE))
@ -192,7 +200,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
RCC->CSR = temp_reg;
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSERDY))
if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON))
{
/* Get Start Tick */
tickstart = HAL_GetTick();
@ -206,17 +214,21 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
{
__HAL_RCC_PWR_CLK_DISABLE();
}
}
return HAL_OK;
}
/**
* @brief Get the PeriphClkInit according to the internal
* RCC configuration registers.
* @brief Get the PeriphClkInit according to the internal RCC configuration registers.
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* returns the configuration information for the Extended Peripherals clocks(RTC/LCD clocks).
* @retval None
@ -227,7 +239,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
/* Set all possible values for the extended clock type parameter------------*/
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
#if defined(LCD)
#if defined(LCD)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD;
#endif /* LCD */
@ -249,18 +261,19 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
}
/**
* @brief Returns the peripheral clock frequency
* @note Returns 0 if peripheral clock is unknown
* @brief Return the peripheral clock frequency
* @note Return 0 if peripheral clock is unknown
* @param PeriphClk Peripheral clock identifier
* This parameter can be one of the following values:
* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
* @arg @ref RCC_PERIPHCLK_LCD LCD peripheral clock (depends on devices)
* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
* @arg @ref RCC_PERIPHCLK_LCD LCD peripheral clock (*)
* @note (*) means that this peripheral is not present on all the devices
* @retval Frequency in Hz (0: means that no available frequency for the peripheral)
*/
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
uint32_t temp_reg = 0, clkprediv = 0, frequency = 0;
uint32_t srcclk = 0;
uint32_t temp_reg = 0U, clkprediv = 0U, frequency = 0U;
uint32_t srcclk = 0U;
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
@ -298,22 +311,22 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */
{
frequency = HSE_VALUE / 16;
frequency = HSE_VALUE / 16U;
break;
}
case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */
{
frequency = HSE_VALUE / 8;
frequency = HSE_VALUE / 8U;
break;
}
case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */
{
frequency = HSE_VALUE / 4;
frequency = HSE_VALUE / 4U;
break;
}
default: /* HSE DIV2 has been selected */
{
frequency = HSE_VALUE / 2;
frequency = HSE_VALUE / 2U;
break;
}
}
@ -321,7 +334,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* Clock not enabled for RTC */
else
{
frequency = 0;
frequency = 0U;
}
break;
}
@ -333,7 +346,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
return(frequency);
}
#if defined(RCC_CSR_LSECSSON)
#if defined(RCC_LSECSS_SUPPORT)
/**
* @brief Enables the LSE Clock Security System.
* @note If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied
@ -413,7 +426,7 @@ __weak void HAL_RCCEx_LSECSS_Callback(void)
the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
*/
}
#endif /* RCC_CSR_LSECSSON */
#endif /* RCC_LSECSS_SUPPORT */
/**
* @}
@ -427,6 +440,10 @@ __weak void HAL_RCCEx_LSECSS_Callback(void)
* @}
*/
/**
* @}
*/
#endif /* HAL_RCC_MODULE_ENABLED */
/**
* @}

121
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_rcc_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_HAL_RCC_EX_H
@ -80,12 +80,7 @@
/** @addtogroup RCCEx_Private_Macros
* @{
*/
#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
|| defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
|| defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
|| defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
|| defined(STM32L162xE) || defined(STM32L162xDX)
#if defined(LCD)
#define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD))
@ -93,7 +88,7 @@
#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC)
#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
#endif /* LCD */
/**
* @}
@ -116,16 +111,12 @@ typedef struct
uint32_t RTCClockSelection; /*!< specifies the RTC clock source.
This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
|| defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
|| defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
|| defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
|| defined(STM32L162xE) || defined(STM32L162xDX)
#if defined(LCD)
uint32_t LCDClockSelection; /*!< specifies the LCD clock source.
This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
#endif /* LCD */
} RCC_PeriphCLKInitTypeDef;
/**
@ -143,30 +134,25 @@ typedef struct
*/
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001)
#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
|| defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
|| defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
|| defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
|| defined(STM32L162xE) || defined(STM32L162xDX)
#if defined(LCD)
#define RCC_PERIPHCLK_LCD ((uint32_t)0x00000002)
#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
#endif /* LCD */
/**
* @}
*/
#if defined(RCC_CSR_LSECSSON)
#if defined(RCC_LSECSS_SUPPORT)
/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
* @{
*/
#define RCC_EXTI_LINE_LSECSS (EXTI_IMR_MR19) /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
#define RCC_EXTI_LINE_LSECSS (EXTI_IMR_IM19) /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
/**
* @}
*/
#endif /* RCC_CSR_LSECSSON */
#endif /* RCC_LSECSS_SUPPORT */
/**
* @}
@ -880,44 +866,7 @@ typedef struct
*/
#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
|| defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
|| defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
|| defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
|| defined(STM32L162xE) || defined(STM32L162xDX)
/** @defgroup RCCEx_LCD_Configuration LCd Configuration
* @brief Macros to configure clock source of LCD peripherals.
* @{
*/
/** @brief Macro to configures LCD clock (LCDCLK).
* @note LCD and RTC use the same configuration
* @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the
* LCD clock source.
*
* @param __LCD_CLKSOURCE__ specifies the LCD clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock
*/
#define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__)
/** @brief macros to get the LCD clock source.
*/
#define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE()
/**
* @}
*/
#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
#if defined(RCC_CSR_LSECSSON)
#if defined(RCC_LSECSS_SUPPORT)
/**
* @brief Enable interrupt on RCC LSE CSS EXTI Line 19.
@ -1008,7 +957,44 @@ typedef struct
*/
#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS)
#endif /* RCC_CSR_LSECSSON */
#endif /* RCC_LSECSS_SUPPORT */
#if defined(LCD)
/** @defgroup RCCEx_LCD_Configuration LCD Configuration
* @brief Macros to configure clock source of LCD peripherals.
* @{
*/
/** @brief Macro to configures LCD clock (LCDCLK).
* @note LCD and RTC use the same configuration
* @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the
* LCD clock source.
*
* @param __LCD_CLKSOURCE__ specifies the LCD clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock
* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock
*/
#define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__)
/** @brief Macro to get the LCD clock source.
*/
#define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE()
/** @brief Macro to get the LCD clock pre-scaler.
*/
#define __HAL_RCC_GET_LCD_HSE_PRESCALER() __HAL_RCC_GET_RTC_HSE_PRESCALER()
/**
* @}
*/
#endif /* LCD */
/**
@ -1028,7 +1014,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
#if defined(RCC_CSR_LSECSSON)
#if defined(RCC_LSECSS_SUPPORT)
void HAL_RCCEx_EnableLSECSS(void);
void HAL_RCCEx_DisableLSECSS(void);
@ -1036,7 +1022,8 @@ void HAL_RCCEx_EnableLSECSS_IT(void);
void HAL_RCCEx_LSECSS_IRQHandler(void);
void HAL_RCCEx_LSECSS_Callback(void);
#endif /* RCC_CSR_LSECSSON */
#endif /* RCC_LSECSS_SUPPORT */
/**
* @}
*/

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_rtc.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:

38
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_rtc.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
@ -150,8 +150,8 @@ typedef struct
/** @defgroup RTC_Hour_Formats Hour Formats
* @{
*/
#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040)
#define RTC_HOURFORMAT_24 (0x00000000U)
#define RTC_HOURFORMAT_12 (0x00000040U)
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
((FORMAT) == RTC_HOURFORMAT_24))
@ -162,8 +162,8 @@ typedef struct
/** @defgroup RTC_Output_Polarity_Definitions Outpout Polarity
* @{
*/
#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)
#define RTC_OUTPUT_POLARITY_HIGH (0x00000000U)
#define RTC_OUTPUT_POLARITY_LOW (0x00100000U)
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
((POL) == RTC_OUTPUT_POLARITY_LOW))
@ -174,8 +174,8 @@ typedef struct
/** @defgroup RTC_Output_Type_ALARM_OUT Alarm Output Type
* @{
*/
#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)0x00040000)
#define RTC_OUTPUT_TYPE_OPENDRAIN (0x00000000U)
#define RTC_OUTPUT_TYPE_PUSHPULL (0x00040000U)
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
@ -217,9 +217,9 @@ typedef struct
/** @defgroup RTC_DayLightSaving_Definitions DayLightSaving
* @{
*/
#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)
#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)
#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
#define RTC_DAYLIGHTSAVING_SUB1H (0x00020000U)
#define RTC_DAYLIGHTSAVING_ADD1H (0x00010000U)
#define RTC_DAYLIGHTSAVING_NONE (0x00000000U)
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
@ -231,8 +231,8 @@ typedef struct
/** @defgroup RTC_StoreOperation_Definitions StoreOperation
* @{
*/
#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000)
#define RTC_STOREOPERATION_RESET (0x00000000U)
#define RTC_STOREOPERATION_SET (0x00040000U)
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
((OPERATION) == RTC_STOREOPERATION_SET))
@ -243,8 +243,8 @@ typedef struct
/** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format
* @{
*/
#define RTC_FORMAT_BIN ((uint32_t)0x000000000)
#define RTC_FORMAT_BCD ((uint32_t)0x000000001)
#define RTC_FORMAT_BIN (0x000000000U)
#define RTC_FORMAT_BCD (0x000000001U)
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
/**
@ -324,8 +324,8 @@ typedef struct
/** @defgroup RTC_AlarmDateWeekDay_Definitions AlarmDateWeekDay Definitions
* @{
*/
#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)
#define RTC_ALARMDATEWEEKDAYSEL_DATE (0x00000000U)
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY (0x40000000U)
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
@ -337,12 +337,12 @@ typedef struct
/** @defgroup RTC_AlarmMask_Definitions Alarm Mask Definitions
* @{
*/
#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
#define RTC_ALARMMASK_NONE (0x00000000U)
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
#define RTC_ALARMMASK_ALL (0x80808080U)
#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
/**

8
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_rtc_ex.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Extended RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extension peripheral:
@ -1649,8 +1649,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
}
}
/* Disable the Wake-Up timer */
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
/* Clear flag Wake-Up */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
tickstart = HAL_GetTick();
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */

206
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_rtc_ex.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of RTC HAL Extension module.
******************************************************************************
* @attention
@ -163,10 +163,10 @@ typedef struct
/** @defgroup RTC_Masks_Definitions Masks Definitions
* @{
*/
#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
#define RTC_TR_RESERVED_MASK (0x007F7F7FU)
#define RTC_DR_RESERVED_MASK (0x00FFFF3FU)
#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)
#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_ALRAWF | RTC_FLAG_ALRBWF | RTC_FLAG_WUTWF | \
@ -246,10 +246,10 @@ typedef struct
/** @defgroup RTCEx_Output_selection_Definitions Output selection Definitions
* @{
*/
#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)
#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000)
#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)
#define RTC_OUTPUT_DISABLE (0x00000000U)
#define RTC_OUTPUT_ALARMA (0x00200000U)
#define RTC_OUTPUT_ALARMB (0x00400000U)
#define RTC_OUTPUT_WAKEUP (0x00600000U)
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
((OUTPUT) == RTC_OUTPUT_ALARMA) || \
@ -263,44 +263,44 @@ typedef struct
* @{
*/
#if RTC_BKP_NUMBER > 0
#define RTC_BKP_DR0 ((uint32_t)0x00000000)
#define RTC_BKP_DR1 ((uint32_t)0x00000001)
#define RTC_BKP_DR2 ((uint32_t)0x00000002)
#define RTC_BKP_DR3 ((uint32_t)0x00000003)
#define RTC_BKP_DR4 ((uint32_t)0x00000004)
#define RTC_BKP_DR0 (0x00000000U)
#define RTC_BKP_DR1 (0x00000001U)
#define RTC_BKP_DR2 (0x00000002U)
#define RTC_BKP_DR3 (0x00000003U)
#define RTC_BKP_DR4 (0x00000004U)
#endif /* RTC_BKP_NUMBER > 0 */
#if RTC_BKP_NUMBER > 5
#define RTC_BKP_DR5 ((uint32_t)0x00000005)
#define RTC_BKP_DR6 ((uint32_t)0x00000006)
#define RTC_BKP_DR7 ((uint32_t)0x00000007)
#define RTC_BKP_DR8 ((uint32_t)0x00000008)
#define RTC_BKP_DR9 ((uint32_t)0x00000009)
#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
#define RTC_BKP_DR11 ((uint32_t)0x0000000B)
#define RTC_BKP_DR12 ((uint32_t)0x0000000C)
#define RTC_BKP_DR13 ((uint32_t)0x0000000D)
#define RTC_BKP_DR14 ((uint32_t)0x0000000E)
#define RTC_BKP_DR15 ((uint32_t)0x0000000F)
#define RTC_BKP_DR16 ((uint32_t)0x00000010)
#define RTC_BKP_DR17 ((uint32_t)0x00000011)
#define RTC_BKP_DR18 ((uint32_t)0x00000012)
#define RTC_BKP_DR19 ((uint32_t)0x00000013)
#define RTC_BKP_DR5 (0x00000005U)
#define RTC_BKP_DR6 (0x00000006U)
#define RTC_BKP_DR7 (0x00000007U)
#define RTC_BKP_DR8 (0x00000008U)
#define RTC_BKP_DR9 (0x00000009U)
#define RTC_BKP_DR10 (0x0000000AU)
#define RTC_BKP_DR11 (0x0000000BU)
#define RTC_BKP_DR12 (0x0000000CU)
#define RTC_BKP_DR13 (0x0000000DU)
#define RTC_BKP_DR14 (0x0000000EU)
#define RTC_BKP_DR15 (0x0000000FU)
#define RTC_BKP_DR16 (0x00000010U)
#define RTC_BKP_DR17 (0x00000011U)
#define RTC_BKP_DR18 (0x00000012U)
#define RTC_BKP_DR19 (0x00000013U)
#endif /* RTC_BKP_NUMBER > 5 */
#if RTC_BKP_NUMBER > 20
#define RTC_BKP_DR20 ((uint32_t)0x00000014)
#define RTC_BKP_DR21 ((uint32_t)0x00000015)
#define RTC_BKP_DR22 ((uint32_t)0x00000016)
#define RTC_BKP_DR23 ((uint32_t)0x00000017)
#define RTC_BKP_DR24 ((uint32_t)0x00000018)
#define RTC_BKP_DR25 ((uint32_t)0x00000019)
#define RTC_BKP_DR26 ((uint32_t)0x0000001A)
#define RTC_BKP_DR27 ((uint32_t)0x0000001B)
#define RTC_BKP_DR28 ((uint32_t)0x0000001C)
#define RTC_BKP_DR29 ((uint32_t)0x0000001D)
#define RTC_BKP_DR30 ((uint32_t)0x0000001E)
#define RTC_BKP_DR31 ((uint32_t)0x0000001F)
#define RTC_BKP_DR20 (0x00000014U)
#define RTC_BKP_DR21 (0x00000015U)
#define RTC_BKP_DR22 (0x00000016U)
#define RTC_BKP_DR23 (0x00000017U)
#define RTC_BKP_DR24 (0x00000018U)
#define RTC_BKP_DR25 (0x00000019U)
#define RTC_BKP_DR26 (0x0000001AU)
#define RTC_BKP_DR27 (0x0000001BU)
#define RTC_BKP_DR28 (0x0000001CU)
#define RTC_BKP_DR29 (0x0000001DU)
#define RTC_BKP_DR30 (0x0000001EU)
#define RTC_BKP_DR31 (0x0000001FU)
#endif /* RTC_BKP_NUMBER > 20 */
#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
@ -311,8 +311,8 @@ typedef struct
/** @defgroup RTCEx_Time_Stamp_Edges_Definitions Time Stamp Edges Definitions
* @{
*/
#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)
#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008)
#define RTC_TIMESTAMPEDGE_RISING (0x00000000U)
#define RTC_TIMESTAMPEDGE_FALLING (0x00000008U)
#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
@ -341,8 +341,8 @@ typedef struct
/** @defgroup RTCEx_Tamper_Trigger_Definitions Tamper Trigger Definitions
* @{
*/
#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)
#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)
#define RTC_TAMPERTRIGGER_RISINGEDGE (0x00000000U)
#define RTC_TAMPERTRIGGER_FALLINGEDGE (0x00000002U)
#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
@ -365,13 +365,13 @@ typedef struct
/** @defgroup RTCEx_Tamper_Filter_Definitions Tamper Filter Definitions
* @{
*/
#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
#define RTC_TAMPERFILTER_DISABLE (0x00000000U) /*!< Tamper filter is disabled */
#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800) /*!< Tamper is activated after 2
#define RTC_TAMPERFILTER_2SAMPLE (0x00000800U) /*!< Tamper is activated after 2
consecutive samples at the active level */
#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000) /*!< Tamper is activated after 4
#define RTC_TAMPERFILTER_4SAMPLE (0x00001000U) /*!< Tamper is activated after 4
consecutive samples at the active level */
#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8
#define RTC_TAMPERFILTER_8SAMPLE (0x00001800U) /*!< Tamper is activated after 8
consecutive samples at the active level. */
#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
@ -385,21 +385,21 @@ typedef struct
/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions Tamper Sampling Frequencies
* @{
*/
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 (0x00000000U) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 32768 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 (0x00000100U) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 16384 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 (0x00000200U) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 8192 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (0x00000300U) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 4096 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 (0x00000400U) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 2048 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (0x00000500U) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 1024 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (0x00000600U) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 512 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 (0x00000700U) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 256 */
#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
@ -417,13 +417,13 @@ typedef struct
/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions Tamper Pin Precharge Duration
* @{
*/
#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK (0x00000000U) /*!< Tamper pins are pre-charged before
sampling during 1 RTCCLK cycle */
#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK (0x00002000U) /*!< Tamper pins are pre-charged before
sampling during 2 RTCCLK cycles */
#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK (0x00004000U) /*!< Tamper pins are pre-charged before
sampling during 4 RTCCLK cycles */
#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (0x00006000U) /*!< Tamper pins are pre-charged before
sampling during 8 RTCCLK cycles */
#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
@ -438,7 +438,7 @@ typedef struct
* @{
*/
#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */
#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */
#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE (0x00000000U) /*!< TimeStamp on Tamper Detection event is not saved */
#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
@ -449,8 +449,8 @@ typedef struct
/** @defgroup RTCEx_Tamper_Pull_Up_Definitions Tamper Pull-Up Definitions
* @{
*/
#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */
#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */
#define RTC_TAMPER_PULLUP_ENABLE (0x00000000U) /*!< TimeStamp on Tamper Detection event saved */
#define RTC_TAMPER_PULLUP_DISABLE (RTC_TAFCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */
#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
((STATE) == RTC_TAMPER_PULLUP_DISABLE))
@ -462,12 +462,12 @@ typedef struct
/** @defgroup RTCEx_Wakeup_Timer_Definitions Wakeup Timer Definitions
* @{
*/
#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)
#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001)
#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002)
#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003)
#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004)
#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006)
#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 (0x00000000U)
#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 (0x00000001U)
#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 (0x00000002U)
#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (0x00000003U)
#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS (0x00000004U)
#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (0x00000006U)
#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
@ -484,8 +484,8 @@ typedef struct
/** @defgroup RTCEx_Digital_Calibration_Definitions Digital Calibration Definitions
* @{
*/
#define RTC_CALIBSIGN_POSITIVE ((uint32_t)0x00000000)
#define RTC_CALIBSIGN_NEGATIVE ((uint32_t)0x00000080)
#define RTC_CALIBSIGN_POSITIVE (0x00000000U)
#define RTC_CALIBSIGN_NEGATIVE (0x00000080U)
#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \
((SIGN) == RTC_CALIBSIGN_NEGATIVE))
@ -498,11 +498,11 @@ typedef struct
/** @defgroup RTCEx_Smooth_Calib_Period_Definitions Smooth Calib Period Definitions
* @{
*/
#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
#define RTC_SMOOTHCALIB_PERIOD_32SEC (0x00000000U) /*!< If RTCCLK = 32768 Hz, Smooth calibation
period is 32s, else 2exp20 RTCCLK seconds */
#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
#define RTC_SMOOTHCALIB_PERIOD_16SEC (0x00002000U) /*!< If RTCCLK = 32768 Hz, Smooth calibation
period is 16s, else 2exp19 RTCCLK seconds */
#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
#define RTC_SMOOTHCALIB_PERIOD_8SEC (0x00004000U) /*!< If RTCCLK = 32768 Hz, Smooth calibation
period is 8s, else 2exp18 RTCCLK seconds */
#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
@ -515,10 +515,10 @@ typedef struct
/** @defgroup RTCEx_Smooth_Calib_Plus_Pulses_Definitions Smooth Calib Plus Pulses Definitions
* @{
*/
#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
#define RTC_SMOOTHCALIB_PLUSPULSES_SET (0x00008000U) /*!< The number of RTCCLK pulses added
during a X -second window = Y - CALM[8:0]
with Y = 512, 256, 128 when X = 32, 16, 8 */
#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
#define RTC_SMOOTHCALIB_PLUSPULSES_RESET (0x00000000U) /*!< The number of RTCCLK pulses subbstited
during a 32-second window = CALM[8:0] */
#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
@ -530,7 +530,7 @@ typedef struct
/** @defgroup RTCEx_Smooth_Calib_Minus_Pulses_Definitions Smooth Calib Minus Pulses Definitions
* @{
*/
#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU)
/**
* @}
*/
@ -538,8 +538,8 @@ typedef struct
/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions Add 1 Second Parameter Definitions
* @{
*/
#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)
#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000)
#define RTC_SHIFTADD1S_RESET (0x00000000U)
#define RTC_SHIFTADD1S_SET (0x80000000U)
#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
((SEL) == RTC_SHIFTADD1S_SET))
@ -550,7 +550,7 @@ typedef struct
/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value Substract Fraction Of Second Value
* @{
*/
#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU)
/**
* @}
*/
@ -558,8 +558,8 @@ typedef struct
/** @defgroup RTCEx_Calib_Output_Selection_Definitions Calib Output Selection Definitions
* @{
*/
#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)
#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000)
#define RTC_CALIBOUTPUT_512HZ (0x00000000U)
#define RTC_CALIBOUTPUT_1HZ (0x00080000U)
#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
@ -571,7 +571,7 @@ typedef struct
/** @defgroup RTC_Alarm_Sub_Seconds_Value Alarm Sub Seconds Value
* @{
*/
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFFU)
/**
* @}
*/
@ -579,38 +579,38 @@ typedef struct
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions Alarm Sub Seconds Masks Definitions
* @{
*/
#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
#define RTC_ALARMSUBSECONDMASK_ALL (0x00000000U) /*!< All Alarm SS fields are masked.
There is no comparison on sub seconds
for Alarm */
#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_1 (0x01000000U) /*!< SS[14:1] are don't care in Alarm
comparison. Only SS[0] is compared. */
#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_2 (0x02000000U) /*!< SS[14:2] are don't care in Alarm
comparison. Only SS[1:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_3 (0x03000000U) /*!< SS[14:3] are don't care in Alarm
comparison. Only SS[2:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_4 (0x04000000U) /*!< SS[14:4] are don't care in Alarm
comparison. Only SS[3:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_5 (0x05000000U) /*!< SS[14:5] are don't care in Alarm
comparison. Only SS[4:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_6 (0x06000000U) /*!< SS[14:6] are don't care in Alarm
comparison. Only SS[5:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_7 (0x07000000U) /*!< SS[14:7] are don't care in Alarm
comparison. Only SS[6:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_8 (0x08000000U) /*!< SS[14:8] are don't care in Alarm
comparison. Only SS[7:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_9 (0x09000000U) /*!< SS[14:9] are don't care in Alarm
comparison. Only SS[8:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_10 (0x0A000000U) /*!< SS[14:10] are don't care in Alarm
comparison. Only SS[9:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_11 (0x0B000000U) /*!< SS[14:11] are don't care in Alarm
comparison. Only SS[10:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_12 (0x0C000000U) /*!< SS[14:12] are don't care in Alarm
comparison.Only SS[11:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_13 (0x0D000000U) /*!< SS[14:13] are don't care in Alarm
comparison. Only SS[12:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14 (0x0E000000U) /*!< SS[14] is don't care in Alarm
comparison.Only SS[13:0] are compared */
#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
#define RTC_ALARMSUBSECONDMASK_NONE (0x0F000000U) /*!< SS[14:0] are compared and must match
to activate alarm. */
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
@ -1260,8 +1260,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
* @{
*/
#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT (0x00080000U) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT (0x00100000U) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
/**
* @}

168
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_sd.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief SD card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:
@ -212,67 +212,67 @@
SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\
SDIO_FLAG_DBCKEND))
#define SDIO_CMD0TIMEOUT ((uint32_t)0x00010000)
#define SDIO_CMD0TIMEOUT (0x00010000U)
/**
* @brief Mask for errors Card Status R1 (OCR Register)
*/
#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000)
#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000)
#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000)
#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000)
#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000)
#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000)
#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000)
#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000)
#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000)
#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000)
#define SD_OCR_CC_ERROR ((uint32_t)0x00100000)
#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000)
#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000)
#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000)
#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000)
#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000)
#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000)
#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000)
#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008)
#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008)
#define SD_OCR_ADDR_OUT_OF_RANGE (0x80000000U)
#define SD_OCR_ADDR_MISALIGNED (0x40000000U)
#define SD_OCR_BLOCK_LEN_ERR (0x20000000U)
#define SD_OCR_ERASE_SEQ_ERR (0x10000000U)
#define SD_OCR_BAD_ERASE_PARAM (0x08000000U)
#define SD_OCR_WRITE_PROT_VIOLATION (0x04000000U)
#define SD_OCR_LOCK_UNLOCK_FAILED (0x01000000U)
#define SD_OCR_COM_CRC_FAILED (0x00800000U)
#define SD_OCR_ILLEGAL_CMD (0x00400000U)
#define SD_OCR_CARD_ECC_FAILED (0x00200000U)
#define SD_OCR_CC_ERROR (0x00100000U)
#define SD_OCR_GENERAL_UNKNOWN_ERROR (0x00080000U)
#define SD_OCR_STREAM_READ_UNDERRUN (0x00040000U)
#define SD_OCR_STREAM_WRITE_OVERRUN (0x00020000U)
#define SD_OCR_CID_CSD_OVERWRITE (0x00010000U)
#define SD_OCR_WP_ERASE_SKIP (0x00008000U)
#define SD_OCR_CARD_ECC_DISABLED (0x00004000U)
#define SD_OCR_ERASE_RESET (0x00002000U)
#define SD_OCR_AKE_SEQ_ERROR (0x00000008U)
#define SD_OCR_ERRORBITS (0xFDFFE008U)
/**
* @brief Masks for R6 Response
*/
#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000)
#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000)
#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000)
#define SD_R6_GENERAL_UNKNOWN_ERROR (0x00002000U)
#define SD_R6_ILLEGAL_CMD (0x00004000U)
#define SD_R6_COM_CRC_FAILED (0x00008000U)
#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000)
#define SD_HIGH_CAPACITY ((uint32_t)0x40000000)
#define SD_STD_CAPACITY ((uint32_t)0x00000000)
#define SD_CHECK_PATTERN ((uint32_t)0x000001AA)
#define SD_VOLTAGE_WINDOW_SD (0x80100000U)
#define SD_HIGH_CAPACITY (0x40000000U)
#define SD_STD_CAPACITY (0x00000000U)
#define SD_CHECK_PATTERN (0x000001AAU)
#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF)
#define SD_ALLZERO ((uint32_t)0x00000000)
#define SD_MAX_VOLT_TRIAL (0x0000FFFFU)
#define SD_ALLZERO (0x00000000U)
#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000)
#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000)
#define SD_CARD_LOCKED ((uint32_t)0x02000000)
#define SD_WIDE_BUS_SUPPORT (0x00040000U)
#define SD_SINGLE_BUS_SUPPORT (0x00010000U)
#define SD_CARD_LOCKED (0x02000000U)
#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF)
#define SD_0TO7BITS ((uint32_t)0x000000FF)
#define SD_8TO15BITS ((uint32_t)0x0000FF00)
#define SD_16TO23BITS ((uint32_t)0x00FF0000)
#define SD_24TO31BITS ((uint32_t)0xFF000000)
#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF)
#define SD_DATATIMEOUT (0xFFFFFFFFU)
#define SD_0TO7BITS (0x000000FFU)
#define SD_8TO15BITS (0x0000FF00U)
#define SD_16TO23BITS (0x00FF0000U)
#define SD_24TO31BITS (0xFF000000U)
#define SD_MAX_DATA_LENGTH (0x01FFFFFFU)
#define SD_HALFFIFO ((uint32_t)0x00000008)
#define SD_HALFFIFOBYTES ((uint32_t)0x00000020)
#define SD_HALFFIFO (0x00000008U)
#define SD_HALFFIFOBYTES (0x00000020U)
/**
* @brief Command Class Supported
*/
#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080)
#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040)
#define SD_CCCC_ERASE ((uint32_t)0x00000020)
#define SD_CCCC_LOCK_UNLOCK (0x00000080U)
#define SD_CCCC_WRITE_PROT (0x00000040U)
#define SD_CCCC_ERASE (0x00000020U)
/**
* @brief Following commands are SD Card Specific commands.
@ -1528,34 +1528,34 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
pCardInfo->RCA = (uint16_t)(hsd->RCA);
/* Byte 0 */
tmp = (hsd->CSD[0] & 0xFF000000) >> 24;
tmp = (hsd->CSD[0] & 0xFF000000U) >> 24;
pCardInfo->SD_csd.CSDStruct = (uint8_t)((tmp & 0xC0) >> 6);
pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);
pCardInfo->SD_csd.Reserved1 = tmp & 0x03;
/* Byte 1 */
tmp = (hsd->CSD[0] & 0x00FF0000) >> 16;
tmp = (hsd->CSD[0] & 0x00FF0000U) >> 16;
pCardInfo->SD_csd.TAAC = (uint8_t)tmp;
/* Byte 2 */
tmp = (hsd->CSD[0] & 0x0000FF00) >> 8;
tmp = (hsd->CSD[0] & 0x0000FF00U) >> 8;
pCardInfo->SD_csd.NSAC = (uint8_t)tmp;
/* Byte 3 */
tmp = hsd->CSD[0] & 0x000000FF;
tmp = hsd->CSD[0] & 0x000000FFU;
pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp;
/* Byte 4 */
tmp = (hsd->CSD[1] & 0xFF000000) >> 24;
tmp = (hsd->CSD[1] & 0xFF000000U) >> 24;
pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4);
/* Byte 5 */
tmp = (hsd->CSD[1] & 0x00FF0000) >> 16;
tmp = (hsd->CSD[1] & 0x00FF0000U) >> 16;
pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);
pCardInfo->SD_csd.RdBlockLen = (uint8_t)(tmp & 0x0F);
/* Byte 6 */
tmp = (hsd->CSD[1] & 0x0000FF00) >> 8;
tmp = (hsd->CSD[1] & 0x0000FF00U) >> 8;
pCardInfo->SD_csd.PartBlockRead = (uint8_t)((tmp & 0x80) >> 7);
pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);
pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);
@ -1567,23 +1567,23 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10;
/* Byte 7 */
tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU);
pCardInfo->SD_csd.DeviceSize |= (tmp) << 2;
/* Byte 8 */
tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24);
pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6;
pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07);
/* Byte 9 */
tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16);
pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
pCardInfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1;
/* Byte 10 */
tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8);
pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7;
pCardInfo->CardCapacity = (pCardInfo->SD_csd.DeviceSize + 1) ;
@ -1594,21 +1594,21 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
else if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
{
/* Byte 7 */
tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU);
pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16;
/* Byte 8 */
tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24);
pCardInfo->SD_csd.DeviceSize |= (tmp << 8);
/* Byte 9 */
tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16);
pCardInfo->SD_csd.DeviceSize |= (tmp);
/* Byte 10 */
tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8);
pCardInfo->CardCapacity = (uint64_t)((((uint64_t)pCardInfo->SD_csd.DeviceSize + 1)) * 512 * 1024);
pCardInfo->CardBlockSize = 512;
@ -1623,26 +1623,26 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
pCardInfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1;
/* Byte 11 */
tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF);
tmp = (uint8_t)(hsd->CSD[2] & 0x000000FFU);
pCardInfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7;
pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F);
/* Byte 12 */
tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000) >> 24);
tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000U) >> 24);
pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7;
pCardInfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5;
pCardInfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2;
pCardInfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2;
/* Byte 13 */
tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16);
tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000U) >> 16);
pCardInfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6;
pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5;
pCardInfo->SD_csd.Reserved3 = 0;
pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01);
/* Byte 14 */
tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8);
tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00U) >> 8);
pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7;
pCardInfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6;
pCardInfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5;
@ -1651,73 +1651,73 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
pCardInfo->SD_csd.ECC = (tmp & 0x03);
/* Byte 15 */
tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF);
tmp = (uint8_t)(hsd->CSD[3] & 0x000000FFU);
pCardInfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1;
pCardInfo->SD_csd.Reserved4 = 1;
/* Byte 0 */
tmp = (uint8_t)((hsd->CID[0] & 0xFF000000) >> 24);
tmp = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24);
pCardInfo->SD_cid.ManufacturerID = tmp;
/* Byte 1 */
tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16);
tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000U) >> 16);
pCardInfo->SD_cid.OEM_AppliID = tmp << 8;
/* Byte 2 */
tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8);
tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00U) >> 8);
pCardInfo->SD_cid.OEM_AppliID |= tmp;
/* Byte 3 */
tmp = (uint8_t)(hsd->CID[0] & 0x000000FF);
tmp = (uint8_t)(hsd->CID[0] & 0x000000FFU);
pCardInfo->SD_cid.ProdName1 = tmp << 24;
/* Byte 4 */
tmp = (uint8_t)((hsd->CID[1] & 0xFF000000) >> 24);
tmp = (uint8_t)((hsd->CID[1] & 0xFF000000U) >> 24);
pCardInfo->SD_cid.ProdName1 |= tmp << 16;
/* Byte 5 */
tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16);
tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000U) >> 16);
pCardInfo->SD_cid.ProdName1 |= tmp << 8;
/* Byte 6 */
tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8);
tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00U) >> 8);
pCardInfo->SD_cid.ProdName1 |= tmp;
/* Byte 7 */
tmp = (uint8_t)(hsd->CID[1] & 0x000000FF);
tmp = (uint8_t)(hsd->CID[1] & 0x000000FFU);
pCardInfo->SD_cid.ProdName2 = tmp;
/* Byte 8 */
tmp = (uint8_t)((hsd->CID[2] & 0xFF000000) >> 24);
tmp = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24);
pCardInfo->SD_cid.ProdRev = tmp;
/* Byte 9 */
tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16);
tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000U) >> 16);
pCardInfo->SD_cid.ProdSN = tmp << 24;
/* Byte 10 */
tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8);
tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00U) >> 8);
pCardInfo->SD_cid.ProdSN |= tmp << 16;
/* Byte 11 */
tmp = (uint8_t)(hsd->CID[2] & 0x000000FF);
tmp = (uint8_t)(hsd->CID[2] & 0x000000FFU);
pCardInfo->SD_cid.ProdSN |= tmp << 8;
/* Byte 12 */
tmp = (uint8_t)((hsd->CID[3] & 0xFF000000) >> 24);
tmp = (uint8_t)((hsd->CID[3] & 0xFF000000U) >> 24);
pCardInfo->SD_cid.ProdSN |= tmp;
/* Byte 13 */
tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16);
tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000U) >> 16);
pCardInfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4;
pCardInfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8;
/* Byte 14 */
tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8);
tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00U) >> 8);
pCardInfo->SD_cid.ManufactDate |= tmp;
/* Byte 15 */
tmp = (uint8_t)(hsd->CID[3] & 0x000000FF);
tmp = (uint8_t)(hsd->CID[3] & 0x000000FFU);
pCardInfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1;
pCardInfo->SD_cid.Reserved2 = 1;
@ -1848,7 +1848,7 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
}
/* Test the Version supported by the card*/
SD_SPEC = (SD_scr[1] & 0x01000000) | (SD_scr[1] & 0x02000000);
SD_SPEC = (SD_scr[1] & 0x01000000U) | (SD_scr[1] & 0x02000000U);
if (SD_SPEC != SD_ALLZERO)
{
@ -1878,7 +1878,7 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
/* Send CMD6 switch mode */
sdio_cmdinitstructure.Argument = 0x80FFFF01;
sdio_cmdinitstructure.Argument = 0x80FFFF01U;
sdio_cmdinitstructure.CmdIndex = SD_CMD_HS_SWITCH;
SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sd.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_sd.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of SD HAL module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_smartcard.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_smartcard.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief SMARTCARD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_smartcard.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_smartcard.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief This file contains all the functions prototypes for the SMARTCARD
* firmware library.
******************************************************************************

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_spi.c
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief SPI HAL module driver.
*
* This file provides firmware functions to manage the following

28
hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l1xx_hal_spi.h
* @author MCD Application Team
* @version V1.1.3
* @date 04-March-2016
* @version V1.2.0
* @date 01-July-2016
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
@ -131,13 +131,13 @@ typedef struct __SPI_HandleTypeDef
uint16_t TxXferSize; /* SPI Tx transfer size */
uint16_t TxXferCount; /* SPI Tx Transfer Counter */
__IO uint16_t TxXferCount; /* SPI Tx Transfer Counter */
uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
uint16_t RxXferSize; /* SPI Rx transfer size */
uint16_t RxXferCount; /* SPI Rx Transfer Counter */
__IO uint16_t RxXferCount; /* SPI Rx Transfer Counter */
DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA handle parameters */
@ -409,10 +409,10 @@ typedef struct __SPI_HandleTypeDef
*/
#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg; \
tmpreg = (__HANDLE__)->Instance->SR; \
__IO uint32_t tmpreg_modf; \
tmpreg_modf = (__HANDLE__)->Instance->SR; \
CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
UNUSED(tmpreg); \
UNUSED(tmpreg_modf); \
}while(0)
/** @brief Clear the SPI OVR pending flag.
@ -422,10 +422,10 @@ typedef struct __SPI_HandleTypeDef
*/
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg; \
tmpreg = (__HANDLE__)->Instance->DR; \
tmpreg = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg); \
__IO uint32_t tmpreg_ovr; \
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_ovr); \
}while(0)
/** @brief Clear the SPI FRE pending flag.
@ -435,9 +435,9 @@ typedef struct __SPI_HandleTypeDef
*/
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg; \
tmpreg = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg); \
__IO uint32_t tmpreg_fre; \
tmpreg_fre = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_fre); \
}while(0)
/** @brief Enables the SPI.

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