ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add nanostack support for KW41Z 

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
pull/6622/head
Mahesh Mahadevan 2018-02-08 07:56:58 -06:00
parent 65729d6800
commit 585a4b6ddd
30 changed files with 11551 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
features/nanostack/mbed-mesh-api/mbed_lib.json
View File

@ -161,6 +161,9 @@
},
"NCS36510": {
"mbed-mesh-api.heap-size": 14000
},
"KW41Z": {
"mbed-mesh-api.heap-size": 14000
}
}
}

3
features/nanostack/sal-stack-nanostack/mbed_lib.json
View File

@ -16,6 +16,9 @@
},
"TB_SENSE_12": {
"nanostack.configuration": "lowpan_router"
},
"KW41Z": {
"nanostack.configuration": "lowpan_router"
}
}
}

1093
features/nanostack/targets/TARGET_NXP/TARGET_KW41Z/NanostackRfPhyKw41z.cpp Normal file
View File

File diff suppressed because it is too large Load Diff

36
features/nanostack/targets/TARGET_NXP/TARGET_KW41Z/NanostackRfPhyKw41z.h Normal file
View File

@ -0,0 +1,36 @@
/*
* Copyright (c) 2018 ARM Limited. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef NANOSTACK_PHY_KW41Z_H_
#define NANOSTACK_PHY_KW41Z_H_
#if MBED_CONF_RTOS_PRESENT
#include "rtos/rtos.h"
#endif
#include "NanostackRfPhy.h"
#include "fsl_common.h"
class NanostackRfPhyKw41z : public NanostackRfPhy {
public:
NanostackRfPhyKw41z();
~NanostackRfPhyKw41z();
int8_t rf_register();
void rf_unregister();
void get_mac_address(uint8_t *mac);
void set_mac_address(uint8_t *mac);
};
#endif /* NANOSTACK_PHY_KW41Z_H_ */

215
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/Common/EmbeddedTypes.h Normal file
View File

@ -0,0 +1,215 @@
/*!
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* \file
*
* This file holds type definitions that maps the standard c-types into types
* with guaranteed sizes. The types are target/platform specific and must be edited
* for each new target/platform.
* The header file also provides definitions for TRUE, FALSE and NULL.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _EMBEDDEDTYPES_H_
#define _EMBEDDEDTYPES_H_
/************************************************************************************
*
* INCLUDES
*
************************************************************************************/
#include <stdint.h>
/************************************************************************************
*
* TYPE DEFINITIONS
*
************************************************************************************/
/* boolean types */
typedef uint8_t bool_t;
typedef uint8_t index_t;
/* TRUE/FALSE definition*/
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
/* null pointer definition*/
#ifndef NULL
#define NULL (( void * )( 0x0UL ))
#endif
#if defined(__GNUC__)
#define PACKED_STRUCT struct __attribute__ ((__packed__))
#define PACKED_UNION union __attribute__ ((__packed__))
#elif defined(__IAR_SYSTEMS_ICC__)
#define PACKED_STRUCT __packed struct
#define PACKED_UNION __packed union
#else
#define PACKED_STRUCT struct
#define PACKED_UNION union
#endif
typedef unsigned char uintn8_t;
typedef unsigned long uintn32_t;
typedef unsigned char uchar_t;
#if !defined(MIN)
#define MIN(a,b) (((a) < (b))?(a):(b))
#endif
#if !defined(MAX)
#define MAX(a,b) (((a) > (b))?(a):(b))
#endif
/* Compute the number of elements of an array */
#define NumberOfElements(x) (sizeof(x)/sizeof((x)[0]))
/* Compute the size of a string initialized with quotation marks */
#define SizeOfString(string) (sizeof(string) - 1)
#define GetRelAddr(strct, member) ((uint32_t)&(((strct*)(void *)0)->member))
#define GetSizeOfMember(strct, member) sizeof(((strct*)(void *)0)->member)
/* Type definitions for link configuration of instantiable layers */
#define gInvalidInstanceId_c (instanceId_t)(-1)
typedef uint32_t instanceId_t;
/* Bit shift definitions */
#define BIT0 0x01
#define BIT1 0x02
#define BIT2 0x04
#define BIT3 0x08
#define BIT4 0x10
#define BIT5 0x20
#define BIT6 0x40
#define BIT7 0x80
#define BIT8 0x100
#define BIT9 0x200
#define BIT10 0x400
#define BIT11 0x800
#define BIT12 0x1000
#define BIT13 0x2000
#define BIT14 0x4000
#define BIT15 0x8000
#define BIT16 0x10000
#define BIT17 0x20000
#define BIT18 0x40000
#define BIT19 0x80000
#define BIT20 0x100000
#define BIT21 0x200000
#define BIT22 0x400000
#define BIT23 0x800000
#define BIT24 0x1000000
#define BIT25 0x2000000
#define BIT26 0x4000000
#define BIT27 0x8000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
/* Shift definitions */
#define SHIFT0 (0)
#define SHIFT1 (1)
#define SHIFT2 (2)
#define SHIFT3 (3)
#define SHIFT4 (4)
#define SHIFT5 (5)
#define SHIFT6 (6)
#define SHIFT7 (7)
#define SHIFT8 (8)
#define SHIFT9 (9)
#define SHIFT10 (10)
#define SHIFT11 (11)
#define SHIFT12 (12)
#define SHIFT13 (13)
#define SHIFT14 (14)
#define SHIFT15 (15)
#define SHIFT16 (16)
#define SHIFT17 (17)
#define SHIFT18 (18)
#define SHIFT19 (19)
#define SHIFT20 (20)
#define SHIFT21 (21)
#define SHIFT22 (22)
#define SHIFT23 (23)
#define SHIFT24 (24)
#define SHIFT25 (25)
#define SHIFT26 (26)
#define SHIFT27 (27)
#define SHIFT28 (28)
#define SHIFT29 (29)
#define SHIFT30 (30)
#define SHIFT31 (31)
#define SHIFT32 (32)
#define SHIFT33 (33)
#define SHIFT34 (34)
#define SHIFT35 (35)
#define SHIFT36 (36)
#define SHIFT37 (37)
#define SHIFT38 (38)
#define SHIFT39 (39)
#define SHIFT40 (40)
#define SHIFT41 (41)
#define SHIFT42 (42)
#define SHIFT43 (43)
#define SHIFT44 (44)
#define SHIFT45 (45)
#define SHIFT46 (46)
#define SHIFT47 (47)
#define SHIFT48 (48)
#define SHIFT49 (49)
#define SHIFT50 (50)
#define SHIFT51 (51)
#define SHIFT52 (52)
#define SHIFT53 (53)
#define SHIFT54 (54)
#define SHIFT55 (55)
#define SHIFT56 (56)
#define SHIFT57 (57)
#define SHIFT58 (58)
#define SHIFT59 (59)
#define SHIFT60 (60)
#define SHIFT61 (61)
#define SHIFT62 (62)
#define SHIFT63 (63)
#endif /* _EMBEDDEDTYPES_H_ */

608
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/OSAbstraction/Interface/fsl_os_abstraction.h Normal file
View File

@ -0,0 +1,608 @@
/*!
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* \file
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _FSL_OS_ABSTRACTION_H_
#define _FSL_OS_ABSTRACTION_H_
#include "EmbeddedTypes.h"
#include "fsl_os_abstraction_config.h"
#ifdef __cplusplus
extern "C"
{
#endif
/*! *********************************************************************************
*************************************************************************************
* Public type definitions
*************************************************************************************
********************************************************************************** */
/*! @brief Type for the Task Priority*/
typedef uint16_t osaTaskPriority_t;
/*! @brief Type for the timer definition*/
typedef enum {
osaTimer_Once = 0, /*!< one-shot timer*/
osaTimer_Periodic = 1 /*!< repeating timer*/
} osaTimer_t;
/*! @brief Type for a task handler, returned by the OSA_TaskCreate function. */
typedef void* osaTaskId_t;
/*! @brief Type for the parameter to be passed to the task at its creation */
typedef void* osaTaskParam_t;
/*! @brief Type for task pointer. Task prototype declaration */
typedef void (*osaTaskPtr_t) (osaTaskParam_t task_param);
/*! @brief Type for the semaphore handler, returned by the OSA_SemaphoreCreate function. */
typedef void* osaSemaphoreId_t;
/*! @brief Type for the mutex handler, returned by the OSA_MutexCreate function. */
typedef void* osaMutexId_t;
/*! @brief Type for the event handler, returned by the OSA_EventCreate function. */
typedef void* osaEventId_t;
/*! @brief Type for an event flags group, bit 32 is reserved. */
typedef uint32_t osaEventFlags_t;
/*! @brief Message definition. */
typedef void* osaMsg_t;
/*! @brief Type for the message queue handler, returned by the OSA_MsgQCreate function. */
typedef void* osaMsgQId_t;
/*! @brief Type for the Timer handler, returned by the OSA_TimerCreate function. */
typedef void *osaTimerId_t;
/*! @brief Type for the Timer callback function pointer. */
typedef void (*osaTimerFctPtr_t) (void const *argument);
/*! @brief Thread Definition structure contains startup information of a thread.*/
typedef struct osaThreadDef_tag {
osaTaskPtr_t pthread; /*!< start address of thread function*/
uint32_t tpriority; /*!< initial thread priority*/
uint32_t instances; /*!< maximum number of instances of that thread function*/
uint32_t stacksize; /*!< stack size requirements in bytes; 0 is default stack size*/
uint32_t *tstack;
void *tlink;
uint8_t *tname;
bool_t useFloat;
} osaThreadDef_t;
/*! @brief Thread Link Definition structure .*/
typedef struct osaThreadLink_tag{
uint8_t link[12];
osaTaskId_t osThreadId;
osaThreadDef_t *osThreadDefHandle;
uint32_t *osThreadStackHandle;
}osaThreadLink_t, *osaThreadLinkHandle_t;
/*! @Timer Definition structure contains timer parameters.*/
typedef struct osaTimerDef_tag {
osaTimerFctPtr_t pfCallback; /* < start address of a timer function */
void *argument;
} osaTimerDef_t;
/*! @brief Defines the return status of OSA's functions */
typedef enum osaStatus_tag
{
osaStatus_Success = 0U, /*!< Success */
osaStatus_Error = 1U, /*!< Failed */
osaStatus_Timeout = 2U, /*!< Timeout occurs while waiting */
osaStatus_Idle = 3U /*!< Used for bare metal only, the wait object is not ready
and timeout still not occur */
}osaStatus_t;
/*! *********************************************************************************
*************************************************************************************
* Public macros
*************************************************************************************
********************************************************************************** */
#if defined (FSL_RTOS_MQX)
#define USE_RTOS 1
#elif defined (FSL_RTOS_FREE_RTOS)
#define USE_RTOS 1
#elif defined (FSL_RTOS_UCOSII)
#define USE_RTOS 1
#elif defined (FSL_RTOS_UCOSIII)
#define USE_RTOS 1
#else
#define USE_RTOS 0
#endif
#define OSA_PRIORITY_IDLE (6)
#define OSA_PRIORITY_LOW (5)
#define OSA_PRIORITY_BELOW_NORMAL (4)
#define OSA_PRIORITY_NORMAL (3)
#define OSA_PRIORITY_ABOVE_NORMAL (2)
#define OSA_PRIORITY_HIGH (1)
#define OSA_PRIORITY_REAL_TIME (0)
#define OSA_TASK_PRIORITY_MAX (0)
#define OSA_TASK_PRIORITY_MIN (15)
#define SIZE_IN_UINT32_UNITS(size) (((size) + sizeof(uint32_t) - 1) / sizeof(uint32_t))
/*! @brief Constant to pass as timeout value in order to wait indefinitely. */
#define osaWaitForever_c ((uint32_t)(-1))
#define osaEventFlagsAll_c ((osaEventFlags_t)(0x00FFFFFF))
#define osThreadStackArray(name) osThread_##name##_stack
#define osThreadStackDef(name, stacksize, instances) \
uint32_t osThreadStackArray(name)[SIZE_IN_UINT32_UNITS(stacksize)*(instances)];
/* ==== Thread Management ==== */
/* Create a Thread Definition with function, priority, and stack requirements.
* \param name name of the thread function.
* \param priority initial priority of the thread function.
* \param instances number of possible thread instances.
* \param stackSz stack size (in bytes) requirements for the thread function.
* \param useFloat
*/
#if defined(FSL_RTOS_MQX)
#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \
osaThreadLink_t osThreadLink_##name[instances] = {0}; \
osThreadStackDef(name, stackSz, instances) \
osaThreadDef_t os_thread_def_##name = { (name), \
(priority), \
(instances), \
(stackSz), \
osThreadStackArray(name), \
osThreadLink_##name, \
(uint8_t*) #name,\
(useFloat)}
#elif defined (FSL_RTOS_UCOSII)
#if gTaskMultipleInstancesManagement_c
#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \
osaThreadLink_t osThreadLink_##name[instances] = {0}; \
osThreadStackDef(name, stackSz, instances) \
osaThreadDef_t os_thread_def_##name = { (name), \
(priority), \
(instances), \
(stackSz), \
osThreadStackArray(name), \
osThreadLink_##name, \
(uint8_t*) #name,\
(useFloat)}
#else
#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \
osThreadStackDef(name, stackSz, instances) \
osaThreadDef_t os_thread_def_##name = { (name), \
(priority), \
(instances), \
(stackSz), \
osThreadStackArray(name), \
NULL, \
(uint8_t*) #name,\
(useFloat)}
#endif
#else
#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \
osaThreadDef_t os_thread_def_##name = { (name), \
(priority), \
(instances), \
(stackSz), \
NULL, \
NULL, \
(uint8_t*) #name,\
(useFloat)}
#endif
/* Access a Thread defintion.
* \param name name of the thread definition object.
*/
#define OSA_TASK(name) \
&os_thread_def_##name
#define OSA_TASK_PROTO(name) \
extern osaThreadDef_t os_thread_def_##name
/* ==== Timer Management ====
* Define a Timer object.
* \param name name of the timer object.
* \param function name of the timer call back function.
*/
#define OSA_TIMER_DEF(name, function) \
osaTimerDef_t os_timer_def_##name = \
{ (function), NULL }
/* Access a Timer definition.
* \param name name of the timer object.
*/
#define OSA_TIMER(name) \
&os_timer_def_##name
/*****************************************************************************
******************************************************************************
* Public memory declarations
******************************************************************************
*****************************************************************************/
extern const uint8_t gUseRtos_c;
/*! *********************************************************************************
*************************************************************************************
* Public functions
*************************************************************************************
********************************************************************************** */
/*!
* @name Task management
* @{
*/
/*!
* @brief Creates a task.
*
* This function is used to create task based on the resources defined
* by the macro OSA_TASK_DEFINE.
*
* @param thread_def pointer to the osaThreadDef_t structure which defines the task.
* @param task_param Pointer to be passed to the task when it is created.
*
* @retval taskId The task is successfully created.
* @retval NULL The task can not be created..
*
* Example:
@code
osaTaskId_t taskId;
OSA_TASK_DEFINE( Job1, OSA_PRIORITY_HIGH, 1, 800, 0);;
taskId = OSA__TaskCreate(OSA__TASK(Job1), (osaTaskParam_t)NULL);
@endcode
*/
osaTaskId_t OSA_TaskCreate(osaThreadDef_t *thread_def, osaTaskParam_t task_param);
/*!
* @brief Gets the handler of active task.
*
* @return Handler to current active task.
*/
osaTaskId_t OSA_TaskGetId(void);
/*!
* @brief Puts the active task to the end of scheduler's queue.
*
* When a task calls this function, it gives up the CPU and puts itself to the
* end of a task ready list.
*
* @retval osaStatus_Success The function is called successfully.
* @retval osaStatus_Error Error occurs with this function.
*/
osaStatus_t OSA_TaskYield(void);
/*!
* @brief Gets the priority of a task.
*
* @param taskId The handler of the task whose priority is received.
*
* @return Task's priority.
*/
osaTaskPriority_t OSA_TaskGetPriority(osaTaskId_t taskId);
/*!
* @brief Sets the priority of a task.
*
* @param taskId The handler of the task whose priority is set.
* @param taskPriority The priority to set.
*
* @retval osaStatus_Success Task's priority is set successfully.
* @retval osaStatus_Error Task's priority can not be set.
*/
osaStatus_t OSA_TaskSetPriority(osaTaskId_t taskId, osaTaskPriority_t taskPriority);
/*!
* @brief Destroys a previously created task.
*
* @param taskId The handler of the task to destroy. Returned by the OSA_TaskCreate function.
*
* @retval osaStatus_Success The task was successfully destroyed.
* @retval osaStatus_Error Task destruction failed or invalid parameter.
*/
osaStatus_t OSA_TaskDestroy(osaTaskId_t taskId);
/*!
* @brief Creates a semaphore with a given value.
*
* This function creates a semaphore and sets the value to the parameter
* initValue.
*
* @param initValue Initial value the semaphore will be set to.
*
* @retval handler to the new semaphore if the semaphore is created successfully.
* @retval NULL if the semaphore can not be created.
*
*
*/
osaSemaphoreId_t OSA_SemaphoreCreate(uint32_t initValue);
/*!
* @brief Destroys a previously created semaphore.
*
* @param semId Pointer to the semaphore to destroy.
*
* @retval osaStatus_Success The semaphore is successfully destroyed.
* @retval osaStatus_Error The semaphore can not be destroyed.
*/
osaStatus_t OSA_SemaphoreDestroy(osaSemaphoreId_t semId);
/*!
* @brief Pending a semaphore with timeout.
*
* This function checks the semaphore's counting value. If it is positive,
* decreases it and returns osaStatus_Success. Otherwise, a timeout is used
* to wait.
*
* @param semId Pointer to the semaphore.
* @param millisec The maximum number of milliseconds to wait if semaphore is not
* positive. Pass osaWaitForever_c to wait indefinitely, pass 0
* will return osaStatus_Timeout immediately.
*
* @retval osaStatus_Success The semaphore is received.
* @retval osaStatus_Timeout The semaphore is not received within the specified 'timeout'.
* @retval osaStatus_Error An incorrect parameter was passed.
*/
osaStatus_t OSA_SemaphoreWait(osaSemaphoreId_t semId, uint32_t millisec);
/*!
* @brief Signals for someone waiting on the semaphore to wake up.
*
* Wakes up one task that is waiting on the semaphore. If no task is waiting, increases
* the semaphore's counting value.
*
* @param semId Pointer to the semaphore to signal.
*
* @retval osaStatus_Success The semaphore is successfully signaled.
* @retval osaStatus_Error The object can not be signaled or invalid parameter.
*
*/
osaStatus_t OSA_SemaphorePost(osaSemaphoreId_t semId);
/*!
* @brief Create an unlocked mutex.
*
* This function creates a non-recursive mutex and sets it to unlocked status.
*
* @param none.
*
* @retval handler to the new mutex if the mutex is created successfully.
* @retval NULL if the mutex can not be created.
*/
osaMutexId_t OSA_MutexCreate(void);
/*!
* @brief Waits for a mutex and locks it.
*
* This function checks the mutex's status. If it is unlocked, locks it and returns the
* osaStatus_Success. Otherwise, waits for a timeout in milliseconds to lock.
*
* @param mutexId Pointer to the Mutex.
* @param millisec The maximum number of milliseconds to wait for the mutex.
* If the mutex is locked, Pass the value osaWaitForever_c will
* wait indefinitely, pass 0 will return osaStatus_Timeout
* immediately.
*
* @retval osaStatus_Success The mutex is locked successfully.
* @retval osaStatus_Timeout Timeout occurred.
* @retval osaStatus_Error Incorrect parameter was passed.
*
* @note This is non-recursive mutex, a task can not try to lock the mutex it has locked.
*/
osaStatus_t OSA_MutexLock(osaMutexId_t mutexId, uint32_t millisec);
/*!
* @brief Unlocks a previously locked mutex.
*
* @param mutexId Pointer to the Mutex.
*
* @retval osaStatus_Success The mutex is successfully unlocked.
* @retval osaStatus_Error The mutex can not be unlocked or invalid parameter.
*/
osaStatus_t OSA_MutexUnlock(osaMutexId_t mutexId);
/*!
* @brief Destroys a previously created mutex.
*
* @param mutexId Pointer to the Mutex.
*
* @retval osaStatus_Success The mutex is successfully destroyed.
* @retval osaStatus_Error The mutex can not be destroyed.
*
*/
osaStatus_t OSA_MutexDestroy(osaMutexId_t mutexId);
/*!
* @brief Initializes an event object with all flags cleared.
*
* This function creates an event object and set its clear mode. If autoClear
* is TRUE, when a task gets the event flags, these flags will be
* cleared automatically. Otherwise these flags must
* be cleared manually.
*
* @param autoClear TRUE The event is auto-clear.
* FALSE The event manual-clear
* @retval handler to the new event if the event is created successfully.
* @retval NULL if the event can not be created.
*/
osaEventId_t OSA_EventCreate(bool_t autoClear);
/*!
* @brief Sets one or more event flags.
*
* Sets specified flags of an event object.
*
* @param eventId Pointer to the event.
* @param flagsToSet Flags to be set.
*
* @retval osaStatus_Success The flags were successfully set.
* @retval osaStatus_Error An incorrect parameter was passed.
*/
osaStatus_t OSA_EventSet(osaEventId_t eventId, osaEventFlags_t flagsToSet);
/*!
* @brief Clears one or more flags.
*
* Clears specified flags of an event object.
*
* @param eventId Pointer to the event.
* @param flagsToClear Flags to be clear.
*
* @retval osaStatus_Success The flags were successfully cleared.
* @retval osaStatus_Error An incorrect parameter was passed.
*/
osaStatus_t OSA_EventClear(osaEventId_t eventId, osaEventFlags_t flagsToClear);
/*!
* @brief Waits for specified event flags to be set.
*
* This function waits for a combination of flags to be set in an event object.
* Applications can wait for any/all bits to be set. Also this function could
* obtain the flags who wakeup the waiting task.
*
* @param eventId Pointer to the event.
* @param flagsToWait Flags that to wait.
* @param waitAll Wait all flags or any flag to be set.
* @param millisec The maximum number of milliseconds to wait for the event.
* If the wait condition is not met, pass osaWaitForever_c will
* wait indefinitely, pass 0 will return osaStatus_Timeout
* immediately.
* @param setFlags Flags that wakeup the waiting task are obtained by this parameter.
*
* @retval osaStatus_Success The wait condition met and function returns successfully.
* @retval osaStatus_Timeout Has not met wait condition within timeout.
* @retval osaStatus_Error An incorrect parameter was passed.
*
* @note Please pay attention to the flags bit width, FreeRTOS uses the most
* significant 8 bis as control bits, so do not wait these bits while using
* FreeRTOS.
*
*/
osaStatus_t OSA_EventWait(osaEventId_t eventId, osaEventFlags_t flagsToWait, bool_t waitAll, uint32_t millisec, osaEventFlags_t *pSetFlags);
/*!
* @brief Destroys a previously created event object.
*
* @param eventId Pointer to the event.
*
* @retval osaStatus_Success The event is successfully destroyed.
* @retval osaStatus_Error Event destruction failed.
*/
osaStatus_t OSA_EventDestroy(osaEventId_t eventId);
/*!
* @brief Initializes a message queue.
*
* This function allocates memory for and initializes a message queue. Message queue elements are hardcoded as void*.
*
* @param msgNo :number of messages the message queue should accommodate.
* This parameter should not exceed osNumberOfMessages defined in OSAbstractionConfig.h.
*
* @return: Handler to access the queue for put and get operations. If message queue
* creation failed, return NULL.
*/
osaMsgQId_t OSA_MsgQCreate(uint32_t msgNo);
/*!
* @brief Puts a message at the end of the queue.
*
* This function puts a message to the end of the message queue. If the queue
* is full, this function returns the osaStatus_Error;
*
* @param msgQId pointer to queue returned by the OSA_MsgQCreate function.
* @param pMessage Pointer to the message to be put into the queue.
*
* @retval osaStatus_Success Message successfully put into the queue.
* @retval osaStatus_Error The queue was full or an invalid parameter was passed.
*/
osaStatus_t OSA_MsgQPut(osaMsgQId_t msgQId, osaMsg_t pMessage);
/*!
* @brief Reads and remove a message at the head of the queue.
*
* This function gets a message from the head of the message queue. If the
* queue is empty, timeout is used to wait.
*
* @param msgQId Queue handler returned by the OSA_MsgQCreate function.
* @param pMessage Pointer to a memory to save the message.
* @param millisec The number of milliseconds to wait for a message. If the
* queue is empty, pass osaWaitForever_c will wait indefinitely,
* pass 0 will return osaStatus_Timeout immediately.
*
* @retval osaStatus_Success Message successfully obtained from the queue.
* @retval osaStatus_Timeout The queue remains empty after timeout.
* @retval osaStatus_Error Invalid parameter.
*/
osaStatus_t OSA_MsgQGet(osaMsgQId_t msgQId, osaMsg_t pMessage, uint32_t millisec);
/*!
* @brief Destroys a previously created queue.
*
* @param msgQId queue handler returned by the OSA_MsgQCreate function.
*
* @retval osaStatus_Success The queue was successfully destroyed.
* @retval osaStatus_Error Message queue destruction failed.
*/
osaStatus_t OSA_MsgQDestroy(osaMsgQId_t msgQId);
/*!
* @brief Enable all interrupts.
*/
void OSA_InterruptEnable(void);
/*!
* @brief Disable all interrupts.
*/
void OSA_InterruptDisable(void);
/*!
* @brief Enable all interrupts using PRIMASK.
*/
void OSA_EnableIRQGlobal(void);
/*!
* @brief Disable all interrupts using PRIMASK.
*/
void OSA_DisableIRQGlobal(void);
/*!
* @brief Delays execution for a number of milliseconds.
*
* @param millisec The time in milliseconds to wait.
*/
void OSA_TimeDelay(uint32_t millisec);
/*!
* @brief This function gets current time in milliseconds.
*
* @retval current time in milliseconds
*/
uint32_t OSA_TimeGetMsec(void);
/*!
* @brief Installs the interrupt handler.
*
* @param IRQNumber IRQ number of the interrupt.
* @param handler The interrupt handler to install.
*/
void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void));
#ifdef __cplusplus
}
#endif
#endif

63
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/OSAbstraction/Interface/fsl_os_abstraction_config.h Normal file
View File

@ -0,0 +1,63 @@
/*!
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* \file
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _FSL_OS_ABSTRACTION_CONFIG_H_
#define _FSL_OS_ABSTRACTION_CONFIG_H_
#ifndef osNumberOfSemaphores
#define osNumberOfSemaphores 5
#endif
#ifndef osNumberOfMutexes
#define osNumberOfMutexes 5
#endif
#ifndef osNumberOfMessageQs
#define osNumberOfMessageQs 0
#endif
#ifndef osNumberOfMessages
#define osNumberOfMessages 10
#endif
#ifndef osNumberOfEvents
#define osNumberOfEvents 5
#endif
#ifndef gMainThreadStackSize_c
#define gMainThreadStackSize_c 1024
#endif
#ifndef gMainThreadPriority_c
#define gMainThreadPriority_c 7
#endif
#ifndef gTaskMultipleInstancesManagement_c
#define gTaskMultipleInstancesManagement_c 0
#endif
#endif /* _FSL_OS_ABSTRACTION_CONFIG_H_ */

23
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/OSAbstraction/Source/fsl_os_abstraction_mbed.c Normal file
View File

@ -0,0 +1,23 @@
#include "fsl_os_abstraction.h"
#include "fsl_common.h"
/*FUNCTION**********************************************************************
*
* Function Name : OSA_InterruptEnable
* Description : self explanatory.
*
*END**************************************************************************/
void OSA_InterruptEnable(void)
{
__enable_irq();
}
/*FUNCTION**********************************************************************
*
* Function Name : OSA_InterruptDisable
* Description : self explanatory.
*
*END**************************************************************************/
void OSA_InterruptDisable(void)
{
__disable_irq();
}

207
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_ant_config.c Normal file
View File

@ -0,0 +1,207 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_xcvr.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
const xcvr_mode_config_t ant_mode_config =
{
.radio_mode = ANT_MODE,
.scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK
#if !RADIO_IS_GEN_2P1
| SIM_SCGC5_ANT_MASK
#endif /* !RADIO_IS_GEN_2P1 */
,
/* XCVR_MISC configs */
.xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
.xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(3) |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
/* XCVR_PHY configs */
.phy_pre_ref0_init = RW0PS(0, 0x1B) |
RW0PS(1, 0x1CU) |
RW0PS(2, 0x1CU) |
RW0PS(3, 0x1CU) |
RW0PS(4, 0x1DU) |
RW0PS(5, 0x1DU) |
RW0PS(6, 0x1EU & 0x3U), /* Phase info #6 overlaps two initialization words - only need two lowest bits*/
.phy_pre_ref1_init = (0x1E) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift */
RW1PS(7, 0x1EU) |
RW1PS(8, 0x1EU) |
RW1PS(9, 0x1EU) |
RW1PS(10, 0x1EU) |
RW1PS(11, 0x1DU) |
RW1PS(12, 0x1DU & 0xFU), /* Phase info #12 overlaps two initialization words */
.phy_pre_ref2_init = (0x1D) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift */
RW2PS(13, 0x1CU) |
RW2PS(14, 0x1CU) |
RW2PS(15, 0x1CU),
.phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) |
XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) |
XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
XCVR_PHY_CFG1_BSM_EN_BLE(0) |
XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
XCVR_PHY_CFG1_CTS_THRESH(0xF8) |
XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
.phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
#if !RADIO_IS_GEN_2P1
| XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
#endif /* !RADIO_IS_GEN_2P1 */
,
/* XCVR_RX_DIG configs */
.rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
.rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
.agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
/* XCVR_TSM configs */
#if (DATA_PADDING_EN)
.tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
#else
.tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
#endif /* (DATA_PADDING_EN) */
/* XCVR_TX_DIG configs */
.tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
.tx_gfsk_coeff1_26mhz = 0,
.tx_gfsk_coeff2_26mhz = 0,
.tx_gfsk_coeff1_32mhz = 0,
.tx_gfsk_coeff2_32mhz = 0,
};
/* MODE & DATA RATE combined configuration */
const xcvr_mode_datarate_config_t xcvr_ANT_1mbps_config =
{
.radio_mode = ANT_MODE,
.data_rate = DR_1MBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(14) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFB,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF5,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF0,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEC,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF3,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0001,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0016,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0049,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0069,
/* ANT 32MHz Channel Filter */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFF9,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF4,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFED,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFE7,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFE7,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEE,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFFD,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0031,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004E,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0066,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0073,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};

201
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_ble_config.c Normal file
View File

@ -0,0 +1,201 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_xcvr.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
const xcvr_mode_config_t ble_mode_config =
{
.radio_mode = BLE_MODE,
.scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_BTLL_MASK,
/* XCVR_MISC configs */
.xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
.xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(0) |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
/* XCVR_PHY configs */
.phy_pre_ref0_init = RW0PS(0, 0x19) |
RW0PS(1, 0x19U) |
RW0PS(2, 0x1AU) |
RW0PS(3, 0x1BU) |
RW0PS(4, 0x1CU) |
RW0PS(5, 0x1CU) |
RW0PS(6, 0x1DU & 0x3U), /* Phase info #6 overlaps two initialization words */
.phy_pre_ref1_init = (0x1D) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift*/
RW1PS(7, 0x1EU) |
RW1PS(8, 0x1EU) |
RW1PS(9, 0x1EU) |
RW1PS(10, 0x1DU) |
RW1PS(11, 0x1CU) |
RW1PS(12, 0x1CU & 0xFU), /* Phase info #12 overlaps two initialization words */
.phy_pre_ref2_init = (0x1C) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift*/
RW2PS(13, 0x1BU) |
RW2PS(14, 0x1AU) |
RW2PS(15, 0x19U),
.phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) |
XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) |
XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
XCVR_PHY_CFG1_BSM_EN_BLE(0) |
XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
XCVR_PHY_CFG1_CTS_THRESH(220) |
XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
.phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) /* Per SMB */
#if !RADIO_IS_GEN_2P1
| XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
#endif /* !RADIO_IS_GEN_2P1 */
,
/* XCVR_RX_DIG configs */
.rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
.rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
.agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
/* XCVR_TSM configs */
#if (DATA_PADDING_EN)
.tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
#else
.tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
#endif /* (DATA_PADDING_EN) */
/* XCVR_TX_DIG configs */
.tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
.tx_gfsk_coeff1_26mhz = 0,
.tx_gfsk_coeff2_26mhz = 0,
.tx_gfsk_coeff1_32mhz = 0,
.tx_gfsk_coeff2_32mhz = 0,
};
/* MODE & DATA RATE combined configuration */
const xcvr_mode_datarate_config_t xcvr_BLE_1mbps_config =
{
.radio_mode = BLE_MODE,
.data_rate = DR_1MBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /* TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* BLE 26MHz Channel Filter */
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFA,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF6,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF1,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEE,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEF,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF6,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0004,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0017,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0063,
/* BLE 32MHz Channel Filter */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF5,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFEF,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEB,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEB,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x0000,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0030,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004A,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006B,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
};

623
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_common_config.c Normal file
View File

@ -0,0 +1,623 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_xcvr.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
const xcvr_common_config_t xcvr_common_config =
{
/* XCVR_ANA configs */
.ana_sy_ctrl1.mask = XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_MASK,
.ana_sy_ctrl1.init = XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL(3), /* PLL Analog Loop Filter */
#define hpm_vcm_tx 0
#define hpm_vcm_cal 1
#define hpm_fdb_res_tx 0
#define hpm_fdb_res_cal 1
#define modulation_word_manual 0
#define mod_disable 0
#define hpm_mod_manual 0
#define hpm_mod_disable 0
#define hpm_sdm_out_manual 0
#define hpm_sdm_out_disable 0
#define channel_num 0
#define boc 0
#define bmr 1
#define zoc 0
#define ctune_ldf_lev 8
#define ftf_rx_thrsh 33
#define ftw_rx 0
#define ftf_tx_thrsh 6
#define ftw_tx 0
#define freq_count_go 0
#define freq_count_time 0
#define hpm_sdm_in_manual 0
#define hpm_sdm_out_invert 0
#define hpm_sdm_in_disable 0
#define hpm_lfsr_size 4
#define hpm_dth_scl 0
#define hpm_dth_en 1
#define hpm_integer_scale 0
#define hpm_integer_invert 0
#define hpm_cal_invert 1
#define hpm_mod_in_invert 1
#define hpm_cal_not_bumped 0
#define hpm_cal_count_scale 0
#define hp_cal_disable 0
#define hpm_cal_factor_manual 0
#define hpm_cal_array_size 1
#define hpm_cal_time 0
#define hpm_sdm_denom 256
#define hpm_count_adjust 0
#define pll_ld_manual 0
#define pll_ld_disable 0
#define lpm_sdm_inv 0
#define lpm_disable 0
#define lpm_dth_scl 8
#define lpm_d_ctrl 1
#define lpm_d_ovrd 1
#define lpm_scale 8
#define lpm_sdm_use_neg 0
#define hpm_array_bias 0
#define lpm_intg 38
#define sdm_map_disable 0
#define lpm_sdm_delay 4
#define hpm_sdm_delay 0
#define hpm_integer_delay 0
#define ctune_target_manual 0
#define ctune_target_disable 0
#define ctune_adjust 0
#define ctune_manual 0
#define ctune_disable 0
/*-------------------------------------------------------------------------------------------------*/
.pll_hpm_bump = XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL(hpm_fdb_res_cal) |
XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX(hpm_fdb_res_tx) |
XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL(hpm_vcm_cal) |
XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX(hpm_vcm_tx),
/*-------------------------------------------------------------------------------------------------*/
.pll_mod_ctrl = XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE(hpm_mod_disable) |
XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL(hpm_mod_manual) |
XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE(hpm_sdm_out_disable) |
XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL(hpm_sdm_out_manual) |
XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE(mod_disable) |
XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL(modulation_word_manual),
/*-------------------------------------------------------------------------------------------------*/
.pll_chan_map = XCVR_PLL_DIG_CHAN_MAP_BMR(bmr) |
XCVR_PLL_DIG_CHAN_MAP_BOC(boc) |
XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(channel_num)
#if !RADIO_IS_GEN_2P1
| XCVR_PLL_DIG_CHAN_MAP_ZOC(zoc)
#endif /* !RADIO_IS_GEN_2P1 */
,
/*-------------------------------------------------------------------------------------------------*/
.pll_lock_detect = XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV(ctune_ldf_lev) |
XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO(freq_count_go) |
XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME(freq_count_time) |
XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH(ftf_rx_thrsh) |
XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH(ftf_tx_thrsh) |
XCVR_PLL_DIG_LOCK_DETECT_FTW_RX(ftw_rx) |
XCVR_PLL_DIG_LOCK_DETECT_FTW_TX(ftw_tx),
/*-------------------------------------------------------------------------------------------------*/
.pll_hpm_ctrl = XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT(hpm_cal_invert) |
XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN(hpm_dth_en) |
XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL(hpm_dth_scl) |
XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT(hpm_integer_invert) |
XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE(hpm_integer_scale) |
XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE(hpm_lfsr_size) |
XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT(hpm_mod_in_invert) |
XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE(hpm_sdm_in_disable) |
XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL(hpm_sdm_in_manual) |
XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT(hpm_sdm_out_invert),
/*-------------------------------------------------------------------------------------------------*/
#if !RADIO_IS_GEN_2P1
.pll_hpmcal_ctrl = XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE(hp_cal_disable) |
XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE(hpm_cal_array_size) |
XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE(hpm_cal_count_scale) |
XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL(hpm_cal_factor_manual) |
XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED(hpm_cal_not_bumped) |
XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME(hpm_cal_time),
#endif /* !RADIO_IS_GEN_2P1 */
/*-------------------------------------------------------------------------------------------------*/
.pll_hpm_sdm_res = XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST(hpm_count_adjust) |
XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM(hpm_sdm_denom),
/*-------------------------------------------------------------------------------------------------*/
.pll_lpm_ctrl = XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL(lpm_d_ctrl) |
XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD(lpm_d_ovrd) |
XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE(lpm_disable) |
XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL(lpm_dth_scl) |
XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE(lpm_scale) |
XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV(lpm_sdm_inv) |
XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG(lpm_sdm_use_neg) |
XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE(pll_ld_disable) |
XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL(pll_ld_manual),
/*-------------------------------------------------------------------------------------------------*/
.pll_lpm_sdm_ctrl1 = XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS(hpm_array_bias) |
XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(lpm_intg) |
XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE(sdm_map_disable),
/*-------------------------------------------------------------------------------------------------*/
.pll_delay_match = XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY(hpm_integer_delay) |
XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY(hpm_sdm_delay) |
XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY(lpm_sdm_delay),
/*-------------------------------------------------------------------------------------------------*/
.pll_ctune_ctrl = XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST(ctune_adjust) |
XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE(ctune_disable) |
XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL(ctune_manual) |
XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE(ctune_target_disable) |
XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(ctune_target_manual),
/*-------------------------------------------------------------------------------------------------*/
/* XCVR_RX_DIG configs */
/* NOTE: Clock specific settings are embedded in the mode dependent configs */
.rx_dig_ctrl_init = XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(0) |
XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(0) |
#if !RADIO_IS_GEN_2P1
XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN(0) |
#endif /* !RADIO_IS_GEN_2P1 */
XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(0) |
XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN(1) |
XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(1) |
XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(1) |
XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(1) |
XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(1) |
XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(0) |
XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(0) |
XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(1),
.agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) |
XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2) |
XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN(1) |
XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA(0) |
XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN(1) |
XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC(0) |
XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ(2) |
XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ(2) |
XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH(0xe7),
.agc_ctrl_3_init = XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME(21) |
XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY(2) |
XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S(20) |
XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ(6) |
XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ(2),
/* DCOC configs */
.dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(16) | /* Only the duration changes between 26MHz and 32MHz ref osc settings */
#if (RADIO_IS_GEN_2P1)
XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN(0) |
#endif /* (RADIO_IS_GEN_2P1) */
XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(0) |
XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1) |
XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(0) |
XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) |
XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1),
.dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(20) | /* Only the duration changes between 26MHz and 32MHz ref osc settings */
#if (RADIO_IS_GEN_2P1)
XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN(0) |
#endif /* (RADIO_IS_GEN_2P1) */
XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(0) |
XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1) |
XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(0) |
XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) |
XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1),
.dcoc_ctrl_1_init = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX(26),
.dc_resid_ctrl_init = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE(4) |
XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA(1) |
XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN(1) |
XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX(26),
.dcoc_cal_gain_init = XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1(1) |
XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1(1) |
XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2(1) |
XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2(2) |
XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3(3) |
XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3(1) ,
.dcoc_cal_rcp_init = XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP(1) |
XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(711),
.lna_gain_val_3_0 = XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0(0x1DU) |
XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1(0x32U) |
XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2(0x09U) |
XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3(0x38U),
.lna_gain_val_7_4 = XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4(0x4FU) |
XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5(0x5BU) |
XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6(0x72U) |
XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7(0x8AU),
.lna_gain_val_8 = XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8(0xA0U) |
XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9(0xB6U),
.bba_res_tune_val_7_0 = XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0(0x0) |
XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1(0x0) |
XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2(0x0) |
XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3(0x0) |
XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4(0x0) |
XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5(0x0) |
XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6(0x0) |
XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7(0xF),
.bba_res_tune_val_10_8 = XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8(0x0) |
XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9(0x1) |
XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10(0x2),
.lna_gain_lin_val_2_0_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0(0) |
XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1(0) |
XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2(1),
.lna_gain_lin_val_5_3_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3(3) |
XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4(5) |
XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5(7),
.lna_gain_lin_val_8_6_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6(14) |
XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7(27) |
XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8(50),
.lna_gain_lin_val_9_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9(91),
.bba_res_tune_lin_val_3_0_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0(8) |
XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1(11) |
XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2(16) |
XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3(22),
.bba_res_tune_lin_val_7_4_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4(31) |
XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5(44) |
XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6(62) |
XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7(42), /* Has 2 fractional bits unlike other BBA_RES_TUNE_LIN_VALs */
.bba_res_tune_lin_val_10_8_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8(128) |
XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9(188) |
XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10(288),
.dcoc_bba_step_init = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(939) |
XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(279),
.dcoc_tza_step_00_init = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(77) |
XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(3404),
.dcoc_tza_step_01_init = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(108) |
XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(2439),
.dcoc_tza_step_02_init = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(155) |
XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(1691),
.dcoc_tza_step_03_init = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(220) |
XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(1192),
.dcoc_tza_step_04_init = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(314) |
XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(835),
.dcoc_tza_step_05_init = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(436) |
XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(601),
.dcoc_tza_step_06_init = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(614) |
XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(427),
.dcoc_tza_step_07_init = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(845) |
XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(310),
.dcoc_tza_step_08_init = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(1256) |
XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(209),
.dcoc_tza_step_09_init = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(1805) |
XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(145),
.dcoc_tza_step_10_init = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(2653) |
XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(99),
#if (RADIO_IS_GEN_2P1)
.dcoc_cal_fail_th_init = XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_BETA_F_TH(20) |
XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_ALPHA_F_TH(10),
.dcoc_cal_pass_th_init = XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_BETA_P_TH(16) |
XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_ALPHA_P_TH(2),
#endif /* (RADIO_IS_GEN_2P1) */
/* AGC Configs */
.agc_gain_tbl_03_00_init = XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00(0) |
XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00(0) |
XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01(1) |
XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01(1) |
XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02(2) |
XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02(1) |
XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03(2) |
XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03(2),
.agc_gain_tbl_07_04_init = XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04(2) |
XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04(3) |
XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05(3) |
XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05(0) |
XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06(3) |
XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06(1) |
XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07(3) |
XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07(2),
.agc_gain_tbl_11_08_init = XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08(3) |
XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08(3) |
XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09(4) |
XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09(2) |
XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10(4) |
XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10(3) |
XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11(4) |
XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11(4),
.agc_gain_tbl_15_12_init = XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12(5) |
XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12(4) |
XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13(5) |
XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13(5) |
XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14(6) |
XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14(4) |
XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15(6) |
XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15(5),
.agc_gain_tbl_19_16_init = XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16(6) |
XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16(6) |
XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17(6) |
XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17(7) |
XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18(7) |
XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18(6) |
XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19(7) |
XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19(7),
.agc_gain_tbl_23_20_init = XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20(8) |
XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20(6) |
XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21(8) |
XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21(7) |
XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22(9) |
XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22(6) |
XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23(9) |
XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23(7),
.agc_gain_tbl_26_24_init = XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24(9) |
XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24(8) |
XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25(9) |
XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25(9) |
XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26(9) |
XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26(10),
.rssi_ctrl_0_init = XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS(1) |
XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC(0) |
XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN(1) |
XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(0) |
#if !RADIO_IS_GEN_2P1
XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG(1) |
#else
XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_NB(1) |
#endif /* !RADIO_IS_GEN_2P1 */
XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY(4) |
XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT(3) |
XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE(3) |
XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(0xE8) ,
.cca_ed_lqi_ctrl_0_init = XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH(0) |
XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH(0) |
XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR(0x1A) |
XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ(0),
.cca_ed_lqi_ctrl_1_init = XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY(0) |
XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR(0) |
XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT(0x4) |
XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS(0x7) |
XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS(0) |
#if !RADIO_IS_GEN_2P1
XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE(0) |
#endif /* !RADIO_IS_GEN_2P1 */
XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE(0) |
XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS(0) |
XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE(0) |
XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH(0) |
XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT(0x5) |
XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS(0x2),
/* XCVR_TSM configs */
.tsm_ctrl = XCVR_TSM_CTRL_PA_RAMP_SEL(PA_RAMP_SEL) |
XCVR_TSM_CTRL_DATA_PADDING_EN(DATA_PADDING_EN) |
XCVR_TSM_CTRL_TSM_IRQ0_EN(0) |
XCVR_TSM_CTRL_TSM_IRQ1_EN(0) |
XCVR_TSM_CTRL_RAMP_DN_DELAY(0x4) |
XCVR_TSM_CTRL_TX_ABORT_DIS(0) |
XCVR_TSM_CTRL_RX_ABORT_DIS(0) |
XCVR_TSM_CTRL_ABORT_ON_CTUNE(0) |
XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP(0) |
XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG(0) |
XCVR_TSM_CTRL_BKPT(0xFF) ,
.tsm_ovrd2_init = XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(0) | XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK,
.end_of_seq_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(END_OF_RX_WU_26MHZ) | B1(END_OF_TX_WD) | B0(END_OF_TX_WU),
.end_of_seq_init_32mhz = B3(END_OF_RX_WD) | B2(END_OF_RX_WU) | B1(END_OF_TX_WD) | B0(END_OF_TX_WU),
#if !RADIO_IS_GEN_2P1
.lpps_ctrl_init = B3(102) | B2(40) | B1(0) | B0(0),
#endif /* !RADIO_IS_GEN_2P1 */
.tsm_fast_ctrl2_init_26mhz = B3(102 + ADD_FOR_26MHZ) | B2(40 + ADD_FOR_26MHZ) | B1(66) | B0(8),
.tsm_fast_ctrl2_init_32mhz = B3(102) | B2(40) | B1(66) | B0(8),
.pa_ramp_tbl_0_init = XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0(PA_RAMP_0) | XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1(PA_RAMP_1) |
XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2(PA_RAMP_2) | XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3(PA_RAMP_3),
.pa_ramp_tbl_1_init = XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4(PA_RAMP_4) | XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5(PA_RAMP_5) |
XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6(PA_RAMP_6) | XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7(PA_RAMP_7),
.recycle_count_init_26mhz = B3(0) | B2(0x1C + ADD_FOR_26MHZ) | B1(0x06) | B0(0x66 + ADD_FOR_26MHZ),
.recycle_count_init_26mhz = B3(0) | B2(0x1C) | B1(0x06) | B0(0x66),
.tsm_timing_00_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_hf_en */
.tsm_timing_01_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_adcdac_en */
.tsm_timing_02_init = B3(END_OF_RX_WD) | B2(0x00) | B1(0xFF) | B0(0xFF), /* bb_ldo_bba_en */
.tsm_timing_03_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_pd_en */
.tsm_timing_04_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_fdbk_en */
.tsm_timing_05_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_vcolo_en */
.tsm_timing_06_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_vtref_en */
.tsm_timing_07_init = B3(0x05) | B2(0x00) | B1(0x05) | B0(0x00), /* bb_ldo_fdbk_bleed_en */
.tsm_timing_08_init = B3(0x03) | B2(0x00) | B1(0x03) | B0(0x00), /* bb_ldo_vcolo_bleed_en */
.tsm_timing_09_init = B3(0x03) | B2(0x00) | B1(0x03) | B0(0x00), /* bb_ldo_vcolo_fastcharge_en */
.tsm_timing_10_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* bb_xtal_pll_ref_clk_en */
.tsm_timing_11_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x03), /* bb_xtal_dac_ref_clk_en */
.tsm_timing_12_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_vco_ref_clk_en */
.tsm_timing_13_init = B3(0x18) | B2(0x00) | B1(0x4C) | B0(0x00), /* sy_vco_autotune_en */
.tsm_timing_14_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x31+ADD_FOR_26MHZ) | B1(END_OF_TX_WU + PD_CYCLE_SLIP_TX_LO_ADJ) | B0(0x63 + PD_CYCLE_SLIP_TX_HI_ADJ), /* sy_pd_cycle_slip_ld_ft_en */
.tsm_timing_14_init_32mhz = B3(END_OF_RX_WD) | B2(0x31 + AUX_PLL_DELAY) | B1(END_OF_TX_WU + PD_CYCLE_SLIP_TX_LO_ADJ) | B0(0x63 + PD_CYCLE_SLIP_TX_HI_ADJ),
.tsm_timing_15_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* sy_vco_en */
.tsm_timing_16_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1C + ADD_FOR_26MHZ) | B1(0xFF) | B0(0xFF), /* sy_lo_rx_buf_en */
.tsm_timing_16_init_32mhz = B3(END_OF_RX_WD) | B2(0x1C + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
.tsm_timing_17_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x55), /* sy_lo_tx_buf_en */
.tsm_timing_18_init = B3(END_OF_RX_WD) | B2(0x05 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x05), /* sy_divn_en */
.tsm_timing_19_init = B3(0x18+AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0x4C) | B0(0x03), /* sy_pd_filter_charge_en */
.tsm_timing_20_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* sy_pd_en */
.tsm_timing_21_init = B3(END_OF_RX_WD) | B2(0x04 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x04), /* sy_lo_divn_en */
.tsm_timing_22_init = B3(END_OF_RX_WD) | B2(0x04 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* sy_lo_rx_en */
.tsm_timing_23_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x04), /*sy_lo_tx_en */
.tsm_timing_24_init = B3(0x18) | B2(0x00) | B1(0x4C) | B0(0x00), /* sy_divn_cal_en */
.tsm_timing_25_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1D + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_lna_mixer_en */
.tsm_timing_25_init_32mhz = B3(END_OF_RX_WD) | B2(0x1D + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
.tsm_timing_26_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x58), /* tx_pa_en */
.tsm_timing_27_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_adc_i_q_en */
.tsm_timing_27_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
.tsm_timing_28_init_26mhz = B3(0x21 + ADD_FOR_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_adc_reset_en */
.tsm_timing_28_init_32mhz = B3(0x21 + AUX_PLL_DELAY) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
.tsm_timing_29_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1E + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_i_q_en */
.tsm_timing_29_init_32mhz = B3(END_OF_RX_WD) | B2(0x1E + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
.tsm_timing_30_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_pdet_en */
.tsm_timing_30_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
.tsm_timing_31_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1F + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_tza_dcoc_en */
.tsm_timing_31_init_32mhz = B3(END_OF_RX_WD) | B2(0x1F + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
.tsm_timing_32_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1D + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_tza_i_q_en */
.tsm_timing_32_init_32mhz = B3(END_OF_RX_WD) | B2(0x1D + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
.tsm_timing_33_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_tza_pdet_en */
.tsm_timing_33_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
.tsm_timing_34_init = B3(END_OF_RX_WD) | B2(0x07 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x07), /* pll_dig_en */
.tsm_timing_35_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD), /* tx_dig_en - Byte 0 comes from mode specific settings */
.tsm_timing_36_init_26mhz = B3(END_OF_RX_WD) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_dig_en */
.tsm_timing_36_init_32mhz = B3(END_OF_RX_WD) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
.tsm_timing_37_init_26mhz = B3(0x67 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_init */
.tsm_timing_37_init_32mhz = B3(0x67 + AUX_PLL_DELAY) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
.tsm_timing_38_init = B3(END_OF_RX_WD) | B2(0x0E + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x42), /* sigma_delta_en */
.tsm_timing_39_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_phy_en */
.tsm_timing_39_init_32mhz = B3(END_OF_RX_WD) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
.tsm_timing_40_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x26 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* dcoc_en */
.tsm_timing_40_init_32mhz = B3(END_OF_RX_WD) | B2(0x26 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
.tsm_timing_41_init_26mhz = B3(0x27 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x26 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* dcoc_init */
.tsm_timing_41_init_32mhz = B3(0x27 + AUX_PLL_DELAY) | B2(0x26 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
.tsm_timing_51_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_bias_en */
.tsm_timing_52_init_26mhz = B3(0x17 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x06 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_fcal_en */
.tsm_timing_52_init_32mhz = B3(0x17 + AUX_PLL_DELAY) | B2(0x06 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
.tsm_timing_53_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_lf_pd_en */
.tsm_timing_54_init_26mhz = B3(0x17 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x03 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_pd_lf_filter_charge_en */
.tsm_timing_54_init_32mhz = B3(0x17 + AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
.tsm_timing_55_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_adc_buf_en */
.tsm_timing_55_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
.tsm_timing_56_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_dig_buf_en */
.tsm_timing_56_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
.tsm_timing_57_init = B3(0x1A + AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /*rxtx_rccal_en */
.tsm_timing_58_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x03), /* tx_hpm_dac_en */
/* XCVR_TX_DIG configs */
#define radio_dft_mode 0
#define lfsr_length 4
#define lfsr_en 0
#define dft_clk_sel 4
#define tx_dft_en 0
#define soc_test_sel 0
#define tx_capture_pol 0
#define freq_word_adj 0
#define lrm 0
#define data_padding_pat_1 0x55
#define data_padding_pat_0 0xAA
#define gfsk_multiply_table_manual 0
#define gfsk_mi 1
#define gfsk_mld 0
#define gfsk_fld 0
#define gfsk_mod_index_scaling 0
#define tx_image_filter_ovrd_en 0
#define tx_image_filter_0_ovrd 0
#define tx_image_filter_1_ovrd 0
#define tx_image_filter_2_ovrd 0
#define gfsk_filter_coeff_manual2 0xC0630401
#define gfsk_filter_coeff_manual1 0xBB29960D
#define fsk_modulation_scale_0 0x1800
#define fsk_modulation_scale_1 0x0800
#define dft_mod_patternval 0
#define ctune_bist_go 0
#define ctune_bist_thrshld 0
#define pa_am_mod_freq 0
#define pa_am_mod_entries 0
#define pa_am_mod_en 0
#define syn_bist_go 0
#define syn_bist_all_channels 0
#define freq_count_threshold 0
#define hpm_inl_bist_go 0
#define hpm_dnl_bist_go 0
#define dft_max_ram_size 0
.tx_ctrl = XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(radio_dft_mode) |
XCVR_TX_DIG_CTRL_LFSR_LENGTH(lfsr_length) |
XCVR_TX_DIG_CTRL_LFSR_EN(lfsr_en) |
XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) |
XCVR_TX_DIG_CTRL_TX_DFT_EN(tx_dft_en) |
XCVR_TX_DIG_CTRL_SOC_TEST_SEL(soc_test_sel) |
XCVR_TX_DIG_CTRL_TX_CAPTURE_POL(tx_capture_pol) |
XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ(freq_word_adj),
/*-------------------------------------------------------------------------------------------------*/
.tx_data_padding = XCVR_TX_DIG_DATA_PADDING_LRM(lrm) |
XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1(data_padding_pat_1) |
XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0(data_padding_pat_0),
/*-------------------------------------------------------------------------------------------------*/
.tx_dft_pattern = XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN(dft_mod_patternval),
#if !RADIO_IS_GEN_2P1
/*-------------------------------------------------------------------------------------------------*/
.rf_dft_bist_1 = XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO(ctune_bist_go) |
XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD(ctune_bist_thrshld) |
XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ(pa_am_mod_freq) |
XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES(pa_am_mod_entries) |
XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN(pa_am_mod_en),
/*-------------------------------------------------------------------------------------------------*/
.rf_dft_bist_2 = XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO(syn_bist_go) |
XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS(syn_bist_all_channels) |
XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD(freq_count_threshold) |
XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO(hpm_inl_bist_go) |
XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO(hpm_dnl_bist_go) |
XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE(dft_max_ram_size),
#endif /* !RADIO_IS_GEN_2P1 */
};

353
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c Normal file
View File

@ -0,0 +1,353 @@
/*
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_xcvr.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
/* MODE only configuration */
const xcvr_mode_config_t gfsk_bt_0p3_h_0p5_mode_config =
{
.radio_mode = GFSK_BT_0p3_h_0p5,
.scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
/* XCVR_MISC configs */
.xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
.xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
/* XCVR_PHY configs */
.phy_pre_ref0_init = 0x7BCDEB39,
.phy_pre_ref1_init = 0xCEF7DEF7,
.phy_pre_ref2_init = 0x0000CEB7,
.phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) |
XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) |
XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
XCVR_PHY_CFG1_BSM_EN_BLE(0) |
XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
XCVR_PHY_CFG1_CTS_THRESH(0xda) |
XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
.phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
#if !RADIO_IS_GEN_2P1
| XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
#endif /* !RADIO_IS_GEN_2P1 */
,
/* XCVR_RX_DIG configs */
.rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
.rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
.agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
/* XCVR_TSM configs */
#if (DATA_PADDING_EN)
.tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
#else
.tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
#endif /* (DATA_PADDING_EN) */
/* XCVR_TX_DIG configs */
.tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(1) | /* Use GFSK Manual Filter Coeffs */
XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
.tx_gfsk_coeff1_26mhz = (107U) << 0 | /* coeff 2/13 */
(164U) << 7 | /* coeff 6/9 */
(125U) << 16 | /* coef 3/12 */
(169U) << 23, /* coeff 7/8 */
.tx_gfsk_coeff2_26mhz = (72U) << 0 | /* coeff 0/15 */
(90U) << 8 | /* coeff 1/14 */
(141U) << 16 | /* coeff 4/11 */
(155U) << 24, /* coeff 5/10 */
.tx_gfsk_coeff1_32mhz = (70U) << 0 | /* coeff 2/13 */
(216U) << 7 | /* coeff 6/9 */
(105U) << 16 | /* coef 3/12 */
(233U) << 23, /* coeff 7/8 */
.tx_gfsk_coeff2_32mhz = (25U) << 0 | /* coeff 0/15 */
(44U) << 8 | /* coeff 1/14 */
(145U) << 16 | /* coeff 4/11 */
(184U) << 24, /* coeff 5/10 */
};
/* MODE & DATA RATE combined configuration */
const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_1mbps_config =
{
.radio_mode = GFSK_BT_0p3_h_0p5,
.data_rate = DR_1MBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFF,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF9,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF4,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF2,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF5,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0000,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0011,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0028,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0041,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0055,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0061,
/* 32MHz Channel Filter */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFF,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFA,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF0,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF9,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x000B,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0025,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0043,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005C,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006A,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};
const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_500kbps_config =
{
.radio_mode = GFSK_BT_0p3_h_0p5,
.data_rate = DR_500KBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFC,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF7,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF3,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF2,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF9,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000A,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0023,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0040,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0068,
/* 32MHz Channel Filter */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0001,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFF,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF3,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEF,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF3,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0001,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x001D,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x003F,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0072,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};
const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_250kbps_config =
{
.radio_mode = GFSK_BT_0p3_h_0p5,
.data_rate = DR_250KBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0003,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFF,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF7,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEE,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFF7,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0014,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003C,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0064,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007D,
/* 32MHz Channel Filter */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0003,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE8,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEF,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x000B,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0068,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0086,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1),
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};

341
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c Normal file
View File

@ -0,0 +1,341 @@
/*
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_xcvr.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
/* MODE only configuration */
const xcvr_mode_config_t gfsk_bt_0p5_h_0p32_mode_config =
{
.radio_mode = GFSK_BT_0p5_h_0p32,
.scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
/* XCVR_MISC configs */
.xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
.xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
/* XCVR_PHY configs */
.phy_pre_ref0_init = 0xBBDE739B,
.phy_pre_ref1_init = 0xDEFBDEF7,
.phy_pre_ref2_init = 0x0000E739,
.phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) |
XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) |
XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
XCVR_PHY_CFG1_BSM_EN_BLE(0) |
XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
XCVR_PHY_CFG1_CTS_THRESH(0xF0) |
XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
.phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
#if !RADIO_IS_GEN_2P1
| XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
#endif /* !RADIO_IS_GEN_2P1 */
,
/* XCVR_RX_DIG configs */
.rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
.rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
.agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
/* XCVR_TSM configs */
#if (DATA_PADDING_EN)
.tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
#else
.tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
#endif /* (DATA_PADDING_EN) */
/* XCVR_TX_DIG configs */
.tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
.tx_gfsk_coeff1_26mhz = 0,
.tx_gfsk_coeff2_26mhz = 0,
.tx_gfsk_coeff1_32mhz = 0,
.tx_gfsk_coeff2_32mhz = 0,
};
/* MODE & DATA RATE combined configuration */
const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_1mbps_config =
{
.radio_mode = GFSK_BT_0p5_h_0p32,
.data_rate = DR_1MBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(14) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFB,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF5,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF0,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEC,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF3,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0001,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0016,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0049,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0069,
/* 32MHz Channel Filter */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFF9,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF4,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFED,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFE7,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFE7,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEE,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFFD,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0031,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004E,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0066,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0073,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};
const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_500kbps_config =
{
.radio_mode = GFSK_BT_0p5_h_0p32,
.data_rate = DR_500KBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFA,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF3,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEE,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEF,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF8,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000A,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0025,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0043,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x006B,
/* 32MHz Channel Filter */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0004,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFE,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF6,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFED,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFEF,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0001,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0020,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0044,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0064,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0077,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};
const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_250kbps_config =
{
.radio_mode = GFSK_BT_0p5_h_0p32,
.data_rate = DR_250KBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF1,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF7,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000B,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0027,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0060,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070,
/* 32MHz Channel Filter */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0003,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE8,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEF,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x000B,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0068,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0086,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};

356
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c Normal file
View File

@ -0,0 +1,356 @@
/*
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_xcvr.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
/* MODE only configuration */
const xcvr_mode_config_t gfsk_bt_0p5_h_0p5_mode_config =
{
.radio_mode = GFSK_BT_0p5_h_0p5,
.scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
/* XCVR_MISC configs */
.xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
.xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
.phy_pre_ref0_init = RW0PS(0, 0x19) |
RW0PS(1, 0x19U) |
RW0PS(2, 0x1AU) |
RW0PS(3, 0x1BU) |
RW0PS(4, 0x1CU) |
RW0PS(5, 0x1CU) |
RW0PS(6, 0x1DU & 0x3U), /* Phase info #6 overlaps two initialization words */
.phy_pre_ref1_init = (0x1D) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift*/
RW1PS(7, 0x1EU) |
RW1PS(8, 0x1EU) |
RW1PS(9, 0x1EU) |
RW1PS(10, 0x1DU) |
RW1PS(11, 0x1CU) |
RW1PS(12, 0x1CU & 0xFU), /* Phase info #12 overlaps two initialization words */
.phy_pre_ref2_init = (0x1C) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift*/
RW2PS(13, 0x1BU) |
RW2PS(14, 0x1AU) |
RW2PS(15, 0x19U),
.phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) |
XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) |
XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
XCVR_PHY_CFG1_BSM_EN_BLE(0) |
XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
XCVR_PHY_CFG1_CTS_THRESH(205) |
XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
.phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
#if !RADIO_IS_GEN_2P1
| XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
#endif /* !RADIO_IS_GEN_2P1 */
,
/* XCVR_RX_DIG configs */
.rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
.rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
.agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
/* XCVR_TSM configs */
#if (DATA_PADDING_EN)
.tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
#else
.tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
#endif /* (DATA_PADDING_EN) */
/* XCVR_TX_DIG configs */
.tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
.tx_gfsk_coeff1_26mhz = 0,
.tx_gfsk_coeff2_26mhz = 0,
.tx_gfsk_coeff1_32mhz = 0,
.tx_gfsk_coeff2_32mhz = 0,
};
/* MODE & DATA RATE combined configuration */
const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_1mbps_config =
{
.radio_mode = GFSK_BT_0p5_h_0p5,
.data_rate = DR_1MBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* BLE 26MHz Channel Filter */
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFA,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF6,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF1,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEE,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEF,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF6,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0004,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0017,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0063,
/* BLE 32MHz Channel Filter */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF5,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFEF,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEB,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEB,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x0000,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0030,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004A,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006B,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};
const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_500kbps_config =
{
.radio_mode = GFSK_BT_0p5_h_0p5,
.data_rate = DR_500KBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0004,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFE,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF5,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFE8,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEE,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0001,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0020,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0045,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0065,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0079,
/* 32MHz */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0005,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0006,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0003,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEF,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE6,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE7,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF8,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0019,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0042,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0080,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};
const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_250kbps_config =
{
.radio_mode = GFSK_BT_0p5_h_0p5,
.data_rate = DR_250KBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF1,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF7,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000B,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0027,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0060,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070,
/* 32MHz Channel Filter */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFD,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFF8,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF1,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEC,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFED,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF6,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x000A,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0027,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0046,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0061,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0071,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};

341
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c Normal file
View File

@ -0,0 +1,341 @@
/*
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_xcvr.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
/* MODE only configuration */
const xcvr_mode_config_t gfsk_bt_0p5_h_0p7_mode_config =
{
.radio_mode = GFSK_BT_0p5_h_0p7,
.scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
/* XCVR_MISC configs */
.xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
.xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
/* XCVR_PHY configs */
.phy_pre_ref0_init = 0x37ACE2F7,
.phy_pre_ref1_init = 0xADF3BDEF,
.phy_pre_ref2_init = 0x0000BE33,
.phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) |
XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) |
XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
XCVR_PHY_CFG1_BSM_EN_BLE(0) |
XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
XCVR_PHY_CFG1_CTS_THRESH(0xCD) |
XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
.phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
#if !RADIO_IS_GEN_2P1
| XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
#endif /* !RADIO_IS_GEN_2P1 */
,
/* XCVR_RX_DIG configs */
.rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
.rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
.agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
/* XCVR_TSM configs */
#if (DATA_PADDING_EN)
.tsm_timing_35_init = B0(TX_DIG_EN_ASSERT + TX_DIG_EN_TX_HI_ADJ),
#else
.tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
#endif /* (DATA_PADDING_EN) */
/* XCVR_TX_DIG configs */
.tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(2) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
.tx_gfsk_coeff1_26mhz = 0,
.tx_gfsk_coeff2_26mhz = 0,
.tx_gfsk_coeff1_32mhz = 0,
.tx_gfsk_coeff2_32mhz = 0,
};
/* MODE & DATA RATE combined configuration */
const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_1mbps_config =
{
.radio_mode = GFSK_BT_0p5_h_0p7,
.data_rate = DR_1MBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /* TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0002,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0000,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF9,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF0,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEA,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFFC,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x001B,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0042,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0066,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007C,
/* 32MHz Channel Filter */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0002,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFC,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE9,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF7,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0016,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0040,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0082,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};
const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_500kbps_config =
{
.radio_mode = GFSK_BT_0p5_h_0p7,
.data_rate = DR_500KBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0005,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0001,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF6,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFE8,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEC,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x000C,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003D,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008F,
/* 32MHz Channel Filter */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0004,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0007,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0006,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEC,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFDF,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE3,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0002,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0072,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};
const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config =
{
.radio_mode = GFSK_BT_0p5_h_0p7,
.data_rate = DR_250KBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0000,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFE,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF1,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE6,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEA,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0036,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006B,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008D,
/* 32MHz Channel Filter */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0000,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0004,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0004,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF8,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE6,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE2,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x002E,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x006D,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};

340
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c Normal file
View File

@ -0,0 +1,340 @@
/*
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_xcvr.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
/* MODE only configuration */
const xcvr_mode_config_t gfsk_bt_0p5_h_1p0_mode_config =
{
.radio_mode = GFSK_BT_0p5_h_1p0,
.scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
/* XCVR_MISC configs */
.xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
.xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
/* XCVR_PHY configs */
.phy_pre_ref0_init = 0xF38B5273,
.phy_pre_ref1_init = 0x8CEF9CE6,
.phy_pre_ref2_init = 0x00009D2D,
.phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) |
XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) |
XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
XCVR_PHY_CFG1_BSM_EN_BLE(0) |
XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
XCVR_PHY_CFG1_CTS_THRESH(0xb0) |
XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
.phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
#if !RADIO_IS_GEN_2P1
| XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
#endif /* !RADIO_IS_GEN_2P1 */
,
/* XCVR_RX_DIG configs */
.rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
.rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
.agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
/* XCVR_TSM configs */
#if (DATA_PADDING_EN)
.tsm_timing_35_init = B0(TX_DIG_EN_ASSERT + TX_DIG_EN_TX_HI_ADJ),
#else
.tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
#endif /* (DATA_PADDING_EN) */
/* XCVR_TX_DIG configs */
.tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(3) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
.tx_gfsk_coeff1_26mhz = 0,
.tx_gfsk_coeff2_26mhz = 0,
.tx_gfsk_coeff1_32mhz = 0,
.tx_gfsk_coeff2_32mhz = 0,
};
/* MODE & DATA RATE combined configuration */
const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_1mbps_config =
{
.radio_mode = GFSK_BT_0p5_h_1p0,
.data_rate = DR_1MBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /* TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0003,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF9,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEB,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFE9,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0008,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003A,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0090,
/* 32MHz Channel Filter */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0000,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0007,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0000,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE0,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE1,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFD,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0034,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0072,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x009A,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};
const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_500kbps_config =
{
.radio_mode = GFSK_BT_0p5_h_1p0,
.data_rate = DR_500KBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFD,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFEA,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF3,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0021,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x0013,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFC9,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEE,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x005E,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0004,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFF4E,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0xFFFC,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x018F,
/* 32MHz Channel Filter */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0012,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0011,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFE1,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEE,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0034,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFFD,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFB7,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x003B,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x004F,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFF5B,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0xFFB5,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x018B,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};
const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_250kbps_config =
{
.radio_mode = GFSK_BT_0p5_h_1p0,
.data_rate = DR_250KBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFE,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x000C,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0011,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000B,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF8,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE0,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFD7,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFF0,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x002A,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x009E,
/* 32MHz Channel Filter */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF9,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0000,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x000F,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0019,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x000C,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFEB,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFCD,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFD7,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0017,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0075,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00BB,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};

353
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c Normal file
View File

@ -0,0 +1,353 @@
/*
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_xcvr.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
/* MODE only configuration */
const xcvr_mode_config_t gfsk_bt_0p7_h_0p5_mode_config =
{
.radio_mode = GFSK_BT_0p7_h_0p5,
.scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
/* XCVR_MISC configs */
.xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
.xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
/* XCVR_PHY configs */
.phy_pre_ref0_init = 0x79CDEB39,
.phy_pre_ref1_init = 0xCE77DEF7,
.phy_pre_ref2_init = 0x0000CEB7,
.phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) |
XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) |
XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
XCVR_PHY_CFG1_BSM_EN_BLE(0) |
XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
XCVR_PHY_CFG1_CTS_THRESH(0xb0) |
XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
.phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
#if !RADIO_IS_GEN_2P1
| XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
#endif /* !RADIO_IS_GEN_2P1 */
,
/* XCVR_RX_DIG configs */
.rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
.rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
.agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
/* XCVR_TSM configs */
#if (DATA_PADDING_EN)
.tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
#else
.tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
#endif /* (DATA_PADDING_EN) */
/* XCVR_TX_DIG configs */
.tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(1) | /* Use GFSK Manual Filter Coeffs */
XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
.tx_gfsk_coeff1_26mhz = (27U) << 0 | /* Coeff 2/13 */
(276U) << 7 | /* Coeff 6/9 */
(62U) << 16 | /* Coef 3/12 */
(326U) << 23, /* Coeff 7/8 */
.tx_gfsk_coeff2_26mhz = (3U) << 0 | /* Coeff 0/15 */
(10U) << 8 | /* Coeff 1/14 */
(121U) << 16 | /* Coeff 4/11 */
(198U) << 24, /* Coeff 5/10 */
.tx_gfsk_coeff1_32mhz = (1U) << 0 | /* Coeff 2/13 */
(330U) << 7 | /* Coeff 6/9 */
(7U) << 16 | /* Coef 3/12 */
(510U) << 23, /* Coeff 7/8 */
.tx_gfsk_coeff2_32mhz = (0U) << 0 | /* Coeff 0/15 */
(0U) << 8 | /* Coeff 1/14 */
(37U) << 16 | /* Coeff 4/11 */
(138U) << 24, /* Coeff 5/10 */
};
/* MODE & DATA RATE combined configuration */
const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_1mbps_config =
{
.radio_mode = GFSK_BT_0p7_h_0p5,
.data_rate = DR_1MBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFE,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF8,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF1,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEF,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF4,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0004,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0020,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0041,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005E,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070,
/* 32MHz Channel Filter */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0002,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0000,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEB,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFED,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFFD,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x001B,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0041,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0065,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x007A,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};
const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_500kbps_config =
{
.radio_mode = GFSK_BT_0p7_h_0p5,
.data_rate = DR_500KBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFA,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0019,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0009,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFDB,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFC1,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFFF6,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0072,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00DD,
/* 32MHz Channel Filter */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFC,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFD,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x0016,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001A,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEC,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFBC,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFE0,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00ED,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};
const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config =
{
.radio_mode = GFSK_BT_0p7_h_0p5,
.data_rate = DR_250KBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0000,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFE,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF1,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE6,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEA,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0036,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006B,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008D,
/* 32MHz Channel Filter */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0000,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0004,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0004,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF8,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE6,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE2,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x002E,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x006D,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};

212
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_mode_datarate_config.c Normal file
View File

@ -0,0 +1,212 @@
/*
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_xcvr.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
/* ========================= DATA RATE ONLY settings ===============*/
/*!
* @brief XCVR 1Mbps DATA RATE specific configure structure
*/
const xcvr_datarate_config_t xcvr_1mbps_config =
{
.data_rate = DR_1MBPS,
.phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0xF) |
#if !RADIO_IS_GEN_2P1
XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) |
#endif /* !RADIO_IS_GEN_2P1 */
XCVR_PHY_EL_CFG_EL_INTERVAL(0x20) ,
.rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(0) |
XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16),
.rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) |
XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16),
.agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(10) |
XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA),
.agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(12) |
XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA),
.dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(10) |
XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(21),
.dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(12) |
XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(26),
.dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(3) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(3),
.dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(3) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(3),
.dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) |
XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) |
XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2),
.dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) |
XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(3) |
XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2),
.dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(33) |
XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(6),
.dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(40) |
XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(7),
};
/*!
* @brief XCVR 500K bps DATA RATE specific configure structure
*/
const xcvr_datarate_config_t xcvr_500kbps_config =
{
.data_rate = DR_500KBPS,
.phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x8) |
#if !RADIO_IS_GEN_2P1
XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) |
#endif /* !RADIO_IS_GEN_2P1 */
XCVR_PHY_EL_CFG_EL_INTERVAL(0x10),
.rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) |
XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16),
.rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) |
XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16),
.agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(15) |
XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA),
.agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(18) |
XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA),
.dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(13) |
XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(29),
.dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(16) |
XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(36),
.dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2),
.dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2),
.dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) |
XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) |
XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2),
.dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) |
XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) |
XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2),
.dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(26) |
XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4),
.dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(32) |
XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4),
};
/*!
* @brief XCVR 250K bps DATA RATE specific configure structure
*/
const xcvr_datarate_config_t xcvr_250kbps_config =
{
.data_rate = DR_250KBPS,
.phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x4) |
#if !RADIO_IS_GEN_2P1
XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) |
#endif /* !RADIO_IS_GEN_2P1 */
XCVR_PHY_EL_CFG_EL_INTERVAL(0x8) ,
.rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) |
XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16),
.rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(4) |
XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16),
.agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(18) |
XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA),
.agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(22) |
XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA),
.dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(16) |
XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(34),
.dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(20) |
XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(42),
.dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(1) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2),
.dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(1) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2),
.dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(0) |
XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(1) |
XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1),
.dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(0) |
XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(1) |
XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1),
.dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(13) |
XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4),
.dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(16) |
XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4),
};

343
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_msk_config.c Normal file
View File

@ -0,0 +1,343 @@
/*
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_xcvr.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
/* MODE only configuration */
const xcvr_mode_config_t msk_mode_config =
{
.radio_mode = MSK,
.scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
/* XCVR_MISC configs */
.xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
.xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(9) |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(4) |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
/* XCVR_PHY configs */
.phy_pre_ref0_init = 0x79CDEB38,
.phy_pre_ref1_init = 0xCE77DFF7,
.phy_pre_ref2_init = 0x0000CEB7,
.phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) |
XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) |
XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
XCVR_PHY_CFG1_BSM_EN_BLE(0) |
XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
XCVR_PHY_CFG1_CTS_THRESH(208U) |
XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
.phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
#if !RADIO_IS_GEN_2P1
| XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
#endif /* !RADIO_IS_GEN_2P1 */
,
/* XCVR_RX_DIG configs */
.rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
.rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
.agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
/* XCVR_TSM configs */
#if (DATA_PADDING_EN)
.tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
#else
.tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
#endif /* (DATA_PADDING_EN) */
/* XCVR_TX_DIG configs */
.tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
.tx_gfsk_coeff1_26mhz = 0,
.tx_gfsk_coeff2_26mhz = 0,
.tx_gfsk_coeff1_32mhz = 0,
.tx_gfsk_coeff2_32mhz = 0,
};
/* MODE & DATA RATE combined configuration */
const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config =
{
.radio_mode = MSK,
.data_rate = DR_1MBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
/* MSK 1MBPS channel filter @ 26MHz RF OSC */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0002,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0000,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF9,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF0,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEA,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFFC,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x001B,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0042,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0066,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007C,
/* MSK 1MBPS channel filter @ 32MHz RF OSC */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0002,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFC,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE9,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF7,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0016,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0040,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0082,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};
const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config =
{
.radio_mode = MSK,
.data_rate = DR_500KBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xa) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
/* MSK 500KBPS channel filter @ 26MHz RF OSC */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFC,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFE7,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0038,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0092,
/* MSK 500KBPS channel filter @ 32MHz RF OSC */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0002,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0006,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0009,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0003,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF3,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE2,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE0,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0031,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0071,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x009C,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};
const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config =
{
.radio_mode = MSK,
.data_rate = DR_250KBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFA,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0019,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0009,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFDB,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFC1,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFFF6,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0072,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00DD,
/* MSK 250KBPS channel filter @ 32MHz RF OSC */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFC,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFD,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x0016,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001A,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEC,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFBC,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFE0,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00ED,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};

244
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_zgbe_config.c Normal file
View File

@ -0,0 +1,244 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_xcvr.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
const xcvr_mode_config_t zgbe_mode_config =
{
.radio_mode = ZIGBEE_MODE,
.scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_ZigBee_MASK,
/* XCVR_MISC configs */
.xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
.xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(4) |
XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) |
XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(2),
/* XCVR_PHY configs */
.phy_pre_ref0_init = 0x0, /* Not used in Zigbee */
.phy_pre_ref1_init = 0x0, /* Not used in Zigbee */
.phy_pre_ref2_init = 0x0, /* Not used in Zigbee */
.phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) |
XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) |
XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
XCVR_PHY_CFG1_BSM_EN_BLE(0) |
XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
XCVR_PHY_CFG1_CTS_THRESH(0xC0) |
XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
.phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
#if !RADIO_IS_GEN_2P1
| XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
#endif /* !RADIO_IS_GEN_2P1 */
,
/* XCVR_PLL_DIG configs */
/* XCVR_RX_DIG configs */
.rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(1) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
.rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(1) | /* Depends on protocol */
XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
.agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
/* XCVR_TSM configs */
#if (DATA_PADDING_EN)
.tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+ZGBE_TX_DIG_EN_TX_HI_ADJ), /* DATA_PADDING adjustments are specified relative to the non-Zigbee base timing */
#else
.tsm_timing_35_init = B0(ZGBE_TX_DIG_EN_ASSERT),
#endif /* (DATA_PADDING_EN) */
/* XCVR_TX_DIG configs */
.tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) |
XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0) ,
.tx_gfsk_coeff1_26mhz = 0,
.tx_gfsk_coeff2_26mhz = 0,
.tx_gfsk_coeff1_32mhz = 0,
.tx_gfsk_coeff2_32mhz = 0,
};
const xcvr_mode_datarate_config_t xcvr_ZIGBEE_500kbps_config =
{
.radio_mode = ZIGBEE_MODE,
.data_rate = DR_500KBPS,
.ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
.ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */
.ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
.ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(1) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(1), /* BBA_BW_SEL and BBA2_BW_SEL */
.ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
.ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(1), /*TZA_BW_SEL */
.phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) ,
/* AGC configs */
.agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(8) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
.agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) |
XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
/* All constant values are represented as 16 bits, register writes will remove unused bits */
.rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFF,
.rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF,
.rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0002,
.rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0008,
.rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A,
.rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0000,
.rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE8,
.rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFD7,
.rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFE6,
.rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0022,
.rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0075,
.rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00B2,
/* IEEE 802.15.4 32MHz Channel Filter -- 1.55/1.25/5/0.97/B5 */
.rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF,
.rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFF,
.rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005,
.rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0004,
.rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2,
.rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2,
.rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001D,
.rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0025,
.rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFCE,
.rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFA1,
.rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0040,
.rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0124,
.rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
.rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
.tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
.tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
};
/* CUSTOM datarate dependent config structure for ONLY 802.15.4 */
/*!
* @brief XCVR 500K bps DATA RATE specific configure structure
*/
const xcvr_datarate_config_t xcvr_802_15_4_500kbps_config =
{
.data_rate = DR_500KBPS,
.phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) |
XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x8) |
XCVR_PHY_EL_CFG_EL_INTERVAL(0x10) ,
.rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) |
XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16),
.rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) |
XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16),
.agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(13) |
XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA),
.agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(10) |
XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA),
.dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(13) |
XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(29),
.dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(21) |
XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(47),
.dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2),
.dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) |
XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2),
.dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) |
XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) |
XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2),
.dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(1) |
XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) |
XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1),
.dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(26) |
XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4),
.dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(48) |
XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(0),
};

160
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/dbg_ram_capture.c Normal file
View File

@ -0,0 +1,160 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_device_registers.h"
#include "fsl_xcvr.h"
#include "dbg_ram_capture.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#if RADIO_IS_GEN_3P0
#define PKT_RAM_SIZE_16B_WORDS (1152) /* Number of 16bit entries in each Packet RAM bank */
#else
#define PKT_RAM_SIZE_16B_WORDS (544) /* Number of 16bit entries in each Packet RAM bank */
#endif /* RADIO_IS_GEN_3P0 */
#define SIGN_EXTND_12_16(x) ((x) | (((x) & 0x800) ? 0xF000 : 0x0))
#define SIGN_EXTND_5_8(x) ((x) | (((x) & 0x10) ? 0xE0 : 0x0))
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
void dbg_ram_init(void)
{
XCVR_RX_DIG->RX_DIG_CTRL |= XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK; /* Turns on clocking to DMA/DBG blocks */
XCVR_MISC->PACKET_RAM_CTRL |= XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK; /* Make PKT RAM available to just XCVR */
/* Some external code must perform the RX warmup request. */
}
dbgRamStatus_t dbg_ram_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer)
{
dbgRamStatus_t status = DBG_RAM_SUCCESS;
uint32_t temp;
volatile uint8_t *pkt_ram_ptr0, *pkt_ram_ptr1;
uint8_t * output_ptr;
uint16_t i;
/* Some external code must perform the RX warmup request after the dbg_ram_init() call */
if (result_buffer == NULL)
{
status = DBG_RAM_FAIL_NULL_POINTER;
}
else
{
if (buffer_sz_bytes > (544*2*2))
{
status = DBG_RAM_FAIL_SAMPLE_NUM_LIMIT;
}
else
{
temp = XCVR_MISC->PACKET_RAM_CTRL & ~XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK;
switch (dbg_page)
{
case DBG_PAGE_RXDIGIQ:
case DBG_PAGE_RAWADCIQ:
case DBG_PAGE_DCESTIQ:
XCVR_MISC->PACKET_RAM_CTRL = temp | XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(dbg_page);
while (!(XCVR_MISC->PACKET_RAM_CTRL & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(2)))
{
/* Waiting for PKT_RAM to fill, wait for PKT_RAM_1 full to ensure complete memory is filled. */
}
/* Copy to output by bytes to avoid any access size problems in 16 bit packet RAM. */
output_ptr = result_buffer;
#if !RADIO_IS_GEN_2P1
pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_0[0]);
pkt_ram_ptr1 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_1[0]);
#else
pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[0]);
pkt_ram_ptr1 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[XCVR_PKT_RAM_PACKET_RAM_COUNT>>1]); /* Second packet RAM starts halfway through */
#endif /* !RADIO_IS_GEN_2P1 */
/* For *IQ pages I and Q are stored alternately in packet ram 0 & 1 */
for (i = 0; i < buffer_sz_bytes / 4; i++)
{
*output_ptr++ = *pkt_ram_ptr0++;
*output_ptr++ = *pkt_ram_ptr0++;
*output_ptr++ = *pkt_ram_ptr1++;
*output_ptr++ = *pkt_ram_ptr1++;
}
break;
case DBG_PAGE_RXINPH:
case DBG_PAGE_DEMOD_HARD:
case DBG_PAGE_DEMOD_SOFT:
case DBG_PAGE_DEMOD_DATA:
case DBG_PAGE_DEMOD_CFO_PH:
XCVR_MISC->PACKET_RAM_CTRL = temp | XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(dbg_page);
while (!(XCVR_MISC->PACKET_RAM_CTRL & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(2)))
{
/* Waiting for PKT_RAM to fill, wait for PKT_RAM_1 full to ensure complete memory is filled. */
}
/* Copy to output by bytes to avoid any access size problems in 16 bit packet RAM. */
output_ptr = result_buffer;
#if !RADIO_IS_GEN_2P1
pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_0[0]);
#else
pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[0]);
#endif /* !RADIO_IS_GEN_2P1 */
/* This is for non I/Q */
for (i = 0; i < buffer_sz_bytes; i++)
{
*output_ptr = *pkt_ram_ptr0;
pkt_ram_ptr0++;
output_ptr++;
}
break;
case DBG_PAGE_IDLE:
default:
status = DBG_RAM_FAIL_PAGE_ERROR; /* Illegal capture page request. */
break;
}
}
}
XCVR_MISC->PACKET_RAM_CTRL &= ~XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK; /* Clear DBG_PAGE to terminate the acquisition */
/* Process the samples and copy to output pointer */
XCVR_MISC->PACKET_RAM_CTRL &= ~XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK; /* Make PKT RAM available to protocol blocks */
XCVR_RX_DIG->RX_DIG_CTRL &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK; /* Turns off clocking to DMA/DBG blocks */
return status;
}

206
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/dbg_ram_capture.h Normal file
View File

@ -0,0 +1,206 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _DBG_RAM_CAPTURE_H_
/* clang-format off */
#define _DBG_RAM_CAPTURE_H_
/* clang-format on */
#include "fsl_common.h"
#include "fsl_device_registers.h"
/*!
* @addtogroup xcvr
* @{
*/
/*! @file*/
/*******************************************************************************
* Definitions
******************************************************************************/
/* Page definitions */
#define DBG_PAGE_IDLE (0x00)
#define DBG_PAGE_RXDIGIQ (0x01)
#define DBG_PAGE_RAWADCIQ (0x04)
#define DBG_PAGE_DCESTIQ (0x07)
#define DBG_PAGE_RXINPH (0x0A)
#define DBG_PAGE_DEMOD_HARD (0x0B)
#define DBG_PAGE_DEMOD_SOFT (0x0C)
#define DBG_PAGE_DEMOD_DATA (0x0D)
#define DBG_PAGE_DEMOD_CFO_PH (0x0E)
typedef enum _dbgRamStatus
{
DBG_RAM_SUCCESS = 0,
DBG_RAM_FAIL_SAMPLE_NUM_LIMIT = 1,
DBG_RAM_FAIL_PAGE_ERROR = 2,
DBG_RAM_FAIL_NULL_POINTER = 3,
DBG_RAM_INVALID_TRIG_SETTING = 4,
DBG_RAM_FAIL_NOT_ENOUGH_SAMPLES = 5,
DBG_RAM_CAPTURE_NOT_COMPLETE = 6, /* Not an error response, but an indication that capture isn't complete for status polling */
} dbgRamStatus_t;
#if RADIO_IS_GEN_3P0
typedef enum _dbgRamStartTriggerType
{
NO_START_TRIG = 0,
START_ON_FSK_PREAMBLE_FOUND = 1,
START_ON_FSK_AA_MATCH = 2,
START_ON_ZBDEMOD_PREAMBLE_FOUND = 3,
START_ON_ZBDEMOD_SFD_MATCH = 4,
START_ON_AGC_DCOC_GAIN_CHG = 5,
START_ON_TSM_RX_DIG_EN = 6,
START_ON_TSM_SPARE2_EN = 7,
INVALID_START_TRIG = 8
} dbgRamStartTriggerType;
typedef enum _dbgRamStopTriggerType
{
NO_STOP_TRIG = 0,
STOP_ON_FSK_PREAMBLE_FOUND = 1,
STOP_ON_FSK_AA_MATCH = 2,
STOP_ON_ZBDEMOD_PREAMBLE_FOUND = 3,
STOP_ON_ZBDEMOD_SFD_MATCH = 4,
STOP_ON_AGC_DCOC_GAIN_CHG = 5,
STOP_ON_TSM_RX_DIG_EN = 6,
STOP_ON_TSM_SPARE3_EN = 7,
STOP_ON_TSM_PLL_UNLOCK = 8,
STOP_ON_BLE_CRC_ERROR_INC = 9,
STOP_ON_CRC_FAIL_ZGBE_GENFSK = 10,
STOP_ON_GENFSK_HEADER_FAIL = 11,
INVALID_STOP_TRIG = 12
} dbgRamStopTriggerType;
#endif /* RADIO_IS_GEN_3P0 */
/*! *********************************************************************************
* \brief This function prepares for sample capture to packet RAM.
*
* \return None.
*
* \details
* This routine assumes that some other functions in the calling routine both set
* the channel and force RX warmup before calling ::dbg_ram_capture().
***********************************************************************************/
void dbg_ram_init(void);
/*! *********************************************************************************
* \brief This function performs any state restoration at the completion of PKT RAM capture.
*
* \details
* Any clocks enabled to the packet RAM capture circuitry are disabled.
***********************************************************************************/
void dbg_ram_release(void);
#if RADIO_IS_GEN_3P0
/*! *********************************************************************************
* \brief This function initiates the capture of transceiver data to the transceiver packet RAM.
*
* \param[in] dbg_page - The page selector (DBG_PAGE).
* \param[in] dbg_start_trigger - The trigger to start acquisition (must be "no trigger" if a stop trigger is enabled).
* \param[in] dbg_stop_trigger - The trigger to stop acquisition (must be "no trigger" if a start trigger is enabled).
*
* \return Status of the request.
*
* \details
* This function starts the process of capturing data to the packet RAM. Depending upon the start and stop trigger
* settings, the actual capture process can take an indeterminate amount of time. Other APIs are provided to
* perform a blocking wait for completion or allow polling for completion of the capture.
* After any capture has completed, a separate routine must be called to postprocess the capture and copy all
* data out of the packet RAM into a normal RAM buffer.
***********************************************************************************/
dbgRamStatus_t dbg_ram_start_capture(uint8_t dbg_page, dbgRamStartTriggerType start_trig, dbgRamStopTriggerType stop_trig);
/*! *********************************************************************************
* \brief This function performs a blocking wait for completion of the capture of transceiver data to the transceiver packet RAM.
*
* \return Status of the request, DBG_RAM_SUCCESS if capture is complete.
*
* \details
* This function performs a wait loop for capture completion and may take an indeterminate amount of time for
* some capture trigger types.
***********************************************************************************/
dbgRamStatus_t dbg_ram_wait_for_complete(void); /* Blocking wait for capture completion, no matter what trigger type */
/*! *********************************************************************************
* \brief This function polls the state of the capture of transceiver data to the transceiver packet RAM.
*
* \return Status of the request, DBG_RAM_SUCCESS if capture is complete, DBG_RAM_CAPTURE_NOT_COMPLETE if not complete.
*
***********************************************************************************/
dbgRamStatus_t dbg_ram_poll_capture_status(void); /* Non-blocking completion check, just reads the current status of the capure */
/*! *********************************************************************************
* \brief This function processes the captured data into a usable order and copies from packet RAM to normal RAM.
*
* \param[in] dbg_page - The page selector (DBG_PAGE).
* \param[in] buffer_sz_bytes - The size of the output buffer (in bytes)
* \param[in] result_buffer - The pointer to the output buffer of a size large enough for the samples.
*
* \return None.
*
* \details
* Data is copied from packet RAM in bytes to ensure no access problems. Data is unpacked from packet RAM
* (either sequentially captured or simultaneously captured) into a linear RAM buffer in system RAM.
* If a start trigger is enabled then the first buffer_sz_bytes that are captured are copied out.
* If a stop trigger is enabled then the last buffer_sz_bytes that are captured are copied out.
***********************************************************************************/
dbgRamStatus_t dbg_ram_postproc_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer); /* postprocess a capture to unpack data */
#else
/*! *********************************************************************************
* \brief This function captures transceiver data to the transceiver packet RAM.
*
* \param[in] dbg_page - The page selector (DBG_PAGE).
* \param[in] buffer_sz_bytes - The size of the output buffer (in bytes)
* \param[in] result_buffer - The pointer to the output buffer of a size large enough for the samples.
*
* \return None.
*
* \details
* The capture to packet RAM always captures a full PKT_RAM worth of samples. The samples will be
* copied to the buffer pointed to by result_buffer parameter until buffer_sz_bytes worth of data have
* been copied. Data will be copied
* NOTE: This routine has a slight hazard of getting stuck waiting for debug RAM to fill up when RX has
* not been enabled or RX ends before the RAM fills up (such as when capturing packet data ). It is
* intended to be used with manually triggered RX where RX data will continue as long as needed.
***********************************************************************************/
dbgRamStatus_t dbg_ram_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer);
#endif /* RADIO_IS_GEN_3P0 */
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* _DBG_RAM_CAPTURE_H_ */

2123
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/fsl_xcvr.c Normal file
View File

File diff suppressed because it is too large Load Diff

1236
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/fsl_xcvr.h Normal file
View File

File diff suppressed because it is too large Load Diff

995
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/fsl_xcvr_trim.c Normal file
View File

@ -0,0 +1,995 @@
/*
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_device_registers.h"
#include "fsl_common.h"
#include "fsl_xcvr.h"
#include "fsl_xcvr_trim.h"
#include "dbg_ram_capture.h"
#include "math.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
void DC_Measure_short(IQ_t chan, DAC_SWEEP_STEP2_t dcoc_init_val);
float calc_dcoc_dac_step(GAIN_CALC_TBL_ENTRY2_T * meas_ptr, GAIN_CALC_TBL_ENTRY2_T * baseline_meas_ptr );
extern float roundf (float);
/*******************************************************************************
* Variables
******************************************************************************/
const int8_t TsettleCal = 10;
static GAIN_CALC_TBL_ENTRY2_T measurement_tbl2[NUM_I_Q_CHAN][NUM_SWEEP_STEP_ENTRIES2];
static const int8_t sweep_step_values2[NUM_SWEEP_STEP_ENTRIES2] =
{
0, /* Baseline entry is first and not used in this table */
-16,
+16,
-4,
-4,
-4,
-4,
-4,
-4,
-4,
-4,
-4,
-4,
-4,
+4,
+4,
+4,
+4,
+4,
+4,
+4,
+4,
+4,
+4,
+4
};
/*******************************************************************************
* Macros
******************************************************************************/
#define ISIGN(x) !((uint16_t)x & 0x8000)
#define ABS(x) ((x) > 0 ? (x) : -(x))
/*******************************************************************************
* Code
******************************************************************************/
/*! *********************************************************************************
* \brief This function performs a trim of the BBA DCOC DAC on the DUT
*
* \return status - 1 if passed, 0 if failed.
*
* \ingroup PublicAPIs
*
* \details
* Requires the RX to be warmed up before this function is called.
*
***********************************************************************************/
uint8_t rx_bba_dcoc_dac_trim_shortIQ(void)
{
uint8_t i;
float temp_mi = 0;
float temp_mq = 0;
float temp_pi = 0;
float temp_pq = 0;
float temp_step = 0;
uint8_t bbf_dacinit_i, bbf_dacinit_q;
uint32_t dcoc_init_reg_value_dcgain = 0x80802020; /* Used in 2nd & 3rd Generation DCOC Trims only. */
uint32_t bbf_dcoc_step;
uint32_t bbf_dcoc_step_rcp;
TZAdcocstep_t tza_dcoc_step[11];
uint8_t status = 0;
/* Save register values. */
uint32_t dcoc_ctrl_0_stack;
uint32_t dcoc_ctrl_1_stack;
uint32_t agc_ctrl_1_stack;
uint32_t rx_dig_ctrl_stack;
uint32_t dcoc_cal_gain_state;
XcvrCalDelay(1000);
dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore. */
dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore. */
rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore. */
agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore. */
dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore. */
/* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode. */
XCVR_RX_DIG->RX_DIG_CTRL = (XCVR_RX_DIG->RX_DIG_CTRL & ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK) | XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(0); /* Turn OFF AGC */
XCVR_RX_DIG->AGC_CTRL_1 = (XCVR_RX_DIG->AGC_CTRL_1 & ~XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_MASK) | XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) ; /* Set LNA Manual Gain */
XCVR_RX_DIG->AGC_CTRL_1 = (XCVR_RX_DIG->AGC_CTRL_1 & ~XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_MASK) | XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) ; /* Set BBA Manual Gain */
XCVR_RX_DIG->RX_DIG_CTRL = (XCVR_RX_DIG->RX_DIG_CTRL & ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK) | XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(0); /* Enable HW DC Calibration -- Disable for SW-DCOC */
XCVR_RX_DIG->DCOC_CTRL_0 = (XCVR_RX_DIG->DCOC_CTRL_0 & ~XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_MASK) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable Manual DCOC */
/* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode. */
XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(0x20) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(0x20) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(0x80) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(0x80);
/* Set DCOC Tracking State. */
XCVR_RX_DIG->DCOC_CTRL_0 = (XCVR_RX_DIG->DCOC_CTRL_0 & ~XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_MASK) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(0); /* Disables DCOC Tracking when set to 0 */
/* Apply Manual Gain. */
XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x02) | XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x00) ;
XcvrCalDelay(TsettleCal);
dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; /* Capture DC null setting. */
bbf_dacinit_i = (dcoc_init_reg_value_dcgain & 0x000000FFU);
bbf_dacinit_q = (dcoc_init_reg_value_dcgain & 0x0000FF00U) >> 8;
DC_Measure_short(I_CHANNEL, NOMINAL2);
DC_Measure_short(Q_CHANNEL, NOMINAL2);
/* SWEEP Q CHANNEL */
/* BBF NEG STEP */
XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - 16);
XcvrCalDelay(TsettleCal);
DC_Measure_short(Q_CHANNEL, BBF_NEG);
/* BBF POS STEP */
XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q + 16);
XcvrCalDelay(TsettleCal);
DC_Measure_short(Q_CHANNEL, BBF_POS);
XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial. */
XcvrCalDelay(TsettleCal);
/* SWEEP I CHANNEL */
/* BBF NEG STEP */
XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - 16);
XcvrCalDelay(TsettleCal);
DC_Measure_short(I_CHANNEL, BBF_NEG);
/* BBF POS STEP */
XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + 16);
XcvrCalDelay(TsettleCal);
DC_Measure_short(I_CHANNEL, BBF_POS);
XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DACs to initial. */
XcvrCalDelay(TsettleCal);
/* Calculate BBF DCOC STEPS, RECIPROCALS */
temp_mi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_NEG], &measurement_tbl2[I_CHANNEL][NOMINAL2]);
temp_mq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_NEG], &measurement_tbl2[Q_CHANNEL][NOMINAL2]);
temp_pi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_POS], &measurement_tbl2[I_CHANNEL][NOMINAL2]);
temp_pq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_POS], &measurement_tbl2[Q_CHANNEL][NOMINAL2]);
temp_step = (temp_mi+temp_pi + temp_mq+temp_pq) / 4;
bbf_dcoc_step = (uint32_t)roundf(temp_step * 8U);
if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305))
{
bbf_dcoc_step_rcp = (uint32_t)roundf((float)0x8000U / temp_step);
/* Calculate TZA DCOC STEPS & RECIPROCALS and IQ_DC_GAIN_MISMATCH. */
for (i = TZA_STEP_N0; i <= TZA_STEP_N10; i++) /* Relying on enumeration ordering. */
{
/* Calculate TZA DCOC STEPSIZE & its RECIPROCAL. */
switch(i){
case TZA_STEP_N0:
temp_step = (bbf_dcoc_step >> 3U) / 3.6F;
break;
case TZA_STEP_N1:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_01_init >> 16)/(xcvr_common_config.dcoc_tza_step_00_init >> 16);
break;
case TZA_STEP_N2:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_02_init >> 16)/(xcvr_common_config.dcoc_tza_step_01_init >> 16);
break;
case TZA_STEP_N3:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_03_init >> 16)/(xcvr_common_config.dcoc_tza_step_02_init >> 16);
break;
case TZA_STEP_N4:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_04_init >> 16)/(xcvr_common_config.dcoc_tza_step_03_init >> 16);
break;
case TZA_STEP_N5:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_05_init >> 16)/(xcvr_common_config.dcoc_tza_step_04_init >> 16);
break;
case TZA_STEP_N6:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_06_init >> 16)/(xcvr_common_config.dcoc_tza_step_05_init >> 16);
break;
case TZA_STEP_N7:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_07_init >> 16)/(xcvr_common_config.dcoc_tza_step_06_init >> 16);
break;
case TZA_STEP_N8:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_08_init >> 16)/(xcvr_common_config.dcoc_tza_step_07_init >> 16);
break;
case TZA_STEP_N9:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_09_init >> 16)/(xcvr_common_config.dcoc_tza_step_08_init >> 16);
break;
case TZA_STEP_N10:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_10_init >> 16)/(xcvr_common_config.dcoc_tza_step_09_init >> 16);
break;
default:
break;
}
tza_dcoc_step[i-TZA_STEP_N0].dcoc_step = (uint32_t)roundf(temp_step * 8);
tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / temp_step);
}
/* Make the trims active. */
XCVR_RX_DIG->DCOC_BBA_STEP = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_step) | XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_step_rcp) ;
XCVR_RX_DIG->DCOC_TZA_STEP_0 = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp) ;
XCVR_RX_DIG->DCOC_TZA_STEP_1 = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(tza_dcoc_step[1].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(tza_dcoc_step[1].dcoc_step_rcp) ;
XCVR_RX_DIG->DCOC_TZA_STEP_2 = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(tza_dcoc_step[2].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(tza_dcoc_step[2].dcoc_step_rcp) ;
XCVR_RX_DIG->DCOC_TZA_STEP_3 = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(tza_dcoc_step[3].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(tza_dcoc_step[3].dcoc_step_rcp) ;
XCVR_RX_DIG->DCOC_TZA_STEP_4 = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(tza_dcoc_step[4].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(tza_dcoc_step[4].dcoc_step_rcp) ;
XCVR_RX_DIG->DCOC_TZA_STEP_5 = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(tza_dcoc_step[5].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(tza_dcoc_step[5].dcoc_step_rcp) ;
XCVR_RX_DIG->DCOC_TZA_STEP_6 = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(tza_dcoc_step[6].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(tza_dcoc_step[6].dcoc_step_rcp) ;
XCVR_RX_DIG->DCOC_TZA_STEP_7 = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(tza_dcoc_step[7].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(tza_dcoc_step[7].dcoc_step_rcp) ;
XCVR_RX_DIG->DCOC_TZA_STEP_8 = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(tza_dcoc_step[8].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(tza_dcoc_step[8].dcoc_step_rcp) ;
XCVR_RX_DIG->DCOC_TZA_STEP_9 = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(tza_dcoc_step[9].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(tza_dcoc_step[9].dcoc_step_rcp) ;
XCVR_RX_DIG->DCOC_TZA_STEP_10 = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(tza_dcoc_step[10].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(tza_dcoc_step[10].dcoc_step_rcp) ;
status = 1; /* Success */
}
else
{
status = 0; /* Failure */
}
/* Restore Registers. */
XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings. */
XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings. */
XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings. */
XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting. */
XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore. */
return status;
}
/*! *********************************************************************************
* \brief This function performs one point of the DC GAIN calibration process on the DUT
*
* \param[in] chan - whether the I or Q channel is being tested.
* \param[in] stage - whether the BBF or TZA gain stage is being tested.
* \param[in] dcoc_init_val - the value being set in the ***DCOC_INIT_* register by the parent.
* \param[in] ext_measmt - the external measurement (in milliVolts) captured by the parent after the ***DCOC_INIT_* register was setup.
*
* \ingroup PublicAPIs
*
* \details
* Relies on a static array to store each point of data for later processing in ::DC_GainCalc().
*
***********************************************************************************/
void DC_Measure_short(IQ_t chan, DAC_SWEEP_STEP2_t dcoc_init_val)
{
int16_t dc_meas_i = 0;
int16_t dc_meas_q = 0;
int16_t sum_dc_meas_i = 0;
int16_t sum_dc_meas_q = 0;
{
int8_t i;
const int8_t iterations = 1;
sum_dc_meas_i = 0;
sum_dc_meas_q = 0;
for (i = 0; i < iterations; i++)
{
rx_dc_sample_average(&dc_meas_i, &dc_meas_q);
sum_dc_meas_i = sum_dc_meas_i + dc_meas_i;
sum_dc_meas_q = sum_dc_meas_q + dc_meas_q;
}
sum_dc_meas_i = sum_dc_meas_i / iterations;
sum_dc_meas_q = sum_dc_meas_q / iterations;
}
measurement_tbl2[chan][dcoc_init_val].step_value = sweep_step_values2[dcoc_init_val];
if (chan == I_CHANNEL)
{
measurement_tbl2[chan][dcoc_init_val].internal_measurement = dc_meas_i;
}
else
{
measurement_tbl2[chan][dcoc_init_val].internal_measurement = dc_meas_q;
}
}
/*! *********************************************************************************
* \brief This function calculates one point of DC DAC step based on digital samples of I or Q.
*
* \param[in] meas_ptr - pointer to the structure containing the measured data from internal measurement.
* \param[in] baseline_meas_ptr - pointer to the structure containing the baseline measured data from internal measurement.
*
* \return result of the calculation, the measurement DCOC DAC step value for this measurement point.
*
***********************************************************************************/
float calc_dcoc_dac_step(GAIN_CALC_TBL_ENTRY2_T * meas_ptr, GAIN_CALC_TBL_ENTRY2_T * baseline_meas_ptr )
{
static int16_t norm_dc_code;
static float dc_step;
/* Normalize internal measurement */
norm_dc_code = meas_ptr->internal_measurement - baseline_meas_ptr->internal_measurement;
dc_step = (float)(norm_dc_code) / (float)(meas_ptr->step_value);
dc_step = (dc_step < 0)? -dc_step: dc_step;
return dc_step;
}
/*! *********************************************************************************
* \brief Temporary delay function
*
* \param[in] none.
*
* \return none.
*
* \details
*
***********************************************************************************/
void XcvrCalDelay(uint32_t time)
{
while(time * 32 > 0) /* Time delay is roughly in uSec. */
{
time--;
}
}
/*! *********************************************************************************
* \brief This function calculates the average (DC value) based on a smaller set of digital samples of I and Q.
*
* \param[in] i_avg - pointer to the location for storing the calculated average for I channel samples.
* \param[in] q_avg - pointer to the location for storing the calculated average for Q channel samples.
*
***********************************************************************************/
void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg)
{
static uint32_t samples[128]; /* 544*2*2 (entire packet ram1/2 size) */
uint16_t i;
uint32_t rx_sample;
uint16_t * sample_ptr;
uint32_t temp, end_of_rx_wu;
uint32_t num_iq_samples;
float avg_i = 0;
float avg_q = 0;
num_iq_samples = 128;
/* Clear the entire allocated sample buffer */
for (i = 0; i < num_iq_samples; i++)
{
samples[i]=0;
}
/* Assume this has been called *AFTER* RxWu has completed. */
/* XCVR_ForceRxWu(); */
/* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase) */
temp = XCVR_TSM->END_OF_SEQ;
end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT;
while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {};
dbg_ram_init();
/* Argument below is # of bytes, so *2 (I+Q) and *2 (2bytes/sample) */
#if RADIO_IS_GEN_3P0
dbg_ram_start_capture(DBG_PAGE_RXDIGIQ, NO_START_TRIG, NO_STOP_TRIG);
dbg_ram_wait_for_complete();
dbg_ram_postproc_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]);
dbg_ram_release();
#else
(void)dbg_ram_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]);
#endif /* RADIO_IS_GEN_3P0 */
/* Sign extend the IQ samples in place in the sample buffer. */
sample_ptr = (uint16_t *)(&samples[0]);
for (i = 0; i < num_iq_samples * 2; i++)
{
rx_sample = *sample_ptr;
rx_sample |= ((rx_sample & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */
*sample_ptr = rx_sample;
sample_ptr++;
}
sample_ptr = (uint16_t *)(&samples[0]);
for (i = 0; i < num_iq_samples * 2; i += 2)
{
static int16_t i_value;
static int16_t q_value;
/* Average I & Q channels separately. */
i_value = *(sample_ptr + i); /* Sign extend from 12 to 16 bits. */
q_value = *(sample_ptr + i + 1); /* Sign extend from 12 to 16 bits. */
avg_i += ((float)i_value - avg_i) / (float)(i + 1); /* Rolling average I */
avg_q += ((float)q_value - avg_q) / (float)(i + 1); /* Rolling average Q */
}
XcvrCalDelay(10);
*i_avg = (int16_t)avg_i;
*q_avg = (int16_t)avg_q;
}
/*! *********************************************************************************
* \brief This function calculates the average (DC value) based on a larger set of digital samples of I and Q.
*
* \param[in] i_avg - pointer to the location for storing the calculated average for I channel samples.
* \param[in] q_avg - pointer to the location for storing the calculated average for Q channel samples.
*
***********************************************************************************/
void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg)
{
static uint32_t samples[512]; /* 544*2*2 (entire packet ram1/2 size) */
uint16_t i;
uint32_t rx_sample;
uint16_t * sample_ptr;
uint32_t temp, end_of_rx_wu;
uint32_t num_iq_samples;
float avg_i = 0;
float avg_q = 0;
num_iq_samples = 512;
/* Clear the entire allocated sample buffer. */
for (i = 0; i < num_iq_samples; i++)
{
samples[i]=0;
}
/* Assume this has been called *AFTER* RxWu has completed. */
/* XCVR_ForceRxWu(); */
/* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase). */
temp = XCVR_TSM->END_OF_SEQ;
end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT;
while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {};
dbg_ram_init();
/* Argument below is # of bytes, so *2 (I+Q) and *2 (2bytes/sample) */
#if RADIO_IS_GEN_3P0
dbg_ram_start_capture(DBG_PAGE_RXDIGIQ, NO_START_TRIG, NO_STOP_TRIG);
dbg_ram_wait_for_complete();
dbg_ram_postproc_capture(DBG_PAGE_RXDIGIQ,num_iq_samples * 2 * 2, &samples[0]);
dbg_ram_release();
#else
(void)dbg_ram_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]);
#endif /* RADIO_IS_GEN_3P0 */
/* Sign extend the IQ samples in place in the sample buffer. */
sample_ptr = (uint16_t *)(&samples[0]);
for (i = 0; i < num_iq_samples * 2; i++)
{
rx_sample = *sample_ptr;
rx_sample |= ((rx_sample & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */
*sample_ptr = rx_sample;
sample_ptr++;
}
sample_ptr = (uint16_t *)(&samples[0]);
for (i = 0; i < num_iq_samples * 2; i += 2)
{
static int16_t i_value;
static int16_t q_value;
/* Average I & Q channels separately. */
i_value = *(sample_ptr + i); /* Sign extend from 12 to 16 bits */
q_value = *(sample_ptr + i + 1); /* Sign extend from 12 to 16 bits */
avg_i += ((float)i_value - avg_i) / (float)(i + 1); /* Rolling average I */
avg_q += ((float)q_value - avg_q) / (float)(i + 1); /* Rolling average Q */
}
XcvrCalDelay(10);
*i_avg = (int16_t)avg_i;
*q_avg = (int16_t)avg_q;
}
/*! *********************************************************************************
* rx_dc_est_average : Get DC EST values and return the Average
***********************************************************************************/
void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg, uint16_t SampleNumber)
{
float avg_i = 0;
float avg_q = 0;
uint16_t i = 0;
static uint32_t dc_temp, temp;
uint32_t end_of_rx_wu = 0;
static int16_t dc_meas_i;
static int16_t dc_meas_q;
/* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase). */
temp = XCVR_TSM->END_OF_SEQ;
end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT;
while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {};
/* Read DCOC DC EST register. */
for (i = 0; i < SampleNumber; i++)
{
dc_temp = XCVR_RX_DIG->DCOC_DC_EST;
dc_meas_i = dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK;
temp = dc_meas_i;
temp |= ((temp & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */
dc_meas_i = temp;
avg_i += (float) dc_meas_i;
dc_meas_q = (dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK) >> XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT;
temp = dc_meas_q;
temp |= ((temp & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */
dc_meas_q = temp;
avg_q += (float) dc_meas_q;
}
avg_i /= (float) SampleNumber;
avg_q /= (float) SampleNumber;
*i_avg = (int16_t)avg_i;
*q_avg = (int16_t)avg_q;
}
/*! *********************************************************************************
* \brief This function performs a trim of the BBA DCOC DAC on the DUT
*
* \return status - 1 if passed, 0 if failed.
*
* \ingroup PublicAPIs
*
* \details
* Requires the RX to be warmed up before this function is called.
*
***********************************************************************************/
uint8_t rx_bba_dcoc_dac_trim_DCest(void)
{
uint8_t i;
float temp_mi = 0;
float temp_mq = 0;
float temp_pi = 0;
float temp_pq = 0;
float temp_step = 0;
uint32_t bbf_dcoc_step;
uint32_t bbf_dcoc_step_rcp;
TZAdcocstep_t tza_dcoc_step[11];
uint8_t status = 0;
uint8_t bbf_dacinit_i, bbf_dacinit_q;
uint8_t tza_dacinit_i, tza_dacinit_q;
int16_t dc_meas_i;
int16_t dc_meas_q;
uint32_t dcoc_init_reg_value_dcgain = 0x80802020; /* Used in 2nd & 3rd Generation DCOC Trims only */
uint32_t temp;
uint32_t dcoc_ctrl_0_stack;
uint32_t dcoc_ctrl_1_stack;
uint32_t agc_ctrl_1_stack;
uint32_t rx_dig_ctrl_stack;
uint32_t dcoc_cal_gain_state;
/* Save register */
dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */
dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */
rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore */
agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */
dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */
/* Register config */
/* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode */
temp = XCVR_RX_DIG->RX_DIG_CTRL;
temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK; /* Turn OFF AGC */
temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK; /* Disable for SW control of DCOC */
temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK; /* Disable for SW control of DCOC */
XCVR_RX_DIG->RX_DIG_CTRL = temp;
XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | /* Enable LNA Manual Gain */
XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | /* Enable BBA Manual Gain */
XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x0) | /* Set LNA Manual Gain */
XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x0); /* Set BBA Manual Gain */
/* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode */
temp = XCVR_RX_DIG->DCOC_CTRL_0;
temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable Manual DCOC */
temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1); /* Ensure DCOC Tracking is enabled */
temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(1); /* Enable DC Estimator */
temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1); /* Ensure DC correction is enabled */
XCVR_RX_DIG->DCOC_CTRL_0 = temp;
XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(0x20) |
XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(0x20) |
XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(0x80) |
XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(0x80);
XcvrCalDelay(TsettleCal);
/* Set default DCOC DAC INIT Value */
dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; /* Store DCOC DAC INIT values */
bbf_dacinit_i = (dcoc_init_reg_value_dcgain & 0x000000FFU);
bbf_dacinit_q = (dcoc_init_reg_value_dcgain & 0x0000FF00U)>>8;
tza_dacinit_i = (dcoc_init_reg_value_dcgain & 0x00FF0000U)>>16;
tza_dacinit_q = dcoc_init_reg_value_dcgain >> 24;
XcvrCalDelay(TsettleCal * 4);
rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64);
measurement_tbl2[I_CHANNEL][NOMINAL2].step_value = sweep_step_values2[NOMINAL2];
measurement_tbl2[Q_CHANNEL][NOMINAL2].step_value = sweep_step_values2[NOMINAL2];
measurement_tbl2[I_CHANNEL][NOMINAL2].internal_measurement = dc_meas_i;
measurement_tbl2[Q_CHANNEL][NOMINAL2].internal_measurement = dc_meas_q;
/* SWEEP I/Q CHANNEL */
/* BBF NEG STEP */
XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - 16) |
XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - 16) |
XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) |
XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q);
XcvrCalDelay(TsettleCal * 2);
rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64);
measurement_tbl2[I_CHANNEL][BBF_NEG].step_value = -16;
measurement_tbl2[Q_CHANNEL][BBF_NEG].step_value = -16;
measurement_tbl2[I_CHANNEL][BBF_NEG].internal_measurement = dc_meas_i;
measurement_tbl2[Q_CHANNEL][BBF_NEG].internal_measurement = dc_meas_q;
/* BBF POS STEP */
XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + 16) |
XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q + 16) |
XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) |
XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q);
XcvrCalDelay(TsettleCal * 2);
rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64);
measurement_tbl2[I_CHANNEL][BBF_POS].step_value = +16;
measurement_tbl2[Q_CHANNEL][BBF_POS].step_value = +16;
measurement_tbl2[I_CHANNEL][BBF_POS].internal_measurement = dc_meas_i;
measurement_tbl2[Q_CHANNEL][BBF_POS].internal_measurement = dc_meas_q;
XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial */
/* Calculate BBF DCOC STEPS, RECIPROCALS */
temp_mi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_NEG], &measurement_tbl2[I_CHANNEL][NOMINAL2]);
temp_mq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_NEG], &measurement_tbl2[Q_CHANNEL][NOMINAL2]);
temp_pi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_POS], &measurement_tbl2[I_CHANNEL][NOMINAL2]);
temp_pq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_POS], &measurement_tbl2[Q_CHANNEL][NOMINAL2]);
temp_step = (temp_mi + temp_pi + temp_mq + temp_pq) / 4;
bbf_dcoc_step = (uint32_t)roundf(temp_step * 8U);
if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305))
{
bbf_dcoc_step_rcp = (uint32_t)roundf((float)0x8000U / temp_step);
/* Calculate TZA DCOC STEPS & RECIPROCALS and IQ_DC_GAIN_MISMATCH */
for (i = TZA_STEP_N0; i <= TZA_STEP_N10; i++)
{
/* Calculate TZA DCOC STEPSIZE & its RECIPROCAL */
switch(i){
case TZA_STEP_N0:
temp_step = (bbf_dcoc_step>>3U) / 3.6F;
break;
case TZA_STEP_N1:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_01_init >> 16) / (xcvr_common_config.dcoc_tza_step_00_init >> 16);
break;
case TZA_STEP_N2:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_02_init >> 16) / (xcvr_common_config.dcoc_tza_step_01_init >> 16);
break;
case TZA_STEP_N3:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_03_init >> 16) / (xcvr_common_config.dcoc_tza_step_02_init >> 16);
break;
case TZA_STEP_N4:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_04_init >> 16) / (xcvr_common_config.dcoc_tza_step_03_init >> 16);
break;
case TZA_STEP_N5:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_05_init >> 16) / (xcvr_common_config.dcoc_tza_step_04_init >> 16);
break;
case TZA_STEP_N6:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_06_init >> 16) / (xcvr_common_config.dcoc_tza_step_05_init >> 16);
break;
case TZA_STEP_N7:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_07_init >> 16) / (xcvr_common_config.dcoc_tza_step_06_init >> 16);
break;
case TZA_STEP_N8:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_08_init >> 16) / (xcvr_common_config.dcoc_tza_step_07_init >> 16);
break;
case TZA_STEP_N9:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_09_init >> 16) / (xcvr_common_config.dcoc_tza_step_08_init >> 16);
break;
case TZA_STEP_N10:
temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_10_init >> 16) / (xcvr_common_config.dcoc_tza_step_09_init >> 16);
break;
default:
break;
}
tza_dcoc_step[i-TZA_STEP_N0].dcoc_step = (uint32_t)roundf(temp_step * 8);
tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / temp_step);
}
/* Make the trims active */
XCVR_RX_DIG->DCOC_BBA_STEP = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_step) | XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_step_rcp);
XCVR_RX_DIG->DCOC_TZA_STEP_0 = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp);
XCVR_RX_DIG->DCOC_TZA_STEP_1 = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(tza_dcoc_step[1].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(tza_dcoc_step[1].dcoc_step_rcp);
XCVR_RX_DIG->DCOC_TZA_STEP_2 = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(tza_dcoc_step[2].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(tza_dcoc_step[2].dcoc_step_rcp);
XCVR_RX_DIG->DCOC_TZA_STEP_3 = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(tza_dcoc_step[3].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(tza_dcoc_step[3].dcoc_step_rcp);
XCVR_RX_DIG->DCOC_TZA_STEP_4 = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(tza_dcoc_step[4].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(tza_dcoc_step[4].dcoc_step_rcp);
XCVR_RX_DIG->DCOC_TZA_STEP_5 = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(tza_dcoc_step[5].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(tza_dcoc_step[5].dcoc_step_rcp);
XCVR_RX_DIG->DCOC_TZA_STEP_6 = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(tza_dcoc_step[6].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(tza_dcoc_step[6].dcoc_step_rcp);
XCVR_RX_DIG->DCOC_TZA_STEP_7 = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(tza_dcoc_step[7].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(tza_dcoc_step[7].dcoc_step_rcp);
XCVR_RX_DIG->DCOC_TZA_STEP_8 = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(tza_dcoc_step[8].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(tza_dcoc_step[8].dcoc_step_rcp);
XCVR_RX_DIG->DCOC_TZA_STEP_9 = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(tza_dcoc_step[9].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(tza_dcoc_step[9].dcoc_step_rcp);
XCVR_RX_DIG->DCOC_TZA_STEP_10 = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(tza_dcoc_step[10].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(tza_dcoc_step[10].dcoc_step_rcp);
status = 1; /* Success */
}
else
{
status = 0; /* Failure */
}
/* Restore Registers */
XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings */
XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */
XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings */
XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */
XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore */
return status;
}
/*! *********************************************************************************
* DCOC_DAC_INIT_Cal : slope sign seek depending on measure's sign
***********************************************************************************/
void DCOC_DAC_INIT_Cal(uint8_t standalone_operation)
{
int16_t dc_meas_i = 2000, dc_meas_i_p = 2000;
int16_t dc_meas_q = 2000, dc_meas_q_p = 2000;
uint8_t curr_tza_dac_i, curr_tza_dac_q;
uint8_t curr_bba_dac_i, curr_bba_dac_q;
uint8_t p_tza_dac_i = 0, p_tza_dac_q = 0;
uint8_t p_bba_dac_i = 0, p_bba_dac_q = 0;
uint8_t i = 0;
uint8_t bba_gain = 11;
bool TZA_I_OK = 0, TZA_Q_OK = 0, BBA_I_OK = 0, BBA_Q_OK = 0;
uint32_t dcoc_ctrl_0_stack;
uint32_t dcoc_ctrl_1_stack;
uint32_t agc_ctrl_1_stack;
uint32_t rx_dig_ctrl_stack;
uint32_t dcoc_cal_gain_state;
uint32_t xcvr_ctrl_stack = 0;
uint32_t temp;
/* Save registers */
dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */
dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */
rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore */
agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */
dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */
/* WarmUp */
if (standalone_operation)
{
temp = XCVR_MISC->XCVR_CTRL;
xcvr_ctrl_stack = temp;
temp &= ~(XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK);
temp |= XCVR_CTRL_XCVR_CTRL_PROTOCOL(0);
XCVR_MISC->XCVR_CTRL = temp;
XCVR_OverrideChannel(12, 1); /* Calibrate on channel #12, 2.426 GHz in BLE map */
XCVR_ForceRxWu();
XcvrCalDelay(2000);
}
/* Register config */
/* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode */
temp = XCVR_RX_DIG->RX_DIG_CTRL;
temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK; /* Turn OFF AGC */
temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK; /* Disable for SW control of DCOC */
temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK; /* Disable for SW control of DCOC */
XCVR_RX_DIG->RX_DIG_CTRL = temp;
XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | /* Enable LNA Manual Gain */
XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | /* Enable BBA Manual Gain */
XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x0) | /* Set LNA Manual Gain */
XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x0); /* Set BBA Manual Gain */
/* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode */
temp = XCVR_RX_DIG->DCOC_CTRL_0;
temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable Manual DCOC */
temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1); /* Ensure DCOC Tracking is enabled */
temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(1); /* Enable DC Estimator */
temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1); /* Ensure DC correction is enabled */
XCVR_RX_DIG->DCOC_CTRL_0 = temp;
XcvrCalDelay(TsettleCal);
/* Set default DCOC DAC INIT Value */
/* LNA and BBA DAC Sweep */
curr_bba_dac_i = 0x20;
curr_bba_dac_q = 0x20;
curr_tza_dac_i = 0x80;
curr_tza_dac_q = 0x80;
/* Perform a first DC measurement to ensure that measurement is not clipping */
XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) |
XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) |
XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) |
XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q);
do
{
bba_gain--;
/* Set DAC user gain */
XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) |
XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0) | /* 2 */
XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) |
XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(bba_gain) ; /* 10 */
XcvrCalDelay(TsettleCal * 2);
rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64);
} while ((ABS(dc_meas_i) > 1900) | (ABS(dc_meas_q) > 1900));
for (i = 0; i < 0x0F; i++)
{
/* I channel : */
if (!TZA_I_OK)
{
if ((ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p)) && (i > 0))
{
if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p)))
{
curr_tza_dac_i = p_tza_dac_i;
}
TZA_I_OK = 1;
}
else
{
p_tza_dac_i = curr_tza_dac_i;
if (ISIGN(dc_meas_i)) /* If positif */
{
curr_tza_dac_i--;
}
else
{
curr_tza_dac_i++;
}
}
}
else /* Sweep BBA I */
{
if (!BBA_I_OK)
{
if ((ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p)) && (curr_bba_dac_i != 0x20))
{
if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p)))
{
curr_bba_dac_i = p_bba_dac_i;
}
BBA_I_OK = 1;
}
else
{
p_bba_dac_i = curr_bba_dac_i;
if (ISIGN(dc_meas_i)) /* If positif */
{
curr_bba_dac_i--;
}
else
{
curr_bba_dac_i++;
}
}
}
}
/* Q channel : */
if (!TZA_Q_OK)
{
if ((ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p)) && (i > 0))
{
if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p)))
{
curr_tza_dac_q = p_tza_dac_q;
}
TZA_Q_OK = 1;
}
else
{
p_tza_dac_q = curr_tza_dac_q;
if (ISIGN(dc_meas_q)) /* If positif */
{
curr_tza_dac_q--;
}
else
{
curr_tza_dac_q++;
}
}
}
else /* Sweep BBA Q */
{
if (!BBA_Q_OK)
{
if ((ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p)) && (curr_bba_dac_q != 0x20))
{
if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p)))
{
curr_bba_dac_q = p_bba_dac_q;
}
BBA_Q_OK = 1;
}
else
{
p_bba_dac_q = curr_bba_dac_q;
if (ISIGN(dc_meas_q)) /* If positif */
{
curr_bba_dac_q--;
}
else
{
curr_bba_dac_q++;
}
}
}
}
/* DC OK break : */
if (TZA_I_OK && TZA_Q_OK && BBA_I_OK && BBA_Q_OK)
{
break;
}
dc_meas_i_p = dc_meas_i; /* Store as previous value */
dc_meas_q_p = dc_meas_q; /* Store as previous value */
XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) |
XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) |
XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) |
XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q);
XcvrCalDelay(TsettleCal * 2);
rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64);
}
/* Apply optimized DCOC DAC INIT : */
XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) |
XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) |
XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) |
XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q);
/* WarmDown */
if (standalone_operation)
{
XCVR_ForceRxWd(); /* Don't leave the receiver running. */
XcvrCalDelay(200);
XCVR_OverrideChannel(0xFF,1); /* Release channel overrides */
XCVR_MISC->XCVR_CTRL = xcvr_ctrl_stack;
}
/* Restore register */
XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings */
XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */
XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings */
XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */
XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore */
}

136
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/fsl_xcvr_trim.h Normal file
View File

@ -0,0 +1,136 @@
/*
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _FSL_XCVR_TRIM_H_
/* Clang-format off. */
#define _FSL_XCVR_TRIM_H_
/* Clang-format on. */
#include "fsl_device_registers.h"
/*!
* @addtogroup xcvr
* @{
*/
/*! @file*/
/************************************************************************************
*************************************************************************************
* Public constant definitions
*************************************************************************************
************************************************************************************/
/************************************************************************************
*************************************************************************************
* Public type definitions
*************************************************************************************
************************************************************************************/
/* \brief The enumerations used to define the I & Q channel selections. */
typedef enum
{
I_CHANNEL = 0,
Q_CHANNEL = 1,
NUM_I_Q_CHAN = 2
} IQ_t;
typedef enum /* Enumeration of ADC_GAIN_CAL 2 */
{
NOMINAL2 = 0,
BBF_NEG = 1,
BBF_POS = 2,
TZA_STEP_N0 = 3,
TZA_STEP_N1 = 4,
TZA_STEP_N2 = 5,
TZA_STEP_N3 = 6,
TZA_STEP_N4 = 7,
TZA_STEP_N5 = 8,
TZA_STEP_N6 = 9,
TZA_STEP_N7 = 10,
TZA_STEP_N8 = 11,
TZA_STEP_N9 = 12,
TZA_STEP_N10 = 13,
TZA_STEP_P0 = 14,
TZA_STEP_P1 = 15,
TZA_STEP_P2 = 16,
TZA_STEP_P3 = 17,
TZA_STEP_P4 = 18,
TZA_STEP_P5 = 19,
TZA_STEP_P6 = 20,
TZA_STEP_P7 = 21,
TZA_STEP_P8 = 22,
TZA_STEP_P9 = 23,
TZA_STEP_P10 = 24,
NUM_SWEEP_STEP_ENTRIES2 = 25 /* Including the baseline entry #0. */
} DAC_SWEEP_STEP2_t;
/* \brief Defines an entry in an array of structs to describe TZA DCOC STEP and TZA_DCOC_STEP_RECIPROCAL. */
typedef struct
{
uint16_t dcoc_step;
uint16_t dcoc_step_rcp;
// uint16_t dcoc_step_q;
// uint16_t dcoc_step_rcp_q;
} TZAdcocstep_t;
typedef struct
{
int8_t step_value; /* The offset from nominal DAC value (see sweep_step_values[]) */
int16_t internal_measurement; /* The value (average code) measured from DMA samples. */
// uint8_t valid; /* Set to TRUE (non zero) when a value is written to this table entry. */
} GAIN_CALC_TBL_ENTRY2_T;
/*******************************************************************************
* Definitions
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg);
void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg);
uint8_t rx_bba_dcoc_dac_trim_shortIQ(void);
void XcvrCalDelay(uint32_t time);
void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg, uint16_t SampleNumber);
uint8_t rx_bba_dcoc_dac_trim_DCest(void);
void DCOC_DAC_INIT_Cal(uint8_t standalone_operation);
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* _FSL_XCVR_TRIM_H_ */

530
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/ifr_radio.c Normal file
View File

@ -0,0 +1,530 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_device_registers.h"
#include "fsl_xcvr.h"
#include "ifr_radio.h"
#include "fsl_os_abstraction.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define IFR_RAM (0)
#if RADIO_IS_GEN_3P0
#define RDINDX (0x41U)
#define K3_BASE_INDEX (0x11U) /* Based for read index */
#else
#define RDRSRC (0x03U)
#define KW4x_512_BASE (0x20000U)
#define KW4x_256_BASE (0x10000U)
#endif /* RADIO_IS_GEN_3P0 */
#if RADIO_IS_GEN_2P1
#define FTFA (FTFE)
#endif /* RADIO_IS_GEN_2P1 */
/*******************************************************************************
* Prototypes
******************************************************************************/
uint32_t read_another_ifr_word(void);
uint32_t read_first_ifr_word(uint32_t read_addr);
#if RADIO_IS_GEN_3P0
uint64_t read_index_ifr(uint32_t read_addr);
#else
/*! *********************************************************************************
* @brief Reads a location in block 1 IFR for use by the radio.
*
* This function handles reading IFR data from flash memory for trim loading.
*
* @param read_addr the address in the IFR to be read.
*
* @details This function wraps both the Gen2 read_resource command and the Gen2.1 and Gen3 read_index
***********************************************************************************/
#if RADIO_IS_GEN_2P1
uint64_t read_resource_ifr(uint32_t read_addr);
#else
uint32_t read_resource_ifr(uint32_t read_addr);
#endif /* RADIO_IS_GEN_2P1 */
#endif /* RADIO_IS_GEN_3P0 */
void store_sw_trim(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries, uint32_t addr, uint32_t data);
/*******************************************************************************
* Variables
******************************************************************************/
static uint32_t ifr_read_addr;
#if RADIO_IS_GEN_3P0
static uint64_t packed_data_long; /* Storage for 2 32 bit values to be read by read_index */
static uint8_t num_words_avail; /* Number of 32 bit words available in packed_data_long storage */
const uint32_t BLOCK_1_IFR[]=
{
/* Revised fallback table which should work with untrimmed parts */
0xABCDFFFEU, /* Version #FFFE indicates default trim values */
/* Trim table is empty for Gen3 by default */
/* No TRIM_STATUS in SW fallback array. */
0xFEED0E0FU /* End of File */
};
#else
#if RADIO_IS_GEN_2P0
const uint32_t BLOCK_1_IFR[]=
{
/* Revised fallback table which should work with untrimmed parts */
0xABCDFFFEU, /* Version #FFFE indicates default trim values */
0x4005912CU, /* RSIM_ANA_TRIM address */
0x784B0000U, /* RSIM_ANA_TRIM default value */
/* No TRIM_STATUS in SW fallback array. */
0xFEED0E0FU /* End of File */
};
#else
static uint64_t packed_data_long; /* Storage for 2 32 bit values to be read by read_index */
static uint8_t num_words_avail; /* Number of 32 bit words available in packed_data_long storage */
const uint32_t BLOCK_1_IFR[]=
{
/* Revised fallback table which should work with untrimmed parts */
0xABCDFFFEU, /* Version #FFFE indicates default trim values */
0x4005912CU, /* RSIM_ANA_TRIM address */
0x784B0000U, /* RSIM_ANA_TRIM default value */
/* No TRIM_STATUS in SW fallback array. */
0xFEED0E0FU /* End of File */
};
#endif /* RADIO_IS_GEN_2P0 */
#endif /* RADIO_IS_GEN_3P0 */
/*******************************************************************************
* Code
******************************************************************************/
/*! *********************************************************************************
* \brief Read command for reading the first 32bit word from IFR, encapsulates different
* flash IFR read mechanisms for multiple generations of SOC
*
* \param read_addr flash address
*
* \return 8 bytes of packed data containing radio trims only
*
***********************************************************************************/
uint32_t read_first_ifr_word(uint32_t read_addr)
{
ifr_read_addr = read_addr;
return read_another_ifr_word();
}
/*! *********************************************************************************
* \brief Read command for reading additional 32bit words from IFR. Encapsulates multiple IFR read mechanisms.
*
* \param read_addr flash address
*
* \return 8 bytes of packed data containing radio trims only
*
* \remarks PRE-CONDITIONS:
* The function read_first_ifr_word() must have been called so that the ifr_read_addr variable is setup prior to use.
*
***********************************************************************************/
uint32_t read_another_ifr_word(void)
{
uint32_t packed_data;
#if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1)
/* Using some static storage and alternating reads to read_index_ifr to replace read_resource_ifr */
if (num_words_avail == 0)
{
#if RADIO_IS_GEN_3P0
packed_data_long = read_index_ifr(ifr_read_addr);
#else /* Use 64 bit return version of read_resource */
packed_data_long = read_resource_ifr(ifr_read_addr);
#endif /* RADIO_IS_GEN_3P0 */
num_words_avail = 2;
ifr_read_addr++; /* Read index addresses increment by 1 */
}
packed_data = (uint32_t)(packed_data_long & 0xFFFFFFFF);
packed_data_long = packed_data_long >> 32;
num_words_avail--;
#else
packed_data = read_resource_ifr(ifr_read_addr);
ifr_read_addr += 4; /* Read resource addresses increment by 4 */
#endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */
return packed_data;
}
#if RADIO_IS_GEN_3P0
/*! *********************************************************************************
* \brief Read command for reading from IFR using RDINDEX command
*
* \param read_addr flash address
*
* \return 8 bytes of packed data containing radio trims only
*
***********************************************************************************/
uint64_t read_index_ifr(uint32_t read_addr)
{
uint8_t rdindex = read_addr;
uint64_t read_data;
uint8_t i;
while ((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 to make sure not interrupting a prior operation */
if ((FTFE->FSTAT & FTFE_FSTAT_ACCERR_MASK) == FTFE_FSTAT_ACCERR_MASK )
{
FTFE->FSTAT = (1 << FTFE_FSTAT_ACCERR_SHIFT); /* Write 1 to ACCEER to clear errors */
}
FTFE->FCCOB[0] = RDINDX;
FTFE->FCCOB[1] = rdindex;
OSA_InterrupDisable();
FTFE->FSTAT = FTFE_FSTAT_CCIF_MASK;
while((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */
OSA_InterruptEnable();
/* Pack read data back into 64 bit type */
read_data = FTFE->FCCOB[11]; /* MSB goes in first, will be shifted left sequentially */
for (i = 10; i > 3; i--)
{
read_data = read_data << 8;
read_data |= FTFE->FCCOB[i];
}
return read_data;
}
#else
/*! *********************************************************************************
* \brief Read command for reading from IFR
*
* \param read_addr flash address
*
* \return packed data containing radio trims only
*
***********************************************************************************/
#if RADIO_IS_GEN_2P0
uint32_t read_resource_ifr(uint32_t read_addr)
{
uint32_t packed_data;
uint8_t flash_addr23_16, flash_addr15_8, flash_addr7_0;
uint32_t read_data31_24, read_data23_16, read_data15_8, read_data7_0;
flash_addr23_16 = (uint8_t)((read_addr & 0xFF0000) >> 16);
flash_addr15_8 = (uint8_t)((read_addr & 0x00FF00) >> 8);
flash_addr7_0 = (uint8_t)(read_addr & 0xFF);
while ((FTFA_FSTAT_CCIF_MASK & FTFA->FSTAT) == 0); /* Wait till CCIF=1 */
if ((FTFA->FSTAT & FTFA_FSTAT_ACCERR_MASK) == FTFA_FSTAT_ACCERR_MASK )
{
FTFA->FSTAT = (1<<FTFA_FSTAT_ACCERR_SHIFT); /* Write 1 to ACCEER to clear errors */
}
FTFA->FCCOB0 = RDRSRC;
FTFA->FCCOB1 = flash_addr23_16;
FTFA->FCCOB2 = flash_addr15_8;
FTFA->FCCOB3 = flash_addr7_0;
FTFA->FCCOB8 = 0x00;
OSA_InterruptDisable();
FTFA->FSTAT = FTFA_FSTAT_CCIF_MASK;
while ((FTFA_FSTAT_CCIF_MASK & FTFA->FSTAT) == 0); /* Wait till CCIF=1 */
OSA_InterruptEnable();
/* Start reading */
read_data31_24 = FTFA->FCCOB4; /* FTFA->FCCOB[4] */
read_data23_16 = FTFA->FCCOB5; /* FTFA->FCCOB[5] */
read_data15_8 = FTFA->FCCOB6; /* FTFA->FCCOB[6] */
read_data7_0 = FTFA->FCCOB7; /* FTFA->FCCOB[7] */
packed_data = (read_data31_24 << 24) | (read_data23_16 << 16) | (read_data15_8 << 8) | (read_data7_0 << 0);
return packed_data;
}
#else
uint64_t read_resource_ifr(uint32_t read_addr)
{
uint64_t packed_data;
uint8_t flash_addr23_16, flash_addr15_8, flash_addr7_0;
uint8_t read_data[8];
uint64_t temp_64;
uint8_t i;
flash_addr23_16 = (uint8_t)((read_addr & 0xFF0000) >> 16);
flash_addr15_8 = (uint8_t)((read_addr & 0x00FF00) >> 8);
flash_addr7_0 = (uint8_t)(read_addr & 0xFF);
while((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */
if ((FTFE->FSTAT & FTFE_FSTAT_ACCERR_MASK) == FTFE_FSTAT_ACCERR_MASK )
{
FTFE->FSTAT = (1<<FTFE_FSTAT_ACCERR_SHIFT); /* Write 1 to ACCEER to clear errors */
}
FTFE->FCCOB0 = RDRSRC;
FTFE->FCCOB1 = flash_addr23_16;
FTFE->FCCOB2 = flash_addr15_8;
FTFE->FCCOB3 = flash_addr7_0;
FTFE->FCCOB4 = 0x00;
OSA_InterruptDisable();
FTFE->FSTAT = FTFE_FSTAT_CCIF_MASK;
while ((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */
OSA_InterruptEnable();
/* Start reading */
read_data[7] = FTFE->FCCOB4;
read_data[6] = FTFE->FCCOB5;
read_data[5] = FTFE->FCCOB6;
read_data[4] = FTFE->FCCOB7;
read_data[3] = FTFE->FCCOB8;
read_data[2] = FTFE->FCCOB9;
read_data[1] = FTFE->FCCOBA;
read_data[0] = FTFE->FCCOBB;
packed_data = 0;
for (i = 0; i < 8; i++)
{
temp_64 = read_data[i];
packed_data |= temp_64 << (i * 8);
}
return packed_data;
}
#endif /* RADIO_IS_GEN_2P0 */
#endif /* RADIO_IS_GEN_3P0 */
/*! *********************************************************************************
* \brief Store a SW trim value in the table passed in from calling function.
*
* \param sw_trim_tbl pointer to the software trim table to hold SW trim values
* \param num_entries the number of entries in the SW trim table
* \param addr the software trim ID
* \param data the value of the software trim
*
***********************************************************************************/
void store_sw_trim(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries, uint32_t addr, uint32_t data)
{
uint16_t i;
if (sw_trim_tbl != NULL)
{
for (i = 0; i < num_entries; i++)
{
if (addr == sw_trim_tbl[i].trim_id)
{
sw_trim_tbl[i].trim_value = data;
sw_trim_tbl[i].valid = 1;
break; /* Don't need to scan the array any further... */
}
}
}
}
/*! *********************************************************************************
* \brief Process block 1 IFR data.
*
* \param sw_trim_tbl pointer to the software trim table to hold SW trim values
* \param num_entries the number of entries in the SW trim table
*
* \remarks
* Uses a IFR v2 formatted default array if the IFR is blank or corrupted.
* Stores SW trim values to an array passed into this function.
*
***********************************************************************************/
void handle_ifr(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries)
{
uint32_t dest_addr;
uint32_t read_addr;
uint32_t dest_data;
uint32_t packed_data;
uint32_t *ifr_ptr;
#if RADIO_IS_GEN_3P0
num_words_avail = 0; /* Prep for handling 64 bit words from flash */
#endif /* RADIO_IS_GEN_3P0 */
#if RADIO_IS_GEN_3P0
read_addr = K3_BASE_INDEX;
#else
#ifdef CPU_MKW41Z256VHT4
read_addr = KW4x_256_BASE;
#else
read_addr = KW4x_512_BASE;
#endif /* CPU_MKW41Z256VHT4 */
#endif /* RADIO_IS_GEN_3P0 */
/* Read first entry in IFR table */
packed_data = read_first_ifr_word(read_addr);
if ((packed_data&~IFR_VERSION_MASK) == IFR_VERSION_HDR)
{
/* Valid header was found, process real IFR data */
XCVR_MISC->OVERWRITE_VER = (packed_data & IFR_VERSION_MASK);
store_sw_trim(sw_trim_tbl, num_entries, 0xABCD, (packed_data & IFR_VERSION_MASK)); /* Place IFR version # in SW trim array*/
packed_data = read_another_ifr_word();
while (packed_data !=IFR_EOF_SYMBOL)
{
if (IS_A_SW_ID(packed_data)) /* SW Trim case (non_reg writes) */
{
dest_addr = packed_data;
packed_data = read_another_ifr_word();
dest_data = packed_data;
/* Place SW trim in array for driver SW to use */
store_sw_trim(sw_trim_tbl, num_entries, dest_addr, dest_data);
}
else
{
if (IS_VALID_REG_ADDR(packed_data)) /* Valid register write address */
{
dest_addr = packed_data;
packed_data = read_another_ifr_word();
dest_data = packed_data;
*(uint32_t *)(dest_addr) = dest_data;
}
else
{ /* Invalid address case */
}
}
packed_data=read_another_ifr_word();
}
}
else
{
/* Valid header is not present, use blind IFR trim table */
ifr_ptr = (void *)BLOCK_1_IFR;
packed_data = *ifr_ptr;
XCVR_MISC->OVERWRITE_VER = (packed_data & IFR_VERSION_MASK);
store_sw_trim(sw_trim_tbl, num_entries, 0xABCD, (packed_data & IFR_VERSION_MASK)); /* Place IFR version # in SW trim array */
ifr_ptr++;
packed_data= *ifr_ptr;
while (packed_data != IFR_EOF_SYMBOL)
{
if (IS_A_SW_ID(packed_data))
{
/* SW Trim case (non_reg writes) */
dest_addr = packed_data;
ifr_ptr++;
packed_data = *(ifr_ptr);
dest_data = packed_data;
/* Place SW trim in array for driver SW to use */
store_sw_trim(sw_trim_tbl, num_entries, dest_addr, dest_data);
}
else
{
dest_addr = packed_data;
ifr_ptr++;
packed_data = *ifr_ptr;
dest_data = packed_data;
/* Valid register write address */
if (IS_VALID_REG_ADDR(dest_addr))
{
*(uint32_t *)(dest_addr) = dest_data;
}
else
{
/* Invalid address case */
}
}
ifr_ptr++;
packed_data= *ifr_ptr;
}
}
}
#if RADIO_IS_GEN_3P0
#else
uint32_t handle_ifr_die_id(void)
{
uint32_t id_x, id_y;
uint32_t id;
id = read_resource_ifr(0x90);
id_x = id & 0x00FF0000;
id_y = id & 0x000000FF;
return (id_x | id_y);
}
uint32_t handle_ifr_die_kw_type(void)
{
uint32_t zb, ble;
zb = read_resource_ifr(0x80) & 0x8000;
ble= read_resource_ifr(0x88) & 0x100000;
return (zb | ble);
}
#endif /* RADIO_IS_GEN_3P0 */
/*! *********************************************************************************
* \brief Dumps block 1 IFR data to an array.
*
* \param dump_tbl pointer to the table to hold the dumped IFR values
* \param num_entries the number of entries to dump
*
* \remarks
* Starts at the first address in IFR and dumps sequential entries.
*
***********************************************************************************/
void dump_ifr(uint32_t * dump_tbl, uint8_t num_entries)
{
#if RADIO_IS_GEN_3P0
uint32_t ifr_address = 0x20000;
#else
uint32_t ifr_address = 0x20000;
#endif /* RADIO_IS_GEN_3P0 */
uint32_t * dump_ptr = dump_tbl;
uint8_t i;
*dump_ptr = read_first_ifr_word(ifr_address);
dump_ptr++;
for (i = 0; i < num_entries - 1; i++)
{
*dump_ptr = read_another_ifr_word();
dump_ptr++;
}
}

199
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/middleware/wireless/TARGET_FRAMEWORK_5_3_3/XCVR/MKW41Z4/ifr_radio.h Normal file
View File

@ -0,0 +1,199 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __IFR_RADIO_H__
/* clang-format off */
#define __IFR_RADIO_H__
/* clang-format on */
#include <stdint.h>
/* clang-format off */
#define _FSL_XCVR_H_
/* clang-format on */
/*!
* @addtogroup xcvr
* @{
*/
/*! @file*/
/*******************************************************************************
* Definitions
******************************************************************************/
#define IFR_EOF_SYMBOL (0xFEED0E0FU) /* < Denotes the "End of File" for IFR data */
#define IFR_VERSION_HDR (0xABCD0000U) /* < Constant value for upper 16 bits of IFR data header */
#define IFR_VERSION_MASK (0x0000FFFFU) /* < Mask for version number (lower 16 bits) of IFR data header */
#define IFR_SW_ID_MIN (0x00000000U) /* < Lower limit of SW trim IDs */
#define IFR_SW_ID_MAX (0x0000FFFFU) /* < Lower limit of SW trim IDs */
#define IS_A_SW_ID(x) ((IFR_SW_ID_MIN < (x)) && (IFR_SW_ID_MAX >= (x)))
/* K3 valid registers support */
#if (defined(CPU_K32W042S1M2CAx_M0P) || defined(CPU_K32W042S1M2VPJ_M0P))
#define IS_VALID_REG_ADDR(x) (((x) & 0xFFFF0000U) == 0x41000000U) /* Valid addresses are 0x410xxxxx */
#endif /* (defined(CPU_K32W042S1M2CAx_M0P) || defined(CPU_K32W042S1M2VPJ_M0P)) */
/* KW41 and KW35/36 valid registers support */
#if (defined(CPU_MKW41Z256VHT4) || defined(CPU_MKW41Z512VHT4) || \
defined(CPU_MKW31Z256VHT4) || defined(CPU_MKW31Z512VHT4) || \
defined(CPU_MKW21Z256VHT4) || defined(CPU_MKW21Z512VHT4) || \
defined(CPU_MKW35A512VFP4) || defined(CPU_MKW36A512VFP4) )
#define IS_VALID_REG_ADDR(x) (((x) & 0xFFFF0000U) == 0x40050000U) /* Valid addresses are 0x4005xxxx */
#endif
#define MAKE_MASK(size) ((1 << (size)) - 1)
#define MAKE_MASKSHFT(size, bitpos) (MAKE_MASK(size) << (bitpos))
#define IFR_TZA_CAP_TUNE_MASK (0x0000000FU)
#define IFR_TZA_CAP_TUNE_SHIFT (0)
#define IFR_BBF_CAP_TUNE_MASK (0x000F0000U)
#define IFR_BBF_CAP_TUNE_SHIFT (16)
#define IFR_RES_TUNE2_MASK (0x00F00000U)
#define IFR_RES_TUNE2_SHIFT (20)
/* \var typedef uint8_t IFR_ERROR_T */
/* \brief The IFR error reporting type. */
/* See #IFR_ERROR_T_enum for the enumeration definitions. */
typedef uint8_t IFR_ERROR_T;
/* \brief The enumerations used to describe IFR errors. */
enum IFR_ERROR_T_enum
{
IFR_SUCCESS = 0,
INVALID_POINTER = 1, /* < NULL pointer error */
INVALID_DEST_SIZE_SHIFT = 2, /* < the bits won't fit as specified in the destination */
};
/* \var typedef uint16_t SW_TRIM_ID_T */
/* \brief The SW trim ID type. */
/* See #SW_TRIM_ID_T_enum for the enumeration definitions. */
typedef uint16_t SW_TRIM_ID_T;
/* \brief The enumerations used to define SW trim IDs. */
enum SW_TRIM_ID_T_enum
{
Q_RELATIVE_GAIN_BY_PART = 0, /* < Q vs I relative gain trim ID */
ADC_GAIN = 1, /* < ADC gain trim ID */
ZB_FILT_TRIM = 2, /* < Baseband Bandwidth filter trim ID for BLE */
BLE_FILT_TRIM = 3, /* < Baseband Bandwidth filter trim ID for BLE */
TRIM_STATUS = 4, /* < Status result of the trim process (error indications) */
TRIM_VERSION = 0xABCD, /* < Version number of the IFR trim algorithm/format. */
};
/* \var typedef uint32_t IFR_TRIM_STATUS_T */
/* \brief The definition of failure bits stored in IFR trim status word. */
/* See #IFR_TRIM_STATUS_T_enum for the enumeration definitions. */
typedef uint32_t IFR_TRIM_STATUS_T;
/* \brief The enumerations used to describe trim algorithm failures in the status entry in IFR. */
/* This enum represents multiple values which can be OR'd together in a single status word. */
enum IFR_TRIM_STATUS_T_enum
{
TRIM_ALGORITHM_SUCCESS = 0,
BGAP_VOLTAGE_TRIM_FAILED = 1, /* < algorithm failure in BGAP voltagetrim */
IQMC_GAIN_ADJ_FAILED = 2, /* < algorithm failure in IQMC gain trim */
IQMC_PHASE_ADJ_FAILED = 4, /* < algorithm failure in IQMC phase trim */
IQMC_DC_GAIN_ADJ_FAILED = 8, /* < */
ADC_GAIN_TRIM_FAILED = 10, /* <*/
ZB_FILT_TRIM_FAILED = 20, /* < */
BLE_FILT_TRIM_FAILED = 40, /* < */
};
/* \var typedef struct IFR_SW_TRIM_TBL_ENTRY_T */
/* \brief Structure defining an entry in a table used to contain values to be passed back from IFR */
/* handling routine to XCVR driver software. */
typedef struct
{
SW_TRIM_ID_T trim_id; /* < The assigned ID */
uint32_t trim_value; /* < The value fetched from IFR.*/
uint8_t valid; /* < validity of the trim_value field after IFR processing is complete (TRUE/FALSE).*/
} IFR_SW_TRIM_TBL_ENTRY_T;
/*******************************************************************************
* API
******************************************************************************/
/*!
* @brief Reads a location in block 1 IFR for use by the radio.
*
* This function handles reading IFR data from flash memory for trim loading.
*
* @param read_addr the address in the IFR to be read.
*/
uint32_t read_resource_ifr(uint32_t read_addr);
/*!
* @brief Reads a location in a simulated data array to support IFR handler testing.
*
* This function handles reading data from a const table for testing the trim loading functions.
*
* @param read_addr the address in the IFR to be read.
*/
uint32_t read_resource(uint16_t resource_id);
/*!
* @brief Main IFR handler function called by XCVR driver software to process trim table.
*
* This function handles reading data from IFR and either loading to registers or storing to a SW trim values table.
*
* @param sw_trim_tbl pointer to the table used to store software trim values.
* @param num_entries the number of entries that can be stored in the SW trim table.
*/
void handle_ifr(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries);
/*!
* @brief Handler function to read die_id from IFR locations..
*
* This function handles reading die ID value for debug and testing usage.
*
* @return the value of the die ID field.
*/
uint32_t handle_ifr_die_id(void);
/*!
* @brief Handler function to read KW chip version from IFR locations..
*
* This function handles reading KW chip version for debug and testing usage.
*
* @return the value of the KW version field.
*/
uint32_t handle_ifr_die_kw_type(void);
/*!
* @brief Debug function to dump the IFR contents to a RAM array.
*
* This function handles reading data from IFR and storing to a RAM array for debug.
*
* @param dump_tbl pointer to the table used to store IFR entry values.
* @param num_entries the number of entries that can be stored in the dump table.
*/
void dump_ifr(uint32_t * dump_tbl, uint8_t num_entries);
#endif /*__IFR_RADIO_H__ */

10
targets/targets.json
View File

@ -1357,7 +1357,7 @@
"supported_form_factors": ["ARDUINO"],
"core": "Cortex-M0+",
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
"extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
"extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM", "FRAMEWORK_5_3_3", "NXP"],
"is_disk_virtual": true,
"macros": ["CPU_MKW41Z512VHT4", "FSL_RTOS_MBED"],
"inherits": ["Target"],
@ -1381,11 +1381,15 @@
"SPISLAVE",
"TRNG",
"STDIO_MESSAGES",
"FLASH"
"FLASH",
"802_15_4_PHY"
],
"release_versions": ["2", "5"],
"device_name": "MKW41Z512xxx4",
"bootloader_supported": true
"bootloader_supported": true,
"overrides": {
"network-default-interface-type": "MESH"
}
},
"MCU_K24F1M": {
"core": "Cortex-M4F",

3
tools/test_configs/NanostackMACTester.json
View File

@ -12,8 +12,7 @@
"nanostack-hal.event_loop_thread_stack_size": 2000,
"mbed-trace.enable": true,
"nsapi.default-stack": "LWIP",
"target.device_has_add": ["802_15_4_PHY"],
"atmel-rf.provide-default": true
"target.device_has_add": ["802_15_4_PHY"]
}
}
}