mirror of https://github.com/ARMmbed/mbed-os.git
commit
5750f31d6d
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@ -45,7 +45,6 @@ I2CSlave slave(D3, D6);
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volatile int why;
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volatile bool master_complete = false;
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void cbmaster_done(int event) {
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printf("cbmaster_done\n");
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master_complete = true;
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why = event;
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}
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@ -70,7 +69,8 @@ int main()
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// First transfer: master to slave
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printf("\nFirst transfer: Master Tx, Repeated Start\n");
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master.transfer(ADDR, buf_master, SIZE, 0, 0, callback, I2C_EVENT_ALL, true);
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if(master.transfer(ADDR, buf_master, SIZE, 0, 0, callback, I2C_EVENT_ALL, true) != 0)
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notify_completion(false);
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while (!master_complete) {
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if(slave.receive() == I2CSlave::WriteAddressed) {
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@ -90,7 +90,8 @@ int main()
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// Second transfer: slave to master
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printf("\nSecond transfer: Master Rx\n");
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master.transfer(ADDR, 0, 0, res_master, SIZE, callback, I2C_EVENT_ALL, true);
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if(master.transfer(ADDR, 0, 0, res_master, SIZE, callback, I2C_EVENT_ALL, true) != 0)
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notify_completion(false);
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while (!master_complete) {
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if(slave.receive() == I2CSlave::ReadAddressed) {
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@ -118,7 +119,8 @@ int main()
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// Third transfer: Tx/Rx
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printf("\nThird transfer: Master Tx/Rx\n");
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master.transfer(ADDR, buf_master_tx, SIZE, buf_master_rx, SIZE, callback, I2C_EVENT_ALL, false);
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if(master.transfer(ADDR, buf_master_tx, SIZE, buf_master_rx, SIZE, callback, I2C_EVENT_ALL, false) != 0)
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notify_completion(false);
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while (!master_complete) {
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@ -130,6 +132,7 @@ int main()
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buf_slave_txrx[i]++;
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}
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}
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if((i == I2CSlave::ReadAddressed) ) {
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slave.write(buf_slave_txrx, SIZE);
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}
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@ -84,17 +84,29 @@ struct spi_s {
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};
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struct i2c_s {
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/* The 1st 2 members I2CName i2c
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* and I2C_HandleTypeDef handle should
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* be kept as the first members of this struct
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* to have get_i2c_obj() function work as expected
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*/
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I2CName i2c;
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I2C_HandleTypeDef handle;
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uint8_t index;
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PinName sda;
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PinName scl;
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IRQn_Type event_i2cIRQ;
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IRQn_Type error_i2cIRQ;
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uint8_t XferOperation;
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volatile uint8_t event;
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#if DEVICE_I2CSLAVE
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uint8_t slave;
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volatile uint8_t pending_slave_tx_master_rx;
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volatile uint8_t pending_slave_rx_maxter_tx;
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#endif
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#if DEVICE_I2C_ASYNCH
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uint32_t address;
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uint8_t event;
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uint8_t stop;
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uint8_t available_events;
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uint8_t XferOperation;
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#endif
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};
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@ -3960,7 +3960,8 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
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__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
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hi2c->State = HAL_I2C_STATE_READY;
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hi2c->PreviousState = I2C_STATE_NONE;
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if(hi2c->Mode == HAL_I2C_MODE_MEM)
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{
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hi2c->Mode = HAL_I2C_MODE_NONE;
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@ -29,6 +29,7 @@
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*/
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#include "mbed_assert.h"
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#include "i2c_api.h"
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#include "platform/wait_api.h"
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#if DEVICE_I2C
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@ -36,16 +37,29 @@
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#include "pinmap.h"
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#include "PeripheralPins.h"
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/* Timeout values for flags and events waiting loops. These timeouts are
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not based on accurate values, they just guarantee that the application will
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not remain stuck if the I2C communication is corrupted. */
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#define FLAG_TIMEOUT ((int)0x1000)
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#define LONG_TIMEOUT ((int)0x8000)
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#ifndef DEBUG_STDIO
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# define DEBUG_STDIO 0
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#endif
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int i2c1_inited = 0;
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int i2c2_inited = 0;
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int i2c3_inited = 0;
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int fmpi2c1_inited = 0;
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#if DEBUG_STDIO
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# include <stdio.h>
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# define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
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#else
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# define DEBUG_PRINTF(...) {}
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#endif
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/* Timeout values are based on core clock and I2C clock.
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The BYTE_TIMEOUT is computed as twice the number of cycles it would
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take to send 10 bits over I2C. Most Flags should take less than that.
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This is for immediate FLAG or ACK check.
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*/
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#define BYTE_TIMEOUT ((SystemCoreClock / handle->Init.ClockSpeed) * 2 * 10)
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/* Timeout values based on I2C clock.
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The BYTE_TIMEOUT_US is computed as 3x the time in us it would
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take to send 10 bits over I2C. Most Flags should take less than that.
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This is for complete transfers check.
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*/
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#define BYTE_TIMEOUT_US ((SystemCoreClock / handle->Init.ClockSpeed) * 3 * 10)
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#if DEVICE_I2C_ASYNCH
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#define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c))
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@ -53,6 +67,111 @@ int fmpi2c1_inited = 0;
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#define I2C_S(obj) (struct i2c_s *) (obj)
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#endif
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/* could be defined at family level */
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#define I2C_NUM (5)
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static I2C_HandleTypeDef* i2c_handles[I2C_NUM];
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static void i2c1_irq(void)
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{
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I2C_HandleTypeDef * handle = i2c_handles[0];
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HAL_I2C_EV_IRQHandler(handle);
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HAL_I2C_ER_IRQHandler(handle);
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}
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static void i2c2_irq(void)
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{
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I2C_HandleTypeDef * handle = i2c_handles[1];
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HAL_I2C_EV_IRQHandler(handle);
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HAL_I2C_ER_IRQHandler(handle);
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}
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#if defined(I2C3_BASE)
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static void i2c3_irq(void)
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{
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I2C_HandleTypeDef * handle = i2c_handles[2];
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HAL_I2C_EV_IRQHandler(handle);
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HAL_I2C_ER_IRQHandler(handle);
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}
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#endif
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#if defined(I2C4_BASE)
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static void i2c4_irq(void)
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{
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I2C_HandleTypeDef * handle = i2c_handles[3];
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HAL_I2C_EV_IRQHandler(handle);
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HAL_I2C_ER_IRQHandler(handle);
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}
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#endif
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#if defined(FMPI2C1_BASE)
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static void i2c5_irq(void)
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{
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I2C_HandleTypeDef * handle = i2c_handles[4];
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HAL_I2C_EV_IRQHandler(handle);
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HAL_I2C_ER_IRQHandler(handle);
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}
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#endif
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void i2c_ev_err_enable(i2c_t *obj, uint32_t handler) {
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struct i2c_s *obj_s = I2C_S(obj);
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IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
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IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
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/* Set up event IT using IRQ and handler tables */
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NVIC_SetVector(irq_event_n, handler);
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HAL_NVIC_SetPriority(irq_event_n, 0, 0);
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HAL_NVIC_EnableIRQ(irq_event_n);
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/* Set up error IT using IRQ and handler tables */
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NVIC_SetVector(irq_error_n, handler);
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HAL_NVIC_SetPriority(irq_error_n, 0, 1);
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HAL_NVIC_EnableIRQ(irq_error_n);
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}
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void i2c_ev_err_disable(i2c_t *obj) {
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struct i2c_s *obj_s = I2C_S(obj);
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IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
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IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
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HAL_NVIC_DisableIRQ(irq_event_n);
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HAL_NVIC_DisableIRQ(irq_error_n);
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}
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void i2c_irq_set(i2c_t *obj, uint32_t enable)
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{
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struct i2c_s *obj_s = I2C_S(obj);
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I2C_HandleTypeDef *handle = &(obj_s->handle);
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uint32_t handler = 0;
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switch (obj_s->index) {
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case 0:
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handler = (uint32_t)&i2c1_irq;
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break;
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case 1:
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handler = (uint32_t)&i2c2_irq;
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break;
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#if defined(I2C3_BASE)
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case 2:
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handler = (uint32_t)&i2c3_irq;
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break;
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#endif
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#if defined(I2C4_BASE)
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case 3:
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handler = (uint32_t)&i2c4_irq;
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break;
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#endif
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#if defined(FMPI2C1_BASE)
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case 4:
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handler = (uint32_t)&i2c5_irq;
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break;
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#endif
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}
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if (enable) {
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i2c_handles[obj_s->index] = handle;
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i2c_ev_err_enable(obj, handler);
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} else { // disable
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i2c_ev_err_disable(obj);
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i2c_handles[obj_s->index] = 0;
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}
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}
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void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
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@ -61,68 +180,75 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
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// Determine the I2C to use
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I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
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I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
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obj_s->sda = sda;
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obj_s->scl = scl;
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obj_s->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
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MBED_ASSERT(obj_s->i2c != (I2CName)NC);
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// Enable I2C1 clock and pinout if not done
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if ((obj_s->i2c == I2C_1) && !i2c1_inited) {
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i2c1_inited = 1;
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if (obj_s->i2c == I2C_1) {
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obj_s->index = 0;
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// Configure I2C pins
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pinmap_pinout(sda, PinMap_I2C_SDA);
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pinmap_pinout(scl, PinMap_I2C_SCL);
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pin_mode(sda, PullUp);
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pin_mode(scl, PullUp);
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#if DEVICE_I2C_ASYNCH
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obj_s->event_i2cIRQ = I2C1_EV_IRQn;
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obj_s->error_i2cIRQ = I2C1_ER_IRQn;
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#endif
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__I2C1_CLK_ENABLE();
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}
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// Enable I2C2 clock and pinout if not done
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if ((obj_s->i2c == I2C_2) && !i2c2_inited) {
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i2c2_inited = 1;
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if (obj_s->i2c == I2C_2) {
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obj_s->index = 1;
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// Configure I2C pins
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pinmap_pinout(sda, PinMap_I2C_SDA);
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pinmap_pinout(scl, PinMap_I2C_SCL);
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pin_mode(sda, PullUp);
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pin_mode(scl, PullUp);
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#if DEVICE_I2C_ASYNCH
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obj_s->event_i2cIRQ = I2C2_EV_IRQn;
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obj_s->error_i2cIRQ = I2C2_ER_IRQn;
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#endif
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__I2C2_CLK_ENABLE();
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}
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#if defined I2C3_BASE
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// Enable I2C3 clock and pinout if not done
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if ((obj_s->i2c == I2C_3) && !i2c3_inited) {
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i2c3_inited = 1;
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if (obj_s->i2c == I2C_3) {
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obj_s->index = 2;
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// Configure I2C pins
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pinmap_pinout(sda, PinMap_I2C_SDA);
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pinmap_pinout(scl, PinMap_I2C_SCL);
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pin_mode(sda, PullUp);
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pin_mode(scl, PullUp);
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#if DEVICE_I2C_ASYNCH
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obj_s->event_i2cIRQ = I2C3_EV_IRQn;
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obj_s->error_i2cIRQ = I2C3_ER_IRQn;
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#endif
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__I2C3_CLK_ENABLE();
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}
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#endif
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#if defined FMPI2C1_BASE
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// Enable I2C3 clock and pinout if not done
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if ((obj_s->i2c == FMPI2C_1) && !fmpi2c1_inited) {
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fmpi2c1_inited = 1;
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#if defined I2C4_BASE
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// Enable clock and pinout if not done
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if (obj_s->i2c == I2C_4) {
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obj_s->index = 3;
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// Configure I2C pins
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pinmap_pinout(sda, PinMap_I2C_SDA);
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pinmap_pinout(scl, PinMap_I2C_SCL);
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pin_mode(sda, PullUp);
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pin_mode(scl, PullUp);
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obj_s->event_i2cIRQ = I2C4_EV_IRQn;
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obj_s->error_i2cIRQ = I2C4_ER_IRQn;
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__I2C4_CLK_ENABLE();
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}
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#endif
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#if defined FMPI2C1_BASE
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// Enable clock and pinout if not done
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if (obj_s->i2c == FMPI2C_1) {
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obj_s->index = 3;
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// Configure I2C pins
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pinmap_pinout(sda, PinMap_I2C_SDA);
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pinmap_pinout(scl, PinMap_I2C_SCL);
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pin_mode(sda, PullUp);
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pin_mode(scl, PullUp);
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#if DEVICE_I2C_ASYNCH
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obj_s->event_i2cIRQ = FMPI2C1_EV_IRQn;
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obj_s->error_i2cIRQ = FMPI2C1_ER_IRQn;
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#endif
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__HAL_RCC_FMPI2C1_CLK_ENABLE();
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}
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#endif
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@ -136,12 +262,18 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
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#if DEVICE_I2CSLAVE
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// I2C master by default
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obj_s->slave = 0;
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obj_s->pending_slave_tx_master_rx = 0;
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obj_s->pending_slave_rx_maxter_tx = 0;
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#endif
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#if DEVICE_I2C_ASYNCH
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// I2C Xfer operation init
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obj_s->event = 0;
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obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
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#endif
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/* Activate default IRQ handlers for sync mode
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* which would be overwritten in async mode
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*/
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i2c_irq_set(obj, 1);
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}
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void i2c_frequency(i2c_t *obj, int hz)
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@ -154,8 +286,8 @@ void i2c_frequency(i2c_t *obj, int hz)
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MBED_ASSERT((hz > 0) && (hz <= 400000));
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// wait before init
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timeout = LONG_TIMEOUT;
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while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (timeout-- != 0));
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timeout = BYTE_TIMEOUT;
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while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
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// I2C configuration
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handle->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
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@ -168,13 +300,20 @@ void i2c_frequency(i2c_t *obj, int hz)
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handle->Init.OwnAddress2 = 0;
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HAL_I2C_Init(handle);
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#if DEVICE_I2CSLAVE
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if (obj_s->slave) {
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/* Enable Address Acknowledge */
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handle->Instance->CR1 |= I2C_CR1_ACK;
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}
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#endif
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}
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i2c_t *get_i2c_obj(I2C_HandleTypeDef *hi2c){
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/* Aim of the function is to get i2c_s pointer using hi2c pointer */
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/* Highly inspired from magical linux kernel's "container_of" */
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/* (which was not directly used since not compatible with IAR toolchain) */
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struct i2c_s *obj_s;
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i2c_t *obj;
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obj_s = (struct i2c_s *)( (char *)hi2c - offsetof(struct i2c_s,handle));
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obj = (i2c_t *)( (char *)obj_s - offsetof(i2c_t,i2c));
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return (obj);
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}
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inline int i2c_start(i2c_t *obj) {
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@ -188,7 +327,7 @@ inline int i2c_start(i2c_t *obj) {
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// Wait the STOP condition has been previously correctly sent
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// This timeout can be avoid in some specific cases by simply clearing the STOP bit
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timeout = FLAG_TIMEOUT;
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timeout = BYTE_TIMEOUT;
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while ((handle->Instance->CR1 & I2C_CR1_STOP) == I2C_CR1_STOP) {
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if ((timeout--) == 0) {
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return 1;
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@ -199,7 +338,7 @@ inline int i2c_start(i2c_t *obj) {
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handle->Instance->CR1 |= I2C_CR1_START;
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// Wait the START condition has been correctly sent
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timeout = FLAG_TIMEOUT;
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timeout = BYTE_TIMEOUT;
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while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_SB) == RESET) {
|
||||
if ((timeout--) == 0) {
|
||||
return 1;
|
||||
|
@ -220,95 +359,89 @@ inline int i2c_stop(i2c_t *obj) {
|
|||
}
|
||||
|
||||
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
|
||||
|
||||
int timeout;
|
||||
int count;
|
||||
int value;
|
||||
struct i2c_s *obj_s = I2C_S(obj);
|
||||
I2C_HandleTypeDef *handle = &(obj_s->handle);
|
||||
int count = 0, ret = 0;
|
||||
uint32_t timeout = 0;
|
||||
|
||||
i2c_start(obj);
|
||||
if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) ||
|
||||
(obj_s->XferOperation == I2C_LAST_FRAME)) {
|
||||
if (stop)
|
||||
obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
|
||||
else
|
||||
obj_s->XferOperation = I2C_FIRST_FRAME;
|
||||
} else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
|
||||
(obj_s->XferOperation == I2C_NEXT_FRAME)) {
|
||||
if (stop)
|
||||
obj_s->XferOperation = I2C_LAST_FRAME;
|
||||
else
|
||||
obj_s->XferOperation = I2C_NEXT_FRAME;
|
||||
}
|
||||
|
||||
// Wait until SB flag is set
|
||||
timeout = FLAG_TIMEOUT;
|
||||
while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_SB) == RESET) {
|
||||
timeout--;
|
||||
if (timeout == 0) {
|
||||
return -1;
|
||||
obj_s->event = 0;
|
||||
ret = HAL_I2C_Master_Sequential_Receive_IT(handle, address, (uint8_t *) data, length, obj_s->XferOperation);
|
||||
|
||||
if(ret == HAL_OK) {
|
||||
timeout = BYTE_TIMEOUT_US * length;
|
||||
/* transfer started : wait completion or timeout */
|
||||
while(!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) {
|
||||
wait_us(1);
|
||||
}
|
||||
}
|
||||
|
||||
handle->Instance->DR = __HAL_I2C_7BIT_ADD_READ(address);
|
||||
|
||||
// Wait address is acknowledged
|
||||
timeout = FLAG_TIMEOUT;
|
||||
while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) == RESET) {
|
||||
timeout--;
|
||||
if (timeout == 0) {
|
||||
return -1;
|
||||
if((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) {
|
||||
DEBUG_PRINTF(" TIMEOUT or error in i2c_read\r\n");
|
||||
/* re-init IP to try and get back in a working state */
|
||||
i2c_init(obj, obj_s->sda, obj_s->scl);
|
||||
} else {
|
||||
count = length;
|
||||
}
|
||||
}
|
||||
__HAL_I2C_CLEAR_ADDRFLAG(handle);
|
||||
|
||||
// Read all bytes except last one
|
||||
for (count = 0; count < (length - 1); count++) {
|
||||
value = i2c_byte_read(obj, 0);
|
||||
data[count] = (char)value;
|
||||
} else {
|
||||
DEBUG_PRINTF("ERROR in i2c_read\r\n");
|
||||
}
|
||||
|
||||
// If not repeated start, send stop.
|
||||
// Warning: must be done BEFORE the data is read.
|
||||
if (stop) {
|
||||
i2c_stop(obj);
|
||||
}
|
||||
|
||||
// Read the last byte
|
||||
value = i2c_byte_read(obj, 1);
|
||||
data[count] = (char)value;
|
||||
|
||||
return length;
|
||||
return count;
|
||||
}
|
||||
|
||||
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
|
||||
|
||||
int timeout;
|
||||
int count;
|
||||
struct i2c_s *obj_s = I2C_S(obj);
|
||||
I2C_HandleTypeDef *handle = &(obj_s->handle);
|
||||
int count = 0, ret = 0;
|
||||
uint32_t timeout = 0;
|
||||
|
||||
i2c_start(obj);
|
||||
|
||||
// Wait until SB flag is set
|
||||
timeout = FLAG_TIMEOUT;
|
||||
while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_SB) == RESET) {
|
||||
timeout--;
|
||||
if (timeout == 0) {
|
||||
return -1;
|
||||
}
|
||||
if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) ||
|
||||
(obj_s->XferOperation == I2C_LAST_FRAME)) {
|
||||
if (stop)
|
||||
obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
|
||||
else
|
||||
obj_s->XferOperation = I2C_FIRST_FRAME;
|
||||
} else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
|
||||
(obj_s->XferOperation == I2C_NEXT_FRAME)) {
|
||||
if (stop)
|
||||
obj_s->XferOperation = I2C_LAST_FRAME;
|
||||
else
|
||||
obj_s->XferOperation = I2C_NEXT_FRAME;
|
||||
}
|
||||
|
||||
handle->Instance->DR = __HAL_I2C_7BIT_ADD_WRITE(address);
|
||||
obj_s->event = 0;
|
||||
|
||||
// Wait address is acknowledged
|
||||
timeout = FLAG_TIMEOUT;
|
||||
while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) == RESET) {
|
||||
timeout--;
|
||||
if (timeout == 0) {
|
||||
return -1;
|
||||
ret = HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *) data, length, obj_s->XferOperation);
|
||||
|
||||
if(ret == HAL_OK) {
|
||||
timeout = BYTE_TIMEOUT_US * length;
|
||||
/* transfer started : wait completion or timeout */
|
||||
while(!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) {
|
||||
wait_us(1);
|
||||
}
|
||||
}
|
||||
__HAL_I2C_CLEAR_ADDRFLAG(handle);
|
||||
|
||||
for (count = 0; count < length; count++) {
|
||||
if (i2c_byte_write(obj, data[count]) != 1) {
|
||||
i2c_stop(obj);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
// If not repeated start, send stop.
|
||||
if (stop) {
|
||||
i2c_stop(obj);
|
||||
if((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) {
|
||||
DEBUG_PRINTF(" TIMEOUT or error in i2c_write\r\n");
|
||||
/* re-init IP to try and get back in a working state */
|
||||
i2c_init(obj, obj_s->sda, obj_s->scl);
|
||||
} else {
|
||||
count = length;
|
||||
}
|
||||
} else {
|
||||
DEBUG_PRINTF("ERROR in i2c_read\r\n");
|
||||
}
|
||||
|
||||
return count;
|
||||
|
@ -329,7 +462,7 @@ int i2c_byte_read(i2c_t *obj, int last) {
|
|||
}
|
||||
|
||||
// Wait until the byte is received
|
||||
timeout = FLAG_TIMEOUT;
|
||||
timeout = BYTE_TIMEOUT;
|
||||
while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_RXNE) == RESET) {
|
||||
if ((timeout--) == 0) {
|
||||
return -1;
|
||||
|
@ -348,7 +481,7 @@ int i2c_byte_write(i2c_t *obj, int data) {
|
|||
handle->Instance->DR = (uint8_t)data;
|
||||
|
||||
// Wait until the byte (might be the address) is transmitted
|
||||
timeout = FLAG_TIMEOUT;
|
||||
timeout = BYTE_TIMEOUT;
|
||||
while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXE) == RESET) &&
|
||||
(__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BTF) == RESET) &&
|
||||
(__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) == RESET)) {
|
||||
|
@ -374,8 +507,8 @@ void i2c_reset(i2c_t *obj) {
|
|||
handle->Instance = (I2C_TypeDef *)(obj_s->i2c);
|
||||
|
||||
// wait before reset
|
||||
timeout = LONG_TIMEOUT;
|
||||
while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (timeout-- != 0));
|
||||
timeout = BYTE_TIMEOUT;
|
||||
while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
|
||||
|
||||
if (obj_s->i2c == I2C_1) {
|
||||
__I2C1_FORCE_RESET();
|
||||
|
@ -392,7 +525,12 @@ void i2c_reset(i2c_t *obj) {
|
|||
__I2C3_RELEASE_RESET();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined I2C4_BASE
|
||||
if (obj_s->i2c == I2C_4) {
|
||||
__I2C4_FORCE_RESET();
|
||||
__I2C4_RELEASE_RESET();
|
||||
}
|
||||
#endif
|
||||
#if defined FMPI2C1_BASE
|
||||
if (obj_s->i2c == FMPI2C_1) {
|
||||
__HAL_RCC_FMPI2C1_FORCE_RESET();
|
||||
|
@ -404,31 +542,27 @@ void i2c_reset(i2c_t *obj) {
|
|||
#if DEVICE_I2CSLAVE
|
||||
|
||||
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
|
||||
|
||||
uint16_t tmpreg = 0;
|
||||
struct i2c_s *obj_s = I2C_S(obj);
|
||||
I2C_TypeDef *i2c = (I2C_TypeDef *)obj_s->i2c;
|
||||
I2C_HandleTypeDef *handle = &(obj_s->handle);
|
||||
|
||||
// Get the old register value
|
||||
tmpreg = i2c->OAR1;
|
||||
// Reset address bits
|
||||
tmpreg &= 0xFC00;
|
||||
// Set new address
|
||||
tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits
|
||||
// Store the new register value
|
||||
i2c->OAR1 = tmpreg;
|
||||
// I2C configuration
|
||||
handle->Init.OwnAddress1 = address;
|
||||
HAL_I2C_Init(handle);
|
||||
|
||||
HAL_I2C_EnableListen_IT(handle);
|
||||
}
|
||||
|
||||
void i2c_slave_mode(i2c_t *obj, int enable_slave) {
|
||||
|
||||
struct i2c_s *obj_s = I2C_S(obj);
|
||||
I2C_TypeDef *i2c = (I2C_TypeDef *)obj_s->i2c;
|
||||
I2C_HandleTypeDef *handle = &(obj_s->handle);
|
||||
|
||||
if (enable_slave) {
|
||||
obj_s->slave = 1;
|
||||
|
||||
/* Enable Address Acknowledge */
|
||||
i2c->CR1 |= I2C_CR1_ACK;
|
||||
HAL_I2C_EnableListen_IT(handle);
|
||||
} else {
|
||||
obj_s->slave = 0;
|
||||
HAL_I2C_DisableListen_IT(handle);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -438,184 +572,131 @@ void i2c_slave_mode(i2c_t *obj, int enable_slave) {
|
|||
#define WriteGeneral 2 // the master is writing to all slave
|
||||
#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
|
||||
|
||||
|
||||
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) {
|
||||
/* Get object ptr based on handler ptr */
|
||||
i2c_t *obj = get_i2c_obj(hi2c);
|
||||
struct i2c_s *obj_s = I2C_S(obj);
|
||||
|
||||
/* Transfer direction in HAL is from Master point of view */
|
||||
if(TransferDirection == I2C_DIRECTION_RECEIVE) {
|
||||
obj_s->pending_slave_tx_master_rx = 1;
|
||||
}
|
||||
|
||||
if(TransferDirection == I2C_DIRECTION_TRANSMIT) {
|
||||
obj_s->pending_slave_rx_maxter_tx = 1;
|
||||
}
|
||||
}
|
||||
|
||||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *I2cHandle){
|
||||
/* Get object ptr based on handler ptr */
|
||||
i2c_t *obj = get_i2c_obj(I2cHandle);
|
||||
struct i2c_s *obj_s = I2C_S(obj);
|
||||
obj_s->pending_slave_tx_master_rx = 0;
|
||||
}
|
||||
|
||||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *I2cHandle){
|
||||
/* Get object ptr based on handler ptr */
|
||||
i2c_t *obj = get_i2c_obj(I2cHandle);
|
||||
struct i2c_s *obj_s = I2C_S(obj);
|
||||
obj_s->pending_slave_rx_maxter_tx = 0;
|
||||
}
|
||||
|
||||
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
/* restart listening for master requests */
|
||||
HAL_I2C_EnableListen_IT(hi2c);
|
||||
}
|
||||
|
||||
int i2c_slave_receive(i2c_t *obj) {
|
||||
|
||||
struct i2c_s *obj_s = I2C_S(obj);
|
||||
I2C_HandleTypeDef *handle = &(obj_s->handle);
|
||||
|
||||
int retValue = NoData;
|
||||
|
||||
/* Reading BUSY flag before ADDR flag could clear ADDR */
|
||||
int addr = __HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR);
|
||||
if(obj_s->pending_slave_rx_maxter_tx) {
|
||||
retValue = WriteAddressed;
|
||||
}
|
||||
|
||||
if (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY) == 1) {
|
||||
if (addr == 1) {
|
||||
if (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TRA) == 1) {
|
||||
retValue = ReadAddressed;
|
||||
} else {
|
||||
retValue = WriteAddressed;
|
||||
}
|
||||
__HAL_I2C_CLEAR_ADDRFLAG(handle);
|
||||
}
|
||||
}
|
||||
if(obj_s->pending_slave_tx_master_rx) {
|
||||
retValue = ReadAddressed;
|
||||
}
|
||||
|
||||
return (retValue);
|
||||
}
|
||||
|
||||
int i2c_slave_read(i2c_t *obj, char *data, int length) {
|
||||
|
||||
struct i2c_s *obj_s = I2C_S(obj);
|
||||
I2C_HandleTypeDef *handle = &(obj_s->handle);
|
||||
int count = 0;
|
||||
int ret = 0;
|
||||
uint32_t timeout = 0;
|
||||
|
||||
uint32_t Timeout;
|
||||
int size = 0;
|
||||
/* Always use I2C_NEXT_FRAME as slave will just adapt to master requests */
|
||||
ret = HAL_I2C_Slave_Sequential_Receive_IT(handle, (uint8_t *) data, length, I2C_NEXT_FRAME);
|
||||
|
||||
while (length > 0) {
|
||||
|
||||
/* Wait until RXNE flag is set */
|
||||
// Wait until the byte is received
|
||||
Timeout = FLAG_TIMEOUT;
|
||||
while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_RXNE) == RESET) {
|
||||
Timeout--;
|
||||
if (Timeout == 0) {
|
||||
return -1;
|
||||
}
|
||||
if(ret == HAL_OK) {
|
||||
timeout = BYTE_TIMEOUT_US * length;
|
||||
while(obj_s->pending_slave_rx_maxter_tx && (--timeout != 0)) {
|
||||
wait_us(1);
|
||||
}
|
||||
|
||||
/* Read data from DR */
|
||||
(*data++) = handle->Instance->DR;
|
||||
length--;
|
||||
size++;
|
||||
|
||||
if ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BTF) == SET) && (length != 0)) {
|
||||
/* Read data from DR */
|
||||
(*data++) = handle->Instance->DR;
|
||||
length--;
|
||||
size++;
|
||||
}
|
||||
if(timeout != 0) {
|
||||
count = length;
|
||||
} else {
|
||||
DEBUG_PRINTF("TIMEOUT or error in i2c_slave_read\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* Wait until STOP flag is set */
|
||||
Timeout = FLAG_TIMEOUT;
|
||||
while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_STOPF) == RESET) {
|
||||
Timeout--;
|
||||
if (Timeout == 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear STOP flag */
|
||||
__HAL_I2C_CLEAR_STOPFLAG(handle);
|
||||
|
||||
/* Wait until BUSY flag is reset */
|
||||
Timeout = FLAG_TIMEOUT;
|
||||
while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY) == SET) {
|
||||
Timeout--;
|
||||
if (Timeout == 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
return size;
|
||||
return count;
|
||||
}
|
||||
|
||||
int i2c_slave_write(i2c_t *obj, const char *data, int length) {
|
||||
|
||||
uint32_t Timeout;
|
||||
int size = 0;
|
||||
struct i2c_s *obj_s = I2C_S(obj);
|
||||
I2C_HandleTypeDef *handle = &(obj_s->handle);
|
||||
int count = 0;
|
||||
int ret = 0;
|
||||
uint32_t timeout = 0;
|
||||
|
||||
while (length > 0) {
|
||||
/* Wait until TXE flag is set */
|
||||
Timeout = FLAG_TIMEOUT;
|
||||
while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXE) == RESET) {
|
||||
Timeout--;
|
||||
if (Timeout == 0) {
|
||||
return -1;
|
||||
}
|
||||
/* Always use I2C_NEXT_FRAME as slave will just adapt to master requests */
|
||||
ret = HAL_I2C_Slave_Sequential_Transmit_IT(handle, (uint8_t *) data, length, I2C_NEXT_FRAME);
|
||||
|
||||
if(ret == HAL_OK) {
|
||||
timeout = BYTE_TIMEOUT_US * length;
|
||||
while(obj_s->pending_slave_tx_master_rx && (--timeout != 0)) {
|
||||
wait_us(1);
|
||||
}
|
||||
|
||||
/* Write data to DR */
|
||||
handle->Instance->DR = (*data++);
|
||||
length--;
|
||||
size++;
|
||||
|
||||
if ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BTF) == SET) && (length != 0)) {
|
||||
/* Write data to DR */
|
||||
handle->Instance->DR = (*data++);
|
||||
length--;
|
||||
size++;
|
||||
}
|
||||
if(timeout != 0) {
|
||||
count = length;
|
||||
} else {
|
||||
DEBUG_PRINTF("TIMEOUT or error in i2c_slave_write\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* Wait until AF flag is set */
|
||||
Timeout = FLAG_TIMEOUT;
|
||||
while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_AF) == RESET) {
|
||||
Timeout--;
|
||||
if (Timeout == 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear AF flag */
|
||||
__HAL_I2C_CLEAR_FLAG(handle, I2C_FLAG_AF);
|
||||
|
||||
|
||||
/* Wait until BUSY flag is reset */
|
||||
Timeout = FLAG_TIMEOUT;
|
||||
while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY) == SET) {
|
||||
Timeout--;
|
||||
if (Timeout == 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
handle->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(handle);
|
||||
|
||||
return size;
|
||||
return count;
|
||||
}
|
||||
|
||||
#endif // DEVICE_I2CSLAVE
|
||||
|
||||
#if DEVICE_I2C_ASYNCH
|
||||
|
||||
|
||||
i2c_t *get_i2c_obj(I2C_HandleTypeDef *hi2c){
|
||||
|
||||
/* Aim of the function is to get i2c_s pointer using hi2c pointer */
|
||||
/* Highly inspired from magical linux kernel's "container_of" */
|
||||
/* (which was not directly used since not compatible with IAR toolchain) */
|
||||
struct i2c_s *obj_s;
|
||||
i2c_t *obj;
|
||||
|
||||
obj_s = (struct i2c_s *)( (char *)hi2c - offsetof(struct i2c_s,handle));
|
||||
obj = (i2c_t *)( (char *)obj_s - offsetof(i2c_t,i2c));
|
||||
|
||||
return (obj);
|
||||
}
|
||||
|
||||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c){
|
||||
/* Get object ptr based on handler ptr */
|
||||
i2c_t *obj = get_i2c_obj(hi2c);
|
||||
struct i2c_s *obj_s = I2C_S(obj);
|
||||
|
||||
#if DEVICE_I2C_ASYNCH
|
||||
/* Handle potential Tx/Rx use case */
|
||||
if ((obj->tx_buff.length) && (obj->rx_buff.length)) {
|
||||
|
||||
if (obj_s->stop) {
|
||||
if (obj_s->stop) {
|
||||
obj_s->XferOperation = I2C_LAST_FRAME;
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
obj_s->XferOperation = I2C_NEXT_FRAME;
|
||||
}
|
||||
|
||||
HAL_I2C_Master_Sequential_Receive_IT(hi2c, obj_s->address, (uint8_t*)obj->rx_buff.buffer , obj->rx_buff.length, obj_s->XferOperation);
|
||||
}
|
||||
else {
|
||||
else
|
||||
#endif
|
||||
{
|
||||
/* Set event flag */
|
||||
obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
|
||||
}
|
||||
|
@ -635,15 +716,17 @@ void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c){
|
|||
/* Get object ptr based on handler ptr */
|
||||
i2c_t *obj = get_i2c_obj(hi2c);
|
||||
struct i2c_s *obj_s = I2C_S(obj);
|
||||
I2C_HandleTypeDef *handle = &(obj_s->handle);
|
||||
|
||||
/* Disable IT. Not always done before calling macro */
|
||||
__HAL_I2C_DISABLE_IT(handle, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
|
||||
DEBUG_PRINTF("HAL_I2C_ErrorCallback:%d, index=%d\r\n", (int) hi2c->ErrorCode, obj_s->index);
|
||||
|
||||
/* Set event flag */
|
||||
/* re-init IP to try and get back in a working state */
|
||||
i2c_init(obj, obj_s->sda, obj_s->scl);
|
||||
|
||||
/* Keep Set event flag */
|
||||
obj_s->event = I2C_EVENT_ERROR;
|
||||
}
|
||||
|
||||
#if DEVICE_I2C_ASYNCH
|
||||
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c){
|
||||
/* Get object ptr based on handler ptr */
|
||||
i2c_t *obj = get_i2c_obj(hi2c);
|
||||
|
@ -683,18 +766,7 @@ void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx,
|
|||
obj_s->address = address;
|
||||
obj_s->stop = stop;
|
||||
|
||||
IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
|
||||
IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
|
||||
|
||||
/* Set up event IT using IRQ and handler tables */
|
||||
NVIC_SetVector(irq_event_n, handler);
|
||||
HAL_NVIC_SetPriority(irq_event_n, 0, 1);
|
||||
HAL_NVIC_EnableIRQ(irq_event_n);
|
||||
|
||||
/* Set up error IT using IRQ and handler tables */
|
||||
NVIC_SetVector(irq_error_n, handler);
|
||||
HAL_NVIC_SetPriority(irq_error_n, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(irq_error_n);
|
||||
i2c_ev_err_enable(obj, handler);
|
||||
|
||||
/* Set operation step depending if stop sending required or not */
|
||||
if ((tx_length && !rx_length) || (!tx_length && rx_length)) {
|
||||
|
|
Loading…
Reference in New Issue