mirror of https://github.com/ARMmbed/mbed-os.git
Add NUC472 eth and entropy
cyliangtw
ccli8
parent
955695679e
commit
5710178afb
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/*
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* Copyright (c) 2012-2015, ARM Limited, All Rights Reserved
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef LWIPOPTS_CONF_H
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#define LWIPOPTS_CONF_H
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#define LWIP_TRANSPORT_ETHERNET 1
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#define ETH_PAD_SIZE 2
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#define MEM_SIZE (16*1024)//(8*1024)//(16*1024)
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#endif
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/*
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* Copyright (c) 2013 Nuvoton Technology Corp.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Description: NUC472 MAC driver source file
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*/
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#include "nuc472_eth.h"
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#include "lwip/opt.h"
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#include "lwip/def.h"
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#define ETH_TRIGGER_RX() do{EMAC->RXST = 0;}while(0)
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#define ETH_TRIGGER_TX() do{EMAC->TXST = 0;}while(0)
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#define ETH_ENABLE_TX() do{EMAC->CTL |= EMAC_CTL_TXON;}while(0)
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#define ETH_ENABLE_RX() do{EMAC->CTL |= EMAC_CTL_RXON;}while(0)
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#define ETH_DISABLE_TX() do{EMAC->CTL &= ~EMAC_CTL_TXON;}while(0)
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#define ETH_DISABLE_RX() do{EMAC->CTL &= ~EMAC_CTL_RXON;}while(0)
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#ifdef __ICCARM__
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#pragma data_alignment=4
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struct eth_descriptor rx_desc[RX_DESCRIPTOR_NUM];
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struct eth_descriptor tx_desc[TX_DESCRIPTOR_NUM];
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#else
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struct eth_descriptor rx_desc[RX_DESCRIPTOR_NUM] __attribute__ ((aligned(4)));
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struct eth_descriptor tx_desc[TX_DESCRIPTOR_NUM] __attribute__ ((aligned(4)));
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#endif
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struct eth_descriptor volatile *cur_tx_desc_ptr, *cur_rx_desc_ptr, *fin_tx_desc_ptr;
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u8_t rx_buf[RX_DESCRIPTOR_NUM][PACKET_BUFFER_SIZE];
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u8_t tx_buf[TX_DESCRIPTOR_NUM][PACKET_BUFFER_SIZE];
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extern void ethernetif_input(u16_t len, u8_t *buf, u32_t s, u32_t ns);
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extern void ethernetif_loopback_input(struct pbuf *p);
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// PTP source clock is 84MHz (Real chip using PLL). Each tick is 11.90ns
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// Assume we want to set each tick to 100ns.
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// Increase register = (100 * 2^31) / (10^9) = 214.71 =~ 215 = 0xD7
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// Addend register = 2^32 * tick_freq / (84MHz), where tick_freq = (2^31 / 215) MHz
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// From above equation, addend register = 2^63 / (84M * 215) ~= 510707200 = 0x1E70C600
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static void mdio_write(u8_t addr, u8_t reg, u16_t val)
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{
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EMAC->MIIMDAT = val;
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EMAC->MIIMCTL = (addr << EMAC_MIIMCTL_PHYADDR_Pos) | reg | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_WRITE_Msk | EMAC_MIIMCTL_MDCON_Msk;
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while (EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk);
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}
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static u16_t mdio_read(u8_t addr, u8_t reg)
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{
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EMAC->MIIMCTL = (addr << EMAC_MIIMCTL_PHYADDR_Pos) | reg | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_MDCON_Msk;
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while (EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk);
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return(EMAC->MIIMDAT);
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}
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static int reset_phy(void)
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{
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u16_t reg;
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u32_t delay;
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mdio_write(CONFIG_PHY_ADDR, MII_BMCR, BMCR_RESET);
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delay = 2000;
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while(delay-- > 0) {
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if((mdio_read(CONFIG_PHY_ADDR, MII_BMCR) & BMCR_RESET) == 0)
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break;
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}
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if(delay == 0) {
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printf("Reset phy failed\n");
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return(-1);
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}
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mdio_write(CONFIG_PHY_ADDR, MII_ADVERTISE, ADVERTISE_CSMA |
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ADVERTISE_10HALF |
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ADVERTISE_10FULL |
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ADVERTISE_100HALF |
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ADVERTISE_100FULL);
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reg = mdio_read(CONFIG_PHY_ADDR, MII_BMCR);
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mdio_write(CONFIG_PHY_ADDR, MII_BMCR, reg | BMCR_ANRESTART);
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delay = 200000;
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while(delay-- > 0) {
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if((mdio_read(CONFIG_PHY_ADDR, MII_BMSR) & (BMSR_ANEGCOMPLETE | BMSR_LSTATUS))
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== (BMSR_ANEGCOMPLETE | BMSR_LSTATUS))
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break;
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}
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if(delay == 0) {
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printf("AN failed. Set to 100 FULL\n");
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EMAC->CTL |= (EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
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return(-1);
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} else {
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reg = mdio_read(CONFIG_PHY_ADDR, MII_LPA);
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if(reg & ADVERTISE_100FULL) {
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printf("100 full\n");
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EMAC->CTL |= (EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
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} else if(reg & ADVERTISE_100HALF) {
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printf("100 half\n");
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EMAC->CTL = (EMAC->CTL & ~EMAC_CTL_FUDUP_Msk) | EMAC_CTL_OPMODE_Msk;
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} else if(reg & ADVERTISE_10FULL) {
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printf("10 full\n");
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EMAC->CTL = (EMAC->CTL & ~EMAC_CTL_OPMODE_Msk) | EMAC_CTL_FUDUP_Msk;
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} else {
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printf("10 half\n");
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EMAC->CTL &= ~(EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
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}
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}
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return(0);
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}
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static void init_tx_desc(void)
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{
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u32_t i;
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cur_tx_desc_ptr = fin_tx_desc_ptr = &tx_desc[0];
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for(i = 0; i < TX_DESCRIPTOR_NUM; i++) {
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tx_desc[i].status1 = TXFD_PADEN | TXFD_CRCAPP | TXFD_INTEN;
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tx_desc[i].buf = &tx_buf[i][0];
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tx_desc[i].status2 = 0;
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tx_desc[i].next = &tx_desc[(i + 1) % TX_DESCRIPTOR_NUM];
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}
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EMAC->TXDSA = (unsigned int)&tx_desc[0];
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return;
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}
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static void init_rx_desc(void)
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{
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u32_t i;
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cur_rx_desc_ptr = &rx_desc[0];
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for(i = 0; i < RX_DESCRIPTOR_NUM; i++) {
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rx_desc[i].status1 = OWNERSHIP_EMAC;
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rx_desc[i].buf = &rx_buf[i][0];
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rx_desc[i].status2 = 0;
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rx_desc[i].next = &rx_desc[(i + 1) % TX_DESCRIPTOR_NUM];
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}
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EMAC->RXDSA = (unsigned int)&rx_desc[0];
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return;
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}
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static void set_mac_addr(u8_t *addr)
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{
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EMAC->CAM0M = (addr[0] << 24) |
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(addr[1] << 16) |
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(addr[2] << 8) |
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addr[3];
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EMAC->CAM0L = (addr[4] << 24) |
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(addr[5] << 16);
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EMAC->CAMCTL = EMAC_CAMCTL_CMPEN_Msk | EMAC_CAMCTL_AMP_Msk | EMAC_CAMCTL_ABP_Msk;
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EMAC->CAMEN = 1; // Enable CAM entry 0
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}
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static void __eth_clk_pin_init()
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{
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/* Enable IP clock */
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CLK_EnableModuleClock(EMAC_MODULE);
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// Configure MDC clock rate to HCLK / (127 + 1) = 656 kHz if system is running at 84 MHz
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CLK_SetModuleClock(EMAC_MODULE, 0, CLK_CLKDIV3_EMAC(127));
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/*---------------------------------------------------------------------------------------------------------*/
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/* Init I/O Multi-function */
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/*---------------------------------------------------------------------------------------------------------*/
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// Configure RMII pins
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SYS->GPC_MFPL |= SYS_GPC_MFPL_PC0MFP_EMAC_REFCLK |
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SYS_GPC_MFPL_PC1MFP_EMAC_MII_RXERR |
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SYS_GPC_MFPL_PC2MFP_EMAC_MII_RXDV |
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SYS_GPC_MFPL_PC3MFP_EMAC_MII_RXD1 |
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SYS_GPC_MFPL_PC4MFP_EMAC_MII_RXD0 |
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SYS_GPC_MFPL_PC6MFP_EMAC_MII_TXD0 |
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SYS_GPC_MFPL_PC7MFP_EMAC_MII_TXD1;
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SYS->GPC_MFPH |= SYS_GPC_MFPH_PC8MFP_EMAC_MII_TXEN;
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// Enable high slew rate on all RMII pins
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PC->SLEWCTL |= 0x1DF;
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// Configure MDC, MDIO at PB14 & PB15
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SYS->GPB_MFPH |= SYS_GPB_MFPH_PB14MFP_EMAC_MII_MDC | SYS_GPB_MFPH_PB15MFP_EMAC_MII_MDIO;
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}
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void ETH_init(u8_t *mac_addr)
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{
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// init CLK & pins
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__eth_clk_pin_init();
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// Reset MAC
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EMAC->CTL = EMAC_CTL_RST_Msk;
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init_tx_desc();
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init_rx_desc();
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set_mac_addr(mac_addr); // need to reconfigure hardware address 'cos we just RESET emc...
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reset_phy();
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EMAC->CTL |= EMAC_CTL_STRIPCRC_Msk | EMAC_CTL_RXON_Msk | EMAC_CTL_TXON_Msk | EMAC_CTL_RMIIEN_Msk | EMAC_CTL_RMIIRXCTL_Msk;
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EMAC->INTEN |= EMAC_INTEN_RXIEN_Msk |
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EMAC_INTEN_RXGDIEN_Msk |
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EMAC_INTEN_RDUIEN_Msk |
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EMAC_INTEN_RXBEIEN_Msk |
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EMAC_INTEN_TXIEN_Msk |
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EMAC_INTEN_TXABTIEN_Msk |
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EMAC_INTEN_TXCPIEN_Msk |
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EMAC_INTEN_TXBEIEN_Msk;
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EMAC->RXST = 0; // trigger Rx
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}
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void ETH_halt(void)
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{
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EMAC->CTL &= ~(EMAC_CTL_RXON_Msk | EMAC_CTL_TXON_Msk);
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}
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void EMAC_RX_IRQHandler(void)
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{
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unsigned int cur_entry, status;
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status = EMAC->INTSTS & 0xFFFF;
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EMAC->INTSTS = status;
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if (status & EMAC_INTSTS_RXBEIF_Msk) {
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// Shouldn't goes here, unless descriptor corrupted
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printf("RX descriptor corrupted \r\n");
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//return;
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}
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ack_emac_rx_isr();
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}
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void EMAC_RX_Action(void)
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{
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unsigned int cur_entry, status;
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do {
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cur_entry = EMAC->CRXDSA;
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if ((cur_entry == (u32_t)cur_rx_desc_ptr) && (!(status & EMAC_INTSTS_RDUIF_Msk))) // cur_entry may equal to cur_rx_desc_ptr if RDU occures
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break;
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status = cur_rx_desc_ptr->status1;
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if(status & OWNERSHIP_EMAC)
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break;
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if (status & RXFD_RXGD) {
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// Lwip will invoke osMutexWait for resource protection, so ethernetif_input can't be called in EMAC_RX_IRQHandler.
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ethernetif_input(status & 0xFFFF, cur_rx_desc_ptr->buf, cur_rx_desc_ptr->status2, (u32_t)cur_rx_desc_ptr->next);
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}
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cur_rx_desc_ptr->status1 = OWNERSHIP_EMAC;
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cur_rx_desc_ptr = cur_rx_desc_ptr->next;
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} while (1);
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ETH_TRIGGER_RX();
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// eth_arch_tcpip_thread();
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}
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void EMAC_TX_IRQHandler(void)
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{
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unsigned int cur_entry, status;
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status = EMAC->INTSTS & 0xFFFF0000;
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EMAC->INTSTS = status;
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if(status & EMAC_INTSTS_TXBEIF_Msk) {
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// Shouldn't goes here, unless descriptor corrupted
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return;
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}
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cur_entry = EMAC->CTXDSA;
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while (cur_entry != (u32_t)fin_tx_desc_ptr) {
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fin_tx_desc_ptr = fin_tx_desc_ptr->next;
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}
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}
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u8_t *ETH_get_tx_buf(void)
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{
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if(cur_tx_desc_ptr->status1 & OWNERSHIP_EMAC)
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return(NULL);
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else
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return(cur_tx_desc_ptr->buf);
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}
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void ETH_trigger_tx(u16_t length, struct pbuf *p)
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{
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struct eth_descriptor volatile *desc;
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cur_tx_desc_ptr->status2 = (unsigned int)length;
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desc = cur_tx_desc_ptr->next; // in case TX is transmitting and overwrite next pointer before we can update cur_tx_desc_ptr
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cur_tx_desc_ptr->status1 |= OWNERSHIP_EMAC;
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cur_tx_desc_ptr = desc;
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|
||||||
|
ETH_TRIGGER_TX();
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
int ETH_link_ok()
|
||||||
|
{
|
||||||
|
/* first, a dummy read to latch */
|
||||||
|
mdio_read(CONFIG_PHY_ADDR, MII_BMSR);
|
||||||
|
if(mdio_read(CONFIG_PHY_ADDR, MII_BMSR) & BMSR_LSTATUS)
|
||||||
|
return 1;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,150 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2013 Nuvoton Technology Corp.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*
|
||||||
|
* Description: NUC472 EMAC driver header file
|
||||||
|
*/
|
||||||
|
#include "lwip/def.h"
|
||||||
|
#include "lwip/pbuf.h"
|
||||||
|
#include "NUC472_442.h"
|
||||||
|
#ifndef _NUC472_ETH_
|
||||||
|
#define _NUC472_ETH_
|
||||||
|
|
||||||
|
/* Generic MII registers. */
|
||||||
|
|
||||||
|
#define MII_BMCR 0x00 /* Basic mode control register */
|
||||||
|
#define MII_BMSR 0x01 /* Basic mode status register */
|
||||||
|
#define MII_PHYSID1 0x02 /* PHYS ID 1 */
|
||||||
|
#define MII_PHYSID2 0x03 /* PHYS ID 2 */
|
||||||
|
#define MII_ADVERTISE 0x04 /* Advertisement control reg */
|
||||||
|
#define MII_LPA 0x05 /* Link partner ability reg */
|
||||||
|
#define MII_EXPANSION 0x06 /* Expansion register */
|
||||||
|
#define MII_DCOUNTER 0x12 /* Disconnect counter */
|
||||||
|
#define MII_FCSCOUNTER 0x13 /* False carrier counter */
|
||||||
|
#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
|
||||||
|
#define MII_RERRCOUNTER 0x15 /* Receive error counter */
|
||||||
|
#define MII_SREVISION 0x16 /* Silicon revision */
|
||||||
|
#define MII_RESV1 0x17 /* Reserved... */
|
||||||
|
#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
|
||||||
|
#define MII_PHYADDR 0x19 /* PHY address */
|
||||||
|
#define MII_RESV2 0x1a /* Reserved... */
|
||||||
|
#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
|
||||||
|
#define MII_NCONFIG 0x1c /* Network interface config */
|
||||||
|
|
||||||
|
/* Basic mode control register. */
|
||||||
|
#define BMCR_RESV 0x007f /* Unused... */
|
||||||
|
#define BMCR_CTST 0x0080 /* Collision test */
|
||||||
|
#define BMCR_FULLDPLX 0x0100 /* Full duplex */
|
||||||
|
#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
|
||||||
|
#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
|
||||||
|
#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
|
||||||
|
#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
|
||||||
|
#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
|
||||||
|
#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
|
||||||
|
#define BMCR_RESET 0x8000 /* Reset the DP83840 */
|
||||||
|
|
||||||
|
/* Basic mode status register. */
|
||||||
|
#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
|
||||||
|
#define BMSR_JCD 0x0002 /* Jabber detected */
|
||||||
|
#define BMSR_LSTATUS 0x0004 /* Link status */
|
||||||
|
#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
|
||||||
|
#define BMSR_RFAULT 0x0010 /* Remote fault detected */
|
||||||
|
#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
|
||||||
|
#define BMSR_RESV 0x07c0 /* Unused... */
|
||||||
|
#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
|
||||||
|
#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
|
||||||
|
#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
|
||||||
|
#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
|
||||||
|
#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
|
||||||
|
|
||||||
|
/* Advertisement control register. */
|
||||||
|
#define ADVERTISE_SLCT 0x001f /* Selector bits */
|
||||||
|
#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
|
||||||
|
#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
|
||||||
|
#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
|
||||||
|
#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
|
||||||
|
#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
|
||||||
|
#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
|
||||||
|
#define ADVERTISE_RESV 0x1c00 /* Unused... */
|
||||||
|
#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
|
||||||
|
#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
|
||||||
|
#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
|
||||||
|
|
||||||
|
#define RX_DESCRIPTOR_NUM 4 //2 // 4: Max Number of Rx Frame Descriptors
|
||||||
|
#define TX_DESCRIPTOR_NUM 4 //2 // 4: Max number of Tx Frame Descriptors
|
||||||
|
|
||||||
|
#define PACKET_BUFFER_SIZE 1520
|
||||||
|
|
||||||
|
#define CONFIG_PHY_ADDR 1
|
||||||
|
|
||||||
|
|
||||||
|
// Frame Descriptor's Owner bit
|
||||||
|
#define OWNERSHIP_EMAC 0x80000000 // 1 = EMAC
|
||||||
|
//#define OWNERSHIP_CPU 0x7fffffff // 0 = CPU
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
// Rx Frame Descriptor Status
|
||||||
|
#define RXFD_RXGD 0x00100000 // Receiving Good Packet Received
|
||||||
|
#define RXFD_RTSAS 0x00800000 // RX Time Stamp Available
|
||||||
|
|
||||||
|
|
||||||
|
// Tx Frame Descriptor's Control bits
|
||||||
|
#define TXFD_TTSEN 0x08 // Tx Time Stamp Enable
|
||||||
|
#define TXFD_INTEN 0x04 // Interrupt Enable
|
||||||
|
#define TXFD_CRCAPP 0x02 // Append CRC
|
||||||
|
#define TXFD_PADEN 0x01 // Padding Enable
|
||||||
|
|
||||||
|
// Tx Frame Descriptor Status
|
||||||
|
#define TXFD_TXCP 0x00080000 // Transmission Completion
|
||||||
|
#define TXFD_TTSAS 0x08000000 // TX Time Stamp Available
|
||||||
|
|
||||||
|
// Tx/Rx buffer descriptor structure
|
||||||
|
struct eth_descriptor;
|
||||||
|
struct eth_descriptor {
|
||||||
|
u32_t status1;
|
||||||
|
u8_t *buf;
|
||||||
|
u32_t status2;
|
||||||
|
struct eth_descriptor *next;
|
||||||
|
#ifdef TIME_STAMPING
|
||||||
|
u32_t backup1;
|
||||||
|
u32_t backup2;
|
||||||
|
u32_t reserved1;
|
||||||
|
u32_t reserved2;
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
#ifdef TIME_STAMPING
|
||||||
|
|
||||||
|
#define ETH_TS_ENABLE() do{EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk;}while(0)
|
||||||
|
#define ETH_TS_START() do{EMAC->TSCTL |= (EMAC_TSCTL_TSMODE_Msk | EMAC_TSCTL_TSIEN_Msk);}while(0)
|
||||||
|
s32_t ETH_settime(u32_t sec, u32_t nsec);
|
||||||
|
s32_t ETH_gettime(u32_t *sec, u32_t *nsec);
|
||||||
|
s32_t ETH_updatetime(u32_t neg, u32_t sec, u32_t nsec);
|
||||||
|
s32_t ETH_adjtimex(int ppm);
|
||||||
|
void ETH_setinc(void);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
extern void ETH_init(u8_t *mac_addr);
|
||||||
|
extern u8_t *ETH_get_tx_buf(void);
|
||||||
|
extern void ETH_trigger_tx(u16_t length, struct pbuf *p);
|
||||||
|
|
||||||
|
#endif /* _NUC472_ETH_ */
|
||||||
|
|
@ -0,0 +1,526 @@
|
||||||
|
/**
|
||||||
|
* @file
|
||||||
|
* Ethernet Interface Skeleton
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. The name of the author may not be used to endorse or promote products
|
||||||
|
* derived from this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||||
|
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||||
|
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||||
|
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||||
|
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||||
|
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
* OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* This file is part of the lwIP TCP/IP stack.
|
||||||
|
*
|
||||||
|
* Author: Adam Dunkels <adam@sics.se>
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This file is a skeleton for developing Ethernet network interface
|
||||||
|
* drivers for lwIP. Add code to the low_level functions and do a
|
||||||
|
* search-and-replace for the word "ethernetif" to replace it with
|
||||||
|
* something that better describes your network interface.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "lwip/opt.h"
|
||||||
|
|
||||||
|
#include "lwip/def.h"
|
||||||
|
#include "lwip/mem.h"
|
||||||
|
#include "lwip/pbuf.h"
|
||||||
|
#include "lwip/sys.h"
|
||||||
|
#include <lwip/stats.h>
|
||||||
|
#include <lwip/snmp.h>
|
||||||
|
#include "netif/etharp.h"
|
||||||
|
#include "netif/ppp_oe.h"
|
||||||
|
#include "nuc472_eth.h"
|
||||||
|
#include "string.h"
|
||||||
|
|
||||||
|
#include "eth_arch.h"
|
||||||
|
#include "sys_arch.h"
|
||||||
|
#include <ctype.h>
|
||||||
|
#include <stdio.h>
|
||||||
|
|
||||||
|
#include "mbed_interface.h"
|
||||||
|
#include "cmsis.h"
|
||||||
|
|
||||||
|
|
||||||
|
/* Define those to better describe your network interface. */
|
||||||
|
#define IFNAME0 'e'
|
||||||
|
#define IFNAME1 'n'
|
||||||
|
|
||||||
|
// Fow now, all interrupt handling happens inside one single handler, so we need to figure
|
||||||
|
// out what actually triggered the interrupt.
|
||||||
|
static volatile uint8_t emac_timer_fired;
|
||||||
|
volatile uint8_t allow_net_callbacks;
|
||||||
|
|
||||||
|
struct netif *_netif;
|
||||||
|
|
||||||
|
unsigned char my_mac_addr[6] = {0x02, 0x00, 0xac, 0x55, 0x66, 0x77};
|
||||||
|
extern u8_t my_mac_addr[6];
|
||||||
|
|
||||||
|
sys_sem_t RxReadySem; /**< RX packet ready semaphore */
|
||||||
|
|
||||||
|
static void __phy_task(void *data);
|
||||||
|
static void __packet_rx_task(void *data);
|
||||||
|
/**
|
||||||
|
* Helper struct to hold private data used to operate your ethernet interface.
|
||||||
|
* Keeping the ethernet address of the MAC in this struct is not necessary
|
||||||
|
* as it is already kept in the struct netif.
|
||||||
|
* But this is only an example, anyway...
|
||||||
|
*/
|
||||||
|
struct ethernetif {
|
||||||
|
struct eth_addr *ethaddr;
|
||||||
|
/* Add whatever per-interface state that is needed here. */
|
||||||
|
};
|
||||||
|
|
||||||
|
// Override mbed_mac_address of mbed_interface.c to provide ethernet devices with a semi-unique MAC address
|
||||||
|
void mbed_mac_address(char *mac)
|
||||||
|
{
|
||||||
|
unsigned char my_mac_addr[6] = {0x02, 0x00, 0xac, 0x55, 0x66, 0x77}; // default mac adderss
|
||||||
|
// Fetch word 0
|
||||||
|
uint32_t word0 = *(uint32_t *)0x7FFFC;
|
||||||
|
// Fetch word 1
|
||||||
|
// we only want bottom 16 bits of word1 (MAC bits 32-47)
|
||||||
|
// and bit 9 forced to 1, bit 8 forced to 0
|
||||||
|
// Locally administered MAC, reduced conflicts
|
||||||
|
// http://en.wikipedia.org/wiki/MAC_address
|
||||||
|
uint32_t word1 = *(uint32_t *)0x7FFF8;
|
||||||
|
if( word0 == 0xFFFFFFFF ) // Not burn any mac address at the last 2 words of flash
|
||||||
|
{
|
||||||
|
mac[0] = my_mac_addr[0];
|
||||||
|
mac[1] = my_mac_addr[1];
|
||||||
|
mac[2] = my_mac_addr[2];
|
||||||
|
mac[3] = my_mac_addr[3];
|
||||||
|
mac[4] = my_mac_addr[4];
|
||||||
|
mac[5] = my_mac_addr[5];
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
word1 |= 0x00000200;
|
||||||
|
word1 &= 0x0000FEFF;
|
||||||
|
|
||||||
|
mac[0] = (word1 & 0x000000ff);
|
||||||
|
mac[1] = (word1 & 0x0000ff00) >> 8;
|
||||||
|
mac[2] = (word0 & 0xff000000) >> 24;
|
||||||
|
mac[3] = (word0 & 0x00ff0000) >> 16;
|
||||||
|
mac[4] = (word0 & 0x0000ff00) >> 8;
|
||||||
|
mac[5] = (word0 & 0x000000ff);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* In this function, the hardware should be initialized.
|
||||||
|
* Called from ethernetif_init().
|
||||||
|
*
|
||||||
|
* @param netif the already initialized lwip network interface structure
|
||||||
|
* for this ethernetif
|
||||||
|
*/
|
||||||
|
static void
|
||||||
|
low_level_init(struct netif *netif)
|
||||||
|
{
|
||||||
|
|
||||||
|
/* set MAC hardware address length */
|
||||||
|
netif->hwaddr_len = ETHARP_HWADDR_LEN;
|
||||||
|
|
||||||
|
/* set MAC hardware address */
|
||||||
|
#if 1 // set MAC HW address
|
||||||
|
#if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
|
||||||
|
netif->hwaddr[0] = MBED_MAC_ADDR_0;
|
||||||
|
netif->hwaddr[1] = MBED_MAC_ADDR_1;
|
||||||
|
netif->hwaddr[2] = MBED_MAC_ADDR_2;
|
||||||
|
netif->hwaddr[3] = MBED_MAC_ADDR_3;
|
||||||
|
netif->hwaddr[4] = MBED_MAC_ADDR_4;
|
||||||
|
netif->hwaddr[5] = MBED_MAC_ADDR_5;
|
||||||
|
#else
|
||||||
|
mbed_mac_address((char *)netif->hwaddr);
|
||||||
|
#endif /* set MAC HW address */
|
||||||
|
|
||||||
|
#else
|
||||||
|
netif->hwaddr[0] = my_mac_addr[0];
|
||||||
|
netif->hwaddr[1] = my_mac_addr[1];
|
||||||
|
netif->hwaddr[2] = my_mac_addr[2];
|
||||||
|
netif->hwaddr[3] = my_mac_addr[3];
|
||||||
|
netif->hwaddr[4] = my_mac_addr[4];
|
||||||
|
netif->hwaddr[5] = my_mac_addr[5];
|
||||||
|
#endif // endif
|
||||||
|
|
||||||
|
/* maximum transfer unit */
|
||||||
|
netif->mtu = 1500;
|
||||||
|
|
||||||
|
/* device capabilities */
|
||||||
|
/* NETIF_FLAG_LINK_UP should be enabled by netif_set_link_up() */
|
||||||
|
netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET;
|
||||||
|
#ifdef LWIP_IGMP
|
||||||
|
netif->flags |= NETIF_FLAG_IGMP;
|
||||||
|
#endif
|
||||||
|
// TODO: enable clock & configure GPIO function
|
||||||
|
ETH_init(netif->hwaddr);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This function should do the actual transmission of the packet. The packet is
|
||||||
|
* contained in the pbuf that is passed to the function. This pbuf
|
||||||
|
* might be chained.
|
||||||
|
*
|
||||||
|
* @param netif the lwip network interface structure for this ethernetif
|
||||||
|
* @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
|
||||||
|
* @return ERR_OK if the packet could be sent
|
||||||
|
* an err_t value if the packet couldn't be sent
|
||||||
|
*
|
||||||
|
* @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
|
||||||
|
* strange results. You might consider waiting for space in the DMA queue
|
||||||
|
* to become availale since the stack doesn't retry to send a packet
|
||||||
|
* dropped because of memory failure (except for the TCP timers).
|
||||||
|
*/
|
||||||
|
|
||||||
|
static err_t
|
||||||
|
low_level_output(struct netif *netif, struct pbuf *p)
|
||||||
|
{
|
||||||
|
struct pbuf *q;
|
||||||
|
u8_t *buf = NULL;
|
||||||
|
u16_t len = 0;
|
||||||
|
|
||||||
|
|
||||||
|
buf = ETH_get_tx_buf();
|
||||||
|
if(buf == NULL)
|
||||||
|
return ERR_MEM;
|
||||||
|
#if ETH_PAD_SIZE
|
||||||
|
pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
for(q = p; q != NULL; q = q->next) {
|
||||||
|
memcpy((u8_t*)&buf[len], q->payload, q->len);
|
||||||
|
len = len + q->len;
|
||||||
|
}
|
||||||
|
#ifdef TIME_STAMPING
|
||||||
|
ETH_trigger_tx(len, p->flags & PBUF_FLAG_GET_TXTS ? p : NULL);
|
||||||
|
#else
|
||||||
|
ETH_trigger_tx(len, NULL);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ETH_PAD_SIZE
|
||||||
|
pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
LINK_STATS_INC(link.xmit);
|
||||||
|
|
||||||
|
return ERR_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Should allocate a pbuf and transfer the bytes of the incoming
|
||||||
|
* packet from the interface into the pbuf.
|
||||||
|
*
|
||||||
|
* @param netif the lwip network interface structure for this ethernetif
|
||||||
|
* @return a pbuf filled with the received packet (including MAC header)
|
||||||
|
* NULL on memory error
|
||||||
|
*/
|
||||||
|
static struct pbuf *
|
||||||
|
low_level_input(struct netif *netif, u16_t len, u8_t *buf)
|
||||||
|
{
|
||||||
|
struct pbuf *p, *q;
|
||||||
|
|
||||||
|
#if ETH_PAD_SIZE
|
||||||
|
len += ETH_PAD_SIZE; /* allow room for Ethernet padding */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* We allocate a pbuf chain of pbufs from the pool. */
|
||||||
|
p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
|
||||||
|
|
||||||
|
if (p != NULL) {
|
||||||
|
|
||||||
|
#if ETH_PAD_SIZE
|
||||||
|
pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
len = 0;
|
||||||
|
/* We iterate over the pbuf chain until we have read the entire
|
||||||
|
* packet into the pbuf. */
|
||||||
|
for(q = p; q != NULL; q = q->next) {
|
||||||
|
memcpy((u8_t*)q->payload, (u8_t*)&buf[len], q->len);
|
||||||
|
len = len + q->len;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if ETH_PAD_SIZE
|
||||||
|
pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
LINK_STATS_INC(link.recv);
|
||||||
|
} else {
|
||||||
|
// do nothing. drop the packet
|
||||||
|
LINK_STATS_INC(link.memerr);
|
||||||
|
LINK_STATS_INC(link.drop);
|
||||||
|
}
|
||||||
|
|
||||||
|
return p;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This function should be called when a packet is ready to be read
|
||||||
|
* from the interface. It uses the function low_level_input() that
|
||||||
|
* should handle the actual reception of bytes from the network
|
||||||
|
* interface. Then the type of the received packet is determined and
|
||||||
|
* the appropriate input function is called.
|
||||||
|
*
|
||||||
|
* @param netif the lwip network interface structure for this ethernetif
|
||||||
|
*/
|
||||||
|
void
|
||||||
|
ethernetif_input(u16_t len, u8_t *buf, u32_t s, u32_t ns)
|
||||||
|
{
|
||||||
|
struct eth_hdr *ethhdr;
|
||||||
|
struct pbuf *p;
|
||||||
|
|
||||||
|
|
||||||
|
/* move received packet into a new pbuf */
|
||||||
|
p = low_level_input(_netif, len, buf);
|
||||||
|
/* no packet could be read, silently ignore this */
|
||||||
|
if (p == NULL) return;
|
||||||
|
#ifdef TIME_STAMPING
|
||||||
|
p->ts_sec = s;
|
||||||
|
p->ts_nsec = ns;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* points to packet payload, which starts with an Ethernet header */
|
||||||
|
ethhdr = p->payload;
|
||||||
|
|
||||||
|
switch (htons(ethhdr->type)) {
|
||||||
|
/* IP or ARP packet? */
|
||||||
|
case ETHTYPE_IP:
|
||||||
|
case ETHTYPE_ARP:
|
||||||
|
#if PPPOE_SUPPORT
|
||||||
|
/* PPPoE packet? */
|
||||||
|
case ETHTYPE_PPPOEDISC:
|
||||||
|
case ETHTYPE_PPPOE:
|
||||||
|
#endif /* PPPOE_SUPPORT */
|
||||||
|
/* full packet send to tcpip_thread to process */
|
||||||
|
if (_netif->input(p, _netif)!=ERR_OK) {
|
||||||
|
LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n"));
|
||||||
|
pbuf_free(p);
|
||||||
|
p = NULL;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
pbuf_free(p);
|
||||||
|
p = NULL;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef TIME_STAMPING
|
||||||
|
void
|
||||||
|
ethernetif_loopback_input(struct pbuf *p) // TODO: make sure packet not drop in input()
|
||||||
|
{
|
||||||
|
struct eth_hdr *ethhdr;
|
||||||
|
|
||||||
|
/* points to packet payload, which starts with an Ethernet header */
|
||||||
|
ethhdr = p->payload;
|
||||||
|
|
||||||
|
switch (htons(ethhdr->type)) {
|
||||||
|
/* IP or ARP packet? */
|
||||||
|
case ETHTYPE_IP:
|
||||||
|
case ETHTYPE_ARP:
|
||||||
|
#if PPPOE_SUPPORT
|
||||||
|
/* PPPoE packet? */
|
||||||
|
case ETHTYPE_PPPOEDISC:
|
||||||
|
case ETHTYPE_PPPOE:
|
||||||
|
#endif /* PPPOE_SUPPORT */
|
||||||
|
/* full packet send to tcpip_thread to process */
|
||||||
|
if (_netif->input(p, _netif)!=ERR_OK) {
|
||||||
|
LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n"));
|
||||||
|
pbuf_free(p);
|
||||||
|
p = NULL;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
pbuf_free(p);
|
||||||
|
p = NULL;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Should be called at the beginning of the program to set up the
|
||||||
|
* network interface. It calls the function low_level_init() to do the
|
||||||
|
* actual setup of the hardware.
|
||||||
|
*
|
||||||
|
* This function should be passed as a parameter to netif_add().
|
||||||
|
*
|
||||||
|
* @param netif the lwip network interface structure for this ethernetif
|
||||||
|
* @return ERR_OK if the loopif is initialized
|
||||||
|
* ERR_MEM if private data couldn't be allocated
|
||||||
|
* any other err_t on error
|
||||||
|
*/
|
||||||
|
err_t
|
||||||
|
eth_arch_enetif_init(struct netif *netif)
|
||||||
|
{
|
||||||
|
err_t err;
|
||||||
|
struct ethernetif *ethernetif;
|
||||||
|
|
||||||
|
LWIP_ASSERT("netif != NULL", (netif != NULL));
|
||||||
|
|
||||||
|
_netif = netif;
|
||||||
|
ethernetif = mem_malloc(sizeof(struct ethernetif));
|
||||||
|
if (ethernetif == NULL) {
|
||||||
|
LWIP_DEBUGF(NETIF_DEBUG, (" eth_arch_enetif_init: out of memory\n"));
|
||||||
|
return ERR_MEM;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Chris: The initialization code uses osDelay, so timers neet to run
|
||||||
|
// SysTick_Init();
|
||||||
|
|
||||||
|
#if LWIP_NETIF_HOSTNAME
|
||||||
|
/* Initialize interface hostname */
|
||||||
|
netif->hostname = "nuc472";
|
||||||
|
#endif /* LWIP_NETIF_HOSTNAME */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Initialize the snmp variables and counters inside the struct netif.
|
||||||
|
* The last argument should be replaced with your link speed, in units
|
||||||
|
* of bits per second.
|
||||||
|
*/
|
||||||
|
NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, LINK_SPEED_OF_YOUR_NETIF_IN_BPS);
|
||||||
|
|
||||||
|
netif->state = ethernetif;
|
||||||
|
netif->name[0] = IFNAME0;
|
||||||
|
netif->name[1] = IFNAME1;
|
||||||
|
/* We directly use etharp_output() here to save a function call.
|
||||||
|
* You can instead declare your own function an call etharp_output()
|
||||||
|
* from it if you have to do some checks before sending (e.g. if link
|
||||||
|
* is available...) */
|
||||||
|
netif->output = etharp_output;
|
||||||
|
netif->linkoutput = low_level_output;
|
||||||
|
|
||||||
|
ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]);
|
||||||
|
|
||||||
|
/* initialize the hardware */
|
||||||
|
low_level_init(netif);
|
||||||
|
|
||||||
|
/* Packet receive task */
|
||||||
|
|
||||||
|
err = sys_sem_new(&RxReadySem, 0);
|
||||||
|
LWIP_ASSERT("RxReadySem creation error", (err == ERR_OK));
|
||||||
|
// In GCC code, DEFAULT_THREAD_STACKSIZE 512 bytes is not enough for rx_task
|
||||||
|
#if defined (__GNUC__)
|
||||||
|
// mbed OS 2.0, DEFAULT_THREAD_STACKSIZE*3
|
||||||
|
// mbed OS 5.0, DEFAULT_THREAD_STACKSIZE*5
|
||||||
|
sys_thread_new("receive_thread", __packet_rx_task, &RxReadySem, DEFAULT_THREAD_STACKSIZE*5, osPriorityNormal);
|
||||||
|
#else
|
||||||
|
sys_thread_new("receive_thread", __packet_rx_task, &RxReadySem, DEFAULT_THREAD_STACKSIZE, osPriorityNormal);
|
||||||
|
#endif
|
||||||
|
/* PHY monitoring task */
|
||||||
|
#if defined (__GNUC__)
|
||||||
|
// mbed OS 2.0, DEFAULT_THREAD_STACKSIZE
|
||||||
|
// mbed OS 5.0, DEFAULT_THREAD_STACKSIZE*2
|
||||||
|
sys_thread_new("phy_thread", __phy_task, netif, DEFAULT_THREAD_STACKSIZE*2, osPriorityNormal);
|
||||||
|
#else
|
||||||
|
sys_thread_new("phy_thread", __phy_task, netif, DEFAULT_THREAD_STACKSIZE, osPriorityNormal);
|
||||||
|
#endif
|
||||||
|
/* Allow the PHY task to detect the initial link state and set up the proper flags */
|
||||||
|
osDelay(10);
|
||||||
|
|
||||||
|
return ERR_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
void eth_arch_enable_interrupts(void) {
|
||||||
|
// enet_hal_config_interrupt(BOARD_DEBUG_ENET_INSTANCE_ADDR, (kEnetTxFrameInterrupt | kEnetRxFrameInterrupt), true);
|
||||||
|
EMAC->INTEN |= EMAC_INTEN_RXIEN_Msk |
|
||||||
|
EMAC_INTEN_TXIEN_Msk ;
|
||||||
|
NVIC_EnableIRQ(EMAC_RX_IRQn);
|
||||||
|
NVIC_EnableIRQ(EMAC_TX_IRQn);
|
||||||
|
}
|
||||||
|
|
||||||
|
void eth_arch_disable_interrupts(void) {
|
||||||
|
NVIC_DisableIRQ(EMAC_RX_IRQn);
|
||||||
|
NVIC_DisableIRQ(EMAC_TX_IRQn);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/* Defines the PHY link speed */
|
||||||
|
typedef enum _phy_speed
|
||||||
|
{
|
||||||
|
kPHY_Speed10M = 0U, /* ENET PHY 10M speed. */
|
||||||
|
kPHY_Speed100M /* ENET PHY 100M speed. */
|
||||||
|
} phy_speed_t;
|
||||||
|
|
||||||
|
/* Defines the PHY link duplex. */
|
||||||
|
typedef enum _phy_duplex
|
||||||
|
{
|
||||||
|
kPHY_HalfDuplex = 0U, /* ENET PHY half duplex. */
|
||||||
|
kPHY_FullDuplex /* ENET PHY full duplex. */
|
||||||
|
} phy_duplex_t;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
int connected;
|
||||||
|
phy_speed_t speed;
|
||||||
|
phy_duplex_t duplex;
|
||||||
|
} PHY_STATE;
|
||||||
|
|
||||||
|
#define STATE_UNKNOWN (-1)
|
||||||
|
|
||||||
|
static void __phy_task(void *data) {
|
||||||
|
struct netif *netif = (struct netif*)data;
|
||||||
|
PHY_STATE crt_state = {STATE_UNKNOWN, (phy_speed_t)STATE_UNKNOWN, (phy_duplex_t)STATE_UNKNOWN};
|
||||||
|
PHY_STATE prev_state;
|
||||||
|
|
||||||
|
prev_state = crt_state;
|
||||||
|
while (1) {
|
||||||
|
// Get current status
|
||||||
|
// Get the actual PHY link speed
|
||||||
|
// Compare with previous state
|
||||||
|
|
||||||
|
if( !(ETH_link_ok()) && (netif->flags & NETIF_FLAG_LINK_UP) ) {
|
||||||
|
//tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_down, (void*) netif, 1);
|
||||||
|
netif_set_link_down(netif);
|
||||||
|
printf("Link Down\r\n");
|
||||||
|
}else if ( ETH_link_ok() && !(netif->flags & NETIF_FLAG_LINK_UP) ) {
|
||||||
|
//tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_up, (void*) netif, 1);
|
||||||
|
netif_set_link_up(netif);
|
||||||
|
printf("Link Up\r\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
// printf("-");
|
||||||
|
osDelay(200);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void ack_emac_rx_isr()
|
||||||
|
{
|
||||||
|
sys_sem_signal(&RxReadySem);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __packet_rx_task(void *data) {
|
||||||
|
|
||||||
|
while (1) {
|
||||||
|
/* Wait for receive task to wakeup */
|
||||||
|
sys_arch_sem_wait(&RxReadySem, 0);
|
||||||
|
EMAC_RX_Action();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,69 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2013 Nuvoton Technology Corp.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*
|
||||||
|
* Description: EMAC driver header file
|
||||||
|
*/
|
||||||
|
#ifndef __ETHERNETIF_H__
|
||||||
|
#define __ETHERNETIF_H__
|
||||||
|
|
||||||
|
|
||||||
|
#include "lwip/err.h"
|
||||||
|
#include "lwip/netif.h"
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//extern sys_sem_t tx_sem;
|
||||||
|
extern sys_sem_t rx_sem;
|
||||||
|
|
||||||
|
//err_t ethernetif_init(struct netif *netif);
|
||||||
|
//err_t ethernetif_input(struct netif *netif);
|
||||||
|
//struct netif *ethernetif_register(void);
|
||||||
|
//int ethernetif_poll(void);
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef SERVER
|
||||||
|
|
||||||
|
#define MAC_ADDR0 0x00
|
||||||
|
#define MAC_ADDR1 0x00
|
||||||
|
#define MAC_ADDR2 0x00
|
||||||
|
#define MAC_ADDR3 0x00
|
||||||
|
#define MAC_ADDR4 0x00
|
||||||
|
#define MAC_ADDR5 0x01
|
||||||
|
|
||||||
|
#else
|
||||||
|
|
||||||
|
#define MAC_ADDR0 0x00
|
||||||
|
#define MAC_ADDR1 0x00
|
||||||
|
#define MAC_ADDR2 0x00
|
||||||
|
#define MAC_ADDR3 0x00
|
||||||
|
#define MAC_ADDR4 0x00
|
||||||
|
//#define MAC_ADDR5 0x02
|
||||||
|
#define MAC_ADDR5 0x03
|
||||||
|
//#define MAC_ADDR5 0x04
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -1956,6 +1956,7 @@
|
||||||
"core": "Cortex-M4F",
|
"core": "Cortex-M4F",
|
||||||
"default_toolchain": "ARM",
|
"default_toolchain": "ARM",
|
||||||
"extra_labels": ["NUVOTON", "NUC472", "NUMAKER_PFM_NUC472"],
|
"extra_labels": ["NUVOTON", "NUC472", "NUMAKER_PFM_NUC472"],
|
||||||
|
"macros": ["MBEDTLS_ENTROPY_HARDWARE_ALT"],
|
||||||
"is_disk_virtual": true,
|
"is_disk_virtual": true,
|
||||||
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
|
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
|
||||||
"inherits": ["Target"],
|
"inherits": ["Target"],
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,114 @@
|
||||||
|
/*
|
||||||
|
* Hardware entropy collector for NUC472's RNGA
|
||||||
|
*
|
||||||
|
* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#include <stdlib.h>
|
||||||
|
#include "cmsis.h"
|
||||||
|
#include "NUC472_442.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Get Random number generator.
|
||||||
|
*/
|
||||||
|
static volatile int g_PRNG_done;
|
||||||
|
|
||||||
|
void CRYPTO_IRQHandler()
|
||||||
|
{
|
||||||
|
if (PRNG_GET_INT_FLAG()) {
|
||||||
|
g_PRNG_done = 1;
|
||||||
|
PRNG_CLR_INT_FLAG();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void rng_get( int32_t *p32ConversionData)
|
||||||
|
{
|
||||||
|
int32_t i32ConversionData;
|
||||||
|
uint32_t au32PrngData[8];
|
||||||
|
/* Unlock protected registers */
|
||||||
|
SYS_UnlockReg();
|
||||||
|
/* Enable IP clock */
|
||||||
|
CLK_EnableModuleClock(CRPT_MODULE);
|
||||||
|
|
||||||
|
/* Lock protected registers */
|
||||||
|
SYS_LockReg();
|
||||||
|
|
||||||
|
NVIC_EnableIRQ(CRPT_IRQn);
|
||||||
|
PRNG_ENABLE_INT();
|
||||||
|
|
||||||
|
// PRNG_Open(PRNG_KEY_SIZE_64, 0, 0);
|
||||||
|
PRNG_Open(PRNG_KEY_SIZE_256, 0, 0);
|
||||||
|
|
||||||
|
PRNG_Start();
|
||||||
|
while (!g_PRNG_done);
|
||||||
|
|
||||||
|
|
||||||
|
PRNG_Read(p32ConversionData);
|
||||||
|
|
||||||
|
// printf(" 0x%08x 0x%08x 0x%08x 0x%08x\n\r", *p32ConversionData, *(p32ConversionData+1), *(p32ConversionData+2), *(p32ConversionData+3));
|
||||||
|
// printf(" 0x%08x 0x%08x 0x%08x 0x%08x\n\r", *(p32ConversionData+4), *(p32ConversionData+5), *(p32ConversionData+6), *(p32ConversionData+7));
|
||||||
|
|
||||||
|
PRNG_DISABLE_INT();
|
||||||
|
NVIC_DisableIRQ(CRPT_IRQn);
|
||||||
|
CLK_DisableModuleClock(CRPT_MODULE);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Get len bytes of entropy from the hardware RNG.
|
||||||
|
*/
|
||||||
|
|
||||||
|
int mbedtls_hardware_poll( void *data,
|
||||||
|
unsigned char *output, size_t len, size_t *olen )
|
||||||
|
{
|
||||||
|
#if 0
|
||||||
|
unsigned long timer = us_ticker_read();
|
||||||
|
((void) data);
|
||||||
|
*olen = 0;
|
||||||
|
|
||||||
|
if( len < sizeof(unsigned long) )
|
||||||
|
return( 0 );
|
||||||
|
|
||||||
|
memcpy( output, &timer, sizeof(unsigned long) );
|
||||||
|
*olen = sizeof(unsigned long);
|
||||||
|
#else
|
||||||
|
*olen = 0;
|
||||||
|
if( len < 32 )
|
||||||
|
{
|
||||||
|
unsigned char tmpBuff[32];
|
||||||
|
rng_get(tmpBuff);
|
||||||
|
memcpy( output, &tmpBuff, len );
|
||||||
|
*olen = len;
|
||||||
|
return( 0 );
|
||||||
|
}
|
||||||
|
for( int i = 0; i < (len/32) ; i++)
|
||||||
|
{
|
||||||
|
rng_get(output);
|
||||||
|
*olen += 32;
|
||||||
|
// printf("Output result of len[%d][%d]: 0x%08x 0x%08x\n\r", len, *olen, *((int32_t *)output), *(((int32_t *)output)+1));
|
||||||
|
output += 32;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return( 0 );
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Loading…
Reference in New Issue