ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #13929 from JeanMarcR/DEEP_SLEEP 

STM32: LPUART clock source selection up to a serial driver
pull/14001/head
Martin Kojtal 2020-12-03 08:47:01 +00:00 committed by GitHub
parent e77b1d8a17 41ed9239be
commit 56f731027e
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 3 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/system_clock.c
View File

@ -154,13 +154,6 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
}
#endif /* DEVICE_USBDEVICE */
/* Select HSI as clock source for LPUART1 */
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
return 0; // FAIL
}
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 2
if (bypass == 0) {
@ -224,13 +217,6 @@ uint8_t SetSysClock_PLL_HSI(void)
}
#endif /* DEVICE_USBDEVICE */
/* Select HSI as clock source for LPUART1 */
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
return 0; // FAIL
}
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 3
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
@ -303,13 +289,6 @@ uint8_t SetSysClock_PLL_MSI(void)
return 0; // FAIL
}
/* Select LSE as clock source for LPUART1 */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
return 0; // FAIL
}
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 4
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz

10
targets/TARGET_STM/TARGET_STM32L5/system_clock.c
View File

@ -176,16 +176,12 @@ uint8_t SetSysClock_PLL_MSI(void)
return 0; // FAIL
}
// Default STDIO is LPUART1
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
#if DEVICE_TRNG
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_RNG;
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG;
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
#else
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
#endif
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
#endif
return 1; // OK
}